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c026408fae
Manually rebased: bcm27xx/patches-5.15/950-0600-xhci-quirks-add-link-TRB-quirk-for-VL805.patch bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch bcm27xx/patches-5.15/950-0717-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch lantiq/patches-5.15/0028-NET-lantiq-various-etop-fixes.patch All other patches automatically rebased Co-authored-by: John Audia <therealgraysky@proton.me> Signed-off-by: John Audia <therealgraysky@proton.me>
31 lines
1.1 KiB
Diff
31 lines
1.1 KiB
Diff
From 1a33a943c643b43033af936f297898b540361c62 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 1 Jan 2022 19:11:55 +0100
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Subject: [PATCH] clk: qcom: ipq8074: disable USB GDSC-s SW_COLLAPSE
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Like in IPQ6018 Qualcomm intentionally disables the SW_COLLAPSE on the USB
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GDSC-s.
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This could potentially be better handled by utilizing the GDSC driver, but
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I am not familiar with it nor do I have datasheets.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -4842,6 +4842,11 @@ static int gcc_ipq8074_probe(struct plat
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/* SW Workaround for UBI32 Huayra PLL */
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regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
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+ /* Disable SW_COLLAPSE for USB0 GDSCR */
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+ regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
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+ /* Disable SW_COLLAPSE for USB1 GDSCR */
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+ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
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+
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clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
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clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
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&nss_crypto_pll_config);
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