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1e368cb085
lede/target/linux/ipq60xx/patches-5.10/999-add-ipq6018-dts.patch
Boos4721 1e368cb085
kernel: bump 5.10 to 5.10.84 (#8411) 
Signed-off-by: boos4721 <3.1415926535boos@gmail.com>
2021-12-10 23:47:33 +08:00

1318 lines
34 KiB
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -9,6 +9,10 @@
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "ipq6018-memory.dtsi"
+
/ {
#address-cells = <2>;
@@ -27,6 +31,24 @@
clock-frequency = <24000000>;
#clock-cells = <0>;
};
+
+ bias_pll_cc_clk: bias-pll-cc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <300000000>;
+ #clock-cells = <0>;
+ };
+
+ bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <416500000>;
+ #clock-cells = <0>;
+ };
+
+ usb3phy_0_cc_pipe_clk: usb3phy-0-cc-pipe-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ #clock-cells = <0>;
+ };
};
cpus: cpus {
@@ -41,7 +63,6 @@
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
};
@@ -53,7 +74,6 @@
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
};
@@ -65,7 +85,6 @@
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
};
@@ -77,7 +96,6 @@
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
};
@@ -87,42 +105,6 @@
};
};
- cpu_opp_table: cpu_opp_table {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-864000000 {
- opp-hz = /bits/ 64 <864000000>;
- opp-microvolt = <725000>;
- clock-latency-ns = <200000>;
- };
- opp-1056000000 {
- opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <787500>;
- clock-latency-ns = <200000>;
- };
- opp-1320000000 {
- opp-hz = /bits/ 64 <1320000000>;
- opp-microvolt = <862500>;
- clock-latency-ns = <200000>;
- };
- opp-1440000000 {
- opp-hz = /bits/ 64 <1440000000>;
- opp-microvolt = <925000>;
- clock-latency-ns = <200000>;
- };
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <987500>;
- clock-latency-ns = <200000>;
- };
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1062500>;
- clock-latency-ns = <200000>;
- };
- };
-
firmware {
scm {
compatible = "qcom,scm";
@@ -146,32 +128,6 @@
method = "smc";
};
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rpm_msg_ram: memory@60000 {
- reg = <0x0 0x60000 0x0 0x6000>;
- no-map;
- };
-
- tz: memory@4a600000 {
- reg = <0x0 0x4a600000 0x0 0x00400000>;
- no-map;
- };
-
- smem_region: memory@4aa00000 {
- reg = <0x0 0x4aa00000 0x0 0x00100000>;
- no-map;
- };
-
- q6_region: memory@4ab00000 {
- reg = <0x0 0x4ab00000 0x0 0x05500000>;
- no-map;
- };
- };
-
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
@@ -221,7 +177,7 @@
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 80>;
+ gpio-ranges = <&tlmm 0 0 80>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -231,13 +187,32 @@
drive-strength = <8>;
bias-pull-down;
};
+
+ qpic_pins: qpic-pins {
+ pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio17";
+ function = "qpic_pad";
+ drive-strength = <8>;
+ bias-disable;
+ };
};
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq6018";
reg = <0x0 0x01800000 0x0 0x80000>;
- clocks = <&xo>, <&sleep_clk>;
- clock-names = "xo", "sleep_clk";
+ clocks = <&xo>,
+ <&sleep_clk>,
+ <&bias_pll_cc_clk>,
+ <&bias_pll_nss_noc_clk>,
+ <&usb3phy_0_cc_pipe_clk>;
+ clock-names = "xo",
+ "sleep_clk",
+ "bias_pll_cc_clk",
+ "bias_pll_nss_noc_clk",
+ "usb3phy_0_cc_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -302,6 +277,294 @@
status = "disabled";
};
+ qpic_bam: dma@7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x0 0x07984000 0x0 0x1a000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "iface_clk", "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ qpic_nand: nand@79b0000 {
+ compatible = "qcom,ipq6018-nand";
+ reg = <0x0 0x079b0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ pinctrl-0 = <&qpic_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ sd_pwrseq: sd-pwrseq {
+ compatible = "mmc-pwrseq-ipq";
+ reset-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+ };
+
+ sdcc1_ice: sdcc1ice@7808000 {
+ compatible = "qcom,ice";
+ reg = <0x0 0x7808000 0x0 0x2000>;
+ interrupts = <0 312 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,vectors-KBps =
+ <78 512 0 0>, /* No vote */
+ <78 512 1000 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN", "MAX";
+ qcom,instance-type = "sdcc";
+ };
+
+ sdhc_1: sdhci@7804000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x0 0x7804000 0x0 0x1000>, <0x0 0x7805000 0x0 0x1000>;
+ reg-names = "hc_mem", "cmdq_mem";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ sdhc-msm-crypto = <&sdcc1_ice>;
+ clocks = <&xo>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "xo", "iface", "core", "ice_core_clk";
+ qcom,ice-clk-rates = <160000000 308570000>;
+ max-frequency = <192000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ bus-width = <8>;
+ non-removable;
+
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci_sd@780400 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x0 0x7804000 0x0 0x1000>;
+ reg-names = "hc_mem";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&xo>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>;
+ clock-names = "xo", "iface", "core";
+ max-frequency = <192000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ bus-width = <4>;
+ vqmmc-supply = <&ipq6018_l2>;
+ mmc-pwrseq = <&sd_pwrseq>;
+ status = "disabled";
+ };
+
+ edma@3ab00000 {
+ compatible = "qcom,edma";
+ reg = <0x3ab00000 0xabe00>;
+ reg-names = "edma-reg-base";
+ qcom,txdesc-ring-start = <23>;
+ qcom,txdesc-rings = <1>;
+ qcom,txcmpl-ring-start = <23>;
+ qcom,txcmpl-rings = <1>;
+ qcom,rxfill-ring-start = <7>;
+ qcom,rxfill-rings = <1>;
+ qcom,rxdesc-ring-start = <15>;
+ qcom,rxdesc-rings = <1>;
+ interrupts = <0 378 4>,
+ <0 354 4>,
+ <0 346 4>,
+ <0 379 4>;
+ resets = <&gcc GCC_EDMA_HW_RESET>;
+ reset-names = "edma_rst";
+ };
+
+ nss-common {
+ compatible = "qcom,nss-common";
+ reg = <0x01868010 0x1000>, <0x40000000 0x1000>;
+ reg-names = "nss-misc-reset", "nss-misc-reset-flag";
+ };
+
+ nss0: nss@40000000 {
+ compatible = "qcom,nss";
+ interrupts = <0 402 0x1>, <0 401 0x1>, <0 400 0x1>,
+ <0 399 0x1>, <0 398 0x1>, <0 397 0x1>,
+ <0 396 0x1>, <0 395 0x1>, <0 394 0x1>,
+ <0 393 0x1>;
+ reg = <0x39000000 0x1000>, <0x0b111000 0x1000>;
+ reg-names = "nphys", "qgic-phys";
+ clocks = <&gcc GCC_NSS_NOC_CLK>,
+ <&gcc GCC_NSS_PTP_REF_CLK>,
+ <&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>,
+ <&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
+ <&gcc GCC_MEM_NOC_UBI32_CLK>,
+ <&gcc GCC_NSS_CE_AXI_CLK>,
+ <&gcc GCC_NSS_CE_APB_CLK>,
+ <&gcc GCC_NSSNOC_CE_AXI_CLK>,
+ <&gcc GCC_NSSNOC_CE_APB_CLK>,
+ <&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
+ <&gcc GCC_UBI0_CORE_CLK>,
+ <&gcc GCC_UBI0_AHB_CLK>,
+ <&gcc GCC_UBI0_AXI_CLK>,
+ <&gcc GCC_UBI0_NC_AXI_CLK>,
+ <&gcc GCC_UBI0_UTCM_CLK>,
+ <&gcc GCC_SNOC_NSSNOC_CLK>;
+ clock-names = "nss-noc-clk", "nss-ptp-ref-clk",
+ "nss-csr-clk", "nss-cfg-clk",
+ "nss-nssnoc-qosgen-ref-clk",
+ "nss-nssnoc-snoc-clk",
+ "nss-nssnoc-timeout-ref-clk",
+ "nss-mem-noc-ubi32-clk",
+ "nss-ce-axi-clk", "nss-ce-apb-clk",
+ "nss-nssnoc-ce-axi-clk",
+ "nss-nssnoc-ce-apb-clk",
+ "nss-nssnoc-ahb-clk",
+ "nss-core-clk", "nss-ahb-clk",
+ "nss-axi-clk", "nss-nc-axi-clk",
+ "nss-utcm-clk", "nss-snoc-nssnoc-clk";
+ qcom,id = <0>;
+ qcom,num-queue = <4>;
+ qcom,num-irq = <10>;
+ qcom,num-pri = <4>;
+ qcom,load-addr = <0x40000000>;
+ qcom,low-frequency = <187200000>;
+ qcom,mid-frequency = <748800000>;
+ qcom,max-frequency = <1497600000>;
+ qcom,bridge-enabled;
+ qcom,ipv4-enabled;
+ qcom,ipv4-reasm-enabled;
+ qcom,ipv6-enabled;
+ qcom,ipv6-reasm-enabled;
+ qcom,wlanredirect-enabled;
+ qcom,tun6rd-enabled;
+ qcom,l2tpv2-enabled;
+ qcom,gre-enabled;
+ qcom,gre-redir-enabled;
+ qcom,gre-redir-mark-enabled;
+ qcom,map-t-enabled;
+ qcom,portid-enabled;
+ qcom,ppe-enabled;
+ qcom,pppoe-enabled;
+ qcom,pptp-enabled;
+ qcom,tunipip6-enabled;
+ qcom,shaping-enabled;
+ qcom,wlan-dataplane-offload-enabled;
+ qcom,vlan-enabled;
+ qcom,capwap-enabled;
+ qcom,dtls-enabled;
+ qcom,tls-enabled;
+ qcom,crypto-enabled;
+ qcom,ipsec-enabled;
+ qcom,qvpn-enabled;
+ qcom,pvxlan-enabled;
+ qcom,clmap-enabled;
+ qcom,vxlan-enabled;
+ qcom,match-enabled;
+ qcom,mirror-enabled;
+ };
+
+ nss_crypto: qcom,nss_crypto {
+ compatible = "qcom,nss-crypto";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,max-contexts = <64>;
+ qcom,max-context-size = <32>;
+ ranges;
+
+ eip197_node {
+ compatible = "qcom,eip197";
+ reg-names = "crypto_pbase";
+ reg = <0x39800000 0x7ffff>;
+ clocks = <&gcc GCC_NSS_CRYPTO_CLK>,
+ <&gcc GCC_NSSNOC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_PPE_CLK>;
+ clock-names = "crypto_clk", "crypto_nocclk",
+ "crypto_ppeclk";
+ clock-frequency = /bits/ 64 <300000000 300000000 300000000>;
+ qcom,dma-mask = <0xff>;
+ qcom,transform-enabled;
+ qcom,aes128-cbc;
+ qcom,aes192-cbc;
+ qcom,aes256-cbc;
+ qcom,aes128-ctr;
+ qcom,aes192-ctr;
+ qcom,aes256-ctr;
+ qcom,aes128-ecb;
+ qcom,aes192-ecb;
+ qcom,aes256-ecb;
+ qcom,3des-cbc;
+ qcom,md5-hash;
+ qcom,sha160-hash;
+ qcom,sha224-hash;
+ qcom,sha256-hash;
+ qcom,sha384-hash;
+ qcom,sha512-hash;
+ qcom,md5-hmac;
+ qcom,sha160-hmac;
+ qcom,sha224-hmac;
+ qcom,sha256-hmac;
+ qcom,sha384-hmac;
+ qcom,sha512-hmac;
+ qcom,aes128-gcm-gmac;
+ qcom,aes192-gcm-gmac;
+ qcom,aes256-gcm-gmac;
+ qcom,aes128-cbc-md5-hmac;
+ qcom,aes128-cbc-sha160-hmac;
+ qcom,aes192-cbc-md5-hmac;
+ qcom,aes192-cbc-sha160-hmac;
+ qcom,aes256-cbc-md5-hmac;
+ qcom,aes256-cbc-sha160-hmac;
+ qcom,aes128-ctr-sha160-hmac;
+ qcom,aes192-ctr-sha160-hmac;
+ qcom,aes256-ctr-sha160-hmac;
+ qcom,aes128-ctr-md5-hmac;
+ qcom,aes192-ctr-md5-hmac;
+ qcom,aes256-ctr-md5-hmac;
+ qcom,3des-cbc-md5-hmac;
+ qcom,3des-cbc-sha160-hmac;
+ qcom,aes128-cbc-sha256-hmac;
+ qcom,aes192-cbc-sha256-hmac;
+ qcom,aes256-cbc-sha256-hmac;
+ qcom,aes128-ctr-sha256-hmac;
+ qcom,aes192-ctr-sha256-hmac;
+ qcom,aes256-ctr-sha256-hmac;
+ qcom,3des-cbc-sha256-hmac;
+ qcom,aes128-cbc-sha384-hmac;
+ qcom,aes192-cbc-sha384-hmac;
+ qcom,aes256-cbc-sha384-hmac;
+ qcom,aes128-ctr-sha384-hmac;
+ qcom,aes192-ctr-sha384-hmac;
+ qcom,aes256-ctr-sha384-hmac;
+ qcom,aes128-cbc-sha512-hmac;
+ qcom,aes192-cbc-sha512-hmac;
+ qcom,aes256-cbc-sha512-hmac;
+ qcom,aes128-ctr-sha512-hmac;
+ qcom,aes192-ctr-sha512-hmac;
+ qcom,aes256-ctr-sha512-hmac;
+
+ engine0 {
+ reg_offset = <0x80000>;
+ qcom,ifpp-enabled;
+ qcom,ipue-enabled;
+ qcom,ofpp-enabled;
+ qcom,opue-enabled;
+ };
+ };
+ };
+
i2c_0: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
@@ -343,12 +606,522 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ pcie_phy: phy@84000 {
+ compatible = "qcom,ipq6018-qmp-pcie-phy";
+ reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+
+ pcie_phy0: lane@84200 {
+ reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
+ <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
+ <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie0_pipe_clk_src";
+ #clock-cells = <0>;
+ gen3 = <1>;
+ };
+ };
+
+ pcie0: pci@20000000 {
+ compatible = "qcom,pcie-ipq6018";
+ reg = <0x0 0x20000000 0x0 0xf1d>,
+ <0x0 0x20000f20 0x0 0xa8>,
+ <0x0 0x20001000 0x0 0x1000>,
+ <0x0 0x80000 0x0 0x2000>,
+ <0x0 0x20100000 0x0 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x20200000 0x20200000
+ 0 0x10000>, /* downstream I/O */
+ <0x82000000 0 0x20220000 0x20220000
+ 0 0xfde0000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi_dev0", "msi_dev1", "msi_dev2",
+ "msi_dev3";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+ <&gcc PCIE0_RCHNG_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky",
+ "axi_s_sticky";
+
+ status = "disabled";
+ };
+
watchdog@b017000 {
compatible = "qcom,kpss-wdt";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0x0b017000 0x0 0x40>;
clocks = <&sleep_clk>;
- timeout-sec = <10>;
+ timeout-sec = <30>;
+ };
+
+ mdio@90000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,qca-mdio", "qcom,ipq40xx-mdio";
+ reg = <0x0 0x90000 0x0 0x64>;
+ status = "disabled";
+ };
+
+ ess-switch@3a000000 {
+ compatible = "qcom,ess-switch-ipq60xx";
+ reg = <0x3a000000 0x1000000>;
+ switch_access_mode = "local bus";
+ clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>,
+ <&gcc GCC_UNIPHY0_AHB_CLK>,
+ <&gcc GCC_UNIPHY0_SYS_CLK>,
+ <&gcc GCC_UNIPHY1_AHB_CLK>,
+ <&gcc GCC_UNIPHY1_SYS_CLK>,
+ <&gcc GCC_PORT1_MAC_CLK>,
+ <&gcc GCC_PORT2_MAC_CLK>,
+ <&gcc GCC_PORT3_MAC_CLK>,
+ <&gcc GCC_PORT4_MAC_CLK>,
+ <&gcc GCC_PORT5_MAC_CLK>,
+ <&gcc GCC_NSS_PPE_CLK>,
+ <&gcc GCC_NSS_PPE_CFG_CLK>,
+ <&gcc GCC_NSSNOC_PPE_CLK>,
+ <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
+ <&gcc GCC_NSS_EDMA_CLK>,
+ <&gcc GCC_NSS_EDMA_CFG_CLK>,
+ <&gcc GCC_NSS_PPE_IPE_CLK>,
+ <&gcc GCC_MDIO_AHB_CLK>,
+ <&gcc GCC_NSS_NOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_NSS_CRYPTO_CLK>,
+ <&gcc GCC_NSS_PTP_REF_CLK>,
+ <&gcc GCC_NSS_PORT1_RX_CLK>,
+ <&gcc GCC_NSS_PORT1_TX_CLK>,
+ <&gcc GCC_NSS_PORT2_RX_CLK>,
+ <&gcc GCC_NSS_PORT2_TX_CLK>,
+ <&gcc GCC_NSS_PORT3_RX_CLK>,
+ <&gcc GCC_NSS_PORT3_TX_CLK>,
+ <&gcc GCC_NSS_PORT4_RX_CLK>,
+ <&gcc GCC_NSS_PORT4_TX_CLK>,
+ <&gcc GCC_NSS_PORT5_RX_CLK>,
+ <&gcc GCC_NSS_PORT5_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
+ <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
+ <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
+ <&gcc NSS_PORT5_RX_CLK_SRC>,
+ <&gcc NSS_PORT5_TX_CLK_SRC>,
+ <&gcc GCC_SNOC_NSSNOC_CLK>;
+ clock-names = "cmn_ahb_clk", "cmn_sys_clk",
+ "uniphy0_ahb_clk", "uniphy0_sys_clk",
+ "uniphy1_ahb_clk", "uniphy1_sys_clk",
+ "port1_mac_clk", "port2_mac_clk",
+ "port3_mac_clk", "port4_mac_clk",
+ "port5_mac_clk",
+ "nss_ppe_clk", "nss_ppe_cfg_clk",
+ "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
+ "nss_edma_clk", "nss_edma_cfg_clk",
+ "nss_ppe_ipe_clk",
+ "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
+ "gcc_nssnoc_snoc_clk",
+ "gcc_nss_crypto_clk",
+ "gcc_nss_ptp_ref_clk",
+ "nss_port1_rx_clk", "nss_port1_tx_clk",
+ "nss_port2_rx_clk", "nss_port2_tx_clk",
+ "nss_port3_rx_clk", "nss_port3_tx_clk",
+ "nss_port4_rx_clk", "nss_port4_tx_clk",
+ "nss_port5_rx_clk", "nss_port5_tx_clk",
+ "uniphy0_port1_rx_clk",
+ "uniphy0_port1_tx_clk",
+ "uniphy0_port2_rx_clk",
+ "uniphy0_port2_tx_clk",
+ "uniphy0_port3_rx_clk",
+ "uniphy0_port3_tx_clk",
+ "uniphy0_port4_rx_clk",
+ "uniphy0_port4_tx_clk",
+ "uniphy0_port5_rx_clk",
+ "uniphy0_port5_tx_clk",
+ "uniphy1_port5_rx_clk",
+ "uniphy1_port5_tx_clk",
+ "nss_port5_rx_clk_src",
+ "nss_port5_tx_clk_src",
+ "gcc_snoc_nssnoc_clk";
+ resets = <&gcc GCC_PPE_FULL_RESET>,
+ <&gcc GCC_UNIPHY0_SOFT_RESET>,
+ <&gcc GCC_UNIPHY0_XPCS_RESET>,
+ <&gcc GCC_UNIPHY1_SOFT_RESET>,
+ <&gcc GCC_UNIPHY1_XPCS_RESET>,
+ <&gcc GCC_NSSPORT1_RESET>,
+ <&gcc GCC_NSSPORT2_RESET>,
+ <&gcc GCC_NSSPORT3_RESET>,
+ <&gcc GCC_NSSPORT4_RESET>,
+ <&gcc GCC_NSSPORT5_RESET>,
+ <&gcc GCC_UNIPHY0_PORT1_ARES>,
+ <&gcc GCC_UNIPHY0_PORT2_ARES>,
+ <&gcc GCC_UNIPHY0_PORT3_ARES>,
+ <&gcc GCC_UNIPHY0_PORT4_ARES>,
+ <&gcc GCC_UNIPHY0_PORT5_ARES>,
+ <&gcc GCC_UNIPHY0_PORT_4_5_RESET>,
+ <&gcc GCC_UNIPHY0_PORT_4_RESET>;
+ reset-names = "ppe_rst", "uniphy0_soft_rst",
+ "uniphy0_xpcs_rst", "uniphy1_soft_rst",
+ "uniphy1_xpcs_rst", "nss_port1_rst",
+ "nss_port2_rst", "nss_port3_rst",
+ "nss_port4_rst", "nss_port5_rst",
+ "uniphy0_port1_dis",
+ "uniphy0_port2_dis",
+ "uniphy0_port3_dis",
+ "uniphy0_port4_dis",
+ "uniphy0_port5_dis",
+ "uniphy0_port_4_5_rst",
+ "uniphy0_port_4_rst";
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_inner_bmp = <0xc0>; /*inner port bitmap*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+ port_scheduler_resource {
+ port@0 {
+ port_id = <0>;
+ ucast_queue = <0 143>;
+ mcast_queue = <256 271>;
+ l0sp = <0 35>;
+ l0cdrr = <0 47>;
+ l0edrr = <0 47>;
+ l1cdrr = <0 7>;
+ l1edrr = <0 7>;
+ };
+ port@1 {
+ port_id = <1>;
+ ucast_queue = <144 159>;
+ mcast_queue = <272 275>;
+ l0sp = <36 39>;
+ l0cdrr = <48 63>;
+ l0edrr = <48 63>;
+ l1cdrr = <8 11>;
+ l1edrr = <8 11>;
+ };
+ port@2 {
+ port_id = <2>;
+ ucast_queue = <160 175>;
+ mcast_queue = <276 279>;
+ l0sp = <40 43>;
+ l0cdrr = <64 79>;
+ l0edrr = <64 79>;
+ l1cdrr = <12 15>;
+ l1edrr = <12 15>;
+ };
+ port@3 {
+ port_id = <3>;
+ ucast_queue = <176 191>;
+ mcast_queue = <280 283>;
+ l0sp = <44 47>;
+ l0cdrr = <80 95>;
+ l0edrr = <80 95>;
+ l1cdrr = <16 19>;
+ l1edrr = <16 19>;
+ };
+ port@4 {
+ port_id = <4>;
+ ucast_queue = <192 207>;
+ mcast_queue = <284 287>;
+ l0sp = <48 51>;
+ l0cdrr = <96 111>;
+ l0edrr = <96 111>;
+ l1cdrr = <20 23>;
+ l1edrr = <20 23>;
+ };
+ port@5 {
+ port_id = <5>;
+ ucast_queue = <208 223>;
+ mcast_queue = <288 291>;
+ l0sp = <52 55>;
+ l0cdrr = <112 127>;
+ l0edrr = <112 127>;
+ l1cdrr = <24 27>;
+ l1edrr = <24 27>;
+ };
+ port@6 {
+ port_id = <6>;
+ ucast_queue = <224 239>;
+ mcast_queue = <292 295>;
+ l0sp = <56 59>;
+ l0cdrr = <128 143>;
+ l0edrr = <128 143>;
+ l1cdrr = <28 31>;
+ l1edrr = <28 31>;
+ };
+ port@7 {
+ port_id = <7>;
+ ucast_queue = <240 255>;
+ mcast_queue = <296 299>;
+ l0sp = <60 63>;
+ l0cdrr = <144 159>;
+ l0edrr = <144 159>;
+ l1cdrr = <32 35>;
+ l1edrr = <32 35>;
+ };
+ };
+ port_scheduler_config {
+ port@0 {
+ port_id = <0>;
+ l1scheduler {
+ group@0 {
+ sp = <0 1>; /*L0 SPs*/
+ /*cpri cdrr epri edrr*/
+ cfg = <0 0 0 0>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ /*unicast queues*/
+ ucast_queue = <0 4 8>;
+ /*multicast queues*/
+ mcast_queue = <256 260>;
+ /*sp cpricdrrepriedrr*/
+ cfg = <0 0 0 0 0>;
+ };
+ group@1 {
+ ucast_queue = <1 5 9>;
+ mcast_queue = <257 261>;
+ cfg = <0 1 1 1 1>;
+ };
+ group@2 {
+ ucast_queue = <2 6 10>;
+ mcast_queue = <258 262>;
+ cfg = <0 2 2 2 2>;
+ };
+ group@3 {
+ ucast_queue = <3 7 11>;
+ mcast_queue = <259 263>;
+ cfg = <0 3 3 3 3>;
+ };
+ };
+ };
+ port@1 {
+ port_id = <1>;
+ l1scheduler {
+ group@0 {
+ sp = <36>;
+ cfg = <0 8 0 8>;
+ };
+ group@1 {
+ sp = <37>;
+ cfg = <1 9 1 9>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <144>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <272>;
+ mcast_loop_pri = <4>;
+ cfg = <36 0 48 0 48>;
+ };
+ };
+ };
+ port@2 {
+ port_id = <2>;
+ l1scheduler {
+ group@0 {
+ sp = <40>;
+ cfg = <0 12 0 12>;
+ };
+ group@1 {
+ sp = <41>;
+ cfg = <1 13 1 13>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <160>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <276>;
+ mcast_loop_pri = <4>;
+ cfg = <40 0 64 0 64>;
+ };
+ };
+ };
+ port@3 {
+ port_id = <3>;
+ l1scheduler {
+ group@0 {
+ sp = <44>;
+ cfg = <0 16 0 16>;
+ };
+ group@1 {
+ sp = <45>;
+ cfg = <1 17 1 17>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <176>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <280>;
+ mcast_loop_pri = <4>;
+ cfg = <44 0 80 0 80>;
+ };
+ };
+ };
+ port@4 {
+ port_id = <4>;
+ l1scheduler {
+ group@0 {
+ sp = <48>;
+ cfg = <0 20 0 20>;
+ };
+ group@1 {
+ sp = <49>;
+ cfg = <1 21 1 21>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <192>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <284>;
+ mcast_loop_pri = <4>;
+ cfg = <48 0 96 0 96>;
+ };
+ };
+ };
+ port@5 {
+ port_id = <5>;
+ l1scheduler {
+ group@0 {
+ sp = <52>;
+ cfg = <0 24 0 24>;
+ };
+ group@1 {
+ sp = <53>;
+ cfg = <1 25 1 25>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <208>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <288>;
+ mcast_loop_pri = <4>;
+ cfg = <52 0 112 0 112>;
+ };
+ };
+ };
+ port@6 {
+ port_id = <6>;
+ l1scheduler {
+ group@0 {
+ sp = <56>;
+ cfg = <0 28 0 28>;
+ };
+ group@1 {
+ sp = <57>;
+ cfg = <1 29 1 29>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <224>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <292>;
+ mcast_loop_pri = <4>;
+ cfg = <56 0 128 0 128>;
+ };
+ };
+ };
+ port@7 {
+ port_id = <7>;
+ l1scheduler {
+ group@0 {
+ sp = <60>;
+ cfg = <0 32 0 32>;
+ };
+ group@1 {
+ sp = <61>;
+ cfg = <1 33 1 33>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <240>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <296>;
+ cfg = <60 0 144 0 144>;
+ };
+ };
+ };
+ };
+ };
+
+ ess-uniphy@7a00000 {
+ compatible = "qcom,ess-uniphy";
+ reg = <0x7a00000 0x30000>;
+ uniphy_access_mode = "local bus";
};
apcs_glb: mailbox@b111000 {
@@ -436,7 +1209,7 @@
};
q6v5_wcss: remoteproc@cd00000 {
- compatible = "qcom,ipq8074-wcss-pil";
+ compatible = "qcom,ipq6018-wcss-pil";
reg = <0x0 0x0cd00000 0x0 0x4040>,
<0x0 0x004ab000 0x0 0x20>;
reg-names = "qdsp6",
@@ -483,6 +1256,277 @@
};
};
+ qusb_phy_1: qusb@59000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x059000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+ status = "disabled";
+ };
+
+ usb2: usb2@7000000 {
+ compatible = "qcom,dwc3";
+ reg = <0x0 0x070F8800 0x0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_SLEEP_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ clock-names = "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <24000000>;
+ resets = <&gcc GCC_USB1_BCR>;
+ status = "disabled";
+
+ dwc_1: dwc3@7000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x7000000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_1>;
+ phy-names = "usb2-phy";
+ snps,dis_ep_cache_eviction;
+ tx-fifo-resize;
+ snps,usb3-u1u2-disable;
+ snps,nominal-elastic-buffer;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-ref-clock-adjustment = <0xA87F0>;
+ snps,quirk-ref-clock-period = <0x29>;
+ dr_mode = "host";
+ };
+ };
+
+ ssphy_0: ssphy@78000 {
+ compatible = "qcom,ipq6018-qmp-usb3-phy";
+ reg = <0x0 0x78000 0x0 0x1C4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb0_ssphy: lane@78200 {
+ reg = <0x00078200 0x130>, /* Tx */
+ <0x00078400 0x200>, /* Rx */
+ <0x00078800 0x1F8>, /* PCS */
+ <0x00078600 0x044>; /* PCS misc */
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_0: qusb@79000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x079000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ usb3: usb3@8A00000 {
+ compatible = "qcom,dwc3";
+ reg = <0x0 0x8AF8800 0x0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "sys_noc_axi",
+ "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <133330000>,
+ <24000000>;
+
+ resets = <&gcc GCC_USB0_BCR>;
+ status = "disabled";
+
+ dwc_0: dwc3@8A00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x8A00000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,dis_ep_cache_eviction;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-ref-clock-adjustment = <0xA87F0>;
+ snps,quirk-ref-clock-period = <0x29>;
+ dr_mode = "host";
+ };
+ };
+
+ wifi0: wifi@c000000 {
+ compatible = "qcom,cnss-qca6018", "qcom,ipq6018-wifi";
+ reg = <0xc000000 0x1000000>;
+ qcom,hw-mode-id = <1>;
+#ifdef __IPQ_MEM_PROFILE_256_MB__
+ qcom,tgt-mem-mode = <2>;
+#elif __IPQ_MEM_PROFILE_512_MB__
+ qcom,tgt-mem-mode = <1>;
+#else
+ qcom,tgt-mem-mode = <0>;
+#endif
+ mem-region = <&q6_region>;
+ qcom,bdf-addr = <0x4ABC0000 0x4ABC0000 0x4ABC0000 0x0 0x0>;
+ qcom,caldb-addr = <0x4B500000 0x4B500000 0x4B500000 0x0 0x0>;
+ qcom,caldb-size = <0x480000>;
+
+ qcom,rproc = <&q6v5_wcss>;
+ interrupts = <0 320 1>, /* o_wcss_apps_intr[0] = */
+ <0 319 1>,
+ <0 318 1>,
+ <0 316 1>,
+ <0 315 1>,
+ <0 314 1>,
+ <0 311 1>,
+ <0 310 1>,
+ <0 411 1>,
+ <0 410 1>,
+ <0 40 1>,
+ <0 39 1>,
+ <0 302 1>,
+ <0 301 1>,
+ <0 37 1>,
+ <0 36 1>,
+ <0 296 1>,
+ <0 295 1>,
+ <0 294 1>,
+ <0 293 1>,
+ <0 292 1>,
+ <0 291 1>,
+ <0 290 1>,
+ <0 289 1>,
+ <0 288 1>, /* o_wcss_apps_intr[25] */
+
+ <0 239 1>,
+ <0 236 1>,
+ <0 235 1>,
+ <0 234 1>,
+ <0 233 1>,
+ <0 232 1>,
+ <0 231 1>,
+ <0 230 1>,
+ <0 229 1>,
+ <0 228 1>,
+ <0 224 1>,
+ <0 223 1>,
+
+ <0 203 1>,
+
+ <0 183 1>,
+ <0 180 1>,
+ <0 179 1>,
+ <0 178 1>,
+ <0 177 1>,
+ <0 176 1>,
+
+ <0 163 1>,
+ <0 162 1>,
+ <0 160 1>,
+ <0 159 1>,
+ <0 158 1>,
+ <0 157 1>,
+ <0 156 1>; /* o_wcss_apps_intr[51] */
+
+ interrupt-names = "misc-pulse1",
+ "misc-latch",
+ "sw-exception",
+ "ce0",
+ "ce1",
+ "ce2",
+ "ce3",
+ "ce4",
+ "ce5",
+ "ce6",
+ "ce7",
+ "ce8",
+ "ce9",
+ "ce10",
+ "ce11",
+ "host2wbm-desc-feed",
+ "host2reo-re-injection",
+ "host2reo-command",
+ "host2rxdma-monitor-ring3",
+ "host2rxdma-monitor-ring2",
+ "host2rxdma-monitor-ring1",
+ "reo2ost-exception",
+ "wbm2host-rx-release",
+ "reo2host-status",
+ "reo2host-destination-ring4",
+ "reo2host-destination-ring3",
+ "reo2host-destination-ring2",
+ "reo2host-destination-ring1",
+ "rxdma2host-monitor-destination-mac3",
+ "rxdma2host-monitor-destination-mac2",
+ "rxdma2host-monitor-destination-mac1",
+ "ppdu-end-interrupts-mac3",
+ "ppdu-end-interrupts-mac2",
+ "ppdu-end-interrupts-mac1",
+ "rxdma2host-monitor-status-ring-mac3",
+ "rxdma2host-monitor-status-ring-mac2",
+ "rxdma2host-monitor-status-ring-mac1",
+ "host2rxdma-host-buf-ring-mac3",
+ "host2rxdma-host-buf-ring-mac2",
+ "host2rxdma-host-buf-ring-mac1",
+ "rxdma2host-destination-ring-mac3",
+ "rxdma2host-destination-ring-mac2",
+ "rxdma2host-destination-ring-mac1",
+ "host2tcl-input-ring4",
+ "host2tcl-input-ring3",
+ "host2tcl-input-ring2",
+ "host2tcl-input-ring1",
+ "wbm2host-tx-completions-ring3",
+ "wbm2host-tx-completions-ring2",
+ "wbm2host-tx-completions-ring1",
+ "tcl2host-status-ring";
+ status = "ok";
+ qcom,pta-num = <0>;
+ qcom,coex-mode = <0x2>;
+ qcom,bt-active-time = <0x18>;
+ qcom,bt-priority-time = <0x12>;
+ qcom,coex-algo = <0x2>;
+ qcom,pta-priority = <0x80800505>;
+ };
};
wcss: wcss-smp2p {
@@ -499,6 +1543,7 @@
wcss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
+ qcom,smp2p-feature-ssr-ack;
#qcom,smem-state-cells = <1>;
};
@@ -527,6 +1572,12 @@
regulator-max-microvolt = <1062500>;
regulator-always-on;
};
+
+ ipq6018_l2: l2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
};
};
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