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40 lines
1.4 KiB
Diff
40 lines
1.4 KiB
Diff
From 26becdb00a29d53a23fd06e67e9750d167fe982d Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 26 Jun 2021 00:51:32 +0200
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Subject: [PATCH] PCI: qcom: Make sure PCI is reset and clocks are enabled
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before init for IP 2.3.3
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IPQ8074 which uses IP 2.3.3 requires that the PHY is
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powered on, resets are asserted as bootloader can
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leave them in a weird state and clocks are enabled
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before accessing the register space.
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Otherwise the system would simply hang on a DBI read.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 5 ++++-
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1 file changed, 4 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -1035,7 +1035,7 @@ static int qcom_pcie_init_2_3_3(struct q
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struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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- u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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+ u16 offset;
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int i, ret;
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u32 val;
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@@ -1111,6 +1111,9 @@ static int qcom_pcie_init_2_3_3(struct q
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writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
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writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
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+
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+ offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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+
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writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
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val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
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