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168 lines
3.7 KiB
Diff
168 lines
3.7 KiB
Diff
From de1ca571d14bab031cc57bab5311db05f33ceec3 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 19 May 2021 00:14:50 +0200
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Subject: [PATCH] arm64: dts: ipq8074: add thermal nodes
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IPQ8074 has a tsens v2.3.0 peripheral which monitors
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temperatures around the various subsystems on the
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die.
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So, lets add the required nodes for tsens and thermal
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zones to enable passive cooling of the device.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 101 ++++++++++++++++++++++++++
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1 file changed, 101 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -6,6 +6,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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#include <dt-bindings/clock/qca,apss-ipq8074.h>
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+#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/spmi/spmi.h>
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/ {
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@@ -38,6 +39,7 @@
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clock-names = "cpu";
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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+ #cooling-cells = <2>;
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};
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CPU1: cpu@1 {
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@@ -48,6 +50,7 @@
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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next-level-cache = <&L2_0>;
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+ #cooling-cells = <2>;
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};
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CPU2: cpu@2 {
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@@ -58,6 +61,7 @@
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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next-level-cache = <&L2_0>;
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+ #cooling-cells = <2>;
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};
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CPU3: cpu@3 {
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@@ -68,6 +72,7 @@
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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next-level-cache = <&L2_0>;
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+ #cooling-cells = <2>;
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};
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L2_0: l2-cache {
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@@ -365,6 +370,16 @@
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status = "disabled";
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};
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+ tsens: thermal-sensor@4a9000 {
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+ compatible = "qcom,ipq8074-tsens";
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+ reg = <0x4a9000 0x1000>, /* TM */
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+ <0x4a8000 0x1000>; /* SROT */
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+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "uplow";
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+ #qcom,sensors = <16>;
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+ #thermal-sensor-cells = <1>;
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+ };
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+
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cryptobam: dma@704000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x00704000 0x20000>;
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@@ -1284,4 +1299,90 @@
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#clock-cells = <0>;
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};
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};
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+
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+ thermal-zones {
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+ nss-top-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 4>;
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+ };
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+
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+ nss0-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 5>;
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+ };
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+
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+ nss1-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 6>;
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+ };
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+
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+ wcss-phya0-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 7>;
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+ };
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+
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+ wcss-phya1-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 8>;
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+ };
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+
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+ cpu0_thermal: cpu0-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 9>;
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+ };
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+
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+ cpu1_thermal: cpu1-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 10>;
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+ };
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+
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+ cpu2_thermal: cpu2-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 11>;
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+ };
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+
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+ cpu3_thermal: cpu3-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 12>;
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+ };
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+
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+ cluster_thermal: cluster-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 13>;
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+ };
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+
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+ wcss-phyb0-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 14>;
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+ };
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+
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+ wcss-phyb1-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 15>;
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+ };
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+ };
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};
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