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42 lines
1.5 KiB
Diff
42 lines
1.5 KiB
Diff
From 6cc04849eea4d87b3b274cc900c6a14a1ac866f5 Mon Sep 17 00:00:00 2001
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From: Praveenkumar I <ipkumar@codeaurora.org>
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Date: Wed, 12 Jul 2017 21:42:11 +0530
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Subject: [PATCH 7/8] clk: qcom: ipq8074: Add NSS PORT clocks frequencies
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The port clock uses different frequency which depends upon
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ethernet PHY mode.
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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(cherry picked from commit ae5f033e8929d0ffc34320c89b5683f801c3121c)
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Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
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Change-Id: I7f5d24bc400b3c35d68ef08ae73ab8395b7dd87b
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---
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drivers/clk/qcom/gcc-ipq8074.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -1810,8 +1810,10 @@ static struct clk_regmap_div nss_port4_t
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static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
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+ F(25000000, P_UNIPHY0_RX, 5, 0, 0),
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F(78125000, P_UNIPHY1_RX, 4, 0, 0),
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F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
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+ F(125000000, P_UNIPHY0_RX, 1, 0, 0),
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F(156250000, P_UNIPHY1_RX, 2, 0, 0),
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F(312500000, P_UNIPHY1_RX, 1, 0, 0),
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{ }
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@@ -1849,8 +1851,10 @@ static struct clk_regmap_div nss_port5_r
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static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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+ F(25000000, P_UNIPHY0_TX, 5, 0, 0),
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F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
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F(78125000, P_UNIPHY1_TX, 4, 0, 0),
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+ F(125000000, P_UNIPHY0_TX, 1, 0, 0),
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F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
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F(156250000, P_UNIPHY1_TX, 2, 0, 0),
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F(312500000, P_UNIPHY1_TX, 1, 0, 0),
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