mirror of
https://github.com/coolsnowwolf/lede.git
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213 lines
6.1 KiB
Diff
213 lines
6.1 KiB
Diff
From 4f579facd45c39f8f8b9993570944f4d83a95955 Mon Sep 17 00:00:00 2001
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From: Praveenkumar I <ipkumar@codeaurora.org>
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Date: Wed, 5 Feb 2020 10:13:01 +0530
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Subject: [PATCH 2/8] ipq8074: gcc: Added support for NSS clocks
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Change-Id: I446e84dbc3498618425677811a73124b99b5c0ad
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Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
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Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++
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drivers/clk/qcom/gcc-ipq8074.c | 68 +++++++++++++++++++-
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include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
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3 files changed, 80 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -1049,5 +1049,17 @@
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resets = <&gcc GCC_EDMA_HW_RESET>;
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reset-names = "edma_rst";
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};
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+
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+ bias_pll_cc_clk {
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+ compatible = "fixed-clock";
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+ clock-frequency = <300000000>;
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+ #clock-cells = <0>;
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+ };
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+
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+ bias_pll_nss_noc_clk {
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+ compatible = "fixed-clock";
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+ clock-frequency = <416500000>;
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+ #clock-cells = <0>;
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+ };
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};
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};
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -3174,6 +3174,24 @@ static struct clk_branch gcc_nss_ptp_ref
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},
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};
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+static struct clk_branch gcc_crypto_ppe_clk = {
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+ .halt_reg = 0x68310,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x68310,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_crypto_ppe_clk",
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+ .parent_names = (const char *[]){
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+ "nss_ppe_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static struct clk_branch gcc_nssnoc_ce_apb_clk = {
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.halt_reg = 0x6830c,
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.clkr = {
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@@ -3346,6 +3364,7 @@ static struct clk_branch gcc_nssnoc_ubi1
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static struct clk_branch gcc_ubi0_ahb_clk = {
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.halt_reg = 0x6820c,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x6820c,
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.enable_mask = BIT(0),
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@@ -3363,6 +3382,7 @@ static struct clk_branch gcc_ubi0_ahb_cl
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static struct clk_branch gcc_ubi0_axi_clk = {
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.halt_reg = 0x68200,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x68200,
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.enable_mask = BIT(0),
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@@ -3380,6 +3400,7 @@ static struct clk_branch gcc_ubi0_axi_cl
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static struct clk_branch gcc_ubi0_nc_axi_clk = {
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.halt_reg = 0x68204,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x68204,
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.enable_mask = BIT(0),
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@@ -3397,6 +3418,7 @@ static struct clk_branch gcc_ubi0_nc_axi
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static struct clk_branch gcc_ubi0_core_clk = {
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.halt_reg = 0x68210,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x68210,
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.enable_mask = BIT(0),
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@@ -3414,6 +3436,7 @@ static struct clk_branch gcc_ubi0_core_c
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static struct clk_branch gcc_ubi0_mpt_clk = {
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.halt_reg = 0x68208,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x68208,
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.enable_mask = BIT(0),
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@@ -3431,6 +3454,7 @@ static struct clk_branch gcc_ubi0_mpt_cl
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static struct clk_branch gcc_ubi1_ahb_clk = {
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.halt_reg = 0x6822c,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x6822c,
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.enable_mask = BIT(0),
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@@ -3448,6 +3472,7 @@ static struct clk_branch gcc_ubi1_ahb_cl
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static struct clk_branch gcc_ubi1_axi_clk = {
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.halt_reg = 0x68220,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x68220,
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.enable_mask = BIT(0),
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@@ -3465,6 +3490,7 @@ static struct clk_branch gcc_ubi1_axi_cl
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static struct clk_branch gcc_ubi1_nc_axi_clk = {
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.halt_reg = 0x68224,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x68224,
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.enable_mask = BIT(0),
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@@ -3482,6 +3508,7 @@ static struct clk_branch gcc_ubi1_nc_axi
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static struct clk_branch gcc_ubi1_core_clk = {
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.halt_reg = 0x68230,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x68230,
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.enable_mask = BIT(0),
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@@ -3499,6 +3526,7 @@ static struct clk_branch gcc_ubi1_core_c
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static struct clk_branch gcc_ubi1_mpt_clk = {
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.halt_reg = 0x68228,
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+ .halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x68228,
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.enable_mask = BIT(0),
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@@ -4381,6 +4409,33 @@ static struct clk_hw *gcc_ipq8074_hws[]
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&nss_ppe_cdiv_clk_src.hw,
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};
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+static const struct alpha_pll_config ubi32_pll_config = {
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+ .l = 0x4e,
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+ .config_ctl_val = 0x200d4aa8,
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+ .config_ctl_hi_val = 0x3c2,
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+ .main_output_mask = BIT(0),
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+ .aux_output_mask = BIT(1),
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+ .pre_div_val = 0x0,
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+ .pre_div_mask = BIT(12),
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+ .post_div_val = 0x0,
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+ .post_div_mask = GENMASK(9, 8),
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+};
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+
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+static const struct alpha_pll_config nss_crypto_pll_config = {
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+ .l = 0x3e,
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+ .alpha = 0x0,
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+ .alpha_hi = 0x80,
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+ .config_ctl_val = 0x4001055b,
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+ .main_output_mask = BIT(0),
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+ .pre_div_val = 0x0,
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+ .pre_div_mask = GENMASK(14, 12),
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+ .post_div_val = 0x1 << 8,
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+ .post_div_mask = GENMASK(11, 8),
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+ .vco_mask = GENMASK(21, 20),
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+ .vco_val = 0x0,
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+ .alpha_en_mask = BIT(24),
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+};
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+
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static struct clk_regmap *gcc_ipq8074_clks[] = {
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[GPLL0_MAIN] = &gpll0_main.clkr,
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[GPLL0] = &gpll0.clkr,
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@@ -4562,6 +4617,7 @@ static struct clk_regmap *gcc_ipq8074_cl
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[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
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[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
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[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
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+ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
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[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
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[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
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[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
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@@ -4773,7 +4829,17 @@ static const struct qcom_cc_desc gcc_ipq
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static int gcc_ipq8074_probe(struct platform_device *pdev)
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{
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- return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
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+ struct regmap *regmap;
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+
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+ regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
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+ if (IS_ERR(regmap))
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+ return PTR_ERR(regmap);
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+
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+ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
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+ clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
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+ &nss_crypto_pll_config);
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+
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+ return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
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}
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static struct platform_driver gcc_ipq8074_driver = {
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--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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@@ -233,6 +233,7 @@
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#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
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#define GCC_PCIE0_RCHNG_CLK_SRC 225
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#define GCC_PCIE0_RCHNG_CLK 226
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+#define GCC_CRYPTO_PPE_CLK 227
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#define GCC_BLSP1_BCR 0
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#define GCC_BLSP1_QUP1_BCR 1
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