mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
45 lines
1.7 KiB
Diff
45 lines
1.7 KiB
Diff
From 35df745d335bd21094f522dc9dff7eaae92114d9 Mon Sep 17 00:00:00 2001
|
|
From: Baruch Siach <baruch@tkos.co.il>
|
|
Date: Wed, 5 May 2021 12:18:29 +0300
|
|
Subject: [PATCH] PCI: dwc: tegra: move GEN3_RELATED DBI register to common
|
|
header
|
|
|
|
These are common dwc macros that will be used for other platforms.
|
|
|
|
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
|
|
---
|
|
drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
|
|
drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
|
|
2 files changed, 6 insertions(+), 6 deletions(-)
|
|
|
|
--- a/drivers/pci/controller/dwc/pcie-designware.h
|
|
+++ b/drivers/pci/controller/dwc/pcie-designware.h
|
|
@@ -74,6 +74,12 @@
|
|
#define PCIE_MSI_INTR0_MASK 0x82C
|
|
#define PCIE_MSI_INTR0_STATUS 0x830
|
|
|
|
+#define GEN3_RELATED_OFF 0x890
|
|
+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
|
|
+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
|
|
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
|
|
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
|
|
+
|
|
#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
|
|
#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
|
|
|
|
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
|
|
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
|
|
@@ -193,12 +193,6 @@
|
|
#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
|
|
#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
|
|
|
|
-#define GEN3_RELATED_OFF 0x890
|
|
-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
|
|
-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
|
|
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
|
|
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
|
|
-
|
|
#define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
|
|
#define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
|
|
#define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
|