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55 lines
1.8 KiB
Diff
55 lines
1.8 KiB
Diff
From 8d111d707f71bc17c616b0bcca327ee0a3db50e8 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Mon, 2 Nov 2020 19:03:59 +0100
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Subject: [PATCH] clk: qcom: ipq8074: fix PCI-E clock oops
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Fix PCI-E clock related kernel oops that are causes by missing
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parent_names.
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Without the use of parent_names kernel will panic on
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clk_core_get_parent_by_index() due to a NULL pointer.
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Without this earlycon is needed to even catch the OOPS as it will reset
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the board before serial is initialized.
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Fixes: f0cfcf1ade20 ("clk: qcom: ipq8074: Add missing clocks for pcie")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 11 +++++------
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1 file changed, 5 insertions(+), 6 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -4329,8 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
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.parent_map = gcc_xo_gpll0_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pcie0_rchng_clk_src",
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- .parent_hws = (const struct clk_hw *[]) {
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- &gpll0.clkr.hw },
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+ .parent_names = gcc_xo_gpll0,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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@@ -4344,8 +4343,8 @@ static struct clk_branch gcc_pcie0_rchng
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie0_rchng_clk",
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- .parent_hws = (const struct clk_hw *[]){
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- &pcie0_rchng_clk_src.clkr.hw,
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+ .parent_names = (const char *[]){
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+ "pcie0_rchng_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@@ -4362,8 +4361,8 @@ static struct clk_branch gcc_pcie0_axi_s
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie0_axi_s_bridge_clk",
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- .parent_hws = (const struct clk_hw *[]){
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- &pcie0_axi_clk_src.clkr.hw,
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+ .parent_names = (const char *[]){
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+ "pcie0_axi_clk_src"
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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