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116 lines
3.3 KiB
Diff
116 lines
3.3 KiB
Diff
From d438c9afd73a482a0438e6cf86daa0580422598e Mon Sep 17 00:00:00 2001
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From: Kathiravan T <kathirav@codeaurora.org>
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Date: Tue, 31 Aug 2021 08:57:32 +0300
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Subject: [PATCH 1013/1013] arm64: dts: qcom: ipq6018: add usb3 DT description
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Based on downstream codeaurora code.
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Tested (USB2 only) on IPQ6010 based hardware.
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Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
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Signed-off-by: Baruch Siach <baruch@tkos.co.il>
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[bjorn: Changed dwc3 node name to usb, per binding]
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/ebc2d340d566fa2d43127e253d5b8b134a87a78e.1630389452.git.baruch@tkos.co.il
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 83 +++++++++++++++++++++++++++
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1 file changed, 83 insertions(+)
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diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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index d8da83aa8bda..b4c9bda0104c 100644
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -715,6 +715,89 @@ dwc_1: usb@7000000 {
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};
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};
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+ ssphy_0: ssphy@78000 {
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+ compatible = "qcom,ipq6018-qmp-usb3-phy";
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+ reg = <0x0 0x78000 0x0 0x1C4>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ #clock-cells = <1>;
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+ ranges;
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+
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+ clocks = <&gcc GCC_USB0_AUX_CLK>,
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+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
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+ clock-names = "aux", "cfg_ahb", "ref";
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+
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+ resets = <&gcc GCC_USB0_PHY_BCR>,
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+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
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+ reset-names = "phy","common";
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+ status = "disabled";
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+
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+ usb0_ssphy: lane@78200 {
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+ reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
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+ <0x0 0x00078400 0x0 0x200>, /* Rx */
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+ <0x0 0x00078800 0x0 0x1F8>, /* PCS */
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+ <0x0 0x00078600 0x0 0x044>; /* PCS misc */
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+ #phy-cells = <0>;
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+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
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+ clock-names = "pipe0";
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+ clock-output-names = "gcc_usb0_pipe_clk_src";
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+ };
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+ };
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+
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+ qusb_phy_0: qusb@79000 {
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+ compatible = "qcom,ipq6018-qusb2-phy";
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+ reg = <0x0 0x079000 0x0 0x180>;
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+ #phy-cells = <0>;
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+
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+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
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+ <&xo>;
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+ clock-names = "cfg_ahb", "ref";
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+
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+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
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+ status = "disabled";
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+ };
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+
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+ usb3: usb3@8A00000 {
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+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
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+ reg = <0x0 0x8AF8800 0x0 0x400>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
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+ <&gcc GCC_USB0_MASTER_CLK>,
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+ <&gcc GCC_USB0_SLEEP_CLK>,
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+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
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+ clock-names = "sys_noc_axi",
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+ "master",
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+ "sleep",
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+ "mock_utmi";
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+
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+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
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+ <&gcc GCC_USB0_MASTER_CLK>,
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+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
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+ assigned-clock-rates = <133330000>,
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+ <133330000>,
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+ <20000000>;
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+
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+ resets = <&gcc GCC_USB0_BCR>;
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+ status = "disabled";
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+
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+ dwc_0: usb@8A00000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0x8A00000 0x0 0xcd00>;
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+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ tx-fifo-resize;
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+ snps,is-utmi-l1-suspend;
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+ snps,hird-threshold = /bits/ 8 <0x0>;
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+ snps,dis_u2_susphy_quirk;
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+ snps,dis_u3_susphy_quirk;
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+ snps,ref-clock-period-ns = <0x32>;
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+ dr_mode = "host";
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+ };
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+ };
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};
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wcss: wcss-smp2p {
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--
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2.37.1
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