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96 lines
2.4 KiB
Diff
96 lines
2.4 KiB
Diff
From: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Subject: [PATCH] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
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Date: Tue, 3 Oct 2023 17:38:41 +0530
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Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018.
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Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
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---
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.../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 77 +++++++++++++++++++
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1 file changed, 77 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
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diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
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new file mode 100644
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index 000000000000..6b2574f9532e
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
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@@ -0,0 +1,77 @@
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/phy/qcom,ipq5018-uniphy-pcie.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm IPQ5018 UNIPHY PCIe PHY driver
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+
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+maintainers:
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+ - Nitheesh Sekar <quic_nsekar@quicinc.com>
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+ - Sricharan Ramabadhran <quic_srichara@quicinc.com>
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+
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+properties:
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+ compatible:
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+ enum:
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+ - qcom,ipq5018-uniphy-pcie-gen2x1
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+ - qcom,ipq5018-uniphy-pcie-gen2x2
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 1
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+
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+ clock-names:
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+ items:
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+ - const: pipe_clk
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+
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+ resets:
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+ maxItems: 2
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+
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+ reset-names:
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+ items:
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+ - const: phy
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+ - const: phy_phy
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+
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+ "#phy-cells":
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+ const: 0
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+
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+ "#clock-cells":
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+ const: 0
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+
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+ clock-output-names:
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+ maxItems: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - resets
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+ - reset-names
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+ - clocks
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+ - clock-names
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+ - "#phy-cells"
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+ - "#clock-cells"
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+ - clock-output-names
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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+ #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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+
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+ phy@86000 {
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+ compatible = "qcom,ipq5018-uniphy-pcie-gen2x2";
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+ reg = <0x86000 0x800>;
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+ #phy-cells = <0>;
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+ #clock-cells = <0>;
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+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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+ clock-names = "pipe_clk";
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+ clock-output-names = "pcie0_pipe_clk";
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+ assigned-clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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+ assigned-clock-rates = <125000000>;
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+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
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+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
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+ reset-names = "phy", "phy_phy";
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+ };
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