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64 lines
1.7 KiB
Diff
64 lines
1.7 KiB
Diff
From: Devi Priya <quic_devipriy@quicinc.com>
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Date: Thu, 5 Oct 2023 21:35:48 +0530
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Subject: [PATCH] dt-bindings: pwm: add IPQ6018 binding
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DT binding for the PWM block in Qualcomm IPQ6018 SoC.
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Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Co-developed-by: Baruch Siach <baruch.siach@siklu.com>
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Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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---
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diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml
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new file mode 100644
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index 000000000000..6d0d7ed271f7
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml
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@@ -0,0 +1,45 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm IPQ6018 PWM controller
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+
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+maintainers:
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+ - Baruch Siach <baruch@tkos.co.il>
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+
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+properties:
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+ compatible:
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+ const: qcom,ipq6018-pwm
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+
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+ reg:
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+ description: Offset of PWM register in the TCSR block.
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 1
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+
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+ "#pwm-cells":
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+ const: 2
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - "#pwm-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
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+
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+ pwm: pwm@a010 {
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+ compatible = "qcom,ipq6018-pwm";
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+ reg = <0xa010 0x20>;
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+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
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+ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
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+ assigned-clock-rates = <100000000>;
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+ #pwm-cells = <2>;
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+ };
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