mirror of
https://github.com/coolsnowwolf/lede.git
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07fa9114d6
* kernel: bump 5.4 to 5.4.189 Signed-off-by: José Hwong <88561480+JoseCoW@users.noreply.github.com> * kernel: bump 5.4 to 5.4.190 Signed-off-by: José Hwong <88561480+JoseCoW@users.noreply.github.com>
171 lines
5.0 KiB
Diff
171 lines
5.0 KiB
Diff
--- b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -1456,6 +1456,12 @@
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status = "disabled";
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};
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+ nss-gmac-common {
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+ compatible = "qcom,nss-gmac-common";
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+ reg = <0x03000000 0x0000FFFF 0x1bb00000 0x0000FFFF 0x00900000 0x00004000>;
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+ reg-names = "nss_reg_base", "qsgmii_reg_base", "clk_ctl_base";
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+ };
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+
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gmac0: ethernet@37000000 {
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device_type = "network";
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compatible = "qcom,ipq806x-gmac", "snps,dwmac";
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@@ -1556,7 +1562,132 @@
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regulator-always-on;
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};
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- sdcc1bam:dma@12402000 {
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+ nss0: nss@40000000 {
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+ compatible = "qcom,nss";
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+ qcom,low-frequency = <733000000>; /* orig value 110000000 */
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+ qcom,mid-frequency = <733000000>; /* orig value 550000000 */
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+ qcom,max-frequency = <733000000>;
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+
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+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x36000000 0x1000 0x39000000 0x10000>;
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+ reg-names = "nphys", "vphys";
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+ clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK_SRC>,
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+ <&gcc NSSTCM_CLK>, <&rpmcc RPM_NSS_FABRIC_0_CLK>,
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+ <&rpmcc RPM_NSS_FABRIC_1_CLK>;
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+ clock-names = "nss-core-clk", "nss-tcm-src",
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+ "nss-tcm-clk", "nss-fab0-clk",
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+ "nss-fab1-clk";
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+ resets = <&gcc UBI32_CORE1_CLKRST_CLAMP_RESET>,
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+ <&gcc UBI32_CORE1_CLAMP_RESET>,
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+ <&gcc UBI32_CORE1_AHB_RESET>,
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+ <&gcc UBI32_CORE1_AXI_RESET>;
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+ reset-names = "clkrst-clamp", "clamp", "ahb", "axi";
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+
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+ qcom,id = <0>;
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+ qcom,num-irq = <2>;
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+ qcom,num-queue = <2>;
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+ qcom,load-addr = <0x40000000>;
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+ qcom,turbo-frequency;
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+
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+ qcom,bridge-enabled;
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+ qcom,gre-enabled;
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+ qcom,gre-redir-enabled;
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+ qcom,gre_tunnel_enabled;
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+ qcom,ipv4-enabled;
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+ qcom,ipv4-reasm-enabled;
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+ qcom,ipv6-enabled;
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+ qcom,ipv6-reasm-enabled;
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+ qcom,l2tpv2-enabled;
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+ qcom,map-t-enabled;
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+ qcom,pppoe-enabled;
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+ qcom,pptp-enabled;
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+ qcom,portid-enabled;
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+ qcom,shaping-enabled;
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+ qcom,tun6rd-enabled;
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+ qcom,tunipip6-enabled;
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+ qcom,vlan-enabled;
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+ qcom,wlan-dataplane-offload-enabled;
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+ qcom,wlanredirect-enabled;
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+ qcom,pxvlan-enabled;
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+ qcom,vxlan-enabled;
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+ qcom,match-enabled;
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+ qcom,mirror-enabled;
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+ qcom,rmnet-enabled;
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+ qcom,clmap-enabled;
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+ };
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+
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+ nss1: nss@40800000 {
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+ compatible = "qcom,nss";
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+ qcom,low-frequency = <733000000>; /* orig value 110000000 */
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+ qcom,mid-frequency = <733000000>; /* orig value 550000000 */
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+ qcom,max-frequency = <733000000>;
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+
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+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x36400000 0x1000 0x39010000 0x10000>;
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+ reg-names = "nphys", "vphys";
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+ resets = <&gcc UBI32_CORE2_CLKRST_CLAMP_RESET>,
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+ <&gcc UBI32_CORE2_CLAMP_RESET>,
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+ <&gcc UBI32_CORE2_AHB_RESET>,
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+ <&gcc UBI32_CORE2_AXI_RESET>;
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+ reset-names = "clkrst-clamp", "clamp", "ahb", "axi";
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+
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+ qcom,id = <1>;
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+ qcom,num-irq = <2>;
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+ qcom,load-addr = <0x40800000>;
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+ qcom,num-queue = <2>;
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+ qcom,turbo-frequency;
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+
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+ qcom,capwap-enabled;
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+ qcom,crypto-enabled;
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+ qcom,dtls-enabled;
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+ qcom,ipsec-enabled;
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+ };
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+
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+ crypto1: crypto@38000000 {
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+ compatible = "qcom,nss-crypto";
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+ reg = <0x38000000 0x20000>, <0x38004000 0x22000>;
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+ reg-names = "crypto_pbase", "bam_base";
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+ clocks = <&gcc CE5_CORE_CLK>, <&gcc CE5_A_CLK>, <&gcc CE5_H_CLK>;
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+ clock-names = "ce5_core", "ce5_aclk", "ce5_hclk";
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+ resets = <&gcc CRYPTO_ENG1_RESET>, <&gcc CRYPTO_AHB_RESET>;
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+ reset-names = "rst_eng", "rst_ahb";
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+ qcom,id = <0>;
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+ qcom,ee = <0>;
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+ };
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+
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+ crypto2: crypto@38400000 {
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+ compatible = "qcom,nss-crypto";
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+ reg = <0x38400000 0x20000>, <0x38404000 0x22000>;
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+ reg-names = "crypto_pbase", "bam_base";
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+ resets = <&gcc CRYPTO_ENG2_RESET>;
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+ reset-names = "rst_eng";
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+ qcom,id = <1>;
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+ qcom,ee = <0>;
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+ };
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+
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+ crypto3: crypto@38800000 {
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+ compatible = "qcom,nss-crypto";
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+ reg = <0x38800000 0x20000>, <0x38804000 0x22000>;
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+ reg-names = "crypto_pbase", "bam_base";
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+ resets = <&gcc CRYPTO_ENG3_RESET>;
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+ reset-names = "rst_eng";
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+ qcom,id = <2>;
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+ qcom,ee = <0>;
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+ };
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+
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+ crypto4: crypto@38c00000 {
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+ compatible = "qcom,nss-crypto";
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+ reg = <0x38c00000 0x20000>, <0x38c04000 0x22000>;
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+ reg-names = "crypto_pbase", "bam_base";
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+ resets = <&gcc CRYPTO_ENG4_RESET>;
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+ reset-names = "rst_eng";
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+ qcom,id = <3>;
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+ qcom,ee = <0>;
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+ };
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+
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+ sdcc1bam: dma@12402000 {
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12402000 0x8000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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@@ -1622,6 +1753,20 @@
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dma-names = "tx", "rx";
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};
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};
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+
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+ nss-common {
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+ compatible = "qcom,nss-common";
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+ reg = <0x03000000 0x00001000>;
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+ reg-names = "nss_fpb_base";
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+ clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK>,
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+ <&rpmcc RPM_NSS_FABRIC_0_CLK>, <&rpmcc RPM_NSS_FABRIC_1_CLK>;
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+ clock-names = "nss_core_clk", "nss_tcm_clk",
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+ "nss-fab0-clk", "nss-fab1-clk";
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+ nss_core-supply = <&smb208_s1b>;
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+ nss_core_vdd_nominal = <1100000>;
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+ nss_core_vdd_high = <1150000>;
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+ nss_core_threshold_freq = <733000000>;
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+ };
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};
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sfpb_mutex: sfpb-mutex {
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