From 99841b41e13b4a0512de1e06191cdcaf7ee0e1d1 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 13 May 2021 12:42:05 +0200
Subject: [PATCH 3/3] arm64: dts: ipq8074: add APPS CPU clock

In preparation for frequency scaling add the APPS
clock support.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+#include <dt-bindings/clock/qca,apss-ipq8074.h>
 #include <dt-bindings/spmi/spmi.h>
 
 / {
@@ -33,6 +34,8 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x0>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			clock-names = "cpu";
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 		};
@@ -42,6 +45,8 @@
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x1>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			clock-names = "cpu";
 			next-level-cache = <&L2_0>;
 		};
 
@@ -50,6 +55,8 @@
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x2>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			clock-names = "cpu";
 			next-level-cache = <&L2_0>;
 		};
 
@@ -58,6 +65,8 @@
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x3>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			clock-names = "cpu";
 			next-level-cache = <&L2_0>;
 		};
 
@@ -909,8 +918,9 @@
 
 		apcs_glb: mailbox@b111000 {
 			compatible = "qcom,ipq8074-apcs-apps-global";
-			reg = <0x0b111000 0x1000>;
+			reg = <0x0b111000 0x6000>;
 
+			#clock-cells = <1>;
 			#mbox-cells = <1>;
 		};