From 4f579facd45c39f8f8b9993570944f4d83a95955 Mon Sep 17 00:00:00 2001 From: Praveenkumar I Date: Wed, 5 Feb 2020 10:13:01 +0530 Subject: [PATCH 2/8] ipq8074: gcc: Added support for NSS clocks Change-Id: I446e84dbc3498618425677811a73124b99b5c0ad Signed-off-by: Praveenkumar I Signed-off-by: Rajkumar Ayyasamy --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++ drivers/clk/qcom/gcc-ipq8074.c | 68 +++++++++++++++++++- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 3 files changed, 80 insertions(+), 1 deletion(-) --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -1037,5 +1037,17 @@ resets = <&gcc GCC_EDMA_HW_RESET>; reset-names = "edma_rst"; }; + + bias_pll_cc_clk { + compatible = "fixed-clock"; + clock-frequency = <300000000>; + #clock-cells = <0>; + }; + + bias_pll_nss_noc_clk { + compatible = "fixed-clock"; + clock-frequency = <416500000>; + #clock-cells = <0>; + }; }; }; --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref }, }; +static struct clk_branch gcc_crypto_ppe_clk = { + .halt_reg = 0x68310, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x68310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_ppe_clk", + .parent_names = (const char *[]){ + "nss_ppe_clk_src" + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { @@ -4608,6 +4626,7 @@ static struct clk_regmap *gcc_ipq8074_cl [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, + [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -233,6 +233,7 @@ #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 #define GCC_PCIE0_RCHNG_CLK_SRC 225 #define GCC_PCIE0_RCHNG_CLK 226 +#define GCC_CRYPTO_PPE_CLK 227 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1