// SPDX-License-Identifier: (GPL-2.0 OR MIT) /dts-v1/; #include #include "mt7981.dtsi" / { model = "HUASIFEI WS3006"; compatible = "huasifei,ws3006", "mediatek,mt7981"; aliases { label-mac-device = &gmac0; led-boot = &status_led; led-failsafe = &status_led; led-running = &status_led; led-upgrade = &status_led; serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; gpio-keys { compatible = "gpio-keys"; reset { label = "reset"; linux,code = ; gpios = <&pio 1 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; status_led: led-0 { label = "green:status"; gpios = <&pio 0 GPIO_ACTIVE_LOW>; }; led-1 { label = "green:sim1"; gpios = <&pio 6 GPIO_ACTIVE_LOW>; }; led-2 { label = "green:sim2"; gpios = <&pio 7 GPIO_ACTIVE_LOW>; }; led-3 { label = "green:gbe"; gpios = <&pio 8 GPIO_ACTIVE_LOW>; }; led-4 { label = "green:5g"; gpios = <&pio 9 GPIO_ACTIVE_LOW>; }; led-5 { label = "green:wlan"; gpios = <&pio 10 GPIO_ACTIVE_LOW>; }; led-6 { label = "green:4g"; gpios = <&pio 11 GPIO_ACTIVE_LOW>; }; }; }; &uart0 { status = "okay"; }; &watchdog { status = "okay"; }; ð { pinctrl-names = "default"; pinctrl-0 = <&mdio_pins>; status = "okay"; gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "2500base-x"; fixed-link { speed = <2500>; full-duplex; pause; }; }; gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; phy-mode = "2500base-x"; phy-handle = <&phy0>; label = "lan3"; }; }; &mdio_bus { switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&pio>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; }; phy0: ethernet-phy@0 { compatible = "ethernet-phy-id03a2.9461"; reg = <0>; phy-mode = "gmii"; nvmem-cells = <&phy_calibration>; nvmem-cell-names = "phy-cal-data"; }; phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <6>; reset-assert-us = <100000>; reset-deassert-us = <100000>; reset-gpios = <&pio 3 GPIO_ACTIVE_LOW>; }; }; &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_flash_pins>; status = "okay"; spi_nand: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-nand"; reg = <0>; spi-max-frequency = <52000000>; spi-cal-enable; spi-cal-mode = "read-data"; spi-cal-datalen = <7>; spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; spi-cal-addrlen = <5>; spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; mediatek,nmbm; mediatek,bmt-max-ratio = <1>; mediatek,bmt-max-reserved-blocks = <64>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "BL2"; reg = <0x0 0x100000>; /* 1 MiB */ read-only; }; partition@100000 { label = "u-boot-env"; reg = <0x100000 0x80000>; /* 0.5 MiB */ }; factory: partition@180000 { label = "Factory"; reg = <0x180000 0x200000>; /* 2 MiB */ read-only; nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; #size-cells = <1>; eeprom_factory_0: eeprom@0 { reg = <0x0 0x1000>; }; }; }; partition@380000 { label = "FIP"; reg = <0x380000 0x200000>; /* 2 MiB */ }; partition@580000 { label = "ubi"; reg = <0x580000 0x6e00000>; /* 110 MiB */ }; partition@7380000 { label = "config"; reg = <0x7380000 0x80000>; /* 0.5 MiB */ }; /* Leave last 12 MiB for NMBM badblock table */ }; }; }; &pio { spi0_flash_pins: spi0-pins { mux { function = "spi"; groups = "spi0", "spi0_wp_hold"; }; conf-pu { pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; drive-strength = ; bias-pull-up = ; }; conf-pd { pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; drive-strength = ; bias-pull-down = ; }; }; }; &switch { ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@5 { reg = <5>; label = "wan"; phy-mode = "2500base-x"; phy-handle = <&phy1>; }; port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; fixed-link { speed = <2500>; full-duplex; pause; }; }; }; }; &wifi { status = "okay"; nvmem-cells = <&eeprom_factory_0>; nvmem-cell-names = "eeprom"; };