--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -60,6 +60,11 @@ static const struct parent_map gcc_xo_gp
 	{ P_GPLL0_DIV2, 4 },
 };
 
+static const char * const gcc_xo_gpll0[] = {
+	"xo",
+	"gpll0",
+};
+
 static const struct parent_map gcc_xo_gpll0_map[] = {
 	{ P_XO, 0 },
 	{ P_GPLL0, 1 },
@@ -951,11 +956,6 @@ static struct clk_rcg2 blsp1_uart6_apps_
 	},
 };
 
-static const struct clk_parent_data gcc_xo_gpll0[] = {
-	{ .fw_name = "xo" },
-	{ .hw = &gpll0.clkr.hw },
-};
-
 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 	F(19200000, P_XO, 1, 0, 0),
 	F(200000000, P_GPLL0, 4, 0, 0),
@@ -969,7 +969,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
 	.parent_map = gcc_xo_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pcie0_axi_clk_src",
-		.parent_data = gcc_xo_gpll0,
+		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1016,7 +1016,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
 	.parent_map = gcc_xo_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pcie1_axi_clk_src",
-		.parent_data = gcc_xo_gpll0,
+		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1330,7 +1330,7 @@ static struct clk_rcg2 nss_ce_clk_src =
 	.parent_map = gcc_xo_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "nss_ce_clk_src",
-		.parent_data = gcc_xo_gpll0,
+		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -4329,7 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
 	.parent_map = gcc_xo_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pcie0_rchng_clk_src",
-		.parent_data = gcc_xo_gpll0,
+		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -4343,9 +4343,9 @@ static struct clk_branch gcc_pcie0_rchng
 		.enable_mask = BIT(1),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie0_rchng_clk",
-			.parent_hws = (const struct clk_hw *[]){
-				&pcie0_rchng_clk_src.clkr.hw,
-			},
+			.parent_names = (const char *[]){
+				"pcie0_rchng_clk_src",
+		},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -4361,9 +4361,9 @@ static struct clk_branch gcc_pcie0_axi_s
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie0_axi_s_bridge_clk",
-			.parent_hws = (const struct clk_hw *[]){
-				&pcie0_axi_clk_src.clkr.hw,
-			},
+			.parent_names = (const char *[]){
+				"pcie0_axi_clk_src"
+		},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,