From b5a258e564a70e0fed38ada2a03e99688fc38e85 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 6 Jun 2022 23:46:28 +0200 Subject: [PATCH] arm64: dts: qcom: ipq6018: add SDHCI controller node Add the required DT node for SDCC v5 SDHCI controller. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -257,6 +257,32 @@ reg = <0x0 0x01937000 0x0 0x21000>; }; + sdhci: mmc@780400 { + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>, + <0x0 0x07808000 0x0 0x2000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + resets = <&gcc GCC_SDCC1_BCR>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr104; + bus-width = <8>; + vqmmc-supply = <&ipq6018_l2>; + status = "disabled"; + }; + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07884000 0x0 0x2b000>;