Prior to commit 8a7d12d674,
cdc-ethernet USB LTE modems (e.g. Quectel EC200A) were consistently named
usb0. After 8a7d12d67, devices began renaming to eth1 due to an assumption
that local MAC addresses originate exclusively from the kernel. Some
devices provide driver-assigned local MACs, causing point-to-point
interfaces with driver-set MACs to adopt eth%d names instead of usb%d.
Restore the naming exception for point-to-point devices: interfaces
without driver MACs or with driver-provided local MACs will retain the
usb%d convention. This addresses issues reported in [1] and fixed in [2].
[1] https://lore.kernel.org/all/Z00udyMgW6XnAw6h@atmark-techno.com/
[2] https://lore.kernel.org/all/20241203130457.904325-1-asmadeus@codewreck.org/
Tested-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Detect the RTL8367D chip family and set the appropriate extif
Co-authored-by: Serge Vasilugin <vasilugin@yandex.ru>
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Uses upstream DSA switch modules (rtl8365mb, rtl8366), similar to
RTL8367C and rtl8366rb swconfig drivers.
The package dependencies exclude targets built without kernel CONFIG_OF.
It also fixes the rtl8366rb LED support.
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add patch to fix Qcom SNAND driver and move the SNAND patches to
backports directory as they are shared between qualcommax and qualcommbe
target.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Follow the advise of Russell King allows to greatly improve the driver
for RealTek's 1G and 2.5G Ethernet PHYs. The results are full/half
duplex as well as Gbit master/slave property being read from PHY
Specific Status Register (PHYSR), and fixes regarding link-partner
advertisement.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Instead of forcing 2.5G PHYs into rate-adapter mode which results higher
energy consumption, lack of support for half-duplex modes and typically
worse performance when linked at speeds less than 2.5G, use SGMII mode
which allows the MAC to follow the PHY speed.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Backport BLOCK OF support patch merged upstream and refresh pending
BLOCK patches.
This is a new way to declare partition table for BLOCK device (eMMC
currently supported) with the use of DTS.
Current pending patch are adapted to not cause regression with current
downstream implementation of a similar functionality.
Also enable the new OF_PARTITION config by default.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The broadcom PHY driver only has to depend upon PTP_1588_CLOCK_OPTIONAL
if NETWORK_PHY_TIMESTAMPING is enabled. The PTP functionality is stubbed
in this case.
Reflect this circumstance in the dependence condition. This allows to
build the driver as a built-in module even if PTP is built as a module.
This is required to include the broadcom PHY module regardless of the
built-setting of the PTP subsystem. On ath79 (and probably more)
targets with Broadcom PHY, Gigabit operation is currently broken as the
PHY driver is only built as a module in case all kernel-packages are
built. Due to this circumstance, affected devices fall back to using the
generic PHY driver.
Signed-off-by: David Bauer <mail@david-bauer.net>
This backport patch inserted suspend/resume callbacks
for the wrong PHY driver.
Signed-off-by: Marco von Rosenberg <marcovr@selfnet.de>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add support for FORESEE F35SQA001G SPI NAND.
Similar to F35SQA002G, but differs in capacity.
Datasheet:
- https://cdn.ozdisan.com/ETicaret_Dosya/704795_871495.pdf
Tested on Xiaomi AX3000T flashed with OpenWRT.
Signed-off-by: Bohdan Chubuk <chbgdn@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport newly introduced support for 'active-high' property and use
it to correctly implement polarity assignment for Aquantia PHY LEDs.
Previously the 'active-low' property was used to switch a LED PIN to
active-high ("drive VDD" in Aquantia-speak) mode.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
PMD Global Transmit Disable bit should be cleared for normal operation.
This should be HW default, however I found that on Asus RT-AX89X that uses
AQR113C PHY and firmware 5.4 this bit is set by default.
With this bit set the AQR cannot achieve a link with its link-partner and
it took me multiple hours of digging through the vendor GPL source to find
this out, so lets always clear this bit during .config_init() to avoid a
situation like this in the future.
aqr107_wait_processor_intensive_op() is moved up because datasheet notes
that any changes to this bit are processor intensive.
This is a modified version of patch that got merged upstream as AQR113C
has a separate config_init() upstream.
Signed-off-by: Robert Marko <robimarko@gmail.com>
