From f24975f2c5c73afff5f178cc5d3965e131ef8c22 Mon Sep 17 00:00:00 2001 From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> Date: Mon, 31 Oct 2022 23:18:29 +0800 Subject: [PATCH] rockchip: update rk3568 pcie2x1 dts part Fixes: #10626 --- target/linux/rockchip/modules.mk | 2 +- ...ockchip-rk356x-Fix-PCIe-register-map.patch | 40 +++++++++++++++++++ ...ockchip-rk356x-Fix-PCIe-register-map.patch | 40 +++++++++++++++++++ 3 files changed, 81 insertions(+), 1 deletion(-) create mode 100644 target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch create mode 100644 target/linux/rockchip/patches-6.1/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch diff --git a/target/linux/rockchip/modules.mk b/target/linux/rockchip/modules.mk index db17ccf17..2c05c2de7 100644 --- a/target/linux/rockchip/modules.mk +++ b/target/linux/rockchip/modules.mk @@ -6,7 +6,7 @@ define KernelPackage/drm-rockchip SUBMENU:=$(VIDEO_MENU) TITLE:=Rockchip DRM support DEPENDS:=@TARGET_rockchip +kmod-backlight +kmod-drm-kms-helper \ - +kmod-multimedia-input +LINUX_6_0:kmod-drm-display-helper + +kmod-multimedia-input +LINUX_6_1:kmod-drm-display-helper KCONFIG:= \ CONFIG_DRM_ROCKCHIP \ CONFIG_DRM_LOAD_EDID_FIRMWARE=y \ diff --git a/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch b/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch new file mode 100644 index 000000000..8e241308b --- /dev/null +++ b/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch @@ -0,0 +1,40 @@ +From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001 +From: Andrew Powers-Holmes +Date: Sat, 12 Nov 2022 22:41:26 +1100 +Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and + range mappings + +The register and range mappings for the PCIe controller in Rockchip's +RK356x SoCs are incorrect. Replace them with corrected values from the +vendor BSP sources, updated to match current DT schema. + +Tested-by: Ondrej Jirman +Signed-off-by: Andrew Powers-Holmes +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------ + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++--- + 2 files changed, 12 insertions(+), 9 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -707,7 +707,7 @@ pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie"; + reg = <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, +- <0x3 0x3f000000 0x0 0x01000000>; ++ <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + interrupts = , + , +@@ -736,8 +736,9 @@ pcie2x1: pcie@fe260000 { + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; +- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 +- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; ++ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, ++ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, ++ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + #address-cells = <3>; diff --git a/target/linux/rockchip/patches-6.1/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch b/target/linux/rockchip/patches-6.1/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch new file mode 100644 index 000000000..1752b986c --- /dev/null +++ b/target/linux/rockchip/patches-6.1/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch @@ -0,0 +1,40 @@ +From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001 +From: Andrew Powers-Holmes +Date: Sat, 12 Nov 2022 22:41:26 +1100 +Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and + range mappings + +The register and range mappings for the PCIe controller in Rockchip's +RK356x SoCs are incorrect. Replace them with corrected values from the +vendor BSP sources, updated to match current DT schema. + +Tested-by: Ondrej Jirman +Signed-off-by: Andrew Powers-Holmes +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------ + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++--- + 2 files changed, 12 insertions(+), 9 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -951,7 +951,7 @@ pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie"; + reg = <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, +- <0x3 0x3f000000 0x0 0x01000000>; ++ <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + interrupts = , + , +@@ -980,8 +980,9 @@ pcie2x1: pcie@fe260000 { + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; +- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 +- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; ++ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, ++ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, ++ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + #address-cells = <3>;