From ec09753204d7650da308341d5ee1ca959c8af4fc Mon Sep 17 00:00:00 2001 From: coolsnowwolf Date: Wed, 20 Mar 2019 13:52:57 +0800 Subject: [PATCH] kernel: bump to 4.9.163 and 4.14.106 --- include/kernel-version.mk | 8 +- .../patches-4.14/500-MIPS-fw-myloader.patch | 2 +- ...ption-fix-dwm-158-3g-modem-interface.patch | 2 +- ...conntrack-add-IPS_OFFLOAD-status-bit.patch | 6 +- ...w_table-fix-offloaded-connection-tim.patch | 4 +- ...90-net-generalize-napi_complete_done.patch | 4 +- .../pending-4.14/308-mips32r2_tune.patch | 2 +- ...ng-with-source-address-failed-policy.patch | 14 +- .../711-dpaa-bqman-support-layerscape.patch | 4 +- .../807-usb-support-layerscape.patch | 4 +- ...eeprom-ethtool-access-into-netdev-co.patch | 2 +- ...fp-use-netdev-sfp_bus-for-start-stop.patch | 4 +- .../oxnas/base-files/etc/board.d/01_leds | 27 -- target/linux/oxnas/base-files/etc/diag.sh | 41 -- target/linux/oxnas/config-4.14 | 69 ++- .../arm/boot/dts/ox820-akitio-mycloud.dts | 14 +- ...dts => ox820-cloudengines-pogoplugpro.dts} | 38 +- ...stg212.dts => ox820-mitrastar-stg-212.dts} | 34 +- .../arch/arm/boot/dts/ox820-shuttle-kd20.dts | 25 +- .../oxnas/files/drivers/pci/host/pcie-oxnas.c | 456 ++++-------------- .../oxnas/files/drivers/phy/phy-oxnas-pcie.c | 150 ++++++ .../files/drivers/power/reset/oxnas-restart.c | 229 +++++++++ target/linux/oxnas/image/ox820.mk | 48 +- target/linux/oxnas/ox820/target.mk | 4 - .../020-nand-partitions-on-pogoplug-v3.patch | 32 ++ .../030-led-aliases-on-pogoplug-v3.patch | 34 ++ ...-pogoplug-series-3-compatible-string.patch | 11 + .../060-fix-oxnas-rps-dt-match.patch | 8 + .../patches-4.14/150-oxnas-restart.patch | 25 + .../patches-4.14/320-oxnas-phy-pcie.patch | 44 ++ .../oxnas/patches-4.14/340-oxnas-pcie.patch | 170 ++++--- .../oxnas/patches-4.14/500-oxnas-sata.patch | 6 +- .../oxnas/patches-4.14/800-oxnas-ehci.patch | 24 +- ...0031-uvc-add-iPassion-iP2970-support.patch | 2 +- ...-sun8i-Handle-integrated-external-MD.patch | 14 +- ...stmmac-sun8i-Restore-the-compatibles.patch | 2 +- ...-sun8i-fix-allwinner-leds-active-low.patch | 2 +- 37 files changed, 940 insertions(+), 625 deletions(-) delete mode 100755 target/linux/oxnas/base-files/etc/board.d/01_leds delete mode 100644 target/linux/oxnas/base-files/etc/diag.sh rename target/linux/oxnas/files/arch/arm/boot/dts/{ox820-cloudengines-pogoplug-pro.dts => ox820-cloudengines-pogoplugpro.dts} (72%) rename target/linux/oxnas/files/arch/arm/boot/dts/{ox820-mitrastar-stg212.dts => ox820-mitrastar-stg-212.dts} (73%) create mode 100644 target/linux/oxnas/files/drivers/phy/phy-oxnas-pcie.c create mode 100644 target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c create mode 100644 target/linux/oxnas/patches-4.14/020-nand-partitions-on-pogoplug-v3.patch create mode 100644 target/linux/oxnas/patches-4.14/030-led-aliases-on-pogoplug-v3.patch create mode 100644 target/linux/oxnas/patches-4.14/040-pogoplug-series-3-compatible-string.patch create mode 100644 target/linux/oxnas/patches-4.14/060-fix-oxnas-rps-dt-match.patch create mode 100644 target/linux/oxnas/patches-4.14/150-oxnas-restart.patch create mode 100644 target/linux/oxnas/patches-4.14/320-oxnas-phy-pcie.patch diff --git a/include/kernel-version.mk b/include/kernel-version.mk index f5cf3500b..9ea94a840 100644 --- a/include/kernel-version.mk +++ b/include/kernel-version.mk @@ -3,13 +3,13 @@ LINUX_RELEASE?=1 LINUX_VERSION-3.18 = .136 -LINUX_VERSION-4.9 = .161 -LINUX_VERSION-4.14 = .104 +LINUX_VERSION-4.9 = .163 +LINUX_VERSION-4.14 = .106 LINUX_VERSION-4.19 = .25 LINUX_KERNEL_HASH-3.18.136 = 48c8775013d23229462134f911bbb14c7935096fcccfb19ce28ecd5f7154f35c -LINUX_KERNEL_HASH-4.9.161 = e11e830b7e55f9eac768bf3c7617a15da22819552595fe786a1fb20bfa8b28a6 -LINUX_KERNEL_HASH-4.14.104 = dd430e3e65138da5799b5ff7353e1a9c72f2f9dc957ac53d2aea3dd8ca7be067 +LINUX_KERNEL_HASH-4.9.163 = c27cf9962c17b91275ab9e74b43c1269f726f79e7a85421be7c5c73d267eef91 +LINUX_KERNEL_HASH-4.14.106 = a0e2af6add699d86cf15e1ee31ad408aa28dbab82f4462450eba51f90e7d2760 LINUX_KERNEL_HASH-4.19.25 = 7ec71d90d6e96e6f741676d157ac06f30c75be4eaf1649143a3c8b7d4f919731 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1)))) diff --git a/target/linux/ar71xx/patches-4.14/500-MIPS-fw-myloader.patch b/target/linux/ar71xx/patches-4.14/500-MIPS-fw-myloader.patch index 0797bf7ba..f22806abc 100644 --- a/target/linux/ar71xx/patches-4.14/500-MIPS-fw-myloader.patch +++ b/target/linux/ar71xx/patches-4.14/500-MIPS-fw-myloader.patch @@ -1,6 +1,6 @@ --- a/arch/mips/Makefile +++ b/arch/mips/Makefile -@@ -223,6 +223,7 @@ cflags-$(toolchain-virt) += -DTOOLCHAIN +@@ -228,6 +228,7 @@ cflags-$(toolchain-virt) += -DTOOLCHAIN # libs-$(CONFIG_FW_ARC) += arch/mips/fw/arc/ libs-$(CONFIG_FW_CFE) += arch/mips/fw/cfe/ diff --git a/target/linux/generic/backport-4.14/030-USB-serial-option-fix-dwm-158-3g-modem-interface.patch b/target/linux/generic/backport-4.14/030-USB-serial-option-fix-dwm-158-3g-modem-interface.patch index 93ca8331e..9f07fddc6 100644 --- a/target/linux/generic/backport-4.14/030-USB-serial-option-fix-dwm-158-3g-modem-interface.patch +++ b/target/linux/generic/backport-4.14/030-USB-serial-option-fix-dwm-158-3g-modem-interface.patch @@ -30,7 +30,7 @@ Signed-off-by: Johan Hovold --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c -@@ -1934,7 +1934,8 @@ static const struct usb_device_id option +@@ -1936,7 +1936,8 @@ static const struct usb_device_id option { USB_DEVICE_INTERFACE_CLASS(0x2001, 0x7d01, 0xff) }, /* D-Link DWM-156 (variant) */ { USB_DEVICE_INTERFACE_CLASS(0x2001, 0x7d02, 0xff) }, { USB_DEVICE_INTERFACE_CLASS(0x2001, 0x7d03, 0xff) }, diff --git a/target/linux/generic/backport-4.14/320-v4.16-netfilter-nf_conntrack-add-IPS_OFFLOAD-status-bit.patch b/target/linux/generic/backport-4.14/320-v4.16-netfilter-nf_conntrack-add-IPS_OFFLOAD-status-bit.patch index 7788dd143..00303f90a 100644 --- a/target/linux/generic/backport-4.14/320-v4.16-netfilter-nf_conntrack-add-IPS_OFFLOAD-status-bit.patch +++ b/target/linux/generic/backport-4.14/320-v4.16-netfilter-nf_conntrack-add-IPS_OFFLOAD-status-bit.patch @@ -47,7 +47,7 @@ Signed-off-by: Pablo Neira Ayuso }; --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c -@@ -901,6 +901,9 @@ static unsigned int early_drop_list(stru +@@ -917,6 +917,9 @@ static unsigned int early_drop_list(stru hlist_nulls_for_each_entry_rcu(h, n, head, hnnode) { tmp = nf_ct_tuplehash_to_ctrack(h); @@ -57,7 +57,7 @@ Signed-off-by: Pablo Neira Ayuso if (nf_ct_is_expired(tmp)) { nf_ct_gc_expired(tmp); continue; -@@ -978,6 +981,18 @@ static bool gc_worker_can_early_drop(con +@@ -994,6 +997,18 @@ static bool gc_worker_can_early_drop(con return false; } @@ -76,7 +76,7 @@ Signed-off-by: Pablo Neira Ayuso static void gc_worker(struct work_struct *work) { unsigned int min_interval = max(HZ / GC_MAX_BUCKETS_DIV, 1u); -@@ -1014,6 +1029,11 @@ static void gc_worker(struct work_struct +@@ -1030,6 +1045,11 @@ static void gc_worker(struct work_struct tmp = nf_ct_tuplehash_to_ctrack(h); scanned++; diff --git a/target/linux/generic/backport-4.14/370-netfilter-nf_flow_table-fix-offloaded-connection-tim.patch b/target/linux/generic/backport-4.14/370-netfilter-nf_flow_table-fix-offloaded-connection-tim.patch index e17b4b620..166b7219d 100644 --- a/target/linux/generic/backport-4.14/370-netfilter-nf_flow_table-fix-offloaded-connection-tim.patch +++ b/target/linux/generic/backport-4.14/370-netfilter-nf_flow_table-fix-offloaded-connection-tim.patch @@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c -@@ -981,18 +981,6 @@ static bool gc_worker_can_early_drop(con +@@ -997,18 +997,6 @@ static bool gc_worker_can_early_drop(con return false; } @@ -40,7 +40,7 @@ Signed-off-by: Felix Fietkau static void gc_worker(struct work_struct *work) { unsigned int min_interval = max(HZ / GC_MAX_BUCKETS_DIV, 1u); -@@ -1029,10 +1017,8 @@ static void gc_worker(struct work_struct +@@ -1045,10 +1033,8 @@ static void gc_worker(struct work_struct tmp = nf_ct_tuplehash_to_ctrack(h); scanned++; diff --git a/target/linux/generic/backport-4.9/090-net-generalize-napi_complete_done.patch b/target/linux/generic/backport-4.9/090-net-generalize-napi_complete_done.patch index dc409ea06..dc97edfdc 100644 --- a/target/linux/generic/backport-4.9/090-net-generalize-napi_complete_done.patch +++ b/target/linux/generic/backport-4.9/090-net-generalize-napi_complete_done.patch @@ -399,7 +399,7 @@ Signed-off-by: David S. Miller /* bnx2x_has_rx_work() reads the status block, --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c -@@ -1781,7 +1781,7 @@ static int bnxt_poll_nitroa0(struct napi +@@ -1787,7 +1787,7 @@ static int bnxt_poll_nitroa0(struct napi } if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { @@ -701,7 +701,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/ibm/ibmveth.c +++ b/drivers/net/ethernet/ibm/ibmveth.c -@@ -1324,7 +1324,7 @@ restart_poll: +@@ -1323,7 +1323,7 @@ static int ibmveth_poll(struct napi_stru ibmveth_replenish_task(adapter); if (frames_processed < budget) { diff --git a/target/linux/generic/pending-4.14/308-mips32r2_tune.patch b/target/linux/generic/pending-4.14/308-mips32r2_tune.patch index 39167bf4a..a67306031 100644 --- a/target/linux/generic/pending-4.14/308-mips32r2_tune.patch +++ b/target/linux/generic/pending-4.14/308-mips32r2_tune.patch @@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau --- a/arch/mips/Makefile +++ b/arch/mips/Makefile -@@ -161,7 +161,7 @@ cflags-$(CONFIG_CPU_VR41XX) += -march=r4 +@@ -166,7 +166,7 @@ cflags-$(CONFIG_CPU_VR41XX) += -march=r4 cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap diff --git a/target/linux/generic/pending-4.14/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-4.14/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch index 03bb75561..e4fdd6c58 100644 --- a/target/linux/generic/pending-4.14/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch +++ b/target/linux/generic/pending-4.14/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch @@ -181,7 +181,7 @@ Signed-off-by: Jonas Gorski cfg->fc_flags |= RTF_REJECT; if (rtm->rtm_type == RTN_LOCAL) -@@ -3502,6 +3536,9 @@ static int rt6_fill_node(struct net *net +@@ -3506,6 +3540,9 @@ static int rt6_fill_node(struct net *net case -EACCES: rtm->rtm_type = RTN_PROHIBIT; break; @@ -191,7 +191,7 @@ Signed-off-by: Jonas Gorski case -EAGAIN: rtm->rtm_type = RTN_THROW; break; -@@ -3820,6 +3857,8 @@ static int ip6_route_dev_notify(struct n +@@ -3824,6 +3861,8 @@ static int ip6_route_dev_notify(struct n #ifdef CONFIG_IPV6_MULTIPLE_TABLES net->ipv6.ip6_prohibit_entry->dst.dev = dev; net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev); @@ -200,7 +200,7 @@ Signed-off-by: Jonas Gorski net->ipv6.ip6_blk_hole_entry->dst.dev = dev; net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev); #endif -@@ -3831,6 +3870,7 @@ static int ip6_route_dev_notify(struct n +@@ -3835,6 +3874,7 @@ static int ip6_route_dev_notify(struct n in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev); #ifdef CONFIG_IPV6_MULTIPLE_TABLES in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev); @@ -208,7 +208,7 @@ Signed-off-by: Jonas Gorski in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev); #endif } -@@ -4047,6 +4087,17 @@ static int __net_init ip6_route_net_init +@@ -4051,6 +4091,17 @@ static int __net_init ip6_route_net_init net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops; dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst, ip6_template_metrics, true); @@ -226,7 +226,7 @@ Signed-off-by: Jonas Gorski #endif net->ipv6.sysctl.flush_delay = 0; -@@ -4065,6 +4116,8 @@ out: +@@ -4069,6 +4120,8 @@ out: return ret; #ifdef CONFIG_IPV6_MULTIPLE_TABLES @@ -235,7 +235,7 @@ Signed-off-by: Jonas Gorski out_ip6_prohibit_entry: kfree(net->ipv6.ip6_prohibit_entry); out_ip6_null_entry: -@@ -4082,6 +4135,7 @@ static void __net_exit ip6_route_net_exi +@@ -4086,6 +4139,7 @@ static void __net_exit ip6_route_net_exi #ifdef CONFIG_IPV6_MULTIPLE_TABLES kfree(net->ipv6.ip6_prohibit_entry); kfree(net->ipv6.ip6_blk_hole_entry); @@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski #endif dst_entries_destroy(&net->ipv6.ip6_dst_ops); } -@@ -4155,6 +4209,9 @@ void __init ip6_route_init_special_entri +@@ -4159,6 +4213,9 @@ void __init ip6_route_init_special_entri init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev; init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); diff --git a/target/linux/layerscape/patches-4.14/711-dpaa-bqman-support-layerscape.patch b/target/linux/layerscape/patches-4.14/711-dpaa-bqman-support-layerscape.patch index 89ace283b..7946d3cbc 100644 --- a/target/linux/layerscape/patches-4.14/711-dpaa-bqman-support-layerscape.patch +++ b/target/linux/layerscape/patches-4.14/711-dpaa-bqman-support-layerscape.patch @@ -270,7 +270,7 @@ Signed-off-by: Biwen Li } static inline int fq_isset(struct qman_fq *fq, u32 mask) -@@ -1566,7 +1604,7 @@ void qman_p_irqsource_add(struct qman_po +@@ -1567,7 +1605,7 @@ void qman_p_irqsource_add(struct qman_po unsigned long irqflags; local_irq_save(irqflags); @@ -279,7 +279,7 @@ Signed-off-by: Biwen Li qm_out(&p->p, QM_REG_IER, p->irq_sources); local_irq_restore(irqflags); } -@@ -1589,7 +1627,7 @@ void qman_p_irqsource_remove(struct qman +@@ -1590,7 +1628,7 @@ void qman_p_irqsource_remove(struct qman */ local_irq_save(irqflags); bits &= QM_PIRQ_VISIBLE; diff --git a/target/linux/layerscape/patches-4.14/807-usb-support-layerscape.patch b/target/linux/layerscape/patches-4.14/807-usb-support-layerscape.patch index 57df1c8b1..35fa2545e 100644 --- a/target/linux/layerscape/patches-4.14/807-usb-support-layerscape.patch +++ b/target/linux/layerscape/patches-4.14/807-usb-support-layerscape.patch @@ -432,7 +432,7 @@ Signed-off-by: Yangbo Lu reg &= ~DWC3_DCTL_INITU2ENA; --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c -@@ -3209,6 +3209,7 @@ int dwc3_gadget_init(struct dwc3 *dwc) +@@ -3210,6 +3210,7 @@ int dwc3_gadget_init(struct dwc3 *dwc) { int ret; int irq; @@ -440,7 +440,7 @@ Signed-off-by: Yangbo Lu irq = dwc3_gadget_get_irq(dwc); if (irq < 0) { -@@ -3285,6 +3286,12 @@ int dwc3_gadget_init(struct dwc3 *dwc) +@@ -3286,6 +3287,12 @@ int dwc3_gadget_init(struct dwc3 *dwc) goto err4; } diff --git a/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch b/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch index f5506a8bd..540ef51ba 100644 --- a/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch +++ b/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch @@ -49,7 +49,7 @@ Signed-off-by: Russell King }; --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -1054,34 +1054,6 @@ int phylink_ethtool_set_pauseparam(struc +@@ -1058,34 +1058,6 @@ int phylink_ethtool_set_pauseparam(struc } EXPORT_SYMBOL_GPL(phylink_ethtool_set_pauseparam); diff --git a/target/linux/mvebu/patches-4.14/409-sfp-use-netdev-sfp_bus-for-start-stop.patch b/target/linux/mvebu/patches-4.14/409-sfp-use-netdev-sfp_bus-for-start-stop.patch index c2cf55428..4db3867c4 100644 --- a/target/linux/mvebu/patches-4.14/409-sfp-use-netdev-sfp_bus-for-start-stop.patch +++ b/target/linux/mvebu/patches-4.14/409-sfp-use-netdev-sfp_bus-for-start-stop.patch @@ -10,7 +10,7 @@ Signed-off-by: Russell King --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -771,8 +771,8 @@ void phylink_start(struct phylink *pl) +@@ -775,8 +775,8 @@ void phylink_start(struct phylink *pl) clear_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); phylink_run_resolve(pl); @@ -21,7 +21,7 @@ Signed-off-by: Russell King if (pl->phydev) phy_start(pl->phydev); } -@@ -784,8 +784,8 @@ void phylink_stop(struct phylink *pl) +@@ -788,8 +788,8 @@ void phylink_stop(struct phylink *pl) if (pl->phydev) phy_stop(pl->phydev); diff --git a/target/linux/oxnas/base-files/etc/board.d/01_leds b/target/linux/oxnas/base-files/etc/board.d/01_leds deleted file mode 100755 index 66a24e108..000000000 --- a/target/linux/oxnas/base-files/etc/board.d/01_leds +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/sh - -. /lib/functions/uci-defaults.sh - -board=$(board_name) -board_config_update - -case $board in - "akitio,myloud") - ucidef_set_led_default "status" "status" "akitio:red:status" "0" - ;; - "mitrastar,stg-212") - ucidef_set_led_default "power" "power" "zyxel:blue:status" "1" - ucidef_set_led_usbdev "usb" "USB" "zyxel:orange:copy" "1-1" - ;; - "shuttle,kd20") - ucidef_set_led_default "power" "power" "kd20:blue:status" "1" - ;; - "cloudengines,pogoplug"*) - ucidef_set_led_default "power" "power" "pogoplug:blue:internal" "1" - ;; - -esac - -board_config_flush - -exit 0 diff --git a/target/linux/oxnas/base-files/etc/diag.sh b/target/linux/oxnas/base-files/etc/diag.sh deleted file mode 100644 index b8a51c276..000000000 --- a/target/linux/oxnas/base-files/etc/diag.sh +++ /dev/null @@ -1,41 +0,0 @@ -#!/bin/sh -# Copyright (C) 2009-2013 OpenWrt.org - -. /lib/functions.sh -. /lib/functions/leds.sh - -get_status_led() { - case $(board_name) in - "akitio,mycloud") - status_led="akitio:red:status" - ;; - "mitrastar,stg-212") - status_led="zyxel:blue:status" - ;; - "shuttle,kd20") - status_led="kd20:blue:status" - ;; - "cloudengines,pogoplug"*) - status_led="pogoplug:blue:internal" - ;; - esac -} - -set_state() { - get_status_led - - case "$1" in - preinit) - status_led_blink_preinit - ;; - failsafe) - status_led_blink_failsafe - ;; - preinit_regular) - status_led_blink_preinit_regular - ;; - done) - status_led_on - ;; - esac -} diff --git a/target/linux/oxnas/config-4.14 b/target/linux/oxnas/config-4.14 index 40a0fcf12..5ff868ad8 100644 --- a/target/linux/oxnas/config-4.14 +++ b/target/linux/oxnas/config-4.14 @@ -12,6 +12,11 @@ CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_CPU_AUTO=y +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y CONFIG_ARCH_NR_GPIO=0 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y # CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set @@ -25,13 +30,13 @@ CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_LIBATA_LEDS=y CONFIG_ARM=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPUIDLE=y CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARM_HAS_SG_CHAIN=y CONFIG_ARM_L1_CACHE_SHIFT=5 @@ -43,7 +48,6 @@ CONFIG_ARM_TIMER_SP804=y CONFIG_ARM_UNWIND=y CONFIG_ATAGS=y CONFIG_AUTO_ZRELADDR=y -CONFIG_BINARY_PRINTF=y CONFIG_BLK_CMDLINE_PARSER=y CONFIG_BLK_DEBUG_FS=y CONFIG_BLK_DEV_BSG=y @@ -51,9 +55,9 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_BLK_MQ_PCI=y CONFIG_BLK_SCSI_REQUEST=y # CONFIG_BPF_SYSCALL is not set +# CONFIG_CACHE_L2X0 is not set CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y @@ -71,16 +75,34 @@ CONFIG_CMDLINE_PARTITION=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_OXNAS=y CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_COREDUMP=y CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_ARM926T=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y CONFIG_CRASH_CORE=y CONFIG_CRC16=y # CONFIG_CRC32_SARWATE is not set CONFIG_CRC32_SLICEBY8=y CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set # CONFIG_DEBUG_USER is not set CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_GZIP=y @@ -96,17 +118,19 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DMA_CMA=y CONFIG_DNOTIFY=y CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y CONFIG_DUMMY_CONSOLE=y # CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_OXNAS=y -CONFIG_EARLY_PRINTK=y -# CONFIG_EDAC_SUPPORT is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y CONFIG_ELF_CORE=y +CONFIG_FAT_FS=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FREEZER=y CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CPU_AUTOPROBE=y @@ -115,15 +139,12 @@ CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_GENERIC_IO=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PINCONF=y CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GLOB=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_GPIO_GENERIC=y @@ -158,7 +179,6 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MEMBLOCK=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y @@ -195,11 +215,9 @@ CONFIG_IOMMU_SUPPORT=y CONFIG_IOSCHED_CFQ=y CONFIG_IRQCHIP=y CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_WORK=y # CONFIG_ISDN is not set -CONFIG_JBD2=y # CONFIG_JFFS2_FS is not set CONFIG_KALLSYMS=y CONFIG_KERNEL_GZIP=y @@ -218,35 +236,34 @@ CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LIBFDT=y CONFIG_LOCALVERSION_AUTO=y CONFIG_LZ4_DECOMPRESS=y -CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y +# CONFIG_MACH_OX810SE is not set CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MEMORY_ISOLATION=y CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_PCI=y CONFIG_MIGRATION=y CONFIG_MODULES_TREE_LOOKUP=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MULTI_IRQ_HANDLER=y CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NLS=y -CONFIG_NOP_TRACER=y CONFIG_NO_BOOTMEM=y CONFIG_NO_HZ=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y CONFIG_OF=y CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_FLATTREE=y CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_MDIO=y CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y CONFIG_OF_RESERVED_MEM=y CONFIG_OLD_SIGACTION=y CONFIG_OLD_SIGSUSPEND3=y @@ -255,10 +272,14 @@ CONFIG_PAGE_OFFSET=0xC0000000 # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set CONFIG_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y +CONFIG_GENERIC_PHY=y +CONFIG_PHY_OXNAS=y CONFIG_PINCTRL=y CONFIG_PINCTRL_OXNAS=y # CONFIG_PINCTRL_SINGLE is not set @@ -266,11 +287,14 @@ CONFIG_PM=y CONFIG_PM_CLK=y # CONFIG_PM_DEBUG is not set CONFIG_PM_SLEEP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_OXNAS=y CONFIG_PPS=y -CONFIG_PROBE_EVENTS=y CONFIG_PTP_1588_CLOCK=y CONFIG_RAS=y CONFIG_RATIONAL=y +# CONFIG_RCU_NEED_SEGCBLIST is not set +# CONFIG_RCU_STALL_COMMON is not set CONFIG_RCU_TRACE=y CONFIG_RD_BZIP2=y CONFIG_RD_GZIP=y @@ -283,7 +307,6 @@ CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_OXNAS=y -CONFIG_RING_BUFFER=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_SCHED_DEBUG=y # CONFIG_SCHED_INFO is not set @@ -300,6 +323,7 @@ CONFIG_SIMPLE_PM_BUS=y CONFIG_SLUB_DEBUG=y CONFIG_SOCK_DIAG=y CONFIG_SPARSE_IRQ=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 CONFIG_SRCU=y CONFIG_STACKTRACE=y # CONFIG_STAGING is not set @@ -314,10 +338,10 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_TRACE_CLOCK=y CONFIG_UEVENT_HELPER_PATH="" CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UPROBES=y -CONFIG_UPROBE_EVENTS=y CONFIG_USB_SUPPORT=y # CONFIG_USERIO is not set CONFIG_USE_OF=y @@ -342,5 +366,4 @@ CONFIG_XZ_DEC_SPARC=y CONFIG_XZ_DEC_X86=y CONFIG_ZBOOT_ROM_BSS=0 CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts index 90ea15d40..c626e5789 100644 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts @@ -23,6 +23,10 @@ serial0 = &uart0; gpio0 = &gpio0; gpio1 = &gpio1; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; }; i2c-gpio { @@ -39,7 +43,7 @@ }; }; - gpio-keys-polled { + keys { compatible = "gpio-keys-polled"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_buttons>; @@ -58,11 +62,11 @@ }; }; - gpio-leds { + leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds>; - status { + led_status: status { label = "akitio:red:status"; gpios = <&gpio0 29 0>; }; @@ -152,6 +156,10 @@ nr-ports = <2>; }; +&pcie_phy { + status = "okay"; +}; + &pcie0 { status = "okay"; }; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplugpro.dts similarity index 72% rename from target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts rename to target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplugpro.dts index 2872d40e3..6f10a9406 100644 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplugpro.dts @@ -28,24 +28,28 @@ serial0 = &uart0; gpio0 = &gpio0; gpio1 = &gpio1; + led-boot = &led_status; + led-failsafe = &led_warn; + led-running = &led_act; + led-upgrade = &led_warn; }; leds { compatible = "gpio-leds"; - blue { + led_status: blue { label = "pogoplug:blue"; gpios = <&gpio0 2 0>; default-state = "keep"; }; - orange { + led_warn: orange { label = "pogoplug:orange"; gpios = <&gpio1 16 1>; default-state = "keep"; }; - green { + led_act: green { label = "pogoplug:green"; gpios = <&gpio1 17 1>; default-state = "keep"; @@ -74,11 +78,27 @@ nand-ecc-algo = "hamming"; partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; + label = "stage1"; + reg = <0x00000000 0x00040000>; read-only; }; + partition@40000 { + label = "u-boot"; + reg = <0x00040000 0x00380000>; + read-only; + }; + + partition@3c0000 { + label = "u-boot-env"; + reg = <0x003c0000 0x00080000>; + }; + + partition@440000 { + label = "kernel"; + reg = <0x00440000 0x009c0000>; + }; + partition@e00000 { label = "ubi"; reg = <0x00e00000 0x07200000>; @@ -86,6 +106,10 @@ }; }; +&ehci { + status = "okay"; +}; + ða { status = "okay"; @@ -93,6 +117,10 @@ pinctrl-0 = <&pinctrl_etha_mdio>; }; +&pcie_phy { + status = "okay"; +}; + &pcie0 { status = "okay"; }; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg212.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg-212.dts similarity index 73% rename from target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg212.dts rename to target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg-212.dts index c1cb1ef97..4610aab88 100644 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg212.dts +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg-212.dts @@ -23,9 +23,13 @@ serial0 = &uart0; gpio0 = &gpio0; gpio1 = &gpio1; + led-boot = &led_status; + led-failsafe = &led_warn; + led-running = &led_status; + led-upgrade = &led_warn; }; - gpio-keys-polled { + keys { compatible = "gpio-keys-polled"; #address-cells = <1>; #size-cells = <0>; @@ -43,19 +47,21 @@ }; }; - gpio-leds { + leds { compatible = "gpio-leds"; - status { + led_status: status { label = "zyxel:blue:status"; gpios = <&gpio1 5 0>; }; - status2 { + led_warn: status2 { label = "zyxel:red:status"; gpios = <&gpio1 6 1>; }; copy { label = "zyxel:orange:copy"; gpios = <&gpio1 8 1>; + trigger-sources = <&ehci_port1>, <&ehci_port2>; + linux,default-trigger = "usbport"; }; }; @@ -87,11 +93,27 @@ nand-ecc-algo = "hamming"; partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; + label = "stage1"; + reg = <0x00000000 0x00040000>; read-only; }; + partition@40000 { + label = "u-boot"; + reg = <0x00040000 0x00380000>; + read-only; + }; + + partition@3c0000 { + label = "u-boot-env"; + reg = <0x003c0000 0x00080000>; + }; + + partition@440000 { + label = "kernel"; + reg = <0x00440000 0x009c0000>; + }; + partition@e00000 { label = "ubi"; reg = <0x00e00000 0x07200000>; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts index 9186d0858..a8a2ec3bc 100644 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts @@ -23,6 +23,10 @@ serial0 = &uart0; gpio0 = &gpio0; gpio1 = &gpio1; + led-boot = &led_status; + led-failsafe = &led_warn; + led-running = &led_status; + led-upgrade = &led_warn; }; i2c-gpio { @@ -37,7 +41,7 @@ }; }; - gpio-keys-polled { + keys { compatible = "gpio-keys-polled"; #address-cells = <1>; #size-cells = <0>; @@ -65,13 +69,13 @@ }; }; - gpio-leds { + leds { compatible = "gpio-leds"; - status { + led_status: status { label = "kd20:blue:status"; gpios = <&gpio1 16 0>; }; - status2 { + led_warn: status2 { label = "kd20:red:status"; gpios = <&gpio1 17 0>; }; @@ -96,6 +100,8 @@ usb { label = "kd20:blue:usb"; gpios = <&gpio1 8 0>; + trigger-sources = <&ehci_port1>, <&ehci_port2>; + linux,default-trigger = "usbport"; }; }; @@ -145,10 +151,15 @@ partition@40000 { label = "u-boot"; - reg = <0x00040000 0x00200000>; + reg = <0x00040000 0x001e0000>; read-only; }; + partition@220000 { + label = "u-boot-env"; + reg = <0x00220000 0x00020000>; + }; + partition@240000 { label = "initrd"; reg = <0x00240000 0x00600000>; @@ -182,6 +193,10 @@ nr-ports = <2>; }; +&pcie_phy { + status = "okay"; +}; + &pcie0 { status = "okay"; }; diff --git a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c index 7cf3ad167..1dd13f936 100644 --- a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c +++ b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c @@ -1,6 +1,8 @@ /* * PCIe driver for PLX NAS782X SoCs * + * Author: Ma Haijun + * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. @@ -11,263 +13,26 @@ #include #include #include +#include #include #include #include -#include -#include -#include +#include #include +#include +#include +#include #include #include #include +#include +#include +#include #include #include #include -#define OXNAS_UART1_BASE 0x44200000 -#define OXNAS_UART1_SIZE SZ_32 -#define OXNAS_UART1_BASE_VA 0xF0000000 - -#define OXNAS_UART2_BASE 0x44300000 -#define OXNAS_UART2_SIZE SZ_32 - -#define OXNAS_PERCPU_BASE 0x47000000 -#define OXNAS_PERCPU_SIZE SZ_8K -#define OXNAS_PERCPU_BASE_VA 0xF0002000 - -#define OXNAS_SYSCRTL_BASE 0x44E00000 -#define OXNAS_SYSCRTL_SIZE SZ_4K -#define OXNAS_SYSCRTL_BASE_VA 0xF0004000 - -#define OXNAS_SECCRTL_BASE 0x44F00000 -#define OXNAS_SECCRTL_SIZE SZ_4K -#define OXNAS_SECCRTL_BASE_VA 0xF0005000 - -#define OXNAS_RPSA_BASE 0x44400000 -#define OXNAS_RPSA_SIZE SZ_4K -#define OXNAS_RPSA_BASE_VA 0xF0006000 - -#define OXNAS_RPSC_BASE 0x44500000 -#define OXNAS_RPSC_SIZE SZ_4K -#define OXNAS_RPSC_BASE_VA 0xF0007000 - - -/* - * Location of flags and vectors in SRAM for controlling the booting of the - * secondary ARM11 processors. - */ - -#define OXNAS_SCU_BASE_VA OXNAS_PERCPU_BASE_VA -#define OXNAS_GICN_BASE_VA(n) (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100) - -#define HOLDINGPEN_CPU IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) -#define HOLDINGPEN_LOCATION IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) - -/** - * System block reset and clock control - */ -#define SYS_CTRL_PCI_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20) -#define SYSCTRL_CLK_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24) -#define SYS_CTRL_CLK_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C) -#define SYS_CTRL_CLK_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30) -#define SYS_CTRL_RST_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34) -#define SYS_CTRL_RST_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38) - -#define SYS_CTRL_PLLSYS_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48) -#define SYS_CTRL_CLK_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64) -#define SYS_CTRL_PLLSYS_KEY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C) -#define SYS_CTRL_GMAC_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78) -#define SYS_CTRL_GMAC_DELAY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100) - -/* Scratch registers */ -#define SYS_CTRL_SCRATCHWORD0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) -#define SYS_CTRL_SCRATCHWORD1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) -#define SYS_CTRL_SCRATCHWORD2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc) -#define SYS_CTRL_SCRATCHWORD3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0) - -#define SYS_CTRL_PLLA_CTRL0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0) -#define SYS_CTRL_PLLA_CTRL1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4) -#define SYS_CTRL_PLLA_CTRL2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8) -#define SYS_CTRL_PLLA_CTRL3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC) - -#define SYS_CTRL_USBHSMPH_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40) -#define SYS_CTRL_USBHSMPH_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44) -#define SYS_CTRL_REF300_DIV IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8) -#define SYS_CTRL_USBHSPHY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84) -#define SYS_CTRL_USB_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90) - -/* pcie */ -#define SYS_CTRL_HCSL_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114) - -/* System control multi-function pin function selection */ -#define SYS_CTRL_SECONDARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14) -#define SYS_CTRL_TERTIARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c) -#define SYS_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94) -#define SYS_CTRL_DEBUG_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c) -#define SYS_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4) -#define SYS_CTRL_PULLUP_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac) - -/* Secure control multi-function pin function selection */ -#define SEC_CTRL_SECONDARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14) -#define SEC_CTRL_TERTIARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c) -#define SEC_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94) -#define SEC_CTRL_DEBUG_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c) -#define SEC_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4) -#define SEC_CTRL_PULLUP_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac) - -#define SEC_CTRL_COPRO_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68) -#define SEC_CTRL_SECURE_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98) -#define SEC_CTRL_LEON_DEBUG IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0) -#define SEC_CTRL_PLLB_DIV_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8) -#define SEC_CTRL_PLLB_CTRL0 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0) -#define SEC_CTRL_PLLB_CTRL1 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) -#define SEC_CTRL_PLLB_CTRL8 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) - -#define RPSA_IRQ_SOFT IOMEM(OXNAS_RPSA_BASE_VA + 0x10) -#define RPSA_FIQ_ENABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x108) -#define RPSA_FIQ_DISABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x10C) -#define RPSA_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC) - -#define RPSC_IRQ_SOFT IOMEM(OXNAS_RPSC_BASE_VA + 0x10) -#define RPSC_FIQ_ENABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x108) -#define RPSC_FIQ_DISABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x10C) -#define RPSC_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC) - -#define RPSA_TIMER2_VAL IOMEM(OXNAS_RPSA_BASE_VA + 0x224) - -#define REF300_DIV_INT_SHIFT 8 -#define REF300_DIV_FRAC_SHIFT 0 -#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) -#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) - -#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16 -#define USBHSPHY_SUSPENDM_MANUAL_STATE 15 -#define USBHSPHY_ATE_ESET 14 -#define USBHSPHY_TEST_DIN 6 -#define USBHSPHY_TEST_ADD 2 -#define USBHSPHY_TEST_DOUT_SEL 1 -#define USBHSPHY_TEST_CLK 0 - -#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5 -#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT) -#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT) -#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT) - -#define USBAMUX_DEVICE BIT(4) - -#define USBPHY_REFCLKDIV_SHIFT 2 -#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT) -#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT) -#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT) - -#define USB_CTRL_USB_CKO_SEL_BIT 0 - -#define USB_INT_CLK_XTAL 0 -#define USB_INT_CLK_REF300 2 -#define USB_INT_CLK_PLLB 3 - -#define SYS_CTRL_GMAC_CKEN_RX_IN 14 -#define SYS_CTRL_GMAC_CKEN_RXN_OUT 13 -#define SYS_CTRL_GMAC_CKEN_RX_OUT 12 -#define SYS_CTRL_GMAC_CKEN_TX_IN 10 -#define SYS_CTRL_GMAC_CKEN_TXN_OUT 9 -#define SYS_CTRL_GMAC_CKEN_TX_OUT 8 -#define SYS_CTRL_GMAC_RX_SOURCE 7 -#define SYS_CTRL_GMAC_TX_SOURCE 6 -#define SYS_CTRL_GMAC_LOW_TX_SOURCE 4 -#define SYS_CTRL_GMAC_AUTO_TX_SOURCE 3 -#define SYS_CTRL_GMAC_RGMII 2 -#define SYS_CTRL_GMAC_SIMPLE_MUX 1 -#define SYS_CTRL_GMAC_CKEN_GTX 0 -#define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT 0 -#define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT 8 -#define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT 16 -#define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT 24 -#define SYS_CTRL_GMAC_TX_VARDELAY(d) ((d)<outbound + PCIE_AHB_SLAVE_CTRL, + regmap_update_bits(pcie->sys_ctrl, pcie->outbound_offset + PCIE_AHB_SLAVE_CTRL, PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes)); wmb(); } @@ -418,17 +164,19 @@ static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes) static int oxnas_pcie_link_up(struct oxnas_pcie *pcie) { unsigned long end; + unsigned int val; /* Poll for PCIE link up */ end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ); while (!time_after(jiffies, end)) { - if (readl(pcie->pcie_ctrl) & PCIE_LINK_UP) + regmap_read(pcie->sys_ctrl, pcie->pcie_ctrl_offset, &val); + if (val & PCIE_LINK_UP) return 1; } return 0; } -static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie) +static void oxnas_pcie_setup_hw(struct oxnas_pcie *pcie) { /* We won't have any inbound address translation. This allows PCI * devices to access anywhere in the AHB address map. Might be regarded @@ -464,26 +212,27 @@ static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie) */ /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */ - writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_IN0_MEM_ADDR); - writel_relaxed(pcie->non_mem.end, pcie->outbound + PCIE_IN0_MEM_LIMIT); - writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_POM0_MEM_ADDR); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_ADDR, pcie->non_mem.start); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_LIMIT, pcie->non_mem.end); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM0_MEM_ADDR, pcie->non_mem.start); /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */ - writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_IN1_MEM_ADDR); - writel_relaxed(pcie->pre_mem.end, pcie->outbound + PCIE_IN1_MEM_LIMIT); - writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_POM1_MEM_ADDR); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_ADDR, pcie->pre_mem.start); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_LIMIT, pcie->pre_mem.end); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM1_MEM_ADDR, pcie->pre_mem.start); /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/ - writel_relaxed(pcie->io.start, pcie->outbound + PCIE_IN_IO_ADDR); - writel_relaxed(pcie->io.end, pcie->outbound + PCIE_IN_IO_LIMIT); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_ADDR, pcie->io.start); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_LIMIT, pcie->io.end); + /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/ - writel_relaxed(pcie->cfg.start, pcie->outbound + PCIE_IN_CFG0_ADDR); - writel_relaxed(pcie->cfg.end, pcie->outbound + PCIE_IN_CFG0_LIMIT); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_ADDR, pcie->cfg.start); + regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_LIMIT, pcie->cfg.end); wmb(); /* Enable outbound address translation */ - oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_OBTRANS); + regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, PCIE_OBTRANS, PCIE_OBTRANS); wmb(); /* @@ -597,7 +346,7 @@ static struct pci_ops oxnas_pcie_ops = { .write = oxnas_pcie_wr_conf, }; -static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys) +static int oxnas_pcie_setup(int nr, struct pci_sys_data *sys) { struct oxnas_pcie *pcie = sys_to_pcie(sys); @@ -619,7 +368,7 @@ static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys) return 1; } -static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie) +static void oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie) { struct hw_pci hw; int i; @@ -639,52 +388,11 @@ static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie pci_common_init_dev(dev, &hw); } -void oxnas_pcie_init_shared_hw(struct platform_device *pdev, - void __iomem *phybase) -{ - struct reset_control *rstc; - int ret; - - /* generate clocks from HCSL buffers, shared parts */ - writel(HCSL_BIAS_ON|HCSL_PCIE_EN, SYS_CTRL_HCSL_CTRL); - - /* Ensure PCIe PHY is properly reset */ - rstc = reset_control_get(&pdev->dev, "phy"); - if (IS_ERR(rstc)) { - ret = PTR_ERR(rstc); - } else { - ret = reset_control_reset(rstc); - reset_control_put(rstc); - } - - if (ret) { - dev_err(&pdev->dev, "phy reset failed %d\n", ret); - return; - } - - /* Enable PCIe Pre-Emphasis: What these value means? */ - - writel(ADDR_VAL(0x0014), phybase + PHY_ADDR); - writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA); - writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA); - - writel(ADDR_VAL(0x2004), phybase + PHY_ADDR); - writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA); - writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA); -} - -static int oxnas_pcie_shared_init(struct platform_device *pdev) +static int oxnas_pcie_shared_init(struct platform_device *pdev, struct oxnas_pcie *pcie) { if (++pcie_shared.refcount == 1) { - /* we are the first */ - struct device_node *np = pdev->dev.of_node; - void __iomem *phy = of_iomap(np, 2); - if (!phy) { - --pcie_shared.refcount; - return -ENOMEM; - } - oxnas_pcie_init_shared_hw(pdev, phy); - iounmap(phy); + phy_init(pcie->phy); + phy_power_on(pcie->phy); return 0; } else { return 0; @@ -701,7 +409,7 @@ static void oxnas_pcie_shared_deinit(struct platform_device *pdev) } #endif -static int __init +static int oxnas_pcie_map_registers(struct platform_device *pdev, struct device_node *np, struct oxnas_pcie *pcie) @@ -711,37 +419,58 @@ oxnas_pcie_map_registers(struct platform_device *pdev, u32 outbound_ctrl_offset; u32 pcie_ctrl_offset; - /* 2 is reserved for shared phy */ ret = of_address_to_resource(np, 0, ®s); - if (ret) + if (ret) { + dev_err(&pdev->dev, "failed to parse base register space\n"); return -EINVAL; + } + pcie->base = devm_ioremap_resource(&pdev->dev, ®s); - if (!pcie->base) + if (!pcie->base) { + dev_err(&pdev->dev, "failed to map base register space\n"); return -ENOMEM; + } ret = of_address_to_resource(np, 1, ®s); - if (ret) + if (ret) { + dev_err(&pdev->dev, "failed to parse inbound register space\n"); return -EINVAL; - pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s); - if (!pcie->inbound) - return -ENOMEM; + } + pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s); + if (!pcie->inbound) { + dev_err(&pdev->dev, "failed to map inbound register space\n"); + return -ENOMEM; + } + + pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL); + if (IS_ERR(pcie->phy)) { + if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) { + dev_err(&pdev->dev, "failed to probe phy\n"); + return PTR_ERR(pcie->phy); + } + dev_warn(&pdev->dev, "phy not attached\n"); + pcie->phy = NULL; + } if (of_property_read_u32(np, "plxtech,pcie-outbound-offset", - &outbound_ctrl_offset)) + &outbound_ctrl_offset)) { + dev_err(&pdev->dev, "failed to parse outbound register offset\n"); return -EINVAL; - /* SYSCRTL is shared by too many drivers, so is mapped by board file */ - pcie->outbound = IOMEM(OXNAS_SYSCRTL_BASE_VA + outbound_ctrl_offset); + } + pcie->outbound_offset = outbound_ctrl_offset; if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset", - &pcie_ctrl_offset)) + &pcie_ctrl_offset)) { + dev_err(&pdev->dev, "failed to parse pcie-ctrl register offset\n"); return -EINVAL; - pcie->pcie_ctrl = IOMEM(OXNAS_SYSCRTL_BASE_VA + pcie_ctrl_offset); + } + pcie->pcie_ctrl_offset = pcie_ctrl_offset; return 0; } -static int __init oxnas_pcie_init_res(struct platform_device *pdev, +static int oxnas_pcie_init_res(struct platform_device *pdev, struct oxnas_pcie *pcie, struct device_node *np) { @@ -823,7 +552,9 @@ static void oxnas_pcie_init_hw(struct platform_device *pdev, mdelay(100); } - oxnas_register_set_mask(SYS_CTRL_HCSL_CTRL, BIT(pcie->hcsl_en)); + /* ToDo: use phy power-on port... */ + regmap_update_bits(pcie->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, + BIT(pcie->hcsl_en), BIT(pcie->hcsl_en)); /* core */ ret = device_reset(&pdev->dev); @@ -845,19 +576,21 @@ static void oxnas_pcie_init_hw(struct platform_device *pdev, } /* allow entry to L23 state */ - oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_READY_ENTR_L23); + regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, + PCIE_READY_ENTR_L23, PCIE_READY_ENTR_L23); /* Set PCIe core into RootCore mode */ - oxnas_register_value_mask(pcie->pcie_ctrl, PCIE_DEVICE_TYPE_MASK, - PCIE_DEVICE_TYPE_ROOT); + regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, + PCIE_DEVICE_TYPE_MASK, PCIE_DEVICE_TYPE_ROOT); wmb(); /* Bring up the PCI core */ - oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_LTSSM); + regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, + PCIE_LTSSM, PCIE_LTSSM); wmb(); } -static int __init oxnas_pcie_probe(struct platform_device *pdev) +static int oxnas_pcie_probe(struct platform_device *pdev) { struct oxnas_pcie *pcie; struct device_node *np = pdev->dev.of_node; @@ -872,6 +605,10 @@ static int __init oxnas_pcie_probe(struct platform_device *pdev) pcie->haslink = 1; spin_lock_init(&pcie->lock); + pcie->sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl"); + if (IS_ERR(pcie->sys_ctrl)) + return PTR_ERR(pcie->sys_ctrl); + ret = oxnas_pcie_init_res(pdev, pcie, np); if (ret) return ret; @@ -891,7 +628,7 @@ static int __init oxnas_pcie_probe(struct platform_device *pdev) goto err_free_gpio; } - ret = oxnas_pcie_shared_init(pdev); + ret = oxnas_pcie_shared_init(pdev, pcie); if (ret) goto err_free_gpio; @@ -922,25 +659,14 @@ static const struct of_device_id oxnas_pcie_of_match_table[] = { { .compatible = "plxtech,nas782x-pcie", }, {}, }; -MODULE_DEVICE_TABLE(of, oxnas_pcie_of_match_table); static struct platform_driver oxnas_pcie_driver = { .driver = { - .owner = THIS_MODULE, .name = "oxnas-pcie", - .of_match_table = - of_match_ptr(oxnas_pcie_of_match_table), + .suppress_bind_attrs = true, + .of_match_table = oxnas_pcie_of_match_table, }, + .probe = oxnas_pcie_probe, }; -static int __init oxnas_pcie_init(void) -{ - return platform_driver_probe(&oxnas_pcie_driver, - oxnas_pcie_probe); -} - -subsys_initcall(oxnas_pcie_init); - -MODULE_AUTHOR("Ma Haijun "); -MODULE_DESCRIPTION("NAS782x PCIe driver"); -MODULE_LICENSE("GPLv2"); +builtin_platform_driver(oxnas_pcie_driver); diff --git a/target/linux/oxnas/files/drivers/phy/phy-oxnas-pcie.c b/target/linux/oxnas/files/drivers/phy/phy-oxnas-pcie.c new file mode 100644 index 000000000..676a5f933 --- /dev/null +++ b/target/linux/oxnas/files/drivers/phy/phy-oxnas-pcie.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Daniel Golle + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ADDR_VAL(val) ((val) & 0xFFFF) +#define DATA_VAL(val) ((val) & 0xFFFF) + +#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114 + +enum { + HCSL_BIAS_ON = BIT(0), + HCSL_PCIE_EN = BIT(1), + HCSL_PCIEA_EN = BIT(2), + HCSL_PCIEB_EN = BIT(3), +}; + +enum { + /* pcie phy reg offset */ + PHY_ADDR = 0, + PHY_DATA = 4, + /* phy data reg bits */ + READ_EN = BIT(16), + WRITE_EN = BIT(17), + CAP_DATA = BIT(18), +}; + +struct oxnas_pcie_phy { + struct device *dev; + void __iomem *membase; + const struct phy_ops *ops; + struct regmap *sys_ctrl; +}; + +static int oxnas_pcie_phy_init(struct phy *phy) +{ + struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy); + struct reset_control *rstc; + int ret; + + /* generate clocks from HCSL buffers, shared parts */ + regmap_write(pciephy->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, HCSL_BIAS_ON|HCSL_PCIE_EN); + + /* Ensure PCIe PHY is properly reset */ + rstc = reset_control_get(pciephy->dev, "phy"); + if (IS_ERR(rstc)) { + ret = PTR_ERR(rstc); + } else { + ret = reset_control_reset(rstc); + reset_control_put(rstc); + } + + if (ret) { + dev_err(pciephy->dev, "phy reset failed %d\n", ret); + return ret; + } + + return 0; +} + +static int oxnas_pcie_phy_power_on(struct phy *phy) +{ + struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy); + + /* Enable PCIe Pre-Emphasis: What these value means? */ + writel(ADDR_VAL(0x0014), pciephy->membase + PHY_ADDR); + writel(DATA_VAL(0xce10) | CAP_DATA, pciephy->membase + PHY_DATA); + writel(DATA_VAL(0xce10) | WRITE_EN, pciephy->membase + PHY_DATA); + + writel(ADDR_VAL(0x2004), pciephy->membase + PHY_ADDR); + writel(DATA_VAL(0x82c7) | CAP_DATA, pciephy->membase + PHY_DATA); + writel(DATA_VAL(0x82c7) | WRITE_EN, pciephy->membase + PHY_DATA); + + return 0; +} + +static const struct phy_ops ops = { + .init = oxnas_pcie_phy_init, + .power_on = oxnas_pcie_phy_power_on, + .owner = THIS_MODULE, +}; + +static int oxnas_pcie_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + struct phy *generic_phy; + struct phy_provider *phy_provider; + struct oxnas_pcie_phy *pciephy; + struct regmap *sys_ctrl; + void __iomem *membase; + + membase = of_iomap(np, 0); + if (IS_ERR(membase)) + return PTR_ERR(membase); + + sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl"); + if (IS_ERR(sys_ctrl)) { + dev_err(dev, "Cannot find OX820 SYSCRTL\n"); + return PTR_ERR(sys_ctrl); + } + + pciephy = devm_kzalloc(dev, sizeof(*pciephy), GFP_KERNEL); + if (!pciephy) + return -ENOMEM; + + pciephy->sys_ctrl = sys_ctrl; + pciephy->membase = membase; + pciephy->dev = dev; + pciephy->ops = &ops; + + generic_phy = devm_phy_create(dev, dev->of_node, pciephy->ops); + if (IS_ERR(generic_phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(generic_phy); + } + + phy_set_drvdata(generic_phy, pciephy); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id oxnas_pcie_phy_id_table[] = { + { .compatible = "oxsemi,ox820-pcie-phy" }, + { }, +}; + +static struct platform_driver oxnas_pcie_phy_driver = { + .probe = oxnas_pcie_phy_probe, + .driver = { + .name = "ox820-pcie-phy", + .of_match_table = oxnas_pcie_phy_id_table, + }, +}; + +builtin_platform_driver(oxnas_pcie_phy_driver); diff --git a/target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c b/target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c new file mode 100644 index 000000000..e0c126eae --- /dev/null +++ b/target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * oxnas SoC reset driver + * based on: + * Microsemi MIPS SoC reset driver + * and ox820_assert_system_reset() written by Ma Hajun + * + * License: GPL + * Copyright (c) 2013 Ma Hajun + * Copyright (c) 2017 Microsemi Corporation + * Copyright (c) 2019 Daniel Golle + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* bit numbers of reset control register */ +#define OX820_SYS_CTRL_RST_SCU 0 +#define OX820_SYS_CTRL_RST_COPRO 1 +#define OX820_SYS_CTRL_RST_ARM0 2 +#define OX820_SYS_CTRL_RST_ARM1 3 +#define OX820_SYS_CTRL_RST_USBHS 4 +#define OX820_SYS_CTRL_RST_USBHSPHYA 5 +#define OX820_SYS_CTRL_RST_MACA 6 +#define OX820_SYS_CTRL_RST_MAC OX820_SYS_CTRL_RST_MACA +#define OX820_SYS_CTRL_RST_PCIEA 7 +#define OX820_SYS_CTRL_RST_SGDMA 8 +#define OX820_SYS_CTRL_RST_CIPHER 9 +#define OX820_SYS_CTRL_RST_DDR 10 +#define OX820_SYS_CTRL_RST_SATA 11 +#define OX820_SYS_CTRL_RST_SATA_LINK 12 +#define OX820_SYS_CTRL_RST_SATA_PHY 13 +#define OX820_SYS_CTRL_RST_PCIEPHY 14 +#define OX820_SYS_CTRL_RST_STATIC 15 +#define OX820_SYS_CTRL_RST_GPIO 16 +#define OX820_SYS_CTRL_RST_UART1 17 +#define OX820_SYS_CTRL_RST_UART2 18 +#define OX820_SYS_CTRL_RST_MISC 19 +#define OX820_SYS_CTRL_RST_I2S 20 +#define OX820_SYS_CTRL_RST_SD 21 +#define OX820_SYS_CTRL_RST_MACB 22 +#define OX820_SYS_CTRL_RST_PCIEB 23 +#define OX820_SYS_CTRL_RST_VIDEO 24 +#define OX820_SYS_CTRL_RST_DDR_PHY 25 +#define OX820_SYS_CTRL_RST_USBHSPHYB 26 +#define OX820_SYS_CTRL_RST_USBDEV 27 +#define OX820_SYS_CTRL_RST_ARMDBG 29 +#define OX820_SYS_CTRL_RST_PLLA 30 +#define OX820_SYS_CTRL_RST_PLLB 31 + +/* bit numbers of clock control register */ +#define OX820_SYS_CTRL_CLK_COPRO 0 +#define OX820_SYS_CTRL_CLK_DMA 1 +#define OX820_SYS_CTRL_CLK_CIPHER 2 +#define OX820_SYS_CTRL_CLK_SD 3 +#define OX820_SYS_CTRL_CLK_SATA 4 +#define OX820_SYS_CTRL_CLK_I2S 5 +#define OX820_SYS_CTRL_CLK_USBHS 6 +#define OX820_SYS_CTRL_CLK_MACA 7 +#define OX820_SYS_CTRL_CLK_MAC OX820_SYS_CTRL_CLK_MACA +#define OX820_SYS_CTRL_CLK_PCIEA 8 +#define OX820_SYS_CTRL_CLK_STATIC 9 +#define OX820_SYS_CTRL_CLK_MACB 10 +#define OX820_SYS_CTRL_CLK_PCIEB 11 +#define OX820_SYS_CTRL_CLK_REF600 12 +#define OX820_SYS_CTRL_CLK_USBDEV 13 +#define OX820_SYS_CTRL_CLK_DDR 14 +#define OX820_SYS_CTRL_CLK_DDRPHY 15 +#define OX820_SYS_CTRL_CLK_DDRCK 16 + +/* Regmap offsets */ +#define OX820_CLK_SET_REGOFFSET 0x2c +#define OX820_CLK_CLR_REGOFFSET 0x30 +#define OX820_RST_SET_REGOFFSET 0x34 +#define OX820_RST_CLR_REGOFFSET 0x38 +#define OX820_SECONDARY_SEL_REGOFFSET 0x14 +#define OX820_TERTIARY_SEL_REGOFFSET 0x8c +#define OX820_QUATERNARY_SEL_REGOFFSET 0x94 +#define OX820_DEBUG_SEL_REGOFFSET 0x9c +#define OX820_ALTERNATIVE_SEL_REGOFFSET 0xa4 +#define OX820_PULLUP_SEL_REGOFFSET 0xac +#define OX820_SEC_SECONDARY_SEL_REGOFFSET 0x100014 +#define OX820_SEC_TERTIARY_SEL_REGOFFSET 0x10008c +#define OX820_SEC_QUATERNARY_SEL_REGOFFSET 0x100094 +#define OX820_SEC_DEBUG_SEL_REGOFFSET 0x10009c +#define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4 +#define OX820_SEC_PULLUP_SEL_REGOFFSET 0x1000ac + + +struct oxnas_restart_context { + struct regmap *sys_ctrl; + struct notifier_block restart_handler; +}; + +static int ox820_restart_handle(struct notifier_block *this, + unsigned long mode, void *cmd) +{ + struct oxnas_restart_context *ctx = container_of(this, struct + oxnas_restart_context, + restart_handler); + u32 value; + + /* Assert reset to cores as per power on defaults + * Don't touch the DDR interface as things will come to an impromptu stop + * NB Possibly should be asserting reset for PLLB, but there are timing + * concerns here according to the docs */ + value = BIT(OX820_SYS_CTRL_RST_COPRO) | + BIT(OX820_SYS_CTRL_RST_USBHS) | + BIT(OX820_SYS_CTRL_RST_USBHSPHYA) | + BIT(OX820_SYS_CTRL_RST_MACA) | + BIT(OX820_SYS_CTRL_RST_PCIEA) | + BIT(OX820_SYS_CTRL_RST_SGDMA) | + BIT(OX820_SYS_CTRL_RST_CIPHER) | + BIT(OX820_SYS_CTRL_RST_SATA) | + BIT(OX820_SYS_CTRL_RST_SATA_LINK) | + BIT(OX820_SYS_CTRL_RST_SATA_PHY) | + BIT(OX820_SYS_CTRL_RST_PCIEPHY) | + BIT(OX820_SYS_CTRL_RST_STATIC) | + BIT(OX820_SYS_CTRL_RST_UART1) | + BIT(OX820_SYS_CTRL_RST_UART2) | + BIT(OX820_SYS_CTRL_RST_MISC) | + BIT(OX820_SYS_CTRL_RST_I2S) | + BIT(OX820_SYS_CTRL_RST_SD) | + BIT(OX820_SYS_CTRL_RST_MACB) | + BIT(OX820_SYS_CTRL_RST_PCIEB) | + BIT(OX820_SYS_CTRL_RST_VIDEO) | + BIT(OX820_SYS_CTRL_RST_USBHSPHYB) | + BIT(OX820_SYS_CTRL_RST_USBDEV); + + regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value); + + /* Release reset to cores as per power on defaults */ + regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET, BIT(OX820_SYS_CTRL_RST_GPIO)); + + /* Disable clocks to cores as per power-on defaults - must leave DDR + * related clocks enabled otherwise we'll stop rather abruptly. */ + value = + BIT(OX820_SYS_CTRL_CLK_COPRO) | + BIT(OX820_SYS_CTRL_CLK_DMA) | + BIT(OX820_SYS_CTRL_CLK_CIPHER) | + BIT(OX820_SYS_CTRL_CLK_SD) | + BIT(OX820_SYS_CTRL_CLK_SATA) | + BIT(OX820_SYS_CTRL_CLK_I2S) | + BIT(OX820_SYS_CTRL_CLK_USBHS) | + BIT(OX820_SYS_CTRL_CLK_MAC) | + BIT(OX820_SYS_CTRL_CLK_PCIEA) | + BIT(OX820_SYS_CTRL_CLK_STATIC) | + BIT(OX820_SYS_CTRL_CLK_MACB) | + BIT(OX820_SYS_CTRL_CLK_PCIEB) | + BIT(OX820_SYS_CTRL_CLK_REF600) | + BIT(OX820_SYS_CTRL_CLK_USBDEV); + + regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value); + + /* Enable clocks to cores as per power-on defaults */ + + /* Set sys-control pin mux'ing as per power-on defaults */ + regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0); + + regmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0); + regmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0); + + /* No need to save any state, as the ROM loader can determine whether + * reset is due to power cycling or programatic action, just hit the + * (self-clearing) CPU reset bit of the block reset register */ + value = + BIT(OX820_SYS_CTRL_RST_SCU) | + BIT(OX820_SYS_CTRL_RST_ARM0) | + BIT(OX820_SYS_CTRL_RST_ARM1); + + regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value); + + pr_emerg("Unable to restart system\n"); + return NOTIFY_DONE; +} + +static int ox820_restart_probe(struct platform_device *pdev) +{ + struct oxnas_restart_context *ctx; + struct regmap *sys_ctrl; + struct device *dev = &pdev->dev; + int err = 0; + + sys_ctrl = syscon_node_to_regmap(pdev->dev.of_node); + if (IS_ERR(sys_ctrl)) + return PTR_ERR(sys_ctrl); + + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->sys_ctrl = sys_ctrl; + ctx->restart_handler.notifier_call = ox820_restart_handle; + ctx->restart_handler.priority = 192; + err = register_restart_handler(&ctx->restart_handler); + if (err) + dev_err(dev, "can't register restart notifier (err=%d)\n", err); + + return err; +} + +static const struct of_device_id ox820_restart_of_match[] = { + { .compatible = "oxsemi,ox820-sys-ctrl" }, + {} +}; + +static struct platform_driver ox820_restart_driver = { + .probe = ox820_restart_probe, + .driver = { + .name = "ox820-chip-reset", + .of_match_table = ox820_restart_of_match, + }, +}; +builtin_platform_driver(ox820_restart_driver); diff --git a/target/linux/oxnas/image/ox820.mk b/target/linux/oxnas/image/ox820.mk index 60f85d11d..de1bfd19f 100644 --- a/target/linux/oxnas/image/ox820.mk +++ b/target/linux/oxnas/image/ox820.mk @@ -11,6 +11,8 @@ define Device/Default SUBPAGESIZE := 512 FILESYSTEMS := squashfs ubifs PROFILES = Default $$(DTS) + SUPPORTED_DEVICES := $(subst _,$(comma),$(1)) + DEVICE_DTS := ox820-$(subst _,-,$(1)) KERNEL := kernel-bin | append-dtb | uImage none IMAGES := ubinized.bin sysupgrade.tar IMAGE/ubinized.bin := append-ubi @@ -36,51 +38,47 @@ define Build/encrypt-3des openssl enc -des3 -a -k $(1) -in $@ -out $@.new && mv $@.new $@ endef -define Device/akitio-mycloud - DEVICE_DTS := ox820-akitio-mycloud +define Device/akitio_mycloud DEVICE_TITLE := Akition myCloud (mini) / SilverStone DC01 - SUPPORTED_DEVICES := akitio,mycloud akitio - DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-ledtrig-usbdev \ + SUPPORTED_DEVICES += akitio + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-usb-ledtrig-usbport \ kmod-i2c-gpio kmod-rtc-ds1307 endef -TARGET_DEVICES += akitio-mycloud +TARGET_DEVICES += akitio_mycloud -define Device/cloudengines-pogoplug-pro - DEVICE_DTS := ox820-cloudengines-pogoplug-pro +define Device/cloudengines_pogoplugpro DEVICE_TITLE := Cloud Engines PogoPlug Pro (with mPCIe) - SUPPORTED_DEVICES := cloudengines,pogoplugpro pogoplug-pro - DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ledtrig-usbdev + SUPPORTED_DEVICES += pogoplug-pro + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport kmod-rt2800-pci wpad-basic endef -TARGET_DEVICES += cloudengines-pogoplug-pro +TARGET_DEVICES += cloudengines_pogoplugpro -define Device/cloudengines-pogoplug-series-3 - DEVICE_DTS := ox820-cloudengines-pogoplug-series-3 +define Device/cloudengines_pogoplug-series-3 DEVICE_TITLE := Cloud Engines PogoPlug Series V3 (without mPCIe) - SUPPORTED_DEVICES := cloudengines,pogoplugv3 pogoplug-v3 - DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ledtrig-usbdev + SUPPORTED_DEVICES += cloudengines,pogoplugv3 pogoplug-v3 + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport endef -TARGET_DEVICES += cloudengines-pogoplug-series-3 +TARGET_DEVICES += cloudengines_pogoplug-series-3 -define Device/shuttle-kd20 - DEVICE_DTS := ox820-shuttle-kd20 +define Device/shuttle_kd20 DEVICE_TITLE := Shuttle KD20 - SUPPORTED_DEVICES := shuttle,kd20 kd20 + SUPPORTED_DEVICES += kd20 KERNEL := kernel-bin | append-dtb | uImage none KERNEL_INITRAMFS_PREFIX = $$(IMAGE_PREFIX)-factory KERNEL_INITRAMFS_SUFFIX := .tar.gz KERNEL_INITRAMFS = kernel-bin | append-dtb | uImage none | omninas-factory | encrypt-3des sohmuntitnlaes - DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-ledtrig-usbdev \ + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-usb-ledtrig-usbport \ kmod-usb3 kmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper \ kmod-hwmon-core kmod-hwmon-gpiofan \ kmod-md-mod kmod-md-raid0 kmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs endef -TARGET_DEVICES += shuttle-kd20 +TARGET_DEVICES += shuttle_kd20 -define Device/mitrastar-stg212 - DEVICE_DTS := ox820-mitrastar-stg212 +define Device/mitrastar_stg-212 DEVICE_TITLE := MitraStar STG-212 - SUPPORTED_DEVICES := mitrastar,stg-212 stg212 + SUPPORTED_DEVICES += stg212 KERNEL := kernel-bin | append-dtb | uImage none - DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-ledtrig-usbdev + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-fs-ext4 kmod-fs-xfs \ + kmod-usb-ledtrig-usbport endef -TARGET_DEVICES += mitrastar-stg212 +TARGET_DEVICES += mitrastar_stg-212 diff --git a/target/linux/oxnas/ox820/target.mk b/target/linux/oxnas/ox820/target.mk index 7c5745814..682047303 100644 --- a/target/linux/oxnas/ox820/target.mk +++ b/target/linux/oxnas/ox820/target.mk @@ -3,10 +3,6 @@ BOARDNAME:=OX820/NAS782x CPU_TYPE:=mpcore FEATURES+=nand pci pcie ubifs usb -DEFAULT_PACKAGES += \ - uboot-oxnas-ox820 - - define Target/Description Oxford/PLXTECH OX820/NAS782x endef \ No newline at end of file diff --git a/target/linux/oxnas/patches-4.14/020-nand-partitions-on-pogoplug-v3.patch b/target/linux/oxnas/patches-4.14/020-nand-partitions-on-pogoplug-v3.patch new file mode 100644 index 000000000..113624088 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/020-nand-partitions-on-pogoplug-v3.patch @@ -0,0 +1,32 @@ +--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts ++++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts +@@ -74,11 +74,27 @@ + nand-ecc-algo = "hamming"; + + partition@0 { +- label = "boot"; +- reg = <0x00000000 0x00e00000>; ++ label = "stage1"; ++ reg = <0x00000000 0x00040000>; + read-only; + }; + ++ partition@40000 { ++ label = "u-boot"; ++ reg = <0x00040000 0x00380000>; ++ read-only; ++ }; ++ ++ partition@3c0000 { ++ label = "u-boot-env"; ++ reg = <0x003c0000 0x00080000>; ++ }; ++ ++ partition@440000 { ++ label = "kernel"; ++ reg = <0x00440000 0x009c0000>; ++ }; ++ + partition@e00000 { + label = "ubi"; + reg = <0x00e00000 0x07200000>; diff --git a/target/linux/oxnas/patches-4.14/030-led-aliases-on-pogoplug-v3.patch b/target/linux/oxnas/patches-4.14/030-led-aliases-on-pogoplug-v3.patch new file mode 100644 index 000000000..4025ec035 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/030-led-aliases-on-pogoplug-v3.patch @@ -0,0 +1,34 @@ +--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts ++++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts +@@ -28,24 +28,28 @@ + serial0 = &uart0; + gpio0 = &gpio0; + gpio1 = &gpio1; ++ led-boot = &led_status; ++ led-failsafe = &led_warn; ++ led-running = &led_act; ++ led-upgrade = &led_warn; + }; + + leds { + compatible = "gpio-leds"; + +- blue { ++ led_status: blue { + label = "pogoplug:blue"; + gpios = <&gpio0 2 0>; + default-state = "keep"; + }; + +- orange { ++ led_warn: orange { + label = "pogoplug:orange"; + gpios = <&gpio1 16 1>; + default-state = "keep"; + }; + +- green { ++ led_act: green { + label = "pogoplug:green"; + gpios = <&gpio1 17 1>; + default-state = "keep"; diff --git a/target/linux/oxnas/patches-4.14/040-pogoplug-series-3-compatible-string.patch b/target/linux/oxnas/patches-4.14/040-pogoplug-series-3-compatible-string.patch new file mode 100644 index 000000000..f14afd453 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/040-pogoplug-series-3-compatible-string.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts ++++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts +@@ -12,7 +12,7 @@ + / { + model = "Cloud Engines PogoPlug Series 3"; + +- compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; ++ compatible = "cloudengines,pogoplug-series-3", "cloudengines,pogoplugv3", "oxsemi,ox820"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; diff --git a/target/linux/oxnas/patches-4.14/060-fix-oxnas-rps-dt-match.patch b/target/linux/oxnas/patches-4.14/060-fix-oxnas-rps-dt-match.patch new file mode 100644 index 000000000..4cc622b19 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/060-fix-oxnas-rps-dt-match.patch @@ -0,0 +1,8 @@ +--- a/drivers/clocksource/timer-oxnas-rps.c ++++ b/drivers/clocksource/timer-oxnas-rps.c +@@ -296,4 +296,4 @@ err_alloc: + TIMER_OF_DECLARE(ox810se_rps, + "oxsemi,ox810se-rps-timer", oxnas_rps_timer_init); + TIMER_OF_DECLARE(ox820_rps, +- "oxsemi,ox820se-rps-timer", oxnas_rps_timer_init); ++ "oxsemi,ox820-rps-timer", oxnas_rps_timer_init); diff --git a/target/linux/oxnas/patches-4.14/150-oxnas-restart.patch b/target/linux/oxnas/patches-4.14/150-oxnas-restart.patch new file mode 100644 index 000000000..dafa96759 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/150-oxnas-restart.patch @@ -0,0 +1,25 @@ +--- a/drivers/power/reset/Kconfig ++++ b/drivers/power/reset/Kconfig +@@ -113,6 +113,12 @@ config POWER_RESET_MSM + help + Power off and restart support for Qualcomm boards. + ++config POWER_RESET_OXNAS ++ bool "OXNAS SoC restart driver" ++ depends on ARCH_OXNAS ++ help ++ Restart support for OXNAS boards. ++ + config POWER_RESET_PIIX4_POWEROFF + tristate "Intel PIIX4 power-off driver" + depends on PCI +--- a/drivers/power/reset/Makefile ++++ b/drivers/power/reset/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_RESET_GPIO_RESTART) + + obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o + obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o + obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o ++obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o + obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o + obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o + obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o diff --git a/target/linux/oxnas/patches-4.14/320-oxnas-phy-pcie.patch b/target/linux/oxnas/patches-4.14/320-oxnas-phy-pcie.patch new file mode 100644 index 000000000..7dc947042 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/320-oxnas-phy-pcie.patch @@ -0,0 +1,44 @@ +--- a/arch/arm/boot/dts/ox820.dtsi ++++ b/arch/arm/boot/dts/ox820.dtsi +@@ -246,6 +246,15 @@ + }; + }; + ++ pcie_phy: pcie-phy@a00000 { ++ compatible = "oxsemi,ox820-pcie-phy"; ++ reg = <0xa00000 0x10>; ++ #phy-cells = <0>; ++ resets = <&reset RESET_PCIEPHY>; ++ reset-names = "phy"; ++ status = "disabled"; ++ }; ++ + sys: sys-ctrl@e00000 { + compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; + reg = <0xe00000 0x200000>; +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -26,6 +26,13 @@ config PHY_LPC18XX_USB_OTG + This driver is need for USB0 support on LPC18xx/43xx and takes + care of enabling and clock setup. + ++config PHY_OXNAS ++ tristate "Oxford Semi. OX820 PCI-E PHY support" ++ depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST) ++ select GENERIC_PHY ++ help ++ This option enables support for OXNAS OX820 SoC PCIE PHY. ++ + config PHY_PISTACHIO_USB + tristate "IMG Pistachio USB2.0 PHY driver" + depends on MACH_PISTACHIO +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -5,6 +5,7 @@ + + obj-$(CONFIG_GENERIC_PHY) += phy-core.o + obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o ++obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o + obj-$(CONFIG_PHY_XGENE) += phy-xgene.o + obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o + obj-$(CONFIG_ARCH_SUNXI) += allwinner/ diff --git a/target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch b/target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch index 4681888da..a6b713758 100644 --- a/target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch +++ b/target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch @@ -22,87 +22,99 @@ --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi -@@ -307,6 +307,83 @@ - reg = <0x1000 0x1000>, +@@ -288,7 +288,7 @@ + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; +- ranges = <0 0x47000000 0x1000000>; ++ ranges = <0 0x47000000 0x2000>; + + scu: scu@0 { + compatible = "arm,arm11mp-scu"; +@@ -317,5 +317,86 @@ <0x100 0x500>; }; -+ -+ pcie0: pcie-controller@c00000 { -+ compatible = "plxtech,nas782x-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ /* flag & space bus address host address size */ -+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000 -+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000 -+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000 -+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>; -+ -+ bus-range = <0x00 0x7f>; -+ -+ /* cfg inbound translator phy*/ -+ reg = <0x47C00000 0x1000>, <0x47D00000 0x100>, <0x44A00000 0x10>; -+ -+ #interrupt-cells = <1>; -+ /* wild card mask, match all bus address & interrupt specifier */ -+ /* format: bus address mask, interrupt specifier mask */ -+ /* each bit 1 means need match, 0 means ignored when match */ -+ interrupt-map-mask = <0 0 0 0>; -+ /* format: a list of: bus address, interrupt specifier, -+ * parent interrupt controller & specifier */ -+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>; -+ -+ gpios = <&gpio1 12 0>; -+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>; -+ clock-names = "pcie", "busclk"; -+ resets = <&reset RESET_PCIEA>, <&reset RESET_PCIEPHY>; -+ reset-names = "pcie", "phy"; -+ -+ plxtech,pcie-hcsl-bit = <2>; -+ plxtech,pcie-ctrl-offset = <0x120>; -+ plxtech,pcie-outbound-offset = <0x138>; -+ status = "disabled"; -+ }; -+ -+ pcie1: pcie-controller@e00000 { -+ compatible = "plxtech,nas782x-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ /* flag & space bus address host address size */ -+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000 -+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000 -+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000 -+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>; -+ -+ bus-range = <0x80 0xff>; -+ -+ /* cfg inbound translator phy*/ -+ reg = <0x47E00000 0x1000>, <0x47F00000 0x100>, <0x44A00000 0x10>; -+ -+ #interrupt-cells = <1>; -+ /* wild card mask, match all bus address & interrupt specifier */ -+ /* format: bus address mask, interrupt specifier mask */ -+ /* each bit 1 means need match, 0 means ignored when match */ -+ interrupt-map-mask = <0 0 0 0>; -+ /* format: a list of: bus address, interrupt specifier, -+ * parent interrupt controller & specifier */ -+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>; -+ -+ /* gpios = <&gpio1 12 0>; */ -+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>; -+ clock-names = "pcie", "busclk"; -+ resets = <&reset RESET_PCIEB>, <&reset RESET_PCIEPHY>; -+ reset-names = "pcie", "phy"; -+ -+ plxtech,pcie-hcsl-bit = <3>; -+ plxtech,pcie-ctrl-offset = <0x124>; -+ plxtech,pcie-outbound-offset = <0x174>; -+ status = "disabled"; -+ }; -+ }; ++ ++ pcie0: pcie-controller@47c00000 { ++ compatible = "plxtech,nas782x-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ /* flag & space bus address host address size */ ++ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000 ++ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000 ++ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000 ++ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>; ++ ++ bus-range = <0x00 0x7f>; ++ ++ /* cfg inbound translator */ ++ reg = <0x47c00000 0x1000>, <0x47d00000 0x100>; ++ ++ phys = <&pcie_phy>; ++ phy-names = "pcie-phy"; ++ ++ #interrupt-cells = <1>; ++ /* wild card mask, match all bus address & interrupt specifier */ ++ /* format: bus address mask, interrupt specifier mask */ ++ /* each bit 1 means need match, 0 means ignored when match */ ++ interrupt-map-mask = <0 0 0 0>; ++ /* format: a list of: bus address, interrupt specifier, ++ * parent interrupt controller & specifier */ ++ interrupt-map = <0 0 0 0 &gic 0 19 0x304>; ++ gpios = <&gpio1 12 0>; ++ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>; ++ clock-names = "pcie", "busclk"; ++ resets = <&reset RESET_PCIEA>; ++ reset-names = "pcie"; ++ ++ plxtech,pcie-hcsl-bit = <2>; ++ plxtech,pcie-ctrl-offset = <0x120>; ++ plxtech,pcie-outbound-offset = <0x138>; ++ status = "disabled"; ++ }; ++ ++ pcie1: pcie-controller@47e00000 { ++ compatible = "plxtech,nas782x-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ /* flag & space bus address host address size */ ++ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000 ++ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000 ++ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000 ++ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>; ++ ++ bus-range = <0x80 0xff>; ++ ++ /* cfg inbound translator */ ++ reg = <0x47e00000 0x1000>, <0x47f00000 0x100>; ++ ++ phys = <&pcie_phy>; ++ phy-names = "pcie-phy"; ++ ++ #interrupt-cells = <1>; ++ /* wild card mask, match all bus address & interrupt specifier */ ++ /* format: bus address mask, interrupt specifier mask */ ++ /* each bit 1 means need match, 0 means ignored when match */ ++ interrupt-map-mask = <0 0 0 0>; ++ /* format: a list of: bus address, interrupt specifier, ++ * parent interrupt controller & specifier */ ++ interrupt-map = <0 0 0 0 &gic 0 20 0x304>; ++ ++ /* gpios = <&gpio1 12 0>; */ ++ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>; ++ clock-names = "pcie", "busclk"; ++ resets = <&reset RESET_PCIEB>; ++ reset-names = "pcie"; ++ ++ plxtech,pcie-hcsl-bit = <3>; ++ plxtech,pcie-ctrl-offset = <0x124>; ++ plxtech,pcie-outbound-offset = <0x174>; ++ status = "disabled"; ++ }; }; }; diff --git a/target/linux/oxnas/patches-4.14/500-oxnas-sata.patch b/target/linux/oxnas/patches-4.14/500-oxnas-sata.patch index f79b100a5..5fe074608 100644 --- a/target/linux/oxnas/patches-4.14/500-oxnas-sata.patch +++ b/target/linux/oxnas/patches-4.14/500-oxnas-sata.patch @@ -26,9 +26,9 @@ obj-$(CONFIG_PATA_ALI) += pata_ali.o --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi -@@ -385,5 +385,20 @@ - }; - +@@ -398,5 +398,20 @@ + plxtech,pcie-outbound-offset = <0x174>; + status = "disabled"; }; + + sata: sata@45900000 { diff --git a/target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch b/target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch index b4e34e5e3..c5a9fa047 100644 --- a/target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch +++ b/target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch @@ -26,7 +26,7 @@ obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi -@@ -105,6 +105,22 @@ +@@ -105,6 +105,31 @@ status = "disabled"; }; @@ -44,8 +44,30 @@ + /* FIXME: how to make this dependency explicit ? */ + oxsemi,ehci_use_pllb; + status = "disabled"; ++ ++ ehci_port1: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++ ehci_port2: port@2 { ++ reg = <2>; ++ #trigger-source-cells = <0>; ++ }; + }; + apb-bridge@44000000 { #address-cells = <1>; #size-cells = <1>; +--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts ++++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts +@@ -106,6 +106,10 @@ + }; + }; + ++&ehci { ++ status = "okay"; ++}; ++ + ða { + status = "okay"; + diff --git a/target/linux/ramips/patches-4.14/0031-uvc-add-iPassion-iP2970-support.patch b/target/linux/ramips/patches-4.14/0031-uvc-add-iPassion-iP2970-support.patch index 19bac1f64..3ef607f14 100644 --- a/target/linux/ramips/patches-4.14/0031-uvc-add-iPassion-iP2970-support.patch +++ b/target/linux/ramips/patches-4.14/0031-uvc-add-iPassion-iP2970-support.patch @@ -13,7 +13,7 @@ Signed-off-by: John Crispin --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c -@@ -2727,6 +2727,18 @@ static const struct usb_device_id uvc_id +@@ -2735,6 +2735,18 @@ static const struct usb_device_id uvc_id .bInterfaceSubClass = 1, .bInterfaceProtocol = 0, .driver_info = UVC_QUIRK_FORCE_Y8 }, diff --git a/target/linux/sunxi/patches-4.14/002-net-stmmac-dwmac-sun8i-Handle-integrated-external-MD.patch b/target/linux/sunxi/patches-4.14/002-net-stmmac-dwmac-sun8i-Handle-integrated-external-MD.patch index 8e0527f3d..6cde0e29b 100644 --- a/target/linux/sunxi/patches-4.14/002-net-stmmac-dwmac-sun8i-Handle-integrated-external-MD.patch +++ b/target/linux/sunxi/patches-4.14/002-net-stmmac-dwmac-sun8i-Handle-integrated-external-MD.patch @@ -115,7 +115,7 @@ Signed-off-by: David S. Miller /* H3/A64 specific bits */ #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ -@@ -634,6 +640,159 @@ static int sun8i_dwmac_reset(struct stmm +@@ -635,6 +641,159 @@ static int sun8i_dwmac_reset(struct stmm return 0; } @@ -275,7 +275,7 @@ Signed-off-by: David S. Miller static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) { struct sunxi_priv_data *gmac = priv->plat->bsp_priv; -@@ -648,35 +807,25 @@ static int sun8i_dwmac_set_syscon(struct +@@ -649,35 +808,25 @@ static int sun8i_dwmac_set_syscon(struct "Current syscon value is not the default %x (expect %x)\n", val, reg); @@ -329,7 +329,7 @@ Signed-off-by: David S. Miller } if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { -@@ -746,81 +895,21 @@ static void sun8i_dwmac_unset_syscon(str +@@ -747,81 +896,21 @@ static void sun8i_dwmac_unset_syscon(str regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); } @@ -420,7 +420,7 @@ Signed-off-by: David S. Miller clk_disable_unprepare(gmac->tx_clk); -@@ -849,7 +938,7 @@ static struct mac_device_info *sun8i_dwm +@@ -850,7 +939,7 @@ static struct mac_device_info *sun8i_dwm if (!mac) return NULL; @@ -429,7 +429,7 @@ Signed-off-by: David S. Miller if (ret) return NULL; -@@ -889,6 +978,8 @@ static int sun8i_dwmac_probe(struct plat +@@ -890,6 +979,8 @@ static int sun8i_dwmac_probe(struct plat struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; int ret; @@ -438,7 +438,7 @@ Signed-off-by: David S. Miller ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) -@@ -932,29 +1023,6 @@ static int sun8i_dwmac_probe(struct plat +@@ -933,29 +1024,6 @@ static int sun8i_dwmac_probe(struct plat } plat_dat->interface = of_get_phy_mode(dev->of_node); @@ -468,7 +468,7 @@ Signed-off-by: David S. Miller /* platform data specifying hardware features and callbacks. * hardware features were copied from Allwinner drivers. -@@ -973,9 +1041,34 @@ static int sun8i_dwmac_probe(struct plat +@@ -974,9 +1042,34 @@ static int sun8i_dwmac_probe(struct plat ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) diff --git a/target/linux/sunxi/patches-4.14/003-net-stmmac-sun8i-Restore-the-compatibles.patch b/target/linux/sunxi/patches-4.14/003-net-stmmac-sun8i-Restore-the-compatibles.patch index 2f4358505..98898fb46 100644 --- a/target/linux/sunxi/patches-4.14/003-net-stmmac-sun8i-Restore-the-compatibles.patch +++ b/target/linux/sunxi/patches-4.14/003-net-stmmac-sun8i-Restore-the-compatibles.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -1072,6 +1072,14 @@ return ret; +@@ -1073,6 +1073,14 @@ return ret; } static const struct of_device_id sun8i_dwmac_match[] = { diff --git a/target/linux/sunxi/patches-4.14/004-net-stmmac-dwmac-sun8i-fix-allwinner-leds-active-low.patch b/target/linux/sunxi/patches-4.14/004-net-stmmac-dwmac-sun8i-fix-allwinner-leds-active-low.patch index b8b5b53b3..1bd5e16c1 100644 --- a/target/linux/sunxi/patches-4.14/004-net-stmmac-dwmac-sun8i-fix-allwinner-leds-active-low.patch +++ b/target/linux/sunxi/patches-4.14/004-net-stmmac-dwmac-sun8i-fix-allwinner-leds-active-low.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -808,8 +808,7 @@ static int sun8i_dwmac_set_syscon(struct +@@ -809,8 +809,7 @@ static int sun8i_dwmac_set_syscon(struct val, reg); if (gmac->variant->soc_has_internal_phy) {