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qualcommax: add ipq8074-nss.dtsi for IPQ807x devices NSS support
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coolsnowwolf
parent
7b6fe1d69a
commit
eb557774e2
@ -0,0 +1,271 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/ {
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nss_dummy_reg: nss-regulator {
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compatible = "regulator-fixed";
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regulator-name = "nss-reg";
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regulator-min-microvolt = <848000>;
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regulator-max-microvolt = <848000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&soc {
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nss-common {
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compatible = "qcom,nss-common";
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reg = <0x01868010 0x1000>;
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reg-names = "nss-misc-reset";
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memory-region = <&nss_region>;
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};
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nss0: nss@40000000 {
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compatible = "qcom,nss";
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interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 385 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 386 IRQ_TYPE_EDGE_RISING>;
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reg = <0x39000000 0x1000>,
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<0x38000000 0x30000>,
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<0x0b111000 0x1000>;
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reg-names = "nphys", "vphys", "qgic-phys";
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clocks = <&gcc GCC_NSS_NOC_CLK>,
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<&gcc GCC_NSS_PTP_REF_CLK>,
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<&gcc GCC_NSS_CSR_CLK>,
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<&gcc GCC_NSS_CFG_CLK>,
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<&gcc GCC_NSS_IMEM_CLK>,
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<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
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<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
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<&gcc GCC_NSSNOC_SNOC_CLK>,
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<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
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<&gcc GCC_NSS_CE_AXI_CLK>,
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<&gcc GCC_NSS_CE_APB_CLK>,
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<&gcc GCC_NSSNOC_CE_AXI_CLK>,
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<&gcc GCC_NSSNOC_CE_APB_CLK>,
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<&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
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<&gcc GCC_UBI0_CORE_CLK>,
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<&gcc GCC_UBI0_AHB_CLK>,
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<&gcc GCC_UBI0_AXI_CLK>,
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<&gcc GCC_UBI0_MPT_CLK>,
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<&gcc GCC_UBI0_NC_AXI_CLK>;
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clock-names = "nss-noc-clk",
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"nss-ptp-ref-clk",
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"nss-csr-clk",
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"nss-cfg-clk",
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"nss-imem-clk",
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"nss-nssnoc-qosgen-ref-clk",
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"nss-mem-noc-nss-axi-clk",
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"nss-nssnoc-snoc-clk",
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"nss-nssnoc-timeout-ref-clk",
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"nss-ce-axi-clk",
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"nss-ce-apb-clk",
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"nss-nssnoc-ce-axi-clk",
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"nss-nssnoc-ce-apb-clk",
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"nss-nssnoc-ahb-clk",
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"nss-core-clk",
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"nss-ahb-clk",
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"nss-axi-clk",
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"nss-mpt-clk",
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"nss-nc-axi-clk";
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qcom,id = <0>;
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qcom,num-queue = <4>;
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qcom,num-irq = <10>;
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qcom,num-pri = <4>;
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qcom,load-addr = <0x40000000>;
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qcom,low-frequency = <187200000>;
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qcom,mid-frequency = <748800000>;
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qcom,max-frequency = <1689600000>;
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qcom,bridge-enabled;
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qcom,ipv4-enabled;
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qcom,ipv4-reasm-enabled;
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qcom,ipv6-enabled;
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qcom,ipv6-reasm-enabled;
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qcom,wlanredirect-enabled;
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qcom,tun6rd-enabled;
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qcom,l2tpv2-enabled;
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qcom,gre-enabled;
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qcom,gre-redir-enabled;
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qcom,gre-redir-mark-enabled;
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qcom,map-t-enabled;
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qcom,portid-enabled;
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qcom,ppe-enabled;
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qcom,pppoe-enabled;
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qcom,pptp-enabled;
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qcom,tunipip6-enabled;
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qcom,shaping-enabled;
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qcom,wlan-dataplane-offload-enabled;
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qcom,vlan-enabled;
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qcom,igs-enabled;
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qcom,vxlan-enabled;
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qcom,match-enabled;
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qcom,mirror-enabled;
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qcom,udp-st-enabled;
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mx-supply = <&nss_dummy_reg>;
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npu-supply = <&nss_dummy_reg>;
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};
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nss1: nss@40800000 {
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compatible = "qcom,nss";
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interrupts = <GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 391 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 392 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 393 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 394 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 395 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 396 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 397 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 398 IRQ_TYPE_EDGE_RISING>;
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reg = <0x39400000 0x1000>,
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<0x38030000 0x30000>,
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<0x0b111000 0x1000>;
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reg-names = "nphys", "vphys", "qgic-phys";
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clocks = <&gcc GCC_NSS_NOC_CLK>,
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<&gcc GCC_NSS_PTP_REF_CLK>,
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<&gcc GCC_NSS_CSR_CLK>,
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<&gcc GCC_NSS_CFG_CLK>,
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<&gcc GCC_NSS_IMEM_CLK>,
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<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
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<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
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<&gcc GCC_NSSNOC_SNOC_CLK>,
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<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
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<&gcc GCC_NSS_CE_AXI_CLK>,
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<&gcc GCC_NSS_CE_APB_CLK>,
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<&gcc GCC_NSSNOC_CE_AXI_CLK>,
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<&gcc GCC_NSSNOC_CE_APB_CLK>,
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<&gcc GCC_NSSNOC_UBI1_AHB_CLK>,
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<&gcc GCC_UBI1_CORE_CLK>,
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<&gcc GCC_UBI1_AHB_CLK>,
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<&gcc GCC_UBI1_AXI_CLK>,
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<&gcc GCC_UBI1_MPT_CLK>,
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<&gcc GCC_UBI1_NC_AXI_CLK>;
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clock-names = "nss-noc-clk",
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"nss-ptp-ref-clk",
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"nss-csr-clk",
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"nss-cfg-clk",
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"nss-imem-clk",
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"nss-nssnoc-qosgen-ref-clk",
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"nss-mem-noc-nss-axi-clk",
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"nss-nssnoc-snoc-clk",
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"nss-nssnoc-timeout-ref-clk",
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"nss-ce-axi-clk",
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"nss-ce-apb-clk",
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"nss-nssnoc-ce-axi-clk",
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"nss-nssnoc-ce-apb-clk",
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"nss-nssnoc-ahb-clk",
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"nss-core-clk",
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"nss-ahb-clk",
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"nss-axi-clk",
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"nss-mpt-clk",
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"nss-nc-axi-clk";
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qcom,id = <1>;
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qcom,num-queue = <4>;
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qcom,num-irq = <9>;
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qcom,num-pri = <4>;
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qcom,load-addr = <0x40800000>;
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qcom,capwap-enabled;
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qcom,dtls-enabled;
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qcom,tls-enabled;
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qcom,crypto-enabled;
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qcom,ipsec-enabled;
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qcom,qvpn-enabled;
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qcom,pvxlan-enabled;
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qcom,clmap-enabled;
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qcom,rmnet_rx-enabled;
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};
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nss_crypto: qcom,nss_crypto {
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compatible = "qcom,nss-crypto";
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#address-cells = <1>;
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#size-cells = <1>;
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qcom,max-contexts = <64>;
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qcom,max-context-size = <32>;
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ranges;
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eip197_node {
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compatible = "qcom,eip197";
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reg-names = "crypto_pbase";
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reg = <0x39800000 0x7ffff>;
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clocks = <&gcc GCC_NSS_CRYPTO_CLK>,
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<&gcc GCC_NSSNOC_CRYPTO_CLK>,
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<&gcc GCC_CRYPTO_PPE_CLK>;
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clock-names = "crypto_clk",
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"crypto_nocclk",
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"crypto_ppeclk";
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clock-frequency = /bits/ 64 <600000000 600000000 300000000>;
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qcom,dma-mask = <0xff>;
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qcom,transform-enabled;
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qcom,aes128-cbc;
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qcom,aes192-cbc;
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qcom,aes256-cbc;
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qcom,aes128-ctr;
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qcom,aes192-ctr;
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qcom,aes256-ctr;
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qcom,aes128-ecb;
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qcom,aes192-ecb;
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qcom,aes256-ecb;
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qcom,3des-cbc;
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qcom,md5-hash;
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qcom,sha160-hash;
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qcom,sha224-hash;
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qcom,sha384-hash;
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qcom,sha512-hash;
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qcom,sha256-hash;
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qcom,md5-hmac;
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qcom,sha160-hmac;
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qcom,sha224-hmac;
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qcom,sha256-hmac;
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qcom,sha384-hmac;
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qcom,sha512-hmac;
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qcom,aes128-gcm-gmac;
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qcom,aes192-gcm-gmac;
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qcom,aes256-gcm-gmac;
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qcom,aes128-cbc-md5-hmac;
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qcom,aes128-cbc-sha160-hmac;
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qcom,aes192-cbc-md5-hmac;
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qcom,aes192-cbc-sha160-hmac;
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qcom,aes256-cbc-md5-hmac;
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qcom,aes256-cbc-sha160-hmac;
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qcom,aes128-ctr-sha160-hmac;
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qcom,aes192-ctr-sha160-hmac;
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qcom,aes256-ctr-sha160-hmac;
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qcom,aes128-ctr-md5-hmac;
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qcom,aes192-ctr-md5-hmac;
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qcom,aes256-ctr-md5-hmac;
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qcom,3des-cbc-md5-hmac;
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qcom,3des-cbc-sha160-hmac;
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qcom,aes128-cbc-sha256-hmac;
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qcom,aes192-cbc-sha256-hmac;
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qcom,aes256-cbc-sha256-hmac;
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qcom,aes128-ctr-sha256-hmac;
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qcom,aes192-ctr-sha256-hmac;
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qcom,aes256-ctr-sha256-hmac;
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qcom,3des-cbc-sha256-hmac;
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qcom,aes128-cbc-sha384-hmac;
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qcom,aes192-cbc-sha384-hmac;
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qcom,aes256-cbc-sha384-hmac;
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qcom,aes128-ctr-sha384-hmac;
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qcom,aes192-ctr-sha384-hmac;
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qcom,aes256-ctr-sha384-hmac;
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qcom,aes128-cbc-sha512-hmac;
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qcom,aes192-cbc-sha512-hmac;
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qcom,aes256-cbc-sha512-hmac;
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qcom,aes128-ctr-sha512-hmac;
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qcom,aes192-ctr-sha512-hmac;
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qcom,aes256-ctr-sha512-hmac;
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engine0 {
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reg_offset = <0x80000>;
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qcom,ifpp-enabled;
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qcom,ipue-enabled;
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qcom,ofpp-enabled;
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qcom,opue-enabled;
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};
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};
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};
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};
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