diff --git a/package/boot/uboot-envtools/files/ipq807x b/package/boot/uboot-envtools/files/ipq807x new file mode 100644 index 000000000..5611b6f4f --- /dev/null +++ b/package/boot/uboot-envtools/files/ipq807x @@ -0,0 +1,23 @@ +[ -e /etc/config/ubootenv ] && exit 0 + +touch /etc/config/ubootenv + +. /lib/uboot-envtools.sh +. /lib/functions.sh + +board=$(board_name) + +case "$board" in +redmi,ax6|\ +xiaomi,ax3600|\ +xiaomi,ax9000) + idx="$(find_mtd_index 0:appsblenv)" + [ -n "$idx" ] && \ + ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x20000" + ;; +esac + +config_load ubootenv +config_foreach ubootenv_add_app_config ubootenv + +exit 0 diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile index 15f8a582f..a69ebe8ea 100644 --- a/package/firmware/ipq-wifi/Makefile +++ b/package/firmware/ipq-wifi/Makefile @@ -50,11 +50,13 @@ ALLWIFIBOARDS:= \ mikrotik_sxtsq-5-ac \ mobipromo_cm520-79f \ nec_wg2600hp3 \ + netgear_sxr80 \ netgear_wac510 \ plasmacloud_pa1200 \ plasmacloud_pa2200 \ - p2w_r619ac \ - qxwlan_e2600ac + redmi_ax6 \ + xiaomi_ax3600 \ + xiaomi_ax9000 ALLWIFIPACKAGES:=$(foreach BOARD,$(ALLWIFIBOARDS),ipq-wifi-$(BOARD)) @@ -62,7 +64,7 @@ define Package/ipq-wifi-default SUBMENU:=ath10k Board-Specific Overrides SECTION:=firmware CATEGORY:=Firmware - DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x) + DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x||TARGET_ipq807x) TITLE:=Custom Board endef @@ -140,10 +142,14 @@ $(eval $(call generate-ipq-wifi-package,mikrotik_hap-ac2,Mikrotik hAP ac2)) $(eval $(call generate-ipq-wifi-package,mikrotik_sxtsq-5-ac,MikroTik SXTsq 5 ac)) $(eval $(call generate-ipq-wifi-package,mobipromo_cm520-79f,MobiPromo CM520-79F)) $(eval $(call generate-ipq-wifi-package,nec_wg2600hp3,NEC Platforms WG2600HP3)) +$(eval $(call generate-ipq-wifi-package,netgear_sxr80,Netgear SXR80)) $(eval $(call generate-ipq-wifi-package,netgear_wac510,Netgear WAC510)) $(eval $(call generate-ipq-wifi-package,plasmacloud_pa1200,Plasma Cloud PA1200)) $(eval $(call generate-ipq-wifi-package,plasmacloud_pa2200,Plasma Cloud PA2200)) $(eval $(call generate-ipq-wifi-package,p2w_r619ac,P&W R619AC)) $(eval $(call generate-ipq-wifi-package,qxwlan_e2600ac,Qxwlan E2600AC)) +$(eval $(call generate-ipq-wifi-package,redmi_ax6,Redmi AX6)) +$(eval $(call generate-ipq-wifi-package,xiaomi_ax3600,Xiaomi AX3600)) +$(eval $(call generate-ipq-wifi-package,xiaomi_ax9000,Xiaomi AX9000)) $(foreach PACKAGE,$(ALLWIFIPACKAGES),$(eval $(call BuildPackage,$(PACKAGE)))) diff --git a/package/firmware/ipq-wifi/board-netgear_sxr80.ipq8074 b/package/firmware/ipq-wifi/board-netgear_sxr80.ipq8074 new file mode 100644 index 000000000..446876c00 Binary files /dev/null and b/package/firmware/ipq-wifi/board-netgear_sxr80.ipq8074 differ diff --git a/package/firmware/ipq-wifi/board-redmi_ax6.ipq8074 b/package/firmware/ipq-wifi/board-redmi_ax6.ipq8074 new file mode 100644 index 000000000..98ed9c6f6 Binary files /dev/null and b/package/firmware/ipq-wifi/board-redmi_ax6.ipq8074 differ diff --git a/package/firmware/ipq-wifi/board-xiaomi_ax3600.ipq8074 b/package/firmware/ipq-wifi/board-xiaomi_ax3600.ipq8074 new file mode 100644 index 000000000..db8ef4cef Binary files /dev/null and b/package/firmware/ipq-wifi/board-xiaomi_ax3600.ipq8074 differ diff --git a/package/firmware/ipq-wifi/board-xiaomi_ax3600.qca9889 b/package/firmware/ipq-wifi/board-xiaomi_ax3600.qca9889 new file mode 100644 index 000000000..af4405cd5 Binary files /dev/null and b/package/firmware/ipq-wifi/board-xiaomi_ax3600.qca9889 differ diff --git a/package/firmware/ipq-wifi/board-xiaomi_ax9000.ipq8074 b/package/firmware/ipq-wifi/board-xiaomi_ax9000.ipq8074 new file mode 100644 index 000000000..babfaa2a9 Binary files /dev/null and b/package/firmware/ipq-wifi/board-xiaomi_ax9000.ipq8074 differ diff --git a/package/kernel/linux/modules/hwmon.mk b/package/kernel/linux/modules/hwmon.mk index a39a8910f..fe82cb05c 100644 --- a/package/kernel/linux/modules/hwmon.mk +++ b/package/kernel/linux/modules/hwmon.mk @@ -122,6 +122,22 @@ endef $(eval $(call KernelPackage,hwmon-drivetemp)) +define KernelPackage/hwmon-emc2305 + TITLE:=SMSC EMC2305 fan support + KCONFIG:=CONFIG_SENSORS_EMC2305 + FILES:= \ + $(LINUX_DIR)/drivers/hwmon/emc2305.ko + AUTOLOAD:=$(call AutoProbe,emc2305) + $(call AddDepends/hwmon,+kmod-i2c-core +kmod-regmap-i2c) +endef + +define KernelPackage/hwmon-emc2305/description + SMSC SMSC EMC2301/2/3/5 fan controllers support +endef + +$(eval $(call KernelPackage,hwmon-emc2305)) + + define KernelPackage/hwmon-gpiofan TITLE:=Generic GPIO FAN support KCONFIG:=CONFIG_SENSORS_GPIO_FAN diff --git a/package/nss/firmware/nss-firmware/Makefile b/package/nss/firmware/nss-firmware/Makefile new file mode 100644 index 000000000..6ea4a57c0 --- /dev/null +++ b/package/nss/firmware/nss-firmware/Makefile @@ -0,0 +1,70 @@ +# +# Copyright (C) 2021 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=nss-firmware +PKG_SOURCE_DATE:=2021-03-12 +PKG_SOURCE_VERSION:=73f378d6be21a9c20a69b77000dbb54a537006a9 +PKG_MIRROR_HASH:=0c21afe29002754edf2983bc9e8543dddd722e75bd12e961e300e99a310d1f62 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/quic/qca-sdk-nss-fw.git + +PKG_LICENSE_FILES:=LICENSE.md + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/package.mk + +VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking_2020.SPF_11.3/CS + +define Package/nss-firmware-default + SECTION:=firmware + CATEGORY:=Firmware + URL:=$(PKG_SOURCE_URL) + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +endef + +define Package/nss-firmware-ipq6018 +$(Package/nss-firmware-default) + TITLE:=NSS firmware for IPQ6018 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ6018.ATH.11.3/BIN-NSS.CP.11.3-9-R.tar.bz2 +endef + +define Package/nss-firmware-ipq8074 +$(Package/nss-firmware-default) + TITLE:=NSS firmware for IPQ8074 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ8074.ATH.11.3/BIN-NSS.HK.11.3-9-R.tar.bz2 +endef + +define Build/Compile + +endef + +define Package/nss-firmware-ipq6018/install + $(TAR) -C $(PKG_BUILD_DIR) -xf $(NSS_ARCHIVE) + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/BIN-NSS.CP.11.3-9-R/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0-retail.bin +endef + +define Package/nss-firmware-ipq8074/install + $(TAR) -C $(PKG_BUILD_DIR) -xf $(NSS_ARCHIVE) + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/BIN-NSS.HK.11.3-9-R/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0-retail.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/BIN-NSS.HK.11.3-9-R/retail_router1.bin \ + $(1)/lib/firmware/qca-nss1-retail.bin +endef + +$(eval $(call BuildPackage,nss-firmware-ipq6018)) +$(eval $(call BuildPackage,nss-firmware-ipq8074)) diff --git a/package/nss/qca/qca-nss-clients/Makefile b/package/nss/qca/qca-nss-clients/Makefile new file mode 100644 index 000000000..10cad4d50 --- /dev/null +++ b/package/nss/qca/qca-nss-clients/Makefile @@ -0,0 +1,59 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-clients +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/nss-clients +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-04-29 +PKG_SOURCE_VERSION:=b93c72c1b72c591c2ddc2f0b24f0e2b457720118 +PKG_MIRROR_HASH:=9fab23da994bfbac9a3cef32cdfec31a87a03ed415f36bc926da32b7b0934259 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-drv-pppoe + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - PPPoE + DEPENDS:=@TARGET_ipq807x +kmod-qca-nss-drv +kmod-ppp +kmod-pppoe + FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) +endef + +define KernelPackage/qca-nss-drv-pppoe/Description +Kernel modules for NSS connection manager - Support for PPPoE +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ + -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ + -I$(STAGING_DIR)/usr/include/nat46 + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe),) +NSS_CLIENTS_MAKE_OPTS+=pppoe=y +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" $(strip $(NSS_CLIENTS_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv-pppoe)) diff --git a/package/nss/qca/qca-nss-clients/files/qca-nss-ipsec b/package/nss/qca/qca-nss-clients/files/qca-nss-ipsec new file mode 100755 index 000000000..5f682c8e9 --- /dev/null +++ b/package/nss/qca/qca-nss-clients/files/qca-nss-ipsec @@ -0,0 +1,214 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log +NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" +NSS_IPSEC_OL_FILE=/tmp/qca_nss_ipsec_ol + +ecm_load () { + if [ ! -d /sys/module/ecm ]; then + /etc/init.d/qca-nss-ecm start + if [ -d /sys/module/ecm ]; then + echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} + fi + fi +} + +ecm_unload () { + if [ -f /tmp/.nss_ipsec_log ]; then + str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` + if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then + /etc/init.d/qca-nss-ecm stop + `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` + fi + fi +} + +ecm_disable() { + + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +kernel_version_check_5_4() { + major_ver=$(uname -r | awk -F '.' '{print $1}') + minor_ver=$(uname -r | awk -F '.' '{print $2}') + if [ $major_ver -lt 5 ] || ([ $major_ver -eq 5 ] && [ $minor_ver -lt 4 ] ) ; then + return 1 + else + return 0 + fi +} + +start_klips() { + if kernel_version_check_5_4 + then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + ipsec eroute + + ecm_enable +} + +stop_klips() { + if kernel_version_check_5_4 + then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + ecm_disable + + /etc/init.d/ipsec stop + rmmod qca-nss-ipsec-klips + rm $NSS_IPSEC_OL_FILE + + ecm_unload +} + +start_xfrm() { + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + # load all NETKEY modules first. + for mod in xfrm_ipcomp ipcomp xfrm6_tunnel ipcomp6 xfrm6_mode_tunnel xfrm6_mode_beet xfrm6_mode_ro \ + xfrm6_mode_transport xfrm4_mode_transport xfrm4_mode_tunnel \ + xfrm4_tunnel xfrm4_mode_beet esp4 esp6 ah4 ah6 af_key + do + insmod $mod 2> /dev/null + done + + # Now load the xfrm plugin + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-xfrm.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + + ecm_enable +} + +stop_xfrm() { + ecm_disable + + #Shutdown Pluto first. Then only plugin can be removed. + plutopid=/var/run/pluto/pluto.pid + if [ -f $plutopid ]; then + pid=`cat $plutopid` + if [ ! -z "$pid" ]; then + ipsec whack --shutdown | grep -v "002"; + if [ -s $plutopid ]; then + echo "Attempt to shut Pluto down failed! Trying kill:" + kill $pid; + sleep 5; + fi + fi + rm -rf $plutopid + fi + ip xfrm state flush; + ip xfrm policy flush; + sleep 2 + + #Now we can remove the plugin + retries=5 + while [ -d /sys/module/qca_nss_ipsec_xfrm ] + do + rmmod qca-nss-ipsec-xfrm + if [ "$?" -eq 0 ]; then + rm $NSS_IPSEC_OL_FILE + break + fi + + if [ ${retries} -eq 0 ]; then + echo "Failed to unload qca-nss-ipsec-xfrm plugin!" + exit + fi + + echo "XFRM plugin unload failed; retrying ${retries} times" + sleep 1 + retries=`expr ${retries} - 1` + done + + /etc/init.d/ipsec stop + ecm_unload +} + +start() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + start_klips + return $? + fi + + start_xfrm + return $? +} + +stop() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + stop_klips + return $? + fi + + stop_xfrm + return $? +} + +restart() { + stop + start +} diff --git a/package/nss/qca/qca-nss-clients/files/qca-nss-mirred.init b/package/nss/qca/qca-nss-clients/files/qca-nss-mirred.init new file mode 100644 index 000000000..1f931f090 --- /dev/null +++ b/package/nss/qca/qca-nss-clients/files/qca-nss-mirred.init @@ -0,0 +1,28 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +restart() { + rmmod act_nssmirred.ko + insmod act_nssmirred.ko +} + +start() { + insmod act_nssmirred.ko +} + +stop() { + rmmod act_nssmirred.ko +} diff --git a/package/nss/qca/qca-nss-clients/files/qca-nss-ovpn.init b/package/nss/qca/qca-nss-clients/files/qca-nss-ovpn.init new file mode 100644 index 000000000..622e295ee --- /dev/null +++ b/package/nss/qca/qca-nss-clients/files/qca-nss-ovpn.init @@ -0,0 +1,69 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +ecm_disable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +restart() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + insmod qca-nss-ovpn-mgr + insmod qca-nss-ovpn-link + + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + return + fi + + ecm_enable +} + +start() { + restart +} + +stop() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + ecm_enable +} diff --git a/package/nss/qca/qca-nss-dp/Makefile b/package/nss/qca/qca-nss-dp/Makefile new file mode 100644 index 000000000..8da7d314a --- /dev/null +++ b/package/nss/qca/qca-nss-dp/Makefile @@ -0,0 +1,62 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-dp +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/nss-dp +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-26 +PKG_SOURCE_VERSION:=e0c89348d5ad99559ce2fbe15d37b3b5bc66aa03 +PKG_MIRROR_HASH:=f369f0c3b33b5f4ad6d0a6ad6ac5495f63c9ecaf94e4e7fa345169f3e44fcf45 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-dp + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-ssdk-nohnat + TITLE:=Kernel driver for NSS data plane + FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko + AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp) +endef + +define KernelPackage/qca-nss-dp/Description +This package contains a NSS data plane driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-dp + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-dp/ +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-ssdk + +NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal +define Build/Configure + $(LN) $(NSS_DP_HAL_DIR)/arch/$(CONFIG_TARGET_BOARD)/nss_$(CONFIG_TARGET_BOARD).h \ + $(PKG_BUILD_DIR)/exports/nss_dp_arch.h +endef + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(SOC)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-dp)) diff --git a/package/nss/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch b/package/nss/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch new file mode 100644 index 000000000..c16a714f7 --- /dev/null +++ b/package/nss/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch @@ -0,0 +1,44 @@ +From 40979666b4371012405715ffa61ab5760fcdc6b3 Mon Sep 17 00:00:00 2001 +Message-Id: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:07:36 +0300 +Subject: [PATCH 1/3] edma_tx_rx: support newer kernels time stamping API + +--- + hal/edma/edma_tx_rx.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/hal/edma/edma_tx_rx.c ++++ b/hal/edma/edma_tx_rx.c +@@ -226,10 +226,16 @@ void nss_phy_tstamp_rx_buf(__attribute__ + * set to the correct PTP class value by calling ptp_classify_raw + * in drv->rxtstamp function. + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) + if (ndev && ndev->phydev && ndev->phydev->drv && + ndev->phydev->drv->rxtstamp) + if(ndev->phydev->drv->rxtstamp(ndev->phydev, skb, 0)) + return; ++#else ++ if (ndev && phy_has_rxtstamp(ndev->phydev)) ++ if (phy_rxtstamp(ndev->phydev, skb, 0)) ++ return; ++#endif + + netif_receive_skb(skb); + } +@@ -247,9 +253,14 @@ void nss_phy_tstamp_tx_buf(struct net_de + * set to the correct PTP class value by calling ptp_classify_raw + * in the drv->txtstamp function. + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) + if (ndev && ndev->phydev && ndev->phydev->drv && + ndev->phydev->drv->txtstamp) + ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0); ++#else ++ if (ndev && phy_has_txtstamp(ndev->phydev)) ++ phy_rxtstamp(ndev->phydev, skb, 0); ++#endif + } + EXPORT_SYMBOL(nss_phy_tstamp_tx_buf); + diff --git a/package/nss/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch b/package/nss/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch new file mode 100644 index 000000000..443a57b4f --- /dev/null +++ b/package/nss/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch @@ -0,0 +1,48 @@ +From cef7873a2d77df13ee702d902ed4e06b2248904b Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:17:22 +0300 +Subject: [PATCH 2/3] nss_dp_main: make phy mode code compatible with newer + kernels + +--- + include/nss_dp_dev.h | 4 ++-- + nss_dp_main.c | 4 ++++ + 2 files changed, 6 insertions(+), 2 deletions(-) + +--- a/include/nss_dp_dev.h ++++ b/include/nss_dp_dev.h +@@ -25,7 +25,7 @@ + #include + #include + #include +-#include ++#include + + #include "nss_dp_api_if.h" + #include "nss_dp_hal_if.h" +@@ -46,7 +46,7 @@ struct nss_dp_dev { + /* Phy related stuff */ + struct phy_device *phydev; /* Phy device */ + struct mii_bus *miibus; /* MII bus */ +- uint32_t phy_mii_type; /* RGMII/SGMII/QSGMII */ ++ phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ + uint32_t phy_mdio_addr; /* Mdio address */ + bool link_poll; /* Link polling enable? */ + uint32_t forced_speed; /* Forced speed? */ +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -463,7 +463,11 @@ static int32_t nss_dp_of_get_pdata(struc + hal_pdata->netdev = netdev; + hal_pdata->macid = dp_priv->macid; + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)) + dp_priv->phy_mii_type = of_get_phy_mode(np); ++#else ++ of_get_phy_mode(np, &dp_priv->phy_mii_type); ++#endif + dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); + if (of_property_read_u32(np, "qcom,phy-mdio-addr", + &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { diff --git a/package/nss/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch b/package/nss/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch new file mode 100644 index 000000000..9c7c53ad5 --- /dev/null +++ b/package/nss/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch @@ -0,0 +1,48 @@ +From c8c52512ff48bee578901c381a42f027e79eadf9 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:20:29 +0300 +Subject: [PATCH 3/3] Drop _nocache variants of ioremap() + +Recent kernels removed them. +--- + hal/edma/edma_data_plane.c | 2 +- + hal/gmac_hal_ops/qcom/qcom_if.c | 2 +- + hal/gmac_hal_ops/syn/xgmac/syn_if.c | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +--- a/hal/edma/edma_data_plane.c ++++ b/hal/edma/edma_data_plane.c +@@ -797,7 +797,7 @@ int edma_init(void) + /* + * Remap register resource + */ +- edma_hw.reg_base = ioremap_nocache((edma_hw.reg_resource)->start, ++ edma_hw.reg_base = ioremap((edma_hw.reg_resource)->start, + resource_size(edma_hw.reg_resource)); + if (!edma_hw.reg_base) { + pr_warn("Unable to remap EDMA register memory.\n"); +--- a/hal/gmac_hal_ops/qcom/qcom_if.c ++++ b/hal/gmac_hal_ops/qcom/qcom_if.c +@@ -400,7 +400,7 @@ static void *qcom_init(struct gmac_hal_p + qhd->nghd.mac_id = gmacpdata->macid; + + /* Populate the mac base addresses */ +- qhd->nghd.mac_base = devm_ioremap_nocache(&dp_priv->pdev->dev, ++ qhd->nghd.mac_base = devm_ioremap(&dp_priv->pdev->dev, + res->start, resource_size(res)); + if (!qhd->nghd.mac_base) { + netdev_dbg(ndev, "ioremap fail.\n"); +--- a/hal/gmac_hal_ops/syn/xgmac/syn_if.c ++++ b/hal/gmac_hal_ops/syn/xgmac/syn_if.c +@@ -422,7 +422,7 @@ static void *syn_init(struct gmac_hal_pl + + /* Populate the mac base addresses */ + shd->nghd.mac_base = +- devm_ioremap_nocache(&dp_priv->pdev->dev, res->start, ++ devm_ioremap(&dp_priv->pdev->dev, res->start, + resource_size(res)); + if (!shd->nghd.mac_base) { + netdev_dbg(ndev, "ioremap fail.\n"); diff --git a/package/nss/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch b/package/nss/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch new file mode 100644 index 000000000..eb57fe90a --- /dev/null +++ b/package/nss/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch @@ -0,0 +1,31 @@ +From d74920e2a7c413ef40eed72f9cf287cf6fbd5fb8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 May 2021 14:56:46 +0200 +Subject: [PATCH 1/2] EDMA: Fix NAPI packet counting + +There is a bug in the NAPI packet counting that will +cause NAPI over budget warnings. + +Signed-off-by: Baruch Siach +Signed-off-by: Robert Marko +--- + hal/edma/edma_tx_rx.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/hal/edma/edma_tx_rx.c ++++ b/hal/edma/edma_tx_rx.c +@@ -458,12 +458,12 @@ int edma_napi(struct napi_struct *napi, + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; +- work_done += edma_clean_tx(ehw, txcmpl_ring); ++ edma_clean_tx(ehw, txcmpl_ring); + } + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; +- work_done += edma_alloc_rx_buffer(ehw, rxfill_ring); ++ edma_alloc_rx_buffer(ehw, rxfill_ring); + } + + /* diff --git a/package/nss/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch b/package/nss/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch new file mode 100644 index 000000000..f231c514a --- /dev/null +++ b/package/nss/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch @@ -0,0 +1,41 @@ +From 44a30d94abcbb10aacc21db29be212518a6b1bf7 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 May 2021 14:57:46 +0200 +Subject: [PATCH] EDMA: Use NAPI_POLL_WEIGHT as NAPI weight + +Currently a weight of 100 is used by the EDMA, according +to upstream max of 64 should be used and that is used for +almost any driver. + +They also introduced NAPI_POLL_WEIGHT define which equals +to 64. + +So use NAPI_POLL_WEIGHT as the weight. + +Signed-off-by: Robert Marko +--- + hal/edma/edma_data_plane.c | 2 +- + hal/edma/edma_data_plane.h | 1 - + 2 files changed, 1 insertion(+), 2 deletions(-) + +--- a/hal/edma/edma_data_plane.c ++++ b/hal/edma/edma_data_plane.c +@@ -582,7 +582,7 @@ static int edma_register_netdevice(struc + */ + if (!edma_hw.napi_added) { + netif_napi_add(netdev, &edma_hw.napi, edma_napi, +- EDMA_NAPI_WORK); ++ NAPI_POLL_WEIGHT); + /* + * Register the interrupt handlers and enable interrupts + */ +--- a/hal/edma/edma_data_plane.h ++++ b/hal/edma/edma_data_plane.h +@@ -27,7 +27,6 @@ + #define EDMA_RX_PREHDR_SIZE (sizeof(struct edma_rx_preheader)) + #define EDMA_TX_PREHDR_SIZE (sizeof(struct edma_tx_preheader)) + #define EDMA_RING_SIZE 128 +-#define EDMA_NAPI_WORK 100 + #define EDMA_START_GMACS NSS_DP_START_IFNUM + #define EDMA_MAX_GMACS NSS_DP_HAL_MAX_PORTS + #define EDMA_TX_PKT_MIN_SIZE 33 /* IPQ807x EDMA needs a minimum packet size of 33 bytes */ diff --git a/package/nss/qca/qca-nss-drv/Makefile b/package/nss/qca/qca-nss-drv/Makefile new file mode 100644 index 000000000..458f8d07a --- /dev/null +++ b/package/nss/qca/qca-nss-drv/Makefile @@ -0,0 +1,121 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-drv +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-drv +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-04-26 +PKG_SOURCE_VERSION:=1cf4bf81fd395f61648efeae78cdf1df60e954ff +PKG_MIRROR_HASH:=86b7455565d28a72da981099c67a89ea9e0ae3874a34be30959dcf48f5e2196c + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients + +define KernelPackage/qca-nss-drv + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-dp + TITLE:=Kernel driver for NSS (core driver) + FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko + AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) +endef + +define KernelPackage/qca-nss-drv/install + $(INSTALL_DIR) $(1)/lib/debug + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_DIR) $(1)/etc/sysctl.d + $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware + $(INSTALL_DIR) $(1)/etc/config + + $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf + $(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw + $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss + +endef + +define KernelPackage/qca-nss-drv/Description +This package contains a NSS driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-drv + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ +endef + +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac -I$(STAGING_DIR)/usr/include/qca-nss-dp -I$(STAGING_DIR)/usr/include/qca-ssdk + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM +LOW_MEM_PROFILE_MAKE_OPTS=y +endif + +ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) +EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K +endif + +DRV_MAKE_OPTS:= +ifeq ($(LOW_MEM_PROFILE_MAKE_OPTS),y) +DRV_MAKE_OPTS+=NSS_DRV_C2C_ENABLE=n \ + NSS_DRV_CAPWAP_ENABLE=n \ + NSS_DRV_CLMAP_ENABLE=n \ + NSS_DRV_CRYPTO_ENABLE=n \ + NSS_DRV_DTLS_ENABLE=n \ + NSS_DRV_GRE_ENABLE=n \ + NSS_DRV_GRE_REDIR_ENABLE=n \ + NSS_DRV_GRE_TUNNEL_ENABLE=n \ + NSS_DRV_IGS_ENABLE=n \ + NSS_DRV_IPSEC_ENABLE=n \ + NSS_DRV_LAG_ENABLE=n \ + NSS_DRV_L2TP_ENABLE=n \ + NSS_DRV_MAPT_ENABLE=n \ + NSS_DRV_OAM_ENABLE=n \ + NSS_DRV_PPTP_ENABLE=n \ + NSS_DRV_PORTID_ENABLE=n \ + NSS_DRV_PVXLAN_ENABLE=n \ + NSS_DRV_QRFS_ENABLE=n \ + NSS_DRV_QVPN_ENABLE=n \ + NSS_DRV_RMNET_ENABLE=n \ + NSS_DRV_SHAPER_ENABLE=n \ + NSS_DRV_SJACK_ENABLE=n \ + NSS_DRV_TLS_ENABLE=n \ + NSS_DRV_TRUSTSEC_ENABLE=n \ + NSS_DRV_TSTAMP_ENABLE=n \ + NSS_DRV_TUN6RD_ENABLE=n \ + NSS_DRV_TUNIPIP6_ENABLE=n \ + NSS_DRV_VXLAN_ENABLE=n \ + NSS_DRV_MATCH_ENABLE=n \ + NSS_DRV_MIRROR_ENABLE=n +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Configure + $(LN) arch/nss_$(SOC).h $(PKG_BUILD_DIR)/exports/nss_arch.h + sed -i "s/define NSS_FW_VERSION_MAJOR.*/define NSS_FW_VERSION_MAJOR 11/" $(PKG_BUILD_DIR)/exports/nss_fw_version.h + sed -i "s/define NSS_FW_VERSION_MINOR.*/define NSS_FW_VERSION_MINOR 3/" $(PKG_BUILD_DIR)/exports/nss_fw_version.h +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv)) diff --git a/package/nss/qca/qca-nss-drv/files/qca-nss-drv.conf b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.conf new file mode 100644 index 000000000..a8a1fbf40 --- /dev/null +++ b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.conf @@ -0,0 +1,6 @@ +config nss_firmware 'qca_nss_0' + +config nss_firmware 'qca_nss_1' + +config general + option enable_rps '1' diff --git a/package/nss/qca/qca-nss-drv/files/qca-nss-drv.debug b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.debug new file mode 100644 index 000000000..5d435c3a7 --- /dev/null +++ b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.debug @@ -0,0 +1,26 @@ +#!/bin/sh /sbin/sysdebug +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe +log cat /sys/kernel/debug/qca-nss-drv/stats/n2h +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 +log cat /sys/kernel/debug/qca-nss-drv/stats/gmac +log cat /sys/kernel/debug/qca-nss-drv/stats/drv +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if +log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/package/nss/qca/qca-nss-drv/files/qca-nss-drv.hotplug b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.hotplug new file mode 100644 index 000000000..1e4813838 --- /dev/null +++ b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.hotplug @@ -0,0 +1,70 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +KERNEL=`uname -r` +case "${KERNEL}" in + 3.4*) + select_or_load=load_nss_fw + ;; + *) + select_or_load=select_nss_fw + ;; +esac + +load_nss_fw () { + ls -l $1 | awk ' { print $9,$5 } '> /dev/console + echo 1 > /sys/class/firmware/$DEVICENAME/loading + cat $1 > /sys/class/firmware/$DEVICENAME/data + echo 0 > /sys/class/firmware/$DEVICENAME/loading +} + +select_nss_fw () { + rm -f /lib/firmware/$DEVICENAME + ln -s $1 /lib/firmware/$DEVICENAME + ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console +} + +[ "$ACTION" != "add" ] && exit + +# dev name for UCI, since it doesn't let you use . or - +SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) + +SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) +[ -e "${SELECTED_FW}" ] && { + $select_or_load ${SELECTED_FW} + exit +} + +case $DEVICENAME in + qca-nss0* | qca-nss.0*) + if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss0-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss0-retail.bin + fi + exit + ;; + qca-nss1* | qca-nss.1*) + if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss1-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss1-retail.bin + fi + exit + ;; +esac + diff --git a/package/nss/qca/qca-nss-drv/files/qca-nss-drv.init b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.init new file mode 100644 index 000000000..de12cb6d1 --- /dev/null +++ b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.init @@ -0,0 +1,50 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=70 + +enable_rps() { + irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 2 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 4 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 8 > /proc/irq/$entry/smp_affinity + done + + # Enable NSS RPS + sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null + +} + + +start() { + local rps_enabled="$(uci_get nss @general[0] enable_rps)" + if [ "$rps_enabled" -eq 1 ]; then + enable_rps + fi +} diff --git a/package/nss/qca/qca-nss-drv/files/qca-nss-drv.sysctl b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.sysctl new file mode 100644 index 000000000..fc36c33eb --- /dev/null +++ b/package/nss/qca/qca-nss-drv/files/qca-nss-drv.sysctl @@ -0,0 +1,4 @@ +# Default Number of connection configuration +dev.nss.ipv4cfg.ipv4_conn=4096 +dev.nss.ipv6cfg.ipv6_conn=4096 + diff --git a/package/nss/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch b/package/nss/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch new file mode 100644 index 000000000..3fea9b5ce --- /dev/null +++ b/package/nss/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch @@ -0,0 +1,25 @@ +From 3885c752e12f74cad6c97888b797e5903ad1930d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 23:22:38 +0200 +Subject: [PATCH] core: add 5.10 kernel to version check + +NSS DRV has a kernel version check, so simply add +5.10 as supported. + +Signed-off-by: Robert Marko +--- + nss_core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -52,7 +52,8 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + diff --git a/package/nss/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch b/package/nss/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..77155750c --- /dev/null +++ b/package/nss/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,164 @@ +From b5e2a7167ca3df9fce34f0d7c05468d4f5597275 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 23:33:18 +0200 +Subject: [PATCH] nss-drv: replace ioremap_nocache() with ioremap() + +ioremap_nocache() does not exist anymore. + +Signed-off-by: Robert Marko +--- + nss_hal/ipq50xx/nss_hal_pvt.c | 6 +++--- + nss_hal/ipq60xx/nss_hal_pvt.c | 8 ++++---- + nss_hal/ipq806x/nss_hal_pvt.c | 4 ++-- + nss_hal/ipq807x/nss_hal_pvt.c | 6 +++--- + nss_hal/nss_hal.c | 4 ++-- + nss_meminfo.c | 2 +- + nss_ppe.c | 2 +- + 7 files changed, 16 insertions(+), 16 deletions(-) + +--- a/nss_hal/ipq50xx/nss_hal_pvt.c ++++ b/nss_hal/ipq50xx/nss_hal_pvt.c +@@ -184,13 +184,13 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -348,7 +348,7 @@ static int __nss_hal_common_reset(struct + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -207,13 +207,13 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -433,13 +433,13 @@ static int __nss_hal_common_reset(struct + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; + } + +- nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); ++ nss_misc_reset_flag = ioremap(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); + if (!nss_misc_reset_flag) { + pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -458,7 +458,7 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->vphys = res_vphys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -711,7 +711,7 @@ static int __nss_hal_common_reset(struct + } + of_node_put(cmn); + +- fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); ++ fpb_base = ioremap(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); + if (!fpb_base) { + pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -234,7 +234,7 @@ static struct nss_platform_data *__nss_h + npd->vphys = res_vphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -247,7 +247,7 @@ static struct nss_platform_data *__nss_h + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -467,7 +467,7 @@ static int __nss_hal_common_reset(struct + } + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -78,9 +78,9 @@ int nss_hal_firmware_load(struct nss_ctx + return rc; + } + +- load_mem = ioremap_nocache(npd->load_addr, nss_fw->size); ++ load_mem = ioremap(npd->load_addr, nss_fw->size); + if (!load_mem) { +- nss_info_always("%px: ioremap_nocache failed: %x", nss_ctx, npd->load_addr); ++ nss_info_always("%px: ioremap failed: %x", nss_ctx, npd->load_addr); + release_firmware(nss_fw); + return rc; + } +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -728,7 +728,7 @@ bool nss_meminfo_init(struct nss_ctx_ins + /* + * meminfo_start is the label where the start address of meminfo map is stored. + */ +- meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, ++ meminfo_start = (uint32_t *)ioremap(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, + NSS_MEMINFO_RESERVE_AREA_SIZE); + if (!meminfo_start) { + nss_info_always("%px: cannot remap meminfo start\n", nss_ctx); +--- a/nss_ppe.c ++++ b/nss_ppe.c +@@ -357,7 +357,7 @@ void nss_ppe_init(void) + /* + * Get the PPE base address + */ +- ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE); ++ ppe_pvt.ppe_base = ioremap(PPE_BASE_ADDR, PPE_REG_SIZE); + if (!ppe_pvt.ppe_base) { + nss_warning("DRV can't get PPE base address\n"); + return; diff --git a/package/nss/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch b/package/nss/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch new file mode 100644 index 000000000..0c13a7887 --- /dev/null +++ b/package/nss/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch @@ -0,0 +1,49 @@ +From 62e457f262aaa0db7113ad3ccbcb7ae49d4d7ea8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Jun 2021 23:24:43 +0200 +Subject: [PATCH] DMA: Fix NULL pointer exceptions + +There are multiple instances that pass NULL instead +of device to DMA functions. +That is incorrect and will cause kernel NULL pointer +exceptions. + +So, simply pass the device structure pointers. + +Signed-off-by: Robert Marko +--- + nss_core.c | 2 +- + nss_coredump.c | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -1617,7 +1617,7 @@ static int32_t nss_core_handle_cause_que + * + */ + if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { +- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); ++ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); + goto consume; + } + +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_c + dma_addr = nss_own->meminfo_ctx.logbuffer_dma; + } + +- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); + + /* + * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, +@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_c + + offset = (index * sizeof(struct nss_log_entry)) + + offsetof(struct nss_log_descriptor, log_ring_buffer); +- dma_sync_single_for_cpu(NULL, dma_addr + offset, ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, + sizeof(struct nss_log_entry), DMA_FROM_DEVICE); + nss_info_always("%px: %s\n", nss_own, nle_print->message); + nle_print++; diff --git a/package/nss/qca/qca-nss-drv/patches/999-treewide-hack-support-for-mismatched-firmware.patch b/package/nss/qca/qca-nss-drv/patches/999-treewide-hack-support-for-mismatched-firmware.patch new file mode 100644 index 000000000..46025b823 --- /dev/null +++ b/package/nss/qca/qca-nss-drv/patches/999-treewide-hack-support-for-mismatched-firmware.patch @@ -0,0 +1,344 @@ +From d0bffc800a50305315a0d7cf37140291ef5b1b61 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Thu, 27 May 2021 03:52:47 +0200 +Subject: [PATCH] treewide: hack support for mismatched firmware + +Make new qsdk feature configurable to support old half compatible +firmware. + +Signed-off-by: Ansuel Smith +--- + exports/nss_fw_version.h | 11 +++++++++++ + exports/nss_ipv4.h | 8 ++++++++ + exports/nss_ipv6.h | 7 +++++++ + exports/nss_wifi_vdev.h | 14 ++++++++++++++ + exports/nss_wifili_if.h | 8 ++++++++ + nss_ipv4_stats.c | 2 ++ + nss_ipv4_strings.c | 2 ++ + nss_ipv6_stats.c | 2 ++ + nss_ipv6_strings.c | 2 ++ + 9 files changed, 56 insertions(+) + create mode 100644 exports/nss_fw_version.h + +diff --git a/exports/nss_fw_version.h b/exports/nss_fw_version.h +new file mode 100644 +index 0000000..895d523 +--- /dev/null ++++ b/exports/nss_fw_version.h +@@ -0,0 +1,11 @@ ++#ifndef __NSS_FW_VERSION_H ++#define __NSS_FW_VERSION_H ++ ++#define NSS_FW_VERSION_MAJOR 11 ++#define NSS_FW_VERSION_MINOR 4 ++ ++#define NSS_FW_VERSION(a,b) (((a) << 8) + (b)) ++ ++#define NSS_FW_VERSION_CODE NSS_FW_VERSION(NSS_FW_VERSION_MAJOR, NSS_FW_VERSION_MINOR) ++ ++#endif /* __NSS_FW_VERSION_H */ +\ No newline at end of file +diff --git a/exports/nss_ipv4.h b/exports/nss_ipv4.h +index ee3a552..25c4d82 100644 +--- a/exports/nss_ipv4.h ++++ b/exports/nss_ipv4.h +@@ -26,6 +26,8 @@ + #include "nss_stats_public.h" + #endif + ++#include "nss_fw_version.h" ++ + /** + * @addtogroup nss_ipv4_subsystem + * @{ +@@ -216,12 +218,14 @@ enum nss_ipv4_stats_types { + /**< Number of IPv4 multicast connection destroy requests that missed the cache. */ + NSS_IPV4_STATS_MC_CONNECTION_FLUSHES, + /**< Number of IPv4 multicast connection flushes. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM, + /**< Number of IPv4 mirror connection requests with an invalid interface number. */ + NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE, + /**< Number of IPv4 mirror connection requests with an invalid interface type. */ + NSS_IPV4_STATS_MIRROR_FAILURES, + /**< Number of IPv4 mirror failures. */ ++#endif + NSS_IPV4_STATS_MAX, + /**< Maximum message type. */ + }; +@@ -609,8 +613,10 @@ struct nss_ipv4_rule_create_msg { + /**< Ingress shaping related accleration parameters. */ + struct nss_ipv4_identifier_rule identifier; + /**< Rule for adding identifier. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + struct nss_ipv4_mirror_rule mirror_rule; + /**< Mirror rule parameter. */ ++#endif + }; + + /** +@@ -955,6 +961,7 @@ struct nss_ipv4_node_sync { + uint32_t ipv4_mc_connection_flushes; + /**< Number of multicast connection flushes. */ + ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t ipv4_connection_create_invalid_mirror_ifnum; + /**< Number of create request failed with an invalid mirror interface number. */ + +@@ -963,6 +970,7 @@ struct nss_ipv4_node_sync { + + uint32_t ipv4_mirror_failures; + /**< Mirror packet failed. */ ++#endif + + uint32_t exception_events[NSS_IPV4_EXCEPTION_EVENT_MAX]; + /**< Number of exception events. */ +diff --git a/exports/nss_ipv6.h b/exports/nss_ipv6.h +index 930e74c..a21f939 100644 +--- a/exports/nss_ipv6.h ++++ b/exports/nss_ipv6.h +@@ -195,6 +195,8 @@ enum nss_ipv6_stats_types { + /**< Number of IPv6 multicast connection destroy requests that missed the cache. */ + NSS_IPV6_STATS_MC_CONNECTION_FLUSHES, + /**< Number of IPv6 multicast connection flushes. */ ++ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM, + /**< Number of IPv6 mirror connection requests with an invalid interface number. */ + NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE, +@@ -202,6 +204,7 @@ enum nss_ipv6_stats_types { + + NSS_IPV6_STATS_MIRROR_FAILURES, + /**< Number of IPv6 mirror failures. */ ++#endif + + NSS_IPV6_STATS_MAX, + /**< Maximum message type. */ +@@ -702,8 +705,10 @@ struct nss_ipv6_rule_create_msg { + /**< Ingress shaping related accleration parameters. */ + struct nss_ipv6_identifier_rule identifier; + /**< Rule for adding identifier. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + struct nss_ipv6_mirror_rule mirror_rule; + /**< Mirror rule parameter. */ ++#endif + }; + + /** +@@ -950,6 +955,7 @@ struct nss_ipv6_node_sync { + uint32_t ipv6_mc_connection_flushes; + /**< Number of multicast connection flushes. */ + ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t ipv6_connection_create_invalid_mirror_ifnum; + /**< Number of create request failed with an invalid mirror interface number. */ + +@@ -958,6 +964,7 @@ struct nss_ipv6_node_sync { + + uint32_t ipv6_mirror_failures; + /**< Mirror packet failed. */ ++#endif + + uint32_t exception_events[NSS_IPV6_EXCEPTION_EVENT_MAX]; + /**< Number of exception events. */ +diff --git a/exports/nss_wifi_vdev.h b/exports/nss_wifi_vdev.h +index 1b52f66..da91b56 100644 +--- a/exports/nss_wifi_vdev.h ++++ b/exports/nss_wifi_vdev.h +@@ -74,8 +74,10 @@ enum nss_wifi_vdev_msg_types { + NSS_WIFI_VDEV_INTERFACE_RECOVERY_RESET_MSG, + NSS_WIFI_VDEV_INTERFACE_RECOVERY_RECONF_MSG, + NSS_WIFI_VDEV_SET_GROUP_KEY, ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_WIFI_VDEV_HMMC_MEMBER_ADD_MSG, + NSS_WIFI_VDEV_HMMC_MEMBER_DEL_MSG, ++#endif + NSS_WIFI_VDEV_MAX_MSG + }; + +@@ -130,6 +132,7 @@ enum nss_wifi_vdev_err_types { + NSS_WIFI_VDEV_VLAN_MODE_CONFIG_FAIL, + NSS_WIFI_VDEV_RECOVERY_RESET_FAIL, + NSS_WIFI_VDEV_RECOVERY_RECONF_FAIL, ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_WIFI_VDEV_CONFIG_GROUP_KEY_FAIL, + NSS_WIFI_VDEV_MULTIPASS_NOT_ENABLED, + NSS_WIFI_VDEV_ALLOC_VLAN_MAP_FAILED, +@@ -139,6 +142,7 @@ enum nss_wifi_vdev_err_types { + NSS_WIFI_VDEV_PPE_PORT_DESTROY_FAIL, + NSS_WIFI_VDEV_PPE_VSI_ASSIGN_FAIL, + NSS_WIFI_VDEV_PPE_VSI_UNASSIGN_FAIL, ++#endif + NSS_WIFI_VDEV_EINV_MAX_CFG + }; + +@@ -161,11 +165,13 @@ enum nss_wifi_vdev_ext_data_pkt_type { + NSS_WIFI_VDEV_EXT_TX_COMPL_PKT_TYPE = 11, /**< Tx completion. */ + NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_WDS_LEARN = 12, /**< WDS source port learning command. */ + NSS_WIFI_VDEV_EXT_DATA_PPDU_INFO = 13, /**< PPDU metadata information. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MCBC_RX = 14, /**< Multicast/broadcast packet received. */ + NSS_WIFI_VDEV_MESH_EXT_DATA_PKT_TYPE_RX_SPL_PACKET = 15, + /**< Mesh link VAP special packet. */ + NSS_WIFI_VDEV_MESH_EXT_DATA_PKT_TYPE_RX_MCAST_EXC = 16, + /**< Mesh link VAP multicast packet. */ ++#endif + NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MAX + }; + +@@ -201,9 +207,11 @@ enum nss_wifi_vdev_cmd { + NSS_WIFI_VDEV_ENABLE_IGMP_ME_CMD, /**< Configuration to set IGMP multicast enhancement on VAP. */ + NSS_WIFI_VDEV_CFG_WDS_BACKHAUL_CMD, + /**< Configuration to set WDS backhaul extension on VAP. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_WIFI_VDEV_CFG_MCBC_EXC_TO_HOST_CMD, /**< Configuration to set multicast/broadcast exception to host on VAP. */ + NSS_WIFI_VDEV_CFG_PEER_AUTHORIZE_CMD, + /**< Configuration to enable peer authorization on VAP. */ ++#endif + NSS_WIFI_VDEV_MAX_CMD + }; + +@@ -271,7 +279,9 @@ struct nss_wifi_vdev_config_msg { + uint8_t is_nss_qwrap_en; /**< VAP is configured for NSS firmware QWRAP logic. */ + uint8_t tx_per_pkt_vdev_id_check; /**< Transmit per-packet virtual device ID check. */ + uint8_t align_pad; /**< Reserved field. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t vap_ext_mode; /**< Different VAP extended modes. */ ++#endif + }; + + /** +@@ -1037,8 +1047,10 @@ struct nss_wifi_vdev_stats_sync_msg { + uint32_t rx_mcast_bytes; /**< Receive multicast bytes count. */ + uint32_t rx_decrypt_err; /**< Receive decryption error */ + uint32_t rx_mic_err; /**< Receive MIC error */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t mcbc_exc_host_fail_cnt; + /**< Number of multicast/broadcast packets failed to send to host through exception path. */ ++#endif + }; + + /** +@@ -1070,6 +1082,7 @@ struct nss_wifi_vdev_msg { + /**< Updates a snooplist group member. */ + struct nss_wifi_vdev_me_snptbl_deny_grp_add_msg vdev_deny_member_add; + /**< Add a snooplist member to the deny list. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + struct nss_wifi_vdev_me_hmmc_add_msg vdev_hmmc_member_add; + /**< Adds a new member into the HMMC list. */ + struct nss_wifi_vdev_me_hmmc_del_msg vdev_hmmc_member_del; +@@ -1078,6 +1091,7 @@ struct nss_wifi_vdev_msg { + /**< Adds a new member into the deny list. */ + struct nss_wifi_vdev_me_deny_ip_del_msg vdev_deny_list_member_del; + /**< Delete a member from the deny list. */ ++#endif + struct nss_wifi_vdev_txmsg vdev_txmsgext; + /**< Transmits special data. */ + struct nss_wifi_vdev_vow_dbg_cfg_msg vdev_vow_dbg_cfg; +diff --git a/exports/nss_wifili_if.h b/exports/nss_wifili_if.h +index fce20fd..1f26d67 100644 +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -62,8 +62,12 @@ + /**< Maximum number of bandwidth supported. */ + #define NSS_WIFILI_REPT_MU_MIMO 1 + #define NSS_WIFILI_REPT_MU_OFDMA_MIMO 3 ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) ++#define NSS_WIFILI_MAX_RESERVED_TYPE 3 ++#else + #define NSS_WIFILI_MAX_RESERVED_TYPE 2 + /**< Maximum reserved type. */ ++#endif + #define NSS_WIFILI_SOC_PER_PACKET_METADATA_SIZE 60 + /**< Metadata area total size. */ + #define NSS_WIFILI_MEC_PEER_ID 0xDEAD +@@ -1333,7 +1337,9 @@ struct nss_wifili_rx_err { + struct nss_wifili_rx_ctrl_stats { + struct nss_wifili_rx_err err; /**< Rx peer errors. */ + uint32_t multipass_rx_pkt_drop; /**< Total number of multipass packets without a VLAN header. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t peer_unauth_rx_pkt_drop; /**< Number of receive packets dropped due to an authorized peer. */ ++#endif + uint32_t reserved_type[NSS_WIFILI_MAX_RESERVED_TYPE]; /**< Reserved type for future use. */ + uint32_t non_amsdu_cnt; /**< Number of MSDUs with no MSDU level aggregation. */ + uint32_t amsdu_cnt; /**< Number of MSDUs part of AMSDU. */ +@@ -1810,10 +1816,12 @@ struct nss_wifili_msg { + /**< Peer four-address event message. */ + struct nss_wifili_dbdc_repeater_loop_detection_msg wdrldm; + /**< Wifili DBDC repeater loop detection message. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + struct nss_wifili_peer_update_auth_flag peer_auth; + /**< Peer authentication flag message. */ + struct nss_wifili_mesh_capability_info cap_info; + /**< Mesh capability flag. */ ++#endif + } msg; /**< Message payload. */ + }; + +diff --git a/nss_ipv4_stats.c b/nss_ipv4_stats.c +index 39b162c..c875a63 100644 +--- a/nss_ipv4_stats.c ++++ b/nss_ipv4_stats.c +@@ -177,9 +177,11 @@ void nss_ipv4_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_ + nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_DESTROY_REQUESTS] += nins->ipv4_mc_connection_destroy_requests; + nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_DESTROY_MISSES] += nins->ipv4_mc_connection_destroy_misses; + nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_FLUSHES] += nins->ipv4_mc_connection_flushes; ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM] += nins->ipv4_connection_create_invalid_mirror_ifnum; + nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE] += nins->ipv4_connection_create_invalid_mirror_iftype; + nss_ipv4_stats[NSS_IPV4_STATS_MIRROR_FAILURES] += nins->ipv4_mirror_failures; ++#endif + + for (i = 0; i < NSS_IPV4_EXCEPTION_EVENT_MAX; i++) { + nss_ipv4_exception_stats[i] += nins->exception_events[i]; +diff --git a/nss_ipv4_strings.c b/nss_ipv4_strings.c +index 77ff352..ce4c249 100644 +--- a/nss_ipv4_strings.c ++++ b/nss_ipv4_strings.c +@@ -137,9 +137,11 @@ struct nss_stats_info nss_ipv4_strings_stats[NSS_IPV4_STATS_MAX] = { + {"mc_destroy_requests" , NSS_STATS_TYPE_SPECIAL}, + {"mc_destroy_misses" , NSS_STATS_TYPE_SPECIAL}, + {"mc_flushes" , NSS_STATS_TYPE_SPECIAL}, ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + {"mirror_invalid_ifnum_conn_create_req" , NSS_STATS_TYPE_SPECIAL}, + {"mirror_invalid_iftype_conn_create_req" , NSS_STATS_TYPE_SPECIAL}, + {"mirror_failures" , NSS_STATS_TYPE_SPECIAL}, ++#endif + }; + + /* +diff --git a/nss_ipv6_stats.c b/nss_ipv6_stats.c +index 617f55b..a492a6c 100644 +--- a/nss_ipv6_stats.c ++++ b/nss_ipv6_stats.c +@@ -180,9 +180,11 @@ void nss_ipv6_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_ + nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_DESTROY_REQUESTS] += nins->ipv6_mc_connection_destroy_requests; + nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_DESTROY_MISSES] += nins->ipv6_mc_connection_destroy_misses; + nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_FLUSHES] += nins->ipv6_mc_connection_flushes; ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM] += nins->ipv6_connection_create_invalid_mirror_ifnum; + nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE] += nins->ipv6_connection_create_invalid_mirror_iftype; + nss_ipv6_stats[NSS_IPV6_STATS_MIRROR_FAILURES] += nins->ipv6_mirror_failures; ++#endif + + for (i = 0; i < NSS_IPV6_EXCEPTION_EVENT_MAX; i++) { + nss_ipv6_exception_stats[i] += nins->exception_events[i]; +diff --git a/nss_ipv6_strings.c b/nss_ipv6_strings.c +index 57b100f..29df9c9 100644 +--- a/nss_ipv6_strings.c ++++ b/nss_ipv6_strings.c +@@ -115,9 +115,11 @@ struct nss_stats_info nss_ipv6_strings_stats[NSS_IPV6_STATS_MAX] = { + {"mc_destroy_requests" ,NSS_STATS_TYPE_SPECIAL}, + {"mc_destroy_misses" ,NSS_STATS_TYPE_SPECIAL}, + {"mc_flushes" ,NSS_STATS_TYPE_SPECIAL}, ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + {"mirror_invalid_ifnum_conn_create_req" ,NSS_STATS_TYPE_SPECIAL}, + {"mirror_invalid_iftype_conn_create_req" ,NSS_STATS_TYPE_SPECIAL}, + {"mirror_failures" ,NSS_STATS_TYPE_SPECIAL}, ++#endif + }; + + /* +-- +2.31.1 + diff --git a/package/nss/qca/qca-nss-ecm/Makefile b/package/nss/qca/qca-nss-ecm/Makefile new file mode 100644 index 000000000..1ebb32917 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/Makefile @@ -0,0 +1,97 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-ecm +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/qca-nss-ecm +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-04-29 +PKG_SOURCE_VERSION:=c115aec34867b582e2e5ea79fc5315971e0e953c +PKG_MIRROR_HASH:=a772996af7bbae7031eebc2f789431d29be67f11eb0a1e874c08b74eec6f4585 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-ecm + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) \ + +kmod-qca-nss-drv \ + +iptables-mod-extra \ + +kmod-ipt-conntrack \ + +kmod-ipt-physdev \ + +iptables-mod-physdev \ + +kmod-ppp \ + +kmod-pppoe + TITLE:=QCA NSS Enhanced Connection Manager (ECM) + FILES:=$(PKG_BUILD_DIR)/*.ko + KCONFIG:=CONFIG_BRIDGE_NETFILTER=y \ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_NF_CONNTRACK_CHAIN_EVENTS=n \ + CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=n +endef + +define KernelPackage/qca-nss-ecm/Description +This package contains the QCA NSS Enhanced Connection Manager +endef + +define KernelPackage/qca-nss-ecm/install + $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d + $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm + $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ + $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down + $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm + $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf + echo 'net.netfilter.nf_conntrack_max=8192' >> $(1)/etc/sysctl.d/qca-nss-ecm.conf +endef + +EXTRA_CFLAGS+=-I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +ECM_MAKE_OPTS+= ECM_FRONT_END_NSS_ENABLE=y \ + ECM_CLASSIFIER_HYFI_ENABLE=n \ + ECM_MULTICAST_ENABLE=n \ + ECM_INTERFACE_IPSEC_ENABLE=n \ + ECM_INTERFACE_PPTP_ENABLE=n \ + ECM_INTERFACE_L2TPV2_ENABLE=n \ + ECM_INTERFACE_GRE_TAP_ENABLE=n \ + ECM_INTERFACE_GRE_TUN_ENABLE=n \ + ECM_INTERFACE_SIT_ENABLE=n \ + ECM_INTERFACE_TUNIPIP6_ENABLE=n \ + ECM_INTERFACE_RAWIP_ENABLE=n \ + ECM_INTERFACE_VLAN_ENABLE=n \ + ECM_CLASSIFIER_MARK_ENABLE=n \ + ECM_CLASSIFIER_DSCP_ENABLE=n \ + ECM_CLASSIFIER_PCC_ENABLE=n \ + ECM_BAND_STEERING_ENABLE=n \ + ECM_INTERFACE_PPPOE_ENABLE=y +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-ecm + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-ecm)) diff --git a/package/nss/qca/qca-nss-ecm/files/ecm_dump.sh b/package/nss/qca/qca-nss-ecm/files/ecm_dump.sh new file mode 100755 index 000000000..dbf7de753 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/files/ecm_dump.sh @@ -0,0 +1,95 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +ECM_MODULE=${1:-ecm_state} +MOUNT_ROOT=/dev/ecm + +# +# usage: ecm_dump.sh [module=ecm_db] +# +# with no parameters, ecm_dump.sh will attempt to mount the +# ecm_db state file and cat its contents. +# +# example with a parameter: ecm_dump.sh ecm_classifier_default +# +# this will cause ecm_dump to attempt to find and mount the state +# file for the ecm_classifier_default module, and if successful +# cat the contents. +# + +# this is one of the state files, which happens to be the +# last module started in ecm +ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major + +# tests to see if ECM is up and ready to receive commands. +# returns 0 if ECM is fully up and ready, else 1 +ecm_is_ready() { + if [ ! -e "${ECM_STATE}" ] + then + return 1 + fi + return 0 +} + +# +# module_state_mount(module_name) +# Mounts the state file of the module, if supported +# +module_state_mount() { + local module_name=$1 + local mount_dir=$2 + local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" + + if [ -e "${mount_dir}/${module_name}" ] + then + # already mounted + return 0 + fi + + #echo "Mount state file for $module_name ..." + if [ ! -e "$state_file" ] + then + #echo "... $module_name does not support state" + return 1 + fi + + local major="`cat $state_file`" + #echo "... Mounting state $state_file with major: $major" + mknod "${mount_dir}/${module_name}" c $major 0 +} + +# +# main +# +ecm_is_ready || { + #echo "ECM is not running" + exit 1 +} + +# all state files are mounted under MOUNT_ROOT, so make sure it exists +mkdir -p ${MOUNT_ROOT} + +# +# attempt to mount state files for the requested module and cat it +# if the mount succeeded +# +module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { + cat ${MOUNT_ROOT}/${ECM_MODULE} + exit 0 +} + +exit 2 diff --git a/package/nss/qca/qca-nss-ecm/files/on-demand-down b/package/nss/qca/qca-nss-ecm/files/on-demand-down new file mode 100644 index 000000000..02d708e03 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/files/on-demand-down @@ -0,0 +1,6 @@ +#!/bin/sh +# Copyright (c) 2016 The Linux Foundation. All rights reserved. + +[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all +} diff --git a/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.defaults b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.defaults new file mode 100644 index 000000000..308e265c9 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.defaults @@ -0,0 +1,28 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +uci -q batch << EOF + delete firewall.qcanssecm + set firewall.qcanssecm=include + set firewall.qcanssecm.type=script + set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm + set firewall.qcanssecm.family=any + set firewall.qcanssecm.reload=1 + commit firewall +EOF + +exit 0 diff --git a/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.firewall b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.firewall new file mode 100644 index 000000000..24c64def2 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.firewall @@ -0,0 +1,18 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.init b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.init new file mode 100644 index 000000000..7afb679f1 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.init @@ -0,0 +1,140 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +# The shebang above has an extra space intentially to avoid having +# openwrt build scripts automatically enable this package starting +# at boot. + +START=19 + +get_front_end_mode() { + config_load "ecm" + config_get front_end global acceleration_engine "auto" + + case $front_end in + auto) + echo '0' + ;; + nss) + echo '1' + ;; + sfe) + echo '2' + ;; + *) + echo 'uci_option_acceleration_engine is invalid' + esac +} + +support_bridge() { + #NSS support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 + #SFE doesn't support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 +} + +load_sfe() { + local kernel_version=$(uname -r) + + [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { + [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { + [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { + [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv + } +} + +load_ecm() { + [ -d /sys/module/ecm ] || { + [ ! -e /proc/device-tree/MP_256 ] && load_sfe + insmod ecm front_end_selection=$(get_front_end_mode) + } + + support_bridge && { + sysctl -w net.bridge.bridge-nf-call-ip6tables=1 + sysctl -w net.bridge.bridge-nf-call-iptables=1 + } +} + +unload_ecm() { + sysctl -w net.bridge.bridge-nf-call-ip6tables=0 + sysctl -w net.bridge.bridge-nf-call-iptables=0 + + if [ -d /sys/module/ecm ]; then + # + # Stop ECM frontends + # + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + + # + # Defunct the connections + # + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 5; + + rmmod ecm + sleep 1 + fi +} + +start() { + # If SFE CM is loaded, return. + if [ -d /sys/module/shortcut_fe_cm ]; then + echo "shortcut_fe CM is loaded, unload it first" + echo "cmd: /etc/init.d/shortcut_fe stop" + return + fi + + load_ecm + + # If the acceleration engine is NSS, enable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 + + support_bridge && { + echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + } + + if [ -d /sys/module/qca_ovsmgr ]; then + insmod ecm_ovs + fi + +} + +stop() { + # If ECM is already not loaded, just return. + if [ ! -d /sys/module/ecm ]; then + return + fi + + # If the acceleration engine is NSS, disable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 + + sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + + if [ -d /sys/module/ecm_ovs ]; then + rmmod ecm_ovs + fi + + unload_ecm +} diff --git a/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl new file mode 100644 index 000000000..1a3d76b18 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl @@ -0,0 +1,2 @@ +# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 +net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.uci b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.uci new file mode 100644 index 000000000..4f2de6877 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/files/qca-nss-ecm.uci @@ -0,0 +1,2 @@ +config ecm 'global' + option acceleration_engine 'auto' diff --git a/package/nss/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch b/package/nss/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch new file mode 100644 index 000000000..4e7932c9d --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch @@ -0,0 +1,335 @@ +From 73345c87b28a473b35b57e673f8de963c3d73da1 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 19 May 2021 02:38:53 +0200 +Subject: [PATCH] treewide: componentize the module even more + +Signed-off-by: Ansuel Smith +--- + Makefile | 56 +++++++++++++++++++++++++------- + ecm_db/ecm_db_connection.c | 8 +++++ + ecm_db/ecm_db_node.c | 4 +++ + ecm_interface.c | 8 +++++ + frontends/ecm_front_end_common.c | 7 ++++ + 5 files changed, 72 insertions(+), 11 deletions(-) + +--- a/Makefile ++++ b/Makefile +@@ -82,10 +82,18 @@ ccflags-$(ECM_INTERFACE_BOND_ENABLE) += + # Define ECM_INTERFACE_PPPOE_ENABLE=y in order + # to enable support for PPPoE acceleration. + # ############################################################################# +-ECM_INTERFACE_PPPOE_ENABLE=y ++ifndef $(ECM_INTERFACE_PPPOE_ENABLE) ++ ECM_INTERFACE_PPPOE_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_PPPOE_ENABLE) += -DECM_INTERFACE_PPPOE_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_L2TPV2_PPTP_ENABLE=y in order ++# to enable support for l2tpv2 or PPTP detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_L2TPV2_PPTP_ENABLE) += -DECM_INTERFACE_L2TPV2_PPTP_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_L2TPV2_ENABLE=y in order + # to enable support for l2tpv2 acceleration. + # ############################################################################# +@@ -118,6 +126,12 @@ ccflags-$(ECM_INTERFACE_PPP_ENABLE) += - + ccflags-$(ECM_INTERFACE_MAP_T_ENABLE) += -DECM_INTERFACE_MAP_T_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_GRE_ENABLE=y in order ++# to enable support for GRE detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_GRE_ENABLE) += -DECM_INTERFACE_GRE_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_GRE_TAP_ENABLE=y in order + # to enable support for GRE TAP interface. + # ############################################################################# +@@ -186,7 +200,9 @@ ccflags-$(ECM_INTERFACE_OVS_BRIDGE_ENABL + # ############################################################################# + # Define ECM_INTERFACE_VLAN_ENABLE=y in order to enable support for VLAN + # ############################################################################# +-ECM_INTERFACE_VLAN_ENABLE=y ++ifndef $(ECM_INTERFACE_VLAN_ENABLE) ++ ECM_INTERFACE_VLAN_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_VLAN_ENABLE) += -DECM_INTERFACE_VLAN_ENABLE + + # ############################################################################# +@@ -228,7 +244,9 @@ ccflags-$(ECM_CLASSIFIER_OVS_ENABLE) += + # ############################################################################# + # Define ECM_CLASSIFIER_MARK_ENABLE=y in order to enable mark classifier. + # ############################################################################# +-ECM_CLASSIFIER_MARK_ENABLE=y ++ifndef $(ECM_CLASSIFIER_MARK_ENABLE) ++ ECM_CLASSIFIER_MARK_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_MARK_ENABLE) += ecm_classifier_mark.o + ccflags-$(ECM_CLASSIFIER_MARK_ENABLE) += -DECM_CLASSIFIER_MARK_ENABLE + +@@ -247,7 +265,9 @@ ccflags-$(ECM_CLASSIFIER_NL_ENABLE) += - + # ############################################################################# + # Define ECM_CLASSIFIER_DSCP_ENABLE=y in order to enable DSCP classifier. + # ############################################################################# +-ECM_CLASSIFIER_DSCP_ENABLE=y ++ifndef $(ECM_CLASSIFIER_DSCP_ENABLE) ++ ECM_CLASSIFIER_DSCP_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_DSCP_ENABLE) += ecm_classifier_dscp.o + ccflags-$(ECM_CLASSIFIER_DSCP_ENABLE) += -DECM_CLASSIFIER_DSCP_ENABLE + ccflags-$(ECM_CLASSIFIER_DSCP_IGS) += -DECM_CLASSIFIER_DSCP_IGS +@@ -274,7 +294,9 @@ endif + # the Parental Controls subsystem classifier in ECM. Currently disabled until + # customers require it / if they need to integrate their Parental Controls with it. + # ############################################################################# +-ECM_CLASSIFIER_PCC_ENABLE=y ++ifndef $(ECM_CLASSIFIER_PCC_ENABLE) ++ ECM_CLASSIFIER_PCC_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_PCC_ENABLE) += ecm_classifier_pcc.o + ccflags-$(ECM_CLASSIFIER_PCC_ENABLE) += -DECM_CLASSIFIER_PCC_ENABLE + +@@ -301,28 +323,36 @@ ccflags-$(ECM_NON_PORTED_SUPPORT_ENABLE) + # ############################################################################# + # Define ECM_STATE_OUTPUT_ENABLE=y to support XML state output + # ############################################################################# +-ECM_STATE_OUTPUT_ENABLE=y ++ifndef $(ECM_STATE_OUTPUT_ENABLE) ++ ECM_STATE_OUTPUT_ENABLE=y ++endif + ecm-$(ECM_STATE_OUTPUT_ENABLE) += ecm_state.o + ccflags-$(ECM_STATE_OUTPUT_ENABLE) += -DECM_STATE_OUTPUT_ENABLE + + # ############################################################################# + # Define ECM_DB_ADVANCED_STATS_ENABLE to support XML state output + # ############################################################################# +-ECM_DB_ADVANCED_STATS_ENABLE=y ++ifndef $(ECM_DB_ADVANCED_STATS_ENABLE) ++ ECM_DB_ADVANCED_STATS_ENABLE=y ++endif + ccflags-$(ECM_DB_ADVANCED_STATS_ENABLE) += -DECM_DB_ADVANCED_STATS_ENABLE + + # ############################################################################# + # Define ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y in order to enable + # the database to track relationships between objects. + # ############################################################################# +-ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++ifndef $(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) ++ ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++endif + ccflags-$(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) += -DECM_DB_XREF_ENABLE + + # ############################################################################# + # Define ECM_TRACKER_DPI_SUPPORT_ENABLE=y in order to enable support for + # deep packet inspection and tracking of data with the trackers. + # ############################################################################# +-ECM_TRACKER_DPI_SUPPORT_ENABLE=y ++ifndef $(ECM_TRACKER_DPI_SUPPORT_ENABLE) ++ ECM_TRACKER_DPI_SUPPORT_ENABLE=y ++endif + ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE) += -DECM_TRACKER_DPI_SUPPORT_ENABLE + + # ############################################################################# +@@ -330,14 +360,18 @@ ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE + # support for the database keeping lists of connections that are assigned + # on a per TYPE of classifier basis. + # ############################################################################# +-ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++ifndef $(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) ++ ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++endif + ccflags-$(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) += -DECM_DB_CTA_TRACK_ENABLE + + # ############################################################################# + # Define ECM_BAND_STEERING_ENABLE=y in order to enable + # band steering feature. + # ############################################################################# +-ECM_BAND_STEERING_ENABLE=y ++ifndef $(ECM_BAND_STEERING_ENABLE) ++ ECM_BAND_STEERING_ENABLE=y ++endif + ccflags-$(ECM_BAND_STEERING_ENABLE) += -DECM_BAND_STEERING_ENABLE + + # ############################################################################# +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -430,7 +430,9 @@ EXPORT_SYMBOL(ecm_db_connection_make_def + */ + void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) + { ++#ifdef ECM_DB_ADVANCED_STATS_ENABLE + int32_t i; ++#endif + + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); + +@@ -529,7 +531,9 @@ EXPORT_SYMBOL(ecm_db_connection_data_tot + */ + void ecm_db_connection_data_totals_update_dropped(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) + { ++#ifdef ECM_DB_ADVANCED_STATS_ENABLE + int32_t i; ++#endif + + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); + +@@ -1508,6 +1512,7 @@ void ecm_db_connection_defunct_all(void) + } + EXPORT_SYMBOL(ecm_db_connection_defunct_all); + ++#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE + /* + * ecm_db_connection_defunct_by_classifier() + * Make defunct based on masked fields +@@ -1667,6 +1672,7 @@ next_ci: + ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt); + } + } ++#endif + + /* + * ecm_db_connection_defunct_by_port() +@@ -1956,6 +1962,7 @@ struct ecm_db_node_instance *ecm_db_conn + } + EXPORT_SYMBOL(ecm_db_connection_node_get_and_ref); + ++#ifdef ECM_DB_XREF_ENABLE + /* + * ecm_db_connection_mapping_get_and_ref_next() + * Return reference to next connection in the mapping chain in the specified direction. +@@ -1997,6 +2004,7 @@ struct ecm_db_connection_instance *ecm_d + return nci; + } + EXPORT_SYMBOL(ecm_db_connection_iface_get_and_ref_next); ++#endif + + /* + * ecm_db_connection_mapping_get_and_ref() +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -224,9 +224,11 @@ EXPORT_SYMBOL(ecm_db_node_get_and_ref_ne + */ + int ecm_db_node_deref(struct ecm_db_node_instance *ni) + { ++#ifdef ECM_DB_XREF_ENABLE + #if (DEBUG_LEVEL >= 1) + int dir; + #endif ++#endif + DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni); + + spin_lock_bh(&ecm_db_lock); +@@ -486,9 +488,11 @@ EXPORT_SYMBOL(ecm_db_node_iface_get_and_ + void ecm_db_node_add(struct ecm_db_node_instance *ni, struct ecm_db_iface_instance *ii, uint8_t *address, + ecm_db_node_final_callback_t final, void *arg) + { ++#ifdef ECM_DB_XREF_ENABLE + #if (DEBUG_LEVEL >= 1) + int dir; + #endif ++#endif + ecm_db_node_hash_t hash_index; + struct ecm_db_listener_instance *li; + +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -1343,6 +1343,7 @@ struct neighbour *ecm_interface_ipv6_nei + */ + bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1367,6 +1368,7 @@ bool ecm_interface_is_pptp(struct sk_buf + } + + dev_put(in); ++#endif + return false; + } + +@@ -1379,6 +1381,7 @@ bool ecm_interface_is_pptp(struct sk_buf + */ + bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + uint32_t flag = 0; + struct net_device *in; + +@@ -1411,6 +1414,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + } + + dev_put(in); ++#endif + return false; + } + +@@ -1423,6 +1427,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + */ + bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1445,6 +1450,7 @@ bool ecm_interface_is_l2tp_pptp(struct s + } + + dev_put(in); ++#endif + return false; + } + +@@ -6630,6 +6636,7 @@ static void ecm_interface_regenerate_con + return; + } + ++#ifdef ECM_DB_XREF_ENABLE + for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) { + /* + * Re-generate all connections associated with this interface +@@ -6645,6 +6652,7 @@ static void ecm_interface_regenerate_con + ci[dir] = cin; + } + } ++#endif + + #ifdef ECM_MULTICAST_ENABLE + /* +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -106,6 +106,7 @@ bool ecm_front_end_gre_proto_is_accel_al + struct nf_conntrack_tuple *tuple, + int ip_version) + { ++#ifdef ECM_INTERFACE_GRE_ENABLE + struct net_device *dev; + struct gre_base_hdr *greh; + +@@ -117,10 +118,12 @@ bool ecm_front_end_gre_proto_is_accel_al + /* + * Case 1: PPTP locally terminated + */ ++#ifdef ECM_INTERFACE_PPTP_ENABLE + if (ecm_interface_is_pptp(skb, outdev)) { + DEBUG_TRACE("%px: PPTP GRE locally terminated - allow acceleration\n", skb); + return true; + } ++#endif + + /* + * Case 2: PPTP pass through +@@ -223,6 +226,10 @@ bool ecm_front_end_gre_proto_is_accel_al + */ + DEBUG_TRACE("%px: GRE IPv%d pass through - allow acceleration\n", skb, ip_version); + return true; ++#else ++ DEBUG_TRACE("%px: GRE%d feature is disabled - do not allow acceleration\n", skb, ip_version); ++ return false; ++#endif + } + + #ifdef ECM_CLASSIFIER_DSCP_ENABLE diff --git a/package/nss/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch b/package/nss/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch new file mode 100644 index 000000000..107b9571b --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch @@ -0,0 +1,831 @@ +From e8b642c23af9146c973e828a7f4e0fb56cfc8d0b Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 15 May 2021 03:51:14 +0200 +Subject: [PATCH] add support for kernel 5.10 + +Signed-off-by: Ansuel Smith +--- + ecm_classifier_default.c | 24 +++--------- + ecm_classifier_dscp.c | 8 +--- + ecm_classifier_emesh.c | 16 ++------ + ecm_classifier_hyfi.c | 7 +--- + ecm_classifier_mark.c | 8 +--- + ecm_classifier_ovs.c | 8 +--- + ecm_classifier_pcc.c | 8 +--- + ecm_conntrack_notifier.c | 8 +--- + ecm_db/ecm_db_connection.c | 7 +--- + ecm_db/ecm_db_host.c | 7 +--- + ecm_db/ecm_db_iface.c | 7 +--- + ecm_db/ecm_db_mapping.c | 7 +--- + ecm_db/ecm_db_node.c | 7 +--- + ecm_interface.c | 4 +- + ecm_state.c | 14 ++----- + frontends/ecm_front_end_common.c | 4 +- + frontends/ecm_front_end_ipv4.c | 7 +--- + frontends/ecm_front_end_ipv6.c | 7 +--- + frontends/nss/ecm_nss_bond_notifier.c | 8 +--- + frontends/nss/ecm_nss_ipv4.c | 49 +++++++------------------ + frontends/nss/ecm_nss_ipv6.c | 49 +++++++------------------ + frontends/nss/ecm_nss_multicast_ipv4.c | 7 +--- + frontends/nss/ecm_nss_multicast_ipv6.c | 7 +--- + frontends/nss/ecm_nss_non_ported_ipv4.c | 7 +--- + frontends/nss/ecm_nss_non_ported_ipv6.c | 7 +--- + frontends/nss/ecm_nss_ported_ipv4.c | 8 +--- + frontends/nss/ecm_nss_ported_ipv6.c | 8 +--- + frontends/sfe/ecm_sfe_ipv4.c | 49 +++++++------------------ + frontends/sfe/ecm_sfe_ipv6.c | 49 +++++++------------------ + frontends/sfe/ecm_sfe_non_ported_ipv4.c | 7 +--- + frontends/sfe/ecm_sfe_non_ported_ipv6.c | 7 +--- + frontends/sfe/ecm_sfe_ported_ipv4.c | 8 +--- + frontends/sfe/ecm_sfe_ported_ipv6.c | 8 +--- + 33 files changed, 122 insertions(+), 314 deletions(-) + +--- a/ecm_classifier_default.c ++++ b/ecm_classifier_default.c +@@ -776,26 +776,14 @@ int ecm_classifier_default_init(struct d + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_default_enabled)) { +- DEBUG_ERROR("Failed to create ecm deafult classifier enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_default_enabled); + +- if (!debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_default_accel_mode)) { +- DEBUG_ERROR("Failed to create ecm deafult classifier accel_mode file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_default_accel_mode); + +- if (!debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_accel_delay_pkts)) { +- DEBUG_ERROR("Failed to create accel delay packet counts in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_accel_delay_pkts); + + return 0; + } +--- a/ecm_classifier_dscp.c ++++ b/ecm_classifier_dscp.c +@@ -747,12 +747,8 @@ int ecm_classifier_dscp_init(struct dent + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, +- (u32 *)&ecm_classifier_dscp_enabled)) { +- DEBUG_ERROR("Failed to create dscp enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_dscp_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, ++ (u32 *)&ecm_classifier_dscp_enabled); + + return 0; + } +--- a/ecm_classifier_emesh.c ++++ b/ecm_classifier_emesh.c +@@ -977,19 +977,11 @@ int ecm_classifier_emesh_init(struct den + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, +- (u32 *)&ecm_classifier_emesh_enabled)) { +- DEBUG_ERROR("Failed to create ecm emesh classifier enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_emesh_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, ++ (u32 *)&ecm_classifier_emesh_enabled); + +- if (!debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, +- (u32 *)&ecm_classifier_emesh_latency_config_enabled)) { +- DEBUG_ERROR("Failed to create ecm emesh classifier latency config enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_emesh_dentry); +- return -1; +- } ++ debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, ++ (u32 *)&ecm_classifier_emesh_latency_config_enabled); + + /* + * Register for service prioritization notification update. +--- a/ecm_classifier_hyfi.c ++++ b/ecm_classifier_hyfi.c +@@ -1099,11 +1099,8 @@ int ecm_classifier_hyfi_rules_init(struc + goto classifier_task_cleanup; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, +- (u32 *)&ecm_classifier_hyfi_enabled)) { +- DEBUG_ERROR("Failed to create ecm hyfi classifier enabled file in debugfs\n"); +- goto classifier_task_cleanup; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, ++ (u32 *)&ecm_classifier_hyfi_enabled); + + if (!debugfs_create_file("cmd", S_IWUSR, ecm_classifier_hyfi_dentry, + NULL, &ecm_classifier_hyfi_cmd_fops)) { +--- a/ecm_classifier_mark.c ++++ b/ecm_classifier_mark.c +@@ -753,12 +753,8 @@ int ecm_classifier_mark_init(struct dent + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, +- (u32 *)&ecm_classifier_mark_enabled)) { +- DEBUG_ERROR("Failed to create mark enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_mark_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, ++ (u32 *)&ecm_classifier_mark_enabled); + + return 0; + } +--- a/ecm_classifier_ovs.c ++++ b/ecm_classifier_ovs.c +@@ -2200,12 +2200,8 @@ int ecm_classifier_ovs_init(struct dentr + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, +- (u32 *)&ecm_classifier_ovs_enabled)) { +- DEBUG_ERROR("Failed to create ovs enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_ovs_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, ++ (u32 *)&ecm_classifier_ovs_enabled); + + return 0; + } +--- a/ecm_classifier_pcc.c ++++ b/ecm_classifier_pcc.c +@@ -1308,12 +1308,8 @@ int ecm_classifier_pcc_init(struct dentr + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, +- (u32 *)&ecm_classifier_pcc_enabled)) { +- DEBUG_ERROR("Failed to create pcc enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_pcc_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, ++ (u32 *)&ecm_classifier_pcc_enabled); + + return 0; + } +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -414,12 +414,8 @@ int ecm_conntrack_notifier_init(struct d + return -1; + } + +- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, +- (u32 *)&ecm_conntrack_notifier_stopped)) { +- DEBUG_ERROR("Failed to create ecm conntrack notifier stopped file in debugfs\n"); +- debugfs_remove_recursive(ecm_conntrack_notifier_dentry); +- return -1; +- } ++ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, ++ (u32 *)&ecm_conntrack_notifier_stopped); + + #ifdef CONFIG_NF_CONNTRACK_EVENTS + /* +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -3642,11 +3642,8 @@ static struct file_operations ecm_db_con + */ + bool ecm_db_connection_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("connection_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_connection_count)) { +- DEBUG_ERROR("Failed to create ecm db connection count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("connection_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_connection_count); + + if (!debugfs_create_file("connection_count_simple", S_IRUGO, dentry, + NULL, &ecm_db_connection_count_simple_fops)) { +--- a/ecm_db/ecm_db_host.c ++++ b/ecm_db/ecm_db_host.c +@@ -770,11 +770,8 @@ EXPORT_SYMBOL(ecm_db_host_alloc); + bool ecm_db_host_init(struct dentry *dentry) + { + +- if (!debugfs_create_u32("host_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_host_count)) { +- DEBUG_ERROR("Failed to create ecm db host count file in debugfs\n"); +- return false;; +- } ++ debugfs_create_u32("host_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_host_count); + + ecm_db_host_table = vzalloc(sizeof(struct ecm_db_host_instance *) * ECM_DB_HOST_HASH_SLOTS); + if (!ecm_db_host_table) { +--- a/ecm_db/ecm_db_iface.c ++++ b/ecm_db/ecm_db_iface.c +@@ -3670,11 +3670,8 @@ EXPORT_SYMBOL(ecm_db_iface_alloc); + */ + bool ecm_db_iface_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("iface_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_iface_count)) { +- DEBUG_ERROR("Failed to create ecm db iface count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("iface_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_iface_count); + + return true; + } +--- a/ecm_db/ecm_db_mapping.c ++++ b/ecm_db/ecm_db_mapping.c +@@ -806,11 +806,8 @@ EXPORT_SYMBOL(ecm_db_mapping_alloc); + */ + bool ecm_db_mapping_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("mapping_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_mapping_count)) { +- DEBUG_ERROR("Failed to create ecm db mapping count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("mapping_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_mapping_count); + + ecm_db_mapping_table = vzalloc(sizeof(struct ecm_db_mapping_instance *) * ECM_DB_MAPPING_HASH_SLOTS); + if (!ecm_db_mapping_table) { +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -1187,11 +1187,8 @@ keep_sni_conn: + */ + bool ecm_db_node_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("node_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_node_count)) { +- DEBUG_ERROR("Failed to create ecm db node count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("node_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_node_count); + + ecm_db_node_table = vzalloc(sizeof(struct ecm_db_node_instance *) * ECM_DB_NODE_HASH_SLOTS); + if (!ecm_db_node_table) { +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -332,7 +332,7 @@ static struct net_device *ecm_interface_ + struct net_device *dev; + + ECM_IP_ADDR_TO_NIN6_ADDR(addr6, addr); +- dev = (struct net_device *)ipv6_dev_find(&init_net, &addr6, 1); ++ dev = (struct net_device *)ipv6_dev_find_and_hold(&init_net, &addr6, 1); + return dev; + } + #endif +@@ -734,7 +734,7 @@ static bool ecm_interface_mac_addr_get_i + * Get the MAC address that corresponds to IP address given. + */ + ECM_IP_ADDR_TO_NIN6_ADDR(daddr, addr); +- local_dev = ipv6_dev_find(&init_net, &daddr, 1); ++ local_dev = ipv6_dev_find_and_hold(&init_net, &daddr, 1); + if (local_dev) { + DEBUG_TRACE("%pi6 is a local address\n", &daddr); + memcpy(mac_addr, dev->dev_addr, ETH_ALEN); +--- a/ecm_state.c ++++ b/ecm_state.c +@@ -899,17 +899,11 @@ int ecm_state_init(struct dentry *dentry + return -1; + } + +- if (!debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, +- (u32 *)&ecm_state_dev_major_id)) { +- DEBUG_ERROR("Failed to create ecm state dev major file in debugfs\n"); +- goto init_cleanup; +- } ++ debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, ++ (u32 *)&ecm_state_dev_major_id); + +- if (!debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, +- (u32 *)&ecm_state_file_output_mask)) { +- DEBUG_ERROR("Failed to create ecm state output mask file in debugfs\n"); +- goto init_cleanup; +- } ++ debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, ++ (u32 *)&ecm_state_file_output_mask); + + /* + * Register a char device that we will use to provide a dump of our state +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -192,7 +192,7 @@ bool ecm_front_end_gre_proto_is_accel_al + return false; + } + } else { +- dev = ipv6_dev_find(&init_net, &(tuple->src.u3.in6), 1); ++ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->src.u3.in6), 1); + if (dev) { + /* + * Source IP address is local +@@ -202,7 +202,7 @@ bool ecm_front_end_gre_proto_is_accel_al + return false; + } + +- dev = ipv6_dev_find(&init_net, &(tuple->dst.u3.in6), 1); ++ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->dst.u3.in6), 1); + if (dev) { + /* + * Destination IP address is local +--- a/frontends/ecm_front_end_ipv4.c ++++ b/frontends/ecm_front_end_ipv4.c +@@ -376,11 +376,8 @@ void ecm_front_end_ipv4_stop(int num) + */ + int ecm_front_end_ipv4_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv4_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv4 stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv4_stopped); + + switch (ecm_front_end_type_get()) { + case ECM_FRONT_END_TYPE_NSS: +--- a/frontends/ecm_front_end_ipv6.c ++++ b/frontends/ecm_front_end_ipv6.c +@@ -255,11 +255,8 @@ void ecm_front_end_ipv6_stop(int num) + */ + int ecm_front_end_ipv6_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv6_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv6 stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv6_stopped); + + switch (ecm_front_end_type_get()) { + case ECM_FRONT_END_TYPE_NSS: +--- a/frontends/nss/ecm_nss_bond_notifier.c ++++ b/frontends/nss/ecm_nss_bond_notifier.c +@@ -240,12 +240,8 @@ int ecm_nss_bond_notifier_init(struct de + return -1; + } + +- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, +- (u32 *)&ecm_nss_bond_notifier_stopped)) { +- DEBUG_ERROR("Failed to create ecm bond notifier stopped file in debugfs\n"); +- debugfs_remove_recursive(ecm_nss_bond_notifier_dentry); +- return -1; +- } ++ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, ++ (u32 *)&ecm_nss_bond_notifier_stopped); + + /* + * Register Link Aggregation callbacks with the bonding driver +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2802,41 +2802,23 @@ int ecm_nss_ipv4_init(struct dentry *den + return result; + } + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, + NULL, &ecm_nss_ipv4_accel_limit_mode_fops)) { +@@ -2867,11 +2849,8 @@ int ecm_nss_ipv4_init(struct dentry *den + goto task_cleanup; + } + +- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 vlan passthrough file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable); + + #ifdef ECM_NON_PORTED_SUPPORT_ENABLE + if (!ecm_nss_non_ported_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) { +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2542,41 +2542,23 @@ int ecm_nss_ipv6_init(struct dentry *den + return result; + } + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, + NULL, &ecm_nss_ipv6_accel_limit_mode_fops)) { +@@ -2607,11 +2589,8 @@ int ecm_nss_ipv6_init(struct dentry *den + goto task_cleanup; + } + +- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 vlan passthrough file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable); + + #ifdef ECM_NON_PORTED_SUPPORT_ENABLE + if (!ecm_nss_non_ported_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) { +--- a/frontends/nss/ecm_nss_multicast_ipv4.c ++++ b/frontends/nss/ecm_nss_multicast_ipv4.c +@@ -4139,11 +4139,8 @@ void ecm_nss_multicast_ipv4_stop(int num + */ + int ecm_nss_multicast_ipv4_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv4_mc_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv4 mc stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv4_mc_stopped); + + /* + * Register multicast update callback to MCS snooper +--- a/frontends/nss/ecm_nss_multicast_ipv6.c ++++ b/frontends/nss/ecm_nss_multicast_ipv6.c +@@ -3939,11 +3939,8 @@ void ecm_nss_multicast_ipv6_stop(int num + */ + int ecm_nss_multicast_ipv6_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv6_mc_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv6 mc stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv6_mc_stopped); + + /* + * Register multicast update callback to MCS snooper +--- a/frontends/nss/ecm_nss_non_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv4.c +@@ -2615,11 +2615,8 @@ done: + */ + bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count); + + return true; + } +--- a/frontends/nss/ecm_nss_non_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv6.c +@@ -2329,11 +2329,8 @@ done: + */ + bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count); + + return true; + } +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -2944,12 +2944,8 @@ bool ecm_nss_ported_ipv4_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); + + return true; + } +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c +@@ -2732,12 +2732,8 @@ bool ecm_nss_ported_ipv6_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ipv4.c +@@ -1808,48 +1808,27 @@ int ecm_sfe_ipv4_init(struct dentry *den + } + + #ifdef CONFIG_XFRM +- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 reject_acceleration_for_ipsec file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec); + #endif + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, + NULL, &ecm_sfe_ipv4_accel_limit_mode_fops)) { +--- a/frontends/sfe/ecm_sfe_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ipv6.c +@@ -1532,48 +1532,27 @@ int ecm_sfe_ipv6_init(struct dentry *den + } + + #ifdef CONFIG_XFRM +- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 reject_acceleration_for_ipsec file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec); + #endif + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, + NULL, &ecm_sfe_ipv6_accel_limit_mode_fops)) { +--- a/frontends/sfe/ecm_sfe_non_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv4.c +@@ -2284,11 +2284,8 @@ done: + */ + bool ecm_sfe_non_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count); + + return true; + } +--- a/frontends/sfe/ecm_sfe_non_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv6.c +@@ -2083,11 +2083,8 @@ done: + */ + bool ecm_sfe_non_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv4.c +@@ -2528,12 +2528,8 @@ bool ecm_sfe_ported_ipv4_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP]); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv6.c +@@ -2374,12 +2374,8 @@ bool ecm_sfe_ported_ipv6_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP]); + + return true; + } diff --git a/package/nss/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch b/package/nss/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch new file mode 100644 index 000000000..72005cd70 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch @@ -0,0 +1,25 @@ +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -421,7 +421,11 @@ int ecm_conntrack_notifier_init(struct d + /* + * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections + */ ++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS ++ result = nf_conntrack_register_chain_notifier(&init_net, &ecm_conntrack_notifier); ++#else + result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); ++#endif + if (result < 0) { + DEBUG_ERROR("Can't register nf notifier hook.\n"); + debugfs_remove_recursive(ecm_conntrack_notifier_dentry); +@@ -439,7 +443,9 @@ EXPORT_SYMBOL(ecm_conntrack_notifier_ini + void ecm_conntrack_notifier_exit(void) + { + DEBUG_INFO("ECM Conntrack Notifier exit\n"); +-#ifdef CONFIG_NF_CONNTRACK_EVENTS ++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS ++ nf_conntrack_unregister_chain_notifier(&init_net, &ecm_conntrack_notifier); ++#else + nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); + #endif + /* diff --git a/package/nss/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch b/package/nss/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch new file mode 100644 index 000000000..a998d8295 --- /dev/null +++ b/package/nss/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch @@ -0,0 +1,58 @@ +From e6d701c0d454d841366c556b2ef07a5203ffb35d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 21 May 2021 21:41:31 +0200 +Subject: [PATCH] More compile fixes + +More runtime compile fixes. + +Signed-off-by: Robert Marko +--- + frontends/nss/ecm_nss_ported_ipv4.c | 12 +++--------- + frontends/nss/ecm_nss_ported_ipv6.c | 12 +++--------- + 2 files changed, 6 insertions(+), 18 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ported_ipv4.c b/frontends/nss/ecm_nss_ported_ipv4.c +index 3522f0f..7f5fcd1 100644 +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -2935,14 +2935,8 @@ done: + */ + bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- struct dentry *udp_dentry; +- +- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, ++ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_UDP]); +- if (!udp_dentry) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 udp_accelerated_count file in debugfs\n"); +- return false; +- } + + debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); +diff --git a/frontends/nss/ecm_nss_ported_ipv6.c b/frontends/nss/ecm_nss_ported_ipv6.c +index f43ac95..e0f779c 100644 +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c + /* + * ecm_nss_ported_ipv6_connection_callback() +@@ -2723,14 +2723,8 @@ done: + */ + bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- struct dentry *udp_dentry; +- +- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, ++ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_UDP]); +- if (!udp_dentry) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 udp_accelerated_count file in debugfs\n"); +- return false; +- } + + debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); +-- +2.31.1 + diff --git a/package/nss/qca/qca-ssdk-shell/Makefile b/package/nss/qca/qca-ssdk-shell/Makefile new file mode 100644 index 000000000..e6bd6a3f7 --- /dev/null +++ b/package/nss/qca/qca-ssdk-shell/Makefile @@ -0,0 +1,48 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-ssdk-shell +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/ssdk-shell +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-01-27 +PKG_SOURCE_VERSION:=5661366d471a78314bc7010f985ad8cc15be832a +PKG_MIRROR_HASH:=73111e09e896f0abbe3ee1c358aea7ec14fe5e668ce8753b8968e03c78f9599b + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define Package/qca-ssdk-shell + SECTION:=QCA + CATEGORY:=Utilities + TITLE:=Shell application for QCA SSDK +endef + + +define Package/qca-ssdk-shell/Description + This package contains a qca-ssdk shell application for QCA chipset +endef + +ifndef CONFIG_TOOLCHAIN_BIN_PATH +CONFIG_TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + CFLAGS="$(TARGET_CFLAGS)" \ + LDFLAGS="$(TARGET_LDFLAGS)" \ + ARCH=$(LINUX_KARCH) + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) +endef + +define Package/qca-ssdk-shell/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/build/bin/ssdk_sh $(1)/usr/sbin/ +endef + + +$(eval $(call BuildPackage,qca-ssdk-shell)) diff --git a/package/nss/qca/qca-ssdk/Makefile b/package/nss/qca/qca-ssdk/Makefile new file mode 100644 index 000000000..204bf2d39 --- /dev/null +++ b/package/nss/qca/qca-ssdk/Makefile @@ -0,0 +1,93 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-ssdk +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/qca-ssdk +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-04-28 +PKG_SOURCE_VERSION:=c9bc3bc34eaaac78083573524097356e2dcc1b66 +PKG_MIRROR_HASH:=29db78529be32427b8b96fcbfec22a016a243676781ec96d9d65b810944fa405 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-ssdk-nohnat + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for QCA SSDK + DEPENDS:=@(TARGET_ipq807x) + FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko + AUTOLOAD:=$(call AutoLoad,30,qca-ssdk) +endef + +define KernelPackage/qca-ssdk-nohnat/Description +This package contains a qca-ssdk driver for QCA chipset +endef + +GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/') + +ifdef CONFIG_TOOLCHAIN_BIN_PATH +TOOLCHAIN_BIN_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) +else +TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +MAKE_FLAGS+= \ + TARGET_NAME=$(CONFIG_TARGET_NAME) \ + TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + ARCH=$(LINUX_KARCH) \ + TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \ + GCC_VERSION=$(GCC_VERSION) \ + EXTRA_CFLAGS=-I$(STAGING_DIR)/usr/include \ + $(KERNEL_MAKE_FLAGS) + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq60xx" "ipq807x")) + MAKE_FLAGS+= PTP_FEATURE=disable SWCONFIG_FEATURE=disable +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + MAKE_FLAGS+= CHIP_TYPE=HPPE +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + MAKE_FLAGS+= CHIP_TYPE=CPPE +endif + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/ref + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/fal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/sal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/init + $(CP) -rf $(PKG_BUILD_DIR)/include/api/sw_ioctl.h $(1)/usr/include/qca-ssdk/api + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_vsi.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_vsi.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_fdb.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_fdb.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \ + fi + $(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/*.h $(1)/usr/include/qca-ssdk + +endef + +define KernelPackage/qca-ssdk-nohnat/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk +endef + +$(eval $(call KernelPackage,qca-ssdk-nohnat)) diff --git a/package/nss/qca/qca-ssdk/files/qca-ssdk b/package/nss/qca/qca-ssdk/files/qca-ssdk new file mode 100755 index 000000000..389279c0c --- /dev/null +++ b/package/nss/qca/qca-ssdk/files/qca-ssdk @@ -0,0 +1,206 @@ +#!/bin/sh /etc/rc.common +# Copyright (c) 2018, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=16 + +#!/bin/sh +ruletype="ip4 ip6" +side="wan lan" +qwan="1 3 2 0 5 7 6 4" +qlan="0 1 2 3 4 5 6 7" + +function create_war_acl_rules(){ + for lw in $side + do + #echo $lw + if [ "$lw" == "wan" ];then + listid=254 + queue=$qwan + portmap=0x20 + else + listid=255 + queue=$qlan + portmap=0x1e + fi + #echo $queue + #echo "creating list $listid" + ssdk_sh acl list create $listid 255 + ruleid=0 + for rt in $ruletype + do + for qid in $queue + do + cmd="ssdk_sh acl rule add $listid $ruleid 1 n 0 0" + #echo $cmd + if [ "$rt" == "ip4" ];then + cmd="$cmd ip4 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" + #echo $cmd + else + cmd="$cmd ip6 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" + #echo $cmd + fi + if [ $ruleid -le 3 ];then + #non-zero dscp + cmd="$cmd y 0x0 0xff" + elif [ $ruleid -le 7 ];then + #zero dscp + cmd="$cmd n" + elif [ $ruleid -le 11 ];then + #non-zero dscp + cmd="$cmd y 0x0 0xff" + else + #zero dscp + cmd="$cmd n" + fi + p=$((ruleid/2)) + cmd="$cmd y mask $((ruleid%2)) 0x1 y mask $((p%2)) 0x1 n n n n n n n n n n n n n n n y n n n n n n n y $qid n n 0 0 n n n n n n n n n n n n n n n n n n n n 0" + #echo $cmd + $cmd + ruleid=`expr $ruleid + 1` + done + done + ssdk_sh acl list bind $listid 0 1 $portmap + done +} + +function create_war_cosmap(){ + ssdk_sh cosmap pri2q set 0 0 + ssdk_sh cosmap pri2q set 1 0 + ssdk_sh cosmap pri2q set 2 0 + ssdk_sh cosmap pri2q set 3 0 + ssdk_sh cosmap pri2q set 4 1 + ssdk_sh cosmap pri2q set 5 1 + ssdk_sh cosmap pri2q set 6 1 + ssdk_sh cosmap pri2q set 7 1 + ssdk_sh cosmap pri2ehq set 0 0 + ssdk_sh cosmap pri2ehq set 1 0 + ssdk_sh cosmap pri2ehq set 2 0 + ssdk_sh cosmap pri2ehq set 3 0 + ssdk_sh cosmap pri2ehq set 4 1 + ssdk_sh cosmap pri2ehq set 5 1 + ssdk_sh cosmap pri2ehq set 6 1 + ssdk_sh cosmap pri2ehq set 7 1 +} + +function create_acl_byp_egstp_rules(){ + ssdk_sh debug module_func set servcode 0xf 0x0 0x0 + ssdk_sh servcode config set 1 n 0 0xfffefc7f 0xffbdff 0 0 0 0 0 0 + ssdk_sh debug module_func set servcode 0x0 0x0 0x0 + ssdk_sh acl list create 56 48 + ssdk_sh acl rule add 56 0 1 n 0 0 mac n n n n n y 01-80-c2-00-00-00 ff-ff-ff-ff-ff-ff n n n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl rule add 56 1 1 n 0 0 mac n n n n n n n yes 0x8809 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl rule add 56 2 1 n 0 0 mac n n n n n n n yes 0x888e 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl list bind 56 0 2 1 +} + +function delete_war_acl_rules(){ + for lw in $side + do + #echo $lw + if [ "$lw" == "wan" ];then + listid=254 + queue=$qwan + portmap=0x20 + else + listid=255 + queue=$qlan + portmap=0x1e + fi + ssdk_sh acl list unbind $listid 0 1 $portmap + for rt in $ruletype + do + for qid in $queue + do + cmd="ssdk_sh acl rule del $listid 0 1" + echo $cmd + $cmd + done + done + #echo "deleting list $listid" + ssdk_sh acl list destroy $listid + done +} + +function delete_war_cosmap(){ + ssdk_sh cosmap pri2q set 0 0 + ssdk_sh cosmap pri2q set 1 0 + ssdk_sh cosmap pri2q set 2 1 + ssdk_sh cosmap pri2q set 3 1 + ssdk_sh cosmap pri2q set 4 2 + ssdk_sh cosmap pri2q set 5 2 + ssdk_sh cosmap pri2q set 6 3 + ssdk_sh cosmap pri2q set 7 3 + ssdk_sh cosmap pri2ehq set 0 1 + ssdk_sh cosmap pri2ehq set 1 0 + ssdk_sh cosmap pri2ehq set 2 2 + ssdk_sh cosmap pri2ehq set 3 2 + ssdk_sh cosmap pri2ehq set 4 3 + ssdk_sh cosmap pri2ehq set 5 3 + ssdk_sh cosmap pri2ehq set 6 4 + ssdk_sh cosmap pri2ehq set 7 5 +} + +function delete_acl_byp_egstp_rules(){ + ssdk_sh debug module_func set servcode 0xf 0x0 0x0 + ssdk_sh servcode config set 1 n 0 0xfffefcff 0xffbfff 0 0 0 0 0 0 + ssdk_sh debug module_func set servcode 0x0 0x0 0x0 + ssdk_sh acl list unbind 56 0 2 1 + ssdk_sh acl rule del 56 0 1 + ssdk_sh acl rule del 56 1 1 + ssdk_sh acl rule del 56 2 1 + ssdk_sh acl list destroy 56 +} + +function edma_war_config_add(){ + create_war_cosmap + ssdk_sh acl status set enable + create_war_acl_rules +} + +function edma_war_config_del(){ + delete_war_acl_rules + delete_war_cosmap +} + +start() { + chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` + #The following commands should be uncommented to enable EDMA WAR + if [ "$chip_ver" = "0x1401" ]; then + #edma_war_config_add + echo '' + fi + #The following commands should be uncommented to add acl egress stp bypass rules + if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then + #create_acl_byp_egstp_rules + echo '' + fi + echo starting +} + +stop() { + chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` + #The following commands should be uncommented to disable EDMA WAR + if [ "$chip_ver" = "0x1401" ]; then + #edma_war_config_del + echo '' + fi + #The following commands should be uncommented to delete acl egress stp bypass rules + if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then + #delete_acl_byp_egstp_rules + echo '' + fi + echo stoping +} diff --git a/package/nss/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch b/package/nss/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch new file mode 100644 index 000000000..1ee44fa96 --- /dev/null +++ b/package/nss/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch @@ -0,0 +1,56 @@ +From 472c0c8132784608312c80c4b02c03ea7c132235 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 13:41:12 +0200 +Subject: [PATCH] SSDK: config: add kernel 5.10 + +This is purely to identify it and be able to set +flags correctly. + +Signed-off-by: Robert Marko +--- + config | 6 +++++- + make/linux_opt.mk | 4 ++-- + 2 files changed, 7 insertions(+), 3 deletions(-) + +--- a/config ++++ b/config +@@ -22,6 +22,10 @@ ifeq ($(KVER),$(filter 5.4%,$(KVER))) + OS_VER=5_4 + endif + ++ifeq ($(KVER),$(filter 5.10%,$(KVER))) ++OS_VER=5_10 ++endif ++ + ifeq ($(KVER), 3.4.0) + OS_VER=3_4 + endif +@@ -123,7 +127,7 @@ endif + endif + + ifeq ($(ARCH), arm64) +-ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER))) ++ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) + CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large + endif + endif +--- a/make/linux_opt.mk ++++ b/make/linux_opt.mk +@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + KASAN_SHADOW_SCALE_SHIFT := 3 + endif + +- ifeq (5_4, $(OS_VER)) ++ ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) + ifeq ($(ARCH), arm64) + KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) + endif +@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + + endif + +- ifeq ($(OS_VER),$(filter 4_4 5_4, $(OS_VER))) ++ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) + MODULE_CFLAG += -DKVER34 + MODULE_CFLAG += -DKVER32 + MODULE_CFLAG += -DLNX26_22 diff --git a/package/nss/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch b/package/nss/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..b293ad295 --- /dev/null +++ b/package/nss/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,102 @@ +From 784f2cfdfaf3bdf44917924e157049230a0ef5f8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 13:45:45 +0200 +Subject: [PATCH] SSDK: replace ioremap_nocache with ioremap + +ioremap_nocache was dropped upstream, simply use the +generic variety. + +Signed-off-by: Robert Marko +--- + src/init/ssdk_clk.c | 10 +++++----- + src/init/ssdk_init.c | 2 +- + src/init/ssdk_plat.c | 6 +++--- + 3 files changed, 9 insertions(+), 9 deletions(-) + +--- a/src/init/ssdk_clk.c ++++ b/src/init/ssdk_clk.c +@@ -623,7 +623,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, + { + void __iomem *tcsr_base = NULL; + +- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); ++ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); + if (!tcsr_base) + { + SSDK_ERROR("Failed to map tcsr eth address!\n"); +@@ -640,7 +640,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, + { + void __iomem *tcsr_base = NULL; + +- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); ++ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); + if (!tcsr_base) + { + SSDK_ERROR("Failed to map tcsr eth address!\n"); +@@ -688,7 +688,7 @@ ssdk_mp_cmnblk_stable_check(void) + a_uint32_t reg_val; + int i, loops = 20; + +- pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); ++ pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); + if (!pll_lock) { + SSDK_ERROR("Failed to map CMN PLL LOCK register!\n"); + return A_FALSE; +@@ -745,7 +745,7 @@ static void ssdk_cmnblk_pll_src_set(enum + void __iomem *cmn_pll_src_base = NULL; + a_uint32_t reg_val; + +- cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); ++ cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); + if (!cmn_pll_src_base) { + SSDK_ERROR("Failed to map cmn pll source address!\n"); + return; +@@ -766,7 +766,7 @@ static void ssdk_cmnblk_init(enum cmnblk + void __iomem *gcc_pll_base = NULL; + a_uint32_t reg_val; + +- gcc_pll_base = ioremap_nocache(CMN_BLK_ADDR, CMN_BLK_SIZE); ++ gcc_pll_base = ioremap(CMN_BLK_ADDR, CMN_BLK_SIZE); + if (!gcc_pll_base) { + SSDK_ERROR("Failed to map gcc pll address!\n"); + return; +--- a/src/init/ssdk_init.c ++++ b/src/init/ssdk_init.c +@@ -2770,7 +2770,7 @@ static int ssdk_dess_mac_mode_init(a_uin + (a_uint8_t *)®_value, 4); + mdelay(10); + /*softreset psgmii, fixme*/ +- gcc_addr = ioremap_nocache(0x1812000, 0x200); ++ gcc_addr = ioremap(0x1812000, 0x200); + if (!gcc_addr) { + SSDK_ERROR("gcc map fail!\n"); + return 0; +--- a/src/init/ssdk_plat.c ++++ b/src/init/ssdk_plat.c +@@ -1312,7 +1312,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id); + if(reg_mode == HSL_REG_LOCAL_BUS) { + ssdk_uniphy_reg_map_info_get(dev_id, &map); +- qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->uniphy_hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); +@@ -1327,7 +1327,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + reg_mode = ssdk_switch_reg_access_mode_get(dev_id); + if(reg_mode == HSL_REG_LOCAL_BUS) { + ssdk_switch_reg_map_info_get(dev_id, &map); +- qca_phy_priv_global[dev_id]->hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); +@@ -1358,7 +1358,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + return -1; + } + +- qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->psgmii_hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); diff --git a/package/nss/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch b/package/nss/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch new file mode 100644 index 000000000..3bcbcccf6 --- /dev/null +++ b/package/nss/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch @@ -0,0 +1,40 @@ +From b6190ca46287d01a895c7cc14de30410c09ff1b8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 17:15:46 +0200 +Subject: [PATCH] SSDK: platform: use of_mdio_find_bus() to get MDIO bus + +Kernel has a generic of_mdio_find_bus() which can get the appropriate +MDIO bus based on the DT node. +So, drop the getting MDIO from platform data, which no longer works +in 5.4 and later and use of_mdio_find_bus(). + +Signed-off-by: Baruch Siach +Signed-off-by: Robert Marko +--- + src/init/ssdk_plat.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +--- a/src/init/ssdk_plat.c ++++ b/src/init/ssdk_plat.c +@@ -551,7 +551,6 @@ static int miibus_get(a_uint32_t dev_id) + struct device_node *mdio_node = NULL; + struct device_node *switch_node = NULL; + struct platform_device *mdio_plat = NULL; +- struct ipq40xx_mdio_data *mdio_data = NULL; + struct qca_phy_priv *priv; + hsl_reg_mode reg_mode = HSL_REG_LOCAL_BUS; + priv = qca_phy_priv_global[dev_id]; +@@ -584,12 +583,7 @@ static int miibus_get(a_uint32_t dev_id) + + if(reg_mode == HSL_REG_LOCAL_BUS) + { +- mdio_data = dev_get_drvdata(&mdio_plat->dev); +- if (!mdio_data) { +- SSDK_ERROR("cannot get mdio_data reference from device data\n"); +- return 1; +- } +- priv->miibus = mdio_data->mii_bus; ++ priv->miibus = of_mdio_find_bus(mdio_node); + } + else + priv->miibus = dev_get_drvdata(&mdio_plat->dev); diff --git a/target/linux/ipq807x/Makefile b/target/linux/ipq807x/Makefile index dab05ca20..003893bca 100644 --- a/target/linux/ipq807x/Makefile +++ b/target/linux/ipq807x/Makefile @@ -2,13 +2,19 @@ include $(TOPDIR)/rules.mk ARCH:=aarch64 BOARD:=ipq807x -BOARDNAME:=Qualcomm Atheros IPQ807x -FEATURES:=squashfs ramdisk source-only +BOARDNAME:=Qualcomm IPQ807x +FEATURES:=squashfs ramdisk fpu nand source-only KERNELNAME:=Image dtbs CPU_TYPE:=cortex-a53 +SUBTARGETS:=generic -KERNEL_PATCHVER:=5.4 +KERNEL_PATCHVER:=5.10 include $(INCLUDE_DIR)/target.mk +DEFAULT_PACKAGES += \ + kmod-usb3 kmod-usb-dwc3 kmod-usb-dwc3-qcom \ + kmod-leds-gpio kmod-gpio-button-hotplug \ + ath11k-firmware-ipq8074 kmod-ath11k-ahb \ + wpad-basic-wolfssl kmod-qca-nss-dp $(eval $(call BuildTarget)) diff --git a/target/linux/ipq807x/base-files/etc/board.d/02_network b/target/linux/ipq807x/base-files/etc/board.d/02_network new file mode 100644 index 000000000..b9782d05f --- /dev/null +++ b/target/linux/ipq807x/base-files/etc/board.d/02_network @@ -0,0 +1,33 @@ +# +# Copyright (c) 2015 The Linux Foundation. All rights reserved. +# Copyright (c) 2011-2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh + +ipq807x_setup_interfaces() +{ + local board="$1" + + case "$board" in + netgear,sxr80|\ + xiaomi,ax9000) + ucidef_set_interfaces_lan_wan "eth0 eth1 eth2 eth3" "eth4" + ;; + redmi,ax6|\ + xiaomi,ax3600) + ucidef_set_interfaces_lan_wan "eth1 eth2 eth3" "eth0" + ;; + *) + echo "Unsupported hardware. Network interfaces not initialized" + ;; + esac +} + +board_config_update +board=$(board_name) +ipq807x_setup_interfaces $board +board_config_flush + +exit 0 diff --git a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata new file mode 100644 index 000000000..22d9e3421 --- /dev/null +++ b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -0,0 +1,27 @@ +#!/bin/sh + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/functions/caldata.sh + +board=$(board_name) + +case "$FIRMWARE" in +"ath10k/cal-pci-0000:01:00.0.bin") + case "$board" in + xiaomi,ax3600) + caldata_extract "0:art" 0x33000 0x844 + ;; + esac + ;; +"ath10k/cal-pci-0001:01:00.0.bin") + case "$board" in + xiaomi,ax9000) + caldata_extract "0:art" 0x4d000 0x844 + ;; + esac + ;; +*) + exit 1 + ;; +esac diff --git a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata index c2a980196..f11e1dbf7 100644 --- a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata +++ b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata @@ -1,4 +1,4 @@ -#!/bin/sh -x +#!/bin/sh [ -e /lib/firmware/$FIRMWARE ] && exit 0 @@ -7,10 +7,20 @@ board=$(board_name) case "$FIRMWARE" in -"IPQ8074/caldata.bin") +"ath11k/IPQ8074/hw2.0/caldata.bin") case "$board" in - xiaomi,ax3600) - caldata_extract "0:ART" 0x1000 0x20000 + netgear,sxr80|\ + redmi,ax6|\ + xiaomi,ax3600|\ + xiaomi,ax9000) + caldata_extract "0:art" 0x1000 0x20000 + ;; + esac + ;; +"ath11k/QCN9074/hw1.0/caldata.bin") + case "$board" in + xiaomi,ax9000) + caldata_extract "0:art" 0x26800 0x20000 ;; esac ;; diff --git a/target/linux/ipq807x/base-files/etc/init.d/bootcount b/target/linux/ipq807x/base-files/etc/init.d/bootcount index 280c109cf..62f400a58 100755 --- a/target/linux/ipq807x/base-files/etc/init.d/bootcount +++ b/target/linux/ipq807x/base-files/etc/init.d/bootcount @@ -4,6 +4,7 @@ START=99 boot() { case $(board_name) in + redmi,ax6|\ xiaomi,ax3600) # OTA handling should not be used. Reset it just in case. fw_setenv flag_ota_reboot 0 @@ -11,4 +12,4 @@ boot() { fw_setenv flag_boot_success 1 ;; esac -} \ No newline at end of file +} diff --git a/target/linux/ipq807x/base-files/etc/inittab b/target/linux/ipq807x/base-files/etc/inittab deleted file mode 100644 index 3181021a0..000000000 --- a/target/linux/ipq807x/base-files/etc/inittab +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2013 The Linux Foundation. All rights reserved. -::sysinit:/etc/init.d/rcS S boot -::shutdown:/etc/init.d/rcS K shutdown -ttyMSM0::askfirst:/usr/libexec/login.sh -ttyMSM1::askfirst:/usr/libexec/login.sh diff --git a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh old mode 100755 new mode 100644 index be37dcc3d..8068181fa --- a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh +++ b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh @@ -10,7 +10,9 @@ platform_check_image() { platform_do_upgrade() { case "$(board_name)" in - xiaomi,ax3600) + redmi,ax6|\ + xiaomi,ax3600|\ + xiaomi,ax9000) part_num="$(fw_printenv -n flag_boot_rootfs)" if [ "$part_num" -eq "0" ]; then CI_UBIPART="rootfs_1" @@ -40,4 +42,4 @@ platform_do_upgrade() { default_do_upgrade "$1" ;; esac -} \ No newline at end of file +} diff --git a/target/linux/ipq807x/config-5.4 b/target/linux/ipq807x/config-5.10 similarity index 54% rename from target/linux/ipq807x/config-5.4 rename to target/linux/ipq807x/config-5.10 index 4c66e2017..b4072d0ad 100644 --- a/target/linux/ipq807x/config-5.4 +++ b/target/linux/ipq807x/config-5.10 @@ -1,36 +1,7 @@ CONFIG_64BIT=y -# CONFIG_ALLOW_DEV_COREDUMP is not set # CONFIG_APQ_GCC_8084 is not set # CONFIG_APQ_MMCC_8084 is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y -CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_FAST_MULTIPLIER=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_GIGANTIC_PAGE=y -CONFIG_ARCH_HAS_KCOV=y -CONFIG_ARCH_HAS_KEEPINITRD=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_ARCH_HAS_PTE_DEVMAP=y -CONFIG_ARCH_HAS_PTE_SPECIAL=y -CONFIG_ARCH_HAS_SETUP_DMA_OPS=y -CONFIG_ARCH_HAS_SET_DIRECT_MAP=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MMAP_RND_BITS=18 @@ -40,209 +11,140 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_QCOM=y +CONFIG_ARCH_RANDOM=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_SUPPORTS_INT128=y -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_STACKWALK=y CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_USE_MEMREMAP_PROT=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y CONFIG_ARM64=y CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_AMU_EXTN=y +CONFIG_ARM64_BTI=y CONFIG_ARM64_CNP=y -CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARM64_CRYPTO=y +CONFIG_ARM64_E0PD=y CONFIG_ARM64_ERRATUM_1165522=y CONFIG_ARM64_ERRATUM_1286807=y CONFIG_ARM64_ERRATUM_1418040=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_MODULE_PLTS=y +CONFIG_ARM64_MTE=y CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_PAN=y CONFIG_ARM64_PA_BITS=48 CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_SSBD=y +CONFIG_ARM64_RAS_EXTN=y CONFIG_ARM64_SVE=y CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_UAO=y +CONFIG_ARM64_TLB_RANGE=y CONFIG_ARM64_VA_BITS=39 CONFIG_ARM64_VA_BITS_39=y CONFIG_ARM64_VHE=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y # CONFIG_ARMV8_DEPRECATED is not set CONFIG_ARM_AMBA=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_CCI=y -CONFIG_ARM_CCI400_COMMON=y -CONFIG_ARM_CCI400_PMU=y -CONFIG_ARM_CCI_PMU=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_V2M=y CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_PMU=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_QCOM_CPUFREQ_HW is not set # CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set # CONFIG_ARM_SCMI_PROTOCOL is not set -CONFIG_ASN1=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_ASYMMETRIC_KEY_TYPE=y -CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y -CONFIG_AT803X_PHY=y +CONFIG_ARM_SMCCC_SOC_ID=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_PM=y CONFIG_BLOCK_COMPAT=y CONFIG_CAVIUM_TX2_ERRATUM_219=y -CONFIG_CC_HAS_KASAN_GENERIC=y -# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CLEANCACHE=y CONFIG_CLKDEV_LOOKUP=y CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_QCOM=y CONFIG_COMPAT=y -CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_COMPAT_32BIT_TIME is not set CONFIG_COMPAT_BINFMT_ELF=y CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_CONFIGFS_FS=y CONFIG_COREDUMP=y -CONFIG_CORESIGHT=y -# CONFIG_CORESIGHT_CATU is not set -# CONFIG_CORESIGHT_CPU_DEBUG is not set -CONFIG_CORESIGHT_LINKS_AND_SINKS=y -CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -# CONFIG_CORESIGHT_SINK_ETBV10 is not set -CONFIG_CORESIGHT_SINK_TPIU=y -CONFIG_CORESIGHT_SOURCE_ETM4X=y -CONFIG_CORESIGHT_STM=y CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set CONFIG_CPU_FREQ_GOV_ATTR_SET=y CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_THERMAL=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y -# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_THERMAL=y CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DEV_QCE=y +CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y +# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set +# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set +CONFIG_CRYPTO_DEV_QCE_SHA=y +CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y +CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512 CONFIG_CRYPTO_DEV_QCOM_RNG=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set -# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set -CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_ZSTD=y CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_GPIO=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DEVMEM=y +CONFIG_DEV_COREDUMP=y CONFIG_DMADEVICES=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y CONFIG_DMA_REMAP=y CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DRM_RCAR_WRITEBACK=y CONFIG_DTC=y CONFIG_DT_IDLE_STATES=y -CONFIG_DYNAMIC_DEBUG=y CONFIG_EDAC_SUPPORT=y -CONFIG_EFI_EARLYCON=y -CONFIG_EXT4_FS=y -# CONFIG_EXT4_USE_FOR_EXT2 is not set -CONFIG_FB=y -CONFIG_FB_CMDLINE=y +CONFIG_ETHTOOL_NETLINK=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_AUTOSELECT=y -CONFIG_FONT_SUPPORT=y CONFIG_FRAME_POINTER=y -CONFIG_FRAME_WARN=2048 -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y CONFIG_FUJITSU_ERRATUM_010001=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y @@ -258,7 +160,6 @@ CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y @@ -278,172 +179,108 @@ CONFIG_GLOB=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_STACKLEAK=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ASM_MODVERSIONS=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FAST_GUP=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_VDSO=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_PATA_PLATFORM=y -CONFIG_HAVE_PCI=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SCHED_AVG_IRQ=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HOLES_IN_ZONE=y -CONFIG_HOTPLUG_CPU=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y -CONFIG_HW_RANDOM=y CONFIG_HZ=250 +# CONFIG_HZ_100 is not set CONFIG_HZ_250=y +CONFIG_HZ_PERIODIC=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y CONFIG_I2C_HELPER_AUTO=y +# CONFIG_I2C_QCOM_CCI is not set CONFIG_I2C_QUP=y -CONFIG_IIO=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IPQ_APSS_6018 is not set CONFIG_IPQ_APSS_8074=y +# CONFIG_IPQ_APSS_PLL is not set # CONFIG_IPQ_GCC_4019 is not set +# CONFIG_IPQ_GCC_6018 is not set # CONFIG_IPQ_GCC_806X is not set CONFIG_IPQ_GCC_8074=y # CONFIG_IPQ_LCC_806X is not set CONFIG_IRQCHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KEYS=y -CONFIG_KEYS_COMPAT=y # CONFIG_KPSS_XCC is not set -# CONFIG_KVM is not set CONFIG_LEDS_TLC591XX=y CONFIG_LIBFDT=y +CONFIG_LLD_VERSION=0 CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_MAILBOX=y # CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BITBANG=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_GPIO=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_IPQ4019=y # CONFIG_MDM_GCC_9615 is not set # CONFIG_MDM_LCC_9615 is not set CONFIG_MEMFD_CREATE=y -CONFIG_MFD_QCOM_RPM=y +# CONFIG_MFD_HI6421_SPMI is not set +# CONFIG_MFD_QCOM_RPM is not set CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_SYSCON=y +CONFIG_MHI_BUS=y +CONFIG_MHI_BUS_DEBUG=y CONFIG_MIGRATION=y CONFIG_MMC=y -CONFIG_MMC_ARMMMCI=y CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_QCOM_DML=y +CONFIG_MMC_CQHCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_MSM=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MODULES_TREE_LOOKUP=y CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MPILIB=y # CONFIG_MSM_GCC_8660 is not set # CONFIG_MSM_GCC_8916 is not set +# CONFIG_MSM_GCC_8939 is not set # CONFIG_MSM_GCC_8960 is not set # CONFIG_MSM_GCC_8974 is not set # CONFIG_MSM_GCC_8994 is not set # CONFIG_MSM_GCC_8996 is not set # CONFIG_MSM_GCC_8998 is not set +# CONFIG_MSM_GPUCC_8998 is not set # CONFIG_MSM_LCC_8960 is not set # CONFIG_MSM_MMCC_8960 is not set # CONFIG_MSM_MMCC_8974 is not set # CONFIG_MSM_MMCC_8996 is not set -CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MSM_MMCC_8998 is not set CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_QCOMSMEM_PARTS=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -CONFIG_MTD_UBI_GLUEBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SWITCHDEV=y -# CONFIG_NET_VENDOR_CAVIUM is not set CONFIG_NLS=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 +CONFIG_NR_CPUS=256 CONFIG_NVMEM=y -# CONFIG_OCTEONTX2_AF is not set +# CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_SYSFS=y CONFIG_OF=y CONFIG_OF_ADDRESS=y CONFIG_OF_EARLY_FLATTREE=y @@ -453,94 +290,90 @@ CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y CONFIG_OF_NET=y -CONFIG_OID_REGISTRY=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_PADATA=y -CONFIG_PANIC_TIMEOUT=5 CONFIG_PARTITION_PERCPU=y CONFIG_PCI=y -# CONFIG_PCIE_AL is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_PME=y CONFIG_PCIE_QCOM=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_EVENTS=y CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYLIB=y CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_PHY_QCOM_APQ8064_SATA is not set +# CONFIG_PHY_QCOM_IPQ4019_USB is not set # CONFIG_PHY_QCOM_IPQ806X_SATA is not set +# CONFIG_PHY_QCOM_IPQ806X_USB is not set # CONFIG_PHY_QCOM_PCIE2 is not set CONFIG_PHY_QCOM_QMP=y CONFIG_PHY_QCOM_QUSB2=y -# CONFIG_PHY_QCOM_UFS is not set -CONFIG_PID_IN_CONTEXTIDR=y +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set +# CONFIG_PHY_QCOM_USB_SS is not set CONFIG_PINCTRL=y # CONFIG_PINCTRL_APQ8064 is not set # CONFIG_PINCTRL_APQ8084 is not set # CONFIG_PINCTRL_IPQ4019 is not set +# CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8064 is not set CONFIG_PINCTRL_IPQ8074=y # CONFIG_PINCTRL_MDM9615 is not set CONFIG_PINCTRL_MSM=y +# CONFIG_PINCTRL_MSM8226 is not set # CONFIG_PINCTRL_MSM8660 is not set # CONFIG_PINCTRL_MSM8916 is not set # CONFIG_PINCTRL_MSM8960 is not set +# CONFIG_PINCTRL_MSM8976 is not set # CONFIG_PINCTRL_MSM8994 is not set # CONFIG_PINCTRL_MSM8996 is not set # CONFIG_PINCTRL_MSM8998 is not set -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set # CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set # CONFIG_PINCTRL_QCS404 is not set # CONFIG_PINCTRL_SC7180 is not set # CONFIG_PINCTRL_SDM660 is not set # CONFIG_PINCTRL_SDM845 is not set # CONFIG_PINCTRL_SM8150 is not set -# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +# CONFIG_PINCTRL_SM8250 is not set CONFIG_PM=y # CONFIG_PM8916_WATCHDOG is not set CONFIG_PM_CLK=y CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_MSM=y # CONFIG_POWER_RESET_QCOM_PON is not set CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y CONFIG_PRINTK_TIME=y -CONFIG_PROC_PAGE_MONITOR=y -# CONFIG_PROC_STRIPPED is not set -CONFIG_PTP_1588_CLOCK=y -CONFIG_PWM=y -CONFIG_PWM_SYSFS=y -CONFIG_QCOM_A53PLL=y +# CONFIG_QCOM_A53PLL is not set # CONFIG_QCOM_AOSS_QMP is not set CONFIG_QCOM_APCS_IPC=y # CONFIG_QCOM_APR is not set CONFIG_QCOM_BAM_DMA=y +# CONFIG_QCOM_CLK_APCC_MSM8996 is not set # CONFIG_QCOM_CLK_APCS_MSM8916 is not set -# CONFIG_QCOM_CLK_RPM is not set -# CONFIG_QCOM_CLK_RPMH is not set -# CONFIG_QCOM_CLK_SMD_RPM is not set # CONFIG_QCOM_COINCELL is not set # CONFIG_QCOM_COMMAND_DB is not set +# CONFIG_QCOM_CPR is not set CONFIG_QCOM_EBI2=y # CONFIG_QCOM_FASTRPC is not set # CONFIG_QCOM_GENI_SE is not set -CONFIG_QCOM_GLINK_SSR=y # CONFIG_QCOM_GSBI is not set # CONFIG_QCOM_HFPLL is not set +# CONFIG_QCOM_IPCC is not set # CONFIG_QCOM_LLCC is not set CONFIG_QCOM_MDT_LOADER=y +# CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set CONFIG_QCOM_PIL_INFO=y # CONFIG_QCOM_Q6V5_ADSP is not set @@ -551,53 +384,48 @@ CONFIG_QCOM_Q6V5_WCSS=y CONFIG_QCOM_QFPROM=y CONFIG_QCOM_QMI_HELPERS=y # CONFIG_QCOM_RMTFS_MEM is not set -CONFIG_QCOM_RPMH=y -CONFIG_QCOM_RPMPD=y +# CONFIG_QCOM_RPMH is not set CONFIG_QCOM_RPROC_COMMON=y CONFIG_QCOM_SCM=y -CONFIG_QCOM_SCM_64=y # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -CONFIG_QCOM_SMD_RPM=y +# CONFIG_QCOM_SMD_RPM is not set CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMEM_STATE=y CONFIG_QCOM_SMP2P=y # CONFIG_QCOM_SMSM is not set CONFIG_QCOM_SOCINFO=y -CONFIG_QCOM_SPMI_VADC=y -CONFIG_QCOM_SYSMON=y +# CONFIG_QCOM_SYSMON is not set CONFIG_QCOM_TSENS=y -CONFIG_QCOM_VADC_COMMON=y -CONFIG_QCOM_WCNSS_CTRL=y -CONFIG_QCOM_WCNSS_PIL=y +# CONFIG_QCOM_WCNSS_CTRL is not set +# CONFIG_QCOM_WCNSS_PIL is not set CONFIG_QCOM_WDT=y # CONFIG_QCS_GCC_404 is not set +# CONFIG_QCS_Q6SSTOP_404 is not set # CONFIG_QCS_TURING_404 is not set CONFIG_QRTR=y +CONFIG_QRTR_MHI=y CONFIG_QRTR_SMD=y -# CONFIG_QRTR_TUN is not set +CONFIG_QRTR_TUN=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_MODULE_REGION_FULL=y CONFIG_RATIONAL=y -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -# CONFIG_RCU_EXPERT is not set CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_RCU_STALL_COMMON=y -CONFIG_RD_GZIP=y -CONFIG_REFCOUNT_FULL=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y CONFIG_REGMAP_SPMI=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_QCOM_RPM=y -CONFIG_REGULATOR_QCOM_RPMH=y -CONFIG_REGULATOR_QCOM_SMD_RPM=y +# CONFIG_REGULATOR_QCOM_LABIBB is not set CONFIG_REGULATOR_QCOM_SPMI=y -CONFIG_RELAY=y +# CONFIG_REGULATOR_QCOM_USB_VBUS is not set +# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set +CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set @@ -605,15 +433,20 @@ CONFIG_RFS_ACCEL=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y CONFIG_RPMSG=y CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_QCOM_GLINK_NATIVE=y +CONFIG_RPMSG_QCOM_GLINK=y CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_RPMSG_QCOM_SMD=y CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_PM8XXX is not set -CONFIG_RTC_I2C_AND_SPI=y CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_THERMAL_PRESSURE=y +# CONFIG_SC_DISPCC_7180 is not set +# CONFIG_SC_GCC_7180 is not set +# CONFIG_SC_GPUCC_7180 is not set +# CONFIG_SC_LPASS_CORECC_7180 is not set +# CONFIG_SC_MSS_7180 is not set +# CONFIG_SC_VIDEOCC_7180 is not set # CONFIG_SDM_CAMCC_845 is not set # CONFIG_SDM_DISPCC_845 is not set # CONFIG_SDM_GCC_660 is not set @@ -621,92 +454,61 @@ CONFIG_RWSEM_SPIN_ON_OWNER=y # CONFIG_SDM_GPUCC_845 is not set # CONFIG_SDM_LPASSCC_845 is not set # CONFIG_SDM_VIDEOCC_845 is not set -# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SGL_ALLOC=y CONFIG_SMP=y # CONFIG_SM_GCC_8150 is not set -CONFIG_SND=y -# CONFIG_SND_COMPRESS_OFFLOAD is not set -CONFIG_SND_JACK=y -CONFIG_SND_PCM=y -CONFIG_SND_SOC=y -# CONFIG_SND_SOC_APQ8016_SBC is not set -CONFIG_SND_SOC_I2C_AND_SPI=y -CONFIG_SND_SOC_QCOM=y -# CONFIG_SND_SOC_STORM is not set +# CONFIG_SM_GCC_8250 is not set +# CONFIG_SM_GPUCC_8150 is not set +# CONFIG_SM_GPUCC_8250 is not set +# CONFIG_SM_VIDEOCC_8150 is not set +# CONFIG_SM_VIDEOCC_8250 is not set CONFIG_SOC_BUS=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSE_IRQ=y CONFIG_SPI=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set CONFIG_SPMI_MSM_PMIC_ARB=y # CONFIG_SPMI_PMIC_CLKDIV is not set CONFIG_SRCU=y -# CONFIG_STAGING is not set -CONFIG_STM=y -# CONFIG_STM_PROTO_BASIC is not set -# CONFIG_STM_PROTO_SYS_T is not set -# CONFIG_STM_SOURCE_HEARTBEAT is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y CONFIG_SWIOTLB=y CONFIG_SWPHY=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYSVIPC_COMPAT=y CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_TASKS_RCU=y CONFIG_THERMAL=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_NETLINK=y CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THREAD_INFO_IN_TASK=y CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y CONFIG_TREE_SRCU=y +# CONFIG_UACCE is not set CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UBIFS_FS_ZSTD=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB=y +CONFIG_USB_COMMON=y CONFIG_USB_SUPPORT=y CONFIG_VIRTIO=y # CONFIG_VIRTIO_BLK is not set -# CONFIG_VIRTIO_CONSOLE is not set # CONFIG_VIRTIO_NET is not set -CONFIG_VIRTUALIZATION=y CONFIG_VMAP_STACK=y -CONFIG_VM_EVENT_COUNTERS=y CONFIG_WANT_DEV_COREDUMP=y CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_XPS=y CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y CONFIG_ZONE_DMA32=y diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts index 6ca8ee7ca..0e5b1906e 100644 --- a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts +++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts @@ -1,262 +1,71 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Robert Marko */ + /dts-v1/; -#include "ipq8074.dtsi" -#include -#include +#include "ipq8071-ax3600.dtsi" / { - #address-cells = <0x2>; - #size-cells = <0x2>; - model = "Xiaomi Mi AIoT Router AX3600"; + model = "Xiaomi AX3600"; compatible = "xiaomi,ax3600", "qcom,ipq8074"; - interrupt-parent = <&intc>; - - aliases { - serial0 = &blsp1_uart5; - serial1 = &blsp1_uart3; - led-boot = &led_system_yellow; - led-failsafe = &led_system_yellow; - led-running = &led_system_blue; - led-upgrade = &led_system_yellow; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs-append = " swiotlb=1"; - }; - - reserved-memory { - ranges; - #address-cells = <0x2>; - #size-cells = <0x2>; - - tz@4ac00000 { - reg = <0x0 0x4ac00000 0x0 0x400000>; - no-map; - }; - - wcnss@4b000000 { - reg = <0x0 0x4b000000 0x0 0x3700000>; - no-map; - }; - - rsvd2@50b00000 { - reg = <0x0 0x50b00000 0x0 0x400000>; - no-map; - }; - - wifi_dump@50500000 { - reg = <0x0 0x50500000 0x0 0x200000>; - no-map; - }; - - rsvd1@50700000 { - reg = <0x0 0x50700000 0x0 0x400000>; - no-map; - }; - - q6_etr_dump@4e700000 { - reg = <0x0 0x4e700000 0x0 0x100000>; - no-map; - }; - - sbl@4aa00000 { - reg = <0x0 0x4aa00000 0x0 0x100000>; - no-map; - }; - - uboot@4a600000 { - reg = <0x0 0x4a600000 0x0 0x400000>; - no-map; - }; - - nss@40000000 { - reg = <0x0 0x40000000 0x0 0x1000000>; - no-map; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; leds { compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; led_system_blue: system-blue { - label = "ax3600:blue:system"; + label = "blue:system"; gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; }; led_system_yellow: system-yellow { - label = "ax3600:yellow:system"; + label = "yellow:system"; gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>; }; network-yellow { - label = "ax3600:yellow:network"; + label = "yellow:network"; gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; }; network-blue { - label = "ax3600:blue:network"; + label = "blue:network"; gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; }; aiot { - label = "ax3600:blue:aiot"; + label = "blue:aiot"; gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; }; }; }; -&blsp1_uart3 { +&qmp_pcie_phy0 { status = "okay"; }; -&blsp1_uart5 { - status = "okay"; -}; - -&qpic_bam { - status = "okay"; -}; - -&qpic_nand { +&pcie0 { status = "okay"; - nand@0 { - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; + perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; - partition@0 { - label = "0:SBL1"; - reg = <0x00000000 0x100000>; - read-only; - }; + wifi0: wifi@1,0 { + status = "okay"; - partition@100000 { - label = "0:MIBIB"; - reg = <0x00100000 0x100000>; - read-only; - }; + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; - partition@200000 { - label = "0:QSEE"; - reg = <0x00200000 0x300000>; - read-only; - }; - - partition@500000 { - label = "0:DEVCFG"; - reg = <0x00500000 0x80000>; - read-only; - }; - - partition@580000 { - label = "0:RPM"; - reg = <0x00580000 0x80000>; - read-only; - }; - - partition@600000 { - label = "0:CDT"; - reg = <0x00600000 0x80000>; - read-only; - }; - - partition@680000 { - label = "0:APPSBLENV"; - reg = <0x00680000 0x80000>; - }; - - partition@700000 { - label = "0:APPSBL"; - reg = <0x00700000 0x100000>; - read-only; - }; - - partition@800000 { - label = "0:ART"; - reg = <0x00800000 0x80000>; - read-only; - }; - - partition@880000 { - label = "bdata"; - reg = <0x00880000 0x80000>; - read-only; - }; - - partition@900000 { - label = "crash"; - reg = <0x00900000 0x80000>; - read-only; - }; - - partition@980000 { - label = "crash_syslog"; - reg = <0x00980000 0x80000>; - read-only; - }; - - partition@a00000 { - label = "rootfs"; - reg = <0x00a00000 0x23c0000>; - }; - - partition@2dc0000 { - label = "rootfs_1"; - reg = <0x02dc0000 0x23c0000>; - }; - - partition@5180000 { - label = "overlay"; - reg = <0x05180000 0x1ec0000>; - }; - - partition@7040000 { - label = "rsvd0"; - reg = <0x07040000 0x80000>; - }; + qcom,ath10k-calibration-variant = "Xiaomi-AX3600"; }; }; }; -&wifi0 { - status = "okay"; -}; - -&tlmm { - button_pins: button-pins { - pins = "gpio34"; - function = "gpio"; - bias-pull-up; - drive-strength = <8>; - }; - - led_pins: led-pins { - pins = "gpio21", "gpio22", "gpio42", "gpio43", "gpio51"; - function = "gpio"; - bias-pull-down; - drive-strength = <8>; - }; +&wifi { + qcom,ath11k-calibration-variant = "Xiaomi-AX3600"; }; diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi new file mode 100644 index 000000000..153bced8a --- /dev/null +++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Robert Marko */ + +#include "ipq8074.dtsi" +#include "ipq8074-ac-cpu.dtsi" +#include "ipq8074-ac-nss.dtsi" +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + led-boot = &led_system_yellow; + led-failsafe = &led_system_yellow; + led-running = &led_system_blue; + led-upgrade = &led_system_yellow; + /* Aliases as required by u-boot to patch MAC addresses */ + ethernet1 = &dp2; + ethernet2 = &dp3; + ethernet3 = &dp4; + ethernet4 = &dp5; + label-mac-device = &dp2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&tlmm { + mdio_pins: mdio-pins { + mdc { + pins = "gpio68"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio { + pins = "gpio69"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&blsp1_uart5 { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + /* + * Disable the reset GPIO temporarely as it + * resets the 100Mbit LED configuration which + * the bootloader writes. + */ + //reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; + + ethernet-phy@1 { + reg = <1>; + }; + + ethernet-phy@2 { + reg = <2>; + }; + + ethernet-phy@3 { + reg = <3>; + }; + + ethernet-phy@4 { + reg = <4>; + }; +}; + +&ess_switch { + switch_cpu_bmp = <0x1>; /* cpu port bitmap */ + switch_lan_bmp = <0x1e>; /* lan port bitmap */ + switch_wan_bmp = <0x20>; /* wan port bitmap */ + switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ + switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/ + switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ + bm_tick_mode = <0>; /* bm tick mode */ + tm_tick_mode = <0>; /* tm tick mode */ + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <0>; + }; + port@1 { + port_id = <2>; + phy_address = <1>; + }; + port@2 { + port_id = <3>; + phy_address = <2>; + }; + port@3 { + port_id = <4>; + phy_address = <3>; + }; + port@4 { + port_id = <5>; + phy_address = <4>; + }; + }; + port_scheduler_resource { + port@0 { + port_id = <0>; + ucast_queue = <0 143>; + mcast_queue = <256 271>; + l0sp = <0 35>; + l0cdrr = <0 47>; + l0edrr = <0 47>; + l1cdrr = <0 7>; + l1edrr = <0 7>; + }; + port@1 { + port_id = <1>; + ucast_queue = <144 159>; + mcast_queue = <272 275>; + l0sp = <36 39>; + l0cdrr = <48 63>; + l0edrr = <48 63>; + l1cdrr = <8 11>; + l1edrr = <8 11>; + }; + port@2 { + port_id = <2>; + ucast_queue = <160 175>; + mcast_queue = <276 279>; + l0sp = <40 43>; + l0cdrr = <64 79>; + l0edrr = <64 79>; + l1cdrr = <12 15>; + l1edrr = <12 15>; + }; + port@3 { + port_id = <3>; + ucast_queue = <176 191>; + mcast_queue = <280 283>; + l0sp = <44 47>; + l0cdrr = <80 95>; + l0edrr = <80 95>; + l1cdrr = <16 19>; + l1edrr = <16 19>; + }; + port@4 { + port_id = <4>; + ucast_queue = <192 207>; + mcast_queue = <284 287>; + l0sp = <48 51>; + l0cdrr = <96 111>; + l0edrr = <96 111>; + l1cdrr = <20 23>; + l1edrr = <20 23>; + }; + port@5 { + port_id = <5>; + ucast_queue = <208 223>; + mcast_queue = <288 291>; + l0sp = <52 55>; + l0cdrr = <112 127>; + l0edrr = <112 127>; + l1cdrr = <24 27>; + l1edrr = <24 27>; + }; + port@6 { + port_id = <6>; + ucast_queue = <224 239>; + mcast_queue = <292 295>; + l0sp = <56 59>; + l0cdrr = <128 143>; + l0edrr = <128 143>; + l1cdrr = <28 31>; + l1edrr = <28 31>; + }; + port@7 { + port_id = <7>; + ucast_queue = <240 255>; + mcast_queue = <296 299>; + l0sp = <60 63>; + l0cdrr = <144 159>; + l0edrr = <144 159>; + l1cdrr = <32 35>; + l1edrr = <32 35>; + }; + }; + port_scheduler_config { + port@0 { + port_id = <0>; + l1scheduler { + group@0 { + sp = <0 1>; /*L0 SPs*/ + /*cpri cdrr epri edrr*/ + cfg = <0 0 0 0>; + }; + }; + l0scheduler { + group@0 { + /*unicast queues*/ + ucast_queue = <0 4 8>; + /*multicast queues*/ + mcast_queue = <256 260>; + /*sp cpri cdrr epri edrr*/ + cfg = <0 0 0 0 0>; + }; + group@1 { + ucast_queue = <1 5 9>; + mcast_queue = <257 261>; + cfg = <0 1 1 1 1>; + }; + group@2 { + ucast_queue = <2 6 10>; + mcast_queue = <258 262>; + cfg = <0 2 2 2 2>; + }; + group@3 { + ucast_queue = <3 7 11>; + mcast_queue = <259 263>; + cfg = <0 3 3 3 3>; + }; + }; + }; + port@1 { + port_id = <1>; + l1scheduler { + group@0 { + sp = <36>; + cfg = <0 8 0 8>; + }; + group@1 { + sp = <37>; + cfg = <1 9 1 9>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <144>; + ucast_loop_pri = <16>; + mcast_queue = <272>; + mcast_loop_pri = <4>; + cfg = <36 0 48 0 48>; + }; + }; + }; + port@2 { + port_id = <2>; + l1scheduler { + group@0 { + sp = <40>; + cfg = <0 12 0 12>; + }; + group@1 { + sp = <41>; + cfg = <1 13 1 13>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <160>; + ucast_loop_pri = <16>; + mcast_queue = <276>; + mcast_loop_pri = <4>; + cfg = <40 0 64 0 64>; + }; + }; + }; + port@3 { + port_id = <3>; + l1scheduler { + group@0 { + sp = <44>; + cfg = <0 16 0 16>; + }; + group@1 { + sp = <45>; + cfg = <1 17 1 17>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <176>; + ucast_loop_pri = <16>; + mcast_queue = <280>; + mcast_loop_pri = <4>; + cfg = <44 0 80 0 80>; + }; + }; + }; + port@4 { + port_id = <4>; + l1scheduler { + group@0 { + sp = <48>; + cfg = <0 20 0 20>; + }; + group@1 { + sp = <49>; + cfg = <1 21 1 21>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <192>; + ucast_loop_pri = <16>; + mcast_queue = <284>; + mcast_loop_pri = <4>; + cfg = <48 0 96 0 96>; + }; + }; + }; + port@5 { + port_id = <5>; + l1scheduler { + group@0 { + sp = <52>; + cfg = <0 24 0 24>; + }; + group@1 { + sp = <53>; + cfg = <1 25 1 25>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <208>; + ucast_loop_pri = <16>; + mcast_queue = <288>; + mcast_loop_pri = <4>; + cfg = <52 0 112 0 112>; + }; + }; + }; + port@6 { + port_id = <6>; + l1scheduler { + group@0 { + sp = <56>; + cfg = <0 28 0 28>; + }; + group@1 { + sp = <57>; + cfg = <1 29 1 29>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <224>; + ucast_loop_pri = <16>; + mcast_queue = <292>; + mcast_loop_pri = <4>; + cfg = <56 0 128 0 128>; + }; + }; + }; + port@7 { + port_id = <7>; + l1scheduler { + group@0 { + sp = <60>; + cfg = <0 32 0 32>; + }; + group@1 { + sp = <61>; + cfg = <1 33 1 33>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <240>; + ucast_loop_pri = <16>; + mcast_queue = <296>; + cfg = <60 0 144 0 144>; + }; + }; + }; + }; +}; + +&soc { + dp2: dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <2>; + reg = <0x3a001200 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <1>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp3: dp3 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <3>; + reg = <0x3a001400 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <2>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp4: dp4 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <4>; + reg = <0x3a001600 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <3>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp5: dp5 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <5>; + reg = <0x3a001800 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <4>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; +}; + +&wifi { + status = "okay"; + + qcom,board_id = <658>; +}; diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts new file mode 100644 index 000000000..c66fb95bc --- /dev/null +++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Zhijun You */ + +/dts-v1/; + +#include "ipq8071-ax3600.dtsi" + +/ { + model = "Redmi AX6"; + compatible = "redmi,ax6", "qcom,ipq8074"; + + leds { + compatible = "gpio-leds"; + + led_system_blue: system-blue { + label = "blue:system"; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + }; + + led_system_yellow: system-yellow { + label = "yellow:system"; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; + }; + + network-blue { + label = "blue:network"; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + }; + + network-yellow { + label = "yellow:network"; + gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&wifi { + qcom,ath11k-calibration-variant = "Redmi-AX6"; +}; diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts new file mode 100644 index 000000000..1f84807a1 --- /dev/null +++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts @@ -0,0 +1,629 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2021, Robert Marko */ + +/dts-v1/; + +#include "ipq8074.dtsi" +#include "ipq8074-hk-cpu.dtsi" +#include "ipq8074-ac-nss.dtsi" +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + model = "Xiaomi AX9000"; + compatible = "xiaomi,ax9000", "qcom,ipq8074"; + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + led-boot = &led_system_yellow; + led-failsafe = &led_system_yellow; + led-running = &led_system_blue; + led-upgrade = &led_system_yellow; + /* Aliases as required by u-boot to patch MAC addresses */ + ethernet0 = &dp1; + ethernet1 = &dp2; + ethernet2 = &dp3; + ethernet3 = &dp4; + ethernet4 = &dp5; + label-mac-device = &dp5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; /* Labeled Mesh on the device */ + gpios = <&tlmm 46 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_system_blue: system-blue { + label = "blue:system"; + gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + color = ; + }; + + led_system_yellow: system-yellow { + label = "yellow:system"; + gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + color = ; + }; + + network-yellow { + label = "yellow:network"; + gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>; + color = ; + }; + + network-blue { + label = "blue:network"; + gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + color = ; + }; + + top-red { + label = "red:top"; + gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>; + color = ; + default-state = "keep"; + }; + + top-green { + label = "green:top"; + gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + color = ; + default-state = "keep"; + }; + + top-blue { + label = "blue:top"; + gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>; + color = ; + default-state = "keep"; + }; + }; +}; + +&tlmm { + mdio_pins: mdio-pins { + mdc { + pins = "gpio68"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio { + pins = "gpio69"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + i2c_pins: i2c-pins { + pins = "gpio0", "gpio2"; + function = "blsp5_i2c"; + drive-strength = <8>; + bias-disable; + }; +}; + +&blsp1_uart5 { + status = "okay"; +}; + +&blsp1_i2c6 { + status = "okay"; + + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + + /* Driver missing, justa placeholder */ + emc2301@2f { + compatible = "smsc,emc2301"; + reg = <0x2f>; + }; +}; + +&prng { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&qusb_phy_0 { + status = "okay"; +}; + +&ssphy_0 { + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; + + ethernet-phy@0 { + reg = <0>; + }; + + ethernet-phy@1 { + reg = <1>; + }; + + ethernet-phy@2 { + reg = <2>; + }; + + ethernet-phy@3 { + reg = <3>; + }; + + ethernet-phy@24 { + /* + * It looks like the PHY is too slow for + * auto probing after reset is deasserted + * so set the ID manually. + */ + compatible = "ethernet-phy-id004d.d101"; + reg = <24>; + reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + }; +}; + +&qmp_pcie_phy0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>; +}; + +&qmp_pcie_phy1 { + status = "disabled"; +}; + +&pcie1 { + status = "disabled"; + + perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>; +}; + +&ess_switch { + switch_cpu_bmp = <0x1>; /* cpu port bitmap */ + switch_lan_bmp = <0x1e>; /* lan port bitmap */ + switch_wan_bmp = <0x20>; /* wan port bitmap */ + switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ + switch_mac_mode1 = <0x0f>; /* mac mode for uniphy instance1*/ + switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ + bm_tick_mode = <0>; /* bm tick mode */ + tm_tick_mode = <0>; /* tm tick mode */ + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <0>; + }; + + port@1 { + port_id = <2>; + phy_address = <1>; + }; + + port@2 { + port_id = <3>; + phy_address = <2>; + }; + + port@3 { + port_id = <4>; + phy_address = <3>; + }; + + port@4 { + port_id = <5>; + phy_address = <24>; + port_mac_sel = "QGMAC_PORT"; + }; + }; + port_scheduler_resource { + port@0 { + port_id = <0>; + ucast_queue = <0 143>; + mcast_queue = <256 271>; + l0sp = <0 35>; + l0cdrr = <0 47>; + l0edrr = <0 47>; + l1cdrr = <0 7>; + l1edrr = <0 7>; + }; + port@1 { + port_id = <1>; + ucast_queue = <144 159>; + mcast_queue = <272 275>; + l0sp = <36 39>; + l0cdrr = <48 63>; + l0edrr = <48 63>; + l1cdrr = <8 11>; + l1edrr = <8 11>; + }; + port@2 { + port_id = <2>; + ucast_queue = <160 175>; + mcast_queue = <276 279>; + l0sp = <40 43>; + l0cdrr = <64 79>; + l0edrr = <64 79>; + l1cdrr = <12 15>; + l1edrr = <12 15>; + }; + port@3 { + port_id = <3>; + ucast_queue = <176 191>; + mcast_queue = <280 283>; + l0sp = <44 47>; + l0cdrr = <80 95>; + l0edrr = <80 95>; + l1cdrr = <16 19>; + l1edrr = <16 19>; + }; + port@4 { + port_id = <4>; + ucast_queue = <192 207>; + mcast_queue = <284 287>; + l0sp = <48 51>; + l0cdrr = <96 111>; + l0edrr = <96 111>; + l1cdrr = <20 23>; + l1edrr = <20 23>; + }; + port@5 { + port_id = <5>; + ucast_queue = <208 223>; + mcast_queue = <288 291>; + l0sp = <52 55>; + l0cdrr = <112 127>; + l0edrr = <112 127>; + l1cdrr = <24 27>; + l1edrr = <24 27>; + }; + port@6 { + port_id = <6>; + ucast_queue = <224 239>; + mcast_queue = <292 295>; + l0sp = <56 59>; + l0cdrr = <128 143>; + l0edrr = <128 143>; + l1cdrr = <28 31>; + l1edrr = <28 31>; + }; + port@7 { + port_id = <7>; + ucast_queue = <240 255>; + mcast_queue = <296 299>; + l0sp = <60 63>; + l0cdrr = <144 159>; + l0edrr = <144 159>; + l1cdrr = <32 35>; + l1edrr = <32 35>; + }; + }; + port_scheduler_config { + port@0 { + port_id = <0>; + l1scheduler { + group@0 { + sp = <0 1>; /*L0 SPs*/ + /*cpri cdrr epri edrr*/ + cfg = <0 0 0 0>; + }; + }; + l0scheduler { + group@0 { + /*unicast queues*/ + ucast_queue = <0 4 8>; + /*multicast queues*/ + mcast_queue = <256 260>; + /*sp cpri cdrr epri edrr*/ + cfg = <0 0 0 0 0>; + }; + group@1 { + ucast_queue = <1 5 9>; + mcast_queue = <257 261>; + cfg = <0 1 1 1 1>; + }; + group@2 { + ucast_queue = <2 6 10>; + mcast_queue = <258 262>; + cfg = <0 2 2 2 2>; + }; + group@3 { + ucast_queue = <3 7 11>; + mcast_queue = <259 263>; + cfg = <0 3 3 3 3>; + }; + }; + }; + port@1 { + port_id = <1>; + l1scheduler { + group@0 { + sp = <36>; + cfg = <0 8 0 8>; + }; + group@1 { + sp = <37>; + cfg = <1 9 1 9>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <144>; + ucast_loop_pri = <16>; + mcast_queue = <272>; + mcast_loop_pri = <4>; + cfg = <36 0 48 0 48>; + }; + }; + }; + port@2 { + port_id = <2>; + l1scheduler { + group@0 { + sp = <40>; + cfg = <0 12 0 12>; + }; + group@1 { + sp = <41>; + cfg = <1 13 1 13>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <160>; + ucast_loop_pri = <16>; + mcast_queue = <276>; + mcast_loop_pri = <4>; + cfg = <40 0 64 0 64>; + }; + }; + }; + port@3 { + port_id = <3>; + l1scheduler { + group@0 { + sp = <44>; + cfg = <0 16 0 16>; + }; + group@1 { + sp = <45>; + cfg = <1 17 1 17>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <176>; + ucast_loop_pri = <16>; + mcast_queue = <280>; + mcast_loop_pri = <4>; + cfg = <44 0 80 0 80>; + }; + }; + }; + port@4 { + port_id = <4>; + l1scheduler { + group@0 { + sp = <48>; + cfg = <0 20 0 20>; + }; + group@1 { + sp = <49>; + cfg = <1 21 1 21>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <192>; + ucast_loop_pri = <16>; + mcast_queue = <284>; + mcast_loop_pri = <4>; + cfg = <48 0 96 0 96>; + }; + }; + }; + port@5 { + port_id = <5>; + l1scheduler { + group@0 { + sp = <52>; + cfg = <0 24 0 24>; + }; + group@1 { + sp = <53>; + cfg = <1 25 1 25>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <208>; + ucast_loop_pri = <16>; + mcast_queue = <288>; + mcast_loop_pri = <4>; + cfg = <52 0 112 0 112>; + }; + }; + }; + port@6 { + port_id = <6>; + l1scheduler { + group@0 { + sp = <56>; + cfg = <0 28 0 28>; + }; + group@1 { + sp = <57>; + cfg = <1 29 1 29>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <224>; + ucast_loop_pri = <16>; + mcast_queue = <292>; + mcast_loop_pri = <4>; + cfg = <56 0 128 0 128>; + }; + }; + }; + port@7 { + port_id = <7>; + l1scheduler { + group@0 { + sp = <60>; + cfg = <0 32 0 32>; + }; + group@1 { + sp = <61>; + cfg = <1 33 1 33>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <240>; + ucast_loop_pri = <16>; + mcast_queue = <296>; + cfg = <60 0 144 0 144>; + }; + }; + }; + }; +}; + +&soc { + dp1: dp1 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <1>; + reg = <0x3a001000 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <0>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp2: dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <2>; + reg = <0x3a001200 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <1>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp3: dp3 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <3>; + reg = <0x3a001400 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <2>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp4: dp4 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <4>; + reg = <0x3a001600 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <3>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp5: dp5 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <5>; + reg = <0x3a001800 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <24>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; +}; + +&wifi { + status = "okay"; + + qcom,board_id = <660>; + qcom,ath11k-calibration-variant = "Xiaomi-AX9000"; +}; diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi new file mode 100644 index 000000000..4b2c3c484 --- /dev/null +++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-only + +&CPU0 { + operating-points-v2 = <&cpu_opp_table>; + voltage-tolerance = <1>; + cpu0-supply = <&s3>; +}; + +&CPU1 { + operating-points-v2 = <&cpu_opp_table>; + voltage-tolerance = <1>; + cpu-supply = <&s3>; +}; + +&CPU2 { + operating-points-v2 = <&cpu_opp_table>; + voltage-tolerance = <1>; + cpu-supply = <&s3>; +}; + +&CPU3 { + operating-points-v2 = <&cpu_opp_table>; + voltage-tolerance = <1>; + cpu-supply = <&s3>; +}; + +&cpus { + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-microvolt = <704000>; + clock-latency-ns = <200000>; + }; + opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-microvolt = <824000>; + clock-latency-ns = <200000>; + }; + }; +}; + +&cpu0_thermal { + trips { + cpu0_passive: cpu-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_passive>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu1_thermal { + trips { + cpu1_passive: cpu-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_passive>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu2_thermal { + trips { + cpu2_passive: cpu-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_passive>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu3_thermal { + trips { + cpu3_passive: cpu-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_passive>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cluster_thermal { + trips { + cluster_passive: cluster-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster_crit: cluster_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cluster_passive>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-nss.dtsi b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-nss.dtsi new file mode 100644 index 000000000..608d07f78 --- /dev/null +++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-nss.dtsi @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0-only + +&soc { + dummy_reg: dummy-regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "dummy-reg"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <848000>; + regulator-always-on; + regulator-boot-on; + }; + + nss-common { + compatible = "qcom,nss-common"; + reg = <0x01868010 0x1000>; + reg-names = "nss-misc-reset"; + }; + + nss0: nss@40000000 { + compatible = "qcom,nss"; + interrupts = , + , + , + , + , + , + , + , + , + ; + reg = <0x39000000 0x1000>, + <0x38000000 0x30000>, + <0x0b111000 0x1000>; + reg-names = "nphys", "vphys", "qgic-phys"; + clocks = <&gcc GCC_NSS_NOC_CLK>, + <&gcc GCC_NSS_PTP_REF_CLK>, + <&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>, + <&gcc GCC_NSS_IMEM_CLK>, + <&gcc GCC_NSSNOC_QOSGEN_REF_CLK>, + <&gcc GCC_MEM_NOC_NSS_AXI_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>, + <&gcc GCC_NSS_CE_AXI_CLK>, + <&gcc GCC_NSS_CE_APB_CLK>, + <&gcc GCC_NSSNOC_CE_AXI_CLK>, + <&gcc GCC_NSSNOC_CE_APB_CLK>, + <&gcc GCC_NSSNOC_UBI0_AHB_CLK>, + <&gcc GCC_UBI0_CORE_CLK>, + <&gcc GCC_UBI0_AHB_CLK>, + <&gcc GCC_UBI0_AXI_CLK>, + <&gcc GCC_UBI0_MPT_CLK>, + <&gcc GCC_UBI0_NC_AXI_CLK>; + clock-names = "nss-noc-clk", "nss-ptp-ref-clk", + "nss-csr-clk", "nss-cfg-clk", + "nss-imem-clk", + "nss-nssnoc-qosgen-ref-clk", + "nss-mem-noc-nss-axi-clk", + "nss-nssnoc-snoc-clk", + "nss-nssnoc-timeout-ref-clk", + "nss-ce-axi-clk", "nss-ce-apb-clk", + "nss-nssnoc-ce-axi-clk", + "nss-nssnoc-ce-apb-clk", + "nss-nssnoc-ahb-clk", + "nss-core-clk", "nss-ahb-clk", + "nss-axi-clk", "nss-mpt-clk", + "nss-nc-axi-clk"; + qcom,id = <0>; + qcom,num-queue = <4>; + qcom,num-irq = <10>; + qcom,num-pri = <4>; + qcom,load-addr = <0x40000000>; + qcom,low-frequency = <187200000>; + qcom,mid-frequency = <748800000>; + qcom,max-frequency = <1497600000>; + npu-supply = <&dummy_reg>; + mx-supply = <&dummy_reg>; + qcom,bridge-enabled; + qcom,ipv4-enabled; + qcom,ipv4-reasm-enabled; + qcom,ipv6-enabled; + qcom,ipv6-reasm-enabled; + qcom,wlanredirect-enabled; + qcom,tun6rd-enabled; + qcom,l2tpv2-enabled; + qcom,gre-enabled; + qcom,gre-redir-enabled; + qcom,gre-redir-mark-enabled; + qcom,map-t-enabled; + qcom,portid-enabled; + qcom,ppe-enabled; + qcom,pppoe-enabled; + qcom,pptp-enabled; + qcom,tunipip6-enabled; + qcom,shaping-enabled; + qcom,wlan-dataplane-offload-enabled; + qcom,vlan-enabled; + qcom,igs-enabled; + qcom,vxlan-enabled; + qcom,match-enabled; + qcom,mirror-enabled; + qcom,udp-st-enabled; + }; + + nss1: nss@40800000 { + compatible = "qcom,nss"; + interrupts = , + , + , + , + , + , + , + , + ; + reg = <0x39400000 0x1000>, + <0x38030000 0x30000>, + <0x0b111000 0x1000>; + reg-names = "nphys", "vphys", "qgic-phys"; + clocks = <&gcc GCC_NSS_NOC_CLK>, + <&gcc GCC_NSS_PTP_REF_CLK>, + <&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>, + <&gcc GCC_NSS_IMEM_CLK>, + <&gcc GCC_NSSNOC_QOSGEN_REF_CLK>, + <&gcc GCC_MEM_NOC_NSS_AXI_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>, + <&gcc GCC_NSS_CE_AXI_CLK>, + <&gcc GCC_NSS_CE_APB_CLK>, + <&gcc GCC_NSSNOC_CE_AXI_CLK>, + <&gcc GCC_NSSNOC_CE_APB_CLK>, + <&gcc GCC_NSSNOC_UBI1_AHB_CLK>, + <&gcc GCC_UBI1_CORE_CLK>, + <&gcc GCC_UBI1_AHB_CLK>, + <&gcc GCC_UBI1_AXI_CLK>, + <&gcc GCC_UBI1_MPT_CLK>, + <&gcc GCC_UBI1_NC_AXI_CLK>; + clock-names = "nss-noc-clk", "nss-ptp-ref-clk", + "nss-csr-clk", "nss-cfg-clk", + "nss-imem-clk", + "nss-nssnoc-qosgen-ref-clk", + "nss-mem-noc-nss-axi-clk", + "nss-nssnoc-snoc-clk", + "nss-nssnoc-timeout-ref-clk", + "nss-ce-axi-clk", "nss-ce-apb-clk", + "nss-nssnoc-ce-axi-clk", + "nss-nssnoc-ce-apb-clk", + "nss-nssnoc-ahb-clk", + "nss-core-clk", "nss-ahb-clk", + "nss-axi-clk", "nss-mpt-clk", + "nss-nc-axi-clk"; + qcom,id = <1>; + qcom,num-queue = <4>; + qcom,num-irq = <9>; + qcom,num-pri = <4>; + qcom,load-addr = <0x40800000>; + qcom,capwap-enabled; + qcom,dtls-enabled; + qcom,tls-enabled; + qcom,crypto-enabled; + qcom,ipsec-enabled; + qcom,qvpn-enabled; + qcom,pvxlan-enabled; + qcom,clmap-enabled; + qcom,rmnet_rx-enabled; + }; + + nss_crypto: qcom,nss_crypto { + compatible = "qcom,nss-crypto"; + #address-cells = <1>; + #size-cells = <1>; + qcom,max-contexts = <64>; + qcom,max-context-size = <32>; + ranges; + + eip197_node { + compatible = "qcom,eip197"; + reg-names = "crypto_pbase"; + reg = <0x39800000 0x7ffff>; + clocks = <&gcc GCC_NSS_CRYPTO_CLK>, + <&gcc GCC_NSSNOC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_PPE_CLK>; + clock-names = "crypto_clk", + "crypto_nocclk", + "crypto_ppeclk"; + clock-frequency = /bits/ 64 <600000000 600000000 300000000>; + qcom,dma-mask = <0xff>; + qcom,transform-enabled; + qcom,aes128-cbc; + qcom,aes192-cbc; + qcom,aes256-cbc; + qcom,aes128-ctr; + qcom,aes192-ctr; + qcom,aes256-ctr; + qcom,aes128-ecb; + qcom,aes192-ecb; + qcom,aes256-ecb; + qcom,3des-cbc; + qcom,md5-hash; + qcom,sha160-hash; + qcom,sha224-hash; + qcom,sha384-hash; + qcom,sha512-hash; + qcom,sha256-hash; + qcom,md5-hmac; + qcom,sha160-hmac; + qcom,sha224-hmac; + qcom,sha256-hmac; + qcom,sha384-hmac; + qcom,sha512-hmac; + qcom,aes128-gcm-gmac; + qcom,aes192-gcm-gmac; + qcom,aes256-gcm-gmac; + qcom,aes128-cbc-md5-hmac; + qcom,aes128-cbc-sha160-hmac; + qcom,aes192-cbc-md5-hmac; + qcom,aes192-cbc-sha160-hmac; + qcom,aes256-cbc-md5-hmac; + qcom,aes256-cbc-sha160-hmac; + qcom,aes128-ctr-sha160-hmac; + qcom,aes192-ctr-sha160-hmac; + qcom,aes256-ctr-sha160-hmac; + qcom,aes128-ctr-md5-hmac; + qcom,aes192-ctr-md5-hmac; + qcom,aes256-ctr-md5-hmac; + qcom,3des-cbc-md5-hmac; + qcom,3des-cbc-sha160-hmac; + qcom,aes128-cbc-sha256-hmac; + qcom,aes192-cbc-sha256-hmac; + qcom,aes256-cbc-sha256-hmac; + qcom,aes128-ctr-sha256-hmac; + qcom,aes192-ctr-sha256-hmac; + qcom,aes256-ctr-sha256-hmac; + qcom,3des-cbc-sha256-hmac; + qcom,aes128-cbc-sha384-hmac; + qcom,aes192-cbc-sha384-hmac; + qcom,aes256-cbc-sha384-hmac; + qcom,aes128-ctr-sha384-hmac; + qcom,aes192-ctr-sha384-hmac; + qcom,aes256-ctr-sha384-hmac; + qcom,aes128-cbc-sha512-hmac; + qcom,aes192-cbc-sha512-hmac; + qcom,aes256-cbc-sha512-hmac; + qcom,aes128-ctr-sha512-hmac; + qcom,aes192-ctr-sha512-hmac; + qcom,aes256-ctr-sha512-hmac; + + engine0 { + reg_offset = <0x80000>; + qcom,ifpp-enabled; + qcom,ipue-enabled; + qcom,ofpp-enabled; + qcom,opue-enabled; + }; + }; + }; +}; diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi new file mode 100644 index 000000000..be7b4a972 --- /dev/null +++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0-only + +&CPU0 { + operating-points-v2 = <&cpu_opp_table>; + voltage-tolerance = <1>; + cpu0-supply = <&s3>; +}; + +&CPU1 { + operating-points-v2 = <&cpu_opp_table>; + voltage-tolerance = <1>; + cpu-supply = <&s3>; +}; + +&CPU2 { + operating-points-v2 = <&cpu_opp_table>; + voltage-tolerance = <1>; + cpu-supply = <&s3>; +}; + +&CPU3 { + operating-points-v2 = <&cpu_opp_table>; + voltage-tolerance = <1>; + cpu-supply = <&s3>; +}; + +&cpus { + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-microvolt = <704000>; + clock-latency-ns = <200000>; + }; + opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-microvolt = <784000>; + clock-latency-ns = <200000>; + }; + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-microvolt = <832000>; + clock-latency-ns = <200000>; + }; + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-microvolt = <880000>; + clock-latency-ns = <200000>; + }; + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-microvolt = <904000>; + clock-latency-ns = <200000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <984000>; + clock-latency-ns = <200000>; + }; + }; +}; + +&cpu0_thermal { + trips { + cpu0_passive_low: cpu-passive-low { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_passive_high: cpu-passive-high { + temperature = <100000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_passive_low>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu0_passive_high>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu1_thermal { + trips { + cpu1_passive_low: cpu-passive-low { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_passive_high: cpu-passive-high { + temperature = <100000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_passive_low>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu1_passive_high>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu2_thermal { + trips { + cpu2_passive_low: cpu-passive-low { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_passive_high: cpu-passive-high { + temperature = <100000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_passive_low>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu2_passive_high>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu3_thermal { + trips { + cpu3_passive_low: cpu-passive-low { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_passive_high: cpu-passive-high { + temperature = <100000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_passive_low>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu3_passive_high>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cluster_thermal { + trips { + cluster_passive_low: cluster-passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster_passive_high: cluster-passive-high { + temperature = <100000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster_crit: cluster_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cluster_passive_low>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cluster_passive_high>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-sxr80.dts b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-sxr80.dts new file mode 100644 index 000000000..49cb30758 --- /dev/null +++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-sxr80.dts @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "ipq8074.dtsi" +#include "ipq8074-ac-cpu.dtsi" +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + model = "Netgear SXR80"; + compatible = "netgear,sxr80", "qcom,ipq8074"; + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + led-boot = &led_front_blue; + led-failsafe = &led_front_red; + led-running = &led_front_green; + led-upgrade = &led_front_white; + /* Aliases as required by u-boot to patch MAC addresses */ + ethernet0 = "/soc/dp1"; + ethernet1 = "/soc/dp2"; + ethernet2 = "/soc/dp3"; + ethernet3 = "/soc/dp4"; + ethernet6 = "/soc/dp5"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_front_blue: front-blue { + label = "blue:front"; + gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; + }; + + led_front_green: front-green { + label = "green:front"; + gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + }; + + led_front_red: front-red { + label = "red:front"; + gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; + }; + + led_front_white: front-white { + label = "white:front"; + gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + }; + + led_power_green: power-green { + label = "green:power"; + gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_power_red: power-red { + label = "red:power"; + gpios = <&tlmm 22 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + + }; +}; + +&tlmm { + mdio_pins: mdio-pins { + mdc { + pins = "gpio68"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio { + pins = "gpio69"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + i2c_0_pins: i2c-0-pinmux { + mux { + pins = "gpio42", "gpio43"; + function = "blsp1_i2c"; + drive-strength = <8>; + bias-disable; + }; + }; + + leds_pins: leds_pinmux { + led_power_green { + pins = "gpio21"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + led_power_red { + pins = "gpio22"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + led_white { + pins = "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + led_green { + pins = "gpio29"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + led_red { + pins = "gpio31"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + led_blue { + pins = "gpio33"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + +}; + +&blsp1_uart5 { + status = "okay"; +}; + +&blsp1_i2c2 { + pinctrl-0 = <&i2c_0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + tlc59208f@27 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59108"; + reg = <0x27>; + + led0@0 { + label = "orbi:led0:rgb"; + reg = <0x0>; + linux,default_trigger = "default-on"; + }; + led1@1 { + label = "orbi:led1:rgb"; + reg = <0x1>; + linux,default_trigger = "default-on"; + }; + led2@2 { + label = "orbi:led2:rgb"; + reg = <0x2>; + linux,default_trigger = "default-on"; + }; + led3@3 { + label = "orbi:led3:rgb"; + reg = <0x3>; + linux,default_trigger = "default-on"; + + }; + }; +}; + +&prng { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 25 1>; + + ethernet-phy@0 { + reg = <0>; +// Disabled to resolve multiple configured reset lines causing issues +// reset-gpios = <&tlmm 37 0>; + }; + + ethernet-phy@1 { + reg = <1>; + }; + + ethernet-phy@2 { + reg = <2>; + }; + + ethernet-phy@3 { + reg = <3>; + }; + + ethernet-phy@4 { + reg = <28>; +// Disabled to resolve multiple configured reset lines causing issues +// reset-gpios = <&tlmm 25 1>; + }; + +}; + +&ess_switch { + switch_cpu_bmp = <0x1>; /* cpu port bitmap */ + switch_lan_bmp = <0x3e>; /* lan port bitmap */ + switch_wan_bmp = <0x40>; /* wan port bitmap */ + switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ + switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/ + switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/ + bm_tick_mode = <0>; /* bm tick mode */ + tm_tick_mode = <0>; /* tm tick mode */ + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <0>; + }; + port@1 { + port_id = <2>; + phy_address = <1>; + }; + port@2 { + port_id = <3>; + phy_address = <2>; + }; + port@3 { + port_id = <4>; + phy_address = <3>; + }; + port@5 { + port_id = <6>; + phy_address = <28>; + port_mac_sel = "QGMAC_PORT"; + }; + }; + port_scheduler_resource { + port@0 { + port_id = <0>; + ucast_queue = <0 143>; + mcast_queue = <256 271>; + l0sp = <0 35>; + l0cdrr = <0 47>; + l0edrr = <0 47>; + l1cdrr = <0 7>; + l1edrr = <0 7>; + }; + port@1 { + port_id = <1>; + ucast_queue = <144 159>; + mcast_queue = <272 275>; + l0sp = <36 39>; + l0cdrr = <48 63>; + l0edrr = <48 63>; + l1cdrr = <8 11>; + l1edrr = <8 11>; + }; + port@2 { + port_id = <2>; + ucast_queue = <160 175>; + mcast_queue = <276 279>; + l0sp = <40 43>; + l0cdrr = <64 79>; + l0edrr = <64 79>; + l1cdrr = <12 15>; + l1edrr = <12 15>; + }; + port@3 { + port_id = <3>; + ucast_queue = <176 191>; + mcast_queue = <280 283>; + l0sp = <44 47>; + l0cdrr = <80 95>; + l0edrr = <80 95>; + l1cdrr = <16 19>; + l1edrr = <16 19>; + }; + port@4 { + port_id = <4>; + ucast_queue = <192 207>; + mcast_queue = <284 287>; + l0sp = <48 51>; + l0cdrr = <96 111>; + l0edrr = <96 111>; + l1cdrr = <20 23>; + l1edrr = <20 23>; + }; + port@5 { + port_id = <5>; + ucast_queue = <208 223>; + mcast_queue = <288 291>; + l0sp = <52 55>; + l0cdrr = <112 127>; + l0edrr = <112 127>; + l1cdrr = <24 27>; + l1edrr = <24 27>; + }; + port@6 { + port_id = <6>; + ucast_queue = <224 239>; + mcast_queue = <292 295>; + l0sp = <56 59>; + l0cdrr = <128 143>; + l0edrr = <128 143>; + l1cdrr = <28 31>; + l1edrr = <28 31>; + }; + port@7 { + port_id = <7>; + ucast_queue = <240 255>; + mcast_queue = <296 299>; + l0sp = <60 63>; + l0cdrr = <144 159>; + l0edrr = <144 159>; + l1cdrr = <32 35>; + l1edrr = <32 35>; + }; + }; + port_scheduler_config { + port@0 { + port_id = <0>; + l1scheduler { + group@0 { + sp = <0 1>; /*L0 SPs*/ + /*cpri cdrr epri edrr*/ + cfg = <0 0 0 0>; + }; + }; + l0scheduler { + group@0 { + /*unicast queues*/ + ucast_queue = <0 4 8>; + /*multicast queues*/ + mcast_queue = <256 260>; + /*sp cpri cdrr epri edrr*/ + cfg = <0 0 0 0 0>; + }; + group@1 { + ucast_queue = <1 5 9>; + mcast_queue = <257 261>; + cfg = <0 1 1 1 1>; + }; + group@2 { + ucast_queue = <2 6 10>; + mcast_queue = <258 262>; + cfg = <0 2 2 2 2>; + }; + group@3 { + ucast_queue = <3 7 11>; + mcast_queue = <259 263>; + cfg = <0 3 3 3 3>; + }; + }; + }; + port@1 { + port_id = <1>; + l1scheduler { + group@0 { + sp = <36>; + cfg = <0 8 0 8>; + }; + group@1 { + sp = <37>; + cfg = <1 9 1 9>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <144>; + ucast_loop_pri = <16>; + mcast_queue = <272>; + mcast_loop_pri = <4>; + cfg = <36 0 48 0 48>; + }; + }; + }; + port@2 { + port_id = <2>; + l1scheduler { + group@0 { + sp = <40>; + cfg = <0 12 0 12>; + }; + group@1 { + sp = <41>; + cfg = <1 13 1 13>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <160>; + ucast_loop_pri = <16>; + mcast_queue = <276>; + mcast_loop_pri = <4>; + cfg = <40 0 64 0 64>; + }; + }; + }; + port@3 { + port_id = <3>; + l1scheduler { + group@0 { + sp = <44>; + cfg = <0 16 0 16>; + }; + group@1 { + sp = <45>; + cfg = <1 17 1 17>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <176>; + ucast_loop_pri = <16>; + mcast_queue = <280>; + mcast_loop_pri = <4>; + cfg = <44 0 80 0 80>; + }; + }; + }; + port@4 { + port_id = <4>; + l1scheduler { + group@0 { + sp = <48>; + cfg = <0 20 0 20>; + }; + group@1 { + sp = <49>; + cfg = <1 21 1 21>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <192>; + ucast_loop_pri = <16>; + mcast_queue = <284>; + mcast_loop_pri = <4>; + cfg = <48 0 96 0 96>; + }; + }; + }; + port@5 { + port_id = <5>; + l1scheduler { + group@0 { + sp = <52>; + cfg = <0 24 0 24>; + }; + group@1 { + sp = <53>; + cfg = <1 25 1 25>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <208>; + ucast_loop_pri = <16>; + mcast_queue = <288>; + mcast_loop_pri = <4>; + cfg = <52 0 112 0 112>; + }; + }; + }; + port@6 { + port_id = <6>; + l1scheduler { + group@0 { + sp = <56>; + cfg = <0 28 0 28>; + }; + group@1 { + sp = <57>; + cfg = <1 29 1 29>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <224>; + ucast_loop_pri = <16>; + mcast_queue = <292>; + mcast_loop_pri = <4>; + cfg = <56 0 128 0 128>; + }; + }; + }; + port@7 { + port_id = <7>; + l1scheduler { + group@0 { + sp = <60>; + cfg = <0 32 0 32>; + }; + group@1 { + sp = <61>; + cfg = <1 33 1 33>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <240>; + ucast_loop_pri = <16>; + mcast_queue = <296>; + cfg = <60 0 144 0 144>; + }; + }; + }; + }; +}; + +&soc { + dp1: dp1 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <1>; + reg = <0x3a001000 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <0>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp2: dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <2>; + reg = <0x3a001200 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <1>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp3: dp3 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <3>; + reg = <0x3a001400 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <2>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp4: dp4 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <4>; + reg = <0x3a001600 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <3>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + + dp5: dp5 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <5>; + reg = <0x3a001800 0x200>; + qcom,mactype = <0>; + local-mac-address = [000000000000]; + qcom,link-poll = <1>; + qcom,phy-mdio-addr = <28>; + phy-mode = "sgmii"; + mdio-bus = <&mdio>; + }; + +}; + +&wifi { + status = "okay"; + + qcom,ath11k-calibration-variant = "Netgear-SXR80"; +}; + diff --git a/target/linux/ipq807x/files/drivers/hwmon/emc2305.c b/target/linux/ipq807x/files/drivers/hwmon/emc2305.c new file mode 100644 index 000000000..147900154 --- /dev/null +++ b/target/linux/ipq807x/files/drivers/hwmon/emc2305.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 Sartura Ltd. + * + * Driver for the SMSC/Microchip EMC2301/2/3/5 fan controller. + * + * Author: Robert Marko + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MANUFACTURER_ID_REG 0xfe +#define SMSC_MANUFACTURER_ID 0x5d + +#define PRODUCT_ID_REG 0xfd +#define EMC2305_PRODUCT_ID 0x34 +#define EMC2303_PRODUCT_ID 0x35 +#define EMC2302_PRODUCT_ID 0x36 +#define EMC2301_PRODUCT_ID 0x37 + +#define TACH1_HIGH_BYTE 0x3e +#define TACH1_LOW_BYTE 0x3f + +#define FAN1_CONFIG 0x32 +#define FAN_TACH_RANGE_MASK GENMASK(6, 5) +#define FAN_TACH_MULTIPLIER_8 3 +#define FAN_TACH_MULTIPLIER_4 2 +#define FAN_TACH_MULTIPLIER_2 1 +#define FAN_TACH_MULTIPLIER_1 0 +#define FAN_TACH_CONSTANT 3932160 +#define FAN_TACH_READING_MASK GENMASK(15,3) + +#define TACH1_TARGET_LOW_BYTE 0x3c +#define TACH1_TARGET_HIGH_BYTE 0x3d +#define TACH_HIGH_MASK GENMASK(12,5) +#define TACH_LOW_MASK GENMASK(4,0) + +#define FANX_OFFSET 0x10 +#define FAN_NUM_MAX 5 + +struct emc2305_fan_data { + u32 min_rpm; + u32 max_rpm; + u32 target_rpm; +}; + +struct emc2305_data { + struct regmap *regmap; + struct i2c_client *client; + struct emc2305_fan_data fan_data[FAN_NUM_MAX]; +}; + +static struct regmap_config emc2305_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff, +}; + +static int emc2305_read_fan(struct emc2305_data *data, int channel, + long *val) +{ + unsigned int regval, high_byte, low_byte; + u8 range, multiplier; + int ret; + + ret = regmap_read(data->regmap, + FAN1_CONFIG + channel * FANX_OFFSET, + ®val); + if (ret < 0) + return ret; + + range = FIELD_GET(FAN_TACH_RANGE_MASK, regval); + + switch (range) { + case FAN_TACH_MULTIPLIER_8: + multiplier = 8; + break; + case FAN_TACH_MULTIPLIER_4: + multiplier = 4; + break; + case FAN_TACH_MULTIPLIER_2: + multiplier = 2; + break; + case FAN_TACH_MULTIPLIER_1: + multiplier = 1; + break; + default: + return -EINVAL; + } + + ret = regmap_read(data->regmap, + TACH1_HIGH_BYTE + channel * FANX_OFFSET, + &high_byte); + if (ret < 0) + return ret; + + ret = regmap_read(data->regmap, + TACH1_LOW_BYTE + channel * FANX_OFFSET, + &low_byte); + if (ret < 0) + return ret; + + regval = (u8) high_byte << 8 | (u8) low_byte; + + *val = (FAN_TACH_CONSTANT * multiplier) / FIELD_GET(FAN_TACH_READING_MASK, regval); + + return 0; +} + +static int emc2305_read_fan_target(struct emc2305_data *data, int channel, + long *val) +{ + unsigned int regval; + int ret; + + ret = regmap_bulk_read(data->regmap, + TACH1_TARGET_LOW_BYTE + channel * FANX_OFFSET, + ®val, + 2); + if (ret < 0) + return ret; + + *val = regval; + + return 0; +} + +static int emc2305_set_fan_target(struct emc2305_data *data, int channel, + long val) +{ + int ret; + + ret = regmap_write(data->regmap, + TACH1_TARGET_LOW_BYTE + channel * FANX_OFFSET, + val & TACH_LOW_MASK); + if (ret < 0) + return ret; + + ret = regmap_write(data->regmap, + TACH1_TARGET_HIGH_BYTE + channel * FANX_OFFSET, + (val & TACH_HIGH_MASK) >> 5); + if (ret < 0) + return ret; + + return 0; +} + +static int emc2305_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct emc2305_data *data = dev_get_drvdata(dev); + int err; + + switch (type) { + case hwmon_fan: + switch (attr) { + case hwmon_fan_target: + err = emc2305_set_fan_target(data, channel, val); + break; + default: + return -EOPNOTSUPP; + } + break; + default: + return -EOPNOTSUPP; + } + + return err; +} + +static int emc2305_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct emc2305_data *data = dev_get_drvdata(dev); + int err; + + switch (type) { + case hwmon_fan: + switch (attr) { + case hwmon_fan_input: + err = emc2305_read_fan(data, channel, val); + break; + case hwmon_fan_target: + err = emc2305_read_fan_target(data, channel, val); + break; + default: + return -EOPNOTSUPP; + } + break; + default: + return -EOPNOTSUPP; + } + + return err; +} + +static const char * const emc2305_fan_label[] = { + "Fan1", + "Fan2", + "Fan3", + "Fan4", + "Fan5", +}; + +static int emc2305_read_string(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + switch (type) { + case hwmon_fan: + *str = emc2305_fan_label[channel]; + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static umode_t emc2305_is_visible(const void *data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_fan: + switch (attr) { + case hwmon_fan_input: + case hwmon_fan_label: + return 0444; + case hwmon_fan_target: + return 0644; + default: + return 0; + } + default: + return 0; + } +} + +static const struct hwmon_channel_info *emc2301_info[] = { + HWMON_CHANNEL_INFO(fan, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL), + NULL +}; + +static const struct hwmon_channel_info *emc2302_info[] = { + HWMON_CHANNEL_INFO(fan, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL), + NULL +}; + +static const struct hwmon_channel_info *emc2303_info[] = { + HWMON_CHANNEL_INFO(fan, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL), + NULL +}; + +static const struct hwmon_channel_info *emc2305_info[] = { + HWMON_CHANNEL_INFO(fan, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL, + HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL), + NULL +}; + +static const struct hwmon_ops emc2305_hwmon_ops = { + .is_visible = emc2305_is_visible, + .write = emc2305_write, + .read = emc2305_read, + .read_string = emc2305_read_string, +}; + +static struct hwmon_chip_info emc2305_chip_info = { + .ops = &emc2305_hwmon_ops, +}; + +static int emc2305_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct emc2305_data *data; + struct device *hwmon_dev; + const char *model_name; + unsigned int regval; + int ret; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client = client; + i2c_set_clientdata(client, data); + + data->regmap = devm_regmap_init_i2c(client, &emc2305_regmap_config); + if (IS_ERR(data->regmap)) { + dev_err(dev, "failed to allocate register map\n"); + return PTR_ERR(data->regmap); + } + + ret = regmap_read(data->regmap, MANUFACTURER_ID_REG, ®val); + if (ret < 0) + return ret; + + if (regval != SMSC_MANUFACTURER_ID) { + dev_err(dev, "Invalid manufacturer id: 0x%x\n", regval); + return -ENODEV; + } + + ret = regmap_read(data->regmap, PRODUCT_ID_REG, ®val); + if (ret < 0) + return ret; + + switch (regval) { + case EMC2305_PRODUCT_ID: + model_name = "emc2305"; + emc2305_chip_info.info = emc2305_info; + break; + case EMC2303_PRODUCT_ID: + model_name = "emc2303"; + emc2305_chip_info.info = emc2303_info; + break; + case EMC2302_PRODUCT_ID: + model_name = "emc2302"; + emc2305_chip_info.info = emc2302_info; + break; + case EMC2301_PRODUCT_ID: + model_name = "emc2301"; + emc2305_chip_info.info = emc2301_info; + break; + default: + dev_err(dev, "Unknown ID detected: 0x%x\n", regval); + return -ENODEV; + } + + dev_info(dev, "%s detected\n", model_name); + + hwmon_dev = devm_hwmon_device_register_with_info(dev, model_name, + data, &emc2305_chip_info, + NULL); + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + + return 0; +} + +static const struct of_device_id emc2305_of_match[] = { + { .compatible = "smsc,emc2301", }, + { .compatible = "smsc,emc2302", }, + { .compatible = "smsc,emc2303", }, + { .compatible = "smsc,emc2305", }, + { }, +}; +MODULE_DEVICE_TABLE(of, emc2305_of_match); + +static struct i2c_driver emc2305_driver = { + .probe_new = emc2305_probe, + .driver = { + .name = "emc2305", + .of_match_table = of_match_ptr(emc2305_of_match), + }, +}; +module_i2c_driver(emc2305_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Robert Marko "); +MODULE_DESCRIPTION("SMSC EMC2301/2/3/5 fan controller"); diff --git a/target/linux/ipq807x/image/Makefile b/target/linux/ipq807x/image/Makefile index d7bb5ff1f..4b0a657c0 100644 --- a/target/linux/ipq807x/image/Makefile +++ b/target/linux/ipq807x/image/Makefile @@ -3,46 +3,16 @@ include $(INCLUDE_DIR)/image.mk define Device/Default PROFILES := Default - KERNEL_DEPENDS = $$(wildcard $(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dts) - KERNEL_INITRAMFS_PREFIX := $$(IMG_PREFIX)-$(1)-initramfs - KERNEL_PREFIX := $$(IMAGE_PREFIX) - KERNEL_LOADADDR := 0x41080000 - DEVICE_DTS_DIR := $(DTS_DIR)/qcom + KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts) + KERNEL_LOADADDR := 0x41000000 DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1))) - SUPPORTED_DEVICES := $(subst _,$(comma),$(1)) + DEVICE_DTS_CONFIG := config@1 + DEVICE_DTS_DIR := $(DTS_DIR)/qcom + IMAGES := sysupgrade.bin IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata IMAGE/sysupgrade.bin/squashfs := endef -define Device/FitImage - KERNEL_SUFFIX := -fit-uImage.itb - KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb - KERNEL_NAME := Image -endef - -define Device/FitImageLzma - KERNEL_SUFFIX := -fit-uImage.itb - KERNEL = kernel-bin | lzma | fit lzma $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb - KERNEL_NAME := Image -endef - -define Device/UbiFit - KERNEL_IN_UBI := 1 - IMAGES := nand-factory.ubi nand-sysupgrade.bin - IMAGE/nand-factory.ubi := append-ubi - IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata -endef - -define Device/xiaomi_ax3600 - $(call Device/FitImage) - $(call Device/UbiFit) - DEVICE_VENDOR := Xiaomi - DEVICE_MODEL := Mi AIoT Router AX3600 - BLOCKSIZE := 128k - PAGESIZE := 2048 - DEVICE_DTS_CONFIG := config@ac04 - SOC := ipq8071 -endef -TARGET_DEVICES += xiaomi_ax3600 +include $(SUBTARGET).mk $(eval $(call BuildImage)) diff --git a/target/linux/ipq807x/image/generic.mk b/target/linux/ipq807x/image/generic.mk new file mode 100644 index 000000000..2ca5af78a --- /dev/null +++ b/target/linux/ipq807x/image/generic.mk @@ -0,0 +1,73 @@ +define Device/FitImage + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := Image +endef + +define Device/FitImageLzma + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | lzma | fit lzma $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := Image +endef + +define Device/FitzImage + KERNEL_SUFFIX := -fit-zImage.itb + KERNEL = kernel-bin | fit none $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := zImage +endef + +define Device/UbiFit + KERNEL_IN_UBI := 1 + IMAGES := nand-factory.ubi nand-sysupgrade.bin + IMAGE/nand-factory.ubi := append-ubi + IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata +endef + +define Device/netgear_sxr80 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Netgear + DEVICE_MODEL := SXR80 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_DTS_CONFIG := config@hk01 + SOC := ipq8074 + DEVICE_PACKAGES := ipq-wifi-netgear_sxr80 uboot-envtools +endef +TARGET_DEVICES += netgear_sxr80 + +define Device/redmi_ax6 + $(call Device/xiaomi_ax3600) + DEVICE_VENDOR := Redmi + DEVICE_MODEL := AX6 + DEVICE_PACKAGES := ipq-wifi-redmi_ax6 uboot-envtools +endef +TARGET_DEVICES += redmi_ax6 + +define Device/xiaomi_ax3600 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := AX3600 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_DTS_CONFIG := config@ac04 + SOC := ipq8071 + DEVICE_PACKAGES := ipq-wifi-xiaomi_ax3600 kmod-ath10k-ct ath10k-firmware-qca9887-ct \ + uboot-envtools +endef +TARGET_DEVICES += xiaomi_ax3600 + +define Device/xiaomi_ax9000 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := AX9000 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_DTS_CONFIG := config@hk14 + SOC := ipq8072 + DEVICE_PACKAGES := ipq-wifi-xiaomi_ax9000 kmod-ath10k-ct ath10k-firmware-qca9887-ct \ + uboot-envtools +endef +TARGET_DEVICES += xiaomi_ax9000 diff --git a/target/linux/ipq807x/patches-5.10/001-v5.11-remoteproc-sysmon-Expose-the-shutdown-result.patch b/target/linux/ipq807x/patches-5.10/001-v5.11-remoteproc-sysmon-Expose-the-shutdown-result.patch new file mode 100644 index 000000000..57d2cbf6e --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/001-v5.11-remoteproc-sysmon-Expose-the-shutdown-result.patch @@ -0,0 +1,222 @@ +From c47b1e60f043925ecce585f8c5340c049deda25e Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Sat, 21 Nov 2020 21:41:33 -0800 +Subject: [PATCH] remoteproc: sysmon: Expose the shutdown result + +A graceful shutdown of the Qualcomm remote processors where +traditionally performed by invoking a shared memory state signal and +waiting for the associated ack. + +This was later superseded by the "sysmon" mechanism, where some form of +shared memory bus is used to send a "graceful shutdown request" message +and one of more signals comes back to indicate its success. + +But when this newer mechanism is in effect the firmware is shut down by +the time the older mechanism, implemented in the remoteproc drivers, +attempts to perform a graceful shutdown - and as such it will never +receive an ack back. + +This patch therefor track the success of the latest shutdown attempt in +sysmon and exposes a new function in the API that the remoteproc driver +can use to query the success and the necessity of invoking the older +mechanism. + +Tested-by: Steev Klimaszewski +Reviewed-by: Rishabh Bhatnagar +Link: https://lore.kernel.org/r/20201122054135.802935-3-bjorn.andersson@linaro.org +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/qcom_common.h | 6 +++ + drivers/remoteproc/qcom_sysmon.c | 82 ++++++++++++++++++++++++-------- + 2 files changed, 69 insertions(+), 19 deletions(-) + +--- a/drivers/remoteproc/qcom_common.h ++++ b/drivers/remoteproc/qcom_common.h +@@ -51,6 +51,7 @@ struct qcom_sysmon *qcom_add_sysmon_subd + const char *name, + int ssctl_instance); + void qcom_remove_sysmon_subdev(struct qcom_sysmon *sysmon); ++bool qcom_sysmon_shutdown_acked(struct qcom_sysmon *sysmon); + #else + static inline struct qcom_sysmon *qcom_add_sysmon_subdev(struct rproc *rproc, + const char *name, +@@ -62,6 +63,11 @@ static inline struct qcom_sysmon *qcom_a + static inline void qcom_remove_sysmon_subdev(struct qcom_sysmon *sysmon) + { + } ++ ++static inline bool qcom_sysmon_shutdown_acked(struct qcom_sysmon *sysmon) ++{ ++ return false; ++} + #endif + + #endif +--- a/drivers/remoteproc/qcom_sysmon.c ++++ b/drivers/remoteproc/qcom_sysmon.c +@@ -44,6 +44,7 @@ struct qcom_sysmon { + struct mutex lock; + + bool ssr_ack; ++ bool shutdown_acked; + + struct qmi_handle qmi; + struct sockaddr_qrtr ssctl; +@@ -115,10 +116,13 @@ out_unlock: + /** + * sysmon_request_shutdown() - request graceful shutdown of remote + * @sysmon: sysmon context ++ * ++ * Return: boolean indicator of the remote processor acking the request + */ +-static void sysmon_request_shutdown(struct qcom_sysmon *sysmon) ++static bool sysmon_request_shutdown(struct qcom_sysmon *sysmon) + { + char *req = "ssr:shutdown"; ++ bool acked = false; + int ret; + + mutex_lock(&sysmon->lock); +@@ -141,9 +145,13 @@ static void sysmon_request_shutdown(stru + if (!sysmon->ssr_ack) + dev_err(sysmon->dev, + "unexpected response to sysmon shutdown request\n"); ++ else ++ acked = true; + + out_unlock: + mutex_unlock(&sysmon->lock); ++ ++ return acked; + } + + static int sysmon_callback(struct rpmsg_device *rpdev, void *data, int count, +@@ -297,14 +305,33 @@ static struct qmi_msg_handler qmi_indica + {} + }; + ++static bool ssctl_request_shutdown_wait(struct qcom_sysmon *sysmon) ++{ ++ int ret; ++ ++ ret = wait_for_completion_timeout(&sysmon->shutdown_comp, 10 * HZ); ++ if (ret) ++ return true; ++ ++ ret = try_wait_for_completion(&sysmon->ind_comp); ++ if (ret) ++ return true; ++ ++ dev_err(sysmon->dev, "timeout waiting for shutdown ack\n"); ++ return false; ++} ++ + /** + * ssctl_request_shutdown() - request shutdown via SSCTL QMI service + * @sysmon: sysmon context ++ * ++ * Return: boolean indicator of the remote processor acking the request + */ +-static void ssctl_request_shutdown(struct qcom_sysmon *sysmon) ++static bool ssctl_request_shutdown(struct qcom_sysmon *sysmon) + { + struct ssctl_shutdown_resp resp; + struct qmi_txn txn; ++ bool acked = false; + int ret; + + reinit_completion(&sysmon->ind_comp); +@@ -312,7 +339,7 @@ static void ssctl_request_shutdown(struc + ret = qmi_txn_init(&sysmon->qmi, &txn, ssctl_shutdown_resp_ei, &resp); + if (ret < 0) { + dev_err(sysmon->dev, "failed to allocate QMI txn\n"); +- return; ++ return false; + } + + ret = qmi_send_request(&sysmon->qmi, &sysmon->ssctl, &txn, +@@ -320,27 +347,23 @@ static void ssctl_request_shutdown(struc + if (ret < 0) { + dev_err(sysmon->dev, "failed to send shutdown request\n"); + qmi_txn_cancel(&txn); +- return; ++ return false; + } + + ret = qmi_txn_wait(&txn, 5 * HZ); +- if (ret < 0) ++ if (ret < 0) { + dev_err(sysmon->dev, "failed receiving QMI response\n"); +- else if (resp.resp.result) ++ } else if (resp.resp.result) { + dev_err(sysmon->dev, "shutdown request failed\n"); +- else ++ } else { + dev_dbg(sysmon->dev, "shutdown request completed\n"); +- +- if (sysmon->shutdown_irq > 0) { +- ret = wait_for_completion_timeout(&sysmon->shutdown_comp, +- 10 * HZ); +- if (!ret) { +- ret = try_wait_for_completion(&sysmon->ind_comp); +- if (!ret) +- dev_err(sysmon->dev, +- "timeout waiting for shutdown ack\n"); +- } ++ acked = true; + } ++ ++ if (sysmon->shutdown_irq > 0) ++ return ssctl_request_shutdown_wait(sysmon); ++ ++ return acked; + } + + /** +@@ -510,6 +533,9 @@ static void sysmon_stop(struct rproc_sub + .subsys_name = sysmon->name, + .ssr_event = SSCTL_SSR_EVENT_BEFORE_SHUTDOWN + }; ++ bool acked; ++ ++ sysmon->shutdown_acked = false; + + mutex_lock(&sysmon->state_lock); + sysmon->state = SSCTL_SSR_EVENT_BEFORE_SHUTDOWN; +@@ -521,9 +547,11 @@ static void sysmon_stop(struct rproc_sub + return; + + if (sysmon->ssctl_version) +- ssctl_request_shutdown(sysmon); ++ acked = ssctl_request_shutdown(sysmon); + else if (sysmon->ept) +- sysmon_request_shutdown(sysmon); ++ acked = sysmon_request_shutdown(sysmon); ++ ++ sysmon->shutdown_acked = acked; + } + + static void sysmon_unprepare(struct rproc_subdev *subdev) +@@ -682,6 +710,22 @@ void qcom_remove_sysmon_subdev(struct qc + EXPORT_SYMBOL_GPL(qcom_remove_sysmon_subdev); + + /** ++ * qcom_sysmon_shutdown_acked() - query the success of the last shutdown ++ * @sysmon: sysmon context ++ * ++ * When sysmon is used to request a graceful shutdown of the remote processor ++ * this can be used by the remoteproc driver to query the success, in order to ++ * know if it should fall back to other means of requesting a shutdown. ++ * ++ * Return: boolean indicator of the success of the last shutdown request ++ */ ++bool qcom_sysmon_shutdown_acked(struct qcom_sysmon *sysmon) ++{ ++ return sysmon && sysmon->shutdown_acked; ++} ++EXPORT_SYMBOL_GPL(qcom_sysmon_shutdown_acked); ++ ++/** + * sysmon_probe() - probe sys_mon channel + * @rpdev: rpmsg device handle + * diff --git a/target/linux/ipq807x/patches-5.10/002-v5.11-remoteproc-qcom-q6v5-Query-sysmon-before-graceful-sh.patch b/target/linux/ipq807x/patches-5.10/002-v5.11-remoteproc-qcom-q6v5-Query-sysmon-before-graceful-sh.patch new file mode 100644 index 000000000..aeb0e1b7b --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/002-v5.11-remoteproc-qcom-q6v5-Query-sysmon-before-graceful-sh.patch @@ -0,0 +1,120 @@ +From 47c815630294b6d2284fff10377d808f376de2b2 Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Sat, 21 Nov 2020 21:41:34 -0800 +Subject: [PATCH 01/16] remoteproc: qcom: q6v5: Query sysmon before graceful + shutdown + +Requesting a graceful shutdown through the shared memory state signals +will not be acked in the event that sysmon has already successfully shut +down the remote firmware. So extend the stop request API to optionally +take the remoteproc's sysmon instance and query if there's already been +a successful shutdown attempt, before doing the signal dance. + +Tested-by: Steev Klimaszewski +Reviewed-by: Rishabh Bhatnagar +Link: https://lore.kernel.org/r/20201122054135.802935-4-bjorn.andersson@linaro.org +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/qcom_q6v5.c | 8 +++++++- + drivers/remoteproc/qcom_q6v5.h | 3 ++- + drivers/remoteproc/qcom_q6v5_adsp.c | 2 +- + drivers/remoteproc/qcom_q6v5_mss.c | 2 +- + drivers/remoteproc/qcom_q6v5_pas.c | 2 +- + drivers/remoteproc/qcom_q6v5_wcss.c | 2 +- + 6 files changed, 13 insertions(+), 6 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5.c ++++ b/drivers/remoteproc/qcom_q6v5.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include "qcom_common.h" + #include "qcom_q6v5.h" + + #define Q6V5_PANIC_DELAY_MS 200 +@@ -146,15 +147,20 @@ static irqreturn_t q6v5_stop_interrupt(i + /** + * qcom_q6v5_request_stop() - request the remote processor to stop + * @q6v5: reference to qcom_q6v5 context ++ * @sysmon: reference to the remote's sysmon instance, or NULL + * + * Return: 0 on success, negative errno on failure + */ +-int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5) ++int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon) + { + int ret; + + q6v5->running = false; + ++ /* Don't perform SMP2P dance if sysmon already shut down the remote */ ++ if (qcom_sysmon_shutdown_acked(sysmon)) ++ return 0; ++ + qcom_smem_state_update_bits(q6v5->state, + BIT(q6v5->stop_bit), BIT(q6v5->stop_bit)); + +--- a/drivers/remoteproc/qcom_q6v5.h ++++ b/drivers/remoteproc/qcom_q6v5.h +@@ -8,6 +8,7 @@ + + struct rproc; + struct qcom_smem_state; ++struct qcom_sysmon; + + struct qcom_q6v5 { + struct device *dev; +@@ -40,7 +41,7 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v + + int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5); + int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5); +-int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5); ++int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon); + int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout); + unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5); + +--- a/drivers/remoteproc/qcom_q6v5_adsp.c ++++ b/drivers/remoteproc/qcom_q6v5_adsp.c +@@ -266,7 +266,7 @@ static int adsp_stop(struct rproc *rproc + int handover; + int ret; + +- ret = qcom_q6v5_request_stop(&adsp->q6v5); ++ ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon); + if (ret == -ETIMEDOUT) + dev_err(adsp->dev, "timed out on wait\n"); + +--- a/drivers/remoteproc/qcom_q6v5_mss.c ++++ b/drivers/remoteproc/qcom_q6v5_mss.c +@@ -1376,7 +1376,7 @@ static int q6v5_stop(struct rproc *rproc + struct q6v5 *qproc = (struct q6v5 *)rproc->priv; + int ret; + +- ret = qcom_q6v5_request_stop(&qproc->q6v5); ++ ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon); + if (ret == -ETIMEDOUT) + dev_err(qproc->dev, "timed out on wait\n"); + +--- a/drivers/remoteproc/qcom_q6v5_pas.c ++++ b/drivers/remoteproc/qcom_q6v5_pas.c +@@ -217,7 +217,7 @@ static int adsp_stop(struct rproc *rproc + int handover; + int ret; + +- ret = qcom_q6v5_request_stop(&adsp->q6v5); ++ ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon); + if (ret == -ETIMEDOUT) + dev_err(adsp->dev, "timed out on wait\n"); + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -390,7 +390,7 @@ static int q6v5_wcss_stop(struct rproc * + int ret; + + /* WCSS powerdown */ +- ret = qcom_q6v5_request_stop(&wcss->q6v5); ++ ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); + if (ret == -ETIMEDOUT) { + dev_err(wcss->dev, "timed out on wait\n"); + return ret; diff --git a/target/linux/ipq807x/patches-5.4/106-01-remoteproc-qcom-wcss-populate-hardcoded-param-using-driver-data.patch b/target/linux/ipq807x/patches-5.10/003-v5.13-remoteproc-qcom-wcss-populate-hardcoded-param-using-.patch similarity index 51% rename from target/linux/ipq807x/patches-5.4/106-01-remoteproc-qcom-wcss-populate-hardcoded-param-using-driver-data.patch rename to target/linux/ipq807x/patches-5.10/003-v5.13-remoteproc-qcom-wcss-populate-hardcoded-param-using-.patch index 4e028f450..b7f9bd425 100644 --- a/target/linux/ipq807x/patches-5.4/106-01-remoteproc-qcom-wcss-populate-hardcoded-param-using-driver-data.patch +++ b/target/linux/ipq807x/patches-5.10/003-v5.13-remoteproc-qcom-wcss-populate-hardcoded-param-using-.patch @@ -1,58 +1,8 @@ -From patchwork Thu Jul 30 12:14:01 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692903 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D0FF717CA - for ; - Thu, 30 Jul 2020 12:14:32 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by mail.kernel.org (Postfix) with ESMTP id C220E20838 - for ; - Thu, 30 Jul 2020 12:14:32 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1726781AbgG3MOc (ORCPT - ); - Thu, 30 Jul 2020 08:14:32 -0400 -Received: from alexa-out.qualcomm.com ([129.46.98.28]:15938 "EHLO - alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1726967AbgG3MOb (ORCPT - ); - Thu, 30 Jul 2020 08:14:31 -0400 -Received: from ironmsg07-lv.qualcomm.com (HELO ironmsg07-lv.qulacomm.com) - ([10.47.202.151]) - by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:14:31 -0700 -Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) - by ironmsg07-lv.qulacomm.com with ESMTP/TLS/AES256-SHA; - 30 Jul 2020 05:14:29 -0700 -Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) - by ironmsg01-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:44:06 +0530 -Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) - id 20D2D213B6; Thu, 30 Jul 2020 17:44:04 +0530 (IST) -From: Gokul Sriram Palanisamy -To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, - sboyd@kernel.org, linux-clk@vger.kernel.org, - linux-arm-msm@vger.kernel.org -Cc: agross@kernel.org, linux-soc@vger.kernel.org, - devicetree@vger.kernel.org, govinds@codeaurora.org, - sricharan@codeaurora.org, gokulsri@codeaurora.org -Subject: [PATCH v8 1/4] remoteproc: qcom: wcss: populate hardcoded param using - driver data -Date: Thu, 30 Jul 2020 17:44:01 +0530 -Message-Id: <1596111244-28411-2-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> -References: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org - +From 6a83f257a5a10b24c7311475f19d58399c475476 Mon Sep 17 00:00:00 2001 From: Govind Singh +Date: Fri, 29 Jan 2021 00:18:12 +0530 +Subject: [PATCH 02/16] remoteproc: qcom: wcss: populate hardcoded param using + driver data Q6 based WiFi fw loading is supported across different targets, ex: IPQ8074/QCS404. In order to @@ -61,6 +11,8 @@ hardcoded param using driver data. Signed-off-by: Govind Singh Signed-off-by: Gokul Sriram Palanisamy +Link: https://lore.kernel.org/r/1611859695-11824-2-git-send-email-gokulsri@codeaurora.org +Signed-off-by: Bjorn Andersson --- drivers/remoteproc/qcom_q6v5_wcss.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/target/linux/ipq807x/patches-5.4/106-02-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for-QCS404.patch b/target/linux/ipq807x/patches-5.10/004-v5.13-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for.patch similarity index 86% rename from target/linux/ipq807x/patches-5.4/106-02-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for-QCS404.patch rename to target/linux/ipq807x/patches-5.10/004-v5.13-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for.patch index 12fee4070..00b9cec66 100644 --- a/target/linux/ipq807x/patches-5.4/106-02-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for-QCS404.patch +++ b/target/linux/ipq807x/patches-5.10/004-v5.13-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for.patch @@ -1,57 +1,8 @@ -From patchwork Thu Jul 30 12:14:03 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692923 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F13D81746 - for ; - Thu, 30 Jul 2020 12:14:40 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by mail.kernel.org (Postfix) with ESMTP id DA5CA22BEA - for ; - Thu, 30 Jul 2020 12:14:40 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1726967AbgG3MOk (ORCPT - ); - Thu, 30 Jul 2020 08:14:40 -0400 -Received: from alexa-out.qualcomm.com ([129.46.98.28]:22096 "EHLO - alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1727837AbgG3MOj (ORCPT - ); - Thu, 30 Jul 2020 08:14:39 -0400 -Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) - by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:14:34 -0700 -Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) - by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; - 30 Jul 2020 05:14:31 -0700 -Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) - by ironmsg01-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:44:06 +0530 -Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) - id 5CF85218A5; Thu, 30 Jul 2020 17:44:04 +0530 (IST) -From: Gokul Sriram Palanisamy -To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, - sboyd@kernel.org, linux-clk@vger.kernel.org, - linux-arm-msm@vger.kernel.org -Cc: agross@kernel.org, linux-soc@vger.kernel.org, - devicetree@vger.kernel.org, govinds@codeaurora.org, - sricharan@codeaurora.org, gokulsri@codeaurora.org -Subject: [PATCH v8 3/4] remoteproc: qcom: wcss: Add non pas wcss Q6 support - for QCS404 -Date: Thu, 30 Jul 2020 17:44:03 +0530 -Message-Id: <1596111244-28411-4-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> -References: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org - +From 155940892f022482c7e7a33c917fd766519d031b Mon Sep 17 00:00:00 2001 From: Govind Singh +Date: Fri, 29 Jan 2021 00:18:14 +0530 +Subject: [PATCH 03/16] remoteproc: qcom: wcss: Add non pas wcss Q6 support for + QCS404 Add non PAS WCSS remoteproc driver support for QCS404 SOC. Add WCSS q6 bootup and shutdown sequence handled from @@ -59,9 +10,11 @@ Application Processor SubSystem(APSS). Signed-off-by: Govind Singh Signed-off-by: Gokul Sriram Palanisamy +Link: https://lore.kernel.org/r/1611859695-11824-4-git-send-email-gokulsri@codeaurora.org +Signed-off-by: Bjorn Andersson --- - drivers/remoteproc/qcom_q6v5_wcss.c | 564 +++++++++++++++++++++++++++++++++--- - 1 file changed, 526 insertions(+), 38 deletions(-) + drivers/remoteproc/qcom_q6v5_wcss.c | 566 ++++++++++++++++++++++++++-- + 1 file changed, 528 insertions(+), 38 deletions(-) --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -465,12 +418,12 @@ Signed-off-by: Gokul Sriram Palanisamy int ret; /* WCSS powerdown */ -- ret = qcom_q6v5_request_stop(&wcss->q6v5); +- ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); - if (ret == -ETIMEDOUT) { - dev_err(wcss->dev, "timed out on wait\n"); - return ret; + if (wcss->requires_force_stop) { -+ ret = qcom_q6v5_request_stop(&wcss->q6v5); ++ ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); + if (ret == -ETIMEDOUT) { + dev_err(wcss->dev, "timed out on wait\n"); + return ret; @@ -768,17 +721,19 @@ Signed-off-by: Gokul Sriram Palanisamy if (ret) goto free_rproc; -@@ -584,6 +1051,9 @@ static int q6v5_wcss_probe(struct platfo - - qcom_add_glink_subdev(rproc, &wcss->glink_subdev); +@@ -585,6 +1052,11 @@ static int q6v5_wcss_probe(struct platfo + qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss"); qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); -+ wcss->sysmon = qcom_add_sysmon_subdev(rproc, -+ desc->sysmon_name, -+ desc->ssctl_id); ++ if (desc->ssctl_id) ++ wcss->sysmon = qcom_add_sysmon_subdev(rproc, ++ desc->sysmon_name, ++ desc->ssctl_id); ++ ret = rproc_add(rproc); if (ret) -@@ -612,10 +1082,28 @@ static int q6v5_wcss_remove(struct platf + goto free_rproc; +@@ -612,10 +1084,28 @@ static int q6v5_wcss_remove(struct platf static const struct wcss_data wcss_ipq8074_res_init = { .firmware_name = "IPQ8074/q6_fw.mdt", .crash_reason_smem = WCSS_CRASH_REASON, diff --git a/target/linux/ipq807x/patches-5.10/005-v5.13-remoteproc-qcom-wcss-explicitly-request-exclusive-re.patch b/target/linux/ipq807x/patches-5.10/005-v5.13-remoteproc-qcom-wcss-explicitly-request-exclusive-re.patch new file mode 100644 index 000000000..3b09a6dd2 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/005-v5.13-remoteproc-qcom-wcss-explicitly-request-exclusive-re.patch @@ -0,0 +1,43 @@ +From 7b230496f6b45e840bc7b13e7df2a8676bab9230 Mon Sep 17 00:00:00 2001 +From: Govind Singh +Date: Fri, 29 Jan 2021 00:18:15 +0530 +Subject: [PATCH 04/16] remoteproc: qcom: wcss: explicitly request exclusive + reset control + +Use request exclusive reset control for wcss reset controls. + +Signed-off-by: Govind Singh +Signed-off-by: Gokul Sriram Palanisamy +Link: https://lore.kernel.org/r/1611859695-11824-5-git-send-email-gokulsri@codeaurora.org +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -788,21 +788,21 @@ static int q6v5_wcss_init_reset(struct q + struct device *dev = wcss->dev; + + if (desc->aon_reset_required) { +- wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset"); ++ wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset"); + if (IS_ERR(wcss->wcss_aon_reset)) { + dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n"); + return PTR_ERR(wcss->wcss_aon_reset); + } + } + +- wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset"); ++ wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset"); + if (IS_ERR(wcss->wcss_reset)) { + dev_err(wcss->dev, "unable to acquire wcss_reset\n"); + return PTR_ERR(wcss->wcss_reset); + } + + if (desc->wcss_q6_reset_required) { +- wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset"); ++ wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset"); + if (IS_ERR(wcss->wcss_q6_reset)) { + dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); + return PTR_ERR(wcss->wcss_q6_reset); diff --git a/target/linux/ipq807x/patches-5.10/006-v5.13-remoteproc-qcom-wcss-Fix-return-value-check-in-q6v5_.patch b/target/linux/ipq807x/patches-5.10/006-v5.13-remoteproc-qcom-wcss-Fix-return-value-check-in-q6v5_.patch new file mode 100644 index 000000000..fe5e33c23 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/006-v5.13-remoteproc-qcom-wcss-Fix-return-value-check-in-q6v5_.patch @@ -0,0 +1,32 @@ +From 5b8b0967576f04d2ee3ea36310c078a3d50e7339 Mon Sep 17 00:00:00 2001 +From: Wei Yongjun +Date: Fri, 19 Mar 2021 09:41:00 +0000 +Subject: [PATCH 05/16] remoteproc: qcom: wcss: Fix return value check in + q6v5_wcss_init_mmio() + +In case of error, the function devm_ioremap() returns NULL pointer +not ERR_PTR(). The IS_ERR() test in the return value check should +be replaced with NULL test. + +Fixes: 0af65b9b915e ("remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404") +Reported-by: Hulk Robot +Signed-off-by: Wei Yongjun +Link: https://lore.kernel.org/r/20210319094100.4185044-1-weiyongjun1@huawei.com +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -829,8 +829,8 @@ static int q6v5_wcss_init_mmio(struct q6 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); + wcss->reg_base = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); +- if (IS_ERR(wcss->reg_base)) +- return PTR_ERR(wcss->reg_base); ++ if (!wcss->reg_base) ++ return -ENOMEM; + + if (wcss->version == WCSS_IPQ8074) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); diff --git a/target/linux/ipq807x/patches-5.10/007-v5.13-remoteproc-qcom-wcss-Fix-wrong-pointer-passed-to-PTR.patch b/target/linux/ipq807x/patches-5.10/007-v5.13-remoteproc-qcom-wcss-Fix-wrong-pointer-passed-to-PTR.patch new file mode 100644 index 000000000..65676cf11 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/007-v5.13-remoteproc-qcom-wcss-Fix-wrong-pointer-passed-to-PTR.patch @@ -0,0 +1,32 @@ +From 6a52dbbde0e741e84f217cf762233589cc3efd13 Mon Sep 17 00:00:00 2001 +From: Wei Yongjun +Date: Fri, 26 Mar 2021 02:47:41 +0000 +Subject: [PATCH 06/16] remoteproc: qcom: wcss: Fix wrong pointer passed to + PTR_ERR() + +PTR_ERR should access the value just tested by IS_ERR, otherwise +the wrong error code will be returned. + +This commit fix it by return 'ret' directly. + +Reviewed-by: Dan Carpenter +Fixes: 0af65b9b915e ("remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404") +Reported-by: Hulk Robot +Signed-off-by: Wei Yongjun +Link: https://lore.kernel.org/r/20210326024741.841267-1-weiyongjun1@huawei.com +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -972,7 +972,7 @@ static int q6v5_wcss_init_clock(struct q + ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get axim cbcr clk\n"); +- return PTR_ERR(wcss->qdsp6ss_abhm_cbcr); ++ return ret; + } + + wcss->lcc_bcr_sleep = devm_clk_get(wcss->dev, "lcc_bcr_sleep"); diff --git a/target/linux/ipq807x/patches-5.10/008-v5.13-remoteproc-qcom-wcss-Remove-unnecessary-PTR_ERR.patch b/target/linux/ipq807x/patches-5.10/008-v5.13-remoteproc-qcom-wcss-Remove-unnecessary-PTR_ERR.patch new file mode 100644 index 000000000..dff8bda73 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/008-v5.13-remoteproc-qcom-wcss-Remove-unnecessary-PTR_ERR.patch @@ -0,0 +1,89 @@ +From 00f24490f498db0ea67715a4dfe6c4a6ca11c6a0 Mon Sep 17 00:00:00 2001 +From: Junlin Yang +Date: Thu, 8 Apr 2021 22:33:22 +0800 +Subject: [PATCH 07/16] remoteproc: qcom: wcss: Remove unnecessary PTR_ERR() + +Remove unnecessary PTR_ERR(), it has been assigned to ret before, +so return ret directly. + +Signed-off-by: Junlin Yang +Link: https://lore.kernel.org/r/20210408143322.1647-1-angkery@163.com +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -913,7 +913,7 @@ static int q6v5_wcss_init_clock(struct q + ret = PTR_ERR(wcss->gcc_abhs_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get gcc abhs clock"); +- return PTR_ERR(wcss->gcc_abhs_cbcr); ++ return ret; + } + + wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr"); +@@ -921,7 +921,7 @@ static int q6v5_wcss_init_clock(struct q + ret = PTR_ERR(wcss->gcc_axim_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get gcc axim clock\n"); +- return PTR_ERR(wcss->gcc_axim_cbcr); ++ return ret; + } + + wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev, +@@ -930,7 +930,7 @@ static int q6v5_wcss_init_clock(struct q + ret = PTR_ERR(wcss->ahbfabric_cbcr_clk); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get ahbfabric clock\n"); +- return PTR_ERR(wcss->ahbfabric_cbcr_clk); ++ return ret; + } + + wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "tcsr_lcc_cbc"); +@@ -938,7 +938,7 @@ static int q6v5_wcss_init_clock(struct q + ret = PTR_ERR(wcss->lcc_csr_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get csr cbcr clk\n"); +- return PTR_ERR(wcss->lcc_csr_cbcr); ++ return ret; + } + + wcss->ahbs_cbcr = devm_clk_get(wcss->dev, +@@ -947,7 +947,7 @@ static int q6v5_wcss_init_clock(struct q + ret = PTR_ERR(wcss->ahbs_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n"); +- return PTR_ERR(wcss->ahbs_cbcr); ++ return ret; + } + + wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev, +@@ -956,7 +956,7 @@ static int q6v5_wcss_init_clock(struct q + ret = PTR_ERR(wcss->tcm_slave_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get tcm cbcr clk\n"); +- return PTR_ERR(wcss->tcm_slave_cbcr); ++ return ret; + } + + wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "lcc_abhm_cbc"); +@@ -964,7 +964,7 @@ static int q6v5_wcss_init_clock(struct q + ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get abhm cbcr clk\n"); +- return PTR_ERR(wcss->qdsp6ss_abhm_cbcr); ++ return ret; + } + + wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "lcc_axim_cbc"); +@@ -980,7 +980,7 @@ static int q6v5_wcss_init_clock(struct q + ret = PTR_ERR(wcss->lcc_bcr_sleep); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get bcr cbcr clk\n"); +- return PTR_ERR(wcss->lcc_bcr_sleep); ++ return ret; + } + + return 0; diff --git a/target/linux/ipq807x/patches-5.10/009-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch b/target/linux/ipq807x/patches-5.10/009-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch new file mode 100644 index 000000000..a78dc82a4 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/009-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch @@ -0,0 +1,217 @@ +From 803eb124e1a64e42888542c3444bfe6dac412c7f Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam +Date: Mon, 4 Jan 2021 09:41:35 +0530 +Subject: mtd: parsers: Add Qcom SMEM parser + +NAND based Qualcomm platforms have the partition table populated in the +Shared Memory (SMEM). Hence, add a parser for parsing the partitions +from it. + +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-3-manivannan.sadhasivam@linaro.org +--- + drivers/mtd/parsers/Kconfig | 8 ++ + drivers/mtd/parsers/Makefile | 1 + + drivers/mtd/parsers/qcomsmempart.c | 170 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 179 insertions(+) + create mode 100644 drivers/mtd/parsers/qcomsmempart.c + +--- a/drivers/mtd/parsers/Kconfig ++++ b/drivers/mtd/parsers/Kconfig +@@ -196,6 +196,14 @@ config MTD_REDBOOT_PARTS_READONLY + + endif # MTD_REDBOOT_PARTS + ++config MTD_QCOMSMEM_PARTS ++ tristate "Qualcomm SMEM NAND flash partition parser" ++ depends on MTD_NAND_QCOM || COMPILE_TEST ++ depends on QCOM_SMEM ++ help ++ This provides support for parsing partitions from Shared Memory (SMEM) ++ for NAND flash on Qualcomm platforms. ++ + config MTD_ROUTERBOOT_PARTS + tristate "RouterBoot flash partition parser" + depends on MTD && OF +--- a/drivers/mtd/parsers/Makefile ++++ b/drivers/mtd/parsers/Makefile +@@ -13,4 +13,5 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o + obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o ++obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o + obj-$(CONFIG_MTD_ROUTERBOOT_PARTS) += routerbootpart.o +--- /dev/null ++++ b/drivers/mtd/parsers/qcomsmempart.c +@@ -0,0 +1,170 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Qualcomm SMEM NAND flash partition parser ++ * ++ * Copyright (C) 2020, Linaro Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SMEM_AARM_PARTITION_TABLE 9 ++#define SMEM_APPS 0 ++ ++#define SMEM_FLASH_PART_MAGIC1 0x55ee73aa ++#define SMEM_FLASH_PART_MAGIC2 0xe35ebddb ++#define SMEM_FLASH_PTABLE_V3 3 ++#define SMEM_FLASH_PTABLE_V4 4 ++#define SMEM_FLASH_PTABLE_MAX_PARTS_V3 16 ++#define SMEM_FLASH_PTABLE_MAX_PARTS_V4 48 ++#define SMEM_FLASH_PTABLE_HDR_LEN (4 * sizeof(u32)) ++#define SMEM_FLASH_PTABLE_NAME_SIZE 16 ++ ++/** ++ * struct smem_flash_pentry - SMEM Flash partition entry ++ * @name: Name of the partition ++ * @offset: Offset in blocks ++ * @length: Length of the partition in blocks ++ * @attr: Flags for this partition ++ */ ++struct smem_flash_pentry { ++ char name[SMEM_FLASH_PTABLE_NAME_SIZE]; ++ __le32 offset; ++ __le32 length; ++ u8 attr; ++} __packed __aligned(4); ++ ++/** ++ * struct smem_flash_ptable - SMEM Flash partition table ++ * @magic1: Partition table Magic 1 ++ * @magic2: Partition table Magic 2 ++ * @version: Partition table version ++ * @numparts: Number of partitions in this ptable ++ * @pentry: Flash partition entries belonging to this ptable ++ */ ++struct smem_flash_ptable { ++ __le32 magic1; ++ __le32 magic2; ++ __le32 version; ++ __le32 numparts; ++ struct smem_flash_pentry pentry[SMEM_FLASH_PTABLE_MAX_PARTS_V4]; ++} __packed __aligned(4); ++ ++static int parse_qcomsmem_part(struct mtd_info *mtd, ++ const struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct smem_flash_pentry *pentry; ++ struct smem_flash_ptable *ptable; ++ size_t len = SMEM_FLASH_PTABLE_HDR_LEN; ++ struct mtd_partition *parts; ++ int ret, i, numparts; ++ char *name, *c; ++ ++ pr_debug("Parsing partition table info from SMEM\n"); ++ ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); ++ if (IS_ERR(ptable)) { ++ pr_err("Error reading partition table header\n"); ++ return PTR_ERR(ptable); ++ } ++ ++ /* Verify ptable magic */ ++ if (le32_to_cpu(ptable->magic1) != SMEM_FLASH_PART_MAGIC1 || ++ le32_to_cpu(ptable->magic2) != SMEM_FLASH_PART_MAGIC2) { ++ pr_err("Partition table magic verification failed\n"); ++ return -EINVAL; ++ } ++ ++ /* Ensure that # of partitions is less than the max we have allocated */ ++ numparts = le32_to_cpu(ptable->numparts); ++ if (numparts > SMEM_FLASH_PTABLE_MAX_PARTS_V4) { ++ pr_err("Partition numbers exceed the max limit\n"); ++ return -EINVAL; ++ } ++ ++ /* Find out length of partition data based on table version */ ++ if (le32_to_cpu(ptable->version) <= SMEM_FLASH_PTABLE_V3) { ++ len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V3 * ++ sizeof(struct smem_flash_pentry); ++ } else if (le32_to_cpu(ptable->version) == SMEM_FLASH_PTABLE_V4) { ++ len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V4 * ++ sizeof(struct smem_flash_pentry); ++ } else { ++ pr_err("Unknown ptable version (%d)", le32_to_cpu(ptable->version)); ++ return -EINVAL; ++ } ++ ++ /* ++ * Now that the partition table header has been parsed, verified ++ * and the length of the partition table calculated, read the ++ * complete partition table ++ */ ++ ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); ++ if (IS_ERR_OR_NULL(ptable)) { ++ pr_err("Error reading partition table\n"); ++ return PTR_ERR(ptable); ++ } ++ ++ parts = kcalloc(numparts, sizeof(*parts), GFP_KERNEL); ++ if (!parts) ++ return -ENOMEM; ++ ++ for (i = 0; i < numparts; i++) { ++ pentry = &ptable->pentry[i]; ++ if (pentry->name[0] == '\0') ++ continue; ++ ++ name = kstrdup(pentry->name, GFP_KERNEL); ++ if (!name) { ++ ret = -ENOMEM; ++ goto out_free_parts; ++ } ++ ++ /* Convert name to lower case */ ++ for (c = name; *c != '\0'; c++) ++ *c = tolower(*c); ++ ++ parts[i].name = name; ++ parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize; ++ parts[i].mask_flags = pentry->attr; ++ parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize; ++ pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x\n", ++ i, pentry->name, le32_to_cpu(pentry->offset), ++ le32_to_cpu(pentry->length), pentry->attr); ++ } ++ ++ pr_debug("SMEM partition table found: ver: %d len: %d\n", ++ le32_to_cpu(ptable->version), numparts); ++ *pparts = parts; ++ ++ return numparts; ++ ++out_free_parts: ++ while (--i >= 0) ++ kfree(parts[i].name); ++ kfree(parts); ++ *pparts = NULL; ++ ++ return ret; ++} ++ ++static const struct of_device_id qcomsmem_of_match_table[] = { ++ { .compatible = "qcom,smem-part" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, qcomsmem_of_match_table); ++ ++static struct mtd_part_parser mtd_parser_qcomsmem = { ++ .parse_fn = parse_qcomsmem_part, ++ .name = "qcomsmem", ++ .of_match_table = qcomsmem_of_match_table, ++}; ++module_mtd_part_parser(mtd_parser_qcomsmem); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Manivannan Sadhasivam "); ++MODULE_DESCRIPTION("Qualcomm SMEM NAND flash partition parser"); diff --git a/target/linux/ipq807x/patches-5.10/010-v5.11-PCI-dwc-Drop-the-.set_num_vectors-host-op.patch b/target/linux/ipq807x/patches-5.10/010-v5.11-PCI-dwc-Drop-the-.set_num_vectors-host-op.patch new file mode 100644 index 000000000..c8bdec864 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/010-v5.11-PCI-dwc-Drop-the-.set_num_vectors-host-op.patch @@ -0,0 +1,120 @@ +From 80b960829a85e555b96bfd4e31f31b3db3e8f5da Mon Sep 17 00:00:00 2001 +From: Rob Herring +Date: Thu, 5 Nov 2020 15:11:50 -0600 +Subject: [PATCH 1/5] PCI: dwc: Drop the .set_num_vectors() host op + +There's no reason for the .set_num_vectors() host op. Drivers needing a +non-default value can just initialize pcie_port.num_vectors directly. + +Link: https://lore.kernel.org/r/20201105211159.1814485-8-robh@kernel.org +Tested-by: Marek Szyprowski +Signed-off-by: Rob Herring +Signed-off-by: Lorenzo Pieralisi +Acked-by: Jingoo Han +Cc: Gustavo Pimentel +Cc: Lorenzo Pieralisi +Cc: Bjorn Helgaas +Cc: Thierry Reding +Cc: Jonathan Hunter +Cc: linux-tegra@vger.kernel.org +--- + .../pci/controller/dwc/pcie-designware-host.c | 19 ++++--------------- + .../pci/controller/dwc/pcie-designware-plat.c | 7 +------ + drivers/pci/controller/dwc/pcie-designware.h | 1 - + drivers/pci/controller/dwc/pcie-tegra194.c | 7 +------ + 4 files changed, 6 insertions(+), 28 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -358,22 +358,11 @@ int dw_pcie_host_init(struct pcie_port * + pci->link_gen = of_pci_get_max_link_speed(np); + + if (pci_msi_enabled()) { +- /* +- * If a specific SoC driver needs to change the +- * default number of vectors, it needs to implement +- * the set_num_vectors callback. +- */ +- if (!pp->ops->set_num_vectors) { ++ if (!pp->num_vectors) { + pp->num_vectors = MSI_DEF_NUM_VECTORS; +- } else { +- pp->ops->set_num_vectors(pp); +- +- if (pp->num_vectors > MAX_MSI_IRQS || +- pp->num_vectors == 0) { +- dev_err(dev, +- "Invalid number of vectors\n"); +- return -EINVAL; +- } ++ } else if (pp->num_vectors > MAX_MSI_IRQS) { ++ dev_err(dev, "Invalid number of vectors\n"); ++ return -EINVAL; + } + + if (!pp->ops->msi_host_init) { +--- a/drivers/pci/controller/dwc/pcie-designware-plat.c ++++ b/drivers/pci/controller/dwc/pcie-designware-plat.c +@@ -44,14 +44,8 @@ static int dw_plat_pcie_host_init(struct + return 0; + } + +-static void dw_plat_set_num_vectors(struct pcie_port *pp) +-{ +- pp->num_vectors = MAX_MSI_IRQS; +-} +- + static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { + .host_init = dw_plat_pcie_host_init, +- .set_num_vectors = dw_plat_set_num_vectors, + }; + + static int dw_plat_pcie_establish_link(struct dw_pcie *pci) +@@ -128,6 +122,7 @@ static int dw_plat_add_pcie_port(struct + return pp->msi_irq; + } + ++ pp->num_vectors = MAX_MSI_IRQS; + pp->ops = &dw_plat_pcie_host_ops; + + ret = dw_pcie_host_init(pp); +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -174,7 +174,6 @@ enum dw_pcie_device_mode { + + struct dw_pcie_host_ops { + int (*host_init)(struct pcie_port *pp); +- void (*set_num_vectors)(struct pcie_port *pp); + int (*msi_host_init)(struct pcie_port *pp); + }; + +--- a/drivers/pci/controller/dwc/pcie-tegra194.c ++++ b/drivers/pci/controller/dwc/pcie-tegra194.c +@@ -990,11 +990,6 @@ static int tegra_pcie_dw_link_up(struct + return !!(val & PCI_EXP_LNKSTA_DLLLA); + } + +-static void tegra_pcie_set_msi_vec_num(struct pcie_port *pp) +-{ +- pp->num_vectors = MAX_MSI_IRQS; +-} +- + static int tegra_pcie_dw_start_link(struct dw_pcie *pci) + { + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); +@@ -1019,7 +1014,6 @@ static const struct dw_pcie_ops tegra_dw + + static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { + .host_init = tegra_pcie_dw_host_init, +- .set_num_vectors = tegra_pcie_set_msi_vec_num, + }; + + static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie) +@@ -2003,6 +1997,7 @@ static int tegra_pcie_dw_probe(struct pl + pci->n_fts[1] = FTS_VAL; + + pp = &pci->pp; ++ pp->num_vectors = MAX_MSI_IRQS; + pcie->dev = &pdev->dev; + pcie->mode = (enum dw_pcie_device_mode)data->mode; + diff --git a/target/linux/ipq807x/patches-5.10/011-v5.11-PCI-dwc-Move-MSI-interrupt-setup-into-DWC-common-cod.patch b/target/linux/ipq807x/patches-5.10/011-v5.11-PCI-dwc-Move-MSI-interrupt-setup-into-DWC-common-cod.patch new file mode 100644 index 000000000..634e0b437 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/011-v5.11-PCI-dwc-Move-MSI-interrupt-setup-into-DWC-common-cod.patch @@ -0,0 +1,288 @@ +From 264b6fd7baa53bfaef2a6d41067b9568dff7163a Mon Sep 17 00:00:00 2001 +From: Rob Herring +Date: Thu, 5 Nov 2020 15:11:51 -0600 +Subject: [PATCH 2/5] PCI: dwc: Move MSI interrupt setup into DWC common code + +Platforms using the built-in DWC MSI controller all have a dedicated +interrupt with "msi" name or at index 0, so let's move setting up the +interrupt to the common DWC code. + +spear13xx and dra7xx are the 2 oddballs with muxed interrupts, so +we need to prevent configuring the MSI interrupt by setting msi_irq +to negative. + +Link: https://lore.kernel.org/r/20201105211159.1814485-9-robh@kernel.org +Tested-by: Marek Szyprowski +Signed-off-by: Rob Herring +Signed-off-by: Lorenzo Pieralisi +Acked-by: Jingoo Han +Cc: Lorenzo Pieralisi +Cc: Bjorn Helgaas +Cc: Kukjin Kim +Cc: Krzysztof Kozlowski +Cc: Richard Zhu +Cc: Lucas Stach +Cc: Shawn Guo +Cc: Sascha Hauer +Cc: Pengutronix Kernel Team +Cc: Fabio Estevam +Cc: NXP Linux Team +Cc: Yue Wang +Cc: Kevin Hilman +Cc: Neil Armstrong +Cc: Jerome Brunet +Cc: Martin Blumenstingl +Cc: Jesper Nilsson +Cc: Gustavo Pimentel +Cc: Xiaowei Song +Cc: Binghui Wang +Cc: Stanimir Varbanov +Cc: Andy Gross +Cc: Bjorn Andersson +Cc: Pratyush Anand +Cc: Thierry Reding +Cc: Jonathan Hunter +Cc: Kunihiko Hayashi +Cc: Masahiro Yamada +Cc: linux-samsung-soc@vger.kernel.org +Cc: linux-amlogic@lists.infradead.org +Cc: linux-arm-kernel@axis.com +Cc: linux-arm-msm@vger.kernel.org +Cc: linux-tegra@vger.kernel.org +--- + drivers/pci/controller/dwc/pci-dra7xx.c | 3 +++ + drivers/pci/controller/dwc/pci-exynos.c | 6 ----- + drivers/pci/controller/dwc/pci-imx6.c | 6 ----- + drivers/pci/controller/dwc/pci-meson.c | 6 ----- + drivers/pci/controller/dwc/pcie-artpec6.c | 6 ----- + .../pci/controller/dwc/pcie-designware-host.c | 11 +++++++++- + .../pci/controller/dwc/pcie-designware-plat.c | 6 ----- + drivers/pci/controller/dwc/pcie-histb.c | 6 ----- + drivers/pci/controller/dwc/pcie-kirin.c | 22 ------------------- + drivers/pci/controller/dwc/pcie-qcom.c | 8 ------- + drivers/pci/controller/dwc/pcie-spear13xx.c | 1 + + drivers/pci/controller/dwc/pcie-tegra194.c | 8 ------- + drivers/pci/controller/dwc/pcie-uniphier.c | 6 ----- + 13 files changed, 14 insertions(+), 81 deletions(-) + +--- a/drivers/pci/controller/dwc/pci-dra7xx.c ++++ b/drivers/pci/controller/dwc/pci-dra7xx.c +@@ -622,6 +622,9 @@ static int __init dra7xx_add_pcie_port(s + if (pp->irq < 0) + return pp->irq; + ++ /* MSI IRQ is muxed */ ++ pp->msi_irq = -ENODEV; ++ + ret = dra7xx_pcie_init_irq_domain(pp); + if (ret < 0) + return ret; +--- a/drivers/pci/controller/dwc/pci-exynos.c ++++ b/drivers/pci/controller/dwc/pci-exynos.c +@@ -415,12 +415,6 @@ static int __init exynos_add_pcie_port(s + return ret; + } + +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- pp->msi_irq = platform_get_irq(pdev, 0); +- if (pp->msi_irq < 0) +- return pp->msi_irq; +- } +- + pp->ops = &exynos_pcie_host_ops; + + ret = dw_pcie_host_init(pp); +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -853,12 +853,6 @@ static int imx6_add_pcie_port(struct imx + struct device *dev = &pdev->dev; + int ret; + +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- pp->msi_irq = platform_get_irq_byname(pdev, "msi"); +- if (pp->msi_irq < 0) +- return pp->msi_irq; +- } +- + pp->ops = &imx6_pcie_host_ops; + + ret = dw_pcie_host_init(pp); +--- a/drivers/pci/controller/dwc/pci-meson.c ++++ b/drivers/pci/controller/dwc/pci-meson.c +@@ -405,12 +405,6 @@ static int meson_add_pcie_port(struct me + struct device *dev = &pdev->dev; + int ret; + +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- pp->msi_irq = platform_get_irq(pdev, 0); +- if (pp->msi_irq < 0) +- return pp->msi_irq; +- } +- + pp->ops = &meson_pcie_host_ops; + + ret = dw_pcie_host_init(pp); +--- a/drivers/pci/controller/dwc/pcie-artpec6.c ++++ b/drivers/pci/controller/dwc/pcie-artpec6.c +@@ -348,12 +348,6 @@ static int artpec6_add_pcie_port(struct + struct device *dev = pci->dev; + int ret; + +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- pp->msi_irq = platform_get_irq_byname(pdev, "msi"); +- if (pp->msi_irq < 0) +- return pp->msi_irq; +- } +- + pp->ops = &artpec6_pcie_host_ops; + + ret = dw_pcie_host_init(pp); +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -366,13 +366,22 @@ int dw_pcie_host_init(struct pcie_port * + } + + if (!pp->ops->msi_host_init) { ++ if (!pp->msi_irq) { ++ pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi"); ++ if (pp->msi_irq < 0) { ++ pp->msi_irq = platform_get_irq(pdev, 0); ++ if (pp->msi_irq < 0) ++ return pp->msi_irq; ++ } ++ } ++ + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + +- if (pp->msi_irq) ++ if (pp->msi_irq > 0) + irq_set_chained_handler_and_data(pp->msi_irq, + dw_chained_msi_isr, + pp); +--- a/drivers/pci/controller/dwc/pcie-designware-plat.c ++++ b/drivers/pci/controller/dwc/pcie-designware-plat.c +@@ -116,12 +116,6 @@ static int dw_plat_add_pcie_port(struct + if (pp->irq < 0) + return pp->irq; + +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- pp->msi_irq = platform_get_irq(pdev, 0); +- if (pp->msi_irq < 0) +- return pp->msi_irq; +- } +- + pp->num_vectors = MAX_MSI_IRQS; + pp->ops = &dw_plat_pcie_host_ops; + +--- a/drivers/pci/controller/dwc/pcie-histb.c ++++ b/drivers/pci/controller/dwc/pcie-histb.c +@@ -400,12 +400,6 @@ static int histb_pcie_probe(struct platf + return PTR_ERR(hipcie->bus_reset); + } + +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- pp->msi_irq = platform_get_irq_byname(pdev, "msi"); +- if (pp->msi_irq < 0) +- return pp->msi_irq; +- } +- + hipcie->phy = devm_phy_get(dev, "phy"); + if (IS_ERR(hipcie->phy)) { + dev_info(dev, "no pcie-phy found\n"); +--- a/drivers/pci/controller/dwc/pcie-kirin.c ++++ b/drivers/pci/controller/dwc/pcie-kirin.c +@@ -444,31 +444,9 @@ static const struct dw_pcie_host_ops kir + .host_init = kirin_pcie_host_init, + }; + +-static int kirin_pcie_add_msi(struct dw_pcie *pci, +- struct platform_device *pdev) +-{ +- int irq; +- +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) +- return irq; +- +- pci->pp.msi_irq = irq; +- } +- +- return 0; +-} +- + static int kirin_add_pcie_port(struct dw_pcie *pci, + struct platform_device *pdev) + { +- int ret; +- +- ret = kirin_pcie_add_msi(pci, pdev); +- if (ret) +- return ret; +- + pci->pp.ops = &kirin_pcie_host_ops; + + return dw_pcie_host_init(&pci->pp); +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -1434,14 +1434,6 @@ static int qcom_pcie_probe(struct platfo + + pp->ops = &qcom_pcie_dw_ops; + +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- pp->msi_irq = platform_get_irq_byname(pdev, "msi"); +- if (pp->msi_irq < 0) { +- ret = pp->msi_irq; +- goto err_pm_runtime_put; +- } +- } +- + ret = phy_init(pcie->phy); + if (ret) { + pm_runtime_disable(&pdev->dev); +--- a/drivers/pci/controller/dwc/pcie-spear13xx.c ++++ b/drivers/pci/controller/dwc/pcie-spear13xx.c +@@ -183,6 +183,7 @@ static int spear13xx_add_pcie_port(struc + } + + pp->ops = &spear13xx_pcie_host_ops; ++ pp->msi_irq = -ENODEV; + + ret = dw_pcie_host_init(pp); + if (ret) { +--- a/drivers/pci/controller/dwc/pcie-tegra194.c ++++ b/drivers/pci/controller/dwc/pcie-tegra194.c +@@ -1554,14 +1554,6 @@ static int tegra_pcie_config_rp(struct t + char *name; + int ret; + +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- pp->msi_irq = of_irq_get_byname(dev->of_node, "msi"); +- if (!pp->msi_irq) { +- dev_err(dev, "Failed to get MSI interrupt\n"); +- return -ENODEV; +- } +- } +- + pm_runtime_enable(dev); + + ret = pm_runtime_get_sync(dev); +--- a/drivers/pci/controller/dwc/pcie-uniphier.c ++++ b/drivers/pci/controller/dwc/pcie-uniphier.c +@@ -341,12 +341,6 @@ static int uniphier_add_pcie_port(struct + + pp->ops = &uniphier_pcie_host_ops; + +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- pp->msi_irq = platform_get_irq_byname(pdev, "msi"); +- if (pp->msi_irq < 0) +- return pp->msi_irq; +- } +- + ret = dw_pcie_host_init(pp); + if (ret) { + dev_err(dev, "Failed to initialize host (%d)\n", ret); diff --git a/target/linux/ipq807x/patches-5.10/012-v5.11-PCI-dwc-Rework-MSI-initialization.patch b/target/linux/ipq807x/patches-5.10/012-v5.11-PCI-dwc-Rework-MSI-initialization.patch new file mode 100644 index 000000000..bffa02507 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/012-v5.11-PCI-dwc-Rework-MSI-initialization.patch @@ -0,0 +1,199 @@ +From ed016f820e3f1b980dfe0ef6137069e008f99109 Mon Sep 17 00:00:00 2001 +From: Rob Herring +Date: Thu, 5 Nov 2020 15:11:52 -0600 +Subject: [PATCH 3/5] PCI: dwc: Rework MSI initialization + +There are 3 possible MSI implementations for the DWC host. The first is +using the built-in DWC MSI controller. The 2nd is a custom MSI +controller as part of the PCI host (keystone only). The 3rd is an +external MSI controller (typically GICv3 ITS). Currently, the last 2 +are distinguished with a .msi_host_init() hook with the 3rd option using +an empty function. However we can detect the 3rd case with the presence +of 'msi-parent' or 'msi-map' properties, so let's do that instead and +remove the empty functions. + +Link: https://lore.kernel.org/r/20201105211159.1814485-10-robh@kernel.org +Tested-by: Marek Szyprowski +Signed-off-by: Rob Herring +Signed-off-by: Lorenzo Pieralisi +Acked-by: Jingoo Han +Cc: Murali Karicheri +Cc: Lorenzo Pieralisi +Cc: Bjorn Helgaas +Cc: Minghuan Lian +Cc: Mingkai Hu +Cc: Roy Zang +Cc: Gustavo Pimentel +Cc: linuxppc-dev@lists.ozlabs.org +--- + drivers/pci/controller/dwc/pci-keystone.c | 9 ------- + drivers/pci/controller/dwc/pci-layerscape.c | 25 ------------------- + .../pci/controller/dwc/pcie-designware-host.c | 20 +++++++++------ + drivers/pci/controller/dwc/pcie-designware.h | 1 + + drivers/pci/controller/dwc/pcie-intel-gw.c | 9 ------- + 5 files changed, 13 insertions(+), 51 deletions(-) + +--- a/drivers/pci/controller/dwc/pci-keystone.c ++++ b/drivers/pci/controller/dwc/pci-keystone.c +@@ -272,14 +272,6 @@ static void ks_pcie_handle_legacy_irq(st + ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); + } + +-/* +- * Dummy function so that DW core doesn't configure MSI +- */ +-static int ks_pcie_am654_msi_host_init(struct pcie_port *pp) +-{ +- return 0; +-} +- + static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) + { + ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); +@@ -855,7 +847,6 @@ static const struct dw_pcie_host_ops ks_ + + static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { + .host_init = ks_pcie_host_init, +- .msi_host_init = ks_pcie_am654_msi_host_init, + }; + + static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) +--- a/drivers/pci/controller/dwc/pci-layerscape.c ++++ b/drivers/pci/controller/dwc/pci-layerscape.c +@@ -182,37 +182,12 @@ static int ls1021_pcie_host_init(struct + return ls_pcie_host_init(pp); + } + +-static int ls_pcie_msi_host_init(struct pcie_port *pp) +-{ +- struct dw_pcie *pci = to_dw_pcie_from_pp(pp); +- struct device *dev = pci->dev; +- struct device_node *np = dev->of_node; +- struct device_node *msi_node; +- +- /* +- * The MSI domain is set by the generic of_msi_configure(). This +- * .msi_host_init() function keeps us from doing the default MSI +- * domain setup in dw_pcie_host_init() and also enforces the +- * requirement that "msi-parent" exists. +- */ +- msi_node = of_parse_phandle(np, "msi-parent", 0); +- if (!msi_node) { +- dev_err(dev, "failed to find msi-parent\n"); +- return -EINVAL; +- } +- +- of_node_put(msi_node); +- return 0; +-} +- + static const struct dw_pcie_host_ops ls1021_pcie_host_ops = { + .host_init = ls1021_pcie_host_init, +- .msi_host_init = ls_pcie_msi_host_init, + }; + + static const struct dw_pcie_host_ops ls_pcie_host_ops = { + .host_init = ls_pcie_host_init, +- .msi_host_init = ls_pcie_msi_host_init, + }; + + static const struct dw_pcie_ops dw_ls1021_pcie_ops = { +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -358,6 +358,10 @@ int dw_pcie_host_init(struct pcie_port * + pci->link_gen = of_pci_get_max_link_speed(np); + + if (pci_msi_enabled()) { ++ pp->has_msi_ctrl = !(pp->ops->msi_host_init || ++ of_property_read_bool(np, "msi-parent") || ++ of_property_read_bool(np, "msi-map")); ++ + if (!pp->num_vectors) { + pp->num_vectors = MSI_DEF_NUM_VECTORS; + } else if (pp->num_vectors > MAX_MSI_IRQS) { +@@ -365,7 +369,11 @@ int dw_pcie_host_init(struct pcie_port * + return -EINVAL; + } + +- if (!pp->ops->msi_host_init) { ++ if (pp->ops->msi_host_init) { ++ ret = pp->ops->msi_host_init(pp); ++ if (ret < 0) ++ return ret; ++ } else if (pp->has_msi_ctrl) { + if (!pp->msi_irq) { + pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi"); + if (pp->msi_irq < 0) { +@@ -395,10 +403,6 @@ int dw_pcie_host_init(struct pcie_port * + pp->msi_data = 0; + goto err_free_msi; + } +- } else { +- ret = pp->ops->msi_host_init(pp); +- if (ret < 0) +- return ret; + } + } + +@@ -419,7 +423,7 @@ int dw_pcie_host_init(struct pcie_port * + return 0; + + err_free_msi: +- if (pci_msi_enabled() && !pp->ops->msi_host_init) ++ if (pp->has_msi_ctrl) + dw_pcie_free_msi(pp); + return ret; + } +@@ -429,7 +433,7 @@ void dw_pcie_host_deinit(struct pcie_por + { + pci_stop_root_bus(pp->bridge->bus); + pci_remove_root_bus(pp->bridge->bus); +- if (pci_msi_enabled() && !pp->ops->msi_host_init) ++ if (pp->has_msi_ctrl) + dw_pcie_free_msi(pp); + } + EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); +@@ -540,7 +544,7 @@ void dw_pcie_setup_rc(struct pcie_port * + + dw_pcie_setup(pci); + +- if (pci_msi_enabled() && !pp->ops->msi_host_init) { ++ if (pp->has_msi_ctrl) { + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -178,6 +178,7 @@ struct dw_pcie_host_ops { + }; + + struct pcie_port { ++ bool has_msi_ctrl:1; + u64 cfg0_base; + void __iomem *va_cfg0_base; + u32 cfg0_size; +--- a/drivers/pci/controller/dwc/pcie-intel-gw.c ++++ b/drivers/pci/controller/dwc/pcie-intel-gw.c +@@ -401,14 +401,6 @@ static int intel_pcie_rc_init(struct pci + return intel_pcie_host_setup(lpp); + } + +-/* +- * Dummy function so that DW core doesn't configure MSI +- */ +-static int intel_pcie_msi_init(struct pcie_port *pp) +-{ +- return 0; +-} +- + static u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr) + { + return cpu_addr + BUS_IATU_OFFSET; +@@ -420,7 +412,6 @@ static const struct dw_pcie_ops intel_pc + + static const struct dw_pcie_host_ops intel_pcie_dw_ops = { + .host_init = intel_pcie_rc_init, +- .msi_host_init = intel_pcie_msi_init, + }; + + static const struct intel_pcie_soc pcie_data = { diff --git a/target/linux/ipq807x/patches-5.10/013-v5.11-PCI-dwc-Move-link-handling-into-common-code.patch b/target/linux/ipq807x/patches-5.10/013-v5.11-PCI-dwc-Move-link-handling-into-common-code.patch new file mode 100644 index 000000000..b12da222e --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/013-v5.11-PCI-dwc-Move-link-handling-into-common-code.patch @@ -0,0 +1,603 @@ +From 533bee2aeda70c212a3fb5547d5beb6406e3ccf7 Mon Sep 17 00:00:00 2001 +From: Rob Herring +Date: Thu, 5 Nov 2020 15:11:53 -0600 +Subject: [PATCH 4/5] PCI: dwc: Move link handling into common code + +All the DWC drivers do link setup and checks at roughly the same time. +Let's use the existing .start_link() hook (currently only used in EP +mode) and move the link handling to the core code. + +The behavior for a link down was inconsistent as some drivers would fail +probe in that case while others succeed. Let's standardize this to +succeed as there are usecases where devices (and the link) appear later +even without hotplug. For example, a reconfigured FPGA device. + +Link: https://lore.kernel.org/r/20201105211159.1814485-11-robh@kernel.org +Tested-by: Marek Szyprowski +Signed-off-by: Rob Herring +Signed-off-by: Lorenzo Pieralisi +Acked-by: Jingoo Han +Cc: Kishon Vijay Abraham I +Cc: Lorenzo Pieralisi +Cc: Bjorn Helgaas +Cc: Kukjin Kim +Cc: Krzysztof Kozlowski +Cc: Richard Zhu +Cc: Lucas Stach +Cc: Shawn Guo +Cc: Sascha Hauer +Cc: Pengutronix Kernel Team +Cc: Fabio Estevam +Cc: NXP Linux Team +Cc: Murali Karicheri +Cc: Yue Wang +Cc: Kevin Hilman +Cc: Neil Armstrong +Cc: Jerome Brunet +Cc: Martin Blumenstingl +Cc: Thomas Petazzoni +Cc: Jesper Nilsson +Cc: Gustavo Pimentel +Cc: Xiaowei Song +Cc: Binghui Wang +Cc: Andy Gross +Cc: Bjorn Andersson +Cc: Stanimir Varbanov +Cc: Pratyush Anand +Cc: Thierry Reding +Cc: Jonathan Hunter +Cc: Kunihiko Hayashi +Cc: Masahiro Yamada +Cc: linux-omap@vger.kernel.org +Cc: linux-samsung-soc@vger.kernel.org +Cc: linux-amlogic@lists.infradead.org +Cc: linux-arm-kernel@axis.com +Cc: linux-arm-msm@vger.kernel.org +Cc: linux-tegra@vger.kernel.org +--- + drivers/pci/controller/dwc/pci-dra7xx.c | 2 - + drivers/pci/controller/dwc/pci-exynos.c | 41 +++++++---------- + drivers/pci/controller/dwc/pci-imx6.c | 9 ++-- + drivers/pci/controller/dwc/pci-keystone.c | 9 ---- + drivers/pci/controller/dwc/pci-meson.c | 24 ++++------ + drivers/pci/controller/dwc/pcie-armada8k.c | 39 +++++++--------- + drivers/pci/controller/dwc/pcie-artpec6.c | 2 - + .../pci/controller/dwc/pcie-designware-host.c | 9 ++++ + .../pci/controller/dwc/pcie-designware-plat.c | 3 -- + drivers/pci/controller/dwc/pcie-histb.c | 34 +++++++------- + drivers/pci/controller/dwc/pcie-kirin.c | 23 ++-------- + drivers/pci/controller/dwc/pcie-qcom.c | 19 ++------ + drivers/pci/controller/dwc/pcie-spear13xx.c | 46 ++++++++----------- + drivers/pci/controller/dwc/pcie-tegra194.c | 1 - + drivers/pci/controller/dwc/pcie-uniphier.c | 13 ++---- + 15 files changed, 103 insertions(+), 171 deletions(-) + +--- a/drivers/pci/controller/dwc/pci-dra7xx.c ++++ b/drivers/pci/controller/dwc/pci-dra7xx.c +@@ -183,8 +183,6 @@ static int dra7xx_pcie_host_init(struct + + dw_pcie_setup_rc(pp); + +- dra7xx_pcie_establish_link(pci); +- dw_pcie_wait_for_link(pci); + dw_pcie_msi_init(pp); + dra7xx_pcie_enable_interrupts(dra7xx); + +--- a/drivers/pci/controller/dwc/pci-exynos.c ++++ b/drivers/pci/controller/dwc/pci-exynos.c +@@ -229,30 +229,9 @@ static void exynos_pcie_assert_reset(str + GPIOF_OUT_INIT_HIGH, "RESET"); + } + +-static int exynos_pcie_establish_link(struct exynos_pcie *ep) ++static int exynos_pcie_start_link(struct dw_pcie *pci) + { +- struct dw_pcie *pci = ep->pci; +- struct pcie_port *pp = &pci->pp; +- struct device *dev = pci->dev; +- +- if (dw_pcie_link_up(pci)) { +- dev_err(dev, "Link already up\n"); +- return 0; +- } +- +- exynos_pcie_assert_core_reset(ep); +- +- phy_reset(ep->phy); +- +- exynos_pcie_writel(ep->mem_res->elbi_base, 1, +- PCIE_PWR_RESET); +- +- phy_power_on(ep->phy); +- phy_init(ep->phy); +- +- exynos_pcie_deassert_core_reset(ep); +- dw_pcie_setup_rc(pp); +- exynos_pcie_assert_reset(ep); ++ struct exynos_pcie *ep = to_exynos_pcie(pci); + + /* assert LTSSM enable */ + exynos_pcie_writel(ep->mem_res->elbi_base, PCIE_ELBI_LTSSM_ENABLE, +@@ -386,7 +365,20 @@ static int exynos_pcie_host_init(struct + + pp->bridge->ops = &exynos_pci_ops; + +- exynos_pcie_establish_link(ep); ++ exynos_pcie_assert_core_reset(ep); ++ ++ phy_reset(ep->phy); ++ ++ exynos_pcie_writel(ep->mem_res->elbi_base, 1, ++ PCIE_PWR_RESET); ++ ++ phy_power_on(ep->phy); ++ phy_init(ep->phy); ++ ++ exynos_pcie_deassert_core_reset(ep); ++ dw_pcie_setup_rc(pp); ++ exynos_pcie_assert_reset(ep); ++ + exynos_pcie_enable_interrupts(ep); + + return 0; +@@ -430,6 +422,7 @@ static const struct dw_pcie_ops dw_pcie_ + .read_dbi = exynos_pcie_read_dbi, + .write_dbi = exynos_pcie_write_dbi, + .link_up = exynos_pcie_link_up, ++ .start_link = exynos_pcie_start_link, + }; + + static int __init exynos_pcie_probe(struct platform_device *pdev) +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -745,9 +745,9 @@ static void imx6_pcie_ltssm_enable(struc + } + } + +-static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) ++static int imx6_pcie_start_link(struct dw_pcie *pci) + { +- struct dw_pcie *pci = imx6_pcie->pci; ++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct device *dev = pci->dev; + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 tmp; +@@ -835,7 +835,6 @@ static int imx6_pcie_host_init(struct pc + imx6_pcie_deassert_core_reset(imx6_pcie); + imx6_setup_phy_mpll(imx6_pcie); + dw_pcie_setup_rc(pp); +- imx6_pcie_establish_link(imx6_pcie); + dw_pcie_msi_init(pp); + + return 0; +@@ -865,7 +864,7 @@ static int imx6_add_pcie_port(struct imx + } + + static const struct dw_pcie_ops dw_pcie_ops = { +- /* No special ops needed, but pcie-designware still expects this struct */ ++ .start_link = imx6_pcie_start_link, + }; + + #ifdef CONFIG_PM_SLEEP +@@ -974,7 +973,7 @@ static int imx6_pcie_resume_noirq(struct + imx6_pcie_deassert_core_reset(imx6_pcie); + dw_pcie_setup_rc(pp); + +- ret = imx6_pcie_establish_link(imx6_pcie); ++ ret = imx6_pcie_start_link(imx6_pcie->pci); + if (ret < 0) + dev_info(dev, "pcie link is down after resume.\n"); + +--- a/drivers/pci/controller/dwc/pci-keystone.c ++++ b/drivers/pci/controller/dwc/pci-keystone.c +@@ -511,14 +511,8 @@ static void ks_pcie_stop_link(struct dw_ + static int ks_pcie_start_link(struct dw_pcie *pci) + { + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); +- struct device *dev = pci->dev; + u32 val; + +- if (dw_pcie_link_up(pci)) { +- dev_dbg(dev, "link is already up\n"); +- return 0; +- } +- + /* Initiate Link Training */ + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); +@@ -834,9 +828,6 @@ static int __init ks_pcie_host_init(stru + "Asynchronous external abort"); + #endif + +- ks_pcie_start_link(pci); +- dw_pcie_wait_for_link(pci); +- + return 0; + } + +--- a/drivers/pci/controller/dwc/pci-meson.c ++++ b/drivers/pci/controller/dwc/pci-meson.c +@@ -231,7 +231,7 @@ static void meson_pcie_assert_reset(stru + gpiod_set_value_cansleep(mp->reset_gpio, 0); + } + +-static void meson_pcie_init_dw(struct meson_pcie *mp) ++static void meson_pcie_ltssm_enable(struct meson_pcie *mp) + { + u32 val; + +@@ -289,20 +289,14 @@ static void meson_set_max_rd_req_size(st + dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); + } + +-static int meson_pcie_establish_link(struct meson_pcie *mp) ++static int meson_pcie_start_link(struct dw_pcie *pci) + { +- struct dw_pcie *pci = &mp->pci; +- struct pcie_port *pp = &pci->pp; +- +- meson_pcie_init_dw(mp); +- meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); +- meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); +- +- dw_pcie_setup_rc(pp); ++ struct meson_pcie *mp = to_meson_pcie(pci); + ++ meson_pcie_ltssm_enable(mp); + meson_pcie_assert_reset(mp); + +- return dw_pcie_wait_for_link(pci); ++ return 0; + } + + static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, +@@ -380,14 +374,13 @@ static int meson_pcie_host_init(struct p + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct meson_pcie *mp = to_meson_pcie(pci); +- int ret; + + pp->bridge->ops = &meson_pci_ops; + +- ret = meson_pcie_establish_link(mp); +- if (ret) +- return ret; ++ meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); ++ meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); + ++ dw_pcie_setup_rc(pp); + dw_pcie_msi_init(pp); + + return 0; +@@ -418,6 +411,7 @@ static int meson_add_pcie_port(struct me + + static const struct dw_pcie_ops dw_pcie_ops = { + .link_up = meson_pcie_link_up, ++ .start_link = meson_pcie_start_link, + }; + + static int meson_pcie_probe(struct platform_device *pdev) +--- a/drivers/pci/controller/dwc/pcie-armada8k.c ++++ b/drivers/pci/controller/dwc/pcie-armada8k.c +@@ -154,10 +154,24 @@ static int armada8k_pcie_link_up(struct + return 0; + } + +-static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) ++static int armada8k_pcie_start_link(struct dw_pcie *pci) ++{ ++ u32 reg; ++ ++ /* Start LTSSM */ ++ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); ++ reg |= PCIE_APP_LTSSM_EN; ++ dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); ++ ++ return 0; ++} ++ ++static int armada8k_pcie_host_init(struct pcie_port *pp) + { +- struct dw_pcie *pci = pcie->pci; + u32 reg; ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ ++ dw_pcie_setup_rc(pp); + + if (!dw_pcie_link_up(pci)) { + /* Disable LTSSM state machine to enable configuration */ +@@ -193,26 +207,6 @@ static void armada8k_pcie_establish_link + PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + +- if (!dw_pcie_link_up(pci)) { +- /* Configuration done. Start LTSSM */ +- reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); +- reg |= PCIE_APP_LTSSM_EN; +- dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); +- } +- +- /* Wait until the link becomes active again */ +- if (dw_pcie_wait_for_link(pci)) +- dev_err(pci->dev, "Link not up after reconfiguration\n"); +-} +- +-static int armada8k_pcie_host_init(struct pcie_port *pp) +-{ +- struct dw_pcie *pci = to_dw_pcie_from_pp(pp); +- struct armada8k_pcie *pcie = to_armada8k_pcie(pci); +- +- dw_pcie_setup_rc(pp); +- armada8k_pcie_establish_link(pcie); +- + return 0; + } + +@@ -269,6 +263,7 @@ static int armada8k_add_pcie_port(struct + + static const struct dw_pcie_ops dw_pcie_ops = { + .link_up = armada8k_pcie_link_up, ++ .start_link = armada8k_pcie_start_link, + }; + + static int armada8k_pcie_probe(struct platform_device *pdev) +--- a/drivers/pci/controller/dwc/pcie-artpec6.c ++++ b/drivers/pci/controller/dwc/pcie-artpec6.c +@@ -329,8 +329,6 @@ static int artpec6_pcie_host_init(struct + artpec6_pcie_deassert_core_reset(artpec6_pcie); + artpec6_pcie_wait_for_phy(artpec6_pcie); + dw_pcie_setup_rc(pp); +- artpec6_pcie_establish_link(pci); +- dw_pcie_wait_for_link(pci); + dw_pcie_msi_init(pp); + + return 0; +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -416,6 +416,15 @@ int dw_pcie_host_init(struct pcie_port * + goto err_free_msi; + } + ++ if (!dw_pcie_link_up(pci) && pci->ops->start_link) { ++ ret = pci->ops->start_link(pci); ++ if (ret) ++ goto err_free_msi; ++ } ++ ++ /* Ignore errors, the link may come up later */ ++ dw_pcie_wait_for_link(pci); ++ + bridge->sysdata = pp; + + ret = pci_host_probe(bridge); +--- a/drivers/pci/controller/dwc/pcie-designware-plat.c ++++ b/drivers/pci/controller/dwc/pcie-designware-plat.c +@@ -35,10 +35,7 @@ static const struct of_device_id dw_plat + + static int dw_plat_pcie_host_init(struct pcie_port *pp) + { +- struct dw_pcie *pci = to_dw_pcie_from_pp(pp); +- + dw_pcie_setup_rc(pp); +- dw_pcie_wait_for_link(pci); + dw_pcie_msi_init(pp); + + return 0; +--- a/drivers/pci/controller/dwc/pcie-histb.c ++++ b/drivers/pci/controller/dwc/pcie-histb.c +@@ -169,39 +169,36 @@ static int histb_pcie_link_up(struct dw_ + return 0; + } + +-static int histb_pcie_establish_link(struct pcie_port *pp) ++static int histb_pcie_start_link(struct dw_pcie *pci) + { +- struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct histb_pcie *hipcie = to_histb_pcie(pci); + u32 regval; + +- if (dw_pcie_link_up(pci)) { +- dev_info(pci->dev, "Link already up\n"); +- return 0; +- } +- +- /* PCIe RC work mode */ +- regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0); +- regval &= ~PCIE_DEVICE_TYPE_MASK; +- regval |= PCIE_WM_RC; +- histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval); +- +- /* setup root complex */ +- dw_pcie_setup_rc(pp); +- + /* assert LTSSM enable */ + regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL7); + regval |= PCIE_APP_LTSSM_ENABLE; + histb_pcie_writel(hipcie, PCIE_SYS_CTRL7, regval); + +- return dw_pcie_wait_for_link(pci); ++ return 0; + } + + static int histb_pcie_host_init(struct pcie_port *pp) + { ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ struct histb_pcie *hipcie = to_histb_pcie(pci); ++ u32 regval; ++ + pp->bridge->ops = &histb_pci_ops; + +- histb_pcie_establish_link(pp); ++ /* PCIe RC work mode */ ++ regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0); ++ regval &= ~PCIE_DEVICE_TYPE_MASK; ++ regval |= PCIE_WM_RC; ++ histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval); ++ ++ /* setup root complex */ ++ dw_pcie_setup_rc(pp); ++ + dw_pcie_msi_init(pp); + + return 0; +@@ -300,6 +297,7 @@ static const struct dw_pcie_ops dw_pcie_ + .read_dbi = histb_pcie_read_dbi, + .write_dbi = histb_pcie_write_dbi, + .link_up = histb_pcie_link_up, ++ .start_link = histb_pcie_start_link, + }; + + static int histb_pcie_probe(struct platform_device *pdev) +--- a/drivers/pci/controller/dwc/pcie-kirin.c ++++ b/drivers/pci/controller/dwc/pcie-kirin.c +@@ -395,32 +395,14 @@ static int kirin_pcie_link_up(struct dw_ + return 0; + } + +-static int kirin_pcie_establish_link(struct pcie_port *pp) ++static int kirin_pcie_start_link(struct dw_pcie *pci) + { +- struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); +- struct device *dev = kirin_pcie->pci->dev; +- int count = 0; +- +- if (kirin_pcie_link_up(pci)) +- return 0; +- +- dw_pcie_setup_rc(pp); + + /* assert LTSSM enable */ + kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT, + PCIE_APP_LTSSM_ENABLE); + +- /* check if the link is up or not */ +- while (!kirin_pcie_link_up(pci)) { +- usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX); +- count++; +- if (count == 1000) { +- dev_err(dev, "Link Fail\n"); +- return -EINVAL; +- } +- } +- + return 0; + } + +@@ -428,7 +410,7 @@ static int kirin_pcie_host_init(struct p + { + pp->bridge->ops = &kirin_pci_ops; + +- kirin_pcie_establish_link(pp); ++ dw_pcie_setup_rc(pp); + dw_pcie_msi_init(pp); + + return 0; +@@ -438,6 +420,7 @@ static const struct dw_pcie_ops kirin_dw + .read_dbi = kirin_pcie_read_dbi, + .write_dbi = kirin_pcie_write_dbi, + .link_up = kirin_pcie_link_up, ++ .start_link = kirin_pcie_start_link, + }; + + static const struct dw_pcie_host_ops kirin_pcie_host_ops = { +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -207,18 +207,15 @@ static void qcom_ep_reset_deassert(struc + usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); + } + +-static int qcom_pcie_establish_link(struct qcom_pcie *pcie) ++static int qcom_pcie_start_link(struct dw_pcie *pci) + { +- struct dw_pcie *pci = pcie->pci; +- +- if (dw_pcie_link_up(pci)) +- return 0; ++ struct qcom_pcie *pcie = to_qcom_pcie(pci); + + /* Enable Link Training state machine */ + if (pcie->ops->ltssm_enable) + pcie->ops->ltssm_enable(pcie); + +- return dw_pcie_wait_for_link(pci); ++ return 0; + } + + static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) +@@ -1290,15 +1287,8 @@ static int qcom_pcie_host_init(struct pc + + qcom_ep_reset_deassert(pcie); + +- ret = qcom_pcie_establish_link(pcie); +- if (ret) +- goto err; +- + return 0; +-err: +- qcom_ep_reset_assert(pcie); +- if (pcie->ops->post_deinit) +- pcie->ops->post_deinit(pcie); ++ + err_disable_phy: + phy_power_off(pcie->phy); + err_deinit: +@@ -1365,6 +1355,7 @@ static const struct qcom_pcie_ops ops_2_ + + static const struct dw_pcie_ops dw_pcie_ops = { + .link_up = qcom_pcie_link_up, ++ .start_link = qcom_pcie_start_link, + }; + + static int qcom_pcie_probe(struct platform_device *pdev) +--- a/drivers/pci/controller/dwc/pcie-tegra194.c ++++ b/drivers/pci/controller/dwc/pcie-tegra194.c +@@ -1549,7 +1549,6 @@ static int tegra_pcie_deinit_controller( + + static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) + { +- struct pcie_port *pp = &pcie->pci.pp; + struct device *dev = pcie->dev; + char *name; + int ret; +--- a/drivers/pci/controller/dwc/pcie-uniphier.c ++++ b/drivers/pci/controller/dwc/pcie-uniphier.c +@@ -146,16 +146,13 @@ static int uniphier_pcie_link_up(struct + return (val & mask) == mask; + } + +-static int uniphier_pcie_establish_link(struct dw_pcie *pci) ++static int uniphier_pcie_start_link(struct dw_pcie *pci) + { + struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); + +- if (dw_pcie_link_up(pci)) +- return 0; +- + uniphier_pcie_ltssm_enable(priv, true); + +- return dw_pcie_wait_for_link(pci); ++ return 0; + } + + static void uniphier_pcie_stop_link(struct dw_pcie *pci) +@@ -318,10 +315,6 @@ static int uniphier_pcie_host_init(struc + uniphier_pcie_irq_enable(priv); + + dw_pcie_setup_rc(pp); +- ret = uniphier_pcie_establish_link(pci); +- if (ret) +- return ret; +- + dw_pcie_msi_init(pp); + + return 0; +@@ -385,7 +378,7 @@ out_clk_disable: + } + + static const struct dw_pcie_ops dw_pcie_ops = { +- .start_link = uniphier_pcie_establish_link, ++ .start_link = uniphier_pcie_start_link, + .stop_link = uniphier_pcie_stop_link, + .link_up = uniphier_pcie_link_up, + }; diff --git a/target/linux/ipq807x/patches-5.10/014-v5.11-PCI-dwc-Move-dw_pcie_msi_init-into-core.patch b/target/linux/ipq807x/patches-5.10/014-v5.11-PCI-dwc-Move-dw_pcie_msi_init-into-core.patch new file mode 100644 index 000000000..fda806e00 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/014-v5.11-PCI-dwc-Move-dw_pcie_msi_init-into-core.patch @@ -0,0 +1,272 @@ +From 02c98d70da854cd4d145afe800194768c5eefe1d Mon Sep 17 00:00:00 2001 +From: Rob Herring +Date: Thu, 5 Nov 2020 15:11:54 -0600 +Subject: [PATCH 5/5] PCI: dwc: Move dw_pcie_msi_init() into core + +The host drivers which call dw_pcie_msi_init() are all the ones using +the built-in MSI controller, so let's move it into the common DWC code. + +Link: https://lore.kernel.org/r/20201105211159.1814485-12-robh@kernel.org +Tested-by: Marek Szyprowski +Signed-off-by: Rob Herring +Signed-off-by: Lorenzo Pieralisi +Acked-by: Jingoo Han +Cc: Kishon Vijay Abraham I +Cc: Lorenzo Pieralisi +Cc: Bjorn Helgaas +Cc: Kukjin Kim +Cc: Krzysztof Kozlowski +Cc: Richard Zhu +Cc: Lucas Stach +Cc: Shawn Guo +Cc: Sascha Hauer +Cc: Pengutronix Kernel Team +Cc: Fabio Estevam +Cc: NXP Linux Team +Cc: Yue Wang +Cc: Kevin Hilman +Cc: Neil Armstrong +Cc: Jerome Brunet +Cc: Martin Blumenstingl +Cc: Jesper Nilsson +Cc: Gustavo Pimentel +Cc: Xiaowei Song +Cc: Binghui Wang +Cc: Stanimir Varbanov +Cc: Andy Gross +Cc: Bjorn Andersson +Cc: Pratyush Anand +Cc: Thierry Reding +Cc: Jonathan Hunter +Cc: Kunihiko Hayashi +Cc: Masahiro Yamada +Cc: linux-omap@vger.kernel.org +Cc: linux-samsung-soc@vger.kernel.org +Cc: linux-amlogic@lists.infradead.org +Cc: linux-arm-kernel@axis.com +Cc: linux-arm-msm@vger.kernel.org +Cc: linux-tegra@vger.kernel.org +--- + drivers/pci/controller/dwc/pci-dra7xx.c | 2 -- + drivers/pci/controller/dwc/pci-exynos.c | 4 ---- + drivers/pci/controller/dwc/pci-imx6.c | 1 - + drivers/pci/controller/dwc/pci-meson.c | 1 - + drivers/pci/controller/dwc/pcie-artpec6.c | 1 - + drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++---- + drivers/pci/controller/dwc/pcie-designware-plat.c | 1 - + drivers/pci/controller/dwc/pcie-designware.h | 10 ---------- + drivers/pci/controller/dwc/pcie-histb.c | 2 -- + drivers/pci/controller/dwc/pcie-kirin.c | 1 - + drivers/pci/controller/dwc/pcie-qcom.c | 2 -- + drivers/pci/controller/dwc/pcie-spear13xx.c | 6 +----- + drivers/pci/controller/dwc/pcie-tegra194.c | 2 -- + drivers/pci/controller/dwc/pcie-uniphier.c | 1 - + 14 files changed, 6 insertions(+), 37 deletions(-) + +--- a/drivers/pci/controller/dwc/pci-dra7xx.c ++++ b/drivers/pci/controller/dwc/pci-dra7xx.c +@@ -182,8 +182,6 @@ static int dra7xx_pcie_host_init(struct + struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); + + dw_pcie_setup_rc(pp); +- +- dw_pcie_msi_init(pp); + dra7xx_pcie_enable_interrupts(dra7xx); + + return 0; +--- a/drivers/pci/controller/dwc/pci-exynos.c ++++ b/drivers/pci/controller/dwc/pci-exynos.c +@@ -273,12 +273,8 @@ static irqreturn_t exynos_pcie_irq_handl + + static void exynos_pcie_msi_init(struct exynos_pcie *ep) + { +- struct dw_pcie *pci = ep->pci; +- struct pcie_port *pp = &pci->pp; + u32 val; + +- dw_pcie_msi_init(pp); +- + /* enable MSI interrupt */ + val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL); + val |= IRQ_MSI_ENABLE; +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -835,7 +835,6 @@ static int imx6_pcie_host_init(struct pc + imx6_pcie_deassert_core_reset(imx6_pcie); + imx6_setup_phy_mpll(imx6_pcie); + dw_pcie_setup_rc(pp); +- dw_pcie_msi_init(pp); + + return 0; + } +--- a/drivers/pci/controller/dwc/pci-meson.c ++++ b/drivers/pci/controller/dwc/pci-meson.c +@@ -381,7 +381,6 @@ static int meson_pcie_host_init(struct p + meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); + + dw_pcie_setup_rc(pp); +- dw_pcie_msi_init(pp); + + return 0; + } +--- a/drivers/pci/controller/dwc/pcie-artpec6.c ++++ b/drivers/pci/controller/dwc/pcie-artpec6.c +@@ -329,7 +329,6 @@ static int artpec6_pcie_host_init(struct + artpec6_pcie_deassert_core_reset(artpec6_pcie); + artpec6_pcie_wait_for_phy(artpec6_pcie); + dw_pcie_setup_rc(pp); +- dw_pcie_msi_init(pp); + + return 0; + } +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -256,7 +256,7 @@ int dw_pcie_allocate_domains(struct pcie + return 0; + } + +-void dw_pcie_free_msi(struct pcie_port *pp) ++static void dw_pcie_free_msi(struct pcie_port *pp) + { + if (pp->msi_irq) { + irq_set_chained_handler(pp->msi_irq, NULL); +@@ -275,19 +275,18 @@ void dw_pcie_free_msi(struct pcie_port * + } + } + +-void dw_pcie_msi_init(struct pcie_port *pp) ++static void dw_pcie_msi_init(struct pcie_port *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + u64 msi_target = (u64)pp->msi_data; + +- if (!IS_ENABLED(CONFIG_PCI_MSI)) ++ if (!pci_msi_enabled() || !pp->has_msi_ctrl) + return; + + /* Program the msi_data */ + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); + } +-EXPORT_SYMBOL_GPL(dw_pcie_msi_init); + + int dw_pcie_host_init(struct pcie_port *pp) + { +@@ -416,6 +415,8 @@ int dw_pcie_host_init(struct pcie_port * + goto err_free_msi; + } + ++ dw_pcie_msi_init(pp); ++ + if (!dw_pcie_link_up(pci) && pci->ops->start_link) { + ret = pci->ops->start_link(pci); + if (ret) +--- a/drivers/pci/controller/dwc/pcie-designware-plat.c ++++ b/drivers/pci/controller/dwc/pcie-designware-plat.c +@@ -36,7 +36,6 @@ static const struct of_device_id dw_plat + static int dw_plat_pcie_host_init(struct pcie_port *pp) + { + dw_pcie_setup_rc(pp); +- dw_pcie_msi_init(pp); + + return 0; + } +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -365,8 +365,6 @@ static inline void dw_pcie_dbi_ro_wr_dis + + #ifdef CONFIG_PCIE_DW_HOST + irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); +-void dw_pcie_msi_init(struct pcie_port *pp); +-void dw_pcie_free_msi(struct pcie_port *pp); + void dw_pcie_setup_rc(struct pcie_port *pp); + int dw_pcie_host_init(struct pcie_port *pp); + void dw_pcie_host_deinit(struct pcie_port *pp); +@@ -379,14 +377,6 @@ static inline irqreturn_t dw_handle_msi_ + return IRQ_NONE; + } + +-static inline void dw_pcie_msi_init(struct pcie_port *pp) +-{ +-} +- +-static inline void dw_pcie_free_msi(struct pcie_port *pp) +-{ +-} +- + static inline void dw_pcie_setup_rc(struct pcie_port *pp) + { + } +--- a/drivers/pci/controller/dwc/pcie-histb.c ++++ b/drivers/pci/controller/dwc/pcie-histb.c +@@ -199,8 +199,6 @@ static int histb_pcie_host_init(struct p + /* setup root complex */ + dw_pcie_setup_rc(pp); + +- dw_pcie_msi_init(pp); +- + return 0; + } + +--- a/drivers/pci/controller/dwc/pcie-kirin.c ++++ b/drivers/pci/controller/dwc/pcie-kirin.c +@@ -411,7 +411,6 @@ static int kirin_pcie_host_init(struct p + pp->bridge->ops = &kirin_pci_ops; + + dw_pcie_setup_rc(pp); +- dw_pcie_msi_init(pp); + + return 0; + } +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -1283,8 +1283,6 @@ static int qcom_pcie_host_init(struct pc + } + + dw_pcie_setup_rc(pp); +- dw_pcie_msi_init(pp); +- + qcom_ep_reset_deassert(pcie); + + return 0; +--- a/drivers/pci/controller/dwc/pcie-spear13xx.c ++++ b/drivers/pci/controller/dwc/pcie-spear13xx.c +@@ -124,16 +124,12 @@ static irqreturn_t spear13xx_pcie_irq_ha + + static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie) + { +- struct dw_pcie *pci = spear13xx_pcie->pci; +- struct pcie_port *pp = &pci->pp; + struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; + + /* Enable MSI interrupt */ +- if (IS_ENABLED(CONFIG_PCI_MSI)) { +- dw_pcie_msi_init(pp); ++ if (IS_ENABLED(CONFIG_PCI_MSI)) + writel(readl(&app_reg->int_mask) | + MSI_CTRL_INT, &app_reg->int_mask); +- } + } + + static int spear13xx_pcie_link_up(struct dw_pcie *pci) +--- a/drivers/pci/controller/dwc/pcie-tegra194.c ++++ b/drivers/pci/controller/dwc/pcie-tegra194.c +@@ -765,8 +765,6 @@ static void tegra_pcie_enable_msi_interr + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); + u32 val; + +- dw_pcie_msi_init(pp); +- + /* Enable MSI interrupt generation */ + val = appl_readl(pcie, APPL_INTR_EN_L0_0); + val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN; +--- a/drivers/pci/controller/dwc/pcie-uniphier.c ++++ b/drivers/pci/controller/dwc/pcie-uniphier.c +@@ -315,7 +315,6 @@ static int uniphier_pcie_host_init(struc + uniphier_pcie_irq_enable(priv); + + dw_pcie_setup_rc(pp); +- dw_pcie_msi_init(pp); + + return 0; + } diff --git a/target/linux/ipq807x/patches-5.10/100-clk-qcom-ipq8074-fix-PCI-E-clock-oops.patch b/target/linux/ipq807x/patches-5.10/100-clk-qcom-ipq8074-fix-PCI-E-clock-oops.patch new file mode 100644 index 000000000..87428c0da --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/100-clk-qcom-ipq8074-fix-PCI-E-clock-oops.patch @@ -0,0 +1,54 @@ +From 8d111d707f71bc17c616b0bcca327ee0a3db50e8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 2 Nov 2020 19:03:59 +0100 +Subject: [PATCH] clk: qcom: ipq8074: fix PCI-E clock oops + +Fix PCI-E clock related kernel oops that are causes by missing +parent_names. + +Without the use of parent_names kernel will panic on +clk_core_get_parent_by_index() due to a NULL pointer. + +Without this earlycon is needed to even catch the OOPS as it will reset +the board before serial is initialized. + +Fixes: f0cfcf1ade20 ("clk: qcom: ipq8074: Add missing clocks for pcie") +Signed-off-by: Robert Marko +--- + drivers/clk/qcom/gcc-ipq8074.c | 11 +++++------ + 1 file changed, 5 insertions(+), 6 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -4329,8 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pcie0_rchng_clk_src", +- .parent_hws = (const struct clk_hw *[]) { +- &gpll0.clkr.hw }, ++ .parent_names = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +@@ -4344,8 +4343,8 @@ static struct clk_branch gcc_pcie0_rchng + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_rchng_clk", +- .parent_hws = (const struct clk_hw *[]){ +- &pcie0_rchng_clk_src.clkr.hw, ++ .parent_names = (const char *[]){ ++ "pcie0_rchng_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -4362,8 +4361,8 @@ static struct clk_branch gcc_pcie0_axi_s + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_axi_s_bridge_clk", +- .parent_hws = (const struct clk_hw *[]){ +- &pcie0_axi_clk_src.clkr.hw, ++ .parent_names = (const char *[]){ ++ "pcie0_axi_clk_src" + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, diff --git a/target/linux/ipq807x/patches-5.10/101-arm64-dts-ipq8074-add-crypto-nodes.patch b/target/linux/ipq807x/patches-5.10/101-arm64-dts-ipq8074-add-crypto-nodes.patch new file mode 100644 index 000000000..2d872d152 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/101-arm64-dts-ipq8074-add-crypto-nodes.patch @@ -0,0 +1,48 @@ +From 69581d91675df8c0d9b5f746de7c2f3d73344280 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 11 May 2021 15:10:37 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add crypto nodes + +IPQ8074 uses Qualcom QCE crypto engine v5.1 +which is already supported. + +So simply add nodes for its DMA and QCE itself. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -197,6 +197,30 @@ + status = "disabled"; + }; + ++ cryptobam: dma@704000 { ++ compatible = "qcom,bam-v1.7.0"; ++ reg = <0x00704000 0x20000>; ++ interrupts = ; ++ clocks = <&gcc GCC_CRYPTO_AHB_CLK>; ++ clock-names = "bam_clk"; ++ #dma-cells = <1>; ++ qcom,ee = <1>; ++ qcom,controlled-remotely = <1>; ++ status = "disabled"; ++ }; ++ ++ crypto: crypto@73a000 { ++ compatible = "qcom,crypto-v5.1"; ++ reg = <0x0073a000 0x6000>; ++ clocks = <&gcc GCC_CRYPTO_AHB_CLK>, ++ <&gcc GCC_CRYPTO_AXI_CLK>, ++ <&gcc GCC_CRYPTO_CLK>; ++ clock-names = "iface", "bus", "core"; ++ dmas = <&cryptobam 2>, <&cryptobam 3>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq8074-pinctrl"; + reg = <0x01000000 0x300000>; diff --git a/target/linux/ipq807x/patches-5.10/102-arm64-dts-ipq8074-add-PRNG-node.patch b/target/linux/ipq807x/patches-5.10/102-arm64-dts-ipq8074-add-PRNG-node.patch new file mode 100644 index 000000000..1aafef56a --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/102-arm64-dts-ipq8074-add-PRNG-node.patch @@ -0,0 +1,30 @@ +From ff46c62852e862ac360aeb1054180c8e715fbeb4 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 11 May 2021 15:23:53 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add PRNG node + +PRNG insinde of IPQ8074 is already supported, +so simply add the node for it. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -197,6 +197,14 @@ + status = "disabled"; + }; + ++ prng: rng@e3000 { ++ compatible = "qcom,prng-ee"; ++ reg = <0x000e3000 0x1000>; ++ clocks = <&gcc GCC_PRNG_AHB_CLK>; ++ clock-names = "core"; ++ status = "disabled"; ++ }; ++ + cryptobam: dma@704000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x00704000 0x20000>; diff --git a/target/linux/ipq807x/patches-5.4/106-04-remoteproc-qcom-Add-PRNG-proxy-clock.patch b/target/linux/ipq807x/patches-5.10/103-remoteproc-qcom-Add-PRNG-proxy-clock.patch similarity index 55% rename from target/linux/ipq807x/patches-5.4/106-04-remoteproc-qcom-Add-PRNG-proxy-clock.patch rename to target/linux/ipq807x/patches-5.10/103-remoteproc-qcom-Add-PRNG-proxy-clock.patch index f19d641be..b8e842b30 100644 --- a/target/linux/ipq807x/patches-5.4/106-04-remoteproc-qcom-Add-PRNG-proxy-clock.patch +++ b/target/linux/ipq807x/patches-5.10/103-remoteproc-qcom-Add-PRNG-proxy-clock.patch @@ -1,56 +1,7 @@ -From patchwork Thu Jul 30 12:26:35 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692951 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A2A513B6 - for ; - Thu, 30 Jul 2020 12:29:02 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by mail.kernel.org (Postfix) with ESMTP id 0B7292082E - for ; - Thu, 30 Jul 2020 12:29:02 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1728690AbgG3M3B (ORCPT - ); - Thu, 30 Jul 2020 08:29:01 -0400 -Received: from alexa-out.qualcomm.com ([129.46.98.28]:43483 "EHLO - alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1728430AbgG3M2t (ORCPT - ); - Thu, 30 Jul 2020 08:28:49 -0400 -Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) - by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:48 -0700 -Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) - by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; - 30 Jul 2020 05:28:46 -0700 -Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) - by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:11 +0530 -Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) - id F3197218A1; Thu, 30 Jul 2020 17:58:09 +0530 (IST) +From e0d3c4e232c2b29532f7b894485814782201fdd9 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy -To: gokulsri@codeaurora.org, agross@kernel.org, - bjorn.andersson@linaro.org, david.brown@linaro.org, - devicetree@vger.kernel.org, jassisinghbrar@gmail.com, - linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, - mark.rutland@arm.com, mturquette@baylibre.com, - nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, - sboyd@kernel.org, sricharan@codeaurora.org -Subject: [PATCH v7 1/9] remoteproc: qcom: Add PRNG proxy clock -Date: Thu, 30 Jul 2020 17:56:35 +0530 -Message-Id: <1596112003-31663-2-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org +Date: Sat, 30 Jan 2021 10:50:05 +0530 +Subject: [PATCH 08/16] remoteproc: qcom: Add PRNG proxy clock PRNG clock is needed by the secure PIL, support for the same is added in subsequent patches. @@ -59,7 +10,7 @@ Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Signed-off-by: Nikhil Prakash V --- - drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++++++++---------- + drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++-------- 1 file changed, 47 insertions(+), 18 deletions(-) --- a/drivers/remoteproc/qcom_q6v5_wcss.c @@ -185,7 +136,7 @@ Signed-off-by: Nikhil Prakash V if (ret) goto free_rproc; } -@@ -1080,6 +1106,7 @@ static int q6v5_wcss_remove(struct platf +@@ -1082,6 +1108,7 @@ static int q6v5_wcss_remove(struct platf } static const struct wcss_data wcss_ipq8074_res_init = { @@ -193,7 +144,7 @@ Signed-off-by: Nikhil Prakash V .firmware_name = "IPQ8074/q6_fw.mdt", .crash_reason_smem = WCSS_CRASH_REASON, .aon_reset_required = true, -@@ -1089,6 +1116,8 @@ static const struct wcss_data wcss_ipq80 +@@ -1091,6 +1118,8 @@ static const struct wcss_data wcss_ipq80 }; static const struct wcss_data wcss_qcs404_res_init = { diff --git a/target/linux/ipq807x/patches-5.4/106-05-remoteproc-qcom-Add-secure-PIL-support.patch b/target/linux/ipq807x/patches-5.10/104-remoteproc-qcom-Add-secure-PIL-support.patch similarity index 57% rename from target/linux/ipq807x/patches-5.4/106-05-remoteproc-qcom-Add-secure-PIL-support.patch rename to target/linux/ipq807x/patches-5.10/104-remoteproc-qcom-Add-secure-PIL-support.patch index 1dc3dfd40..1931b01e1 100644 --- a/target/linux/ipq807x/patches-5.4/106-05-remoteproc-qcom-Add-secure-PIL-support.patch +++ b/target/linux/ipq807x/patches-5.10/104-remoteproc-qcom-Add-secure-PIL-support.patch @@ -1,56 +1,7 @@ -From patchwork Thu Jul 30 12:26:36 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692981 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 430041744 - for ; - Thu, 30 Jul 2020 12:29:20 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by mail.kernel.org (Postfix) with ESMTP id 346672082E - for ; - Thu, 30 Jul 2020 12:29:20 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1728528AbgG3M3S (ORCPT - ); - Thu, 30 Jul 2020 08:29:18 -0400 -Received: from alexa-out.qualcomm.com ([129.46.98.28]:43483 "EHLO - alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1728318AbgG3M2r (ORCPT - ); - Thu, 30 Jul 2020 08:28:47 -0400 -Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) - by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:46 -0700 -Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) - by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; - 30 Jul 2020 05:28:44 -0700 -Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) - by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:13 +0530 -Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) - id 072B2218A1; Thu, 30 Jul 2020 17:58:11 +0530 (IST) +From a6256ebbd66f3457e4a285b72b362d452bc6854f Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy -To: gokulsri@codeaurora.org, agross@kernel.org, - bjorn.andersson@linaro.org, david.brown@linaro.org, - devicetree@vger.kernel.org, jassisinghbrar@gmail.com, - linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, - mark.rutland@arm.com, mturquette@baylibre.com, - nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, - sboyd@kernel.org, sricharan@codeaurora.org -Subject: [PATCH v7 2/9] remoteproc: qcom: Add secure PIL support -Date: Thu, 30 Jul 2020 17:56:36 +0530 -Message-Id: <1596112003-31663-3-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org +Date: Sat, 30 Jan 2021 10:50:06 +0530 +Subject: [PATCH 09/16] remoteproc: qcom: Add secure PIL support IPQ8074 uses secure PIL. Hence, adding the support for the same. @@ -58,7 +9,7 @@ Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Signed-off-by: Nikhil Prakash V --- - drivers/remoteproc/qcom_q6v5_wcss.c | 43 ++++++++++++++++++++++++++++++++++--- + drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 3 deletions(-) --- a/drivers/remoteproc/qcom_q6v5_wcss.c @@ -136,7 +87,7 @@ Signed-off-by: Nikhil Prakash V + /* WCSS powerdown */ if (wcss->requires_force_stop) { - ret = qcom_q6v5_request_stop(&wcss->q6v5); + ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); @@ -741,6 +766,7 @@ static int q6v5_wcss_stop(struct rproc * return ret; } @@ -182,7 +133,7 @@ Signed-off-by: Nikhil Prakash V ret = q6v5_wcss_init_mmio(wcss, pdev); if (ret) -@@ -1113,6 +1149,7 @@ static const struct wcss_data wcss_ipq80 +@@ -1115,6 +1151,7 @@ static const struct wcss_data wcss_ipq80 .wcss_q6_reset_required = true, .ops = &q6v5_wcss_ipq8074_ops, .requires_force_stop = true, diff --git a/target/linux/ipq807x/patches-5.4/106-06-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-firmware.patch b/target/linux/ipq807x/patches-5.10/105-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch similarity index 52% rename from target/linux/ipq807x/patches-5.4/106-06-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-firmware.patch rename to target/linux/ipq807x/patches-5.10/105-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch index 3346b3460..fd82c57b5 100644 --- a/target/linux/ipq807x/patches-5.4/106-06-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-firmware.patch +++ b/target/linux/ipq807x/patches-5.10/105-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch @@ -1,57 +1,8 @@ -From patchwork Thu Jul 30 12:26:37 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692965 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BBE09722 - for ; - Thu, 30 Jul 2020 12:29:16 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by mail.kernel.org (Postfix) with ESMTP id A87452082E - for ; - Thu, 30 Jul 2020 12:29:16 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1728400AbgG3M2s (ORCPT - ); - Thu, 30 Jul 2020 08:28:48 -0400 -Received: from alexa-out.qualcomm.com ([129.46.98.28]:26713 "EHLO - alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1728315AbgG3M2q (ORCPT - ); - Thu, 30 Jul 2020 08:28:46 -0400 -Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) - by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:46 -0700 -Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) - by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; - 30 Jul 2020 05:28:44 -0700 -Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) - by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:13 +0530 -Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) - id 1DA23213B6; Thu, 30 Jul 2020 17:58:12 +0530 (IST) +From ea44aa0384fec6d6fcd5bf6bf52175628bad7319 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy -To: gokulsri@codeaurora.org, agross@kernel.org, - bjorn.andersson@linaro.org, david.brown@linaro.org, - devicetree@vger.kernel.org, jassisinghbrar@gmail.com, - linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, - mark.rutland@arm.com, mturquette@baylibre.com, - nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, - sboyd@kernel.org, sricharan@codeaurora.org -Subject: [PATCH v7 3/9] remoteproc: qcom: Add support for split q6 + m3 wlan +Date: Sat, 30 Jan 2021 10:50:07 +0530 +Subject: [PATCH 10/16] remoteproc: qcom: Add support for split q6 + m3 wlan firmware -Date: Thu, 30 Jul 2020 17:56:37 +0530 -Message-Id: <1596112003-31663-4-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 supports split firmware for q6 and m3 as well. So add support for loading the m3 firmware before q6. @@ -62,7 +13,7 @@ Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Signed-off-by: Nikhil Prakash V --- - drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++++++---- + drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) --- a/drivers/remoteproc/qcom_q6v5_wcss.c @@ -132,7 +83,7 @@ Signed-off-by: Nikhil Prakash V ret = q6v5_wcss_init_mmio(wcss, pdev); if (ret) -@@ -1143,7 +1167,8 @@ static int q6v5_wcss_remove(struct platf +@@ -1145,7 +1169,8 @@ static int q6v5_wcss_remove(struct platf static const struct wcss_data wcss_ipq8074_res_init = { .init_clock = ipq8074_init_clock, @@ -142,7 +93,7 @@ Signed-off-by: Nikhil Prakash V .crash_reason_smem = WCSS_CRASH_REASON, .aon_reset_required = true, .wcss_q6_reset_required = true, -@@ -1156,7 +1181,7 @@ static const struct wcss_data wcss_qcs40 +@@ -1158,7 +1183,7 @@ static const struct wcss_data wcss_qcs40 .init_clock = qcs404_init_clock, .init_regulator = qcs404_init_regulator, .crash_reason_smem = WCSS_CRASH_REASON, diff --git a/target/linux/ipq807x/patches-5.10/106-remoteproc-qcom-Add-ssr-subdevice-identifier.patch b/target/linux/ipq807x/patches-5.10/106-remoteproc-qcom-Add-ssr-subdevice-identifier.patch new file mode 100644 index 000000000..9307a944a --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/106-remoteproc-qcom-Add-ssr-subdevice-identifier.patch @@ -0,0 +1,24 @@ +From dcfc2e3a3e346e0cad4c5b8707aaab96f4bbb59d Mon Sep 17 00:00:00 2001 +From: Gokul Sriram Palanisamy +Date: Sat, 30 Jan 2021 10:50:08 +0530 +Subject: [PATCH 11/16] remoteproc: qcom: Add ssr subdevice identifier + +Add name for ssr subdevice on IPQ8074 SoC. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -1174,6 +1174,7 @@ static const struct wcss_data wcss_ipq80 + .crash_reason_smem = WCSS_CRASH_REASON, + .aon_reset_required = true, + .wcss_q6_reset_required = true, ++ .ssr_name = "q6wcss", + .ops = &q6v5_wcss_ipq8074_ops, + .requires_force_stop = true, + .need_mem_protection = true, diff --git a/target/linux/ipq807x/patches-5.10/107-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch b/target/linux/ipq807x/patches-5.10/107-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch new file mode 100644 index 000000000..d844aa7cf --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/107-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch @@ -0,0 +1,80 @@ +From 543a7093420b500a197fc64361084613f248f07a Mon Sep 17 00:00:00 2001 +From: Gokul Sriram Palanisamy +Date: Sat, 30 Jan 2021 10:50:09 +0530 +Subject: [PATCH 12/16] remoteproc: qcom: Update regmap offsets for halt + register + +Fixed issue in reading halt-regs parameter from device-tree. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++-------- + 1 file changed, 14 insertions(+), 8 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -86,7 +86,7 @@ + #define TCSR_WCSS_CLK_MASK 0x1F + #define TCSR_WCSS_CLK_ENABLE 0x14 + +-#define MAX_HALT_REG 3 ++#define MAX_HALT_REG 4 + + #define WCNSS_PAS_ID 6 + +@@ -154,6 +154,7 @@ struct wcss_data { + u32 version; + bool aon_reset_required; + bool wcss_q6_reset_required; ++ bool bcr_reset_required; + const char *ssr_name; + const char *sysmon_name; + int ssctl_id; +@@ -874,10 +875,13 @@ static int q6v5_wcss_init_reset(struct q + } + } + +- wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset"); +- if (IS_ERR(wcss->wcss_q6_bcr_reset)) { +- dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); +- return PTR_ERR(wcss->wcss_q6_bcr_reset); ++ if (desc->bcr_reset_required) { ++ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, ++ "wcss_q6_bcr_reset"); ++ if (IS_ERR(wcss->wcss_q6_bcr_reset)) { ++ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); ++ return PTR_ERR(wcss->wcss_q6_bcr_reset); ++ } + } + + return 0; +@@ -925,9 +929,9 @@ static int q6v5_wcss_init_mmio(struct q6 + return -EINVAL; + } + +- wcss->halt_q6 = halt_reg[0]; +- wcss->halt_wcss = halt_reg[1]; +- wcss->halt_nc = halt_reg[2]; ++ wcss->halt_q6 = halt_reg[1]; ++ wcss->halt_wcss = halt_reg[2]; ++ wcss->halt_nc = halt_reg[3]; + + return 0; + } +@@ -1174,6 +1178,7 @@ static const struct wcss_data wcss_ipq80 + .crash_reason_smem = WCSS_CRASH_REASON, + .aon_reset_required = true, + .wcss_q6_reset_required = true, ++ .bcr_reset_required = false, + .ssr_name = "q6wcss", + .ops = &q6v5_wcss_ipq8074_ops, + .requires_force_stop = true, +@@ -1188,6 +1193,7 @@ static const struct wcss_data wcss_qcs40 + .version = WCSS_QCS404, + .aon_reset_required = false, + .wcss_q6_reset_required = false, ++ .bcr_reset_required = true, + .ssr_name = "mpss", + .sysmon_name = "wcnss", + .ssctl_id = 0x12, diff --git a/target/linux/ipq807x/patches-5.10/108-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch b/target/linux/ipq807x/patches-5.10/108-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch new file mode 100644 index 000000000..516273ffb --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/108-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch @@ -0,0 +1,25 @@ +From 12c7588316e1aceb3a4918896735e8bc3757815f Mon Sep 17 00:00:00 2001 +From: Gokul Sriram Palanisamy +Date: Sat, 30 Jan 2021 10:50:10 +0530 +Subject: [PATCH 13/16] dt-bindings: clock: qcom: Add reset for WCSSAON + +Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V +Acked-by: Rob Herring +Acked-by: Stephen Boyd +--- + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +@@ -366,5 +366,6 @@ + #define GCC_PCIE1_AHB_ARES 129 + #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 + #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 ++#define GCC_WCSSAON_RESET 132 + + #endif diff --git a/target/linux/ipq807x/patches-5.10/109-clk-qcom-Add-WCSSAON-reset.patch b/target/linux/ipq807x/patches-5.10/109-clk-qcom-Add-WCSSAON-reset.patch new file mode 100644 index 000000000..f36b560a9 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/109-clk-qcom-Add-WCSSAON-reset.patch @@ -0,0 +1,25 @@ +From 6de5e246382d6b15f297cadbf26bdd78ee7f9fea Mon Sep 17 00:00:00 2001 +From: Gokul Sriram Palanisamy +Date: Sat, 30 Jan 2021 10:50:11 +0530 +Subject: [PATCH 14/16] clk: qcom: Add WCSSAON reset + +Add WCSSAON reset required for Q6v5 on IPQ8074 SoC. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V +Acked-by: Stephen Boyd +--- + drivers/clk/qcom/gcc-ipq8074.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -4744,6 +4744,7 @@ static const struct qcom_reset_map gcc_i + [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, + [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, + [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, ++ [GCC_WCSSAON_RESET] = { 0x59010, 0 }, + }; + + static const struct of_device_id gcc_ipq8074_match_table[] = { diff --git a/target/linux/ipq807x/patches-5.10/110-arm64-dts-Add-support-for-scm-on-IPQ8074-SoCs.patch b/target/linux/ipq807x/patches-5.10/110-arm64-dts-Add-support-for-scm-on-IPQ8074-SoCs.patch new file mode 100644 index 000000000..6dbabf1ce --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/110-arm64-dts-Add-support-for-scm-on-IPQ8074-SoCs.patch @@ -0,0 +1,28 @@ +From b177148d326cac30723f5fe9c939db2919aab33a Mon Sep 17 00:00:00 2001 +From: Gokul Sriram Palanisamy +Date: Sat, 30 Jan 2021 10:50:12 +0530 +Subject: [PATCH 15/16] arm64: dts: Add support for scm on IPQ8074 SoCs + +Enables scm support, clock is not needed for enabling scm interface. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -76,6 +76,12 @@ + method = "smc"; + }; + ++ firmware { ++ scm { ++ compatible = "qcom,scm-ipq8074", "qcom,scm"; ++ }; ++ }; ++ + soc: soc { + #address-cells = <0x1>; + #size-cells = <0x1>; diff --git a/target/linux/ipq807x/patches-5.4/106-11-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch b/target/linux/ipq807x/patches-5.10/111-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch similarity index 65% rename from target/linux/ipq807x/patches-5.4/106-11-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch rename to target/linux/ipq807x/patches-5.10/111-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch index dcd8e6a4d..688333421 100644 --- a/target/linux/ipq807x/patches-5.4/106-11-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch +++ b/target/linux/ipq807x/patches-5.10/111-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch @@ -1,35 +1,59 @@ -From cc3bb635a139e9967c43a5e4ba36ec6ff929cb8f Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 23 Aug 2020 00:00:44 +0200 -Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC +From 9428cd325c99212b25407df8035284012d65acdb Mon Sep 17 00:00:00 2001 +From: Gokul Sriram Palanisamy +Date: Sat, 30 Jan 2021 10:50:13 +0530 +Subject: [PATCH 16/16] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC Enable remoteproc WCSS PIL driver with glink and ssr subdevices. Also configures shared memory and enables smp2p and mailboxes required for IPC. -Signed-off-by: Robert Marko +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V --- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 93 insertions(+) + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 121 ++++++++++++++++++++++++++ + 1 file changed, 121 insertions(+) --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -107,6 +107,11 @@ - reg = <0x0 0x4ab00000 0x0 0x100000>; - no-map; - }; +@@ -76,12 +76,66 @@ + method = "smc"; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ smem_region: memory@4ab00000 { ++ no-map; ++ reg = <0x0 0x4ab00000 0x0 0x00100000>; ++ }; + + q6_region: memory@4b000000 { + no-map; + reg = <0x0 0x4b000000 0x0 0x05f00000>; + }; ++ }; ++ + firmware { + scm { + compatible = "qcom,scm-ipq8074", "qcom,scm"; + }; }; - smem { -@@ -115,6 +120,32 @@ - hwlocks = <&tcsr_mutex 0>; - }; - ++ tcsr_mutex: hwlock@193d000 { ++ compatible = "qcom,tcsr-mutex"; ++ syscon = <&tcsr_mutex_regs 0 0x80>; ++ #hwlock-cells = <1>; ++ }; ++ ++ smem { ++ compatible = "qcom,smem"; ++ memory-region = <&smem_region>; ++ hwlocks = <&tcsr_mutex 0>; ++ }; ++ + wcss: smp2p-wcss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; @@ -59,22 +83,21 @@ Signed-off-by: Robert Marko soc: soc { #address-cells = <0x1>; #size-cells = <0x1>; -@@ -220,6 +251,11 @@ - reg = <0x1905000 0x8000>; +@@ -727,5 +781,72 @@ + "axi_m_sticky"; + status = "disabled"; }; - ++ + tcsr_q6: syscon@1945000 { + compatible = "syscon"; + reg = <0x01945000 0xe000>; + }; + - sdhc_1: sdhci@7824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x500>, <0x7824000 0x800>; -@@ -390,6 +426,13 @@ - ; - }; - ++ tcsr_mutex_regs: syscon@193d000 { ++ compatible = "syscon"; ++ reg = <0x01905000 0x8000>; ++ }; ++ + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; + reg = <0x0b111000 0x1000>; @@ -82,13 +105,6 @@ Signed-off-by: Robert Marko + #mbox-cells = <1>; + }; + - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; -@@ -449,6 +492,56 @@ - }; - }; - + q6v5_wcss: q6v5_wcss@cd00000 { + compatible = "qcom,ipq8074-wcss-pil"; + reg = <0x0cd00000 0x4040>, @@ -138,7 +154,5 @@ Signed-off-by: Robert Marko + }; + }; + }; -+ - pcie1: pci@10000000 { - compatible = "qcom,pcie-ipq8074"; - reg = <0x10000000 0xf1d + }; + }; diff --git a/target/linux/ipq807x/patches-5.10/112-qcom-socinfo-Add-IPQ8074-SoC-family-ID-s.patch b/target/linux/ipq807x/patches-5.10/112-qcom-socinfo-Add-IPQ8074-SoC-family-ID-s.patch new file mode 100644 index 000000000..5fa58dbc4 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/112-qcom-socinfo-Add-IPQ8074-SoC-family-ID-s.patch @@ -0,0 +1,35 @@ +From 5454294f432c0c095f3e2b54fd45491be779c545 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 11 May 2021 18:11:13 +0200 +Subject: [PATCH] soc: qcom: socinfo: Add IPQ8074 SoC family ID-s + +Add ID-s for the Qualcomm IPQ8074 SoC family. + +Signed-off-by: Robert Marko +--- + drivers/soc/qcom/socinfo.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/soc/qcom/socinfo.c ++++ b/drivers/soc/qcom/socinfo.c +@@ -224,8 +224,20 @@ static const struct soc_id soc_id[] = { + { 312, "APQ8096SG" }, + { 318, "SDM630" }, + { 321, "SDM845" }, ++ { 323, "IPQ8074" }, + { 341, "SDA845" }, ++ { 342, "IPQ8072" }, ++ { 343, "IPQ8076" }, ++ { 344, "IPQ8078" }, + { 356, "SM8250" }, ++ { 375, "IPQ8070" }, ++ { 376, "IPQ8071" }, ++ { 389, "IPQ8072A" }, ++ { 390, "IPQ8074A" }, ++ { 391, "IPQ8076A" }, ++ { 392, "IPQ8078A" }, ++ { 395, "IPQ8070A" }, ++ { 396, "IPQ8071A" }, + { 402, "IPQ6018" }, + { 425, "SC7180" }, + }; diff --git a/target/linux/ipq807x/patches-5.10/113-net-mdio-ipq4019-add-clock-handling.patch b/target/linux/ipq807x/patches-5.10/113-net-mdio-ipq4019-add-clock-handling.patch new file mode 100644 index 000000000..863bf2bdf --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/113-net-mdio-ipq4019-add-clock-handling.patch @@ -0,0 +1,49 @@ +From d91c466ec19e5ced30631cec703164c79525b986 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 27 Dec 2020 18:55:56 +0100 +Subject: [PATCH] net: mdio-ipq4019: add clock handling + +Newer SoC-s like IPQ807x and IPQ60xx use the same MDIO controller, +but have separate MDIO clocks that need to be handled. +So lets add support for doing that. + +Signed-off-by: Robert Marko +--- + drivers/net/mdio/mdio-ipq4019.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/net/mdio/mdio-ipq4019.c ++++ b/drivers/net/mdio/mdio-ipq4019.c +@@ -2,6 +2,7 @@ + /* Copyright (c) 2015, The Linux Foundation. All rights reserved. */ + /* Copyright (c) 2020 Sartura Ltd. */ + ++#include + #include + #include + #include +@@ -33,6 +34,7 @@ + + struct ipq4019_mdio_data { + void __iomem *membase; ++ struct clk *clk; + }; + + static int ipq4019_mdio_wait_busy(struct mii_bus *bus) +@@ -187,6 +189,16 @@ static int ipq4019_mdio_probe(struct pla + if (IS_ERR(priv->membase)) + return PTR_ERR(priv->membase); + ++ priv->clk = devm_clk_get_optional(&pdev->dev, "mdio_ahb"); ++ if (IS_ERR(priv->clk)) { ++ dev_err(&pdev->dev, "Failed getting clock!\n"); ++ return PTR_ERR(priv->clk); ++ } ++ ++ ret = clk_prepare_enable(priv->clk); ++ if (ret) ++ return ret; ++ + bus->name = "ipq4019_mdio"; + bus->read = ipq4019_mdio_read; + bus->write = ipq4019_mdio_write; diff --git a/target/linux/ipq807x/patches-5.10/114-arm64-dts-ipq8074-Add-MDIO-support.patch b/target/linux/ipq807x/patches-5.10/114-arm64-dts-ipq8074-Add-MDIO-support.patch new file mode 100644 index 000000000..8f9176e12 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/114-arm64-dts-ipq8074-Add-MDIO-support.patch @@ -0,0 +1,34 @@ +From 67ba6e563928123fc65dab604592a60da2cce648 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 11 May 2021 18:24:35 +0200 +Subject: [PATCH] arm64: dts: ipq8074: Add MDIO support + +MDIO controller is the same one as in IPQ4019, so +lets add the node to support it. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -257,6 +257,18 @@ + status = "disabled"; + }; + ++ mdio: mdio@90000 { ++ compatible = "qcom,ipq4019-mdio"; ++ reg = <0x00090000 0x64>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ clocks = <&gcc GCC_MDIO_AHB_CLK>; ++ clock-names = "mdio_ahb"; ++ ++ status = "disabled"; ++ }; ++ + prng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; diff --git a/target/linux/ipq807x/patches-5.10/115-phy-qcom-qmp-Add-IPQ8074-PCIe-Gen3-QMP-PHY-support.patch b/target/linux/ipq807x/patches-5.10/115-phy-qcom-qmp-Add-IPQ8074-PCIe-Gen3-QMP-PHY-support.patch new file mode 100644 index 000000000..4b9a37885 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/115-phy-qcom-qmp-Add-IPQ8074-PCIe-Gen3-QMP-PHY-support.patch @@ -0,0 +1,369 @@ +From 57887b141d68224dcf4039a2f5215011f43dd9f4 Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Wed, 29 Jul 2020 21:00:04 +0530 +Subject: [PATCH] phy: qcom-qmp: Add IPQ8074 PCIe Gen3 QMP PHY support + +IPQ8074 has two PCIe ports, One Gen2 and one Gen3 port. +Since support for Gen2 PHY is already available, add support for +PCIe Gen3 PHY. + +Co-developed-by: Selvam Sathappan Periakaruppan +Signed-off-by: Selvam Sathappan Periakaruppan +Signed-off-by: Sivaprakash Murugesan +Signed-off-by: Robert Marko +--- + drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 139 ++++++++++++++++++ + drivers/phy/qualcomm/phy-qcom-qmp.c | 171 +++++++++++++++++++++- + 2 files changed, 308 insertions(+), 2 deletions(-) + create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h + +--- /dev/null ++++ b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h +@@ -0,0 +1,139 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++/* ++ * Copyright (c) 2020, The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef PHY_QCOM_PCIE_H ++#define PHY_QCOM_PCIE_H ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES PLL registers */ ++#define QSERDES_PLL_BG_TIMER 0x00c ++#define QSERDES_PLL_SSC_PER1 0x01c ++#define QSERDES_PLL_SSC_PER2 0x020 ++#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 ++#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 ++#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c ++#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 ++#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c ++#define QSERDES_PLL_CLK_ENABLE1 0x040 ++#define QSERDES_PLL_SYS_CLK_CTRL 0x044 ++#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 ++#define QSERDES_PLL_PLL_IVCO 0x050 ++#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 ++#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 ++#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 ++#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 ++#define QSERDES_PLL_BG_TRIM 0x074 ++#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 ++#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c ++#define QSERDES_PLL_CP_CTRL_MODE0 0x080 ++#define QSERDES_PLL_CP_CTRL_MODE1 0x084 ++#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 ++#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C ++#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 ++#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 ++#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 ++#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 ++#define QSERDES_PLL_RESETSM_CNTRL 0x0b0 ++#define QSERDES_PLL_LOCK_CMP_EN 0x0c4 ++#define QSERDES_PLL_DEC_START_MODE0 0x0cc ++#define QSERDES_PLL_DEC_START_MODE1 0x0d0 ++#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 ++#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc ++#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 ++#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 ++#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 ++#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC ++#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 ++#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 ++#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 ++#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c ++#define QSERDES_PLL_VCO_TUNE_MAP 0x120 ++#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 ++#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 ++#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c ++#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 ++#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c ++#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 ++#define QSERDES_PLL_CLK_SELECT 0x16c ++#define QSERDES_PLL_HSCLK_SEL 0x170 ++#define QSERDES_PLL_CORECLK_DIV 0x17c ++#define QSERDES_PLL_CORE_CLK_EN 0x184 ++#define QSERDES_PLL_CMN_CONFIG 0x18c ++#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 ++#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - - QSERDES TX registers */ ++#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c ++#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 ++#define QSERDES_TX0_LANE_MODE_1 0x084 ++#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES RX registers */ ++#define QSERDES_RX0_UCDR_FO_GAIN 0x008 ++#define QSERDES_RX0_UCDR_SO_GAIN 0x014 ++#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034 ++#define QSERDES_RX0_UCDR_PI_CONTROLS 0x044 ++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec ++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0 ++#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4 ++#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8 ++#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc ++#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 ++#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114 ++#define QSERDES_RX0_SIGDET_ENABLES 0x118 ++#define QSERDES_RX0_SIGDET_CNTRL 0x11c ++#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124 ++#define QSERDES_RX0_RX_MODE_00_LOW 0x170 ++#define QSERDES_RX0_RX_MODE_00_HIGH 0x174 ++#define QSERDES_RX0_RX_MODE_00_HIGH2 0x178 ++#define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c ++#define QSERDES_RX0_RX_MODE_00_HIGH4 0x180 ++#define QSERDES_RX0_RX_MODE_01_LOW 0x184 ++#define QSERDES_RX0_RX_MODE_01_HIGH 0x188 ++#define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c ++#define QSERDES_RX0_RX_MODE_01_HIGH3 0x190 ++#define QSERDES_RX0_RX_MODE_01_HIGH4 0x194 ++#define QSERDES_RX0_RX_MODE_10_LOW 0x198 ++#define QSERDES_RX0_RX_MODE_10_HIGH 0x19c ++#define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0 ++#define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4 ++#define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8 ++#define QSERDES_RX0_DFE_EN_TIMER 0x1b4 ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - PCS registers */ ++ ++#define PCS_COM_FLL_CNTRL1 0x098 ++#define PCS_COM_FLL_CNTRL2 0x09c ++#define PCS_COM_FLL_CNT_VAL_L 0x0a0 ++#define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4 ++#define PCS_COM_FLL_MAN_CODE 0x0a8 ++#define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc ++#define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c ++#define PCS_COM_RX_SIGDET_LVL 0x188 ++#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 ++#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 ++#define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8 ++#define PCS_COM_EQ_CONFIG5 0x1ec ++ ++/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - PCS Misc registers */ ++ ++#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c ++#define PCS_PCIE_POWER_STATE_CONFIG4 0x414 ++#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c ++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440 ++#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444 ++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448 ++#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c ++#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c ++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478 ++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480 ++#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484 ++#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490 ++#define PCS_PCIE_EQ_CONFIG1 0x4a0 ++#define PCS_PCIE_EQ_CONFIG2 0x4a4 ++#define PCS_PCIE_PRESET_P10_PRE 0x4bc ++#define PCS_PCIE_PRESET_P10_POST 0x4e0 ++ ++#endif +--- a/drivers/phy/qualcomm/phy-qcom-qmp.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp.c +@@ -23,6 +23,7 @@ + #include + + #include "phy-qcom-qmp.h" ++#include "phy-qcom-pcie3-qmp.h" + + /* QPHY_SW_RESET bit */ + #define SW_RESET BIT(0) +@@ -676,6 +677,132 @@ static const struct qmp_phy_init_tbl ipq + QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), + }; + ++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9), ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42), ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), ++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), ++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), ++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), ++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), ++}; + static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +@@ -2187,6 +2314,36 @@ static const struct qmp_phy_cfg ipq8074_ + .pwrdn_delay_max = 1005, /* us */ + }; + ++static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), ++ .tx_tbl = ipq8074_pcie_gen3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), ++ .rx_tbl = ipq8074_pcie_gen3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), ++ .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ + static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, +@@ -3476,8 +3633,15 @@ static int phy_pipe_clk_register(struct + + init.ops = &clk_fixed_rate_ops; + +- /* controllers using QMP phys use 125MHz pipe clock interface */ +- fixed->fixed_rate = 125000000; ++ /* ++ * controllers using QMP phys use 125MHz pipe clock interface unless ++ * other frequency is specified in dts ++ */ ++ ret = of_property_read_u32(np, "clock-output-rate", ++ (u32 *)&fixed->fixed_rate); ++ if (ret) ++ fixed->fixed_rate = 125000000; ++ + fixed->hw.init = &init; + + ret = devm_clk_hw_register(qmp->dev, &fixed->hw); +@@ -3859,6 +4023,9 @@ static const struct of_device_id qcom_qm + .compatible = "qcom,ipq8074-qmp-pcie-phy", + .data = &ipq8074_pciephy_cfg, + }, { ++ .compatible = "qcom,ipq8074-qmp-pcie-gen3-phy", ++ .data = &ipq8074_pciephy_gen3_cfg, ++ }, { + .compatible = "qcom,sc7180-qmp-usb3-phy", + .data = &sc7180_usb3phy_cfg, + }, { diff --git a/target/linux/ipq807x/patches-5.10/116-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch b/target/linux/ipq807x/patches-5.10/116-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch new file mode 100644 index 000000000..fe76db641 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/116-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch @@ -0,0 +1,44 @@ +From 35df745d335bd21094f522dc9dff7eaae92114d9 Mon Sep 17 00:00:00 2001 +From: Baruch Siach +Date: Wed, 5 May 2021 12:18:29 +0300 +Subject: [PATCH] PCI: dwc: tegra: move GEN3_RELATED DBI register to common + header + +These are common dwc macros that will be used for other platforms. + +Signed-off-by: Baruch Siach +--- + drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++ + drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------ + 2 files changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -74,6 +74,12 @@ + #define PCIE_MSI_INTR0_MASK 0x82C + #define PCIE_MSI_INTR0_STATUS 0x830 + ++#define GEN3_RELATED_OFF 0x890 ++#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) ++#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) ++#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 ++#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) ++ + #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 + #define PORT_MLTI_UPCFG_SUPPORT BIT(7) + +--- a/drivers/pci/controller/dwc/pcie-tegra194.c ++++ b/drivers/pci/controller/dwc/pcie-tegra194.c +@@ -193,12 +193,6 @@ + #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8) + #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) + +-#define GEN3_RELATED_OFF 0x890 +-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) +-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) +-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 +-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) +- + #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0 + #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3 + #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0) diff --git a/target/linux/ipq807x/patches-5.10/117-PCI-qcom-add-support-for-IPQ60xx-PCIe-controller.patch b/target/linux/ipq807x/patches-5.10/117-PCI-qcom-add-support-for-IPQ60xx-PCIe-controller.patch new file mode 100644 index 000000000..382ca98dd --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/117-PCI-qcom-add-support-for-IPQ60xx-PCIe-controller.patch @@ -0,0 +1,230 @@ +From 809a720946f720dca2009bac29294992375a31b9 Mon Sep 17 00:00:00 2001 +From: Selvam Sathappan Periakaruppan +Date: Tue, 11 May 2021 21:53:08 +0200 +Subject: [PATCH] PCI: qcom: add support for IPQ60xx PCIe controller + +IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that +platform. + +The code is based on downstream Codeaurora kernel v5.4. Split out the +DBI registers access part from .init into .post_init. DBI registers are +only accessible after phy_power_on(). + +Signed-off-by: Selvam Sathappan Periakaruppan +Signed-off-by: Baruch Siach +--- + drivers/pci/controller/dwc/pcie-designware.h | 1 + + drivers/pci/controller/dwc/pcie-qcom.c | 150 +++++++++++++++++++ + 2 files changed, 151 insertions(+) + +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -76,6 +76,7 @@ + + #define GEN3_RELATED_OFF 0x890 + #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) ++#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) + #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) + #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 + #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -51,6 +51,10 @@ + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 + #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C + #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 ++#define AHB_CLK_EN BIT(0) ++#define MSTR_AXI_CLK_EN BIT(1) ++#define BYPASS BIT(4) ++ + #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 + #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 + #define PCIE20_PARF_LTSSM 0x1B0 +@@ -92,6 +96,12 @@ + #define SLV_ADDR_SPACE_SZ 0x10000000 + + #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 ++#define PCIE_CAP_CURR_DEEMPHASIS BIT(16) ++#define SPEED_GEN1 0x1 ++#define SPEED_GEN2 0x2 ++#define SPEED_GEN3 0x3 ++#define AXI_CLK_RATE 200000000 ++#define RCHNG_CLK_RATE 100000000 + + #define DEVICE_TYPE_RC 0x4 + +@@ -161,6 +171,11 @@ struct qcom_pcie_resources_2_7_0 { + struct clk *pipe_clk; + }; + ++struct qcom_pcie_resources_2_9_0 { ++ struct clk_bulk_data clks[5]; ++ struct reset_control *rst; ++}; ++ + union qcom_pcie_resources { + struct qcom_pcie_resources_1_0_0 v1_0_0; + struct qcom_pcie_resources_2_1_0 v2_1_0; +@@ -168,6 +183,7 @@ union qcom_pcie_resources { + struct qcom_pcie_resources_2_3_3 v2_3_3; + struct qcom_pcie_resources_2_4_0 v2_4_0; + struct qcom_pcie_resources_2_7_0 v2_7_0; ++ struct qcom_pcie_resources_2_9_0 v2_9_0; + }; + + struct qcom_pcie; +@@ -1252,6 +1268,130 @@ static void qcom_pcie_post_deinit_2_7_0( + clk_disable_unprepare(res->pipe_clk); + } + ++static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; ++ struct dw_pcie *pci = pcie->pci; ++ struct device *dev = pci->dev; ++ int ret; ++ ++ res->clks[0].id = "iface"; ++ res->clks[1].id = "axi_m"; ++ res->clks[2].id = "axi_s"; ++ res->clks[3].id = "axi_bridge"; ++ res->clks[4].id = "rchng"; ++ ++ ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); ++ if (ret < 0) ++ return ret; ++ ++ res->rst = devm_reset_control_array_get_exclusive(dev); ++ if (IS_ERR(res->rst)) ++ return PTR_ERR(res->rst); ++ ++ return 0; ++} ++ ++static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; ++ ++ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++} ++ ++static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; ++ struct device *dev = pcie->pci->dev; ++ int ret; ++ ++ ret = reset_control_assert(res->rst); ++ if (ret) { ++ dev_err(dev, "reset assert failed (%d)\n", ret); ++ return ret; ++ } ++ ++ usleep_range(2000, 2500); ++ ++ ret = reset_control_deassert(res->rst); ++ if (ret) { ++ dev_err(dev, "reset deassert failed (%d)\n", ret); ++ return ret; ++ } ++ ++ /* ++ * Don't have a way to see if the reset has completed. ++ * Wait for some time. ++ */ ++ usleep_range(2000, 2500); ++ ++ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ if (ret) ++ goto err_reset; ++ ++ return 0; ++ ++ /* ++ * Not checking for failure, will anyway return ++ * the original failure in 'ret'. ++ */ ++err_reset: ++ reset_control_assert(res->rst); ++ ++ return ret; ++} ++ ++static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) ++{ ++ struct dw_pcie *pci = pcie->pci; ++ u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); ++ u32 val; ++ int i; ++ ++ writel(SLV_ADDR_SPACE_SZ, ++ pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); ++ ++ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); ++ val &= ~BIT(0); ++ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); ++ ++ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); ++ ++ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); ++ writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, ++ pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); ++ writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS ++ | GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, ++ pci->dbi_base + GEN3_RELATED_OFF); ++ ++ writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS ++ | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | ++ AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, ++ pcie->parf + PCIE20_PARF_SYS_CTRL); ++ ++ writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); ++ ++ dw_pcie_dbi_ro_wr_en(pci); ++ writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); ++ ++ /* Configure PCIe link capabilities for ASPM */ ++ val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); ++ val &= ~PCI_EXP_LNKCAP_ASPMS; ++ writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); ++ ++ writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + ++ PCI_EXP_DEVCTL2); ++ ++ writel(PCIE_CAP_CURR_DEEMPHASIS | SPEED_GEN3, ++ pci->dbi_base + offset + PCI_EXP_DEVCTL2); ++ ++ for (i = 0;i < 256;i++) ++ writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N ++ + (4 * i)); ++ ++ return 0; ++} ++ + static int qcom_pcie_link_up(struct dw_pcie *pci) + { + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); +@@ -1351,6 +1491,15 @@ static const struct qcom_pcie_ops ops_2_ + .post_deinit = qcom_pcie_post_deinit_2_7_0, + }; + ++/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ ++static const struct qcom_pcie_ops ops_2_9_0 = { ++ .get_resources = qcom_pcie_get_resources_2_9_0, ++ .init = qcom_pcie_init_2_9_0, ++ .post_init = qcom_pcie_post_init_2_9_0, ++ .deinit = qcom_pcie_deinit_2_9_0, ++ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, ++}; ++ + static const struct dw_pcie_ops dw_pcie_ops = { + .link_up = qcom_pcie_link_up, + .start_link = qcom_pcie_start_link, +@@ -1457,6 +1606,7 @@ static const struct of_device_id qcom_pc + { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, + { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, + { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, ++ { .compatible = "qcom,pcie-ipq6018", .data = &ops_2_9_0 }, + { } + }; + diff --git a/target/linux/ipq807x/patches-5.10/118-arm64-dts-ipq8074-Fixup-PCIe-dts-nodes.patch b/target/linux/ipq807x/patches-5.10/118-arm64-dts-ipq8074-Fixup-PCIe-dts-nodes.patch new file mode 100644 index 000000000..0f1472fe4 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/118-arm64-dts-ipq8074-Fixup-PCIe-dts-nodes.patch @@ -0,0 +1,196 @@ +From f46a2d9ff3346809e64fbf5c1796651207b57f00 Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Wed, 29 Jul 2020 21:00:07 +0530 +Subject: [PATCH] arm64: dts: ipq8074: Fixup PCIe dts nodes + +ipq8074 PCIe nodes missing required properties to make them work. +Add these properties. + +Signed-off-by: Sivaprakash Murugesan +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 109 +++++++++++++++++--------- + 1 file changed, 74 insertions(+), 35 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -227,34 +227,66 @@ + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + }; + +- pcie_phy0: phy@86000 { +- compatible = "qcom,ipq8074-qmp-pcie-phy"; +- reg = <0x00086000 0x1000>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_PCIE0_PIPE_CLK>; +- clock-names = "pipe_clk"; +- clock-output-names = "pcie20_phy0_pipe_clk"; ++ qmp_pcie_phy0: phy@84000 { ++ compatible = "qcom,ipq8074-qmp-pcie-gen3-phy"; ++ reg = <0x00084000 0x1bc>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ clocks = <&gcc GCC_PCIE0_AUX_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>; ++ clock-names = "aux", "cfg_ahb"; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, +- <&gcc GCC_PCIE0PHY_PHY_BCR>; ++ <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; ++ + status = "disabled"; ++ pcie_phy0: lane@84200 { ++ reg = <0x84200 0x16c>, /* Serdes Tx */ ++ <0x84400 0x200>, /* Serdes Rx */ ++ <0x84800 0x4f4>; /* PCS: Lane0, COM, PCIE */ ++ #phy-cells = <0>; ++ ++ clocks = <&gcc GCC_PCIE0_PIPE_CLK>; ++ clock-names = "pipe0"; ++ clock-output-names = "gcc_pcie0_pipe_clk_src"; ++ clock-output-rate = <250000000>; ++ #clock-cells = <0>; ++ }; + }; + +- pcie_phy1: phy@8e000 { ++ qmp_pcie_phy1: phy@8e000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; +- reg = <0x0008e000 0x1000>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_PCIE1_PIPE_CLK>; +- clock-names = "pipe_clk"; +- clock-output-names = "pcie20_phy1_pipe_clk"; ++ reg = <0x8e000 0x1c4>; /* Serdes PLL */ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ clocks = <&gcc GCC_PCIE1_AUX_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>; ++ clock-names = "aux", "cfg_ahb"; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, +- <&gcc GCC_PCIE1PHY_PHY_BCR>; ++ <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", + "common"; ++ + status = "disabled"; ++ pcie_phy1: lane@8e200 { ++ reg = <0x8e200 0x130>, /* Serdes Tx */ ++ <0x8e400 0x200>, /* Serdes Rx */ ++ <0x8e800 0x1f8>; /* PCS */ ++ #phy-cells = <0>; ++ ++ clocks = <&gcc GCC_PCIE1_PIPE_CLK>; ++ clock-names = "pipe0"; ++ clock-output-names = "gcc_pcie1_pipe_clk_src"; ++ clock-output-rate = <125000000>; ++ #clock-cells = <0>; ++ }; + }; + + mdio: mdio@90000 { +@@ -671,10 +703,10 @@ + + pcie1: pci@10000000 { + compatible = "qcom,pcie-ipq8074"; +- reg = <0x10000000 0xf1d +- 0x10000f20 0xa8 +- 0x00088000 0x2000 +- 0x10100000 0x1000>; ++ reg = <0x10000000 0xf1d>, ++ <0x10000f20 0xa8>, ++ <0x00088000 0x2000>, ++ <0x10100000 0x1000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <1>; +@@ -687,9 +719,9 @@ + phy-names = "pciephy"; + + ranges = <0x81000000 0 0x10200000 0x10200000 +- 0 0x100000 /* downstream I/O */ +- 0x82000000 0 0x10300000 0x10300000 +- 0 0xd00000>; /* non-prefetchable memory */ ++ 0 0x100000>, /* downstream I/O */ ++ <0x82000000 0 0x10220000 0x10220000 ++ 0 0xfde0000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi"; +@@ -732,12 +764,13 @@ + }; + + pcie0: pci@20000000 { +- compatible = "qcom,pcie-ipq8074"; +- reg = <0x20000000 0xf1d +- 0x20000f20 0xa8 +- 0x00080000 0x2000 +- 0x20100000 0x1000>; +- reg-names = "dbi", "elbi", "parf", "config"; ++ compatible = "qcom,pcie-ipq8074-gen3"; ++ reg = <0x20000000 0xf1d>, ++ <0x20000f20 0xa8>, ++ <0x20001000 0x1000>, ++ <0x00080000 0x4000>, ++ <0x20100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; +@@ -749,9 +782,9 @@ + phy-names = "pciephy"; + + ranges = <0x81000000 0 0x20200000 0x20200000 +- 0 0x100000 /* downstream I/O */ +- 0x82000000 0 0x20300000 0x20300000 +- 0 0xd00000>; /* non-prefetchable memory */ ++ 0 0x100000>, /* downstream I/O */ ++ <0x82000000 0 0x20220000 0x20220000 ++ 0 0xfde0000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi"; +@@ -770,27 +803,33 @@ + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, +- <&gcc GCC_PCIE0_AUX_CLK>; ++ <&gcc GCC_PCIE0_AUX_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE0_RCHNG_CLK>; + + clock-names = "iface", + "axi_m", + "axi_s", + "ahb", +- "aux"; ++ "aux", ++ "axi_bridge", ++ "rchng"; + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, +- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; ++ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", +- "axi_m_sticky"; ++ "axi_m_sticky", ++ "axi_s_sticky"; + status = "disabled"; + }; + diff --git a/target/linux/ipq807x/patches-5.10/119-qcom-backport-register-define.patch b/target/linux/ipq807x/patches-5.10/119-qcom-backport-register-define.patch new file mode 100644 index 000000000..b1e5c82f3 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/119-qcom-backport-register-define.patch @@ -0,0 +1,26 @@ +From 5d3f9ed5a9eb305a2531015cc65200d48be5dbf4 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 11 May 2021 22:21:57 +0200 +Subject: [PATCH 1/2] PCI: qcom: backport register define + +This is used by the pending IPQ6018 PCI support which +uses the same Gen3 IP and the one we are reusing for +IPQ8074. + +Without it compilation will break. + +Signed-off-by: Robert Marko +--- + drivers/pci/controller/dwc/pcie-qcom.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -61,6 +61,7 @@ + #define PCIE20_PARF_SID_OFFSET 0x234 + #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C + #define PCIE20_PARF_DEVICE_TYPE 0x1000 ++#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 + + #define PCIE20_ELBI_SYS_CTRL 0x04 + #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) diff --git a/target/linux/ipq807x/patches-5.10/120-PCI-qcom-Add-IPQ8074-PCIe-Gen3-support.patch b/target/linux/ipq807x/patches-5.10/120-PCI-qcom-Add-IPQ8074-PCIe-Gen3-support.patch new file mode 100644 index 000000000..0cb6aa89c --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/120-PCI-qcom-Add-IPQ8074-PCIe-Gen3-support.patch @@ -0,0 +1,48 @@ +From 9467e9860e72d7351b24dc6d77f0e9fe141ce166 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 26 May 2021 16:06:32 +0200 +Subject: [PATCH] PCI: qcom: Add IPQ8074 PCIe Gen3 support + +IPQ6018 uses the same v2.9.0 IP for the Gen3 PCIe +controller. + +So, lets reuse that and add clocks that the IPQ6018 +patch missed. + +Signed-off-by: Robert Marko +--- + drivers/pci/controller/dwc/pcie-qcom.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -173,7 +173,7 @@ struct qcom_pcie_resources_2_7_0 { + }; + + struct qcom_pcie_resources_2_9_0 { +- struct clk_bulk_data clks[5]; ++ struct clk_bulk_data clks[7]; + struct reset_control *rst; + }; + +@@ -1279,8 +1279,10 @@ static int qcom_pcie_get_resources_2_9_0 + res->clks[0].id = "iface"; + res->clks[1].id = "axi_m"; + res->clks[2].id = "axi_s"; +- res->clks[3].id = "axi_bridge"; +- res->clks[4].id = "rchng"; ++ res->clks[3].id = "ahb"; ++ res->clks[4].id = "aux"; ++ res->clks[5].id = "axi_bridge"; ++ res->clks[6].id = "rchng"; + + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) +@@ -1608,6 +1610,7 @@ static const struct of_device_id qcom_pc + { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, + { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, + { .compatible = "qcom,pcie-ipq6018", .data = &ops_2_9_0 }, ++ { .compatible = "qcom,pcie-ipq8074-gen3", .data = &ops_2_9_0 }, + { } + }; + diff --git a/target/linux/ipq807x/patches-5.10/122-arm64-uaccess-include-scheduler.h.patch b/target/linux/ipq807x/patches-5.10/122-arm64-uaccess-include-scheduler.h.patch new file mode 100644 index 000000000..40244b080 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/122-arm64-uaccess-include-scheduler.h.patch @@ -0,0 +1,27 @@ +From 5fcad0d86d985b068eb97e55b55f7be87cd1b008 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 17:01:29 +0200 +Subject: [PATCH] arm64: uaccess: include scheduler.h + +Qualcomm SSDK exposed a bug in which the uaccess is +using a struct and header definition that are not +included. + +So, simply: #include to fix it. + +Signed-off-by: Robert Marko +--- + arch/arm64/include/asm/uaccess.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/include/asm/uaccess.h ++++ b/arch/arm64/include/asm/uaccess.h +@@ -24,6 +24,8 @@ + #include + #include + ++#include ++ + #define get_fs() (current_thread_info()->addr_limit) + + static inline void set_fs(mm_segment_t fs) diff --git a/target/linux/ipq807x/patches-5.10/123-arm64-dts-ipq8074-add-networking-nodes.patch b/target/linux/ipq807x/patches-5.10/123-arm64-dts-ipq8074-add-networking-nodes.patch new file mode 100644 index 000000000..d1b15b748 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/123-arm64-dts-ipq8074-add-networking-nodes.patch @@ -0,0 +1,170 @@ +From f581e7b004d0d997acc1f0fa5b2c454f90f0b2de Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 18:49:30 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add networking nodes + +Add networking nodes required for SSDK and NSS-DP. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 150 ++++++++++++++++++++++++++ + 1 file changed, 150 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -899,5 +899,155 @@ + }; + }; + }; ++ ++ ess_switch: ess-switch@3a000000 { ++ compatible = "qcom,ess-switch-ipq807x"; ++ reg = <0x3a000000 0x1000000>; ++ switch_access_mode = "local bus"; ++ switch_cpu_bmp = <0x1>; /* cpu port bitmap */ ++ switch_inner_bmp = <0x80>; /*inner port bitmap*/ ++ mdio-bus = <&mdio>; ++ clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, ++ <&gcc GCC_CMN_12GPLL_SYS_CLK>, ++ <&gcc GCC_UNIPHY0_AHB_CLK>, ++ <&gcc GCC_UNIPHY0_SYS_CLK>, ++ <&gcc GCC_UNIPHY1_AHB_CLK>, ++ <&gcc GCC_UNIPHY1_SYS_CLK>, ++ <&gcc GCC_UNIPHY2_AHB_CLK>, ++ <&gcc GCC_UNIPHY2_SYS_CLK>, ++ <&gcc GCC_PORT1_MAC_CLK>, ++ <&gcc GCC_PORT2_MAC_CLK>, ++ <&gcc GCC_PORT3_MAC_CLK>, ++ <&gcc GCC_PORT4_MAC_CLK>, ++ <&gcc GCC_PORT5_MAC_CLK>, ++ <&gcc GCC_PORT6_MAC_CLK>, ++ <&gcc GCC_NSS_PPE_CLK>, ++ <&gcc GCC_NSS_PPE_CFG_CLK>, ++ <&gcc GCC_NSSNOC_PPE_CLK>, ++ <&gcc GCC_NSSNOC_PPE_CFG_CLK>, ++ <&gcc GCC_NSS_EDMA_CLK>, ++ <&gcc GCC_NSS_EDMA_CFG_CLK>, ++ <&gcc GCC_NSS_PPE_IPE_CLK>, ++ <&gcc GCC_NSS_PPE_BTQ_CLK>, ++ <&gcc GCC_NSS_NOC_CLK>, ++ <&gcc GCC_NSSNOC_SNOC_CLK>, ++ <&gcc GCC_MEM_NOC_NSS_AXI_CLK>, ++ <&gcc GCC_NSS_CRYPTO_CLK>, ++ <&gcc GCC_NSS_IMEM_CLK>, ++ <&gcc GCC_NSS_PTP_REF_CLK>, ++ <&gcc GCC_NSS_PORT1_RX_CLK>, ++ <&gcc GCC_NSS_PORT1_TX_CLK>, ++ <&gcc GCC_NSS_PORT2_RX_CLK>, ++ <&gcc GCC_NSS_PORT2_TX_CLK>, ++ <&gcc GCC_NSS_PORT3_RX_CLK>, ++ <&gcc GCC_NSS_PORT3_TX_CLK>, ++ <&gcc GCC_NSS_PORT4_RX_CLK>, ++ <&gcc GCC_NSS_PORT4_TX_CLK>, ++ <&gcc GCC_NSS_PORT5_RX_CLK>, ++ <&gcc GCC_NSS_PORT5_TX_CLK>, ++ <&gcc GCC_NSS_PORT6_RX_CLK>, ++ <&gcc GCC_NSS_PORT6_TX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT1_RX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT1_TX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT2_RX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT2_TX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT3_RX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT3_TX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT4_RX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT4_TX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT5_RX_CLK>, ++ <&gcc GCC_UNIPHY0_PORT5_TX_CLK>, ++ <&gcc GCC_UNIPHY1_PORT5_RX_CLK>, ++ <&gcc GCC_UNIPHY1_PORT5_TX_CLK>, ++ <&gcc GCC_UNIPHY2_PORT6_RX_CLK>, ++ <&gcc GCC_UNIPHY2_PORT6_TX_CLK>, ++ <&gcc NSS_PORT5_RX_CLK_SRC>, ++ <&gcc NSS_PORT5_TX_CLK_SRC>; ++ clock-names = "cmn_ahb_clk", "cmn_sys_clk", ++ "uniphy0_ahb_clk", "uniphy0_sys_clk", ++ "uniphy1_ahb_clk", "uniphy1_sys_clk", ++ "uniphy2_ahb_clk", "uniphy2_sys_clk", ++ "port1_mac_clk", "port2_mac_clk", ++ "port3_mac_clk", "port4_mac_clk", ++ "port5_mac_clk", "port6_mac_clk", ++ "nss_ppe_clk", "nss_ppe_cfg_clk", ++ "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk", ++ "nss_edma_clk", "nss_edma_cfg_clk", ++ "nss_ppe_ipe_clk", "nss_ppe_btq_clk", ++ "gcc_nss_noc_clk", ++ "gcc_nssnoc_snoc_clk", ++ "gcc_mem_noc_nss_axi_clk", ++ "gcc_nss_crypto_clk", ++ "gcc_nss_imem_clk", ++ "gcc_nss_ptp_ref_clk", ++ "nss_port1_rx_clk", "nss_port1_tx_clk", ++ "nss_port2_rx_clk", "nss_port2_tx_clk", ++ "nss_port3_rx_clk", "nss_port3_tx_clk", ++ "nss_port4_rx_clk", "nss_port4_tx_clk", ++ "nss_port5_rx_clk", "nss_port5_tx_clk", ++ "nss_port6_rx_clk", "nss_port6_tx_clk", ++ "uniphy0_port1_rx_clk", ++ "uniphy0_port1_tx_clk", ++ "uniphy0_port2_rx_clk", ++ "uniphy0_port2_tx_clk", ++ "uniphy0_port3_rx_clk", ++ "uniphy0_port3_tx_clk", ++ "uniphy0_port4_rx_clk", ++ "uniphy0_port4_tx_clk", ++ "uniphy0_port5_rx_clk", ++ "uniphy0_port5_tx_clk", ++ "uniphy1_port5_rx_clk", ++ "uniphy1_port5_tx_clk", ++ "uniphy2_port6_rx_clk", ++ "uniphy2_port6_tx_clk", ++ "nss_port5_rx_clk_src", ++ "nss_port5_tx_clk_src"; ++ resets = <&gcc GCC_PPE_FULL_RESET>, ++ <&gcc GCC_UNIPHY0_SOFT_RESET>, ++ <&gcc GCC_UNIPHY0_XPCS_RESET>, ++ <&gcc GCC_UNIPHY1_SOFT_RESET>, ++ <&gcc GCC_UNIPHY1_XPCS_RESET>, ++ <&gcc GCC_UNIPHY2_SOFT_RESET>, ++ <&gcc GCC_UNIPHY2_XPCS_RESET>, ++ <&gcc GCC_NSSPORT1_RESET>, ++ <&gcc GCC_NSSPORT2_RESET>, ++ <&gcc GCC_NSSPORT3_RESET>, ++ <&gcc GCC_NSSPORT4_RESET>, ++ <&gcc GCC_NSSPORT5_RESET>, ++ <&gcc GCC_NSSPORT6_RESET>; ++ reset-names = "ppe_rst", "uniphy0_soft_rst", ++ "uniphy0_xpcs_rst", "uniphy1_soft_rst", ++ "uniphy1_xpcs_rst", "uniphy2_soft_rst", ++ "uniphy2_xpcs_rst", "nss_port1_rst", ++ "nss_port2_rst", "nss_port3_rst", ++ "nss_port4_rst", "nss_port5_rst", ++ "nss_port6_rst"; ++ }; ++ ++ ess-uniphy@7a00000 { ++ compatible = "qcom,ess-uniphy"; ++ reg = <0x7a00000 0x30000>; ++ uniphy_access_mode = "local bus"; ++ }; ++ ++ edma@3ab00000 { ++ compatible = "qcom,edma"; ++ reg = <0x3ab00000 0x76900>; ++ reg-names = "edma-reg-base"; ++ qcom,txdesc-ring-start = <23>; ++ qcom,txdesc-rings = <1>; ++ qcom,txcmpl-ring-start = <7>; ++ qcom,txcmpl-rings = <1>; ++ qcom,rxfill-ring-start = <7>; ++ qcom,rxfill-rings = <1>; ++ qcom,rxdesc-ring-start = <15>; ++ qcom,rxdesc-rings = <1>; ++ interrupts = , ++ , ++ , ++ ; ++ resets = <&gcc GCC_EDMA_HW_RESET>; ++ reset-names = "edma_rst"; ++ }; + }; + }; diff --git a/target/linux/ipq807x/patches-5.10/124-clk-ipq-support-for-resetting-multiple-bits.patch b/target/linux/ipq807x/patches-5.10/124-clk-ipq-support-for-resetting-multiple-bits.patch new file mode 100644 index 000000000..4819a6782 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/124-clk-ipq-support-for-resetting-multiple-bits.patch @@ -0,0 +1,56 @@ +From 027818c51e6732f8a2f7986515264cebaf9a1704 Mon Sep 17 00:00:00 2001 +From: Rajkumar Ayyasamy +Date: Wed, 18 Mar 2020 17:08:11 +0530 +Subject: [PATCH 1/8] clk: ipq: support for resetting multiple bits + +Current reset structure takes only one reset bit and +calculates the bitmask in its reset operation. Some of the +reset registers contains multiple bits in which each bit +will be associated with subsystem reset inside the block. To +reset properly the complete block, all the subsystem reset +should be triggered at same time i.e the register write +should go in one AHB write. + +This patch adds the support for giving the complete bitmask +in reset structure and reset operation will use this bitmask +for all reset operations. + +Change-Id: Ief49f8746624a0fc1e067d815725ae7c254c2c6f +Signed-off-by: Abhishek Sahu +(cherry picked from commit ef555fc1cffa6e823a9d929711cacae0821b35ec) +Signed-off-by: Rajkumar Ayyasamy +--- + drivers/clk/qcom/reset.c | 4 ++-- + drivers/clk/qcom/reset.h | 1 + + 2 files changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/clk/qcom/reset.c ++++ b/drivers/clk/qcom/reset.c +@@ -28,7 +28,7 @@ qcom_reset_assert(struct reset_controlle + + rst = to_qcom_reset_controller(rcdev); + map = &rst->reset_map[id]; +- mask = BIT(map->bit); ++ mask = map->bitmask ? map->bitmask : BIT(map->bit); + + return regmap_update_bits(rst->regmap, map->reg, mask, mask); + } +@@ -42,7 +42,7 @@ qcom_reset_deassert(struct reset_control + + rst = to_qcom_reset_controller(rcdev); + map = &rst->reset_map[id]; +- mask = BIT(map->bit); ++ mask = map->bitmask ? map->bitmask : BIT(map->bit); + + return regmap_update_bits(rst->regmap, map->reg, mask, 0); + } +--- a/drivers/clk/qcom/reset.h ++++ b/drivers/clk/qcom/reset.h +@@ -11,6 +11,7 @@ + struct qcom_reset_map { + unsigned int reg; + u8 bit; ++ u32 bitmask; + }; + + struct regmap; diff --git a/target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch b/target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch new file mode 100644 index 000000000..ff3c7d048 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch @@ -0,0 +1,212 @@ +From 4f579facd45c39f8f8b9993570944f4d83a95955 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Wed, 5 Feb 2020 10:13:01 +0530 +Subject: [PATCH 2/8] ipq8074: gcc: Added support for NSS clocks + +Change-Id: I446e84dbc3498618425677811a73124b99b5c0ad +Signed-off-by: Praveenkumar I +Signed-off-by: Rajkumar Ayyasamy +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++ + drivers/clk/qcom/gcc-ipq8074.c | 68 +++++++++++++++++++- + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + + 3 files changed, 80 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -1049,5 +1049,17 @@ + resets = <&gcc GCC_EDMA_HW_RESET>; + reset-names = "edma_rst"; + }; ++ ++ bias_pll_cc_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <300000000>; ++ #clock-cells = <0>; ++ }; ++ ++ bias_pll_nss_noc_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <416500000>; ++ #clock-cells = <0>; ++ }; + }; + }; +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -3174,6 +3174,24 @@ static struct clk_branch gcc_nss_ptp_ref + }, + }; + ++static struct clk_branch gcc_crypto_ppe_clk = { ++ .halt_reg = 0x68310, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x68310, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_crypto_ppe_clk", ++ .parent_names = (const char *[]){ ++ "nss_ppe_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ + static struct clk_branch gcc_nssnoc_ce_apb_clk = { + .halt_reg = 0x6830c, + .clkr = { +@@ -3346,6 +3364,7 @@ static struct clk_branch gcc_nssnoc_ubi1 + + static struct clk_branch gcc_ubi0_ahb_clk = { + .halt_reg = 0x6820c, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x6820c, + .enable_mask = BIT(0), +@@ -3363,6 +3382,7 @@ static struct clk_branch gcc_ubi0_ahb_cl + + static struct clk_branch gcc_ubi0_axi_clk = { + .halt_reg = 0x68200, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68200, + .enable_mask = BIT(0), +@@ -3380,6 +3400,7 @@ static struct clk_branch gcc_ubi0_axi_cl + + static struct clk_branch gcc_ubi0_nc_axi_clk = { + .halt_reg = 0x68204, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68204, + .enable_mask = BIT(0), +@@ -3397,6 +3418,7 @@ static struct clk_branch gcc_ubi0_nc_axi + + static struct clk_branch gcc_ubi0_core_clk = { + .halt_reg = 0x68210, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68210, + .enable_mask = BIT(0), +@@ -3414,6 +3436,7 @@ static struct clk_branch gcc_ubi0_core_c + + static struct clk_branch gcc_ubi0_mpt_clk = { + .halt_reg = 0x68208, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68208, + .enable_mask = BIT(0), +@@ -3431,6 +3454,7 @@ static struct clk_branch gcc_ubi0_mpt_cl + + static struct clk_branch gcc_ubi1_ahb_clk = { + .halt_reg = 0x6822c, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x6822c, + .enable_mask = BIT(0), +@@ -3448,6 +3472,7 @@ static struct clk_branch gcc_ubi1_ahb_cl + + static struct clk_branch gcc_ubi1_axi_clk = { + .halt_reg = 0x68220, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68220, + .enable_mask = BIT(0), +@@ -3465,6 +3490,7 @@ static struct clk_branch gcc_ubi1_axi_cl + + static struct clk_branch gcc_ubi1_nc_axi_clk = { + .halt_reg = 0x68224, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68224, + .enable_mask = BIT(0), +@@ -3482,6 +3508,7 @@ static struct clk_branch gcc_ubi1_nc_axi + + static struct clk_branch gcc_ubi1_core_clk = { + .halt_reg = 0x68230, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68230, + .enable_mask = BIT(0), +@@ -3499,6 +3526,7 @@ static struct clk_branch gcc_ubi1_core_c + + static struct clk_branch gcc_ubi1_mpt_clk = { + .halt_reg = 0x68228, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68228, + .enable_mask = BIT(0), +@@ -4381,6 +4409,33 @@ static struct clk_hw *gcc_ipq8074_hws[] + &nss_ppe_cdiv_clk_src.hw, + }; + ++static const struct alpha_pll_config ubi32_pll_config = { ++ .l = 0x4e, ++ .config_ctl_val = 0x200d4aa8, ++ .config_ctl_hi_val = 0x3c2, ++ .main_output_mask = BIT(0), ++ .aux_output_mask = BIT(1), ++ .pre_div_val = 0x0, ++ .pre_div_mask = BIT(12), ++ .post_div_val = 0x0, ++ .post_div_mask = GENMASK(9, 8), ++}; ++ ++static const struct alpha_pll_config nss_crypto_pll_config = { ++ .l = 0x3e, ++ .alpha = 0x0, ++ .alpha_hi = 0x80, ++ .config_ctl_val = 0x4001055b, ++ .main_output_mask = BIT(0), ++ .pre_div_val = 0x0, ++ .pre_div_mask = GENMASK(14, 12), ++ .post_div_val = 0x1 << 8, ++ .post_div_mask = GENMASK(11, 8), ++ .vco_mask = GENMASK(21, 20), ++ .vco_val = 0x0, ++ .alpha_en_mask = BIT(24), ++}; ++ + static struct clk_regmap *gcc_ipq8074_clks[] = { + [GPLL0_MAIN] = &gpll0_main.clkr, + [GPLL0] = &gpll0.clkr, +@@ -4562,6 +4617,7 @@ static struct clk_regmap *gcc_ipq8074_cl + [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, + [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, + [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, ++ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, + [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, + [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, + [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, +@@ -4773,7 +4829,17 @@ static const struct qcom_cc_desc gcc_ipq + + static int gcc_ipq8074_probe(struct platform_device *pdev) + { +- return qcom_cc_probe(pdev, &gcc_ipq8074_desc); ++ struct regmap *regmap; ++ ++ regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); ++ clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, ++ &nss_crypto_pll_config); ++ ++ return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap); + } + + static struct platform_driver gcc_ipq8074_driver = { +--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +@@ -233,6 +233,7 @@ + #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 + #define GCC_PCIE0_RCHNG_CLK_SRC 225 + #define GCC_PCIE0_RCHNG_CLK 226 ++#define GCC_CRYPTO_PPE_CLK 227 + + #define GCC_BLSP1_BCR 0 + #define GCC_BLSP1_QUP1_BCR 1 diff --git a/target/linux/ipq807x/patches-5.10/126-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch b/target/linux/ipq807x/patches-5.10/126-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch new file mode 100644 index 000000000..6fc058640 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/126-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch @@ -0,0 +1,352 @@ +From 6504bc9edeb1a2a54d813f4bb5d0267e7bf827f9 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Thu, 6 Feb 2020 17:35:42 +0530 +Subject: [PATCH 4/8] clk: ipq8074: Support added for necessary clocks and + reset + +Change-Id: I21a76a44185f766e9b6dcba274392ea8e599718b +Signed-off-by: Praveenkumar I +Signed-off-by: Rajkumar Ayyasamy +--- + drivers/clk/qcom/gcc-ipq8074.c | 238 ++++++++++++++++++- + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 35 ++- + 2 files changed, 258 insertions(+), 15 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -396,6 +396,22 @@ static const struct parent_map gcc_xo_gp + { P_SLEEP_CLK, 6 }, + }; + ++static const char * const gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = { ++ "xo", ++ "gpll4", ++ "gpll0", ++ "gpll6", ++ "gpll0_out_main_div2", ++}; ++ ++static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL4, 1 }, ++ { P_GPLL0, 2 }, ++ { P_GPLL6, 3 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ + static struct clk_alpha_pll gpll0_main = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], +@@ -962,6 +978,12 @@ static const struct freq_tbl ftbl_pcie_a + { } + }; + ++struct freq_tbl ftbl_pcie_rchng_clk_src[] = { ++ F(19200000, P_XO, 1, 0, 0), ++ F(100000000, P_GPLL0, 8, 0, 0), ++ { } ++}; ++ + static struct clk_rcg2 pcie0_axi_clk_src = { + .cmd_rcgr = 0x75054, + .freq_tbl = ftbl_pcie_axi_clk_src, +@@ -2013,6 +2035,78 @@ static struct clk_rcg2 gp3_clk_src = { + }, + }; + ++struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { ++ F(160000000, P_GPLL0_DIV2, 2.5, 0, 0), ++ F(320000000, P_GPLL0, 2.5, 0, 0), ++ F(600000000, P_GPLL6, 2, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 qdss_tsctr_clk_src = { ++ .cmd_rcgr = 0x29064, ++ .freq_tbl = ftbl_qdss_tsctr_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "qdss_tsctr_clk_src", ++ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2, ++ .num_parents = 5, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_fixed_factor qdss_dap_sync_clk_src = { ++ .mult = 1, ++ .div = 4, ++ .hw.init = &(struct clk_init_data){ ++ .name = "qdss_dap_sync_clk_src", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++struct freq_tbl ftbl_qdss_at_clk_src[] = { ++ F(66670000, P_GPLL0_DIV2, 6, 0, 0), ++ F(240000000, P_GPLL6, 6, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 qdss_at_clk_src = { ++ .cmd_rcgr = 0x2900c, ++ .freq_tbl = ftbl_qdss_at_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "qdss_at_clk_src", ++ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2, ++ .num_parents = 5, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++ ++struct freq_tbl ftbl_adss_pwm_clk_src[] = { ++ F(19200000, P_XO, 1, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 adss_pwm_clk_src = { ++ .cmd_rcgr = 0x1c008, ++ .freq_tbl = ftbl_adss_pwm_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "adss_pwm_clk_src", ++ .parent_names = gcc_xo_gpll0, ++ .num_parents = 2, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ + static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x01008, + .clkr = { +@@ -4344,13 +4438,7 @@ static struct clk_branch gcc_gp3_clk = { + }, + }; + +-static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { +- F(19200000, P_XO, 1, 0, 0), +- F(100000000, P_GPLL0, 8, 0, 0), +- { } +-}; +- +-static struct clk_rcg2 pcie0_rchng_clk_src = { ++struct clk_rcg2 pcie0_rchng_clk_src = { + .cmd_rcgr = 0x75070, + .freq_tbl = ftbl_pcie_rchng_clk_src, + .hid_width = 5, +@@ -4399,6 +4487,114 @@ static struct clk_branch gcc_pcie0_axi_s + }, + }; + ++static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = { ++ .halt_reg = 0x4700c, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x4700c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_bus_timeout2_ahb_clk", ++ .parent_names = (const char *[]){ ++ "usb0_master_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = { ++ .halt_reg = 0x47014, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x47014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_bus_timeout3_ahb_clk", ++ .parent_names = (const char *[]){ ++ "usb1_master_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_dcc_clk = { ++ .halt_reg = 0x77004, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x77004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_dcc_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_at_clk = { ++ .halt_reg = 0x29024, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x29024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_at_clk", ++ .parent_names = (const char *[]){ ++ "qdss_at_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_dap_clk = { ++ .halt_reg = 0x29084, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x29084, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_dap_clk", ++ .parent_names = (const char *[]){ ++ "qdss_dap_sync_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_adss_pwm_clk = { ++ .halt_reg = 0x1c020, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x1c020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_adss_pwm_clk", ++ .parent_names = (const char *[]){ ++ "adss_pwm_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ + static struct clk_hw *gcc_ipq8074_hws[] = { + &gpll0_out_main_div2.hw, + &gpll6_out_main_div2.hw, +@@ -4407,6 +4603,7 @@ static struct clk_hw *gcc_ipq8074_hws[] + &gcc_xo_div4_clk_src.hw, + &nss_noc_clk_src.hw, + &nss_ppe_cdiv_clk_src.hw, ++ &qdss_dap_sync_clk_src.hw, + }; + + static const struct alpha_pll_config ubi32_pll_config = { +@@ -4665,6 +4862,15 @@ static struct clk_regmap *gcc_ipq8074_cl + [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, + [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, + [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, ++ [GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr, ++ [GCC_SNOC_BUS_TIMEOUT3_AHB_CLK] = &gcc_snoc_bus_timeout3_ahb_clk.clkr, ++ [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, ++ [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, ++ [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, ++ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, ++ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, ++ [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr, ++ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, + }; + + static const struct qcom_reset_map gcc_ipq8074_resets[] = { +@@ -4801,6 +5007,20 @@ static const struct qcom_reset_map gcc_i + [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, + [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, + [GCC_WCSSAON_RESET] = { 0x59010, 0 }, ++ [GCC_PPE_FULL_RESET] = { 0x68014, 0, 0xf0000}, ++ [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0, 0x3ff2}, ++ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 }, ++ [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0, 0x32}, ++ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 }, ++ [GCC_UNIPHY2_SOFT_RESET] = { 0x56204, 0, 0x32}, ++ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 }, ++ [GCC_EDMA_HW_RESET] = { 0x68014, 0, 0x300000}, ++ [GCC_NSSPORT1_RESET] = { 0x68014, 0, 0x1000003}, ++ [GCC_NSSPORT2_RESET] = { 0x68014, 0, 0x200000c}, ++ [GCC_NSSPORT3_RESET] = { 0x68014, 0, 0x4000030}, ++ [GCC_NSSPORT4_RESET] = { 0x68014, 0, 0x8000300}, ++ [GCC_NSSPORT5_RESET] = { 0x68014, 0, 0x10000c00}, ++ [GCC_NSSPORT6_RESET] = { 0x68014, 0, 0x20003000}, + }; + + static const struct of_device_id gcc_ipq8074_match_table[] = { +--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +@@ -230,10 +230,19 @@ + #define GCC_GP1_CLK 221 + #define GCC_GP2_CLK 222 + #define GCC_GP3_CLK 223 +-#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 +-#define GCC_PCIE0_RCHNG_CLK_SRC 225 +-#define GCC_PCIE0_RCHNG_CLK 226 +-#define GCC_CRYPTO_PPE_CLK 227 ++#define GCC_CRYPTO_PPE_CLK 224 ++#define GCC_PCIE0_RCHNG_CLK_SRC 225 ++#define GCC_PCIE0_RCHNG_CLK 226 ++#define GCC_PCIE0_AXI_S_BRIDGE_CLK 227 ++#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 228 ++#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 229 ++#define GCC_DCC_CLK 230 ++#define ADSS_PWM_CLK_SRC 231 ++#define GCC_ADSS_PWM_CLK 232 ++#define QDSS_TSCTR_CLK_SRC 233 ++#define QDSS_AT_CLK_SRC 234 ++#define GCC_QDSS_AT_CLK 235 ++#define GCC_QDSS_DAP_CLK 236 + + #define GCC_BLSP1_BCR 0 + #define GCC_BLSP1_QUP1_BCR 1 +@@ -368,5 +377,19 @@ + #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 + #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 + #define GCC_WCSSAON_RESET 132 ++#define GCC_PPE_FULL_RESET 133 ++#define GCC_UNIPHY0_SOFT_RESET 134 ++#define GCC_UNIPHY0_XPCS_RESET 135 ++#define GCC_UNIPHY1_SOFT_RESET 136 ++#define GCC_UNIPHY1_XPCS_RESET 137 ++#define GCC_UNIPHY2_SOFT_RESET 138 ++#define GCC_UNIPHY2_XPCS_RESET 139 ++#define GCC_EDMA_HW_RESET 140 ++#define GCC_NSSPORT1_RESET 141 ++#define GCC_NSSPORT2_RESET 142 ++#define GCC_NSSPORT3_RESET 143 ++#define GCC_NSSPORT4_RESET 144 ++#define GCC_NSSPORT5_RESET 145 ++#define GCC_NSSPORT6_RESET 146 + + #endif diff --git a/target/linux/ipq807x/patches-5.10/127-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch b/target/linux/ipq807x/patches-5.10/127-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch new file mode 100644 index 000000000..978aa4e66 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/127-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch @@ -0,0 +1,44 @@ +From 462aa0c53397ec5bf78e3e7f68aa8a3ca300f4ba Mon Sep 17 00:00:00 2001 +From: Selvam Sathappan Periakaruppan +Date: Tue, 24 Mar 2020 19:09:38 +0530 +Subject: [PATCH 5/8] clk: qcom: ipq8074: Fix gcc_snoc_bus_timeout_ahb_clk + offset + +By default, the ipq8074 V2 clks are provided in the gcc driver. +Updating the gcc_snoc_bus_timeout_ahb_clk offsets also as needed +in ipq8074 V2. + +Change-Id: I5a6e98d002f5c3354a804e55dd9ebb1f83f7f974 +Signed-off-by: Selvam Sathappan Periakaruppan +--- + drivers/clk/qcom/gcc-ipq8074.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -4488,10 +4488,10 @@ static struct clk_branch gcc_pcie0_axi_s + }; + + static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = { +- .halt_reg = 0x4700c, ++ .halt_reg = 0x47014, + .halt_bit = 31, + .clkr = { +- .enable_reg = 0x4700c, ++ .enable_reg = 0x47014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_snoc_bus_timeout2_ahb_clk", +@@ -4506,10 +4506,10 @@ static struct clk_branch gcc_snoc_bus_ti + }; + + static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = { +- .halt_reg = 0x47014, ++ .halt_reg = 0x4701C, + .halt_bit = 31, + .clkr = { +- .enable_reg = 0x47014, ++ .enable_reg = 0x4701C, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_snoc_bus_timeout3_ahb_clk", diff --git a/target/linux/ipq807x/patches-5.10/128-qcom-clk-ipq8074-fix-port-6-clock-issue-for-1G.patch b/target/linux/ipq807x/patches-5.10/128-qcom-clk-ipq8074-fix-port-6-clock-issue-for-1G.patch new file mode 100644 index 000000000..5f648d341 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/128-qcom-clk-ipq8074-fix-port-6-clock-issue-for-1G.patch @@ -0,0 +1,35 @@ +From d4f5b0945dd4ec3638009fca0b4d13098155dca9 Mon Sep 17 00:00:00 2001 +From: zhongjia +Date: Thu, 13 Aug 2020 00:38:46 +0800 +Subject: [PATCH 6/8] qcom: clk: ipq8074: fix port 6 clock issue for 1G + +Change-Id: I279321a33f77404f75d4c60c607892df36fb25be +Signed-off-by: zhongjia +--- + drivers/clk/qcom/gcc-ipq8074.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -1889,8 +1889,10 @@ static struct clk_regmap_div nss_port5_t + + static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), ++ F(25000000, P_UNIPHY2_RX, 5, 0, 0), + F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), + F(78125000, P_UNIPHY2_RX, 4, 0, 0), ++ F(125000000, P_UNIPHY2_RX, 1, 0, 0), + F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), + F(156250000, P_UNIPHY2_RX, 2, 0, 0), + F(312500000, P_UNIPHY2_RX, 1, 0, 0), +@@ -1929,8 +1931,10 @@ static struct clk_regmap_div nss_port6_r + + static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), ++ F(25000000, P_UNIPHY2_TX, 5, 0, 0), + F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), + F(78125000, P_UNIPHY2_TX, 4, 0, 0), ++ F(125000000, P_UNIPHY2_TX, 1, 0, 0), + F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), + F(156250000, P_UNIPHY2_TX, 2, 0, 0), + F(312500000, P_UNIPHY2_TX, 1, 0, 0), diff --git a/target/linux/ipq807x/patches-5.10/129-clk-qcom-ipq8074-Add-NSS-PORT-clocks-frequencies.patch b/target/linux/ipq807x/patches-5.10/129-clk-qcom-ipq8074-Add-NSS-PORT-clocks-frequencies.patch new file mode 100644 index 000000000..174db4bde --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/129-clk-qcom-ipq8074-Add-NSS-PORT-clocks-frequencies.patch @@ -0,0 +1,41 @@ +From 6cc04849eea4d87b3b274cc900c6a14a1ac866f5 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Wed, 12 Jul 2017 21:42:11 +0530 +Subject: [PATCH 7/8] clk: qcom: ipq8074: Add NSS PORT clocks frequencies + +The port clock uses different frequency which depends upon +ethernet PHY mode. + +Signed-off-by: Abhishek Sahu +(cherry picked from commit ae5f033e8929d0ffc34320c89b5683f801c3121c) +Signed-off-by: Praveenkumar I + +Change-Id: I7f5d24bc400b3c35d68ef08ae73ab8395b7dd87b +--- + drivers/clk/qcom/gcc-ipq8074.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -1810,8 +1810,10 @@ static struct clk_regmap_div nss_port4_t + static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), ++ F(25000000, P_UNIPHY0_RX, 5, 0, 0), + F(78125000, P_UNIPHY1_RX, 4, 0, 0), + F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), ++ F(125000000, P_UNIPHY0_RX, 1, 0, 0), + F(156250000, P_UNIPHY1_RX, 2, 0, 0), + F(312500000, P_UNIPHY1_RX, 1, 0, 0), + { } +@@ -1849,8 +1851,10 @@ static struct clk_regmap_div nss_port5_r + + static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), ++ F(25000000, P_UNIPHY0_TX, 5, 0, 0), + F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), + F(78125000, P_UNIPHY1_TX, 4, 0, 0), ++ F(125000000, P_UNIPHY0_TX, 1, 0, 0), + F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), + F(156250000, P_UNIPHY1_TX, 2, 0, 0), + F(312500000, P_UNIPHY1_TX, 1, 0, 0), diff --git a/target/linux/ipq807x/patches-5.10/130-clk-qcom-ipq8074-change-freq-table-for-port5_tx_clk_.patch b/target/linux/ipq807x/patches-5.10/130-clk-qcom-ipq8074-change-freq-table-for-port5_tx_clk_.patch new file mode 100644 index 000000000..ad02baa6e --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/130-clk-qcom-ipq8074-change-freq-table-for-port5_tx_clk_.patch @@ -0,0 +1,38 @@ +From be45ad064b7afdbc1e4f36c5a04c27cc364900c2 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Tue, 7 Nov 2017 15:03:52 +0530 +Subject: [PATCH 8/8] clk: qcom: ipq8074: change freq table for + port5_tx_clk_src + +Originally QCOM clock framework assumes that there will be +only one entry for each freq but in port5, the same freq can be +supplied by 2 sources, uniphy0 and uniphy1. We need to move +uniphy1 above uniphy0 in frequency table so that uniphy1 will be +selected instead of uniphy0 if uniphy0 is running in +125 Mhz and uniphy1 is running in 312 Mhz. + +Signed-off-by: Abhishek Sahu +(cherry picked from commit 559fcf09e9681f7d1fcbd981a5de7957ffb3e496) +Signed-off-by: Praveenkumar I + +Change-Id: I91c17714922afc1ef4cdb5e6e47e2e813e2e9777 +--- + drivers/clk/qcom/gcc-ipq8074.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -1851,11 +1851,11 @@ static struct clk_regmap_div nss_port5_r + + static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), +- F(25000000, P_UNIPHY0_TX, 5, 0, 0), + F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), ++ F(25000000, P_UNIPHY0_TX, 5, 0, 0), + F(78125000, P_UNIPHY1_TX, 4, 0, 0), +- F(125000000, P_UNIPHY0_TX, 1, 0, 0), + F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), ++ F(125000000, P_UNIPHY0_TX, 1, 0, 0), + F(156250000, P_UNIPHY1_TX, 2, 0, 0), + F(312500000, P_UNIPHY1_TX, 1, 0, 0), + { } diff --git a/target/linux/ipq807x/patches-5.4/102-01-arm64-dts-ipq8074-add-SPMI-arbiter-node.patch b/target/linux/ipq807x/patches-5.10/131-arm64-dts-ipq8074-add-SPMI-bus.patch similarity index 56% rename from target/linux/ipq807x/patches-5.4/102-01-arm64-dts-ipq8074-add-SPMI-arbiter-node.patch rename to target/linux/ipq807x/patches-5.10/131-arm64-dts-ipq8074-add-SPMI-bus.patch index afb746580..bdfbff212 100644 --- a/target/linux/ipq807x/patches-5.4/102-01-arm64-dts-ipq8074-add-SPMI-arbiter-node.patch +++ b/target/linux/ipq807x/patches-5.10/131-arm64-dts-ipq8074-add-SPMI-bus.patch @@ -1,25 +1,23 @@ -From 5866b2675eb4aba6ddc1e64d5afce60a4e8ccb0f Mon Sep 17 00:00:00 2001 +From 43d5a2b56802327a27a3acb30eb1e458959f5794 Mon Sep 17 00:00:00 2001 From: Robert Marko -Date: Fri, 21 Aug 2020 15:26:00 +0200 -Subject: [PATCH] arm64: dts: ipq8074: add SPMI arbiter node +Date: Thu, 13 May 2021 11:14:02 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add SPMI bus -IPQ8074 uses the SPMI arbiter to control the PM8074 PMIC connected -to it. -So lets add the SPMI node to enable the arbiter. +IPQ8074 has a SPMI v2 arbiter, so add the node +for it. Signed-off-by: Robert Marko --- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -529,5 +529,26 @@ - "axi_m_sticky"; - status = "disabled"; +@@ -390,6 +390,25 @@ + #reset-cells = <0x1>; }; -+ -+ spmi@200f000 { + ++ spmi_bus: qcom,spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000>, + <0x2400000 0x800000>, @@ -29,15 +27,15 @@ Signed-off-by: Robert Marko + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts = ; + interrupt-names = "periph_irq"; -+ + qcom,ee = <0>; + qcom,channel = <0>; -+ + #address-cells = <2>; + #size-cells = <0>; -+ + interrupt-controller; + #interrupt-cells = <4>; ++ cell-index = <0>; + }; - }; - }; ++ + sdhc_1: sdhci@7824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7824900 0x500>, <0x7824000 0x800>; diff --git a/target/linux/ipq807x/patches-5.10/132-regulator-qcom_spmi-Add-PMD9655-SPMI-regulator.patch b/target/linux/ipq807x/patches-5.10/132-regulator-qcom_spmi-Add-PMD9655-SPMI-regulator.patch new file mode 100644 index 000000000..6b3ca0e1b --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/132-regulator-qcom_spmi-Add-PMD9655-SPMI-regulator.patch @@ -0,0 +1,38 @@ +From 43361c2201bc9b67ee42a6afab7a3a476eaf6156 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Tue, 31 Mar 2020 22:00:27 +0530 +Subject: [PATCH 1/6] regulator: qcom_spmi: Add PMD9655 SPMI regulator + +PMD9655 is used in IPQ8074 and provides S3 for cores, +S4 for UBI core and LDO11 for SDIO/eMMC. + +Signed-off-by: Praveenkumar I +Signed-off-by: Robert Marko +--- + drivers/regulator/qcom_spmi-regulator.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -2082,6 +2082,13 @@ static const struct spmi_regulator_data + { } + }; + ++static const struct spmi_regulator_data pmd9655_regulators[] = { ++ { "s3", 0x1a00, "vdd_s3",}, ++ { "s4", 0x1d00, "vdd_s4",}, ++ { "ldo11", 0x4a00, "vdd_ldo11",}, ++ { } ++}; ++ + static const struct of_device_id qcom_spmi_regulator_match[] = { + { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators }, + { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, +@@ -2094,6 +2101,7 @@ static const struct of_device_id qcom_sp + { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, + { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, + { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, ++ { .compatible = "qcom,pmd9655-regulators", .data = &pmd9655_regulators }, + { } + }; + MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); diff --git a/target/linux/ipq807x/patches-5.10/133-regulator-qcom_spmi-SMPS-range-is-added-to-support-P.patch b/target/linux/ipq807x/patches-5.10/133-regulator-qcom_spmi-SMPS-range-is-added-to-support-P.patch new file mode 100644 index 000000000..06628ad2a --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/133-regulator-qcom_spmi-SMPS-range-is-added-to-support-P.patch @@ -0,0 +1,22 @@ +From 095567c1736af28ef6b472e2ab728a2222a425da Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Mon, 4 May 2020 19:31:00 +0530 +Subject: [PATCH 2/6] regulator: qcom_spmi: SMPS range is added to support + PMD9655 PMIC + +Signed-off-by: Praveenkumar I +Change-Id: I5571801debec25527fd763d95aff27cc42f53bde +--- + drivers/regulator/qcom_spmi-regulator.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -480,6 +480,7 @@ static struct spmi_voltage_range ln_ldo_ + }; + + static struct spmi_voltage_range smps_ranges[] = { ++ SPMI_VOLTAGE_RANGE(2, 670000, 670000, 990000, 990000, 8000), + SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), + SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), + }; diff --git a/target/linux/ipq807x/patches-5.10/134-regulator-qcom_spmi-Initialize-slew-rate-only-if-req.patch b/target/linux/ipq807x/patches-5.10/134-regulator-qcom_spmi-Initialize-slew-rate-only-if-req.patch new file mode 100644 index 000000000..b7fd176fc --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/134-regulator-qcom_spmi-Initialize-slew-rate-only-if-req.patch @@ -0,0 +1,35 @@ +From 0890aba3f364ed0764fdfa79bd77db130396e594 Mon Sep 17 00:00:00 2001 +From: PRAVEENKUMAR I +Date: Tue, 5 May 2020 07:57:21 +0530 +Subject: [PATCH 3/6] regulator: qcom_spmi: Initialize slew rate only if + required + +Initialize slew rate only if set_voltage_time_sel in ops +is defined. + +Change-Id: I661c88d2f4a8f26cc85b1e2d4c8aa3170420ba6c +Signed-off-by: Rajith Cherian +(cherry picked from commit 608a6f171ef4017197fbe2069b5910b582923027) +Signed-off-by: Praveenkumar I + +Change-Id: Ida3cf3d754e1207e34a164d6d86c6e1aa109ef1e +--- + drivers/regulator/qcom_spmi-regulator.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -1610,6 +1610,13 @@ static int spmi_regulator_init_slew_rate + int step, delay, slew_rate, step_delay; + const struct spmi_voltage_range *range; + ++ /* ++ * Slew rate need not be initialized if ++ * set_voltage_time_sel in the ops is not defined. ++ */ ++ if (!vreg->desc.ops->set_voltage_time_sel) ++ return 0; ++ + ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); + if (ret) { + dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); diff --git a/target/linux/ipq807x/patches-5.4/102-03-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch b/target/linux/ipq807x/patches-5.10/135-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch similarity index 78% rename from target/linux/ipq807x/patches-5.4/102-03-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch rename to target/linux/ipq807x/patches-5.10/135-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch index c1da46ae6..0b36cee95 100644 --- a/target/linux/ipq807x/patches-5.4/102-03-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch +++ b/target/linux/ipq807x/patches-5.10/135-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch @@ -1,20 +1,25 @@ -From 2f42b1f07c78c06bd7d5b0d812f48a7b1d96968a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 Aug 2020 23:06:23 +0200 -Subject: [PATCH] regulator: qcom_spmi: Add support for VMPWM_CTL subtype +From 50b5c040b8c1928990baad8e07126df63aa09cce Mon Sep 17 00:00:00 2001 +From: PRAVEENKUMAR I +Date: Tue, 5 May 2020 07:57:52 +0530 +Subject: [PATCH 4/6] regulator: qcom_spmi: Add support for VMPWM_CTL subtype Support for Voltage Mode PWM Controller (VMPWM_CTL). Set/Get microvolts functions added. Function to find the voltage range for this particular subtype added. -Signed-off-by: Robert Marko +Change-Id: Ib4bf35ee65de17a917f01e63208368c7770401d4 +Signed-off-by: Rajith Cherian +(cherry picked from commit 31e7e4183b5afaf18dbca3548f4988c420ebb58b) +Signed-off-by: Praveenkumar I + +Change-Id: Id7a3caef84499b9e2eefda9f57576923c84234f0 --- - drivers/regulator/qcom_spmi-regulator.c | 82 +++++++++++++++++++++++++++++++++++++++++++ + drivers/regulator/qcom_spmi-regulator.c | 82 +++++++++++++++++++++++++ 1 file changed, 82 insertions(+) --- a/drivers/regulator/qcom_spmi-regulator.c +++ b/drivers/regulator/qcom_spmi-regulator.c -@@ -151,6 +151,7 @@ enum spmi_regulator_subtype { +@@ -163,6 +163,7 @@ enum spmi_regulator_subtype { SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, @@ -22,7 +27,7 @@ Signed-off-by: Robert Marko }; enum spmi_common_regulator_registers { -@@ -276,6 +277,10 @@ enum spmi_common_control_register_index +@@ -288,6 +289,10 @@ enum spmi_common_control_register_index #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07 #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0 @@ -33,8 +38,8 @@ Signed-off-by: Robert Marko /* Clock rate in kHz of the FTSMPS regulator reference clock. */ #define SPMI_FTSMPS_CLOCK_RATE 19200 -@@ -473,6 +478,10 @@ static struct spmi_voltage_range smps_ra - SPMI_VOLTAGE_RANGE(2, 670000, 670000, 990000, 990000, 8000), +@@ -485,6 +490,10 @@ static struct spmi_voltage_range smps_ra + SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), }; +static struct spmi_voltage_range smps_vmpwm_ranges[] = { @@ -44,7 +49,7 @@ Signed-off-by: Robert Marko static struct spmi_voltage_range ftsmps_ranges[] = { SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000), SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000), -@@ -522,6 +531,7 @@ static DEFINE_SPMI_SET_POINTS(nldo2); +@@ -550,6 +559,7 @@ static DEFINE_SPMI_SET_POINTS(nldo2); static DEFINE_SPMI_SET_POINTS(nldo3); static DEFINE_SPMI_SET_POINTS(ln_ldo); static DEFINE_SPMI_SET_POINTS(smps); @@ -52,7 +57,7 @@ Signed-off-by: Robert Marko static DEFINE_SPMI_SET_POINTS(ftsmps); static DEFINE_SPMI_SET_POINTS(ftsmps2p5); static DEFINE_SPMI_SET_POINTS(ftsmps426); -@@ -708,6 +718,24 @@ spmi_regulator_find_range(struct spmi_re +@@ -740,6 +750,24 @@ spmi_regulator_find_range(struct spmi_re return NULL; } @@ -77,7 +82,7 @@ Signed-off-by: Robert Marko static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg, int min_uV, int max_uV) { -@@ -929,6 +957,47 @@ static int spmi_regulator_ult_lo_smps_ge +@@ -961,6 +989,47 @@ static int spmi_regulator_ult_lo_smps_ge return spmi_hw_selector_to_sw(vreg, voltage_sel, range); } @@ -125,11 +130,11 @@ Signed-off-by: Robert Marko static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, unsigned selector) { -@@ -1277,6 +1346,18 @@ static struct regulator_ops spmi_smps_op +@@ -1309,6 +1378,18 @@ static const struct regulator_ops spmi_s .set_pull_down = spmi_regulator_common_set_pull_down, }; -+static struct regulator_ops spmi_smps_vmpwm_ops = { ++static const struct regulator_ops spmi_smps_vmpwm_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, @@ -141,14 +146,14 @@ Signed-off-by: Robert Marko + .get_mode = spmi_regulator_common_get_mode, +}; + - static struct regulator_ops spmi_ldo_ops = { + static const struct regulator_ops spmi_ldo_ops = { .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, -@@ -1424,6 +1505,7 @@ static const struct spmi_regulator_mappi +@@ -1454,6 +1535,7 @@ static const struct regulator_ops spmi_h + + static const struct spmi_regulator_mapping supported_regulators[] = { /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ ++ SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0), SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), -+ SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0), SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), - SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), - SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), diff --git a/target/linux/ipq807x/patches-5.10/136-ipq807x-sdhc-Fixed-SDR104-mode-card-detection.patch b/target/linux/ipq807x/patches-5.10/136-ipq807x-sdhc-Fixed-SDR104-mode-card-detection.patch new file mode 100644 index 000000000..30519f343 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/136-ipq807x-sdhc-Fixed-SDR104-mode-card-detection.patch @@ -0,0 +1,53 @@ +From 84d0ae645dc1c3d8726bf8cd482be052f915f00b Mon Sep 17 00:00:00 2001 +From: Vasudevan Murugesan +Date: Thu, 8 Jun 2017 19:13:48 +0530 +Subject: [PATCH 5/6] ipq807x: sdhc: Fixed SDR104 mode card detection + +Change-Id: I353356284d28d09d79bf7d318c4ebcdbc15e5b02 +Signed-off-by: Vasudevan Murugesan +Signed-off-by: Saravanan Jaganathan +(cherry picked from commit 080d3f390aa409ef2b5adf59a175b6bb2aa863fd) +Signed-off-by: Praveenkumar I + +Change-Id: Ie5edb7b3d972e06f3eb2525e10597b49e9bae14d +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 - + drivers/regulator/qcom_spmi-regulator.c | 3 +++ + 2 files changed, 3 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -430,7 +430,6 @@ + + status = "disabled"; + }; +- + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x2b000>; +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -164,6 +164,7 @@ enum spmi_regulator_subtype { + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, + SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, + SPMI_REGULATOR_SUBTYPE_VMPWM_CTL = 0x0a, ++ SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, + }; + + enum spmi_common_regulator_registers { +@@ -492,6 +493,7 @@ static struct spmi_voltage_range smps_ra + + static struct spmi_voltage_range smps_vmpwm_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), ++ SPMI_VOLTAGE_RANGE(1, 1104000, 1104000, 3300000, 3300000, 8000), + }; + + static struct spmi_voltage_range ftsmps_ranges[] = { +@@ -1535,6 +1537,7 @@ static const struct regulator_ops spmi_h + + static const struct spmi_regulator_mapping supported_regulators[] = { + /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ ++ SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, smps_vmpwm, 0), + SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0), + SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), + SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), diff --git a/target/linux/ipq807x/patches-5.10/137-ipq807x-spmi-regulator-Add-separate-voltage-range-fo.patch b/target/linux/ipq807x/patches-5.10/137-ipq807x-spmi-regulator-Add-separate-voltage-range-fo.patch new file mode 100644 index 000000000..4e4b3f1f0 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/137-ipq807x-spmi-regulator-Add-separate-voltage-range-fo.patch @@ -0,0 +1,49 @@ +From c603c7a1e2d5cc432d8e1250baff8130755a6f43 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Mon, 13 Jul 2020 18:13:48 +0530 +Subject: [PATCH 6/6] ipq807x: spmi regulator: Add separate voltage range for + LDO + +When LDO voltage range added in SMPS voltage range structure, +selector value used during set voltage is wrongly calculated. +Because the SMPS voltage range is also taken into account for LDO. + +So, a separate voltage range structure is introduced for LDO. + +Signed-off-by: Praveenkumar I +Change-Id: I883518ae0686762a3774750b1dd480c4fe7298f3 +--- + drivers/regulator/qcom_spmi-regulator.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -493,7 +493,10 @@ static struct spmi_voltage_range smps_ra + + static struct spmi_voltage_range smps_vmpwm_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), +- SPMI_VOLTAGE_RANGE(1, 1104000, 1104000, 3300000, 3300000, 8000), ++}; ++ ++static struct spmi_voltage_range ldo_vmpwm_ranges[] = { ++ SPMI_VOLTAGE_RANGE(0, 1104000, 1104000, 3300000, 3300000, 8000), + }; + + static struct spmi_voltage_range ftsmps_ranges[] = { +@@ -562,6 +565,7 @@ static DEFINE_SPMI_SET_POINTS(nldo3); + static DEFINE_SPMI_SET_POINTS(ln_ldo); + static DEFINE_SPMI_SET_POINTS(smps); + static DEFINE_SPMI_SET_POINTS(smps_vmpwm); ++static DEFINE_SPMI_SET_POINTS(ldo_vmpwm); + static DEFINE_SPMI_SET_POINTS(ftsmps); + static DEFINE_SPMI_SET_POINTS(ftsmps2p5); + static DEFINE_SPMI_SET_POINTS(ftsmps426); +@@ -1537,7 +1541,7 @@ static const struct regulator_ops spmi_h + + static const struct spmi_regulator_mapping supported_regulators[] = { + /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ +- SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, smps_vmpwm, 0), ++ SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, ldo_vmpwm, 0), + SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0), + SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), + SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), diff --git a/target/linux/ipq807x/patches-5.4/102-05-arm64-dts-ipq8074-Add-PMD9655-SPMI-PMIC-nodes.patch b/target/linux/ipq807x/patches-5.10/138-arm64-dts-ipq8074-add-SPMI-PMIC-regulators.patch similarity index 79% rename from target/linux/ipq807x/patches-5.4/102-05-arm64-dts-ipq8074-Add-PMD9655-SPMI-PMIC-nodes.patch rename to target/linux/ipq807x/patches-5.10/138-arm64-dts-ipq8074-add-SPMI-PMIC-regulators.patch index ad63cccaf..ee723f20c 100644 --- a/target/linux/ipq807x/patches-5.4/102-05-arm64-dts-ipq8074-Add-PMD9655-SPMI-PMIC-nodes.patch +++ b/target/linux/ipq807x/patches-5.10/138-arm64-dts-ipq8074-add-SPMI-PMIC-regulators.patch @@ -1,16 +1,16 @@ -From 99007c6f1c4d4d97db51d59808f69505a8bad4fa Mon Sep 17 00:00:00 2001 +From df848f06020c609950107f87c39f41e7eee92b5e Mon Sep 17 00:00:00 2001 From: Robert Marko -Date: Fri, 21 Aug 2020 17:19:00 +0200 -Subject: [PATCH] arm64: dts: ipq8074: Add PMD9655 SPMI PMIC nodes +Date: Thu, 13 May 2021 11:54:35 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add SPMI PMIC regulators -IPQ8074 uses these for CPU scaling, UBI/NSS scaling and -SD card. +PMD9655 is used in IPQ8074 and provides S3 for cores, +S4 for UBI core and LDO11 for SDIO/eMMC. -So lets add the nodes. +So, lets add the nodes in preparation for DVFS later. Signed-off-by: Robert Marko --- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++++++++ + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -23,8 +23,8 @@ Signed-off-by: Robert Marko / { model = "Qualcomm Technologies, Inc. IPQ8074"; -@@ -76,6 +77,15 @@ - method = "smc"; +@@ -136,6 +137,15 @@ + }; }; + e_smps1_reg: fixed-regulator@0 { @@ -39,13 +39,13 @@ Signed-off-by: Robert Marko soc: soc { #address-cells = <0x1>; #size-cells = <0x1>; -@@ -549,6 +559,42 @@ - +@@ -407,6 +417,42 @@ interrupt-controller; #interrupt-cells = <4>; + cell-index = <0>; + + pmic@1 { -+ compatible = "qcom,spmi-pmic"; ++ compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; @@ -80,5 +80,5 @@ Signed-off-by: Robert Marko + }; + }; }; - }; - }; + + sdhc_1: sdhci@7824900 { diff --git a/target/linux/ipq807x/patches-5.10/139-ipq8074-clk-apss-Added-APSS-clock-driver.patch b/target/linux/ipq807x/patches-5.10/139-ipq8074-clk-apss-Added-APSS-clock-driver.patch new file mode 100644 index 000000000..287c4cf57 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/139-ipq8074-clk-apss-Added-APSS-clock-driver.patch @@ -0,0 +1,328 @@ +From 6961b02dd2765b71b201f065172998a16ff9c2eb Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Sun, 22 Mar 2020 20:22:29 +0530 +Subject: [PATCH 1/3] ipq8074: clk: apss: Added APSS clock driver + +apss-ipq8074 files are snapshot form eggplant branch, +https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/commit/?h=keggplant/eggplant&id=f2fb70e8315ef1c450171e59d681c6a156b1a4e8 + +Signed-off-by: Praveenkumar I +Change-Id: I17ecad1f1731c88d8d91485d5d5f8a38b76f7104 +--- + drivers/clk/qcom/Kconfig | 7 + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/apss-ipq8074.c | 210 +++++++++++++++++++ + drivers/clk/qcom/clk-alpha-pll.c | 12 ++ + drivers/clk/qcom/clk-alpha-pll.h | 3 + + include/dt-bindings/clock/qca,apss-ipq8074.h | 25 +++ + 6 files changed, 258 insertions(+) + create mode 100644 drivers/clk/qcom/apss-ipq8074.c + create mode 100644 include/dt-bindings/clock/qca,apss-ipq8074.h + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -155,6 +155,13 @@ config IPQ_GCC_8074 + i2c, USB, SD/eMMC, etc. Select this for the root clock + of ipq8074. + ++config IPQ_APSS_8074 ++ tristate "IPQ8074 APSS Clock Controller" ++ select IPQ_GCC_8074 ++ help ++ Support for APSS clock controller on ipq8074 devices. ++ Say Y if you want to use APSS clocks such as CPU. ++ + config MSM_GCC_8660 + tristate "MSM8660 Global Clock Controller" + help +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -25,6 +25,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq401 + obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o + obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o + obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o ++obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o + obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o + obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o + obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o +--- /dev/null ++++ b/drivers/clk/qcom/apss-ipq8074.c +@@ -0,0 +1,210 @@ ++/* ++ * Copyright (c) 2017,2020. The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "common.h" ++#include "clk-regmap.h" ++#include "clk-pll.h" ++#include "clk-rcg.h" ++#include "clk-branch.h" ++#include "clk-alpha-pll.h" ++#include "clk-regmap-divider.h" ++#include "clk-regmap-mux.h" ++#include "reset.h" ++ ++#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } ++ ++enum { ++ P_XO, ++ P_GPLL0, ++ P_GPLL2, ++ P_GPLL4, ++ P_APSS_PLL_EARLY, ++ P_APSS_PLL ++}; ++ ++static struct clk_alpha_pll apss_pll_early = { ++ .offset = 0x5000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], ++ .clkr = { ++ .enable_reg = 0x5000, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "apss_pll_early", ++ .parent_names = (const char *[]){ ++ "xo" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_huayra_ops, ++ }, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv apss_pll = { ++ .offset = 0x5000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], ++ .width = 2, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "apss_pll", ++ .parent_names = (const char *[]){ "apss_pll_early" }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ }, ++}; ++ ++static const char * const parents_apcs_alias0_clk_src[] = { ++ "xo", ++ "gpll0", ++ "gpll2", ++ "gpll4", ++ "apss_pll", ++ "apss_pll_early", ++}; ++ ++static const struct parent_map parents_apcs_alias0_clk_src_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 4 }, ++ { P_GPLL2, 2 }, ++ { P_GPLL4, 1 }, ++ { P_APSS_PLL, 3 }, ++ { P_APSS_PLL_EARLY, 5 }, ++}; ++ ++struct freq_tbl ftbl_apcs_alias0_clk_src[] = { ++ F(19200000, P_XO, 1, 0, 0), ++ F(403200000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(806400000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1017600000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1382400000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1651200000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1843200000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(1920000000, P_APSS_PLL_EARLY, 1, 0, 0), ++ F(2208000000UL, P_APSS_PLL_EARLY, 1, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 apcs_alias0_clk_src = { ++ .cmd_rcgr = 0x0050, ++ .freq_tbl = ftbl_apcs_alias0_clk_src, ++ .hid_width = 5, ++ .parent_map = parents_apcs_alias0_clk_src_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "apcs_alias0_clk_src", ++ .parent_names = parents_apcs_alias0_clk_src, ++ .num_parents = 6, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_branch apcs_alias0_core_clk = { ++ .halt_reg = 0x0058, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x0058, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "apcs_alias0_core_clk", ++ .parent_names = (const char *[]){ ++ "apcs_alias0_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | ++ CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_regmap *apss_ipq807x_clks[] = { ++ [APSS_PLL_EARLY] = &apss_pll_early.clkr, ++ [APSS_PLL] = &apss_pll.clkr, ++ [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr, ++ [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, ++}; ++ ++static const struct of_device_id apss_ipq807x_match_table[] = { ++ { .compatible = "qcom,apss-ipq807x" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, apss_ipq807x_match_table); ++ ++static const struct regmap_config apss_ipq807x_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x5ffc, ++ .fast_io = true, ++}; ++ ++static const struct qcom_cc_desc apss_ipq807x_desc = { ++ .config = &apss_ipq807x_regmap_config, ++ .clks = apss_ipq807x_clks, ++ .num_clks = ARRAY_SIZE(apss_ipq807x_clks), ++}; ++ ++static int apss_ipq807x_probe(struct platform_device *pdev) ++{ ++ int ret; ++ ++ ret = qcom_cc_probe(pdev, &apss_ipq807x_desc); ++ ++ dev_dbg(&pdev->dev, "Registered ipq807x apss clock provider\n"); ++ ++ return ret; ++} ++ ++static int apss_ipq807x_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static struct platform_driver apss_ipq807x_driver = { ++ .probe = apss_ipq807x_probe, ++ .remove = apss_ipq807x_remove, ++ .driver = { ++ .name = "qcom,apss-ipq807x", ++ .owner = THIS_MODULE, ++ .of_match_table = apss_ipq807x_match_table, ++ }, ++}; ++ ++static int __init apss_ipq807x_init(void) ++{ ++ return platform_driver_register(&apss_ipq807x_driver); ++} ++core_initcall(apss_ipq807x_init); ++ ++static void __exit apss_ipq807x_exit(void) ++{ ++ platform_driver_unregister(&apss_ipq807x_driver); ++} ++module_exit(apss_ipq807x_exit); ++ ++MODULE_DESCRIPTION("QCA APSS IPQ807x Driver"); ++MODULE_LICENSE("Dual BSD/GPLv2"); ++MODULE_ALIAS("platform:apss-ipq807x"); +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -116,6 +116,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MA + [PLL_OFF_OPMODE] = 0x38, + [PLL_OFF_ALPHA_VAL] = 0x40, + }, ++ [CLK_ALPHA_PLL_TYPE_APSS] = { ++ [PLL_OFF_L_VAL] = 0x08, ++ [PLL_OFF_ALPHA_VAL] = 0x10, ++ [PLL_OFF_ALPHA_VAL_U] = 0xff, ++ [PLL_OFF_USER_CTL] = 0x18, ++ [PLL_OFF_USER_CTL_U] = 0xff, ++ [PLL_OFF_CONFIG_CTL] = 0x20, ++ [PLL_OFF_CONFIG_CTL_U] = 0x24, ++ [PLL_OFF_TEST_CTL] = 0x30, ++ [PLL_OFF_TEST_CTL_U] = 0x34, ++ [PLL_OFF_STATUS] = 0x28, ++ } + }; + EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); + +--- a/drivers/clk/qcom/clk-alpha-pll.h ++++ b/drivers/clk/qcom/clk-alpha-pll.h +@@ -15,6 +15,7 @@ enum { + CLK_ALPHA_PLL_TYPE_FABIA, + CLK_ALPHA_PLL_TYPE_TRION, + CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, ++ CLK_ALPHA_PLL_TYPE_APSS, + CLK_ALPHA_PLL_TYPE_MAX, + }; + +@@ -69,6 +70,8 @@ struct clk_alpha_pll { + #define SUPPORTS_OFFLINE_REQ BIT(0) + #define SUPPORTS_FSM_MODE BIT(2) + #define SUPPORTS_DYNAMIC_UPDATE BIT(3) ++ ++ + u8 flags; + + struct clk_regmap clkr; +--- /dev/null ++++ b/include/dt-bindings/clock/qca,apss-ipq8074.h +@@ -0,0 +1,25 @@ ++/* ++ * Copyright (c) 2017,2020. The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H ++#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H ++ ++#define APSS_PLL_EARLY 0 ++#define APSS_PLL 1 ++#define APCS_ALIAS0_CLK_SRC 2 ++#define APCS_ALIAS0_CORE_CLK 3 ++ ++#endif diff --git a/target/linux/ipq807x/patches-5.10/140-clk-qcom-ipq8074-make-apss-clock-as-child-of-mailbox.patch b/target/linux/ipq807x/patches-5.10/140-clk-qcom-ipq8074-make-apss-clock-as-child-of-mailbox.patch new file mode 100644 index 000000000..9166576c5 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/140-clk-qcom-ipq8074-make-apss-clock-as-child-of-mailbox.patch @@ -0,0 +1,105 @@ +From b5c28ea3b9a963d425ae88ef53d266ff8ae95bc2 Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Fri, 24 Apr 2020 23:05:50 +0530 +Subject: [PATCH 2/3] clk: qcom: ipq8074: make apss clock as child of mailbox + +both apcs mailbox and apss clock controller access the same register +space, resource request will fail for one of the two drivers. + +to resolve this make apss clock controller as child of mailbox, the apss +clock controller will use mailbox regmap for resource request and probe. + +Signed-off-by: Sivaprakash Murugesan +Change-Id: Ic26ee78b6f680fa0655a73d3176bae271725ab05 +--- + drivers/clk/qcom/apss-ipq8074.c | 14 ++++++-------- + drivers/mailbox/qcom-apcs-ipc-mailbox.c | 18 +++++++++++++++--- + 2 files changed, 21 insertions(+), 11 deletions(-) + +--- a/drivers/clk/qcom/apss-ipq8074.c ++++ b/drivers/clk/qcom/apss-ipq8074.c +@@ -147,12 +147,6 @@ static struct clk_regmap *apss_ipq807x_c + [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, + }; + +-static const struct of_device_id apss_ipq807x_match_table[] = { +- { .compatible = "qcom,apss-ipq807x" }, +- { } +-}; +-MODULE_DEVICE_TABLE(of, apss_ipq807x_match_table); +- + static const struct regmap_config apss_ipq807x_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, +@@ -170,8 +164,13 @@ static const struct qcom_cc_desc apss_ip + static int apss_ipq807x_probe(struct platform_device *pdev) + { + int ret; ++ struct regmap *regmap; ++ ++ regmap = dev_get_regmap(pdev->dev.parent, NULL); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); + +- ret = qcom_cc_probe(pdev, &apss_ipq807x_desc); ++ ret = qcom_cc_really_probe(pdev, &apss_ipq807x_desc, regmap); + + dev_dbg(&pdev->dev, "Registered ipq807x apss clock provider\n"); + +@@ -189,7 +188,6 @@ static struct platform_driver apss_ipq80 + .driver = { + .name = "qcom,apss-ipq807x", + .owner = THIS_MODULE, +- .of_match_table = apss_ipq807x_match_table, + }, + }; + +--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c ++++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c +@@ -65,7 +65,7 @@ static const struct regmap_config apcs_r + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, +- .max_register = 0xFFC, ++ .max_register = 0x5FFC, + .fast_io = true, + }; + +@@ -82,6 +82,16 @@ static const struct mbox_chan_ops qcom_a + .send_data = qcom_apcs_ipc_send_data, + }; + ++static const struct of_device_id apcs_clk_match_table[] = { ++ { .compatible = "qcom,msm8916-apcs-kpss-global", ++ . data = "qcom-apcs-msm8916-clk", }, ++ { .compatible = "qcom,qcs404-apcs-apps-global", ++ .data = "qcom-apcs-msm8916-clk", }, ++ { .compatible = "qcom,ipq8074-apcs-apps-global", ++ .data = "qcom,apss-ipq807x", }, ++ {} ++}; ++ + static int qcom_apcs_ipc_probe(struct platform_device *pdev) + { + struct qcom_apcs_ipc *apcs; +@@ -91,6 +101,7 @@ static int qcom_apcs_ipc_probe(struct pl + void __iomem *base; + unsigned long i; + int ret; ++ const struct of_device_id *device_id; + + apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL); + if (!apcs) +@@ -125,9 +136,10 @@ static int qcom_apcs_ipc_probe(struct pl + return ret; + } + +- if (apcs_data->clk_name) { ++ device_id = of_match_device(apcs_clk_match_table, &pdev->dev); ++ if (device_id) { + apcs->clk = platform_device_register_data(&pdev->dev, +- apcs_data->clk_name, ++ device_id->data, + PLATFORM_DEVID_NONE, + NULL, 0); + if (IS_ERR(apcs->clk)) diff --git a/target/linux/ipq807x/patches-5.10/141-arm64-dts-ipq8074-add-APPS-CPU-clock.patch b/target/linux/ipq807x/patches-5.10/141-arm64-dts-ipq8074-add-APPS-CPU-clock.patch new file mode 100644 index 000000000..ab556b798 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/141-arm64-dts-ipq8074-add-APPS-CPU-clock.patch @@ -0,0 +1,70 @@ +From 99841b41e13b4a0512de1e06191cdcaf7ee0e1d1 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 12:42:05 +0200 +Subject: [PATCH 3/3] arm64: dts: ipq8074: add APPS CPU clock + +In preparation for frequency scaling add the APPS +clock support. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -5,6 +5,7 @@ + + #include + #include ++#include + #include + + / { +@@ -33,6 +34,8 @@ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ clock-names = "cpu"; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; +@@ -42,6 +45,8 @@ + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ clock-names = "cpu"; + next-level-cache = <&L2_0>; + }; + +@@ -50,6 +55,8 @@ + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ clock-names = "cpu"; + next-level-cache = <&L2_0>; + }; + +@@ -58,6 +65,8 @@ + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ clock-names = "cpu"; + next-level-cache = <&L2_0>; + }; + +@@ -909,8 +918,9 @@ + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; +- reg = <0x0b111000 0x1000>; ++ reg = <0x0b111000 0x6000>; + ++ #clock-cells = <1>; + #mbox-cells = <1>; + }; + diff --git a/target/linux/ipq807x/patches-5.10/142-arm64-dts-ipq8074-add-label-to-cpus.patch b/target/linux/ipq807x/patches-5.10/142-arm64-dts-ipq8074-add-label-to-cpus.patch new file mode 100644 index 000000000..687cb55c4 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/142-arm64-dts-ipq8074-add-label-to-cpus.patch @@ -0,0 +1,26 @@ +From fb5a1fff750f99dbf7cabda0de9fbf7463a07586 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 13:13:46 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add label to cpus + +Add label to cpus node as that makes it +easy to add OPP table in SoC model specific +DTSI as IPQ8074 family has differing clocks +and voltages based on model. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -26,7 +26,7 @@ + }; + }; + +- cpus { ++ cpus: cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + diff --git a/target/linux/ipq807x/patches-5.10/143-arm64-dts-ipq8074-Add-WLAN-node.patch b/target/linux/ipq807x/patches-5.10/143-arm64-dts-ipq8074-Add-WLAN-node.patch new file mode 100644 index 000000000..e270ec41c --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/143-arm64-dts-ipq8074-Add-WLAN-node.patch @@ -0,0 +1,133 @@ +From 0fb054684bdf40f17ab59226dae21ddfe0d79466 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 15:15:46 +0200 +Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node + +IPQ8074 is supported by ath11k, so add the required +DT node. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++ + 1 file changed, 111 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -974,6 +974,117 @@ + }; + }; + ++ wifi: wifi@c0000000 { ++ compatible = "qcom,ipq8074-wifi"; ++ reg = <0xc000000 0x2000000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ ++ interrupt-names = "misc-pulse1", ++ "misc-latch", ++ "sw-exception", ++ "ce0", ++ "ce1", ++ "ce2", ++ "ce3", ++ "ce4", ++ "ce5", ++ "ce6", ++ "ce7", ++ "ce8", ++ "ce9", ++ "ce10", ++ "ce11", ++ "host2wbm-desc-feed", ++ "host2reo-re-injection", ++ "host2reo-command", ++ "host2rxdma-monitor-ring3", ++ "host2rxdma-monitor-ring2", ++ "host2rxdma-monitor-ring1", ++ "reo2ost-exception", ++ "wbm2host-rx-release", ++ "reo2host-status", ++ "reo2host-destination-ring4", ++ "reo2host-destination-ring3", ++ "reo2host-destination-ring2", ++ "reo2host-destination-ring1", ++ "rxdma2host-monitor-destination-mac3", ++ "rxdma2host-monitor-destination-mac2", ++ "rxdma2host-monitor-destination-mac1", ++ "ppdu-end-interrupts-mac3", ++ "ppdu-end-interrupts-mac2", ++ "ppdu-end-interrupts-mac1", ++ "rxdma2host-monitor-status-ring-mac3", ++ "rxdma2host-monitor-status-ring-mac2", ++ "rxdma2host-monitor-status-ring-mac1", ++ "host2rxdma-host-buf-ring-mac3", ++ "host2rxdma-host-buf-ring-mac2", ++ "host2rxdma-host-buf-ring-mac1", ++ "rxdma2host-destination-ring-mac3", ++ "rxdma2host-destination-ring-mac2", ++ "rxdma2host-destination-ring-mac1", ++ "host2tcl-input-ring4", ++ "host2tcl-input-ring3", ++ "host2tcl-input-ring2", ++ "host2tcl-input-ring1", ++ "wbm2host-tx-completions-ring3", ++ "wbm2host-tx-completions-ring2", ++ "wbm2host-tx-completions-ring1", ++ "tcl2host-status-ring"; ++ qcom,rproc = <&q6v5_wcss>; ++ status = "disabled"; ++ }; ++ + ess_switch: ess-switch@3a000000 { + compatible = "qcom,ess-switch-ipq807x"; + reg = <0x3a000000 0x1000000>; diff --git a/target/linux/ipq807x/patches-5.10/144-arm64-dts-ipq8074-add-NSS-reserved-memory-node.patch b/target/linux/ipq807x/patches-5.10/144-arm64-dts-ipq8074-add-NSS-reserved-memory-node.patch new file mode 100644 index 000000000..ce2af3edf --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/144-arm64-dts-ipq8074-add-NSS-reserved-memory-node.patch @@ -0,0 +1,28 @@ +From 22865119dada2a40a5e5e8c5f22b5bec08651021 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 14 May 2021 19:43:41 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add NSS reserved memory node + +NSS FW has its own dedicated memory it needs to get loaded to. +Since it simply uses ioremap() that memory must be reserved +so the kernel will allow using ioremap() on it. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -91,6 +91,11 @@ + #size-cells = <2>; + ranges; + ++ nss@40000000 { ++ no-map; ++ reg = <0x0 0x40000000 0x0 0x01000000>; ++ }; ++ + smem_region: memory@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x00100000>; diff --git a/target/linux/ipq807x/patches-5.10/145-clk-qcom-ipq8074-disable-SW_COLLAPSE-for-USB-GDSCR-s.patch b/target/linux/ipq807x/patches-5.10/145-clk-qcom-ipq8074-disable-SW_COLLAPSE-for-USB-GDSCR-s.patch new file mode 100644 index 000000000..47abf9e03 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/145-clk-qcom-ipq8074-disable-SW_COLLAPSE-for-USB-GDSCR-s.patch @@ -0,0 +1,29 @@ +From a801cc475f0d1fdf29d7b6b56d64df090bf83f8d Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Fri, 3 Apr 2020 12:57:37 +0530 +Subject: [PATCH] clk: qcom: ipq8074: disable SW_COLLAPSE for USB GDSCR's + +Change-Id: Id347be781e2bb449bd7cdf05e3535e8ca3c3ffd6 +Signed-off-by: Abhishek Sahu +(cherry picked from commit 5e100df9c29ed7e5ad12583aa39053f4a9761efe) +Signed-off-by: Praveenkumar I + +Change-Id: I17beca334be79d738a35587860847aa0b1f96fa9 +--- + drivers/clk/qcom/gcc-ipq8074.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -5063,6 +5063,11 @@ static int gcc_ipq8074_probe(struct plat + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + ++ /* Disable SW_COLLAPSE for USB0 GDSCR */ ++ regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0); ++ /* Disable SW_COLLAPSE for USB1 GDSCR */ ++ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); ++ + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); diff --git a/target/linux/ipq807x/patches-5.10/146-clk-qcom-ipq8074-SW-workaround-for-UBI-PLL-lock.patch b/target/linux/ipq807x/patches-5.10/146-clk-qcom-ipq8074-SW-workaround-for-UBI-PLL-lock.patch new file mode 100644 index 000000000..c90462e0f --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/146-clk-qcom-ipq8074-SW-workaround-for-UBI-PLL-lock.patch @@ -0,0 +1,46 @@ +From 5f707d3ff1b22c089253e39906b5edeeb5f10fdc Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Fri, 3 Apr 2020 15:31:59 +0530 +Subject: [PATCH] clk: qcom: ipq8074: SW workaround for UBI PLL lock +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some chip’s Huyara PLL is unable to lock in 5 us and +generating UBI PLL lock error. + + WARNING: CPU: 1 PID: 625 at drivers/clk/qcom/clk-alpha-pll.c:114 + wait_for_pll+0xbc/0xe0() + ubi32_pll_main failed to enable! + CPU: 1 PID: 625 Comm: kmodloader Not tainted 4.4.60 #1 + Hardware name: Generic DT based system + (unwind_backtrace) from [<8021b550>] (show_stack+0x10/0x14) + (show_stack) from [<803f6b24>] (dump_stack+0x80/0xa0) + (dump_stack) from [<80228ff0>] (warn_slowpath_common+0x84/0xb0) + (warn_slowpath_common) from [<80229048>] (warn_slowpath_fmt+0x2c/0x3c) + (warn_slowpath_fmt) from [<8054d53c>] (wait_for_pll+0xbc/0xe0) + (wait_for_pll) from [<8054d6cc>] (clk_alpha_pll_enable+0xe0/0x128) + (clk_alpha_pll_enable) from [<80547b68>] (clk_core_enable+0x68/0x98) + (clk_core_enable) from [<80547b48>] (clk_core_enable+0x48/0x98) + +This is BUG in Huayra PLL HW for which SW workaround +is to set bit 26 of TEST_CTL register. + +Change-Id: Ib5473f4011e3410515f382b2445bee2d66dd654a +Signed-off-by: Abhishek Sahu +--- + drivers/clk/qcom/gcc-ipq8074.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -5068,6 +5068,9 @@ static int gcc_ipq8074_probe(struct plat + /* Disable SW_COLLAPSE for USB1 GDSCR */ + regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); + ++ /* SW Workaround for UBI Huayra PLL */ ++ regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); ++ + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); diff --git a/target/linux/ipq807x/patches-5.10/147-clk-ipq8074-defer-from-disabling-gcc_sleep_clk_src.patch b/target/linux/ipq807x/patches-5.10/147-clk-ipq8074-defer-from-disabling-gcc_sleep_clk_src.patch new file mode 100644 index 000000000..8be26fb2d --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/147-clk-ipq8074-defer-from-disabling-gcc_sleep_clk_src.patch @@ -0,0 +1,31 @@ +From db9c60394765843f6a77833bc40c27fac8852e97 Mon Sep 17 00:00:00 2001 +From: Balaji Prakash J +Date: Mon, 20 Apr 2020 20:07:51 +0530 +Subject: [PATCH] clk: ipq8074: defer from disabling gcc_sleep_clk_src + +Added CLK_IS_CRITICAL flag in order to defer from +disabling the sleep clock source. + +Once the usb sleep clocks are disabled, clock framework +is trying to disable the sleep clock source also and +the below warning is observed. + +[ 28.235750] gcc_sleep_clk_src status stuck at 'on' +[ 28.235794] WARNING: CPU: 0 PID: 29 at drivers/clk/qcom/clk-branch.c:92 clk_branch_toggle+0x160/0x178 + +Signed-off-by: Balaji Prakash J +Change-Id: I61fab902375716272ad9c426ce71581058f7bd35 +--- + drivers/clk/qcom/gcc-ipq8074.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -683,6 +683,7 @@ static struct clk_branch gcc_sleep_clk_s + }, + .num_parents = 1, + .ops = &clk_branch2_ops, ++ .flags = CLK_IS_CRITICAL, + }, + }, + }; diff --git a/target/linux/ipq807x/patches-5.10/148-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch b/target/linux/ipq807x/patches-5.10/148-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch new file mode 100644 index 000000000..2c8887e33 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/148-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch @@ -0,0 +1,41 @@ +From 52315bec6ed633b6a71f28b746029602f8bd70b9 Mon Sep 17 00:00:00 2001 +From: Balaji Prakash J +Date: Wed, 22 Apr 2020 20:35:30 +0530 +Subject: [PATCH] clk: ipq8074: fix gcc_blsp1_ahb_clk properties + +All the voting enabled clocks does not support the enable +from CBCR register. So, updated gcc_blsp1_ahb_clk enable +register and mask to enable bit in APCS_CLOCK_BRANCH_ENA_VOTE. + +Also, the voting controlled clocks are shared among multiple +components like APSS, RPM, NSS, TZ, etc. So, turning the +voting off from APSS does not make the clock off if it has +been voted from another component. Added the flag +BRANCH_HALT_VOTED in order to skip checking the clock +disable status. + +This change is referred from the below commits, +1. 246b4fb3af9bd65d8af794aac2f0e7b1ed9cc2dd +2. c8374157d5ae91d3b3e0d513d62808a798b32d3a + +Signed-off-by: Balaji Prakash J +Change-Id: I505cb560b31ad27a02c165fbe13bb33a2fc7d230 +--- + drivers/clk/qcom/gcc-ipq8074.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -2118,9 +2118,10 @@ struct clk_rcg2 adss_pwm_clk_src = { + + static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x01008, ++ .halt_check = BRANCH_HALT_VOTED, + .clkr = { +- .enable_reg = 0x01008, +- .enable_mask = BIT(0), ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", + .parent_names = (const char *[]){ diff --git a/target/linux/ipq807x/patches-5.10/149-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch b/target/linux/ipq807x/patches-5.10/149-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch new file mode 100644 index 000000000..f484b97a7 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/149-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch @@ -0,0 +1,47 @@ +From 256eda666b4687c5242b9f075caf4e09ad642daa Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Fri, 17 Apr 2020 16:37:10 +0530 +Subject: [PATCH] remoteproc: wcss: disable auto boot for IPQ8074 + +auto boot is disabled for IPQ8074 the wifi driver brings up the wcss. + +Signed-off-by: Sivaprakash Murugesan +Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88 +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -161,6 +161,7 @@ struct wcss_data { + const struct rproc_ops *ops; + bool requires_force_stop; + bool need_mem_protection; ++ bool need_auto_boot; + }; + + static int q6v5_wcss_reset(struct q6v5_wcss *wcss) +@@ -1147,6 +1148,7 @@ static int q6v5_wcss_probe(struct platfo + desc->sysmon_name, + desc->ssctl_id); + ++ rproc->auto_boot = desc->need_auto_boot; + ret = rproc_add(rproc); + if (ret) + goto free_rproc; +@@ -1183,6 +1185,7 @@ static const struct wcss_data wcss_ipq80 + .ops = &q6v5_wcss_ipq8074_ops, + .requires_force_stop = true, + .need_mem_protection = true, ++ .need_auto_boot = false, + }; + + static const struct wcss_data wcss_qcs404_res_init = { +@@ -1199,6 +1202,7 @@ static const struct wcss_data wcss_qcs40 + .ssctl_id = 0x12, + .ops = &q6v5_wcss_qcs404_ops, + .requires_force_stop = false, ++ .need_auto_boot = true, + }; + + static const struct of_device_id q6v5_wcss_of_match[] = { diff --git a/target/linux/ipq807x/patches-5.10/150-arm64-dts-ipq8074-add-missing-reserved-memory-nodes.patch b/target/linux/ipq807x/patches-5.10/150-arm64-dts-ipq8074-add-missing-reserved-memory-nodes.patch new file mode 100644 index 000000000..bc0535998 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/150-arm64-dts-ipq8074-add-missing-reserved-memory-nodes.patch @@ -0,0 +1,65 @@ +From 158bd87b3db04bdd1effe4a92424f9572224a6c3 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 15 May 2021 00:09:21 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add missing reserved memory nodes + +Downstream kernel has more reserved memory nodes. +Without these ath11k will cause a board reset. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 36 +++++++++++++++++++++++++-- + 1 file changed, 34 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -96,15 +96,47 @@ + reg = <0x0 0x40000000 0x0 0x01000000>; + }; + +- smem_region: memory@4ab00000 { ++ tzapp: tzapp@4a400000 { ++ no-map; ++ reg = <0x0 0x4a400000 0x0 0x00200000>; ++ }; ++ ++ ++ uboot@4a600000 { ++ no-map; ++ reg = <0x0 0x4a600000 0x0 0x00400000>; ++ }; ++ ++ sbl@4aa00000 { ++ no-map; ++ reg = <0x0 0x4aa00000 0x0 0x00100000>; ++ }; ++ ++ smem_region: smem@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x00100000>; + }; + +- q6_region: memory@4b000000 { ++ tz@4ac00000 { ++ no-map; ++ reg = <0x0 0x4ac00000 0x0 0x00400000>; ++ }; ++ ++ q6_region: wcnss@4b000000 { + no-map; + reg = <0x0 0x4b000000 0x0 0x05f00000>; + }; ++ ++ q6_etr_region: q6_etr_dump@50f00000 { ++ no-map; ++ reg = <0x0 0x50f00000 0x0 0x00100000>; ++ }; ++ ++ m3_dump@51000000 { ++ no-map; ++ reg = <0x0 0x51000000 0x0 0x100000>; ++ }; ++ + }; + + firmware { diff --git a/target/linux/ipq807x/patches-5.10/151-arm64-dts-ipq8074-add-q6_etr-memory-region-to-remote.patch b/target/linux/ipq807x/patches-5.10/151-arm64-dts-ipq8074-add-q6_etr-memory-region-to-remote.patch new file mode 100644 index 000000000..440603585 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/151-arm64-dts-ipq8074-add-q6_etr-memory-region-to-remote.patch @@ -0,0 +1,24 @@ +From 86aa6afcf280a61150a3e6c796f629d09db88d55 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 15 May 2021 00:18:32 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add q6_etr memory region to remoteproc + +Q6v5 remoteprocessor also has a q6_etr memor region +reserved for it, so add it to the node. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -998,7 +998,7 @@ + qcom,smem-state-names = "shutdown", + "stop"; + +- memory-region = <&q6_region>; ++ memory-region = <&q6_region>, <&q6_etr_region>; + + glink-edge { + interrupts = ; diff --git a/target/linux/ipq807x/patches-5.10/152-thermal-qcom-tsens-Add-IPQ8074-support.patch b/target/linux/ipq807x/patches-5.10/152-thermal-qcom-tsens-Add-IPQ8074-support.patch new file mode 100644 index 000000000..9671ad36b --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/152-thermal-qcom-tsens-Add-IPQ8074-support.patch @@ -0,0 +1,99 @@ +From 98130cb1cb992593b050baa9c4d8484d6fd6e8f6 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 20 Nov 2020 13:52:43 +0100 +Subject: [PATCH] thermal: qcom: tsens: Add IPQ8074 support + +Qualcomm IPQ807x SoC-s use tsens v2.3.0 IP, but they +only have one interrupt and not a dedicated critical interrupt. + +Signed-off-by: Robert Marko +--- + drivers/thermal/qcom/tsens-v2.c | 14 ++++++++++++++ + drivers/thermal/qcom/tsens.c | 27 ++++++++++++++++++--------- + drivers/thermal/qcom/tsens.h | 2 +- + 3 files changed, 33 insertions(+), 10 deletions(-) + +--- a/drivers/thermal/qcom/tsens-v2.c ++++ b/drivers/thermal/qcom/tsens-v2.c +@@ -36,6 +36,14 @@ static struct tsens_features tsens_v2_fe + .max_sensors = 16, + }; + ++static struct tsens_features tsens_ipq8074_feat = { ++ .ver_major = VER_2_X, ++ .crit_int = 0, ++ .adc = 0, ++ .srot_split = 1, ++ .max_sensors = 16, ++}; ++ + static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { + /* ----- SROT ------ */ + /* VERSION */ +@@ -101,6 +109,12 @@ struct tsens_plat_data data_tsens_v2 = { + .fields = tsens_v2_regfields, + }; + ++struct tsens_plat_data data_tsens_ipq8074 = { ++ .ops = &ops_generic_v2, ++ .feat = &tsens_ipq8074_feat, ++ .fields = tsens_v2_regfields, ++}; ++ + /* Kept around for backward compatibility with old msm8996.dtsi */ + struct tsens_plat_data data_8996 = { + .num_sensors = 13, +--- a/drivers/thermal/qcom/tsens.c ++++ b/drivers/thermal/qcom/tsens.c +@@ -323,16 +323,22 @@ static int tsens_read_irq_state(struct t + ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask); + if (ret) + return ret; +- ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id], +- &d->crit_irq_clear); +- if (ret) +- return ret; +- ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id], +- &d->crit_irq_mask); +- if (ret) +- return ret; ++ if (priv->feat->crit_int) { ++ ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id], ++ &d->crit_irq_clear); ++ if (ret) ++ return ret; ++ ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id], ++ &d->crit_irq_mask); ++ if (ret) ++ return ret; + +- d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id); ++ d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id); ++ } else { ++ d->crit_irq_clear = 0; ++ d->crit_irq_mask = 0; ++ d->crit_thresh = 0; ++ } + } else { + /* No mask register on older TSENS */ + d->up_irq_mask = 0; +@@ -917,6 +923,9 @@ static const struct of_device_id tsens_t + }, { + .compatible = "qcom,tsens-v2", + .data = &data_tsens_v2, ++ }, { ++ .compatible = "qcom,ipq8074-tsens", ++ .data = &data_tsens_ipq8074, + }, + {} + }; +--- a/drivers/thermal/qcom/tsens.h ++++ b/drivers/thermal/qcom/tsens.h +@@ -591,6 +591,6 @@ extern struct tsens_plat_data data_8916, + extern struct tsens_plat_data data_tsens_v1, data_8976; + + /* TSENS v2 targets */ +-extern struct tsens_plat_data data_8996, data_tsens_v2; ++extern struct tsens_plat_data data_8996, data_tsens_v2, data_tsens_ipq8074; + + #endif /* __QCOM_TSENS_H__ */ diff --git a/target/linux/ipq807x/patches-5.10/153-drivers-thermal-tsens-fix-wrong-check-for-tzd-in-irq.patch b/target/linux/ipq807x/patches-5.10/153-drivers-thermal-tsens-fix-wrong-check-for-tzd-in-irq.patch new file mode 100644 index 000000000..c30371b9f --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/153-drivers-thermal-tsens-fix-wrong-check-for-tzd-in-irq.patch @@ -0,0 +1,37 @@ +From 10f0582cd0f7c1f3387229f5d341a5ef10a53556 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 19 May 2021 00:46:26 +0200 +Subject: [PATCH 1/2] drivers: thermal: tsens: fix wrong check for tzd in irq + handlers + +Some device can have some thermal sensor disabled from the factory. The +current 2 irq handler functions check all the sensor by default and the +check if the sensor was actually registered is wrong. The tzd is +actually never set if the registration fail hence the IS_ERR check is +wrong. + +Signed-off-by: Ansuel Smith +--- + drivers/thermal/qcom/tsens.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/thermal/qcom/tsens.c ++++ b/drivers/thermal/qcom/tsens.c +@@ -421,7 +421,7 @@ static irqreturn_t tsens_critical_irq_th + const struct tsens_sensor *s = &priv->sensor[i]; + u32 hw_id = s->hw_id; + +- if (IS_ERR(s->tzd)) ++ if (!s->tzd) + continue; + if (!tsens_threshold_violated(priv, hw_id, &d)) + continue; +@@ -471,7 +471,7 @@ static irqreturn_t tsens_irq_thread(int + const struct tsens_sensor *s = &priv->sensor[i]; + u32 hw_id = s->hw_id; + +- if (IS_ERR(s->tzd)) ++ if (!s->tzd) + continue; + if (!tsens_threshold_violated(priv, hw_id, &d)) + continue; diff --git a/target/linux/ipq807x/patches-5.10/154-drivers-thermal-tsens-add-timeout-to-get_tem_tsens_v.patch b/target/linux/ipq807x/patches-5.10/154-drivers-thermal-tsens-add-timeout-to-get_tem_tsens_v.patch new file mode 100644 index 000000000..73eaef837 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/154-drivers-thermal-tsens-add-timeout-to-get_tem_tsens_v.patch @@ -0,0 +1,55 @@ +From 47b165aa6ed3b85b793c5bfb27050c93a194c0cc Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 19 May 2021 00:52:21 +0200 +Subject: [PATCH 2/2] drivers: thermal: tsens: add timeout to + get_tem_tsens_valid + +The function can loop and lock the system if for whatever reason the bit +for the target sensor is NEVER valid. This is the case if a sensor is +disabled by the factory and the valid bit is never reported as actually +valid. Add a timeout check and exit if a timeout occurs. As this is +a very rare condition, handle the timeout only if the first read fails. + +Signed-off-by: Ansuel Smith +--- + drivers/thermal/qcom/tsens.c | 23 ++++++++++++++++------- + 1 file changed, 16 insertions(+), 7 deletions(-) + +--- a/drivers/thermal/qcom/tsens.c ++++ b/drivers/thermal/qcom/tsens.c +@@ -587,19 +587,28 @@ int get_temp_tsens_valid(const struct ts + int hw_id = s->hw_id; + u32 temp_idx = LAST_TEMP_0 + hw_id; + u32 valid_idx = VALID_0 + hw_id; ++ unsigned long timeout; + u32 valid; + int ret; + + ret = regmap_field_read(priv->rf[valid_idx], &valid); + if (ret) + return ret; +- while (!valid) { +- /* Valid bit is 0 for 6 AHB clock cycles. +- * At 19.2MHz, 1 AHB clock is ~60ns. +- * We should enter this loop very, very rarely. +- */ +- ndelay(400); +- ret = regmap_field_read(priv->rf[valid_idx], &valid); ++ ++ if (!valid) { ++ timeout = jiffies + msecs_to_jiffies(20); ++ ++ do { ++ /* Valid bit is 0 for 6 AHB clock cycles. ++ * At 19.2MHz, 1 AHB clock is ~60ns. ++ * We should enter this loop very, very rarely. ++ */ ++ ndelay(400); ++ ret = regmap_field_read(priv->rf[valid_idx], &valid); ++ if (valid || ret) ++ break; ++ } while (!(ret = time_after_eq(jiffies, timeout))); ++ + if (ret) + return ret; + } diff --git a/target/linux/ipq807x/patches-5.10/155-arm64-dts-ipq8074-add-thermal-nodes.patch b/target/linux/ipq807x/patches-5.10/155-arm64-dts-ipq8074-add-thermal-nodes.patch new file mode 100644 index 000000000..5170a072d --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/155-arm64-dts-ipq8074-add-thermal-nodes.patch @@ -0,0 +1,167 @@ +From de1ca571d14bab031cc57bab5311db05f33ceec3 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 19 May 2021 00:14:50 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add thermal nodes + +IPQ8074 has a tsens v2.3.0 peripheral which monitors +temperatures around the various subsystems on the +die. + +So, lets add the required nodes for tsens and thermal +zones to enable passive cooling of the device. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 101 ++++++++++++++++++++++++++ + 1 file changed, 101 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -6,6 +6,7 @@ + #include + #include + #include ++#include + #include + + / { +@@ -38,6 +39,7 @@ + clock-names = "cpu"; + next-level-cache = <&L2_0>; + enable-method = "psci"; ++ #cooling-cells = <2>; + }; + + CPU1: cpu@1 { +@@ -48,6 +50,7 @@ + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + next-level-cache = <&L2_0>; ++ #cooling-cells = <2>; + }; + + CPU2: cpu@2 { +@@ -58,6 +61,7 @@ + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + next-level-cache = <&L2_0>; ++ #cooling-cells = <2>; + }; + + CPU3: cpu@3 { +@@ -68,6 +72,7 @@ + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + next-level-cache = <&L2_0>; ++ #cooling-cells = <2>; + }; + + L2_0: l2-cache { +@@ -365,6 +370,16 @@ + status = "disabled"; + }; + ++ tsens: thermal-sensor@4a9000 { ++ compatible = "qcom,ipq8074-tsens"; ++ reg = <0x4a9000 0x1000>, /* TM */ ++ <0x4a8000 0x1000>; /* SROT */ ++ interrupts = ; ++ interrupt-names = "uplow"; ++ #qcom,sensors = <16>; ++ #thermal-sensor-cells = <1>; ++ }; ++ + cryptobam: dma@704000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x00704000 0x20000>; +@@ -1284,4 +1299,90 @@ + #clock-cells = <0>; + }; + }; ++ ++ thermal-zones { ++ nss-top-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 4>; ++ }; ++ ++ nss0-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 5>; ++ }; ++ ++ nss1-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 6>; ++ }; ++ ++ wcss-phya0-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 7>; ++ }; ++ ++ wcss-phya1-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 8>; ++ }; ++ ++ cpu0_thermal: cpu0-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 9>; ++ }; ++ ++ cpu1_thermal: cpu1-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 10>; ++ }; ++ ++ cpu2_thermal: cpu2-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 11>; ++ }; ++ ++ cpu3_thermal: cpu3-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 12>; ++ }; ++ ++ cluster_thermal: cluster-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 13>; ++ }; ++ ++ wcss-phyb0-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 14>; ++ }; ++ ++ wcss-phyb1-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsens 15>; ++ }; ++ }; + }; diff --git a/target/linux/ipq807x/patches-5.10/156-arm64-dts-ipq8074-disable-USB-phy-by-default.patch b/target/linux/ipq807x/patches-5.10/156-arm64-dts-ipq8074-disable-USB-phy-by-default.patch new file mode 100644 index 000000000..8090e0c58 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/156-arm64-dts-ipq8074-disable-USB-phy-by-default.patch @@ -0,0 +1,27 @@ +From c58dea2220d978756a0f7e815bc13dbfa8c33ebc Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 26 May 2021 16:49:02 +0200 +Subject: [PATCH] arm64: dts: ipq8074: disable USB phy by default + +One of the QUSB USB PHY-s has been left enabled by +default, this is probably just a mistake as other +USB PHY-s are disabled by default. + +It makes no sense to have it enabled by default as +not all board implement USB ports, so disable it. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -286,6 +286,7 @@ + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; ++ status = "disabled"; + }; + + qmp_pcie_phy0: phy@84000 { diff --git a/target/linux/ipq807x/patches-5.10/157-arm64-dts-ipq8074-Add-QUP6-I2C-node.patch b/target/linux/ipq807x/patches-5.10/157-arm64-dts-ipq8074-Add-QUP6-I2C-node.patch new file mode 100644 index 000000000..45b5f3352 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/157-arm64-dts-ipq8074-Add-QUP6-I2C-node.patch @@ -0,0 +1,41 @@ +From 9b2aee0e0fd786c6836d1472cd935186b746bc5e Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 13 Jun 2021 12:10:42 +0200 +Subject: [PATCH] arm64: dts: ipq8074: Add QUP6 I2C node + +Add node to support the QUP6 I2C controller inside +of IPQ8074. +It is exactly the same as QUP2 and QUP3 controllers. + +Some routers like Xiaomi AX9000 and Netgear RBK850 +use this bus. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -634,6 +634,21 @@ + status = "disabled"; + }; + ++ blsp1_i2c6: i2c@78ba000 { ++ compatible = "qcom,i2c-qup-v2.2.1"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x078ba000 0x600>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_AHB_CLK>, ++ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; ++ clock-names = "iface", "core"; ++ clock-frequency = <100000>; ++ dmas = <&blsp_dma 23>, <&blsp_dma 22>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ + qpic_bam: dma@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07984000 0x1a000>; diff --git a/target/linux/ipq807x/patches-5.10/158-hwmon-Add-SMSC-EMC2301-2-3-5-fan-controller-driver.patch b/target/linux/ipq807x/patches-5.10/158-hwmon-Add-SMSC-EMC2301-2-3-5-fan-controller-driver.patch new file mode 100644 index 000000000..8af668569 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/158-hwmon-Add-SMSC-EMC2301-2-3-5-fan-controller-driver.patch @@ -0,0 +1,51 @@ +From a58b73b20db06f91025c5c847fcf2b53e341a6ff Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 14 Jun 2021 19:01:14 +0200 +Subject: [PATCH] hwmon: Add SMSC EMC2301/2/3/5 fan controller driver + +Add support for SMSC EMC2305, EMC2303, EMC2302, EMC2301 fan controller +chips. +The driver primary supports the EMC2305 chip which provides RPM-based +PWM control and monitoring for up to 5 fans. + +According to the SMSC data sheets the EMC2303, EMC2302 and EMC2301 chips +have basically the same functionality and register layout, but support +less fans and (in case of EMC2302 and EMC2301) less possible I2C addresses. +The driver supports them, too. + +Signed-off-by: Robert Marko +--- + drivers/hwmon/Kconfig | 11 +++++++++++ + drivers/hwmon/Makefile | 1 + + 2 files changed, 12 insertions(+) + +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -1601,6 +1601,17 @@ config SENSORS_EMC2103 + This driver can also be built as a module. If so, the module + will be called emc2103. + ++config SENSORS_EMC2305 ++ tristate "SMSC EMC2305" ++ depends on I2C ++ select REGMAP_I2C ++ help ++ If you say yes here you get support for the fan monitoring ++ and control features of the SMSC EMC2301/2/3/5 chips. ++ ++ This driver can also be built as a module. If so, the module ++ will be called emc2305. ++ + config SENSORS_EMC6W201 + tristate "SMSC EMC6W201" + depends on I2C +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -66,6 +66,7 @@ obj-$(CONFIG_SENSORS_DS620) += ds620.o + obj-$(CONFIG_SENSORS_DS1621) += ds1621.o + obj-$(CONFIG_SENSORS_EMC1403) += emc1403.o + obj-$(CONFIG_SENSORS_EMC2103) += emc2103.o ++obj-$(CONFIG_SENSORS_EMC2305) += emc2305.o + obj-$(CONFIG_SENSORS_EMC6W201) += emc6w201.o + obj-$(CONFIG_SENSORS_F71805F) += f71805f.o + obj-$(CONFIG_SENSORS_F71882FG) += f71882fg.o diff --git a/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch b/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch new file mode 100644 index 000000000..a0931ff52 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch @@ -0,0 +1,742 @@ +--- a/net/netfilter/nf_conntrack_proto_tcp.c ++++ b/net/netfilter/nf_conntrack_proto_tcp.c +@@ -32,12 +32,14 @@ + #include + + /* Do not check the TCP window for incoming packets */ +-static int nf_ct_tcp_no_window_check __read_mostly = 1; ++int nf_ct_tcp_no_window_check __read_mostly = 1; ++EXPORT_SYMBOL_GPL(nf_ct_tcp_no_window_check); + + /* "Be conservative in what you do, + be liberal in what you accept from others." + If it's non-zero, we mark only out of window RST segments as INVALID. */ +-static int nf_ct_tcp_be_liberal __read_mostly = 0; ++int nf_ct_tcp_be_liberal __read_mostly = 0; ++EXPORT_SYMBOL_GPL(nf_ct_tcp_be_liberal); + + /* If it is set to zero, we disable picking up already established + connections. */ +--- a/include/linux/if_bridge.h ++++ b/include/linux/if_bridge.h +@@ -60,6 +60,9 @@ struct br_ip_list { + #define BR_DEFAULT_AGEING_TIME (300 * HZ) + + extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *)); ++extern void br_dev_update_stats(struct net_device *dev, ++ struct rtnl_link_stats64 *nlstats); ++extern bool br_is_hairpin_enabled(struct net_device *dev); + + #if IS_ENABLED(CONFIG_BRIDGE) && IS_ENABLED(CONFIG_BRIDGE_IGMP_SNOOPING) + int br_multicast_list_adjacent(struct net_device *dev, +@@ -155,4 +158,41 @@ br_port_flag_is_set(const struct net_dev + } + #endif + ++/* QCA NSS ECM support - Start */ ++extern struct net_device *br_port_dev_get(struct net_device *dev, ++ unsigned char *addr, ++ struct sk_buff *skb, ++ unsigned int cookie); ++extern void br_refresh_fdb_entry(struct net_device *dev, const char *addr); ++extern struct net_bridge_fdb_entry *br_fdb_has_entry(struct net_device *dev, ++ const char *addr, ++ __u16 vid); ++extern void br_fdb_update_register_notify(struct notifier_block *nb); ++extern void br_fdb_update_unregister_notify(struct notifier_block *nb); ++ ++typedef struct net_bridge_port *br_port_dev_get_hook_t(struct net_device *dev, ++ struct sk_buff *skb, ++ unsigned char *addr, ++ unsigned int cookie); ++extern br_port_dev_get_hook_t __rcu *br_port_dev_get_hook; ++ ++#define BR_FDB_EVENT_ADD 0x01 ++#define BR_FDB_EVENT_DEL 0x02 ++ ++struct br_fdb_event { ++ struct net_device *dev; ++ unsigned char addr[6]; ++ unsigned char is_local; ++ struct net_bridge *br; ++ struct net_device *orig_dev; ++}; ++extern void br_fdb_register_notify(struct notifier_block *nb); ++extern void br_fdb_unregister_notify(struct notifier_block *nb); ++ ++typedef struct net_bridge_port *br_get_dst_hook_t( ++ const struct net_bridge_port *src, ++ struct sk_buff **skb); ++extern br_get_dst_hook_t __rcu *br_get_dst_hook; ++/* QCA NSS ECM support - End */ ++ + #endif +--- a/include/linux/if_vlan.h ++++ b/include/linux/if_vlan.h +@@ -222,7 +222,28 @@ extern void vlan_vids_del_by_dev(struct + + extern bool vlan_uses_dev(const struct net_device *dev); + ++/* QCA NSS ECM support - Start */ ++extern void __vlan_dev_update_accel_stats(struct net_device *dev, ++ struct rtnl_link_stats64 *stats); ++extern u16 vlan_dev_get_egress_prio(struct net_device *dev, u32 skb_prio); ++extern struct net_device *vlan_dev_next_dev(const struct net_device *dev); ++/* QCA NSS ECM support - End */ ++ + #else ++/* QCA NSS ECM support - Start */ ++static inline void __vlan_dev_update_accel_stats(struct net_device *dev, ++ struct rtnl_link_stats64 *stats) ++{ ++ ++} ++ ++static inline u16 vlan_dev_get_egress_prio(struct net_device *dev, ++ u32 skb_prio) ++{ ++ return 0; ++} ++/* QCA NSS ECM support - End */ ++ + static inline struct net_device * + __vlan_find_dev_deep_rcu(struct net_device *real_dev, + __be16 vlan_proto, u16 vlan_id) +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -2745,6 +2745,10 @@ enum netdev_cmd { + NETDEV_CVLAN_FILTER_DROP_INFO, + NETDEV_SVLAN_FILTER_PUSH_INFO, + NETDEV_SVLAN_FILTER_DROP_INFO, ++ /* QCA NSS ECM Support - Start */ ++ NETDEV_BR_JOIN, ++ NETDEV_BR_LEAVE, ++ /* QCA NSS ECM Support - End */ + }; + const char *netdev_cmd_to_name(enum netdev_cmd cmd); + +--- a/include/net/ip6_route.h ++++ b/include/net/ip6_route.h +@@ -210,6 +210,11 @@ void rt6_multipath_rebalance(struct fib6 + void rt6_uncached_list_add(struct rt6_info *rt); + void rt6_uncached_list_del(struct rt6_info *rt); + ++/* QCA NSS ECM support - Start */ ++int rt6_register_notifier(struct notifier_block *nb); ++int rt6_unregister_notifier(struct notifier_block *nb); ++/* QCA NSS ECM support - End */ ++ + static inline const struct rt6_info *skb_rt6_info(const struct sk_buff *skb) + { + const struct dst_entry *dst = skb_dst(skb); +--- a/include/net/neighbour.h ++++ b/include/net/neighbour.h +@@ -568,4 +568,15 @@ static inline void neigh_update_is_route + *notify = 1; + } + } ++ ++/* QCA NSS ECM support - Start */ ++struct neigh_mac_update { ++ unsigned char old_mac[ALIGN(MAX_ADDR_LEN, sizeof(unsigned long))]; ++ unsigned char update_mac[ALIGN(MAX_ADDR_LEN, sizeof(unsigned long))]; ++}; ++ ++extern void neigh_mac_update_register_notify(struct notifier_block *nb); ++extern void neigh_mac_update_unregister_notify(struct notifier_block *nb); ++/* QCA NSS ECM support - End */ ++ + #endif +--- a/include/net/route.h ++++ b/include/net/route.h +@@ -234,6 +234,11 @@ struct rtable *rt_dst_alloc(struct net_d + bool nopolicy, bool noxfrm); + struct rtable *rt_dst_clone(struct net_device *dev, struct rtable *rt); + ++/* QCA NSS ECM support - Start */ ++int ip_rt_register_notifier(struct notifier_block *nb); ++int ip_rt_unregister_notifier(struct notifier_block *nb); ++/* QCA NSS ECM support - End */ ++ + struct in_ifaddr; + void fib_add_ifaddr(struct in_ifaddr *); + void fib_del_ifaddr(struct in_ifaddr *, struct in_ifaddr *); +--- a/net/8021q/vlan_core.c ++++ b/net/8021q/vlan_core.c +@@ -550,4 +550,52 @@ static int __init vlan_offload_init(void + return 0; + } + ++/* QCA NSS ECM support - Start */ ++/* Update the VLAN device with statistics from network offload engines */ ++void __vlan_dev_update_accel_stats(struct net_device *dev, ++ struct rtnl_link_stats64 *nlstats) ++{ ++ struct vlan_pcpu_stats *stats; ++ ++ if (!is_vlan_dev(dev)) ++ return; ++ ++ stats = per_cpu_ptr(vlan_dev_priv(dev)->vlan_pcpu_stats, 0); ++ ++ u64_stats_update_begin(&stats->syncp); ++ stats->rx_packets += nlstats->rx_packets; ++ stats->rx_bytes += nlstats->rx_bytes; ++ stats->tx_packets += nlstats->tx_packets; ++ stats->tx_bytes += nlstats->tx_bytes; ++ u64_stats_update_end(&stats->syncp); ++} ++EXPORT_SYMBOL(__vlan_dev_update_accel_stats); ++ ++/* Lookup the 802.1p egress_map table and return the 802.1p value */ ++u16 vlan_dev_get_egress_prio(struct net_device *dev, u32 skb_prio) ++{ ++ struct vlan_priority_tci_mapping *mp; ++ ++ mp = vlan_dev_priv(dev)->egress_priority_map[(skb_prio & 0xf)]; ++ while (mp) { ++ if (mp->priority == skb_prio) { ++ /* This should already be shifted ++ * to mask correctly with the ++ * VLAN's TCI ++ */ ++ return mp->vlan_qos; ++ } ++ mp = mp->next; ++ } ++ return 0; ++} ++EXPORT_SYMBOL(vlan_dev_get_egress_prio); ++ ++struct net_device *vlan_dev_next_dev(const struct net_device *dev) ++{ ++ return vlan_dev_priv(dev)->real_dev; ++} ++EXPORT_SYMBOL(vlan_dev_next_dev); ++/* QCA NSS ECM support - End */ ++ + fs_initcall(vlan_offload_init); +--- a/net/bridge/br_fdb.c ++++ b/net/bridge/br_fdb.c +@@ -37,6 +37,35 @@ static int fdb_insert(struct net_bridge + static void fdb_notify(struct net_bridge *br, + const struct net_bridge_fdb_entry *, int, bool); + ++/* QCA NSS ECM support - Start */ ++ATOMIC_NOTIFIER_HEAD(br_fdb_notifier_list); ++ATOMIC_NOTIFIER_HEAD(br_fdb_update_notifier_list); ++ ++void br_fdb_register_notify(struct notifier_block *nb) ++{ ++ atomic_notifier_chain_register(&br_fdb_notifier_list, nb); ++} ++EXPORT_SYMBOL_GPL(br_fdb_register_notify); ++ ++void br_fdb_unregister_notify(struct notifier_block *nb) ++{ ++ atomic_notifier_chain_unregister(&br_fdb_notifier_list, nb); ++} ++EXPORT_SYMBOL_GPL(br_fdb_unregister_notify); ++ ++void br_fdb_update_register_notify(struct notifier_block *nb) ++{ ++ atomic_notifier_chain_register(&br_fdb_update_notifier_list, nb); ++} ++EXPORT_SYMBOL_GPL(br_fdb_update_register_notify); ++ ++void br_fdb_update_unregister_notify(struct notifier_block *nb) ++{ ++ atomic_notifier_chain_unregister(&br_fdb_update_notifier_list, nb); ++} ++EXPORT_SYMBOL_GPL(br_fdb_update_unregister_notify); ++/* QCA NSS ECM support - End */ ++ + int __init br_fdb_init(void) + { + br_fdb_cache = kmem_cache_create("bridge_fdb_cache", +@@ -342,6 +371,7 @@ void br_fdb_cleanup(struct work_struct * + unsigned long delay = hold_time(br); + unsigned long work_delay = delay; + unsigned long now = jiffies; ++ u8 mac_addr[6]; /* QCA NSS ECM support */ + + /* this part is tricky, in order to avoid blocking learning and + * consequently forwarding, we rely on rcu to delete objects with +@@ -368,8 +398,15 @@ void br_fdb_cleanup(struct work_struct * + work_delay = min(work_delay, this_timer - now); + } else { + spin_lock_bh(&br->hash_lock); +- if (!hlist_unhashed(&f->fdb_node)) ++ if (!hlist_unhashed(&f->fdb_node)) { ++ ether_addr_copy(mac_addr, f->key.addr.addr); + fdb_delete(br, f, true); ++ /* QCA NSS ECM support - Start */ ++ atomic_notifier_call_chain( ++ &br_fdb_update_notifier_list, 0, ++ (void *)mac_addr); ++ /* QCA NSS ECM support - End */ ++ } + spin_unlock_bh(&br->hash_lock); + } + } +@@ -610,6 +647,12 @@ void br_fdb_update(struct net_bridge *br + &fdb->flags))) + clear_bit(BR_FDB_ADDED_BY_EXT_LEARN, + &fdb->flags); ++ ++ /* QCA NSS ECM support - Start */ ++ atomic_notifier_call_chain( ++ &br_fdb_update_notifier_list, ++ 0, (void *)addr); ++ /* QCA NSS ECM support - End */ + } + + if (unlikely(test_bit(BR_FDB_ADDED_BY_USER, &flags))) +@@ -734,6 +777,25 @@ static void fdb_notify(struct net_bridge + struct sk_buff *skb; + int err = -ENOBUFS; + ++ /* QCA NSS ECM support - Start */ ++ if (fdb->dst) { ++ int event; ++ struct br_fdb_event fdb_event; ++ ++ if (type == RTM_NEWNEIGH) ++ event = BR_FDB_EVENT_ADD; ++ else ++ event = BR_FDB_EVENT_DEL; ++ ++ fdb_event.dev = fdb->dst->dev; ++ ether_addr_copy(fdb_event.addr, fdb->key.addr.addr); ++ fdb_event.is_local = test_bit(BR_FDB_LOCAL, &fdb->flags); ++ atomic_notifier_call_chain(&br_fdb_notifier_list, ++ event, ++ (void *)&fdb_event); ++ } ++ /* QCA NSS ECM support - End */ ++ + if (swdev_notify) + br_switchdev_fdb_notify(br, fdb, type); + +@@ -1302,3 +1364,44 @@ void br_fdb_clear_offload(const struct n + spin_unlock_bh(&p->br->hash_lock); + } + EXPORT_SYMBOL_GPL(br_fdb_clear_offload); ++ ++/* QCA NSS ECM support - Start */ ++/* Refresh FDB entries for bridge packets being forwarded by offload engines */ ++void br_refresh_fdb_entry(struct net_device *dev, const char *addr) ++{ ++ struct net_bridge_port *p = br_port_get_rcu(dev); ++ ++ if (!p || p->state == BR_STATE_DISABLED) ++ return; ++ ++ if (!is_valid_ether_addr(addr)) { ++ pr_info("bridge: Attempt to refresh with invalid ether address %pM\n", ++ addr); ++ return; ++ } ++ ++ rcu_read_lock(); ++ br_fdb_update(p->br, p, addr, 0, true); ++ rcu_read_unlock(); ++} ++EXPORT_SYMBOL_GPL(br_refresh_fdb_entry); ++ ++/* Look up the MAC address in the device's bridge fdb table */ ++struct net_bridge_fdb_entry *br_fdb_has_entry(struct net_device *dev, ++ const char *addr, __u16 vid) ++{ ++ struct net_bridge_port *p = br_port_get_rcu(dev); ++ struct net_bridge_fdb_entry *fdb; ++ ++ if (!p || p->state == BR_STATE_DISABLED) ++ return NULL; ++ ++ rcu_read_lock(); ++ fdb = fdb_find_rcu(&p->br->fdb_hash_tbl, addr, vid); ++ rcu_read_unlock(); ++ ++ return fdb; ++} ++EXPORT_SYMBOL_GPL(br_fdb_has_entry); ++/* QCA NSS ECM support - End */ ++ +--- a/net/bridge/br_if.c ++++ b/net/bridge/br_if.c +@@ -26,6 +26,12 @@ + + #include "br_private.h" + ++/* QCA NSS ECM support - Start */ ++/* Hook for external forwarding logic */ ++br_port_dev_get_hook_t __rcu *br_port_dev_get_hook __read_mostly; ++EXPORT_SYMBOL_GPL(br_port_dev_get_hook); ++/* QCA NSS ECM support - End */ ++ + /* + * Determine initial path cost based on speed. + * using recommendations from 802.1d standard +@@ -697,6 +703,8 @@ int br_add_if(struct net_bridge *br, str + + kobject_uevent(&p->kobj, KOBJ_ADD); + ++ call_netdevice_notifiers(NETDEV_BR_JOIN, dev); /* QCA NSS ECM support */ ++ + return 0; + + err7: +@@ -730,6 +738,8 @@ int br_del_if(struct net_bridge *br, str + if (!p || p->br != br) + return -EINVAL; + ++ call_netdevice_notifiers(NETDEV_BR_LEAVE, dev); /* QCA NSS ECM support */ ++ + /* Since more than one interface can be attached to a bridge, + * there still maybe an alternate path for netconsole to use; + * therefore there is no reason for a NETDEV_RELEASE event. +@@ -773,3 +783,98 @@ bool br_port_flag_is_set(const struct ne + return p->flags & flag; + } + EXPORT_SYMBOL_GPL(br_port_flag_is_set); ++ ++/* QCA NSS ECM support - Start */ ++/* Update bridge statistics for bridge packets processed by offload engines */ ++void br_dev_update_stats(struct net_device *dev, ++ struct rtnl_link_stats64 *nlstats) ++{ ++ struct net_bridge *br; ++ struct pcpu_sw_netstats *stats; ++ ++ /* Is this a bridge? */ ++ if (!(dev->priv_flags & IFF_EBRIDGE)) ++ return; ++ ++ br = netdev_priv(dev); ++ stats = this_cpu_ptr(br->stats); ++ ++ u64_stats_update_begin(&stats->syncp); ++ stats->rx_packets += nlstats->rx_packets; ++ stats->rx_bytes += nlstats->rx_bytes; ++ stats->tx_packets += nlstats->tx_packets; ++ stats->tx_bytes += nlstats->tx_bytes; ++ u64_stats_update_end(&stats->syncp); ++} ++EXPORT_SYMBOL_GPL(br_dev_update_stats); ++ ++/* API to know if hairpin feature is enabled/disabled on this bridge port */ ++bool br_is_hairpin_enabled(struct net_device *dev) ++{ ++ struct net_bridge_port *port = br_port_get_check_rcu(dev); ++ ++ if (likely(port)) ++ return port->flags & BR_HAIRPIN_MODE; ++ return false; ++} ++EXPORT_SYMBOL_GPL(br_is_hairpin_enabled); ++ ++/* br_port_dev_get() ++ * If a skb is provided, and the br_port_dev_get_hook_t hook exists, ++ * use that to try and determine the egress port for that skb. ++ * If not, or no egress port could be determined, use the given addr ++ * to identify the port to which it is reachable, ++ * returing a reference to the net device associated with that port. ++ * ++ * NOTE: Return NULL if given dev is not a bridge or the mac has no ++ * associated port. ++ */ ++struct net_device *br_port_dev_get(struct net_device *dev, unsigned char *addr, ++ struct sk_buff *skb, ++ unsigned int cookie) ++{ ++ struct net_bridge_fdb_entry *fdbe; ++ struct net_bridge *br; ++ struct net_device *netdev = NULL; ++ ++ /* Is this a bridge? */ ++ if (!(dev->priv_flags & IFF_EBRIDGE)) ++ return NULL; ++ ++ rcu_read_lock(); ++ ++ /* If the hook exists and the skb isn't NULL, try and get the port */ ++ if (skb) { ++ br_port_dev_get_hook_t *port_dev_get_hook; ++ ++ port_dev_get_hook = rcu_dereference(br_port_dev_get_hook); ++ if (port_dev_get_hook) { ++ struct net_bridge_port *pdst = ++ __br_get(port_dev_get_hook, NULL, dev, skb, ++ addr, cookie); ++ if (pdst) { ++ dev_hold(pdst->dev); ++ netdev = pdst->dev; ++ goto out; ++ } ++ } ++ } ++ ++ /* Either there is no hook, or can't ++ * determine the port to use - fall back to using FDB ++ */ ++ ++ br = netdev_priv(dev); ++ ++ /* Lookup the fdb entry and get reference to the port dev */ ++ fdbe = br_fdb_find_rcu(br, addr, 0); ++ if (fdbe && fdbe->dst) { ++ netdev = fdbe->dst->dev; /* port device */ ++ dev_hold(netdev); ++ } ++out: ++ rcu_read_unlock(); ++ return netdev; ++} ++EXPORT_SYMBOL_GPL(br_port_dev_get); ++/* QCA NSS ECM support - End */ +--- a/net/bridge/br_private.h ++++ b/net/bridge/br_private.h +@@ -1593,4 +1593,9 @@ void br_do_proxy_suppress_arp(struct sk_ + void br_do_suppress_nd(struct sk_buff *skb, struct net_bridge *br, + u16 vid, struct net_bridge_port *p, struct nd_msg *msg); + struct nd_msg *br_is_nd_neigh_msg(struct sk_buff *skb, struct nd_msg *m); ++ ++/* QCA NSS ECM support - Start */ ++#define __br_get(__hook, __default, __args ...) \ ++ (__hook ? (__hook(__args)) : (__default)) ++/* QCA NSS ECM support - End */ + #endif +--- a/net/core/neighbour.c ++++ b/net/core/neighbour.c +@@ -1210,7 +1210,21 @@ static void neigh_update_hhs(struct neig + } + } + ++/* QCA NSS ECM support - start */ ++ATOMIC_NOTIFIER_HEAD(neigh_mac_update_notifier_list); ++ ++void neigh_mac_update_register_notify(struct notifier_block *nb) ++{ ++ atomic_notifier_chain_register(&neigh_mac_update_notifier_list, nb); ++} ++EXPORT_SYMBOL_GPL(neigh_mac_update_register_notify); + ++void neigh_mac_update_unregister_notify(struct notifier_block *nb) ++{ ++ atomic_notifier_chain_unregister(&neigh_mac_update_notifier_list, nb); ++} ++EXPORT_SYMBOL_GPL(neigh_mac_update_unregister_notify); ++/* QCA NSS ECM support - End */ + + /* Generic update routine. + -- lladdr is new lladdr or NULL, if it is not supplied. +@@ -1241,6 +1255,7 @@ static int __neigh_update(struct neighbo + int notify = 0; + struct net_device *dev; + int update_isrouter = 0; ++ struct neigh_mac_update nmu; /* QCA NSS ECM support */ + + trace_neigh_update(neigh, lladdr, new, flags, nlmsg_pid); + +@@ -1255,6 +1270,8 @@ static int __neigh_update(struct neighbo + new = old; + goto out; + } ++ memset(&nmu, 0, sizeof(struct neigh_mac_update)); /* QCA NSS ECM support */ ++ + if (!(flags & NEIGH_UPDATE_F_ADMIN) && + (old & (NUD_NOARP | NUD_PERMANENT))) + goto out; +@@ -1286,6 +1303,11 @@ static int __neigh_update(struct neighbo + - compare new & old + - if they are different, check override flag + */ ++ /* QCA NSS ECM update - Start */ ++ memcpy(nmu.old_mac, neigh->ha, dev->addr_len); ++ memcpy(nmu.update_mac, lladdr, dev->addr_len); ++ /* QCA NSS ECM update - End */ ++ + if ((old & NUD_VALID) && + !memcmp(lladdr, neigh->ha, dev->addr_len)) + lladdr = neigh->ha; +@@ -1408,8 +1430,11 @@ out: + if (((new ^ old) & NUD_PERMANENT) || ext_learn_change) + neigh_update_gc_list(neigh); + +- if (notify) ++ if (notify) { + neigh_update_notify(neigh, nlmsg_pid); ++ atomic_notifier_call_chain(&neigh_mac_update_notifier_list, 0, ++ (struct neigh_mac_update *)&nmu); /* QCA NSS ECM support */ ++ } + + trace_neigh_update_done(neigh, err); + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -1164,6 +1164,9 @@ static bool fib_valid_key_len(u32 key, u + static void fib_remove_alias(struct trie *t, struct key_vector *tp, + struct key_vector *l, struct fib_alias *old); + ++/* Define route change notification chain. */ ++static BLOCKING_NOTIFIER_HEAD(iproute_chain); /* QCA NSS ECM support */ ++ + /* Caller must hold RTNL. */ + int fib_table_insert(struct net *net, struct fib_table *tb, + struct fib_config *cfg, struct netlink_ext_ack *extack) +@@ -1352,6 +1355,9 @@ int fib_table_insert(struct net *net, st + rtmsg_fib(RTM_NEWROUTE, htonl(key), new_fa, plen, new_fa->tb_id, + &cfg->fc_nlinfo, nlflags); + succeeded: ++ blocking_notifier_call_chain(&iproute_chain, ++ RTM_NEWROUTE, fi); ++ + return 0; + + out_remove_new_fa: +@@ -1722,6 +1728,9 @@ int fib_table_delete(struct net *net, st + if (fa_to_delete->fa_state & FA_S_ACCESSED) + rt_cache_flush(cfg->fc_nlinfo.nl_net); + ++ blocking_notifier_call_chain(&iproute_chain, ++ RTM_DELROUTE, fa_to_delete->fa_info); ++ + fib_release_info(fa_to_delete->fa_info); + alias_free_mem_rcu(fa_to_delete); + return 0; +@@ -2358,6 +2367,20 @@ void __init fib_trie_init(void) + 0, SLAB_PANIC, NULL); + } + ++/* QCA NSS ECM support - Start */ ++int ip_rt_register_notifier(struct notifier_block *nb) ++{ ++ return blocking_notifier_chain_register(&iproute_chain, nb); ++} ++EXPORT_SYMBOL(ip_rt_register_notifier); ++ ++int ip_rt_unregister_notifier(struct notifier_block *nb) ++{ ++ return blocking_notifier_chain_unregister(&iproute_chain, nb); ++} ++EXPORT_SYMBOL(ip_rt_unregister_notifier); ++/* QCA NSS ECM support - End */ ++ + struct fib_table *fib_trie_table(u32 id, struct fib_table *alias) + { + struct fib_table *tb; +--- a/include/net/addrconf.h ++++ b/include/net/addrconf.h +@@ -501,4 +501,9 @@ int if6_proc_init(void); + void if6_proc_exit(void); + #endif + ++/* QCA NSS ECM support - Start */ ++struct net_device *ipv6_dev_find_and_hold(struct net *net, struct in6_addr *addr, ++ int strict); ++/* QCA NSS ECM support - End */ ++ + #endif +--- a/net/ipv6/addrconf.c ++++ b/net/ipv6/addrconf.c +@@ -7233,3 +7233,35 @@ void addrconf_cleanup(void) + + destroy_workqueue(addrconf_wq); + } ++ ++/* QCA NSS ECM support - Start */ ++/* ipv6_dev_find_and_hold() ++ * Find (and hold) net device that has the given address. ++ * Or NULL on failure. ++ */ ++struct net_device *ipv6_dev_find_and_hold(struct net *net, struct in6_addr *addr, ++ int strict) ++{ ++ struct inet6_ifaddr *ifp; ++ struct net_device *dev; ++ ++ ifp = ipv6_get_ifaddr(net, addr, NULL, strict); ++ if (!ifp) ++ return NULL; ++ ++ if (!ifp->idev) { ++ in6_ifa_put(ifp); ++ return NULL; ++ } ++ ++ dev = ifp->idev->dev; ++ if (dev) ++ dev_hold(dev); ++ ++ in6_ifa_put(ifp); ++ ++ return dev; ++} ++EXPORT_SYMBOL(ipv6_dev_find_and_hold); ++/* QCA NSS ECM support - End */ ++ +--- a/net/ipv6/ndisc.c ++++ b/net/ipv6/ndisc.c +@@ -649,6 +649,7 @@ void ndisc_send_ns(struct net_device *de + + ndisc_send_skb(skb, daddr, saddr); + } ++EXPORT_SYMBOL(ndisc_send_ns); + + void ndisc_send_rs(struct net_device *dev, const struct in6_addr *saddr, + const struct in6_addr *daddr) +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -3737,6 +3737,9 @@ out_free: + return ERR_PTR(err); + } + ++/* Define route change notification chain. */ ++ATOMIC_NOTIFIER_HEAD(ip6route_chain); /* QCA NSS ECM support */ ++ + int ip6_route_add(struct fib6_config *cfg, gfp_t gfp_flags, + struct netlink_ext_ack *extack) + { +@@ -3748,6 +3751,10 @@ int ip6_route_add(struct fib6_config *cf + return PTR_ERR(rt); + + err = __ip6_ins_rt(rt, &cfg->fc_nlinfo, extack); ++ if (!err) ++ atomic_notifier_call_chain(&ip6route_chain, ++ RTM_NEWROUTE, rt); ++ + fib6_info_release(rt); + + return err; +@@ -3769,6 +3776,9 @@ static int __ip6_del_rt(struct fib6_info + err = fib6_del(rt, info); + spin_unlock_bh(&table->tb6_lock); + ++ if (!err) ++ atomic_notifier_call_chain(&ip6route_chain, ++ RTM_DELROUTE, rt); + out: + fib6_info_release(rt); + return err; +@@ -6120,6 +6130,20 @@ static int ip6_route_dev_notify(struct n + return NOTIFY_OK; + } + ++/* QCA NSS ECM support - Start */ ++int rt6_register_notifier(struct notifier_block *nb) ++{ ++ return atomic_notifier_chain_register(&ip6route_chain, nb); ++} ++EXPORT_SYMBOL(rt6_register_notifier); ++ ++int rt6_unregister_notifier(struct notifier_block *nb) ++{ ++ return atomic_notifier_chain_unregister(&ip6route_chain, nb); ++} ++EXPORT_SYMBOL(rt6_unregister_notifier); ++/* QCA NSS ECM support - End */ ++ + /* + * /proc + */ diff --git a/target/linux/ipq807x/patches-5.10/601-netfilter-export-udp_get_timeouts-function.patch b/target/linux/ipq807x/patches-5.10/601-netfilter-export-udp_get_timeouts-function.patch new file mode 100644 index 000000000..7e43c853d --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/601-netfilter-export-udp_get_timeouts-function.patch @@ -0,0 +1,38 @@ +From e38488fd0a8a11b4bae4ccad9a7a8cfcf9eb5ab7 Mon Sep 17 00:00:00 2001 +From: Murat Sezgin +Date: Mon, 6 Apr 2020 11:08:09 -0700 +Subject: [PATCH] netfilter: export udp_get_timeouts function + +This function is required for acceleration support. + +Signed-off-by: Murat Sezgin +Change-Id: Ibca4f402735764e7e6fb3ce2678e670753c6ef9c +--- + include/net/netfilter/nf_conntrack_timeout.h | 1 + + net/netfilter/nf_conntrack_proto_udp.c | 3 ++- + 2 files changed, 3 insertions(+), 1 deletion(-) + +--- a/include/net/netfilter/nf_conntrack_timeout.h ++++ b/include/net/netfilter/nf_conntrack_timeout.h +@@ -123,5 +123,6 @@ static inline void nf_ct_destroy_timeout + extern struct nf_ct_timeout *(*nf_ct_timeout_find_get_hook)(struct net *net, const char *name); + extern void (*nf_ct_timeout_put_hook)(struct nf_ct_timeout *timeout); + #endif ++extern unsigned int *udp_get_timeouts(struct net *net); + + #endif /* _NF_CONNTRACK_TIMEOUT_H */ +--- a/net/netfilter/nf_conntrack_proto_udp.c ++++ b/net/netfilter/nf_conntrack_proto_udp.c +@@ -29,10 +29,11 @@ static const unsigned int udp_timeouts[U + [UDP_CT_REPLIED] = 120*HZ, + }; + +-static unsigned int *udp_get_timeouts(struct net *net) ++unsigned int *udp_get_timeouts(struct net *net) + { + return nf_udp_pernet(net)->timeouts; + } ++EXPORT_SYMBOL(udp_get_timeouts); + + static void udp_error_log(const struct sk_buff *skb, + const struct nf_hook_state *state, diff --git a/target/linux/ipq807x/patches-5.10/602-qca-add-pppoe-offload-support.patch b/target/linux/ipq807x/patches-5.10/602-qca-add-pppoe-offload-support.patch new file mode 100644 index 000000000..b75327bf2 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/602-qca-add-pppoe-offload-support.patch @@ -0,0 +1,588 @@ +--- a/drivers/net/ppp/ppp_generic.c ++++ b/drivers/net/ppp/ppp_generic.c +@@ -48,6 +48,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -250,6 +251,25 @@ struct ppp_net { + #define seq_before(a, b) ((s32)((a) - (b)) < 0) + #define seq_after(a, b) ((s32)((a) - (b)) > 0) + ++ ++/* ++ * Registration/Unregistration methods ++ * for PPP channel connect and disconnect event notifications. ++ */ ++RAW_NOTIFIER_HEAD(ppp_channel_connection_notifier_list); ++ ++void ppp_channel_connection_register_notify(struct notifier_block *nb) ++{ ++ raw_notifier_chain_register(&ppp_channel_connection_notifier_list, nb); ++} ++EXPORT_SYMBOL_GPL(ppp_channel_connection_register_notify); ++ ++void ppp_channel_connection_unregister_notify(struct notifier_block *nb) ++{ ++ raw_notifier_chain_unregister(&ppp_channel_connection_notifier_list, nb); ++} ++EXPORT_SYMBOL_GPL(ppp_channel_connection_unregister_notify); ++ + /* Prototypes. */ + static int ppp_unattached_ioctl(struct net *net, struct ppp_file *pf, + struct file *file, unsigned int cmd, unsigned long arg); +@@ -3283,7 +3303,10 @@ ppp_connect_channel(struct channel *pch, + struct ppp_net *pn; + int ret = -ENXIO; + int hdrlen; ++ int ppp_proto; ++ int version; + ++ int notify = 0; + pn = ppp_pernet(pch->chan_net); + + mutex_lock(&pn->all_ppp_mutex); +@@ -3314,13 +3337,40 @@ ppp_connect_channel(struct channel *pch, + ++ppp->n_channels; + pch->ppp = ppp; + refcount_inc(&ppp->file.refcnt); ++ ++ /* Set the netdev priv flag if the prototype ++ * is L2TP or PPTP. Return success in all cases ++ */ ++ if (!pch->chan) ++ goto out2; ++ ++ ppp_proto = ppp_channel_get_protocol(pch->chan); ++ if (ppp_proto == PX_PROTO_PPTP) { ++ ppp->dev->priv_flags_ext |= IFF_EXT_PPP_PPTP; ++ } else if (ppp_proto == PX_PROTO_OL2TP) { ++ version = ppp_channel_get_proto_version(pch->chan); ++ if (version == 2) ++ ppp->dev->priv_flags_ext |= IFF_EXT_PPP_L2TPV2; ++ else if (version == 3) ++ ppp->dev->priv_flags_ext |= IFF_EXT_PPP_L2TPV3; ++ } ++ notify = 1; ++ ++ out2: + ppp_unlock(ppp); + ret = 0; +- + outl: + write_unlock_bh(&pch->upl); + out: + mutex_unlock(&pn->all_ppp_mutex); ++ ++ if (notify && ppp && ppp->dev) { ++ dev_hold(ppp->dev); ++ raw_notifier_call_chain(&ppp_channel_connection_notifier_list, ++ PPP_CHANNEL_CONNECT, ppp->dev); ++ dev_put(ppp->dev); ++ } ++ + return ret; + } + +@@ -3338,6 +3388,13 @@ ppp_disconnect_channel(struct channel *p + pch->ppp = NULL; + write_unlock_bh(&pch->upl); + if (ppp) { ++ if (ppp->dev) { ++ dev_hold(ppp->dev); ++ raw_notifier_call_chain(&ppp_channel_connection_notifier_list, ++ PPP_CHANNEL_DISCONNECT, ppp->dev); ++ dev_put(ppp->dev); ++ } ++ + /* remove it from the ppp unit's list */ + ppp_lock(ppp); + list_del(&pch->clist); +@@ -3417,6 +3474,222 @@ static void *unit_find(struct idr *p, in + return idr_find(p, n); + } + ++/* Updates the PPP interface statistics. */ ++void ppp_update_stats(struct net_device *dev, unsigned long rx_packets, ++ unsigned long rx_bytes, unsigned long tx_packets, ++ unsigned long tx_bytes, unsigned long rx_errors, ++ unsigned long tx_errors, unsigned long rx_dropped, ++ unsigned long tx_dropped) ++{ ++ struct ppp *ppp; ++ ++ if (!dev) ++ return; ++ ++ if (dev->type != ARPHRD_PPP) ++ return; ++ ++ ppp = netdev_priv(dev); ++ ++ ppp_xmit_lock(ppp); ++ ppp->stats64.tx_packets += tx_packets; ++ ppp->stats64.tx_bytes += tx_bytes; ++ ppp->dev->stats.tx_errors += tx_errors; ++ ppp->dev->stats.tx_dropped += tx_dropped; ++ if (tx_packets) ++ ppp->last_xmit = jiffies; ++ ppp_xmit_unlock(ppp); ++ ++ ppp_recv_lock(ppp); ++ ppp->stats64.rx_packets += rx_packets; ++ ppp->stats64.rx_bytes += rx_bytes; ++ ppp->dev->stats.rx_errors += rx_errors; ++ ppp->dev->stats.rx_dropped += rx_dropped; ++ if (rx_packets) ++ ppp->last_recv = jiffies; ++ ppp_recv_unlock(ppp); ++} ++ ++/* Returns >0 if the device is a multilink PPP netdevice, 0 if not or < 0 if ++ * the device is not PPP. ++ */ ++int ppp_is_multilink(struct net_device *dev) ++{ ++ struct ppp *ppp; ++ unsigned int flags; ++ ++ if (!dev) ++ return -1; ++ ++ if (dev->type != ARPHRD_PPP) ++ return -1; ++ ++ ppp = netdev_priv(dev); ++ ppp_lock(ppp); ++ flags = ppp->flags; ++ ppp_unlock(ppp); ++ ++ if (flags & SC_MULTILINK) ++ return 1; ++ ++ return 0; ++} ++EXPORT_SYMBOL(ppp_is_multilink); ++ ++/* ppp_channel_get_protocol() ++ * Call this to obtain the underlying protocol of the PPP channel, ++ * e.g. PX_PROTO_OE ++ * ++ * NOTE: Some channels do not use PX sockets so the protocol value may be very ++ * different for them. ++ * NOTE: -1 indicates failure. ++ * NOTE: Once you know the channel protocol you may then either cast 'chan' to ++ * its sub-class or use the channel protocol specific API's as provided by that ++ * channel sub type. ++ */ ++int ppp_channel_get_protocol(struct ppp_channel *chan) ++{ ++ if (!chan->ops->get_channel_protocol) ++ return -1; ++ ++ return chan->ops->get_channel_protocol(chan); ++} ++EXPORT_SYMBOL(ppp_channel_get_protocol); ++ ++/* ppp_channel_get_proto_version() ++ * Call this to get channel protocol version ++ */ ++int ppp_channel_get_proto_version(struct ppp_channel *chan) ++{ ++ if (!chan->ops->get_channel_protocol_ver) ++ return -1; ++ ++ return chan->ops->get_channel_protocol_ver(chan); ++} ++EXPORT_SYMBOL(ppp_channel_get_proto_version); ++ ++/* ppp_channel_hold() ++ * Call this to hold a channel. ++ * ++ * Returns true on success or false if the hold could not happen. ++ * ++ * NOTE: chan must be protected against destruction during this call - ++ * either by correct locking etc. or because you already have an implicit ++ * or explicit hold to the channel already and this is an additional hold. ++ */ ++bool ppp_channel_hold(struct ppp_channel *chan) ++{ ++ if (!chan->ops->hold) ++ return false; ++ ++ chan->ops->hold(chan); ++ return true; ++} ++EXPORT_SYMBOL(ppp_channel_hold); ++ ++/* ppp_channel_release() ++ * Call this to release a hold you have upon a channel ++ */ ++void ppp_channel_release(struct ppp_channel *chan) ++{ ++ chan->ops->release(chan); ++} ++EXPORT_SYMBOL(ppp_channel_release); ++ ++/* Check if ppp xmit lock is on hold */ ++bool ppp_is_xmit_locked(struct net_device *dev) ++{ ++ struct ppp *ppp; ++ ++ if (!dev) ++ return false; ++ ++ if (dev->type != ARPHRD_PPP) ++ return false; ++ ++ ppp = netdev_priv(dev); ++ if (!ppp) ++ return false; ++ ++ if (spin_is_locked(&(ppp)->wlock)) ++ return true; ++ ++ return false; ++} ++EXPORT_SYMBOL(ppp_is_xmit_locked); ++ ++/* ppp_hold_channels() ++ * Returns the PPP channels of the PPP device, storing each one into ++ * channels[]. ++ * ++ * channels[] has chan_sz elements. ++ * This function returns the number of channels stored, up to chan_sz. ++ * It will return < 0 if the device is not PPP. ++ * ++ * You MUST release the channels using ppp_release_channels(). ++ */ ++int ppp_hold_channels(struct net_device *dev, struct ppp_channel *channels[], ++ unsigned int chan_sz) ++{ ++ struct ppp *ppp; ++ int c; ++ struct channel *pch; ++ ++ if (!dev) ++ return -1; ++ ++ if (dev->type != ARPHRD_PPP) ++ return -1; ++ ++ ppp = netdev_priv(dev); ++ ++ c = 0; ++ ppp_lock(ppp); ++ list_for_each_entry(pch, &ppp->channels, clist) { ++ struct ppp_channel *chan; ++ ++ if (!pch->chan) { ++ /* Channel is going / gone away */ ++ continue; ++ } ++ ++ if (c == chan_sz) { ++ /* No space to record channel */ ++ ppp_unlock(ppp); ++ return c; ++ } ++ ++ /* Hold the channel, if supported */ ++ chan = pch->chan; ++ if (!chan->ops->hold) ++ continue; ++ ++ chan->ops->hold(chan); ++ ++ /* Record the channel */ ++ channels[c++] = chan; ++ } ++ ppp_unlock(ppp); ++ return c; ++} ++EXPORT_SYMBOL(ppp_hold_channels); ++ ++/* ppp_release_channels() ++ * Releases channels ++ */ ++void ppp_release_channels(struct ppp_channel *channels[], unsigned int chan_sz) ++{ ++ unsigned int c; ++ ++ for (c = 0; c < chan_sz; ++c) { ++ struct ppp_channel *chan; ++ ++ chan = channels[c]; ++ chan->ops->release(chan); ++ } ++} ++EXPORT_SYMBOL(ppp_release_channels); ++ + /* Module/initialization stuff */ + + module_init(ppp_init); +@@ -3433,6 +3706,7 @@ EXPORT_SYMBOL(ppp_input_error); + EXPORT_SYMBOL(ppp_output_wakeup); + EXPORT_SYMBOL(ppp_register_compressor); + EXPORT_SYMBOL(ppp_unregister_compressor); ++EXPORT_SYMBOL(ppp_update_stats); + MODULE_LICENSE("GPL"); + MODULE_ALIAS_CHARDEV(PPP_MAJOR, 0); + MODULE_ALIAS_RTNL_LINK("ppp"); +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -62,6 +62,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -87,7 +88,7 @@ + static int __pppoe_xmit(struct sock *sk, struct sk_buff *skb); + + static const struct proto_ops pppoe_ops; +-static const struct ppp_channel_ops pppoe_chan_ops; ++static const struct pppoe_channel_ops pppoe_chan_ops; + + /* per-net private data for this module */ + static unsigned int pppoe_net_id __read_mostly; +@@ -692,7 +693,7 @@ static int pppoe_connect(struct socket * + + po->chan.mtu = dev->mtu - sizeof(struct pppoe_hdr) - 2; + po->chan.private = sk; +- po->chan.ops = &pppoe_chan_ops; ++ po->chan.ops = (struct ppp_channel_ops *)&pppoe_chan_ops; + + error = ppp_register_net_channel(dev_net(dev), &po->chan); + if (error) { +@@ -994,9 +995,80 @@ static int pppoe_fill_forward_path(struc + return 0; + } + +-static const struct ppp_channel_ops pppoe_chan_ops = { +- .start_xmit = pppoe_xmit, +- .fill_forward_path = pppoe_fill_forward_path, ++/************************************************************************ ++ * ++ * function called by generic PPP driver to hold channel ++ * ++ ***********************************************************************/ ++static void pppoe_hold_chan(struct ppp_channel *chan) ++{ ++ struct sock *sk = (struct sock *)chan->private; ++ ++ sock_hold(sk); ++} ++ ++/************************************************************************ ++ * ++ * function called by generic PPP driver to release channel ++ * ++ ***********************************************************************/ ++static void pppoe_release_chan(struct ppp_channel *chan) ++{ ++ struct sock *sk = (struct sock *)chan->private; ++ ++ sock_put(sk); ++} ++ ++/************************************************************************ ++ * ++ * function called to get the channel protocol type ++ * ++ ***********************************************************************/ ++static int pppoe_get_channel_protocol(struct ppp_channel *chan) ++{ ++ return PX_PROTO_OE; ++} ++ ++/************************************************************************ ++ * ++ * function called to get the PPPoE channel addressing ++ * NOTE: This function returns a HOLD to the netdevice ++ * ++ ***********************************************************************/ ++static int pppoe_get_addressing(struct ppp_channel *chan, ++ struct pppoe_opt *addressing) ++{ ++ struct sock *sk = (struct sock *)chan->private; ++ struct pppox_sock *po = pppox_sk(sk); ++ int err = 0; ++ ++ *addressing = po->proto.pppoe; ++ if (!addressing->dev) ++ return -ENODEV; ++ ++ dev_hold(addressing->dev); ++ return err; ++} ++ ++/* pppoe_channel_addressing_get() ++ * Return PPPoE channel specific addressing information. ++ */ ++int pppoe_channel_addressing_get(struct ppp_channel *chan, ++ struct pppoe_opt *addressing) ++{ ++ return pppoe_get_addressing(chan, addressing); ++} ++EXPORT_SYMBOL(pppoe_channel_addressing_get); ++ ++static const struct pppoe_channel_ops pppoe_chan_ops = { ++ /* PPPoE specific channel ops */ ++ .get_addressing = pppoe_get_addressing, ++ /* General ppp channel ops */ ++ .ops.start_xmit = pppoe_xmit, ++ .ops.get_channel_protocol = pppoe_get_channel_protocol, ++ .ops.hold = pppoe_hold_chan, ++ .ops.release = pppoe_release_chan, ++ .ops.fill_forward_path = pppoe_fill_forward_path, + }; + + static int pppoe_recvmsg(struct socket *sock, struct msghdr *m, +--- a/include/linux/if_pppox.h ++++ b/include/linux/if_pppox.h +@@ -93,4 +93,17 @@ enum { + PPPOX_DEAD = 16 /* dead, useless, please clean me up!*/ + }; + ++/* ++ * PPPoE Channel specific operations ++ */ ++struct pppoe_channel_ops { ++ /* Must be first - general to all PPP channels */ ++ struct ppp_channel_ops ops; ++ int (*get_addressing)(struct ppp_channel *, struct pppoe_opt *); ++}; ++ ++/* Return PPPoE channel specific addressing information */ ++extern int pppoe_channel_addressing_get(struct ppp_channel *chan, ++ struct pppoe_opt *addressing); ++ + #endif /* !(__LINUX_IF_PPPOX_H) */ +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -1620,6 +1620,24 @@ enum netdev_priv_flags { + IFF_LIVE_RENAME_OK = 1<<30, + }; + ++ ++/** ++ * enum netdev_priv_flags_ext - &struct net_device priv_flags_ext ++ * ++ * These flags are used to check for device type and can be ++ * set and used by the drivers ++ * ++ */ ++enum netdev_priv_flags_ext { ++ IFF_EXT_TUN_TAP = 1<<0, ++ IFF_EXT_PPP_L2TPV2 = 1<<1, ++ IFF_EXT_PPP_L2TPV3 = 1<<2, ++ IFF_EXT_PPP_PPTP = 1<<3, ++ IFF_EXT_GRE_V4_TAP = 1<<4, ++ IFF_EXT_GRE_V6_TAP = 1<<5, ++ IFF_EXT_IFB = 1<<6, ++}; ++ + #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN + #define IFF_EBRIDGE IFF_EBRIDGE + #define IFF_BONDING IFF_BONDING +@@ -1994,6 +2012,7 @@ struct net_device { + + unsigned int flags; + unsigned int priv_flags; ++ unsigned int priv_flags_ext; + + unsigned short gflags; + unsigned short padded; +--- a/include/linux/ppp_channel.h ++++ b/include/linux/ppp_channel.h +@@ -19,6 +19,10 @@ + #include + #include + #include ++#include ++ ++#define PPP_CHANNEL_DISCONNECT 0 ++#define PPP_CHANNEL_CONNECT 1 + + struct ppp_channel; + +@@ -28,9 +32,19 @@ struct ppp_channel_ops { + int (*start_xmit)(struct ppp_channel *, struct sk_buff *); + /* Handle an ioctl call that has come in via /dev/ppp. */ + int (*ioctl)(struct ppp_channel *, unsigned int, unsigned long); ++ /* Get channel protocol type, one of PX_PROTO_XYZ or specific to ++ * the channel subtype ++ */ ++ int (*get_channel_protocol)(struct ppp_channel *); ++ /* Get channel protocol version */ ++ int (*get_channel_protocol_ver)(struct ppp_channel *); ++ /* Hold the channel from being destroyed */ ++ void (*hold)(struct ppp_channel *); ++ /* Release hold on the channel */ ++ void (*release)(struct ppp_channel *); + int (*fill_forward_path)(struct net_device_path_ctx *, +- struct net_device_path *, +- const struct ppp_channel *); ++ struct net_device_path *, ++ const struct ppp_channel *); + }; + + struct ppp_channel { +@@ -74,6 +88,51 @@ extern int ppp_unit_number(struct ppp_ch + /* Get the device name associated with a channel, or NULL if none */ + extern char *ppp_dev_name(struct ppp_channel *); + ++/* Call this to obtain the underlying protocol of the PPP channel, ++ * e.g. PX_PROTO_OE ++ */ ++extern int ppp_channel_get_protocol(struct ppp_channel *); ++ ++/* Call this get protocol version */ ++extern int ppp_channel_get_proto_version(struct ppp_channel *); ++ ++/* Call this to hold a channel */ ++extern bool ppp_channel_hold(struct ppp_channel *); ++ ++/* Call this to release a hold you have upon a channel */ ++extern void ppp_channel_release(struct ppp_channel *); ++ ++/* Release hold on PPP channels */ ++extern void ppp_release_channels(struct ppp_channel *channels[], ++ unsigned int chan_sz); ++ ++/* Hold PPP channels for the PPP device */ ++extern int ppp_hold_channels(struct net_device *dev, ++ struct ppp_channel *channels[], ++ unsigned int chan_sz); ++ ++/* Test if ppp xmit lock is locked */ ++extern bool ppp_is_xmit_locked(struct net_device *dev); ++ ++/* Test if the ppp device is a multi-link ppp device */ ++extern int ppp_is_multilink(struct net_device *dev); ++ ++/* Register the PPP channel connect notifier */ ++extern void ppp_channel_connection_register_notify(struct notifier_block *nb); ++ ++/* Unregister the PPP channel connect notifier */ ++extern void ppp_channel_connection_unregister_notify(struct notifier_block *nb); ++ ++/* Update statistics of the PPP net_device by incrementing related ++ * statistics field value with corresponding parameter ++ */ ++extern void ppp_update_stats(struct net_device *dev, unsigned long rx_packets, ++ unsigned long rx_bytes, unsigned long tx_packets, ++ unsigned long tx_bytes, unsigned long rx_errors, ++ unsigned long tx_errors, unsigned long rx_dropped, ++ unsigned long tx_dropped); ++ ++ + /* + * SMP locking notes: + * The channel code must ensure that when it calls ppp_unregister_channel, diff --git a/target/linux/ipq807x/patches-5.10/603-net-core-Flag-to-identify-ingress-shaping-done-for-e.patch b/target/linux/ipq807x/patches-5.10/603-net-core-Flag-to-identify-ingress-shaping-done-for-e.patch new file mode 100644 index 000000000..616645192 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/603-net-core-Flag-to-identify-ingress-shaping-done-for-e.patch @@ -0,0 +1,74 @@ +From a0c69a23c66ec6f527c439714eb2cc5857a71492 Mon Sep 17 00:00:00 2001 +From: Himanshu Joshi +Date: Tue, 3 Nov 2020 16:41:26 +0530 +Subject: [PATCH] net: core: Flag to identify ingress shaping done for + exceptioned packets. + +Signed-off-by: Himanshu Joshi +Change-Id: Ib3cd341e5b2d4dcf552e02e38d3f34a4f00351cd +--- + include/linux/skbuff.h | 2 ++ + include/net/sch_generic.h | 34 ++++++++++++++++++++++++++++++++++ + 2 files changed, 36 insertions(+) + +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -646,6 +646,7 @@ typedef unsigned char *sk_buff_data_t; + * @offload_fwd_mark: Packet was L2-forwarded in hardware + * @offload_l3_fwd_mark: Packet was L3-forwarded in hardware + * @tc_skip_classify: do not classify packet. set by IFB device ++ * @tc_skip_classify_nss: do not classify packet. set by NSS IFB device + * @tc_at_ingress: used within tc_classify to distinguish in/egress + * @redirected: packet was redirected by packet classifier + * @from_ingress: packet was redirected from the ingress path +@@ -850,6 +851,7 @@ struct sk_buff { + #ifdef CONFIG_NET_CLS_ACT + __u8 tc_skip_classify:1; + __u8 tc_at_ingress:1; ++ __u8 tc_skip_classify_nss:1; + #endif + #ifdef CONFIG_NET_REDIRECT + __u8 redirected:1; +--- a/include/net/sch_generic.h ++++ b/include/net/sch_generic.h +@@ -738,6 +738,40 @@ static inline bool skb_skip_tc_classify( + return false; + } + ++/* ++ * Set skb classify bit field. ++ */ ++static inline void skb_set_tc_classify_nss(struct sk_buff *skb) ++{ ++#ifdef CONFIG_NET_CLS_ACT ++ skb->tc_skip_classify_nss = 1; ++#endif ++} ++ ++/* ++ * Clear skb classify bit field. ++ */ ++static inline void skb_clear_tc_classify_nss(struct sk_buff *skb) ++{ ++#ifdef CONFIG_NET_CLS_ACT ++ skb->tc_skip_classify_nss = 0; ++#endif ++} ++ ++/* ++ * Skip skb processing if sent from ifb dev. ++ */ ++static inline bool skb_skip_tc_classify_nss(struct sk_buff *skb) ++{ ++#ifdef CONFIG_NET_CLS_ACT ++ if (skb->tc_skip_classify_nss) { ++ skb_clear_tc_classify_nss(skb); ++ return true; ++ } ++#endif ++ return false; ++} ++ + /* Reset all TX qdiscs greater than index of a device. */ + static inline void qdisc_reset_all_tx_gt(struct net_device *dev, unsigned int i) + { diff --git a/target/linux/ipq807x/patches-5.10/604-net-core-Replace-nss-keyword-with-offload.patch b/target/linux/ipq807x/patches-5.10/604-net-core-Replace-nss-keyword-with-offload.patch new file mode 100644 index 000000000..f76ea3147 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/604-net-core-Replace-nss-keyword-with-offload.patch @@ -0,0 +1,76 @@ +From 7c55539fa1e4ea6be400a35127ddc52d6dcd86d4 Mon Sep 17 00:00:00 2001 +From: Himanshu Joshi +Date: Thu, 26 Nov 2020 16:21:06 +0530 +Subject: [PATCH] net: core: Replace nss keyword with offload. + +Kernel code should not checked in with NSS keyword. +This change fixes the naming issue for ifb module. + +Signed-off-by: Himanshu Joshi +Change-Id: Iddb97d6ba0a443b830d1ac23728434a417bc8a92 +--- + include/linux/skbuff.h | 4 ++-- + include/net/sch_generic.h | 14 +++++++------- + 2 files changed, 9 insertions(+), 9 deletions(-) + +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -646,7 +646,7 @@ typedef unsigned char *sk_buff_data_t; + * @offload_fwd_mark: Packet was L2-forwarded in hardware + * @offload_l3_fwd_mark: Packet was L3-forwarded in hardware + * @tc_skip_classify: do not classify packet. set by IFB device +- * @tc_skip_classify_nss: do not classify packet. set by NSS IFB device ++ * @tc_skip_classify_offload: do not classify packet set by offload IFB device + * @tc_at_ingress: used within tc_classify to distinguish in/egress + * @redirected: packet was redirected by packet classifier + * @from_ingress: packet was redirected from the ingress path +@@ -851,7 +851,7 @@ struct sk_buff { + #ifdef CONFIG_NET_CLS_ACT + __u8 tc_skip_classify:1; + __u8 tc_at_ingress:1; +- __u8 tc_skip_classify_nss:1; ++ __u8 tc_skip_classify_offload:1; + #endif + #ifdef CONFIG_NET_REDIRECT + __u8 redirected:1; +--- a/include/net/sch_generic.h ++++ b/include/net/sch_generic.h +@@ -741,31 +741,31 @@ static inline bool skb_skip_tc_classify( + /* + * Set skb classify bit field. + */ +-static inline void skb_set_tc_classify_nss(struct sk_buff *skb) ++static inline void skb_set_tc_classify_offload(struct sk_buff *skb) + { + #ifdef CONFIG_NET_CLS_ACT +- skb->tc_skip_classify_nss = 1; ++ skb->tc_skip_classify_offload = 1; + #endif + } + + /* + * Clear skb classify bit field. + */ +-static inline void skb_clear_tc_classify_nss(struct sk_buff *skb) ++static inline void skb_clear_tc_classify_offload(struct sk_buff *skb) + { + #ifdef CONFIG_NET_CLS_ACT +- skb->tc_skip_classify_nss = 0; ++ skb->tc_skip_classify_offload = 0; + #endif + } + + /* + * Skip skb processing if sent from ifb dev. + */ +-static inline bool skb_skip_tc_classify_nss(struct sk_buff *skb) ++static inline bool skb_skip_tc_classify_offload(struct sk_buff *skb) + { + #ifdef CONFIG_NET_CLS_ACT +- if (skb->tc_skip_classify_nss) { +- skb_clear_tc_classify_nss(skb); ++ if (skb->tc_skip_classify_offload) { ++ skb_clear_tc_classify_offload(skb); + return true; + } + #endif diff --git a/target/linux/ipq807x/patches-5.10/900-arm64-dts-add-OpenWrt-DTS-files.patch b/target/linux/ipq807x/patches-5.10/900-arm64-dts-add-OpenWrt-DTS-files.patch new file mode 100644 index 000000000..22f201449 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/900-arm64-dts-add-OpenWrt-DTS-files.patch @@ -0,0 +1,25 @@ +From 8aec79b6d4d59616eb6ce4fbfb94658b3e79d9ce Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 11 May 2021 13:29:33 +0200 +Subject: [PATCH] arm64: dts: add OpenWrt DTS files + +Lets add custom OpenWrt DTS files to Makefile. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/Makefile | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -3,6 +3,10 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.d + dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb + dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8071-ax6.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8071-ax3600.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8072-ax9000.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8074-sxr80.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb diff --git a/target/linux/ipq807x/patches-5.10/901-soc-qcom-Make-QMI-Helpers-user-selectable.patch b/target/linux/ipq807x/patches-5.10/901-soc-qcom-Make-QMI-Helpers-user-selectable.patch new file mode 100644 index 000000000..a5ed332ff --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/901-soc-qcom-Make-QMI-Helpers-user-selectable.patch @@ -0,0 +1,28 @@ +From b9b94712847f8fa6ca8dc03422ba9e0332b6997d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 14:54:43 +0200 +Subject: [PATCH] soc: qcom: Make QMI Helpers user selectable + +Wireless backports for ath11k have a different logic +then upstream as they depend on QMI helpers instead +of selecting them. + +So, to make it possible to select QMI helpers +through KConfig add text to tristate. + +Signed-off-by: Robert Marko +--- + drivers/soc/qcom/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/soc/qcom/Kconfig ++++ b/drivers/soc/qcom/Kconfig +@@ -92,7 +92,7 @@ config QCOM_PDR_HELPERS + select QCOM_QMI_HELPERS + + config QCOM_QMI_HELPERS +- tristate ++ tristate "Qualcomm QMI helpers" + depends on NET + + config QCOM_RMTFS_MEM diff --git a/target/linux/ipq807x/patches-5.10/902-arm64-provide-dma-cache-routines-with-same-API-as-32.patch b/target/linux/ipq807x/patches-5.10/902-arm64-provide-dma-cache-routines-with-same-API-as-32.patch new file mode 100644 index 000000000..a682bb259 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/902-arm64-provide-dma-cache-routines-with-same-API-as-32.patch @@ -0,0 +1,56 @@ +From 181e506248fd24a0febbfbd794bba43a7b346115 Mon Sep 17 00:00:00 2001 +From: Kathiravan T +Date: Fri, 17 Jan 2014 10:33:08 -0800 +Subject: [PATCH] arm64: provide dma cache routines with same API as 32 bit + +The APIs __dma_inv_range() and __dma_clean_range() were +not exported by the third party patch. Since the functions +starting with underscores are not to be directly used by drivers, +related functions without the underscores are provided +which have the same name and functionality as the 32 bit APIs. + +CRs-Fixed: 1053067 +Change-Id: Ie0e681614307d9d9a19e58cacfb9b5dff4528977 + +arm64: add defines for dmac_*_range for compatibility with arm32 + +An earlier patch created defines for dma_*_range APIs to be +compatible with arm 32 bit, however it appears +these API names have not (at least yet) appeared there, so +revise the names to dmac_*_range, which is defined +for arm 32 bit so that there is one name defined +for both architectures. + +CRs-Fixed: 1053067 +Signed-off-by: Larry Bassel +(cherry picked from commit 0930bab0db67cc0d91e52e385e3e061871c6be05) +[psodagud: fixed up trivial merge conflicts and warnings] +Signed-off-by: Prasad Sodagudi + +(cherry picked from commit a313e54567627a1fd96cd267e2c6c358d14e468c) +[kathirav: fixed the trivial conflicts] + +Change-Id: I6456c02bad73fb54a874dc9925d3d43d9b8be2f2 +Signed-off-by: Kathiravan T +--- + arch/arm64/include/asm/cacheflush.h | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/include/asm/cacheflush.h ++++ b/arch/arm64/include/asm/cacheflush.h +@@ -102,6 +102,15 @@ static inline void flush_icache_range(un + extern void __dma_map_area(const void *, size_t, int); + extern void __dma_unmap_area(const void *, size_t, int); + extern void __dma_flush_area(const void *, size_t); ++extern void __dma_inv_area(const void *start, size_t size); ++extern void __dma_clean_area(const void *start, size_t size); ++ ++#define dmac_flush_range(start, end) \ ++ __dma_flush_area(start, (void *)(end) - (void *)(start)) ++#define dmac_inv_range(start, end) \ ++ __dma_inv_area(start, (void *)(end) - (void *)(start)) ++#define dmac_clean_range(start, end) \ ++ __dma_clean_area(start, (void *)(end) - (void *)(start)) + + /* + * Copy user data from/to a page which is mapped into a different diff --git a/target/linux/ipq807x/patches-5.10/903-arm64-mm-export-__dma_inv_area-and-__dma_clean_area.patch b/target/linux/ipq807x/patches-5.10/903-arm64-mm-export-__dma_inv_area-and-__dma_clean_area.patch new file mode 100644 index 000000000..865a7a9d5 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/903-arm64-mm-export-__dma_inv_area-and-__dma_clean_area.patch @@ -0,0 +1,58 @@ +From da0c8f67d9aca417a441af4fb90acf65eef94585 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 23:44:07 +0200 +Subject: [PATCH] arm64: mm: export __dma_inv_area and __dma_clean_area + +Qualcomm NSS drivers use these extensively. + +Signed-off-by: Robert Marko +--- + arch/arm64/include/asm/cacheflush.h | 4 ++-- + arch/arm64/mm/cache.S | 4 ++-- + arch/arm64/mm/flush.c | 2 ++ + 3 files changed, 6 insertions(+), 4 deletions(-) + +--- a/arch/arm64/include/asm/cacheflush.h ++++ b/arch/arm64/include/asm/cacheflush.h +@@ -102,8 +102,8 @@ static inline void flush_icache_range(un + extern void __dma_map_area(const void *, size_t, int); + extern void __dma_unmap_area(const void *, size_t, int); + extern void __dma_flush_area(const void *, size_t); +-extern void __dma_inv_area(const void *start, size_t size); +-extern void __dma_clean_area(const void *start, size_t size); ++extern void __dma_inv_area(const void *, size_t); ++extern void __dma_clean_area(const void *, size_t); + + #define dmac_flush_range(start, end) \ + __dma_flush_area(start, (void *)(end) - (void *)(start)) +--- a/arch/arm64/mm/cache.S ++++ b/arch/arm64/mm/cache.S +@@ -138,7 +138,7 @@ SYM_FUNC_END(__clean_dcache_area_pou) + * - kaddr - kernel address + * - size - size in question + */ +-SYM_FUNC_START_LOCAL(__dma_inv_area) ++SYM_FUNC_START(__dma_inv_area) + SYM_FUNC_START_PI(__inval_dcache_area) + /* FALLTHROUGH */ + +@@ -177,7 +177,7 @@ SYM_FUNC_END(__dma_inv_area) + * - kaddr - kernel address + * - size - size in question + */ +-SYM_FUNC_START_LOCAL(__dma_clean_area) ++SYM_FUNC_START(__dma_clean_area) + SYM_FUNC_START_PI(__clean_dcache_area_poc) + /* FALLTHROUGH */ + +--- a/arch/arm64/mm/flush.c ++++ b/arch/arm64/mm/flush.c +@@ -78,6 +78,8 @@ EXPORT_SYMBOL(flush_dcache_page); + * Additional functions defined in assembly. + */ + EXPORT_SYMBOL(__flush_icache_range); ++EXPORT_SYMBOL(__dma_inv_area); ++EXPORT_SYMBOL(__dma_clean_area); + + #ifdef CONFIG_ARCH_HAS_PMEM_API + void arch_wb_cache_pmem(void *addr, size_t size) diff --git a/target/linux/ipq807x/patches-5.10/990-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch b/target/linux/ipq807x/patches-5.10/990-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch new file mode 100644 index 000000000..eb473410c --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/990-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch @@ -0,0 +1,49 @@ +From 474740fac667ccf7a6b3c748d851e5ed364d59eb Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Mon, 4 Sep 2017 15:00:10 +0530 +Subject: [PATCH 1/3] clk: qcom: fix wrong RCG clock rate for high parent freq + +If the parent clock rate is greater than unsigned long max +divided by 2 then the integer overflow is happening while +calculating the clock rate. Since RCG2 uses half integer +dividers, the clock rate is first being multiplied by 2 +followed by division and this multiplication leads to +overflow. + +Change-Id: I4e4f41b4a539446b962eb684761a3aad6f8a8977 +Signed-off-by: Abhishek Sahu +(cherry picked from commit 9cfedaf465eb18ef31e4d677cba5f3147fe6d430) +Signed-off-by: Praveenkumar I + +Change-Id: I69b78616f468bb7a9647c7994a8579b97c376d4e +--- + drivers/clk/qcom/clk-rcg2.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/clk/qcom/clk-rcg2.c ++++ b/drivers/clk/qcom/clk-rcg2.c +@@ -145,18 +145,18 @@ static int clk_rcg2_set_parent(struct cl + * hid_div n + */ + static unsigned long +-calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) ++calc_rate(unsigned long parent_rate, u32 m, u32 n, u32 mode, u32 hid_div) + { ++ u64 rate = parent_rate; ++ + if (hid_div) { + rate *= 2; +- rate /= hid_div + 1; ++ do_div(rate, hid_div + 1); + } + + if (mode) { +- u64 tmp = rate; +- tmp *= m; +- do_div(tmp, n); +- rate = tmp; ++ rate *= m; ++ do_div(rate, n); + } + + return rate; diff --git a/target/linux/ipq807x/patches-5.10/991-clk-qcom-add-support-for-hw-controlled-RCG.patch b/target/linux/ipq807x/patches-5.10/991-clk-qcom-add-support-for-hw-controlled-RCG.patch new file mode 100644 index 000000000..78d7b20b4 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/991-clk-qcom-add-support-for-hw-controlled-RCG.patch @@ -0,0 +1,136 @@ +From 0245360f8e118b67f4015533cfc79314f2d848d5 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Tue, 13 Jun 2017 15:30:39 +0530 +Subject: [PATCH 2/3] clk: qcom: add support for hw controlled RCG +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The current driver generates stack trace during RCG update if +the RCG is off and new parent source is also disabled. For +hardware controlled RCG’s, clock is forced on during update +process and goes back to off status once switch is completed. +Since the new parent is in disabled state so update bit won’t +be cleared in this case. The check for update bit can be +skipped in this case. + +Signed-off-by: Abhishek Sahu +(cherry picked from commit 84dd0e12f10eebff44a464eb8455205abc4b4178) +Signed-off-by: Praveenkumar I + +Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599 +--- + drivers/clk/qcom/clk-rcg.h | 4 ++++ + drivers/clk/qcom/clk-rcg2.c | 27 +++++++++++++++++++++------ + 2 files changed, 25 insertions(+), 6 deletions(-) + +--- a/drivers/clk/qcom/clk-rcg.h ++++ b/drivers/clk/qcom/clk-rcg.h +@@ -135,6 +135,7 @@ extern const struct clk_ops clk_dyn_rcg_ + * @mnd_width: number of bits in m/n/d values + * @hid_width: number of bits in half integer divider + * @safe_src_index: safe src index value ++ * @flags: RCG2 specific clock flags + * @parent_map: map from software's parent index to hardware's src_sel field + * @freq_tbl: frequency table + * @clkr: regmap clock handle +@@ -145,6 +146,9 @@ struct clk_rcg2 { + u8 mnd_width; + u8 hid_width; + u8 safe_src_index; ++ ++#define CLK_RCG2_HW_CONTROLLED BIT(0) ++ u8 flags; + const struct parent_map *parent_map; + const struct freq_tbl *freq_tbl; + struct clk_regmap clkr; +--- a/drivers/clk/qcom/clk-rcg2.c ++++ b/drivers/clk/qcom/clk-rcg2.c +@@ -97,7 +97,7 @@ err: + return 0; + } + +-static int update_config(struct clk_rcg2 *rcg) ++static int update_config(struct clk_rcg2 *rcg, bool check_update_clear) + { + int count, ret; + u32 cmd; +@@ -109,6 +109,9 @@ static int update_config(struct clk_rcg2 + if (ret) + return ret; + ++ if (!check_update_clear) ++ return 0; ++ + /* Wait for update to take effect */ + for (count = 500; count > 0; count--) { + ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); +@@ -127,14 +130,19 @@ static int clk_rcg2_set_parent(struct cl + { + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + int ret; ++ bool check_update_clear = true; + u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; + ++ if ((rcg->flags & CLK_RCG2_HW_CONTROLLED) && ++ !clk_hw_is_enabled(clk_hw_get_parent_by_index(hw, index))) ++ check_update_clear = false; ++ + ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), + CFG_SRC_SEL_MASK, cfg); + if (ret) + return ret; + +- return update_config(rcg); ++ return update_config(rcg, check_update_clear); + } + + /* +@@ -302,12 +310,19 @@ static int __clk_rcg2_configure(struct c + static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) + { + int ret; ++ bool check_update_clear = true; ++ struct clk_hw *hw = &rcg->clkr.hw; ++ int index = qcom_find_src_index(hw, rcg->parent_map, f->src); + + ret = __clk_rcg2_configure(rcg, f); + if (ret) + return ret; + +- return update_config(rcg); ++ if ((rcg->flags & CLK_RCG2_HW_CONTROLLED) && ++ !clk_hw_is_enabled(clk_hw_get_parent_by_index(hw, index))) ++ check_update_clear = false; ++ ++ return update_config(rcg, check_update_clear); + } + + static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, +@@ -786,7 +801,7 @@ static int clk_gfx3d_set_rate_and_parent + if (ret) + return ret; + +- return update_config(rcg); ++ return update_config(rcg, true); + } + + static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, +@@ -898,7 +913,7 @@ static int clk_rcg2_shared_enable(struct + if (ret) + return ret; + +- ret = update_config(rcg); ++ ret = update_config(rcg, true); + if (ret) + return ret; + +@@ -929,7 +944,7 @@ static void clk_rcg2_shared_disable(stru + regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, + rcg->safe_src_index << CFG_SRC_SEL_SHIFT); + +- update_config(rcg); ++ update_config(rcg, true); + + clk_rcg2_clear_force_enable(hw); + diff --git a/target/linux/ipq807x/patches-5.10/992-clk-qcom-ipq8074-add-hw-controlled-flag.patch b/target/linux/ipq807x/patches-5.10/992-clk-qcom-ipq8074-add-hw-controlled-flag.patch new file mode 100644 index 000000000..971a255c8 --- /dev/null +++ b/target/linux/ipq807x/patches-5.10/992-clk-qcom-ipq8074-add-hw-controlled-flag.patch @@ -0,0 +1,38 @@ +From 18d04f5cae30725ffa0c1c025f6beb1821c46857 Mon Sep 17 00:00:00 2001 +From: Praveenkumar I +Date: Tue, 13 Jun 2017 15:31:34 +0530 +Subject: [PATCH 3/3] clk: qcom: ipq8074: add hw controlled flag +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +These RCG’s are hw controlled so add the +CLK_RCG2_HW_CONTROLLED flag. + +Signed-off-by: Abhishek Sahu +(cherry picked from commit 9a025b8271a95a80e9e769b89154b98b263be860) +Signed-off-by: Praveenkumar I + +Change-Id: Ic5da1551bf46921890955312026b9175a42fe14e +--- + drivers/clk/qcom/gcc-ipq8074.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -648,6 +648,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s + .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .flags = CLK_RCG2_HW_CONTROLLED, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pcnoc_bfdcd_clk_src", + .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, +@@ -1317,6 +1318,7 @@ static struct clk_rcg2 system_noc_bfdcd_ + .freq_tbl = ftbl_system_noc_bfdcd_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map, ++ .flags = CLK_RCG2_HW_CONTROLLED, + .clkr.hw.init = &(struct clk_init_data){ + .name = "system_noc_bfdcd_clk_src", + .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2, diff --git a/target/linux/ipq807x/patches-5.4/997-device_tree_cmdline.patch b/target/linux/ipq807x/patches-5.10/997-device_tree_cmdline.patch similarity index 86% rename from target/linux/ipq807x/patches-5.4/997-device_tree_cmdline.patch rename to target/linux/ipq807x/patches-5.10/997-device_tree_cmdline.patch index 3cc032fdd..27d4d7f1e 100644 --- a/target/linux/ipq807x/patches-5.4/997-device_tree_cmdline.patch +++ b/target/linux/ipq807x/patches-5.10/997-device_tree_cmdline.patch @@ -1,6 +1,6 @@ --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c -@@ -1059,6 +1059,9 @@ int __init early_init_dt_scan_chosen(uns +@@ -1055,6 +1055,9 @@ int __init early_init_dt_scan_chosen(uns p = of_get_flat_dt_prop(node, "bootargs", &l); if (p != NULL && l > 0) strlcpy(data, p, min(l, COMMAND_LINE_SIZE)); diff --git a/target/linux/ipq807x/patches-5.4/0001-v5.7-ARM64-dts-qcom-add-gpio-ranges-property.patch b/target/linux/ipq807x/patches-5.4/0001-v5.7-ARM64-dts-qcom-add-gpio-ranges-property.patch deleted file mode 100644 index db860dde2..000000000 --- a/target/linux/ipq807x/patches-5.4/0001-v5.7-ARM64-dts-qcom-add-gpio-ranges-property.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 297177a45b95097ae4f25a6f6d191d592e1bb018 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Wed, 8 Jan 2020 13:54:57 +0100 -Subject: [PATCH] ARM64: dts: qcom: add gpio-ranges property - -This patch adds the gpio-ranges property to almost all of -the Qualcomm ARM platforms that utilize the pinctrl-msm -framework. - -The gpio-ranges property is part of the gpiolib subsystem. -As a result, the binding text is available in section -"2.1 gpio- and pin-controller interaction" of -Documentation/devicetree/bindings/gpio/gpio.txt - -For more information please see the patch titled: -"pinctrl: msm: fix gpio-hog related boot issues" from -this series. - -Reported-by: Sven Eckelmann -Tested-by: Sven Eckelmann [ipq4019] -Reviewed-by: Bjorn Andersson -Reviewed-by: Linus Walleij -Signed-off-by: Christian Lamparter -Tested-by: Robert Marko [ipq4019] -Cc: Luka Perkov -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20200108125455.308969-2-robert.marko@sartura.hr -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + - 1 files changed, 1 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -21,6 +21,7 @@ - reg = <0x1000000 0x300000>; - interrupts = ; - gpio-controller; -+ gpio-ranges = <&tlmm 0 0 70>; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; diff --git a/target/linux/ipq807x/patches-5.4/0002-v5.8-arm64-dts-ipq8074-qcom-Re-arrange-dts-nodes-based-on.patch b/target/linux/ipq807x/patches-5.4/0002-v5.8-arm64-dts-ipq8074-qcom-Re-arrange-dts-nodes-based-on.patch deleted file mode 100644 index 9f72b935f..000000000 --- a/target/linux/ipq807x/patches-5.4/0002-v5.8-arm64-dts-ipq8074-qcom-Re-arrange-dts-nodes-based-on.patch +++ /dev/null @@ -1,734 +0,0 @@ -From e8a7fdc505bb06625a176f23293811d12d7d24eb Mon Sep 17 00:00:00 2001 -From: Sivaprakash Murugesan -Date: Sat, 11 Apr 2020 08:10:30 +0530 -Subject: [PATCH] arm64: dts: ipq8074: qcom: Re-arrange dts nodes based on - address - -This patch re-arranges ipq8074 device nodes based on node address -followed by node names followed by node labels. - -Suggested-by: Bjorn Andersson -Signed-off-by: Sivaprakash Murugesan -Link: https://lore.kernel.org/r/1586572830-22727-1-git-send-email-sivaprak@codeaurora.org -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 112 +++-- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 474 +++++++++++----------- - 2 files changed, 292 insertions(+), 294 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -@@ -24,63 +24,61 @@ - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x20000000>; - }; -+}; -+ -+&blsp1_i2c2 { -+ status = "ok"; -+}; -+ -+&blsp1_spi1 { -+ status = "ok"; -+ -+ m25p80@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <50000000>; -+ }; -+}; -+ -+&blsp1_uart3 { -+ status = "ok"; -+}; -+ -+&blsp1_uart5 { -+ status = "ok"; -+}; -+ -+&pcie0 { -+ status = "ok"; -+ perst-gpio = <&tlmm 61 0x1>; -+}; -+ -+&pcie1 { -+ status = "ok"; -+ perst-gpio = <&tlmm 58 0x1>; -+}; -+ -+&pcie_phy0 { -+ status = "ok"; -+}; -+ -+&pcie_phy1 { -+ status = "ok"; -+}; -+ -+&qpic_bam { -+ status = "ok"; -+}; -+ -+&qpic_nand { -+ status = "ok"; - -- soc { -- serial@78b3000 { -- status = "ok"; -- }; -- -- spi@78b5000 { -- status = "ok"; -- -- m25p80@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "jedec,spi-nor"; -- reg = <0>; -- spi-max-frequency = <50000000>; -- }; -- }; -- -- serial@78b1000 { -- status = "ok"; -- }; -- -- i2c@78b6000 { -- status = "ok"; -- }; -- -- dma@7984000 { -- status = "ok"; -- }; -- -- nand@79b0000 { -- status = "ok"; -- -- nand@0 { -- reg = <0>; -- nand-ecc-strength = <4>; -- nand-ecc-step-size = <512>; -- nand-bus-width = <8>; -- }; -- }; -- -- phy@86000 { -- status = "ok"; -- }; -- -- phy@8e000 { -- status = "ok"; -- }; -- -- pci@20000000 { -- status = "ok"; -- perst-gpio = <&tlmm 58 0x1>; -- }; -- -- pci@10000000 { -- status = "ok"; -- perst-gpio = <&tlmm 61 0x1>; -- }; -+ nand@0 { -+ reg = <0>; -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; -+ nand-bus-width = <8>; - }; - }; ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -10,15 +10,111 @@ - model = "Qualcomm Technologies, Inc. IPQ8074"; - compatible = "qcom,ipq8074"; - -+ clocks { -+ sleep_clk: sleep_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <32000>; -+ #clock-cells = <0>; -+ }; -+ -+ xo: xo { -+ compatible = "fixed-clock"; -+ clock-frequency = <19200000>; -+ #clock-cells = <0>; -+ }; -+ }; -+ -+ cpus { -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ -+ CPU0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ CPU1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ enable-method = "psci"; -+ reg = <0x1>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ CPU2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ enable-method = "psci"; -+ reg = <0x2>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ CPU3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ enable-method = "psci"; -+ reg = <0x3>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ L2_0: l2-cache { -+ compatible = "cache"; -+ cache-level = <0x2>; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = ; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ - soc: soc { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - -+ pcie_phy0: phy@86000 { -+ compatible = "qcom,ipq8074-qmp-pcie-phy"; -+ reg = <0x00086000 0x1000>; -+ #phy-cells = <0>; -+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -+ clock-names = "pipe_clk"; -+ clock-output-names = "pcie20_phy0_pipe_clk"; -+ -+ resets = <&gcc GCC_PCIE0_PHY_BCR>, -+ <&gcc GCC_PCIE0PHY_PHY_BCR>; -+ reset-names = "phy", -+ "common"; -+ status = "disabled"; -+ }; -+ -+ pcie_phy1: phy@8e000 { -+ compatible = "qcom,ipq8074-qmp-pcie-phy"; -+ reg = <0x0008e000 0x1000>; -+ #phy-cells = <0>; -+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>; -+ clock-names = "pipe_clk"; -+ clock-output-names = "pcie20_phy1_pipe_clk"; -+ -+ resets = <&gcc GCC_PCIE1_PHY_BCR>, -+ <&gcc GCC_PCIE1PHY_PHY_BCR>; -+ reset-names = "phy", -+ "common"; -+ status = "disabled"; -+ }; -+ - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq8074-pinctrl"; -- reg = <0x1000000 0x300000>; -+ reg = <0x01000000 0x300000>; - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 70>; -@@ -66,102 +162,16 @@ - }; - }; - -- intc: interrupt-controller@b000000 { -- compatible = "qcom,msm-qgic2"; -- interrupt-controller; -- #interrupt-cells = <0x3>; -- reg = <0xb000000 0x1000>, <0xb002000 0x1000>; -- }; -- -- timer { -- compatible = "arm,armv8-timer"; -- interrupts = , -- , -- , -- ; -- }; -- -- timer@b120000 { -- #address-cells = <1>; -- #size-cells = <1>; -- ranges; -- compatible = "arm,armv7-timer-mem"; -- reg = <0xb120000 0x1000>; -- clock-frequency = <19200000>; -- -- frame@b120000 { -- frame-number = <0>; -- interrupts = , -- ; -- reg = <0xb121000 0x1000>, -- <0xb122000 0x1000>; -- }; -- -- frame@b123000 { -- frame-number = <1>; -- interrupts = ; -- reg = <0xb123000 0x1000>; -- status = "disabled"; -- }; -- -- frame@b124000 { -- frame-number = <2>; -- interrupts = ; -- reg = <0xb124000 0x1000>; -- status = "disabled"; -- }; -- -- frame@b125000 { -- frame-number = <3>; -- interrupts = ; -- reg = <0xb125000 0x1000>; -- status = "disabled"; -- }; -- -- frame@b126000 { -- frame-number = <4>; -- interrupts = ; -- reg = <0xb126000 0x1000>; -- status = "disabled"; -- }; -- -- frame@b127000 { -- frame-number = <5>; -- interrupts = ; -- reg = <0xb127000 0x1000>; -- status = "disabled"; -- }; -- -- frame@b128000 { -- frame-number = <6>; -- interrupts = ; -- reg = <0xb128000 0x1000>; -- status = "disabled"; -- }; -- }; -- - gcc: gcc@1800000 { - compatible = "qcom,gcc-ipq8074"; -- reg = <0x1800000 0x80000>; -+ reg = <0x01800000 0x80000>; - #clock-cells = <0x1>; - #reset-cells = <0x1>; - }; - -- blsp1_uart5: serial@78b3000 { -- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -- reg = <0x78b3000 0x200>; -- interrupts = ; -- clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, -- <&gcc GCC_BLSP1_AHB_CLK>; -- clock-names = "core", "iface"; -- pinctrl-0 = <&serial_4_pins>; -- pinctrl-names = "default"; -- status = "disabled"; -- }; -- - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; -- reg = <0x7884000 0x2b000>; -+ reg = <0x07884000 0x2b000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; -@@ -171,7 +181,7 @@ - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -- reg = <0x78af000 0x200>; -+ reg = <0x078af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; -@@ -181,7 +191,7 @@ - - blsp1_uart3: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -- reg = <0x78b1000 0x200>; -+ reg = <0x078b1000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; -@@ -194,11 +204,23 @@ - status = "disabled"; - }; - -+ blsp1_uart5: serial@78b3000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x078b3000 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ pinctrl-0 = <&serial_4_pins>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+ }; -+ - blsp1_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; -- reg = <0x78b5000 0x600>; -+ reg = <0x078b5000 0x600>; - interrupts = ; - spi-max-frequency = <50000000>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, -@@ -215,7 +237,7 @@ - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; -- reg = <0x78b6000 0x600>; -+ reg = <0x078b6000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; -@@ -232,7 +254,7 @@ - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; -- reg = <0x78b7000 0x600>; -+ reg = <0x078b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; -@@ -245,7 +267,7 @@ - - qpic_bam: dma@7984000 { - compatible = "qcom,bam-v1.7.0"; -- reg = <0x7984000 0x1a000>; -+ reg = <0x07984000 0x1a000>; - interrupts = ; - clocks = <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "bam_clk"; -@@ -256,7 +278,7 @@ - - qpic_nand: nand@79b0000 { - compatible = "qcom,ipq8074-nand"; -- reg = <0x79b0000 0x10000>; -+ reg = <0x079b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&gcc GCC_QPIC_CLK>, -@@ -272,104 +294,85 @@ - status = "disabled"; - }; - -- pcie_phy0: phy@86000 { -- compatible = "qcom,ipq8074-qmp-pcie-phy"; -- reg = <0x86000 0x1000>; -- #phy-cells = <0>; -- clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -- clock-names = "pipe_clk"; -- clock-output-names = "pcie20_phy0_pipe_clk"; -+ intc: interrupt-controller@b000000 { -+ compatible = "qcom,msm-qgic2"; -+ interrupt-controller; -+ #interrupt-cells = <0x3>; -+ reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; -+ }; - -- resets = <&gcc GCC_PCIE0_PHY_BCR>, -- <&gcc GCC_PCIE0PHY_PHY_BCR>; -- reset-names = "phy", -- "common"; -- status = "disabled"; -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; - }; - -- pcie0: pci@20000000 { -- compatible = "qcom,pcie-ipq8074"; -- reg = <0x20000000 0xf1d -- 0x20000f20 0xa8 -- 0x80000 0x2000 -- 0x20100000 0x1000>; -- reg-names = "dbi", "elbi", "parf", "config"; -- device_type = "pci"; -- linux,pci-domain = <0>; -- bus-range = <0x00 0xff>; -- num-lanes = <1>; -- #address-cells = <3>; -- #size-cells = <2>; -+ timer@b120000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ compatible = "arm,armv7-timer-mem"; -+ reg = <0x0b120000 0x1000>; -+ clock-frequency = <19200000>; - -- phys = <&pcie_phy0>; -- phy-names = "pciephy"; -+ frame@b120000 { -+ frame-number = <0>; -+ interrupts = , -+ ; -+ reg = <0x0b121000 0x1000>, -+ <0x0b122000 0x1000>; -+ }; - -- ranges = <0x81000000 0 0x20200000 0x20200000 -- 0 0x100000 /* downstream I/O */ -- 0x82000000 0 0x20300000 0x20300000 -- 0 0xd00000>; /* non-prefetchable memory */ -+ frame@b123000 { -+ frame-number = <1>; -+ interrupts = ; -+ reg = <0x0b123000 0x1000>; -+ status = "disabled"; -+ }; - -- interrupts = ; -- interrupt-names = "msi"; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 0x7>; -- interrupt-map = <0 0 0 1 &intc 0 75 -- IRQ_TYPE_LEVEL_HIGH>, /* int_a */ -- <0 0 0 2 &intc 0 78 -- IRQ_TYPE_LEVEL_HIGH>, /* int_b */ -- <0 0 0 3 &intc 0 79 -- IRQ_TYPE_LEVEL_HIGH>, /* int_c */ -- <0 0 0 4 &intc 0 83 -- IRQ_TYPE_LEVEL_HIGH>; /* int_d */ -+ frame@b124000 { -+ frame-number = <2>; -+ interrupts = ; -+ reg = <0x0b124000 0x1000>; -+ status = "disabled"; -+ }; - -- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, -- <&gcc GCC_PCIE0_AXI_M_CLK>, -- <&gcc GCC_PCIE0_AXI_S_CLK>, -- <&gcc GCC_PCIE0_AHB_CLK>, -- <&gcc GCC_PCIE0_AUX_CLK>; -+ frame@b125000 { -+ frame-number = <3>; -+ interrupts = ; -+ reg = <0x0b125000 0x1000>; -+ status = "disabled"; -+ }; - -- clock-names = "iface", -- "axi_m", -- "axi_s", -- "ahb", -- "aux"; -- resets = <&gcc GCC_PCIE0_PIPE_ARES>, -- <&gcc GCC_PCIE0_SLEEP_ARES>, -- <&gcc GCC_PCIE0_CORE_STICKY_ARES>, -- <&gcc GCC_PCIE0_AXI_MASTER_ARES>, -- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, -- <&gcc GCC_PCIE0_AHB_ARES>, -- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; -- reset-names = "pipe", -- "sleep", -- "sticky", -- "axi_m", -- "axi_s", -- "ahb", -- "axi_m_sticky"; -- status = "disabled"; -- }; -+ frame@b126000 { -+ frame-number = <4>; -+ interrupts = ; -+ reg = <0x0b126000 0x1000>; -+ status = "disabled"; -+ }; - -- pcie_phy1: phy@8e000 { -- compatible = "qcom,ipq8074-qmp-pcie-phy"; -- reg = <0x8e000 0x1000>; -- #phy-cells = <0>; -- clocks = <&gcc GCC_PCIE1_PIPE_CLK>; -- clock-names = "pipe_clk"; -- clock-output-names = "pcie20_phy1_pipe_clk"; -+ frame@b127000 { -+ frame-number = <5>; -+ interrupts = ; -+ reg = <0x0b127000 0x1000>; -+ status = "disabled"; -+ }; - -- resets = <&gcc GCC_PCIE1_PHY_BCR>, -- <&gcc GCC_PCIE1PHY_PHY_BCR>; -- reset-names = "phy", -- "common"; -- status = "disabled"; -+ frame@b128000 { -+ frame-number = <6>; -+ interrupts = ; -+ reg = <0x0b128000 0x1000>; -+ status = "disabled"; -+ }; - }; - - pcie1: pci@10000000 { - compatible = "qcom,pcie-ipq8074"; - reg = <0x10000000 0xf1d - 0x10000f20 0xa8 -- 0x88000 0x2000 -+ 0x00088000 0x2000 - 0x10100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; -@@ -426,71 +429,68 @@ - "axi_m_sticky"; - status = "disabled"; - }; -- }; -- -- cpus { -- #address-cells = <0x1>; -- #size-cells = <0x0>; -- -- CPU0: cpu@0 { -- device_type = "cpu"; -- compatible = "arm,cortex-a53"; -- reg = <0x0>; -- next-level-cache = <&L2_0>; -- enable-method = "psci"; -- }; -- -- CPU1: cpu@1 { -- device_type = "cpu"; -- compatible = "arm,cortex-a53"; -- enable-method = "psci"; -- reg = <0x1>; -- next-level-cache = <&L2_0>; -- }; - -- CPU2: cpu@2 { -- device_type = "cpu"; -- compatible = "arm,cortex-a53"; -- enable-method = "psci"; -- reg = <0x2>; -- next-level-cache = <&L2_0>; -- }; -- -- CPU3: cpu@3 { -- device_type = "cpu"; -- compatible = "arm,cortex-a53"; -- enable-method = "psci"; -- reg = <0x3>; -- next-level-cache = <&L2_0>; -- }; -+ pcie0: pci@20000000 { -+ compatible = "qcom,pcie-ipq8074"; -+ reg = <0x20000000 0xf1d -+ 0x20000f20 0xa8 -+ 0x00080000 0x2000 -+ 0x20100000 0x1000>; -+ reg-names = "dbi", "elbi", "parf", "config"; -+ device_type = "pci"; -+ linux,pci-domain = <0>; -+ bus-range = <0x00 0xff>; -+ num-lanes = <1>; -+ #address-cells = <3>; -+ #size-cells = <2>; - -- L2_0: l2-cache { -- compatible = "cache"; -- cache-level = <0x2>; -- }; -- }; -+ phys = <&pcie_phy0>; -+ phy-names = "pciephy"; - -- psci { -- compatible = "arm,psci-1.0"; -- method = "smc"; -- }; -+ ranges = <0x81000000 0 0x20200000 0x20200000 -+ 0 0x100000 /* downstream I/O */ -+ 0x82000000 0 0x20300000 0x20300000 -+ 0 0xd00000>; /* non-prefetchable memory */ - -- pmu { -- compatible = "arm,armv8-pmuv3"; -- interrupts = ; -- }; -+ interrupts = ; -+ interrupt-names = "msi"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &intc 0 75 -+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */ -+ <0 0 0 2 &intc 0 78 -+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */ -+ <0 0 0 3 &intc 0 79 -+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ -+ <0 0 0 4 &intc 0 83 -+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - -- clocks { -- sleep_clk: sleep_clk { -- compatible = "fixed-clock"; -- clock-frequency = <32000>; -- #clock-cells = <0>; -- }; -+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, -+ <&gcc GCC_PCIE0_AXI_M_CLK>, -+ <&gcc GCC_PCIE0_AXI_S_CLK>, -+ <&gcc GCC_PCIE0_AHB_CLK>, -+ <&gcc GCC_PCIE0_AUX_CLK>; - -- xo: xo { -- compatible = "fixed-clock"; -- clock-frequency = <19200000>; -- #clock-cells = <0>; -+ clock-names = "iface", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "aux"; -+ resets = <&gcc GCC_PCIE0_PIPE_ARES>, -+ <&gcc GCC_PCIE0_SLEEP_ARES>, -+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, -+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>, -+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, -+ <&gcc GCC_PCIE0_AHB_ARES>, -+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; -+ reset-names = "pipe", -+ "sleep", -+ "sticky", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "axi_m_sticky"; -+ status = "disabled"; - }; - }; - }; diff --git a/target/linux/ipq807x/patches-5.4/0003-v5.9-arm64-dts-ipq8074-enable-sdhci-node.patch b/target/linux/ipq807x/patches-5.4/0003-v5.9-arm64-dts-ipq8074-enable-sdhci-node.patch deleted file mode 100644 index 92aefcd89..000000000 --- a/target/linux/ipq807x/patches-5.4/0003-v5.9-arm64-dts-ipq8074-enable-sdhci-node.patch +++ /dev/null @@ -1,56 +0,0 @@ -From cbc142c89543eb8c506ae0e0f0a36c82d91b5171 Mon Sep 17 00:00:00 2001 -From: Sivaprakash Murugesan -Date: Tue, 9 Jun 2020 17:05:11 +0530 -Subject: [PATCH] arm64: dts: ipq8074: enable sdhci node - -Enable mmc device found on ipq8074 devices - -Signed-off-by: Sivaprakash Murugesan -Link: https://lore.kernel.org/r/1591702511-18571-1-git-send-email-sivaprak@codeaurora.org -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 4 ++++ - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 22 ++++++++++++++++++++++ - 2 files changed, 26 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts -@@ -82,3 +82,7 @@ - nand-bus-width = <8>; - }; - }; -+ -+&sdhc_1 { -+ status = "ok"; -+}; ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -169,6 +169,28 @@ - #reset-cells = <0x1>; - }; - -+ sdhc_1: sdhci@7824900 { -+ compatible = "qcom,sdhci-msm-v4"; -+ reg = <0x7824900 0x500>, <0x7824000 0x800>; -+ reg-names = "hc_mem", "core_mem"; -+ -+ interrupts = , -+ ; -+ interrupt-names = "hc_irq", "pwr_irq"; -+ -+ clocks = <&xo>, -+ <&gcc GCC_SDCC1_AHB_CLK>, -+ <&gcc GCC_SDCC1_APPS_CLK>; -+ clock-names = "xo", "iface", "core"; -+ max-frequency = <384000000>; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ bus-width = <8>; -+ -+ status = "disabled"; -+ }; -+ - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x2b000>; diff --git a/target/linux/ipq807x/patches-5.4/0005-v5.9-mtd-rawnand-qcom-set-BAM-mode-only-if-not-set-alread.patch b/target/linux/ipq807x/patches-5.4/0005-v5.9-mtd-rawnand-qcom-set-BAM-mode-only-if-not-set-alread.patch deleted file mode 100644 index fd3ac1571..000000000 --- a/target/linux/ipq807x/patches-5.4/0005-v5.9-mtd-rawnand-qcom-set-BAM-mode-only-if-not-set-alread.patch +++ /dev/null @@ -1,42 +0,0 @@ -From cb272395dceef1652247dad08a50ed4153ffbd43 Mon Sep 17 00:00:00 2001 -From: Sivaprakash Murugesan -Date: Fri, 12 Jun 2020 13:28:16 +0530 -Subject: [PATCH] mtd: rawnand: qcom: set BAM mode only if not set already - -BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver -is set by writing BAM_MODE_EN bit on NAND_CTRL register. - -NAND_CTRL is an operational register and in BAM mode operational -registers are read only. - -So, before enabling BAM mode by writing the NAND_CTRL register, check -if BAM mode was already enabled by the bootloader, and enable BAM mode -only if it is not enabled already. - -Signed-off-by: Sivaprakash Murugesan -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/1591948696-16015-3-git-send-email-sivaprak@codeaurora.org ---- - drivers/mtd/nand/raw/qcom_nandc.c | 11 ++++++++++- - 1 file changed, 10 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/raw/qcom_nandc.c -+++ b/drivers/mtd/nand/raw/qcom_nandc.c -@@ -2761,7 +2761,16 @@ static int qcom_nandc_setup(struct qcom_ - /* enable ADM or BAM DMA */ - if (nandc->props->is_bam) { - nand_ctrl = nandc_read(nandc, NAND_CTRL); -- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); -+ -+ /* -+ *NAND_CTRL is an operational registers, and CPU -+ * access to operational registers are read only -+ * in BAM mode. So update the NAND_CTRL register -+ * only if it is not in BAM mode. In most cases BAM -+ * mode will be enabled in bootloader -+ */ -+ if (!(nand_ctrl & BAM_MODE_EN)) -+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); - } else { - nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); - } diff --git a/target/linux/ipq807x/patches-5.4/0006-v5.9-clk-qcom-Add-DT-bindings-for-ipq6018-apss-clock-cont.patch b/target/linux/ipq807x/patches-5.4/0006-v5.9-clk-qcom-Add-DT-bindings-for-ipq6018-apss-clock-cont.patch deleted file mode 100644 index ef130a1c7..000000000 --- a/target/linux/ipq807x/patches-5.4/0006-v5.9-clk-qcom-Add-DT-bindings-for-ipq6018-apss-clock-cont.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 49bcaef86eba1a8097980f341e243ba01177a685 Mon Sep 17 00:00:00 2001 -From: Sivaprakash Murugesan -Date: Mon, 22 Jun 2020 09:58:11 +0530 -Subject: [PATCH] clk: qcom: Add DT bindings for ipq6018 apss clock controller - -Add dt-binding for ipq6018 apss clock controller - -Acked-by: Rob Herring -Signed-off-by: Sivaprakash Murugesan -Link: https://lore.kernel.org/r/1592800092-20533-4-git-send-email-sivaprak@codeaurora.org -Signed-off-by: Stephen Boyd ---- - include/dt-bindings/clock/qcom,apss-ipq.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h - ---- /dev/null -+++ b/include/dt-bindings/clock/qcom,apss-ipq.h -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (c) 2018, The Linux Foundation. All rights reserved. -+ */ -+ -+#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H -+#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H -+ -+#define APCS_ALIAS0_CLK_SRC 0 -+#define APCS_ALIAS0_CORE_CLK 1 -+ -+#endif diff --git a/target/linux/ipq807x/patches-5.4/0007-v5.7-net-qrtr-Migrate-nameservice-to-kernel-from-userspac.patch b/target/linux/ipq807x/patches-5.4/0007-v5.7-net-qrtr-Migrate-nameservice-to-kernel-from-userspac.patch deleted file mode 100644 index 22957d8fc..000000000 --- a/target/linux/ipq807x/patches-5.4/0007-v5.7-net-qrtr-Migrate-nameservice-to-kernel-from-userspac.patch +++ /dev/null @@ -1,882 +0,0 @@ -From 0c2204a4ad710d95d348ea006f14ba926e842ffd Mon Sep 17 00:00:00 2001 -From: Manivannan Sadhasivam -Date: Thu, 20 Feb 2020 20:43:26 +0530 -Subject: [PATCH] net: qrtr: Migrate nameservice to kernel from userspace - -The QRTR nameservice has been maintained in userspace for some time. This -commit migrates it to Linux kernel. This change is required in order to -eliminate the need of starting a userspace daemon for making the WiFi -functional for ath11k based devices. Since the QRTR NS is not usually -packed in most of the distros, users need to clone, build and install it -to get the WiFi working. It will become a hassle when the user doesn't -have any other source of network connectivity. - -Signed-off-by: Manivannan Sadhasivam -Signed-off-by: David S. Miller ---- - net/qrtr/Makefile | 2 +- - net/qrtr/ns.c | 751 ++++++++++++++++++++++++++++++++++++++++++++++ - net/qrtr/qrtr.c | 48 +-- - net/qrtr/qrtr.h | 4 + - 4 files changed, 766 insertions(+), 39 deletions(-) - create mode 100644 net/qrtr/ns.c - ---- a/net/qrtr/Makefile -+++ b/net/qrtr/Makefile -@@ -1,5 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0-only --obj-$(CONFIG_QRTR) := qrtr.o -+obj-$(CONFIG_QRTR) := qrtr.o ns.o - - obj-$(CONFIG_QRTR_SMD) += qrtr-smd.o - qrtr-smd-y := smd.o ---- /dev/null -+++ b/net/qrtr/ns.c -@@ -0,0 +1,751 @@ -+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -+/* -+ * Copyright (c) 2015, Sony Mobile Communications Inc. -+ * Copyright (c) 2013, The Linux Foundation. All rights reserved. -+ * Copyright (c) 2020, Linaro Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "qrtr.h" -+ -+static RADIX_TREE(nodes, GFP_KERNEL); -+ -+static struct { -+ struct socket *sock; -+ struct sockaddr_qrtr bcast_sq; -+ struct list_head lookups; -+ struct workqueue_struct *workqueue; -+ struct work_struct work; -+ int local_node; -+} qrtr_ns; -+ -+static const char * const qrtr_ctrl_pkt_strings[] = { -+ [QRTR_TYPE_HELLO] = "hello", -+ [QRTR_TYPE_BYE] = "bye", -+ [QRTR_TYPE_NEW_SERVER] = "new-server", -+ [QRTR_TYPE_DEL_SERVER] = "del-server", -+ [QRTR_TYPE_DEL_CLIENT] = "del-client", -+ [QRTR_TYPE_RESUME_TX] = "resume-tx", -+ [QRTR_TYPE_EXIT] = "exit", -+ [QRTR_TYPE_PING] = "ping", -+ [QRTR_TYPE_NEW_LOOKUP] = "new-lookup", -+ [QRTR_TYPE_DEL_LOOKUP] = "del-lookup", -+}; -+ -+struct qrtr_server_filter { -+ unsigned int service; -+ unsigned int instance; -+ unsigned int ifilter; -+}; -+ -+struct qrtr_lookup { -+ unsigned int service; -+ unsigned int instance; -+ -+ struct sockaddr_qrtr sq; -+ struct list_head li; -+}; -+ -+struct qrtr_server { -+ unsigned int service; -+ unsigned int instance; -+ -+ unsigned int node; -+ unsigned int port; -+ -+ struct list_head qli; -+}; -+ -+struct qrtr_node { -+ unsigned int id; -+ struct radix_tree_root servers; -+}; -+ -+static struct qrtr_node *node_get(unsigned int node_id) -+{ -+ struct qrtr_node *node; -+ -+ node = radix_tree_lookup(&nodes, node_id); -+ if (node) -+ return node; -+ -+ /* If node didn't exist, allocate and insert it to the tree */ -+ node = kzalloc(sizeof(*node), GFP_KERNEL); -+ if (!node) -+ return ERR_PTR(-ENOMEM); -+ -+ node->id = node_id; -+ -+ radix_tree_insert(&nodes, node_id, node); -+ -+ return node; -+} -+ -+static int server_match(const struct qrtr_server *srv, -+ const struct qrtr_server_filter *f) -+{ -+ unsigned int ifilter = f->ifilter; -+ -+ if (f->service != 0 && srv->service != f->service) -+ return 0; -+ if (!ifilter && f->instance) -+ ifilter = ~0; -+ -+ return (srv->instance & ifilter) == f->instance; -+} -+ -+static int service_announce_new(struct sockaddr_qrtr *dest, -+ struct qrtr_server *srv) -+{ -+ struct qrtr_ctrl_pkt pkt; -+ struct msghdr msg = { }; -+ struct kvec iv; -+ -+ trace_printk("advertising new server [%d:%x]@[%d:%d]\n", -+ srv->service, srv->instance, srv->node, srv->port); -+ -+ iv.iov_base = &pkt; -+ iv.iov_len = sizeof(pkt); -+ -+ memset(&pkt, 0, sizeof(pkt)); -+ pkt.cmd = cpu_to_le32(QRTR_TYPE_NEW_SERVER); -+ pkt.server.service = cpu_to_le32(srv->service); -+ pkt.server.instance = cpu_to_le32(srv->instance); -+ pkt.server.node = cpu_to_le32(srv->node); -+ pkt.server.port = cpu_to_le32(srv->port); -+ -+ msg.msg_name = (struct sockaddr *)dest; -+ msg.msg_namelen = sizeof(*dest); -+ -+ return kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); -+} -+ -+static int service_announce_del(struct sockaddr_qrtr *dest, -+ struct qrtr_server *srv) -+{ -+ struct qrtr_ctrl_pkt pkt; -+ struct msghdr msg = { }; -+ struct kvec iv; -+ int ret; -+ -+ trace_printk("advertising removal of server [%d:%x]@[%d:%d]\n", -+ srv->service, srv->instance, srv->node, srv->port); -+ -+ iv.iov_base = &pkt; -+ iv.iov_len = sizeof(pkt); -+ -+ memset(&pkt, 0, sizeof(pkt)); -+ pkt.cmd = cpu_to_le32(QRTR_TYPE_DEL_SERVER); -+ pkt.server.service = cpu_to_le32(srv->service); -+ pkt.server.instance = cpu_to_le32(srv->instance); -+ pkt.server.node = cpu_to_le32(srv->node); -+ pkt.server.port = cpu_to_le32(srv->port); -+ -+ msg.msg_name = (struct sockaddr *)dest; -+ msg.msg_namelen = sizeof(*dest); -+ -+ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); -+ if (ret < 0) -+ pr_err("failed to announce del serivce\n"); -+ -+ return ret; -+} -+ -+static void lookup_notify(struct sockaddr_qrtr *to, struct qrtr_server *srv, -+ bool new) -+{ -+ struct qrtr_ctrl_pkt pkt; -+ struct msghdr msg = { }; -+ struct kvec iv; -+ int ret; -+ -+ iv.iov_base = &pkt; -+ iv.iov_len = sizeof(pkt); -+ -+ memset(&pkt, 0, sizeof(pkt)); -+ pkt.cmd = new ? cpu_to_le32(QRTR_TYPE_NEW_SERVER) : -+ cpu_to_le32(QRTR_TYPE_DEL_SERVER); -+ if (srv) { -+ pkt.server.service = cpu_to_le32(srv->service); -+ pkt.server.instance = cpu_to_le32(srv->instance); -+ pkt.server.node = cpu_to_le32(srv->node); -+ pkt.server.port = cpu_to_le32(srv->port); -+ } -+ -+ msg.msg_name = (struct sockaddr *)to; -+ msg.msg_namelen = sizeof(*to); -+ -+ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); -+ if (ret < 0) -+ pr_err("failed to send lookup notification\n"); -+} -+ -+static int announce_servers(struct sockaddr_qrtr *sq) -+{ -+ struct radix_tree_iter iter; -+ struct qrtr_server *srv; -+ struct qrtr_node *node; -+ void __rcu **slot; -+ int ret; -+ -+ node = node_get(qrtr_ns.local_node); -+ if (!node) -+ return 0; -+ -+ /* Announce the list of servers registered in this node */ -+ radix_tree_for_each_slot(slot, &node->servers, &iter, 0) { -+ srv = radix_tree_deref_slot(slot); -+ -+ ret = service_announce_new(sq, srv); -+ if (ret < 0) { -+ pr_err("failed to announce new service\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static struct qrtr_server *server_add(unsigned int service, -+ unsigned int instance, -+ unsigned int node_id, -+ unsigned int port) -+{ -+ struct qrtr_server *srv; -+ struct qrtr_server *old; -+ struct qrtr_node *node; -+ -+ if (!service || !port) -+ return NULL; -+ -+ srv = kzalloc(sizeof(*srv), GFP_KERNEL); -+ if (!srv) -+ return ERR_PTR(-ENOMEM); -+ -+ srv->service = service; -+ srv->instance = instance; -+ srv->node = node_id; -+ srv->port = port; -+ -+ node = node_get(node_id); -+ if (!node) -+ goto err; -+ -+ /* Delete the old server on the same port */ -+ old = radix_tree_lookup(&node->servers, port); -+ if (old) { -+ radix_tree_delete(&node->servers, port); -+ kfree(old); -+ } -+ -+ radix_tree_insert(&node->servers, port, srv); -+ -+ trace_printk("add server [%d:%x]@[%d:%d]\n", srv->service, -+ srv->instance, srv->node, srv->port); -+ -+ return srv; -+ -+err: -+ kfree(srv); -+ return NULL; -+} -+ -+static int server_del(struct qrtr_node *node, unsigned int port) -+{ -+ struct qrtr_lookup *lookup; -+ struct qrtr_server *srv; -+ struct list_head *li; -+ -+ srv = radix_tree_lookup(&node->servers, port); -+ if (!srv) -+ return -ENOENT; -+ -+ radix_tree_delete(&node->servers, port); -+ -+ /* Broadcast the removal of local servers */ -+ if (srv->node == qrtr_ns.local_node) -+ service_announce_del(&qrtr_ns.bcast_sq, srv); -+ -+ /* Announce the service's disappearance to observers */ -+ list_for_each(li, &qrtr_ns.lookups) { -+ lookup = container_of(li, struct qrtr_lookup, li); -+ if (lookup->service && lookup->service != srv->service) -+ continue; -+ if (lookup->instance && lookup->instance != srv->instance) -+ continue; -+ -+ lookup_notify(&lookup->sq, srv, false); -+ } -+ -+ kfree(srv); -+ -+ return 0; -+} -+ -+/* Announce the list of servers registered on the local node */ -+static int ctrl_cmd_hello(struct sockaddr_qrtr *sq) -+{ -+ return announce_servers(sq); -+} -+ -+static int ctrl_cmd_bye(struct sockaddr_qrtr *from) -+{ -+ struct qrtr_node *local_node; -+ struct radix_tree_iter iter; -+ struct qrtr_ctrl_pkt pkt; -+ struct qrtr_server *srv; -+ struct sockaddr_qrtr sq; -+ struct msghdr msg = { }; -+ struct qrtr_node *node; -+ void __rcu **slot; -+ struct kvec iv; -+ int ret; -+ -+ iv.iov_base = &pkt; -+ iv.iov_len = sizeof(pkt); -+ -+ node = node_get(from->sq_node); -+ if (!node) -+ return 0; -+ -+ /* Advertise removal of this client to all servers of remote node */ -+ radix_tree_for_each_slot(slot, &node->servers, &iter, 0) { -+ srv = radix_tree_deref_slot(slot); -+ server_del(node, srv->port); -+ } -+ -+ /* Advertise the removal of this client to all local servers */ -+ local_node = node_get(qrtr_ns.local_node); -+ if (!local_node) -+ return 0; -+ -+ memset(&pkt, 0, sizeof(pkt)); -+ pkt.cmd = cpu_to_le32(QRTR_TYPE_BYE); -+ pkt.client.node = cpu_to_le32(from->sq_node); -+ -+ radix_tree_for_each_slot(slot, &local_node->servers, &iter, 0) { -+ srv = radix_tree_deref_slot(slot); -+ -+ sq.sq_family = AF_QIPCRTR; -+ sq.sq_node = srv->node; -+ sq.sq_port = srv->port; -+ -+ msg.msg_name = (struct sockaddr *)&sq; -+ msg.msg_namelen = sizeof(sq); -+ -+ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); -+ if (ret < 0) { -+ pr_err("failed to send bye cmd\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static int ctrl_cmd_del_client(struct sockaddr_qrtr *from, -+ unsigned int node_id, unsigned int port) -+{ -+ struct qrtr_node *local_node; -+ struct radix_tree_iter iter; -+ struct qrtr_lookup *lookup; -+ struct qrtr_ctrl_pkt pkt; -+ struct msghdr msg = { }; -+ struct qrtr_server *srv; -+ struct sockaddr_qrtr sq; -+ struct qrtr_node *node; -+ struct list_head *tmp; -+ struct list_head *li; -+ void __rcu **slot; -+ struct kvec iv; -+ int ret; -+ -+ iv.iov_base = &pkt; -+ iv.iov_len = sizeof(pkt); -+ -+ /* Don't accept spoofed messages */ -+ if (from->sq_node != node_id) -+ return -EINVAL; -+ -+ /* Local DEL_CLIENT messages comes from the port being closed */ -+ if (from->sq_node == qrtr_ns.local_node && from->sq_port != port) -+ return -EINVAL; -+ -+ /* Remove any lookups by this client */ -+ list_for_each_safe(li, tmp, &qrtr_ns.lookups) { -+ lookup = container_of(li, struct qrtr_lookup, li); -+ if (lookup->sq.sq_node != node_id) -+ continue; -+ if (lookup->sq.sq_port != port) -+ continue; -+ -+ list_del(&lookup->li); -+ kfree(lookup); -+ } -+ -+ /* Remove the server belonging to this port */ -+ node = node_get(node_id); -+ if (node) -+ server_del(node, port); -+ -+ /* Advertise the removal of this client to all local servers */ -+ local_node = node_get(qrtr_ns.local_node); -+ if (!local_node) -+ return 0; -+ -+ memset(&pkt, 0, sizeof(pkt)); -+ pkt.cmd = cpu_to_le32(QRTR_TYPE_DEL_CLIENT); -+ pkt.client.node = cpu_to_le32(node_id); -+ pkt.client.port = cpu_to_le32(port); -+ -+ radix_tree_for_each_slot(slot, &local_node->servers, &iter, 0) { -+ srv = radix_tree_deref_slot(slot); -+ -+ sq.sq_family = AF_QIPCRTR; -+ sq.sq_node = srv->node; -+ sq.sq_port = srv->port; -+ -+ msg.msg_name = (struct sockaddr *)&sq; -+ msg.msg_namelen = sizeof(sq); -+ -+ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); -+ if (ret < 0) { -+ pr_err("failed to send del client cmd\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static int ctrl_cmd_new_server(struct sockaddr_qrtr *from, -+ unsigned int service, unsigned int instance, -+ unsigned int node_id, unsigned int port) -+{ -+ struct qrtr_lookup *lookup; -+ struct qrtr_server *srv; -+ struct list_head *li; -+ int ret = 0; -+ -+ /* Ignore specified node and port for local servers */ -+ if (from->sq_node == qrtr_ns.local_node) { -+ node_id = from->sq_node; -+ port = from->sq_port; -+ } -+ -+ /* Don't accept spoofed messages */ -+ if (from->sq_node != node_id) -+ return -EINVAL; -+ -+ srv = server_add(service, instance, node_id, port); -+ if (!srv) -+ return -EINVAL; -+ -+ if (srv->node == qrtr_ns.local_node) { -+ ret = service_announce_new(&qrtr_ns.bcast_sq, srv); -+ if (ret < 0) { -+ pr_err("failed to announce new service\n"); -+ return ret; -+ } -+ } -+ -+ /* Notify any potential lookups about the new server */ -+ list_for_each(li, &qrtr_ns.lookups) { -+ lookup = container_of(li, struct qrtr_lookup, li); -+ if (lookup->service && lookup->service != service) -+ continue; -+ if (lookup->instance && lookup->instance != instance) -+ continue; -+ -+ lookup_notify(&lookup->sq, srv, true); -+ } -+ -+ return ret; -+} -+ -+static int ctrl_cmd_del_server(struct sockaddr_qrtr *from, -+ unsigned int service, unsigned int instance, -+ unsigned int node_id, unsigned int port) -+{ -+ struct qrtr_node *node; -+ -+ /* Ignore specified node and port for local servers*/ -+ if (from->sq_node == qrtr_ns.local_node) { -+ node_id = from->sq_node; -+ port = from->sq_port; -+ } -+ -+ /* Don't accept spoofed messages */ -+ if (from->sq_node != node_id) -+ return -EINVAL; -+ -+ /* Local servers may only unregister themselves */ -+ if (from->sq_node == qrtr_ns.local_node && from->sq_port != port) -+ return -EINVAL; -+ -+ node = node_get(node_id); -+ if (!node) -+ return -ENOENT; -+ -+ return server_del(node, port); -+} -+ -+static int ctrl_cmd_new_lookup(struct sockaddr_qrtr *from, -+ unsigned int service, unsigned int instance) -+{ -+ struct radix_tree_iter node_iter; -+ struct qrtr_server_filter filter; -+ struct radix_tree_iter srv_iter; -+ struct qrtr_lookup *lookup; -+ struct qrtr_node *node; -+ void __rcu **node_slot; -+ void __rcu **srv_slot; -+ -+ /* Accept only local observers */ -+ if (from->sq_node != qrtr_ns.local_node) -+ return -EINVAL; -+ -+ lookup = kzalloc(sizeof(*lookup), GFP_KERNEL); -+ if (!lookup) -+ return -ENOMEM; -+ -+ lookup->sq = *from; -+ lookup->service = service; -+ lookup->instance = instance; -+ list_add_tail(&lookup->li, &qrtr_ns.lookups); -+ -+ memset(&filter, 0, sizeof(filter)); -+ filter.service = service; -+ filter.instance = instance; -+ -+ radix_tree_for_each_slot(node_slot, &nodes, &node_iter, 0) { -+ node = radix_tree_deref_slot(node_slot); -+ -+ radix_tree_for_each_slot(srv_slot, &node->servers, -+ &srv_iter, 0) { -+ struct qrtr_server *srv; -+ -+ srv = radix_tree_deref_slot(srv_slot); -+ if (!server_match(srv, &filter)) -+ continue; -+ -+ lookup_notify(from, srv, true); -+ } -+ } -+ -+ /* Empty notification, to indicate end of listing */ -+ lookup_notify(from, NULL, true); -+ -+ return 0; -+} -+ -+static void ctrl_cmd_del_lookup(struct sockaddr_qrtr *from, -+ unsigned int service, unsigned int instance) -+{ -+ struct qrtr_lookup *lookup; -+ struct list_head *tmp; -+ struct list_head *li; -+ -+ list_for_each_safe(li, tmp, &qrtr_ns.lookups) { -+ lookup = container_of(li, struct qrtr_lookup, li); -+ if (lookup->sq.sq_node != from->sq_node) -+ continue; -+ if (lookup->sq.sq_port != from->sq_port) -+ continue; -+ if (lookup->service != service) -+ continue; -+ if (lookup->instance && lookup->instance != instance) -+ continue; -+ -+ list_del(&lookup->li); -+ kfree(lookup); -+ } -+} -+ -+static int say_hello(void) -+{ -+ struct qrtr_ctrl_pkt pkt; -+ struct msghdr msg = { }; -+ struct kvec iv; -+ int ret; -+ -+ iv.iov_base = &pkt; -+ iv.iov_len = sizeof(pkt); -+ -+ memset(&pkt, 0, sizeof(pkt)); -+ pkt.cmd = cpu_to_le32(QRTR_TYPE_HELLO); -+ -+ msg.msg_name = (struct sockaddr *)&qrtr_ns.bcast_sq; -+ msg.msg_namelen = sizeof(qrtr_ns.bcast_sq); -+ -+ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); -+ if (ret < 0) -+ pr_err("failed to send hello msg\n"); -+ -+ return ret; -+} -+ -+static void qrtr_ns_worker(struct work_struct *work) -+{ -+ const struct qrtr_ctrl_pkt *pkt; -+ size_t recv_buf_size = 4096; -+ struct sockaddr_qrtr sq; -+ struct msghdr msg = { }; -+ unsigned int cmd; -+ ssize_t msglen; -+ void *recv_buf; -+ struct kvec iv; -+ int ret; -+ -+ msg.msg_name = (struct sockaddr *)&sq; -+ msg.msg_namelen = sizeof(sq); -+ -+ recv_buf = kzalloc(recv_buf_size, GFP_KERNEL); -+ if (!recv_buf) -+ return; -+ -+ for (;;) { -+ iv.iov_base = recv_buf; -+ iv.iov_len = recv_buf_size; -+ -+ msglen = kernel_recvmsg(qrtr_ns.sock, &msg, &iv, 1, -+ iv.iov_len, MSG_DONTWAIT); -+ -+ if (msglen == -EAGAIN) -+ break; -+ -+ if (msglen < 0) { -+ pr_err("error receiving packet: %zd\n", msglen); -+ break; -+ } -+ -+ pkt = recv_buf; -+ cmd = le32_to_cpu(pkt->cmd); -+ if (cmd < ARRAY_SIZE(qrtr_ctrl_pkt_strings) && -+ qrtr_ctrl_pkt_strings[cmd]) -+ trace_printk("%s from %d:%d\n", -+ qrtr_ctrl_pkt_strings[cmd], sq.sq_node, -+ sq.sq_port); -+ -+ ret = 0; -+ switch (cmd) { -+ case QRTR_TYPE_HELLO: -+ ret = ctrl_cmd_hello(&sq); -+ break; -+ case QRTR_TYPE_BYE: -+ ret = ctrl_cmd_bye(&sq); -+ break; -+ case QRTR_TYPE_DEL_CLIENT: -+ ret = ctrl_cmd_del_client(&sq, -+ le32_to_cpu(pkt->client.node), -+ le32_to_cpu(pkt->client.port)); -+ break; -+ case QRTR_TYPE_NEW_SERVER: -+ ret = ctrl_cmd_new_server(&sq, -+ le32_to_cpu(pkt->server.service), -+ le32_to_cpu(pkt->server.instance), -+ le32_to_cpu(pkt->server.node), -+ le32_to_cpu(pkt->server.port)); -+ break; -+ case QRTR_TYPE_DEL_SERVER: -+ ret = ctrl_cmd_del_server(&sq, -+ le32_to_cpu(pkt->server.service), -+ le32_to_cpu(pkt->server.instance), -+ le32_to_cpu(pkt->server.node), -+ le32_to_cpu(pkt->server.port)); -+ break; -+ case QRTR_TYPE_EXIT: -+ case QRTR_TYPE_PING: -+ case QRTR_TYPE_RESUME_TX: -+ break; -+ case QRTR_TYPE_NEW_LOOKUP: -+ ret = ctrl_cmd_new_lookup(&sq, -+ le32_to_cpu(pkt->server.service), -+ le32_to_cpu(pkt->server.instance)); -+ break; -+ case QRTR_TYPE_DEL_LOOKUP: -+ ctrl_cmd_del_lookup(&sq, -+ le32_to_cpu(pkt->server.service), -+ le32_to_cpu(pkt->server.instance)); -+ break; -+ } -+ -+ if (ret < 0) -+ pr_err("failed while handling packet from %d:%d", -+ sq.sq_node, sq.sq_port); -+ } -+ -+ kfree(recv_buf); -+} -+ -+static void qrtr_ns_data_ready(struct sock *sk) -+{ -+ queue_work(qrtr_ns.workqueue, &qrtr_ns.work); -+} -+ -+void qrtr_ns_init(struct work_struct *work) -+{ -+ struct sockaddr_qrtr sq; -+ int ret; -+ -+ INIT_LIST_HEAD(&qrtr_ns.lookups); -+ INIT_WORK(&qrtr_ns.work, qrtr_ns_worker); -+ -+ ret = sock_create_kern(&init_net, AF_QIPCRTR, SOCK_DGRAM, -+ PF_QIPCRTR, &qrtr_ns.sock); -+ if (ret < 0) -+ return; -+ -+ ret = kernel_getsockname(qrtr_ns.sock, (struct sockaddr *)&sq); -+ if (ret < 0) { -+ pr_err("failed to get socket name\n"); -+ goto err_sock; -+ } -+ -+ qrtr_ns.sock->sk->sk_data_ready = qrtr_ns_data_ready; -+ -+ sq.sq_port = QRTR_PORT_CTRL; -+ qrtr_ns.local_node = sq.sq_node; -+ -+ ret = kernel_bind(qrtr_ns.sock, (struct sockaddr *)&sq, sizeof(sq)); -+ if (ret < 0) { -+ pr_err("failed to bind to socket\n"); -+ goto err_sock; -+ } -+ -+ qrtr_ns.bcast_sq.sq_family = AF_QIPCRTR; -+ qrtr_ns.bcast_sq.sq_node = QRTR_NODE_BCAST; -+ qrtr_ns.bcast_sq.sq_port = QRTR_PORT_CTRL; -+ -+ qrtr_ns.workqueue = alloc_workqueue("qrtr_ns_handler", WQ_UNBOUND, 1); -+ if (!qrtr_ns.workqueue) -+ goto err_sock; -+ -+ ret = say_hello(); -+ if (ret < 0) -+ goto err_wq; -+ -+ return; -+ -+err_wq: -+ destroy_workqueue(qrtr_ns.workqueue); -+err_sock: -+ sock_release(qrtr_ns.sock); -+} -+EXPORT_SYMBOL_GPL(qrtr_ns_init); -+ -+void qrtr_ns_remove(void) -+{ -+ cancel_work_sync(&qrtr_ns.work); -+ destroy_workqueue(qrtr_ns.workqueue); -+ sock_release(qrtr_ns.sock); -+} -+EXPORT_SYMBOL_GPL(qrtr_ns_remove); -+ -+MODULE_AUTHOR("Manivannan Sadhasivam "); -+MODULE_DESCRIPTION("Qualcomm IPC Router Nameservice"); -+MODULE_LICENSE("Dual BSD/GPL"); ---- a/net/qrtr/qrtr.c -+++ b/net/qrtr/qrtr.c -@@ -8,6 +8,7 @@ - #include - #include /* For TIOCINQ/OUTQ */ - #include -+#include - - #include - -@@ -107,6 +108,8 @@ static DEFINE_MUTEX(qrtr_node_lock); - static DEFINE_IDR(qrtr_ports); - static DEFINE_MUTEX(qrtr_port_lock); - -+static struct delayed_work qrtr_ns_work; -+ - /** - * struct qrtr_node - endpoint node - * @ep_lock: lock for endpoint management and callbacks -@@ -1072,38 +1075,6 @@ static int qrtr_create(struct net *net, - return 0; - } - --static const struct nla_policy qrtr_policy[IFA_MAX + 1] = { -- [IFA_LOCAL] = { .type = NLA_U32 }, --}; -- --static int qrtr_addr_doit(struct sk_buff *skb, struct nlmsghdr *nlh, -- struct netlink_ext_ack *extack) --{ -- struct nlattr *tb[IFA_MAX + 1]; -- struct ifaddrmsg *ifm; -- int rc; -- -- if (!netlink_capable(skb, CAP_NET_ADMIN)) -- return -EPERM; -- -- if (!netlink_capable(skb, CAP_SYS_ADMIN)) -- return -EPERM; -- -- ASSERT_RTNL(); -- -- rc = nlmsg_parse_deprecated(nlh, sizeof(*ifm), tb, IFA_MAX, -- qrtr_policy, extack); -- if (rc < 0) -- return rc; -- -- ifm = nlmsg_data(nlh); -- if (!tb[IFA_LOCAL]) -- return -EINVAL; -- -- qrtr_local_nid = nla_get_u32(tb[IFA_LOCAL]); -- return 0; --} -- - static const struct net_proto_family qrtr_family = { - .owner = THIS_MODULE, - .family = AF_QIPCRTR, -@@ -1124,11 +1095,11 @@ static int __init qrtr_proto_init(void) - return rc; - } - -- rc = rtnl_register_module(THIS_MODULE, PF_QIPCRTR, RTM_NEWADDR, qrtr_addr_doit, NULL, 0); -- if (rc) { -- sock_unregister(qrtr_family.family); -- proto_unregister(&qrtr_proto); -- } -+ /* FIXME: Currently, this 2s delay is required to catch the NEW_SERVER -+ * messages from routers. But the fix could be somewhere else. -+ */ -+ INIT_DELAYED_WORK(&qrtr_ns_work, qrtr_ns_init); -+ schedule_delayed_work(&qrtr_ns_work, msecs_to_jiffies(2000)); - - return rc; - } -@@ -1136,7 +1107,8 @@ postcore_initcall(qrtr_proto_init); - - static void __exit qrtr_proto_fini(void) - { -- rtnl_unregister(PF_QIPCRTR, RTM_NEWADDR); -+ cancel_delayed_work_sync(&qrtr_ns_work); -+ qrtr_ns_remove(); - sock_unregister(qrtr_family.family); - proto_unregister(&qrtr_proto); - } ---- a/net/qrtr/qrtr.h -+++ b/net/qrtr/qrtr.h -@@ -29,4 +29,8 @@ void qrtr_endpoint_unregister(struct qrt - - int qrtr_endpoint_post(struct qrtr_endpoint *ep, const void *data, size_t len); - -+void qrtr_ns_init(struct work_struct *work); -+ -+void qrtr_ns_remove(void); -+ - #endif diff --git a/target/linux/ipq807x/patches-5.4/0008-v5.7-net-qrtr-Fix-error-pointer-vs-NULL-bugs.patch b/target/linux/ipq807x/patches-5.4/0008-v5.7-net-qrtr-Fix-error-pointer-vs-NULL-bugs.patch deleted file mode 100644 index 49ad3915b..000000000 --- a/target/linux/ipq807x/patches-5.4/0008-v5.7-net-qrtr-Fix-error-pointer-vs-NULL-bugs.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 9baeea50718fdd55c7ae4d61c15f2a71aef6e050 Mon Sep 17 00:00:00 2001 -From: Dan Carpenter -Date: Wed, 26 Feb 2020 17:51:53 +0300 -Subject: [PATCH] net: qrtr: Fix error pointer vs NULL bugs - -The callers only expect NULL pointers, so returning an error pointer -will lead to an Oops. - -Fixes: 0c2204a4ad71 ("net: qrtr: Migrate nameservice to kernel from userspace") -Signed-off-by: Dan Carpenter -Signed-off-by: David S. Miller ---- - net/qrtr/ns.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/net/qrtr/ns.c -+++ b/net/qrtr/ns.c -@@ -76,7 +76,7 @@ static struct qrtr_node *node_get(unsign - /* If node didn't exist, allocate and insert it to the tree */ - node = kzalloc(sizeof(*node), GFP_KERNEL); - if (!node) -- return ERR_PTR(-ENOMEM); -+ return NULL; - - node->id = node_id; - -@@ -224,7 +224,7 @@ static struct qrtr_server *server_add(un - - srv = kzalloc(sizeof(*srv), GFP_KERNEL); - if (!srv) -- return ERR_PTR(-ENOMEM); -+ return NULL; - - srv->service = service; - srv->instance = instance; diff --git a/target/linux/ipq807x/patches-5.4/0009-v5.7-net-qrtr-Respond-to-HELLO-message.patch b/target/linux/ipq807x/patches-5.4/0009-v5.7-net-qrtr-Respond-to-HELLO-message.patch deleted file mode 100644 index 59e5b688f..000000000 --- a/target/linux/ipq807x/patches-5.4/0009-v5.7-net-qrtr-Respond-to-HELLO-message.patch +++ /dev/null @@ -1,104 +0,0 @@ -From a1dc1d6a05a730b62b45828975a088db577d3139 Mon Sep 17 00:00:00 2001 -From: Bjorn Andersson -Date: Sun, 1 Mar 2020 23:03:04 -0800 -Subject: [PATCH] net: qrtr: Respond to HELLO message - -Lost in the translation from the user space implementation was the -detail that HELLO mesages must be exchanged between each node pair. As -such the incoming HELLO must be replied to. - -Similar to the previous implementation no effort is made to prevent two -Linux boxes from continuously sending HELLO messages back and forth, -this is left to a follow up patch. - -say_hello() is moved, to facilitate the new call site. - -Fixes: 0c2204a4ad71 ("net: qrtr: Migrate nameservice to kernel from userspace") -Reviewed-by: Manivannan Sadhasivam -Tested-by: Manivannan Sadhasivam -Signed-off-by: Bjorn Andersson -Signed-off-by: David S. Miller ---- - net/qrtr/ns.c | 54 ++++++++++++++++++++++++++++----------------------- - 1 file changed, 30 insertions(+), 24 deletions(-) - ---- a/net/qrtr/ns.c -+++ b/net/qrtr/ns.c -@@ -286,9 +286,38 @@ static int server_del(struct qrtr_node * - return 0; - } - -+static int say_hello(struct sockaddr_qrtr *dest) -+{ -+ struct qrtr_ctrl_pkt pkt; -+ struct msghdr msg = { }; -+ struct kvec iv; -+ int ret; -+ -+ iv.iov_base = &pkt; -+ iv.iov_len = sizeof(pkt); -+ -+ memset(&pkt, 0, sizeof(pkt)); -+ pkt.cmd = cpu_to_le32(QRTR_TYPE_HELLO); -+ -+ msg.msg_name = (struct sockaddr *)dest; -+ msg.msg_namelen = sizeof(*dest); -+ -+ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); -+ if (ret < 0) -+ pr_err("failed to send hello msg\n"); -+ -+ return ret; -+} -+ - /* Announce the list of servers registered on the local node */ - static int ctrl_cmd_hello(struct sockaddr_qrtr *sq) - { -+ int ret; -+ -+ ret = say_hello(sq); -+ if (ret < 0) -+ return ret; -+ - return announce_servers(sq); - } - -@@ -566,29 +595,6 @@ static void ctrl_cmd_del_lookup(struct s - } - } - --static int say_hello(void) --{ -- struct qrtr_ctrl_pkt pkt; -- struct msghdr msg = { }; -- struct kvec iv; -- int ret; -- -- iv.iov_base = &pkt; -- iv.iov_len = sizeof(pkt); -- -- memset(&pkt, 0, sizeof(pkt)); -- pkt.cmd = cpu_to_le32(QRTR_TYPE_HELLO); -- -- msg.msg_name = (struct sockaddr *)&qrtr_ns.bcast_sq; -- msg.msg_namelen = sizeof(qrtr_ns.bcast_sq); -- -- ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); -- if (ret < 0) -- pr_err("failed to send hello msg\n"); -- -- return ret; --} -- - static void qrtr_ns_worker(struct work_struct *work) - { - const struct qrtr_ctrl_pkt *pkt; -@@ -725,7 +731,7 @@ void qrtr_ns_init(struct work_struct *wo - if (!qrtr_ns.workqueue) - goto err_sock; - -- ret = say_hello(); -+ ret = say_hello(&qrtr_ns.bcast_sq); - if (ret < 0) - goto err_wq; - diff --git a/target/linux/ipq807x/patches-5.4/0010-v5.7-net-qrtr-Fix-FIXME-related-to-qrtr_ns_init.patch b/target/linux/ipq807x/patches-5.4/0010-v5.7-net-qrtr-Fix-FIXME-related-to-qrtr_ns_init.patch deleted file mode 100644 index 9d71b0a57..000000000 --- a/target/linux/ipq807x/patches-5.4/0010-v5.7-net-qrtr-Fix-FIXME-related-to-qrtr_ns_init.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 71046abfffe9d34ae90c82cf9c8e44355c2e114c Mon Sep 17 00:00:00 2001 -From: Bjorn Andersson -Date: Sun, 1 Mar 2020 23:03:05 -0800 -Subject: [PATCH] net: qrtr: Fix FIXME related to qrtr_ns_init() - -The 2 second delay before calling qrtr_ns_init() meant that the remote -processors would register as endpoints in qrtr and the say_hello() call -would therefor broadcast the outgoing HELLO to them. With the HELLO -handshake corrected this delay is no longer needed. - -Reviewed-by: Manivannan Sadhasivam -Tested-by: Manivannan Sadhasivam -Signed-off-by: Bjorn Andersson -Signed-off-by: David S. Miller ---- - net/qrtr/ns.c | 2 +- - net/qrtr/qrtr.c | 10 +--------- - net/qrtr/qrtr.h | 2 +- - 3 files changed, 3 insertions(+), 11 deletions(-) - ---- a/net/qrtr/ns.c -+++ b/net/qrtr/ns.c -@@ -693,7 +693,7 @@ static void qrtr_ns_data_ready(struct so - queue_work(qrtr_ns.workqueue, &qrtr_ns.work); - } - --void qrtr_ns_init(struct work_struct *work) -+void qrtr_ns_init(void) - { - struct sockaddr_qrtr sq; - int ret; ---- a/net/qrtr/qrtr.c -+++ b/net/qrtr/qrtr.c -@@ -8,7 +8,6 @@ - #include - #include /* For TIOCINQ/OUTQ */ - #include --#include - - #include - -@@ -108,8 +107,6 @@ static DEFINE_MUTEX(qrtr_node_lock); - static DEFINE_IDR(qrtr_ports); - static DEFINE_MUTEX(qrtr_port_lock); - --static struct delayed_work qrtr_ns_work; -- - /** - * struct qrtr_node - endpoint node - * @ep_lock: lock for endpoint management and callbacks -@@ -1095,11 +1092,7 @@ static int __init qrtr_proto_init(void) - return rc; - } - -- /* FIXME: Currently, this 2s delay is required to catch the NEW_SERVER -- * messages from routers. But the fix could be somewhere else. -- */ -- INIT_DELAYED_WORK(&qrtr_ns_work, qrtr_ns_init); -- schedule_delayed_work(&qrtr_ns_work, msecs_to_jiffies(2000)); -+ qrtr_ns_init(); - - return rc; - } -@@ -1107,7 +1100,6 @@ postcore_initcall(qrtr_proto_init); - - static void __exit qrtr_proto_fini(void) - { -- cancel_delayed_work_sync(&qrtr_ns_work); - qrtr_ns_remove(); - sock_unregister(qrtr_family.family); - proto_unregister(&qrtr_proto); ---- a/net/qrtr/qrtr.h -+++ b/net/qrtr/qrtr.h -@@ -29,7 +29,7 @@ void qrtr_endpoint_unregister(struct qrt - - int qrtr_endpoint_post(struct qrtr_endpoint *ep, const void *data, size_t len); - --void qrtr_ns_init(struct work_struct *work); -+void qrtr_ns_init(void); - - void qrtr_ns_remove(void); - diff --git a/target/linux/ipq807x/patches-5.4/0011-v5.7-remoteproc-Use-size_t-type-for-len-in-da_to_va.patch b/target/linux/ipq807x/patches-5.4/0011-v5.7-remoteproc-Use-size_t-type-for-len-in-da_to_va.patch deleted file mode 100644 index 020fc2665..000000000 --- a/target/linux/ipq807x/patches-5.4/0011-v5.7-remoteproc-Use-size_t-type-for-len-in-da_to_va.patch +++ /dev/null @@ -1,222 +0,0 @@ -From 9ce3bf225e5a908756b90b8f7bbc38834427296b Mon Sep 17 00:00:00 2001 -From: Clement Leger -Date: Mon, 2 Mar 2020 10:38:55 +0100 -Subject: [PATCH] remoteproc: Use size_t type for len in da_to_va - -With upcoming changes in elf loader for elf64 support, section size will -be a u64. When used with da_to_va, this will potentially lead to -overflow if using the current "int" type for len argument. Change -da_to_va prototype to use a size_t for len and fix all users of this -function. - -Reviewed-by: Bjorn Andersson -Reviewed-by: Mathieu Poirier -Signed-off-by: Clement Leger -Link: https://lore.kernel.org/r/20200302093902.27849-2-cleger@kalray.eu -Signed-off-by: Bjorn Andersson ---- - drivers/remoteproc/imx_rproc.c | 11 ++++++----- - drivers/remoteproc/keystone_remoteproc.c | 4 ++-- - drivers/remoteproc/qcom_q6v5_adsp.c | 2 +- - drivers/remoteproc/qcom_q6v5_mss.c | 2 +- - drivers/remoteproc/qcom_q6v5_pas.c | 2 +- - drivers/remoteproc/qcom_q6v5_wcss.c | 2 +- - drivers/remoteproc/qcom_wcnss.c | 2 +- - drivers/remoteproc/remoteproc_core.c | 2 +- - drivers/remoteproc/remoteproc_internal.h | 2 +- - drivers/remoteproc/st_slim_rproc.c | 4 ++-- - drivers/remoteproc/wkup_m3_rproc.c | 4 ++-- - include/linux/remoteproc.h | 2 +- - 12 files changed, 20 insertions(+), 19 deletions(-) - ---- a/drivers/remoteproc/imx_rproc.c -+++ b/drivers/remoteproc/imx_rproc.c -@@ -186,7 +186,7 @@ static int imx_rproc_stop(struct rproc * - } - - static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da, -- int len, u64 *sys) -+ size_t len, u64 *sys) - { - const struct imx_rproc_dcfg *dcfg = priv->dcfg; - int i; -@@ -203,19 +203,19 @@ static int imx_rproc_da_to_sys(struct im - } - } - -- dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%x\n", -+ dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n", - da, len); - return -ENOENT; - } - --static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, int len) -+static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct imx_rproc *priv = rproc->priv; - void *va = NULL; - u64 sys; - int i; - -- if (len <= 0) -+ if (len == 0) - return NULL; - - /* -@@ -235,7 +235,8 @@ static void *imx_rproc_da_to_va(struct r - } - } - -- dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%x va = 0x%p\n", da, len, va); -+ dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n", -+ da, len, va); - - return va; - } ---- a/drivers/remoteproc/keystone_remoteproc.c -+++ b/drivers/remoteproc/keystone_remoteproc.c -@@ -246,7 +246,7 @@ static void keystone_rproc_kick(struct r - * can be used either by the remoteproc core for loading (when using kernel - * remoteproc loader), or by any rpmsg bus drivers. - */ --static void *keystone_rproc_da_to_va(struct rproc *rproc, u64 da, int len) -+static void *keystone_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct keystone_rproc *ksproc = rproc->priv; - void __iomem *va = NULL; -@@ -255,7 +255,7 @@ static void *keystone_rproc_da_to_va(str - size_t size; - int i; - -- if (len <= 0) -+ if (len == 0) - return NULL; - - for (i = 0; i < ksproc->num_mems; i++) { ---- a/drivers/remoteproc/qcom_q6v5_adsp.c -+++ b/drivers/remoteproc/qcom_q6v5_adsp.c -@@ -270,7 +270,7 @@ static int adsp_stop(struct rproc *rproc - return ret; - } - --static void *adsp_da_to_va(struct rproc *rproc, u64 da, int len) -+static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; - int offset; ---- a/drivers/remoteproc/qcom_q6v5_mss.c -+++ b/drivers/remoteproc/qcom_q6v5_mss.c -@@ -1186,7 +1186,7 @@ static int q6v5_stop(struct rproc *rproc - return 0; - } - --static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len) -+static void *q6v5_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct q6v5 *qproc = rproc->priv; - int offset; ---- a/drivers/remoteproc/qcom_q6v5_pas.c -+++ b/drivers/remoteproc/qcom_q6v5_pas.c -@@ -159,7 +159,7 @@ static int adsp_stop(struct rproc *rproc - return ret; - } - --static void *adsp_da_to_va(struct rproc *rproc, u64 da, int len) -+static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; - int offset; ---- a/drivers/remoteproc/qcom_q6v5_wcss.c -+++ b/drivers/remoteproc/qcom_q6v5_wcss.c -@@ -406,7 +406,7 @@ static int q6v5_wcss_stop(struct rproc * - return 0; - } - --static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, int len) -+static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct q6v5_wcss *wcss = rproc->priv; - int offset; ---- a/drivers/remoteproc/qcom_wcnss.c -+++ b/drivers/remoteproc/qcom_wcnss.c -@@ -287,7 +287,7 @@ static int wcnss_stop(struct rproc *rpro - return ret; - } - --static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len) -+static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; - int offset; ---- a/drivers/remoteproc/remoteproc_core.c -+++ b/drivers/remoteproc/remoteproc_core.c -@@ -187,7 +187,7 @@ EXPORT_SYMBOL(rproc_va_to_pa); - * here the output of the DMA API for the carveouts, which should be more - * correct. - */ --void *rproc_da_to_va(struct rproc *rproc, u64 da, int len) -+void *rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct rproc_mem_entry *carveout; - void *ptr = NULL; ---- a/drivers/remoteproc/remoteproc_internal.h -+++ b/drivers/remoteproc/remoteproc_internal.h -@@ -50,7 +50,7 @@ void rproc_exit_sysfs(void); - void rproc_free_vring(struct rproc_vring *rvring); - int rproc_alloc_vring(struct rproc_vdev *rvdev, int i); - --void *rproc_da_to_va(struct rproc *rproc, u64 da, int len); -+void *rproc_da_to_va(struct rproc *rproc, u64 da, size_t len); - phys_addr_t rproc_va_to_pa(void *cpu_addr); - int rproc_trigger_recovery(struct rproc *rproc); - ---- a/drivers/remoteproc/st_slim_rproc.c -+++ b/drivers/remoteproc/st_slim_rproc.c -@@ -174,7 +174,7 @@ static int slim_rproc_stop(struct rproc - return 0; - } - --static void *slim_rproc_da_to_va(struct rproc *rproc, u64 da, int len) -+static void *slim_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct st_slim_rproc *slim_rproc = rproc->priv; - void *va = NULL; -@@ -191,7 +191,7 @@ static void *slim_rproc_da_to_va(struct - } - } - -- dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%x va = 0x%pK\n", -+ dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%pK\n", - da, len, va); - - return va; ---- a/drivers/remoteproc/wkup_m3_rproc.c -+++ b/drivers/remoteproc/wkup_m3_rproc.c -@@ -80,14 +80,14 @@ static int wkup_m3_rproc_stop(struct rpr - return 0; - } - --static void *wkup_m3_rproc_da_to_va(struct rproc *rproc, u64 da, int len) -+static void *wkup_m3_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) - { - struct wkup_m3_rproc *wkupm3 = rproc->priv; - void *va = NULL; - int i; - u32 offset; - -- if (len <= 0) -+ if (len == 0) - return NULL; - - for (i = 0; i < WKUPM3_MEM_MAX; i++) { ---- a/include/linux/remoteproc.h -+++ b/include/linux/remoteproc.h -@@ -374,7 +374,7 @@ struct rproc_ops { - int (*start)(struct rproc *rproc); - int (*stop)(struct rproc *rproc); - void (*kick)(struct rproc *rproc, int vqid); -- void * (*da_to_va)(struct rproc *rproc, u64 da, int len); -+ void * (*da_to_va)(struct rproc *rproc, u64 da, size_t len); - int (*parse_fw)(struct rproc *rproc, const struct firmware *fw); - int (*handle_rsc)(struct rproc *rproc, u32 rsc_type, void *rsc, - int offset, int avail); diff --git a/target/linux/ipq807x/patches-5.4/0012-v5.8-remoteproc-wcss-add-support-for-rpmsg-communication.patch b/target/linux/ipq807x/patches-5.4/0012-v5.8-remoteproc-wcss-add-support-for-rpmsg-communication.patch deleted file mode 100644 index e41fad6cd..000000000 --- a/target/linux/ipq807x/patches-5.4/0012-v5.8-remoteproc-wcss-add-support-for-rpmsg-communication.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 8a226e2c71bb3763e27a063d36eac5fa4ea53c3f Mon Sep 17 00:00:00 2001 -From: Sivaprakash Murugesan -Date: Fri, 1 May 2020 21:58:12 +0530 -Subject: [PATCH] remoteproc: wcss: add support for rpmsg communication - -add glink and ssr subdevices for wcss rproc to enable rpmsg -communication. - -Signed-off-by: Sivaprakash Murugesan -Link: https://lore.kernel.org/r/1588350492-4663-1-git-send-email-sivaprak@codeaurora.org -Signed-off-by: Bjorn Andersson ---- - drivers/remoteproc/qcom_q6v5_wcss.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/remoteproc/qcom_q6v5_wcss.c -+++ b/drivers/remoteproc/qcom_q6v5_wcss.c -@@ -91,6 +91,9 @@ struct q6v5_wcss { - phys_addr_t mem_reloc; - void *mem_region; - size_t mem_size; -+ -+ struct qcom_rproc_glink glink_subdev; -+ struct qcom_rproc_ssr ssr_subdev; - }; - - static int q6v5_wcss_reset(struct q6v5_wcss *wcss) -@@ -557,6 +560,9 @@ static int q6v5_wcss_probe(struct platfo - if (ret) - goto free_rproc; - -+ qcom_add_glink_subdev(rproc, &wcss->glink_subdev); -+ qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); -+ - ret = rproc_add(rproc); - if (ret) - goto free_rproc; diff --git a/target/linux/ipq807x/patches-5.4/0013-v5.9-remoteproc-qcom-Introduce-helper-to-store-pil-info-i.patch b/target/linux/ipq807x/patches-5.4/0013-v5.9-remoteproc-qcom-Introduce-helper-to-store-pil-info-i.patch deleted file mode 100644 index 7c63388ed..000000000 --- a/target/linux/ipq807x/patches-5.4/0013-v5.9-remoteproc-qcom-Introduce-helper-to-store-pil-info-i.patch +++ /dev/null @@ -1,190 +0,0 @@ -From 549b67da660d634e3a4a50a325bd1f5609ddb84b Mon Sep 17 00:00:00 2001 -From: Bjorn Andersson -Date: Mon, 22 Jun 2020 12:19:39 -0700 -Subject: [PATCH] remoteproc: qcom: Introduce helper to store pil info in IMEM - -A region in IMEM is used to communicate load addresses of remoteproc to -post mortem debug tools. Implement a helper function that can be used to -store this information in order to enable these tools to process -collected ramdumps. - -Reviewed-by: Mathieu Poirier -Reviewed-by: Vinod Koul -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20200622191942.255460-3-bjorn.andersson@linaro.org -Signed-off-by: Bjorn Andersson ---- - drivers/remoteproc/Kconfig | 3 + - drivers/remoteproc/Makefile | 1 + - drivers/remoteproc/qcom_pil_info.c | 129 +++++++++++++++++++++++++++++ - drivers/remoteproc/qcom_pil_info.h | 9 ++ - 4 files changed, 142 insertions(+) - create mode 100644 drivers/remoteproc/qcom_pil_info.c - create mode 100644 drivers/remoteproc/qcom_pil_info.h - ---- a/drivers/remoteproc/Kconfig -+++ b/drivers/remoteproc/Kconfig -@@ -85,6 +85,9 @@ config KEYSTONE_REMOTEPROC - It's safe to say N here if you're not interested in the Keystone - DSPs or just want to use a bare minimum kernel. - -+config QCOM_PIL_INFO -+ tristate -+ - config QCOM_RPROC_COMMON - tristate - ---- a/drivers/remoteproc/Makefile -+++ b/drivers/remoteproc/Makefile -@@ -14,6 +14,7 @@ obj-$(CONFIG_OMAP_REMOTEPROC) += omap_r - obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o - obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o - obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o -+obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o - obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o - obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o - obj-$(CONFIG_QCOM_Q6V5_ADSP) += qcom_q6v5_adsp.o ---- /dev/null -+++ b/drivers/remoteproc/qcom_pil_info.c -@@ -0,0 +1,129 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2019-2020 Linaro Ltd. -+ */ -+#include -+#include -+#include -+#include -+#include "qcom_pil_info.h" -+ -+/* -+ * The PIL relocation information region is used to communicate memory regions -+ * occupied by co-processor firmware for post mortem crash analysis. -+ * -+ * It consists of an array of entries with an 8 byte textual identifier of the -+ * region followed by a 64 bit base address and 32 bit size, both little -+ * endian. -+ */ -+#define PIL_RELOC_NAME_LEN 8 -+#define PIL_RELOC_ENTRY_SIZE (PIL_RELOC_NAME_LEN + sizeof(__le64) + sizeof(__le32)) -+ -+struct pil_reloc { -+ void __iomem *base; -+ size_t num_entries; -+}; -+ -+static struct pil_reloc _reloc __read_mostly; -+static DEFINE_MUTEX(pil_reloc_lock); -+ -+static int qcom_pil_info_init(void) -+{ -+ struct device_node *np; -+ struct resource imem; -+ void __iomem *base; -+ int ret; -+ -+ /* Already initialized? */ -+ if (_reloc.base) -+ return 0; -+ -+ np = of_find_compatible_node(NULL, NULL, "qcom,pil-reloc-info"); -+ if (!np) -+ return -ENOENT; -+ -+ ret = of_address_to_resource(np, 0, &imem); -+ of_node_put(np); -+ if (ret < 0) -+ return ret; -+ -+ base = ioremap(imem.start, resource_size(&imem)); -+ if (!base) { -+ pr_err("failed to map PIL relocation info region\n"); -+ return -ENOMEM; -+ } -+ -+ memset_io(base, 0, resource_size(&imem)); -+ -+ _reloc.base = base; -+ _reloc.num_entries = resource_size(&imem) / PIL_RELOC_ENTRY_SIZE; -+ -+ return 0; -+} -+ -+/** -+ * qcom_pil_info_store() - store PIL information of image in IMEM -+ * @image: name of the image -+ * @base: base address of the loaded image -+ * @size: size of the loaded image -+ * -+ * Return: 0 on success, negative errno on failure -+ */ -+int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size) -+{ -+ char buf[PIL_RELOC_NAME_LEN]; -+ void __iomem *entry; -+ int ret; -+ int i; -+ -+ mutex_lock(&pil_reloc_lock); -+ ret = qcom_pil_info_init(); -+ if (ret < 0) { -+ mutex_unlock(&pil_reloc_lock); -+ return ret; -+ } -+ -+ for (i = 0; i < _reloc.num_entries; i++) { -+ entry = _reloc.base + i * PIL_RELOC_ENTRY_SIZE; -+ -+ memcpy_fromio(buf, entry, PIL_RELOC_NAME_LEN); -+ -+ /* -+ * An empty record means we didn't find it, given that the -+ * records are packed. -+ */ -+ if (!buf[0]) -+ goto found_unused; -+ -+ if (!strncmp(buf, image, PIL_RELOC_NAME_LEN)) -+ goto found_existing; -+ } -+ -+ pr_warn("insufficient PIL info slots\n"); -+ mutex_unlock(&pil_reloc_lock); -+ return -ENOMEM; -+ -+found_unused: -+ memcpy_toio(entry, image, PIL_RELOC_NAME_LEN); -+found_existing: -+ /* Use two writel() as base is only aligned to 4 bytes on odd entries */ -+ writel(base, entry + PIL_RELOC_NAME_LEN); -+ writel(base >> 32, entry + PIL_RELOC_NAME_LEN + 4); -+ writel(size, entry + PIL_RELOC_NAME_LEN + sizeof(__le64)); -+ mutex_unlock(&pil_reloc_lock); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(qcom_pil_info_store); -+ -+static void __exit pil_reloc_exit(void) -+{ -+ mutex_lock(&pil_reloc_lock); -+ iounmap(_reloc.base); -+ _reloc.base = NULL; -+ mutex_unlock(&pil_reloc_lock); -+} -+module_exit(pil_reloc_exit); -+ -+MODULE_DESCRIPTION("Qualcomm PIL relocation info"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/drivers/remoteproc/qcom_pil_info.h -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+#ifndef __QCOM_PIL_INFO_H__ -+#define __QCOM_PIL_INFO_H__ -+ -+#include -+ -+int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size); -+ -+#endif diff --git a/target/linux/ipq807x/patches-5.4/0014-v5.9-remoteproc-qcom-pil-info-Fix-shift-overflow.patch b/target/linux/ipq807x/patches-5.4/0014-v5.9-remoteproc-qcom-pil-info-Fix-shift-overflow.patch deleted file mode 100644 index 1f7d747e5..000000000 --- a/target/linux/ipq807x/patches-5.4/0014-v5.9-remoteproc-qcom-pil-info-Fix-shift-overflow.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 90ec257c380ebdcebf332b698f3e809cd1157202 Mon Sep 17 00:00:00 2001 -From: Bjorn Andersson -Date: Wed, 15 Jul 2020 22:48:17 -0700 -Subject: [PATCH] remoteproc: qcom: pil-info: Fix shift overflow - -On platforms with 32-bit phys_addr_t the shift to get the upper word of -the base address of the memory region is invalid. Cast the base to 64 -bit to resolv this. - -Fixes: 549b67da660d ("remoteproc: qcom: Introduce helper to store pil info in IMEM") -Tested-by: Nathan Chancellor # build -Reported-by: Lee Jones -Reported-by: Nathan Chancellor -Link: https://lore.kernel.org/r/20200716054817.157608-1-bjorn.andersson@linaro.org -Signed-off-by: Bjorn Andersson ---- - drivers/remoteproc/qcom_pil_info.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/remoteproc/qcom_pil_info.c -+++ b/drivers/remoteproc/qcom_pil_info.c -@@ -108,7 +108,7 @@ found_unused: - found_existing: - /* Use two writel() as base is only aligned to 4 bytes on odd entries */ - writel(base, entry + PIL_RELOC_NAME_LEN); -- writel(base >> 32, entry + PIL_RELOC_NAME_LEN + 4); -+ writel((u64)base >> 32, entry + PIL_RELOC_NAME_LEN + 4); - writel(size, entry + PIL_RELOC_NAME_LEN + sizeof(__le64)); - mutex_unlock(&pil_reloc_lock); - diff --git a/target/linux/ipq807x/patches-5.4/0015-v5.9-remoteproc-qcom-Update-PIL-relocation-info-on-load.patch b/target/linux/ipq807x/patches-5.4/0015-v5.9-remoteproc-qcom-Update-PIL-relocation-info-on-load.patch deleted file mode 100644 index 2b60998d6..000000000 --- a/target/linux/ipq807x/patches-5.4/0015-v5.9-remoteproc-qcom-Update-PIL-relocation-info-on-load.patch +++ /dev/null @@ -1,102 +0,0 @@ -From d4c78d2167913b3f7af0d2189fd3d76f6614a1bf Mon Sep 17 00:00:00 2001 -From: Bjorn Andersson -Date: Mon, 22 Jun 2020 12:19:40 -0700 -Subject: [PATCH] remoteproc: qcom: Update PIL relocation info on load - -Update the PIL relocation information in IMEM with information about -where the firmware for various remoteprocs are loaded. - -Reviewed-by: Vinod Koul -Reviewed-by: Stephen Boyd -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20200622191942.255460-4-bjorn.andersson@linaro.org -Signed-off-by: Bjorn Andersson ---- - drivers/remoteproc/Kconfig | 5 +++++ - drivers/remoteproc/qcom_q6v5_adsp.c | 16 +++++++++++++--- - drivers/remoteproc/qcom_q6v5_mss.c | 3 +++ - drivers/remoteproc/qcom_q6v5_pas.c | 15 ++++++++++++--- - drivers/remoteproc/qcom_q6v5_wcss.c | 14 +++++++++++--- - drivers/remoteproc/qcom_wcnss.c | 14 +++++++++++--- - 6 files changed, 55 insertions(+), 12 deletions(-) - ---- a/drivers/remoteproc/Kconfig -+++ b/drivers/remoteproc/Kconfig -@@ -153,6 +153,7 @@ config QCOM_Q6V5_WCSS - depends on QCOM_SYSMON || QCOM_SYSMON=n - select MFD_SYSCON - select QCOM_MDT_LOADER -+ select QCOM_PIL_INFO - select QCOM_Q6V5_COMMON - select QCOM_RPROC_COMMON - select QCOM_SCM -@@ -183,6 +184,7 @@ config QCOM_WCNSS_PIL - depends on QCOM_SMEM - depends on QCOM_SYSMON || QCOM_SYSMON=n - select QCOM_MDT_LOADER -+ select QCOM_PIL_INFO - select QCOM_RPROC_COMMON - select QCOM_SCM - help ---- a/drivers/remoteproc/qcom_q6v5_wcss.c -+++ b/drivers/remoteproc/qcom_q6v5_wcss.c -@@ -14,6 +14,7 @@ - #include - #include - #include "qcom_common.h" -+#include "qcom_pil_info.h" - #include "qcom_q6v5.h" - - #define WCSS_CRASH_REASON 421 -@@ -424,10 +425,17 @@ static void *q6v5_wcss_da_to_va(struct r - static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) - { - struct q6v5_wcss *wcss = rproc->priv; -+ int ret; -+ -+ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, -+ 0, wcss->mem_region, wcss->mem_phys, -+ wcss->mem_size, &wcss->mem_reloc); -+ if (ret) -+ return ret; -+ -+ qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size); - -- return qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, -- 0, wcss->mem_region, wcss->mem_phys, -- wcss->mem_size, &wcss->mem_reloc); -+ return ret; - } - - static const struct rproc_ops q6v5_wcss_ops = { ---- a/drivers/remoteproc/qcom_wcnss.c -+++ b/drivers/remoteproc/qcom_wcnss.c -@@ -27,6 +27,7 @@ - - #include "qcom_common.h" - #include "remoteproc_internal.h" -+#include "qcom_pil_info.h" - #include "qcom_wcnss.h" - - #define WCNSS_CRASH_REASON_SMEM 422 -@@ -145,10 +146,17 @@ void qcom_wcnss_assign_iris(struct qcom_ - static int wcnss_load(struct rproc *rproc, const struct firmware *fw) - { - struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; -+ int ret; - -- return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID, -- wcnss->mem_region, wcnss->mem_phys, -- wcnss->mem_size, &wcnss->mem_reloc); -+ ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID, -+ wcnss->mem_region, wcnss->mem_phys, -+ wcnss->mem_size, &wcnss->mem_reloc); -+ if (ret) -+ return ret; -+ -+ qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size); -+ -+ return 0; - } - - static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss) diff --git a/target/linux/ipq807x/patches-5.4/0016-v5.7-drivers-provide-devm_platform_get_and_ioremap_resour.patch b/target/linux/ipq807x/patches-5.4/0016-v5.7-drivers-provide-devm_platform_get_and_ioremap_resour.patch deleted file mode 100644 index 72f4f0111..000000000 --- a/target/linux/ipq807x/patches-5.4/0016-v5.7-drivers-provide-devm_platform_get_and_ioremap_resour.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 890cc39a879906b63912482dfc41944579df2dc6 Mon Sep 17 00:00:00 2001 -From: Dejin Zheng -Date: Tue, 24 Mar 2020 00:06:08 +0800 -Subject: [PATCH] drivers: provide devm_platform_get_and_ioremap_resource() - -Since commit "drivers: provide devm_platform_ioremap_resource()", -it was wrap platform_get_resource() and devm_ioremap_resource() as -single helper devm_platform_ioremap_resource(). but now, many drivers -still used platform_get_resource() and devm_ioremap_resource() -together in the kernel tree. The reason can not be replaced is they -still need use the resource variables obtained by platform_get_resource(). -so provide this helper. - -Suggested-by: Geert Uytterhoeven -Suggested-by: Sergei Shtylyov -Reviewed-by: Geert Uytterhoeven -Signed-off-by: Dejin Zheng -Link: https://lore.kernel.org/r/20200323160612.17277-2-zhengdejin5@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/base/platform.c | 22 ++++++++++++++++++++++ - include/linux/platform_device.h | 3 +++ - 2 files changed, 25 insertions(+) - ---- a/drivers/base/platform.c -+++ b/drivers/base/platform.c -@@ -61,6 +61,29 @@ struct resource *platform_get_resource(s - } - EXPORT_SYMBOL_GPL(platform_get_resource); - -+#ifdef CONFIG_HAS_IOMEM -+/** -+ * devm_platform_get_and_ioremap_resource - call devm_ioremap_resource() for a -+ * platform device and get resource -+ * -+ * @pdev: platform device to use both for memory resource lookup as well as -+ * resource management -+ * @index: resource index -+ * @res: optional output parameter to store a pointer to the obtained resource. -+ */ -+void __iomem * -+devm_platform_get_and_ioremap_resource(struct platform_device *pdev, -+ unsigned int index, struct resource **res) -+{ -+ struct resource *r; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, index); -+ if (res) -+ *res = r; -+ return devm_ioremap_resource(&pdev->dev, r); -+} -+EXPORT_SYMBOL_GPL(devm_platform_get_and_ioremap_resource); -+ - /** - * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform - * device -@@ -69,7 +92,6 @@ EXPORT_SYMBOL_GPL(platform_get_resource) - * resource management - * @index: resource index - */ --#ifdef CONFIG_HAS_IOMEM - void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, - unsigned int index) - { ---- a/include/linux/platform_device.h -+++ b/include/linux/platform_device.h -@@ -55,6 +55,9 @@ extern struct device * - platform_find_device_by_driver(struct device *start, - const struct device_driver *drv); - extern void __iomem * -+devm_platform_get_and_ioremap_resource(struct platform_device *pdev, -+ unsigned int index, struct resource **res); -+extern void __iomem * - devm_platform_ioremap_resource(struct platform_device *pdev, - unsigned int index); - extern int platform_get_irq(struct platform_device *, unsigned int); diff --git a/target/linux/ipq807x/patches-5.4/100-arm64-dts-ipq8074-add-watchdog-support.patch b/target/linux/ipq807x/patches-5.4/100-arm64-dts-ipq8074-add-watchdog-support.patch deleted file mode 100644 index 188451623..000000000 --- a/target/linux/ipq807x/patches-5.4/100-arm64-dts-ipq8074-add-watchdog-support.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 50b0dbf203d321257a6422ec51052dc2ed775bfc Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 Aug 2020 15:51:18 +0200 -Subject: [PATCH] arm64: dts: ipq8074: add watchdog support - -IPQ8074 has a secure version of KPSS watchdog that is already supported. -So lets add the node to enable it. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -323,6 +323,14 @@ - reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; - }; - -+ watchdog@b017000 { -+ compatible = "qcom,kpss-wdt"; -+ interrupts = ; -+ reg = <0x0b017000 0x40>; -+ clocks = <&sleep_clk>; -+ timeout-sec = <10>; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupts = , diff --git a/target/linux/ipq807x/patches-5.4/101-arm64-dts-ipq8074-add-PRNG-node.patch b/target/linux/ipq807x/patches-5.4/101-arm64-dts-ipq8074-add-PRNG-node.patch deleted file mode 100644 index c2e8393f9..000000000 --- a/target/linux/ipq807x/patches-5.4/101-arm64-dts-ipq8074-add-PRNG-node.patch +++ /dev/null @@ -1,29 +0,0 @@ -From d623ff8bfd51896d553866f783985d32040bf584 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 Aug 2020 20:19:29 +0200 -Subject: [PATCH] arm64: dts: ipq8074: add PRNG node - -PRNG found in IPQ8074 is already supported so lets add the node -to enable it. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -82,6 +82,13 @@ - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - -+ prng: qrng@e1000 { -+ compatible = "qcom,prng-ee"; -+ reg = <0xe3000 0x1000>; -+ clocks = <&gcc GCC_PRNG_AHB_CLK>; -+ clock-names = "core"; -+ }; -+ - pcie_phy0: phy@86000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x00086000 0x1000>; diff --git a/target/linux/ipq807x/patches-5.4/102-02-regulator-qcom_spmi-Add-support-for-PMD9655-PMIC.patch b/target/linux/ipq807x/patches-5.4/102-02-regulator-qcom_spmi-Add-support-for-PMD9655-PMIC.patch deleted file mode 100644 index e4e2337de..000000000 --- a/target/linux/ipq807x/patches-5.4/102-02-regulator-qcom_spmi-Add-support-for-PMD9655-PMIC.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 9547df62c4fe30ceeb5b0e99c3283c810d2b89e0 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 Aug 2020 22:53:15 +0200 -Subject: [PATCH] regulator: qcom_spmi: Add support for PMD9655 PMIC - -Add support for PMD9655 for in SPMI regulator. -All 4 cores are supplied by a single common buck which -is the S3. -S4 buck powers the UBI cores and this support is required to provide access to NSS -voltage scaling. - -Signed-off-by: Robert Marko ---- - drivers/regulator/qcom_spmi-regulator.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/regulator/qcom_spmi-regulator.c -+++ b/drivers/regulator/qcom_spmi-regulator.c -@@ -470,6 +470,7 @@ static struct spmi_voltage_range ln_ldo_ - static struct spmi_voltage_range smps_ranges[] = { - SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), - SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), -+ SPMI_VOLTAGE_RANGE(2, 670000, 670000, 990000, 990000, 8000), - }; - - static struct spmi_voltage_range ftsmps_ranges[] = { -@@ -1940,6 +1941,12 @@ static const struct spmi_regulator_data - { } - }; - -+static const struct spmi_regulator_data pmd9655_regulators[] = { -+ { "s3", 0x1a00, "vdd_s3", }, -+ { "s4", 0x1d00, "vdd_s4", }, -+ { } -+}; -+ - static const struct of_device_id qcom_spmi_regulator_match[] = { - { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, - { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, -@@ -1948,6 +1955,7 @@ static const struct of_device_id qcom_sp - { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, - { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, - { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, -+ { .compatible = "qcom,pmd9655-regulators", .data = &pmd9655_regulators }, - { } - }; - MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); diff --git a/target/linux/ipq807x/patches-5.4/102-04-regulator-qcom_spmi-Add-support-for-LD011-in-PMD9655.patch b/target/linux/ipq807x/patches-5.4/102-04-regulator-qcom_spmi-Add-support-for-LD011-in-PMD9655.patch deleted file mode 100644 index 08ef88c32..000000000 --- a/target/linux/ipq807x/patches-5.4/102-04-regulator-qcom_spmi-Add-support-for-LD011-in-PMD9655.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 44de637a650e23153abf663b9d896287a9619e18 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 21 Aug 2020 16:56:49 +0200 -Subject: [PATCH] regulator: qcom_spmi: Add support for LD011 in PMD9655 - -LDO11 in PMD9655 is used for SD card support. - -Signed-off-by: Robert Marko ---- - drivers/regulator/qcom_spmi-regulator.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/regulator/qcom_spmi-regulator.c -+++ b/drivers/regulator/qcom_spmi-regulator.c -@@ -152,6 +152,7 @@ enum spmi_regulator_subtype { - SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, - SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, - SPMI_REGULATOR_SUBTYPE_VMPWM_CTL = 0x0a, -+ SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, - }; - - enum spmi_common_regulator_registers { -@@ -479,7 +480,8 @@ static struct spmi_voltage_range smps_ra - }; - - static struct spmi_voltage_range smps_vmpwm_ranges[] = { -- SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), -+ SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), -+ SPMI_VOLTAGE_RANGE(1, 1104000, 1104000, 3300000, 3300000, 8000), - }; - - static struct spmi_voltage_range ftsmps_ranges[] = { -@@ -1526,6 +1528,7 @@ static const struct spmi_regulator_mappi - SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000), - SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000), - SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000), -+ SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, smps_vmpwm, 0), - SPMI_VREG_VS(LV100, 0, INF), - SPMI_VREG_VS(LV300, 0, INF), - SPMI_VREG_VS(MV300, 0, INF), -@@ -2026,6 +2029,7 @@ static const struct spmi_regulator_data - static const struct spmi_regulator_data pmd9655_regulators[] = { - { "s3", 0x1a00, "vdd_s3", }, - { "s4", 0x1d00, "vdd_s4", }, -+ { "ldo11", 0x4a00, "vdd_ldo11", }, - { } - }; - diff --git a/target/linux/ipq807x/patches-5.4/103-01-clk-qcom-Add-IPQ8074-APSS-driver.patch b/target/linux/ipq807x/patches-5.4/103-01-clk-qcom-Add-IPQ8074-APSS-driver.patch deleted file mode 100644 index f0ed363f2..000000000 --- a/target/linux/ipq807x/patches-5.4/103-01-clk-qcom-Add-IPQ8074-APSS-driver.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 0da5c2a83cd8a920889297e83639b92de4eb497c Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 22 Aug 2020 15:40:05 +0200 -Subject: [PATCH] clk: qcom: Add IPQ8074 APSS driver - -APSS clks are needed for CPU scaling. - -Signed-off-by: Robert Marko ---- - drivers/clk/qcom/Kconfig | 10 +++ - drivers/clk/qcom/Makefile | 1 + - drivers/clk/qcom/apss-ipq8074.c | 107 ++++++++++++++++++++++++++++++++ - 3 files changed, 118 insertions(+) - create mode 100644 drivers/clk/qcom/apss-ipq8074.c - ---- a/drivers/clk/qcom/Kconfig -+++ b/drivers/clk/qcom/Kconfig -@@ -88,6 +88,16 @@ config APQ_MMCC_8084 - Say Y if you want to support multimedia devices such as display, - graphics, video encode/decode, camera, etc. - -+config IPQ_APSS_8074 -+ tristate "IPQ8074 APSS Clock Controller" -+ depends on QCOM_APCS_IPC || COMPILE_TEST -+ help -+ Support for APSS clock controller on IPQ8074 platforms. The -+ APSS clock controller manages the Mux and enable block that feeds the -+ CPUs. -+ Say Y if you want to support CPU frequency scaling on -+ IPQ8074 based devices. -+ - config IPQ_GCC_4019 - tristate "IPQ4019 Global Clock Controller" - help ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -19,6 +19,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o - # Keep alphabetically sorted by config - obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o - obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o -+obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o - obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o - obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o - obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o ---- /dev/null -+++ b/drivers/clk/qcom/apss-ipq8074.c -@@ -0,0 +1,107 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2018, The Linux Foundation. All rights reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "common.h" -+#include "clk-regmap.h" -+#include "clk-branch.h" -+#include "clk-alpha-pll.h" -+#include "clk-regmap-mux.h" -+ -+enum { -+ P_XO, -+ P_APSS_PLL_EARLY, -+}; -+ -+static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { -+ { .fw_name = "xo" }, -+ { .fw_name = "pll" }, -+}; -+ -+static const struct parent_map parents_apcs_alias0_clk_src_map[] = { -+ { P_XO, 0 }, -+ { P_APSS_PLL_EARLY, 5 }, -+}; -+ -+static struct clk_regmap_mux apcs_alias0_clk_src = { -+ .reg = 0x0050, -+ .width = 3, -+ .shift = 7, -+ .parent_map = parents_apcs_alias0_clk_src_map, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .name = "apcs_alias0_clk_src", -+ .parent_data = parents_apcs_alias0_clk_src, -+ .num_parents = 2, -+ .ops = &clk_regmap_mux_closest_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+}; -+ -+static struct clk_branch apcs_alias0_core_clk = { -+ .halt_reg = 0x0058, -+ .halt_bit = 31, -+ .clkr = { -+ .enable_reg = 0x0058, -+ .enable_mask = BIT(0), -+ .hw.init = &(struct clk_init_data){ -+ .name = "apcs_alias0_core_clk", -+ .parent_hws = (const struct clk_hw *[]){ -+ &apcs_alias0_clk_src.clkr.hw }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT, -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ -+static const struct regmap_config apss_ipq8074_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = 0x1000, -+ .fast_io = true, -+}; -+ -+static struct clk_regmap *apss_ipq8074_clks[] = { -+ [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr, -+ [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, -+}; -+ -+static const struct qcom_cc_desc apss_ipq8074_desc = { -+ .config = &apss_ipq8074_regmap_config, -+ .clks = apss_ipq8074_clks, -+ .num_clks = ARRAY_SIZE(apss_ipq8074_clks), -+}; -+ -+static int apss_ipq8074_probe(struct platform_device *pdev) -+{ -+ struct regmap *regmap; -+ -+ regmap = dev_get_regmap(pdev->dev.parent, NULL); -+ if (!regmap) -+ return -ENODEV; -+ -+ return qcom_cc_really_probe(pdev, &apss_ipq8074_desc, regmap); -+} -+ -+static struct platform_driver apss_ipq8074_driver = { -+ .probe = apss_ipq8074_probe, -+ .driver = { -+ .name = "qcom,apss-ipq8074-clk", -+ }, -+}; -+ -+module_platform_driver(apss_ipq8074_driver); -+ -+MODULE_DESCRIPTION("QCOM APSS IPQ 8074 CLK Driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq807x/patches-5.4/104-arm64-dts-ipq8074-Add-SMEM-nodes.patch b/target/linux/ipq807x/patches-5.4/104-arm64-dts-ipq8074-Add-SMEM-nodes.patch deleted file mode 100644 index edd0fd01f..000000000 --- a/target/linux/ipq807x/patches-5.4/104-arm64-dts-ipq8074-Add-SMEM-nodes.patch +++ /dev/null @@ -1,65 +0,0 @@ -From c335321e14848fb02b05fa6b8896f3ff1cd22051 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 22 Aug 2020 16:26:34 +0200 -Subject: [PATCH 1/2] arm64: dts: ipq8074: Add SMEM nodes - -SMEM is later needed for all kinds of HW support, its supported -by existing drivers. -So lets add the required nodes. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -67,6 +67,12 @@ - }; - }; - -+ tcsr_mutex: hwlock { -+ compatible = "qcom,tcsr-mutex"; -+ syscon = <&tcsr_mutex_regs 0 0x80>; -+ #hwlock-cells = <1>; -+ }; -+ - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; -@@ -86,6 +92,23 @@ - regulator-boot-on; - }; - -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ smem_region: smem@4ab00000 { -+ reg = <0x0 0x4ab00000 0x0 0x100000>; -+ no-map; -+ }; -+ }; -+ -+ smem { -+ compatible = "qcom,smem"; -+ memory-region = <&smem_region>; -+ hwlocks = <&tcsr_mutex 0>; -+ }; -+ - soc: soc { - #address-cells = <0x1>; - #size-cells = <0x1>; -@@ -186,6 +209,11 @@ - #reset-cells = <0x1>; - }; - -+ tcsr_mutex_regs: syscon@1905000 { -+ compatible = "syscon"; -+ reg = <0x1905000 0x8000>; -+ }; -+ - sdhc_1: sdhci@7824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x500>, <0x7824000 0x800>; diff --git a/target/linux/ipq807x/patches-5.4/105-arm64-dts-ipq8074-Add-SCM-node.patch b/target/linux/ipq807x/patches-5.4/105-arm64-dts-ipq8074-Add-SCM-node.patch deleted file mode 100644 index 702255cf0..000000000 --- a/target/linux/ipq807x/patches-5.4/105-arm64-dts-ipq8074-Add-SCM-node.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 2d9b6b37afc0da0982715c65a50f74983967154e Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 22 Aug 2020 16:29:25 +0200 -Subject: [PATCH 2/2] arm64: dts: ipq8074: Add SCM node - -SCM is used to communicate to all kinds of FW running on the board, -its supported by existing drivers. -So lets add the node to enable it. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -67,6 +67,12 @@ - }; - }; - -+ firmware { -+ scm { -+ compatible = "qcom,scm"; -+ }; -+ }; -+ - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; diff --git a/target/linux/ipq807x/patches-5.4/106-03-remoteproc-qcom-wcss-explicitly-request-exclusive-reset-control.patch b/target/linux/ipq807x/patches-5.4/106-03-remoteproc-qcom-wcss-explicitly-request-exclusive-reset-control.patch deleted file mode 100644 index e8859f130..000000000 --- a/target/linux/ipq807x/patches-5.4/106-03-remoteproc-qcom-wcss-explicitly-request-exclusive-reset-control.patch +++ /dev/null @@ -1,91 +0,0 @@ -From patchwork Thu Jul 30 12:14:04 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692911 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22C5E13B1 - for ; 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Thu, 30 Jul 2020 17:44:05 +0530 (IST) -From: Gokul Sriram Palanisamy -To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, - sboyd@kernel.org, linux-clk@vger.kernel.org, - linux-arm-msm@vger.kernel.org -Cc: agross@kernel.org, linux-soc@vger.kernel.org, - devicetree@vger.kernel.org, govinds@codeaurora.org, - sricharan@codeaurora.org, gokulsri@codeaurora.org -Subject: [PATCH v8 4/4] remoteproc: qcom: wcss: explicitly request exclusive - reset control -Date: Thu, 30 Jul 2020 17:44:04 +0530 -Message-Id: <1596111244-28411-5-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> -References: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org - -From: Govind Singh - -Use request exclusive reset control for wcss reset controls. - -Signed-off-by: Govind Singh -Signed-off-by: Gokul Sriram Palanisamy ---- - drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/remoteproc/qcom_q6v5_wcss.c -+++ b/drivers/remoteproc/qcom_q6v5_wcss.c -@@ -788,21 +788,21 @@ static int q6v5_wcss_init_reset(struct q - struct device *dev = wcss->dev; - - if (desc->aon_reset_required) { -- wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset"); -+ wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset"); - if (IS_ERR(wcss->wcss_aon_reset)) { - dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n"); - return PTR_ERR(wcss->wcss_aon_reset); - } - } - -- wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset"); -+ wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset"); - if (IS_ERR(wcss->wcss_reset)) { - dev_err(wcss->dev, "unable to acquire wcss_reset\n"); - return PTR_ERR(wcss->wcss_reset); - } - - if (desc->wcss_q6_reset_required) { -- wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset"); -+ wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset"); - if (IS_ERR(wcss->wcss_q6_reset)) { - dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); - return PTR_ERR(wcss->wcss_q6_reset); diff --git a/target/linux/ipq807x/patches-5.4/106-07-remoteproc-qcom-Add-ssr-subdevice-identifier.patch b/target/linux/ipq807x/patches-5.4/106-07-remoteproc-qcom-Add-ssr-subdevice-identifier.patch deleted file mode 100644 index c47520540..000000000 --- a/target/linux/ipq807x/patches-5.4/106-07-remoteproc-qcom-Add-ssr-subdevice-identifier.patch +++ /dev/null @@ -1,73 +0,0 @@ -From patchwork Thu Jul 30 12:26:38 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692943 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1B881744 - for ; - Thu, 30 Jul 2020 12:28:46 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by mail.kernel.org (Postfix) with ESMTP id 89AB422B3F - for ; - Thu, 30 Jul 2020 12:28:46 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1728303AbgG3M2q (ORCPT - ); - Thu, 30 Jul 2020 08:28:46 -0400 -Received: from alexa-out.qualcomm.com ([129.46.98.28]:43483 "EHLO - alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1728248AbgG3M2o (ORCPT - ); - Thu, 30 Jul 2020 08:28:44 -0400 -Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) - by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:44 -0700 -Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) - by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; - 30 Jul 2020 05:28:42 -0700 -Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) - by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:14 +0530 -Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) - id 2E02C218A2; Thu, 30 Jul 2020 17:58:12 +0530 (IST) -From: Gokul Sriram Palanisamy -To: gokulsri@codeaurora.org, agross@kernel.org, - bjorn.andersson@linaro.org, david.brown@linaro.org, - devicetree@vger.kernel.org, jassisinghbrar@gmail.com, - linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, - mark.rutland@arm.com, mturquette@baylibre.com, - nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, - sboyd@kernel.org, sricharan@codeaurora.org -Subject: [PATCH v7 4/9] remoteproc: qcom: Add ssr subdevice identifier -Date: Thu, 30 Jul 2020 17:56:38 +0530 -Message-Id: <1596112003-31663-5-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org - -Add name for ssr subdevice on IPQ8074 SoC. - -Signed-off-by: Gokul Sriram Palanisamy -Signed-off-by: Sricharan R -Signed-off-by: Nikhil Prakash V ---- - drivers/remoteproc/qcom_q6v5_wcss.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/remoteproc/qcom_q6v5_wcss.c -+++ b/drivers/remoteproc/qcom_q6v5_wcss.c -@@ -1172,6 +1172,7 @@ static const struct wcss_data wcss_ipq80 - .crash_reason_smem = WCSS_CRASH_REASON, - .aon_reset_required = true, - .wcss_q6_reset_required = true, -+ .ssr_name = "q6wcss", - .ops = &q6v5_wcss_ipq8074_ops, - .requires_force_stop = true, - .need_mem_protection = true, diff --git a/target/linux/ipq807x/patches-5.4/106-08-remoteproc-qcom-Update-regmap-offsets-for-halt-register.patch b/target/linux/ipq807x/patches-5.4/106-08-remoteproc-qcom-Update-regmap-offsets-for-halt-register.patch deleted file mode 100644 index d703467b8..000000000 --- a/target/linux/ipq807x/patches-5.4/106-08-remoteproc-qcom-Update-regmap-offsets-for-halt-register.patch +++ /dev/null @@ -1,129 +0,0 @@ -From patchwork Thu Jul 30 12:26:39 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692949 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03EB21746 - for ; - Thu, 30 Jul 2020 12:29:01 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by mail.kernel.org (Postfix) with ESMTP id E79E222CAD - for ; - Thu, 30 Jul 2020 12:29:00 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1728641AbgG3M24 (ORCPT - ); - Thu, 30 Jul 2020 08:28:56 -0400 -Received: from alexa-out.qualcomm.com ([129.46.98.28]:23866 "EHLO - alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1728529AbgG3M2t (ORCPT - ); - Thu, 30 Jul 2020 08:28:49 -0400 -Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) - by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:48 -0700 -Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) - by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; - 30 Jul 2020 05:28:46 -0700 -Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) - by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:14 +0530 -Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) - id 46F3A218A3; Thu, 30 Jul 2020 17:58:12 +0530 (IST) -From: Gokul Sriram Palanisamy -To: gokulsri@codeaurora.org, agross@kernel.org, - bjorn.andersson@linaro.org, david.brown@linaro.org, - devicetree@vger.kernel.org, jassisinghbrar@gmail.com, - linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, - mark.rutland@arm.com, mturquette@baylibre.com, - nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, - sboyd@kernel.org, sricharan@codeaurora.org -Subject: [PATCH v7 5/9] remoteproc: qcom: Update regmap offsets for halt - register -Date: Thu, 30 Jul 2020 17:56:39 +0530 -Message-Id: <1596112003-31663-6-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org - -Fixed issue in reading halt-regs parameter from device-tree. - -Signed-off-by: Gokul Sriram Palanisamy -Signed-off-by: Sricharan R ---- - drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++-------- - 1 file changed, 14 insertions(+), 8 deletions(-) - ---- a/drivers/remoteproc/qcom_q6v5_wcss.c -+++ b/drivers/remoteproc/qcom_q6v5_wcss.c -@@ -86,7 +86,7 @@ - #define TCSR_WCSS_CLK_MASK 0x1F - #define TCSR_WCSS_CLK_ENABLE 0x14 - --#define MAX_HALT_REG 3 -+#define MAX_HALT_REG 4 - - #define WCNSS_PAS_ID 6 - -@@ -154,6 +154,7 @@ struct wcss_data { - u32 version; - bool aon_reset_required; - bool wcss_q6_reset_required; -+ bool bcr_reset_required; - const char *ssr_name; - const char *sysmon_name; - int ssctl_id; -@@ -874,10 +875,13 @@ static int q6v5_wcss_init_reset(struct q - } - } - -- wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset"); -- if (IS_ERR(wcss->wcss_q6_bcr_reset)) { -- dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); -- return PTR_ERR(wcss->wcss_q6_bcr_reset); -+ if (desc->bcr_reset_required) { -+ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, -+ "wcss_q6_bcr_reset"); -+ if (IS_ERR(wcss->wcss_q6_bcr_reset)) { -+ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); -+ return PTR_ERR(wcss->wcss_q6_bcr_reset); -+ } - } - - return 0; -@@ -925,9 +929,9 @@ static int q6v5_wcss_init_mmio(struct q6 - return -EINVAL; - } - -- wcss->halt_q6 = halt_reg[0]; -- wcss->halt_wcss = halt_reg[1]; -- wcss->halt_nc = halt_reg[2]; -+ wcss->halt_q6 = halt_reg[1]; -+ wcss->halt_wcss = halt_reg[2]; -+ wcss->halt_nc = halt_reg[3]; - - return 0; - } -@@ -1172,6 +1176,7 @@ static const struct wcss_data wcss_ipq80 - .crash_reason_smem = WCSS_CRASH_REASON, - .aon_reset_required = true, - .wcss_q6_reset_required = true, -+ .bcr_reset_required = false, - .ssr_name = "q6wcss", - .ops = &q6v5_wcss_ipq8074_ops, - .requires_force_stop = true, -@@ -1186,6 +1191,7 @@ static const struct wcss_data wcss_qcs40 - .version = WCSS_QCS404, - .aon_reset_required = false, - .wcss_q6_reset_required = false, -+ .bcr_reset_required = true, - .ssr_name = "mpss", - .sysmon_name = "wcnss", - .ssctl_id = 0x12, diff --git a/target/linux/ipq807x/patches-5.4/106-09-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch b/target/linux/ipq807x/patches-5.4/106-09-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch deleted file mode 100644 index 7980b173c..000000000 --- a/target/linux/ipq807x/patches-5.4/106-09-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch +++ /dev/null @@ -1,74 +0,0 @@ -From patchwork Thu Jul 30 12:26:40 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692973 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82285722 - for ; - Thu, 30 Jul 2020 12:29:18 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by mail.kernel.org (Postfix) with ESMTP id 6A4A220842 - for ; - Thu, 30 Jul 2020 12:29:18 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1728355AbgG3M2s (ORCPT - ); - Thu, 30 Jul 2020 08:28:48 -0400 -Received: from alexa-out.qualcomm.com ([129.46.98.28]:23711 "EHLO - alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1728322AbgG3M2q (ORCPT - ); - Thu, 30 Jul 2020 08:28:46 -0400 -Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) - by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:46 -0700 -Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) - by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; - 30 Jul 2020 05:28:44 -0700 -Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) - by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:14 +0530 -Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) - id 7293D218A4; Thu, 30 Jul 2020 17:58:12 +0530 (IST) -From: Gokul Sriram Palanisamy -To: gokulsri@codeaurora.org, agross@kernel.org, - bjorn.andersson@linaro.org, david.brown@linaro.org, - devicetree@vger.kernel.org, jassisinghbrar@gmail.com, - linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, - mark.rutland@arm.com, mturquette@baylibre.com, - nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, - sboyd@kernel.org, sricharan@codeaurora.org -Subject: [PATCH v7 6/9] dt-bindings: clock: qcom: Add reset for WCSSAON -Date: Thu, 30 Jul 2020 17:56:40 +0530 -Message-Id: <1596112003-31663-7-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org - -Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. - -Signed-off-by: Gokul Sriram Palanisamy -Signed-off-by: Sricharan R -Signed-off-by: Nikhil Prakash V -Acked-by: Rob Herring -Acked-by: Stephen Boyd ---- - include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + - 1 file changed, 1 insertion(+) - ---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h -@@ -362,5 +362,6 @@ - #define GCC_PCIE1_AXI_SLAVE_ARES 128 - #define GCC_PCIE1_AHB_ARES 129 - #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 -+#define GCC_WCSSAON_RESET 132 - - #endif diff --git a/target/linux/ipq807x/patches-5.4/106-10-clk-qcom-Add-WCSSAON-reset.patch b/target/linux/ipq807x/patches-5.4/106-10-clk-qcom-Add-WCSSAON-reset.patch deleted file mode 100644 index 116795979..000000000 --- a/target/linux/ipq807x/patches-5.4/106-10-clk-qcom-Add-WCSSAON-reset.patch +++ /dev/null @@ -1,74 +0,0 @@ -From patchwork Thu Jul 30 12:26:41 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Gokul Sriram Palanisamy -X-Patchwork-Id: 11692991 -Return-Path: -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04D351744 - for ; - Thu, 30 Jul 2020 12:29:28 +0000 (UTC) -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by mail.kernel.org (Postfix) with ESMTP id E11AE2082E - for ; - Thu, 30 Jul 2020 12:29:27 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1728211AbgG3M2n (ORCPT - ); - Thu, 30 Jul 2020 08:28:43 -0400 -Received: from alexa-out.qualcomm.com ([129.46.98.28]:26713 "EHLO - alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1726774AbgG3M2m (ORCPT - ); - Thu, 30 Jul 2020 08:28:42 -0400 -Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) - by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:42 -0700 -Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) - by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; - 30 Jul 2020 05:28:40 -0700 -Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) - by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:15 +0530 -Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) - id 902C6218A5; Thu, 30 Jul 2020 17:58:12 +0530 (IST) -From: Gokul Sriram Palanisamy -To: gokulsri@codeaurora.org, agross@kernel.org, - bjorn.andersson@linaro.org, david.brown@linaro.org, - devicetree@vger.kernel.org, jassisinghbrar@gmail.com, - linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, - mark.rutland@arm.com, mturquette@baylibre.com, - nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, - sboyd@kernel.org, sricharan@codeaurora.org -Subject: [PATCH v7 7/9] clk: qcom: Add WCSSAON reset -Date: Thu, 30 Jul 2020 17:56:41 +0530 -Message-Id: <1596112003-31663-8-git-send-email-gokulsri@codeaurora.org> -X-Mailer: git-send-email 2.7.4 -In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> -Sender: linux-arm-msm-owner@vger.kernel.org -Precedence: bulk -List-ID: -X-Mailing-List: linux-arm-msm@vger.kernel.org - -Add WCSSAON reset required for Q6v5 on IPQ8074 SoC. - -Signed-off-by: Gokul Sriram Palanisamy -Signed-off-by: Sricharan R -Signed-off-by: Nikhil Prakash V -Acked-by: Stephen Boyd ---- - drivers/clk/qcom/gcc-ipq8074.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4685,6 +4685,7 @@ static const struct qcom_reset_map gcc_i - [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, - [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, - [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, -+ [GCC_WCSSAON_RESET] = { 0x59010, 0 }, - }; - - static const struct of_device_id gcc_ipq8074_match_table[] = { diff --git a/target/linux/ipq807x/patches-5.4/107-arm64-dts-ipq8074-Add-WLAN-node.patch b/target/linux/ipq807x/patches-5.4/107-arm64-dts-ipq8074-Add-WLAN-node.patch deleted file mode 100644 index 772cccc4c..000000000 --- a/target/linux/ipq807x/patches-5.4/107-arm64-dts-ipq8074-Add-WLAN-node.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 9e4b14257e1b4dd418fe42badc637852c69f1e6b Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 24 Aug 2020 12:33:19 +0200 -Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node - -IPQ8074 has 2 802.11ax radios supported by ath11k. -So lets add the node for ath11k. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 116 +++++++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 116 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -542,6 +542,122 @@ - }; - }; - -+ wifi0: wifi@c0000000 { -+ compatible = "qcom,ipq8074-wifi"; -+ reg = <0xc000000 0x2000000>; -+ interrupts = <0 320 1>, /* o_wcss_apps_intr[0] = */ -+ <0 319 1>, -+ <0 318 1>, -+ <0 317 1>, -+ <0 316 1>, -+ <0 315 1>, -+ <0 314 1>, -+ <0 311 1>, -+ <0 310 1>, -+ <0 411 1>, -+ <0 410 1>, -+ <0 40 1>, -+ <0 39 1>, -+ <0 302 1>, -+ <0 301 1>, -+ <0 37 1>, -+ <0 36 1>, -+ <0 296 1>, -+ <0 295 1>, -+ <0 294 1>, -+ <0 293 1>, -+ <0 292 1>, -+ <0 291 1>, -+ <0 290 1>, -+ <0 289 1>, -+ <0 288 1>, /* o_wcss_apps_intr[25] */ -+ -+ <0 239 1>, -+ <0 236 1>, -+ <0 235 1>, -+ <0 234 1>, -+ <0 233 1>, -+ <0 232 1>, -+ <0 231 1>, -+ <0 230 1>, -+ <0 229 1>, -+ <0 228 1>, -+ <0 224 1>, -+ <0 223 1>, -+ -+ <0 203 1>, -+ -+ <0 183 1>, -+ <0 180 1>, -+ <0 179 1>, -+ <0 178 1>, -+ <0 177 1>, -+ <0 176 1>, -+ -+ <0 163 1>, -+ <0 162 1>, -+ <0 160 1>, -+ <0 159 1>, -+ <0 158 1>, -+ <0 157 1>, -+ <0 156 1>; /* o_wcss_apps_intr[51] */ -+ -+ interrupt-names = "misc-pulse1", -+ "misc-latch", -+ "sw-exception", -+ "watchdog", -+ "ce0", -+ "ce1", -+ "ce2", -+ "ce3", -+ "ce4", -+ "ce5", -+ "ce6", -+ "ce7", -+ "ce8", -+ "ce9", -+ "ce10", -+ "ce11", -+ "host2wbm-desc-feed", -+ "host2reo-re-injection", -+ "host2reo-command", -+ "host2rxdma-monitor-ring3", -+ "host2rxdma-monitor-ring2", -+ "host2rxdma-monitor-ring1", -+ "reo2ost-exception", -+ "wbm2host-rx-release", -+ "reo2host-status", -+ "reo2host-destination-ring4", -+ "reo2host-destination-ring3", -+ "reo2host-destination-ring2", -+ "reo2host-destination-ring1", -+ "rxdma2host-monitor-destination-mac3", -+ "rxdma2host-monitor-destination-mac2", -+ "rxdma2host-monitor-destination-mac1", -+ "ppdu-end-interrupts-mac3", -+ "ppdu-end-interrupts-mac2", -+ "ppdu-end-interrupts-mac1", -+ "rxdma2host-monitor-status-ring-mac3", -+ "rxdma2host-monitor-status-ring-mac2", -+ "rxdma2host-monitor-status-ring-mac1", -+ "host2rxdma-host-buf-ring-mac3", -+ "host2rxdma-host-buf-ring-mac2", -+ "host2rxdma-host-buf-ring-mac1", -+ "rxdma2host-destination-ring-mac3", -+ "rxdma2host-destination-ring-mac2", -+ "rxdma2host-destination-ring-mac1", -+ "host2tcl-input-ring4", -+ "host2tcl-input-ring3", -+ "host2tcl-input-ring2", -+ "host2tcl-input-ring1", -+ "wbm2host-tx-completions-ring3", -+ "wbm2host-tx-completions-ring2", -+ "wbm2host-tx-completions-ring1", -+ "tcl2host-status-ring"; -+ qcom,rproc = <&q6v5_wcss>; -+ status = "disabled"; -+ }; -+ - pcie1: pci@10000000 { - compatible = "qcom,pcie-ipq8074"; - reg = <0x10000000 0xf1d diff --git a/target/linux/ipq807x/patches-5.4/901-arm64-qcom-dts-add-IPQ8074-dts.patch b/target/linux/ipq807x/patches-5.4/901-arm64-qcom-dts-add-IPQ8074-dts.patch deleted file mode 100644 index 0236ec005..000000000 --- a/target/linux/ipq807x/patches-5.4/901-arm64-qcom-dts-add-IPQ8074-dts.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 7dd07fff04e9333ccc660adea4cd51f7f322deb3 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 15 Jun 2020 23:28:00 +0200 -Subject: [PATCH] arm64: qcom: dts: add IPQ8074 dts - -Enable IPQ8074 dts to be built. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/Makefile | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/qcom/Makefile -+++ b/arch/arm64/boot/dts/qcom/Makefile -@@ -1,6 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb - dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb -+dtb-$(CONFIG_ARCH_QCOM) += ipq8071-ax3600.dtb - dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb - dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb - dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb diff --git a/target/linux/ipq807x/profiles/default.mk b/target/linux/ipq807x/profiles/default.mk deleted file mode 100644 index 44935d690..000000000 --- a/target/linux/ipq807x/profiles/default.mk +++ /dev/null @@ -1,8 +0,0 @@ -define Profile/Default - NAME:=Default Profile (minimum package set) -endef - -define Profile/Default/Description - Default package set compatible with most boards. -endef -$(eval $(call Profile,Default))