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Merge pull request #537 from mcucore/master
add TP-Link WR941N V7 support
This commit is contained in:
coolsnowwolf
GitHub
commit
e7a048f438
@ -852,6 +852,7 @@ tl-wa901nd)
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;;
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tl-wa901nd-v2|\
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tl-wr941nd|\
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tl-wr941n-v7|\
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tl-wr1041n-v2)
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ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt"
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;;
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@ -505,6 +505,7 @@ ar71xx_setup_interfaces()
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archer-c7-v4|\
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archer-c7-v5|\
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tl-wdr4300|\
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tl-wr941n-v7|\
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tl-wr1041n-v2)
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ucidef_add_switch "switch0" \
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"0@eth0" "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "1:wan"
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@ -479,6 +479,7 @@ get_status_led() {
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tl-wr842n-v2|\
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tl-wr842n-v3|\
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tl-wr941nd|\
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tl-wr941n-v7|\
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tl-wr941nd-v5)
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status_led="tp-link:green:system"
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;;
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@ -1368,6 +1368,9 @@ ar71xx_board_detect() {
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*"TL-WR941N/ND v6")
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name="tl-wr941nd-v6"
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;;
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*"TL-WR941N v7")
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name="tl-wr941n-v7"
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;;
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*"TL-WR941ND")
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name="tl-wr941nd"
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;;
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@ -492,6 +492,7 @@ platform_check_image() {
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tl-wr941nd|\
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tl-wr941nd-v5|\
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tl-wr941nd-v6|\
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tl-wr941n-v7|\
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ts-d084|\
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wifi-pineapple-nano)
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local magic_ver="0100"
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@ -1984,6 +1984,15 @@ config ATH79_MACH_TL_WR941ND_V6
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select ATH79_DEV_M25P80
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select ATH79_DEV_WMAC
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config ATH79_MACH_TL_WR941N_V7
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bool "TP-LINK TL-WR941N v7 support"
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select SOC_QCA955X
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select ATH79_DEV_ETH
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_M25P80
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select ATH79_DEV_WMAC
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config ATH79_MACH_TL_WR940N_V4
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bool "TP-LINK TL-WR940N v4 support"
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select SOC_QCA956X
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@ -248,6 +248,7 @@ obj-$(CONFIG_ATH79_MACH_TL_WR841N_V9) += mach-tl-wr841n-v9.o
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obj-$(CONFIG_ATH79_MACH_TL_WR902AC_V1) += mach-tl-wr902ac-v1.o
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obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o
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obj-$(CONFIG_ATH79_MACH_TL_WR941ND_V6) += mach-tl-wr941nd-v6.o
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obj-$(CONFIG_ATH79_MACH_TL_WR941N_V7) += mach-tl-wr941n-v7.o
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obj-$(CONFIG_ATH79_MACH_TL_WR940N_V4) += mach-tl-wr940n-v4.o
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obj-$(CONFIG_ATH79_MACH_TL_WR942N_V1) += mach-tl-wr942n-v1.o
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obj-$(CONFIG_ATH79_MACH_TS_D084) += mach-ts-d084.o
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281
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941n-v7.c
Normal file
281
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941n-v7.c
Normal file
@ -0,0 +1,281 @@
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/*
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* TP-LINK TL-WR941N v7 board support
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*
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* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2014 Weijie Gao <hackpacsal@gmail.com>
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* Copyright (c) 2018 Bin Chen <biosdiy@163.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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/* #include "dev-usb.h" */
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define WR941NV7_GPIO_LED_WLAN 12
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#define WR941NV7_GPIO_LED_SYSTEM 19
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#define WR941NV7_GPIO_LED_QSS 15
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#define WR941NV7_GPIO_BTN_RESET 16
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#define WR941NV7_KEYS_POLL_INTERVAL 20 /* msecs */
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#define WR941NV7_KEYS_DEBOUNCE_INTERVAL (3 * WR941NV7_KEYS_POLL_INTERVAL)
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#define ATH_MII_MGMT_CMD 0x24
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#define ATH_MGMT_CMD_READ 0x1
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#define ATH_MII_MGMT_ADDRESS 0x28
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#define ATH_ADDR_SHIFT 8
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#define ATH_MII_MGMT_CTRL 0x2c
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#define ATH_MII_MGMT_STATUS 0x30
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#define ATH_MII_MGMT_IND 0x34
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#define ATH_MGMT_IND_BUSY (1 << 0)
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#define ATH_MGMT_IND_INVALID (1 << 2)
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static const char *wr941nv7_part_probes[] = {
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"tp-link",
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NULL,
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};
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static struct flash_platform_data wr941nv7_flash_data = {
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.part_probes = wr941nv7_part_probes,
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};
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static struct gpio_led wr941nv7_leds_gpio[] __initdata = {
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{
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.name = "tp-link:green:qss",
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.gpio = WR941NV7_GPIO_LED_QSS,
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.active_low = 1,
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},
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{
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.name = "tp-link:green:system",
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.gpio = WR941NV7_GPIO_LED_SYSTEM,
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.active_low = 1,
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},
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{
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.name = "tp-link:green:wlan",
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.gpio = WR941NV7_GPIO_LED_WLAN,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button wr941nv7_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = WR941NV7_KEYS_DEBOUNCE_INTERVAL,
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.gpio = WR941NV7_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static struct mdio_board_info wr941nv7_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 0,
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.platform_data = NULL,
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},
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};
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static unsigned long __init ath_gmac_reg_rd(unsigned long reg)
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{
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void __iomem *base;
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unsigned long t;
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base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE);
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t = __raw_readl(base + reg);
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iounmap(base);
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return t;
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}
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static void __init ath_gmac_reg_wr(unsigned long reg, unsigned long value)
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{
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void __iomem *base;
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unsigned long t = value;
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base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE);
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__raw_writel(t, base + reg);
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iounmap(base);
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}
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static void __init phy_reg_write(unsigned char phy_addr, unsigned char reg, unsigned short data)
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{
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unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg;
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volatile int rddata;
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unsigned short ii = 0xFFFF;
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do
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{
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udelay(5);
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rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
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} while (rddata && --ii);
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ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr);
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ath_gmac_reg_wr(ATH_MII_MGMT_CTRL, data);
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do
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{
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udelay(5);
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rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
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} while (rddata && --ii);
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}
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static unsigned short __init phy_reg_read(unsigned char phy_addr, unsigned char reg)
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{
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unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg, val;
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volatile int rddata;
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unsigned short ii = 0xffff;
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do
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{
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udelay(5);
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rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
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} while (rddata && --ii);
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ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0);
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ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr);
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ath_gmac_reg_wr(ATH_MII_MGMT_CMD, ATH_MGMT_CMD_READ);
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do
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{
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udelay(5);
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rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
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} while (rddata && --ii);
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val = ath_gmac_reg_rd(ATH_MII_MGMT_STATUS);
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ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0);
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return val;
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}
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static void __init athrs27_reg_write(unsigned int s27_addr, unsigned int s27_write_data)
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{
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unsigned int addr_temp;
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unsigned int data;
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unsigned char phy_address, reg_address;
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addr_temp = (s27_addr) >> 2;
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data = addr_temp >> 7;
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phy_address = 0x1f;
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reg_address = 0x10;
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phy_reg_write(phy_address, reg_address, data);
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phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
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reg_address = (((addr_temp << 1) & 0x1e) | 0x1);
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data = (s27_write_data >> 16) & 0xffff;
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phy_reg_write(phy_address, reg_address, data);
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reg_address = ((addr_temp << 1) & 0x1e);
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data = s27_write_data & 0xffff;
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phy_reg_write(phy_address, reg_address, data);
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}
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static unsigned int __init athrs27_reg_read(unsigned int s27_addr)
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{
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unsigned int addr_temp;
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unsigned int s27_rd_csr_low, s27_rd_csr_high, s27_rd_csr;
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unsigned int data;
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unsigned char phy_address, reg_address;
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addr_temp = s27_addr >>2;
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data = addr_temp >> 7;
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phy_address = 0x1f;
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reg_address = 0x10;
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phy_reg_write(phy_address, reg_address, data);
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phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
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reg_address = ((addr_temp << 1) & 0x1e);
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s27_rd_csr_low = (unsigned int) phy_reg_read(phy_address, reg_address);
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reg_address = reg_address | 0x1;
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s27_rd_csr_high = (unsigned int) phy_reg_read(phy_address, reg_address);
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s27_rd_csr = (s27_rd_csr_high << 16) | s27_rd_csr_low ;
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return (s27_rd_csr);
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}
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static void __init ar8236_reset(void)
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{
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unsigned short i = 60;
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athrs27_reg_write(0x0, athrs27_reg_read(0x0) | 0x80000000);
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while (i--)
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{
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mdelay(100);
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if (!(athrs27_reg_read(0x0) & 0x80000000))
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break;
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}
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}
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static void __init wr941nv7_setup(void)
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{
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u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
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u8 *art = (u8 *) KSEG1ADDR(0x1fff1000);
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ath79_register_m25p80(&wr941nv7_flash_data);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(wr941nv7_leds_gpio),
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wr941nv7_leds_gpio);
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ath79_register_gpio_keys_polled(-1, WR941NV7_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(wr941nv7_gpio_keys),
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wr941nv7_gpio_keys);
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/* WiFi Port */
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ath79_register_wmac(art, mac);
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ar8236_reset();
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_MII_GE0 |
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QCA955X_ETH_CFG_MII_GE0_SLAVE);
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mdiobus_register_board_info(wr941nv7_mdio0_info,
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ARRAY_SIZE(wr941nv7_mdio0_info));
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ath79_register_mdio(0, 0x0);
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/* WAN Port */
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ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
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/* GMAC0 is connected to an AR8236 switch */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.speed = SPEED_100;
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ath79_eth0_data.duplex = DUPLEX_FULL;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_register_eth(0);
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/* ath79_register_usb(); */
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}
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MIPS_MACHINE(ATH79_MACH_TL_WR941N_V7, "TL-WR941N-v7",
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"TP-LINK TL-WR941N v7",
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wr941nv7_setup);
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@ -310,6 +310,7 @@ enum ath79_mach_type {
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ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
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ATH79_MACH_TL_WR941ND_V5, /* TP-LINK TL-WR941ND v5 */
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ATH79_MACH_TL_WR941ND_V6, /* TP-LINK TL-WR941ND v6 */
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ATH79_MACH_TL_WR941N_V7, /* TP-LINK TL-WR941N v7 */
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ATH79_MACH_TL_WR940N_V4, /* TP-LINK TL-WR940N v4 */
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ATH79_MACH_TL_WR940N_V6, /* TP-LINK TL-WR940N v6 */
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ATH79_MACH_TL_WR942N_V1, /* TP-LINK TL-WR942N v1 */
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@ -686,3 +686,12 @@ define Device/tl-wr941nd-v6-cn
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TPLINK_HWID := 0x09410006
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endef
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TARGET_DEVICES += tl-wr941nd-v6-cn
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define Device/tl-wr941n-v7
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$(Device/tplink-8mlzma)
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DEVICE_TITLE := TP-LINK TL-WR941N/ND v7
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BOARDNAME := TL-WR941N-v7
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DEVICE_PROFILE := TLWR941
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TPLINK_HWID := 0x09410007
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endef
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TARGET_DEVICES += tl-wr941n-v7
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