ipq807x: refresh 5.10 patches

target/linux/ipq807x/patches-5.10/100-clk-qcom-ipq8074-fix-PCI-E-clock-oops.patch

@@ -1,54 +1,88 @@
-From 8d111d707f71bc17c616b0bcca327ee0a3db50e8 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 2 Nov 2020 19:03:59 +0100
-Subject: [PATCH] clk: qcom: ipq8074: fix PCI-E clock oops
-
-Fix PCI-E clock related kernel oops that are causes by missing
-parent_names.
-
-Without the use of parent_names kernel will panic on
-clk_core_get_parent_by_index() due to a NULL pointer.
-
-Without this earlycon is needed to even catch the OOPS as it will reset
-the board before serial is initialized.
-
-Fixes: f0cfcf1ade20 ("clk: qcom: ipq8074: Add missing clocks for pcie")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/clk/qcom/gcc-ipq8074.c | 11 +++++------
- 1 file changed, 5 insertions(+), 6 deletions(-)
-
 --- a/drivers/clk/qcom/gcc-ipq8074.c
 +++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -4329,8 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
+@@ -60,6 +60,11 @@ static const struct parent_map gcc_xo_gp
+ 	{ P_GPLL0_DIV2, 4 },
+ };
+ 
++static const char * const gcc_xo_gpll0[] = {
++	"xo",
++	"gpll0",
++};
++
+ static const struct parent_map gcc_xo_gpll0_map[] = {
+ 	{ P_XO, 0 },
+ 	{ P_GPLL0, 1 },
+@@ -951,11 +956,6 @@ static struct clk_rcg2 blsp1_uart6_apps_
+ 	},
+ };
+ 
+-static const struct clk_parent_data gcc_xo_gpll0[] = {
+-	{ .fw_name = "xo" },
+-	{ .hw = &gpll0.clkr.hw },
+-};
+-
+ static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
+ 	F(19200000, P_XO, 1, 0, 0),
+ 	F(200000000, P_GPLL0, 4, 0, 0),
+@@ -969,7 +969,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
  	.parent_map = gcc_xo_gpll0_map,
  	.clkr.hw.init = &(struct clk_init_data){
- 		.name = "pcie0_rchng_clk_src",
+ 		.name = "pcie0_axi_clk_src",
--		.parent_hws = (const struct clk_hw *[]) {
+-		.parent_data = gcc_xo_gpll0,
--				&gpll0.clkr.hw },
 +		.parent_names = gcc_xo_gpll0,
  		.num_parents = 2,
  		.ops = &clk_rcg2_ops,
  	},
-@@ -4344,8 +4343,8 @@ static struct clk_branch gcc_pcie0_rchng
+@@ -1016,7 +1016,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
+ 	.parent_map = gcc_xo_gpll0_map,
+ 	.clkr.hw.init = &(struct clk_init_data){
+ 		.name = "pcie1_axi_clk_src",
+-		.parent_data = gcc_xo_gpll0,
++		.parent_names = gcc_xo_gpll0,
+ 		.num_parents = 2,
+ 		.ops = &clk_rcg2_ops,
+ 	},
+@@ -1330,7 +1330,7 @@ static struct clk_rcg2 nss_ce_clk_src =
+ 	.parent_map = gcc_xo_gpll0_map,
+ 	.clkr.hw.init = &(struct clk_init_data){
+ 		.name = "nss_ce_clk_src",
+-		.parent_data = gcc_xo_gpll0,
++		.parent_names = gcc_xo_gpll0,
+ 		.num_parents = 2,
+ 		.ops = &clk_rcg2_ops,
+ 	},
+@@ -4329,7 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
+ 	.parent_map = gcc_xo_gpll0_map,
+ 	.clkr.hw.init = &(struct clk_init_data){
+ 		.name = "pcie0_rchng_clk_src",
+-		.parent_data = gcc_xo_gpll0,
++		.parent_names = gcc_xo_gpll0,
+ 		.num_parents = 2,
+ 		.ops = &clk_rcg2_ops,
+ 	},
+@@ -4343,9 +4343,9 @@ static struct clk_branch gcc_pcie0_rchng
  		.enable_mask = BIT(1),
  		.hw.init = &(struct clk_init_data){
  			.name = "gcc_pcie0_rchng_clk",
 -			.parent_hws = (const struct clk_hw *[]){
 -				&pcie0_rchng_clk_src.clkr.hw,
+-			},
 +			.parent_names = (const char *[]){
 +				"pcie0_rchng_clk_src",
- 			},
++		},
  			.num_parents = 1,
  			.flags = CLK_SET_RATE_PARENT,
-@@ -4362,8 +4361,8 @@ static struct clk_branch gcc_pcie0_axi_s
+ 			.ops = &clk_branch2_ops,
+@@ -4361,9 +4361,9 @@ static struct clk_branch gcc_pcie0_axi_s
  		.enable_mask = BIT(0),
  		.hw.init = &(struct clk_init_data){
  			.name = "gcc_pcie0_axi_s_bridge_clk",
 -			.parent_hws = (const struct clk_hw *[]){
 -				&pcie0_axi_clk_src.clkr.hw,
+-			},
 +			.parent_names = (const char *[]){
 +				"pcie0_axi_clk_src"
- 			},
++		},
  			.num_parents = 1,
  			.flags = CLK_SET_RATE_PARENT,
+ 			.ops = &clk_branch2_ops,

target/linux/ipq807x/patches-5.10/991-clk-qcom-add-support-for-hw-controlled-RCG.patch

@@ -86,7 +86,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
  }
  
  /*
-@@ -302,12 +310,19 @@ static int __clk_rcg2_configure(struct c
+@@ -311,12 +319,19 @@ static int __clk_rcg2_configure(struct c
  static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
  {
  	int ret;
@@ -107,7 +107,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
  }
  
  static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
-@@ -786,7 +801,7 @@ static int clk_gfx3d_set_rate_and_parent
+@@ -796,7 +811,7 @@ static int clk_gfx3d_set_rate_and_parent
  	if (ret)
  		return ret;
  
@@ -116,7 +116,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
  }
  
  static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
-@@ -898,7 +913,7 @@ static int clk_rcg2_shared_enable(struct
+@@ -908,7 +923,7 @@ static int clk_rcg2_shared_enable(struct
  	if (ret)
  		return ret;
  
@@ -125,7 +125,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
  	if (ret)
  		return ret;
  
-@@ -929,7 +944,7 @@ static void clk_rcg2_shared_disable(stru
+@@ -939,7 +954,7 @@ static void clk_rcg2_shared_disable(stru
  	regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
  		     rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
  
@@ -133,4 +133,4 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599
 +	update_config(rcg, true);
  
  	clk_rcg2_clear_force_enable(hw);
- 
+