ar71xx: update kernel from 4.4 to 4.9.54

2025-04-19 03:43:29 +00:00 · 2017-10-12 16:12:47 +08:00 · 2017-10-12 16:12:47 +08:00 · d3ce52d090
commit d3ce52d090
parent 391656812d
128 changed files with 8420 additions and 149 deletions
--- a/target/linux/ar71xx/Makefile
+++ b/target/linux/ar71xx/Makefile
@ -13,7 +13,7 @@ FEATURES:=usbgadget
 CPU_TYPE:=24kc
 SUBTARGETS:=generic nand mikrotik

-KERNEL_PATCHVER:=4.4
+KERNEL_PATCHVER:=4.9

 include $(INCLUDE_DIR)/target.mk

--- a/target/linux/ar71xx/base-files/etc/board.d/02_network
+++ b/target/linux/ar71xx/base-files/etc/board.d/02_network
@ -531,7 +531,8 @@ ar71xx_setup_macs()
 		lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)"))
 		;;
 	tl-wr1043nd-v4)
-		wan_mac=$(mtd_get_mac_binary config 0x1017c)
+		lan_mac=$(mtd_get_mac_binary product-info 8)
+		wan_mac=$(macaddr_add "$lan_mac" 1)
 		;;
 	esr900)
 		wan_mac=$(mtd_get_mac_ascii u-boot-env "wanaddr")
--- a/target/linux/ar71xx/config-4.4
+++ b/target/linux/ar71xx/config-4.4
@ -260,7 +260,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_CEVT_R4K=y
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd"
+CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
 CONFIG_CMDLINE_BOOL=y
 # CONFIG_CMDLINE_OVERRIDE is not set
 CONFIG_COMMON_CLK=y
--- a/target/linux/ar71xx/config-4.9
+++ b/target/linux/ar71xx/config-4.9
@ -0,0 +1,485 @@
+CONFIG_AG71XX=y
+CONFIG_AG71XX_AR8216_SUPPORT=y
+# CONFIG_AG71XX_DEBUG is not set
+# CONFIG_AG71XX_DEBUG_FS is not set
+CONFIG_AR8216_PHY=y
+CONFIG_AR8216_PHY_LEDS=y
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_AT803X_PHY=y
+CONFIG_ATH79=y
+CONFIG_ATH79_DEV_AP9X_PCI=y
+CONFIG_ATH79_DEV_DSA=y
+CONFIG_ATH79_DEV_ETH=y
+CONFIG_ATH79_DEV_GPIO_BUTTONS=y
+CONFIG_ATH79_DEV_LEDS_GPIO=y
+CONFIG_ATH79_DEV_M25P80=y
+CONFIG_ATH79_DEV_NFC=y
+CONFIG_ATH79_DEV_SPI=y
+CONFIG_ATH79_DEV_USB=y
+CONFIG_ATH79_DEV_WMAC=y
+CONFIG_ATH79_MACH_A60=y
+CONFIG_ATH79_MACH_ALFA_AP120C=y
+CONFIG_ATH79_MACH_ALFA_AP96=y
+CONFIG_ATH79_MACH_ALFA_NX=y
+CONFIG_ATH79_MACH_ALL0258N=y
+CONFIG_ATH79_MACH_ALL0315N=y
+CONFIG_ATH79_MACH_ANTMINER_S1=y
+CONFIG_ATH79_MACH_ANTMINER_S3=y
+CONFIG_ATH79_MACH_ANTROUTER_R1=y
+CONFIG_ATH79_MACH_AP121=y
+CONFIG_ATH79_MACH_AP121F=y
+CONFIG_ATH79_MACH_AP132=y
+CONFIG_ATH79_MACH_AP136=y
+CONFIG_ATH79_MACH_AP143=y
+CONFIG_ATH79_MACH_AP147=y
+CONFIG_ATH79_MACH_AP152=y
+CONFIG_ATH79_MACH_AP531B0=y
+# CONFIG_ATH79_MACH_AP81 is not set
+CONFIG_ATH79_MACH_AP90Q=y
+CONFIG_ATH79_MACH_AP96=y
+CONFIG_ATH79_MACH_ARCHER_C25_V1=y
+CONFIG_ATH79_MACH_ARCHER_C58_V1=y
+CONFIG_ATH79_MACH_ARCHER_C59_V1=y
+CONFIG_ATH79_MACH_ARCHER_C60_V1=y
+CONFIG_ATH79_MACH_ARCHER_C7=y
+CONFIG_ATH79_MACH_ARDUINO_YUN=y
+CONFIG_ATH79_MACH_AW_NR580=y
+CONFIG_ATH79_MACH_BHR_4GRV2=y
+CONFIG_ATH79_MACH_BHU_BXU2000N2_A=y
+CONFIG_ATH79_MACH_BSB=y
+CONFIG_ATH79_MACH_C55=y
+# CONFIG_ATH79_MACH_C60 is not set
+CONFIG_ATH79_MACH_CAP324=y
+CONFIG_ATH79_MACH_CAP4200AG=y
+CONFIG_ATH79_MACH_CARAMBOLA2=y
+CONFIG_ATH79_MACH_CF_E316N_V2=y
+CONFIG_ATH79_MACH_CF_E320N_V2=y
+CONFIG_ATH79_MACH_CF_E355AC=y
+CONFIG_ATH79_MACH_CF_E380AC_V1=y
+CONFIG_ATH79_MACH_CF_E380AC_V2=y
+CONFIG_ATH79_MACH_CF_E520N=y
+CONFIG_ATH79_MACH_CF_E530N=y
+CONFIG_ATH79_MACH_CPE505N=y
+CONFIG_ATH79_MACH_CPE510=y
+CONFIG_ATH79_MACH_CPE830=y
+CONFIG_ATH79_MACH_CPE870=y
+CONFIG_ATH79_MACH_CR3000=y
+CONFIG_ATH79_MACH_CR5000=y
+CONFIG_ATH79_MACH_DAP_2695_A1=y
+CONFIG_ATH79_MACH_DB120=y
+CONFIG_ATH79_MACH_DGL_5500_A1=y
+CONFIG_ATH79_MACH_DHP_1565_A1=y
+CONFIG_ATH79_MACH_DIR_505_A1=y
+CONFIG_ATH79_MACH_DIR_600_A1=y
+CONFIG_ATH79_MACH_DIR_615_C1=y
+CONFIG_ATH79_MACH_DIR_615_I1=y
+CONFIG_ATH79_MACH_DIR_825_B1=y
+CONFIG_ATH79_MACH_DIR_825_C1=y
+CONFIG_ATH79_MACH_DIR_869_A1=y
+CONFIG_ATH79_MACH_DLAN_HOTSPOT=y
+CONFIG_ATH79_MACH_DLAN_PRO_1200_AC=y
+CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y
+# CONFIG_ATH79_MACH_DOMYWIFI_DW33D is not set
+CONFIG_ATH79_MACH_DR344=y
+CONFIG_ATH79_MACH_DR531=y
+CONFIG_ATH79_MACH_DRAGINO2=y
+CONFIG_ATH79_MACH_E2100L=y
+CONFIG_ATH79_MACH_EAP120=y
+CONFIG_ATH79_MACH_EAP300V2=y
+CONFIG_ATH79_MACH_EAP7660D=y
+CONFIG_ATH79_MACH_EL_M150=y
+CONFIG_ATH79_MACH_EL_MINI=y
+CONFIG_ATH79_MACH_ENS202EXT=y
+CONFIG_ATH79_MACH_EPG5000=y
+CONFIG_ATH79_MACH_ESR1750=y
+CONFIG_ATH79_MACH_ESR900=y
+CONFIG_ATH79_MACH_EW_DORIN=y
+CONFIG_ATH79_MACH_F9K1115V2=y
+CONFIG_ATH79_MACH_FRITZ300E=y
+CONFIG_ATH79_MACH_GL_AR150=y
+CONFIG_ATH79_MACH_GL_AR300=y
+CONFIG_ATH79_MACH_GL_AR300M=y
+CONFIG_ATH79_MACH_GL_DOMINO=y
+CONFIG_ATH79_MACH_GL_INET=y
+CONFIG_ATH79_MACH_GL_MIFI=y
+CONFIG_ATH79_MACH_GL_USB150=y
+CONFIG_ATH79_MACH_GS_MINIBOX_V1=y
+CONFIG_ATH79_MACH_GS_OOLITE=y
+# CONFIG_ATH79_MACH_HIVEAP_121 is not set
+CONFIG_ATH79_MACH_HIWIFI_HC6361=y
+CONFIG_ATH79_MACH_HORNET_UB=y
+CONFIG_ATH79_MACH_JA76PF=y
+CONFIG_ATH79_MACH_JWAP003=y
+CONFIG_ATH79_MACH_JWAP230=y
+CONFIG_ATH79_MACH_LIMA=y
+CONFIG_ATH79_MACH_MC_MAC1200R=y
+CONFIG_ATH79_MACH_MR12=y
+CONFIG_ATH79_MACH_MR16=y
+CONFIG_ATH79_MACH_MR1750=y
+# CONFIG_ATH79_MACH_MR18 is not set
+CONFIG_ATH79_MACH_MR600=y
+CONFIG_ATH79_MACH_MR900=y
+CONFIG_ATH79_MACH_MYNET_N600=y
+CONFIG_ATH79_MACH_MYNET_N750=y
+CONFIG_ATH79_MACH_MYNET_REXT=y
+CONFIG_ATH79_MACH_MZK_W04NU=y
+CONFIG_ATH79_MACH_MZK_W300NH=y
+CONFIG_ATH79_MACH_NBG460N=y
+CONFIG_ATH79_MACH_NBG6716=y
+CONFIG_ATH79_MACH_OM2P=y
+CONFIG_ATH79_MACH_OM5P=y
+CONFIG_ATH79_MACH_OM5P_AC=y
+CONFIG_ATH79_MACH_OM5P_ACv2=y
+CONFIG_ATH79_MACH_OMY_G1=y
+CONFIG_ATH79_MACH_OMY_X1=y
+CONFIG_ATH79_MACH_ONION_OMEGA=y
+CONFIG_ATH79_MACH_PB42=y
+CONFIG_ATH79_MACH_PB44=y
+CONFIG_ATH79_MACH_PQI_AIR_PEN=y
+CONFIG_ATH79_MACH_QIHOO_C301=y
+CONFIG_ATH79_MACH_R602N=y
+# CONFIG_ATH79_MACH_R6100 is not set
+# CONFIG_ATH79_MACH_RAMBUTAN is not set
+# CONFIG_ATH79_MACH_RB2011 is not set
+# CONFIG_ATH79_MACH_RB4XX is not set
+# CONFIG_ATH79_MACH_RB750 is not set
+# CONFIG_ATH79_MACH_RB91X is not set
+# CONFIG_ATH79_MACH_RB922 is not set
+# CONFIG_ATH79_MACH_RB95X is not set
+# CONFIG_ATH79_MACH_RBSPI is not set
+# CONFIG_ATH79_MACH_RBSXTLITE is not set
+CONFIG_ATH79_MACH_RE450=y
+CONFIG_ATH79_MACH_RW2458N=y
+CONFIG_ATH79_MACH_SC1750=y
+CONFIG_ATH79_MACH_SC300M=y
+CONFIG_ATH79_MACH_SC450=y
+CONFIG_ATH79_MACH_SMART_300=y
+CONFIG_ATH79_MACH_SOM9331=y
+CONFIG_ATH79_MACH_SR3200=y
+CONFIG_ATH79_MACH_TELLSTICK_ZNET_LITE=y
+CONFIG_ATH79_MACH_TEW_632BRP=y
+CONFIG_ATH79_MACH_TEW_673GRU=y
+CONFIG_ATH79_MACH_TEW_712BR=y
+CONFIG_ATH79_MACH_TEW_732BR=y
+CONFIG_ATH79_MACH_TEW_823DRU=y
+CONFIG_ATH79_MACH_TL_MR11U=y
+CONFIG_ATH79_MACH_TL_MR13U=y
+CONFIG_ATH79_MACH_TL_MR3020=y
+CONFIG_ATH79_MACH_TL_MR3X20=y
+CONFIG_ATH79_MACH_TL_MR6400=y
+CONFIG_ATH79_MACH_TL_WA701ND_V2=y
+CONFIG_ATH79_MACH_TL_WA7210N_V2=y
+CONFIG_ATH79_MACH_TL_WA801ND_V3=y
+CONFIG_ATH79_MACH_TL_WA830RE_V2=y
+CONFIG_ATH79_MACH_TL_WA850RE_V2=y
+CONFIG_ATH79_MACH_TL_WA855RE_V1=y
+CONFIG_ATH79_MACH_TL_WA901ND=y
+CONFIG_ATH79_MACH_TL_WA901ND_V2=y
+CONFIG_ATH79_MACH_TL_WA901ND_V4=y
+CONFIG_ATH79_MACH_TL_WAX50RE=y
+CONFIG_ATH79_MACH_TL_WDR3320_V2=y
+CONFIG_ATH79_MACH_TL_WDR3500=y
+CONFIG_ATH79_MACH_TL_WDR4300=y
+CONFIG_ATH79_MACH_TL_WDR6500_V2=y
+CONFIG_ATH79_MACH_TL_WPA8630=y
+CONFIG_ATH79_MACH_TL_WR1041N_V2=y
+CONFIG_ATH79_MACH_TL_WR1043ND=y
+CONFIG_ATH79_MACH_TL_WR1043ND_V2=y
+CONFIG_ATH79_MACH_TL_WR1043ND_V4=y
+CONFIG_ATH79_MACH_TL_WR2543N=y
+CONFIG_ATH79_MACH_TL_WR703N=y
+CONFIG_ATH79_MACH_TL_WR720N_V3=y
+CONFIG_ATH79_MACH_TL_WR741ND=y
+CONFIG_ATH79_MACH_TL_WR741ND_V4=y
+CONFIG_ATH79_MACH_TL_WR802N_V1=y
+CONFIG_ATH79_MACH_TL_WR802N_V2=y
+CONFIG_ATH79_MACH_TL_WR810N=y
+CONFIG_ATH79_MACH_TL_WR840N_V2=y
+CONFIG_ATH79_MACH_TL_WR841N_V1=y
+CONFIG_ATH79_MACH_TL_WR841N_V8=y
+CONFIG_ATH79_MACH_TL_WR841N_V9=y
+CONFIG_ATH79_MACH_TL_WR902AC_V1=y
+CONFIG_ATH79_MACH_TL_WR940N_V4=y
+CONFIG_ATH79_MACH_TL_WR941ND=y
+CONFIG_ATH79_MACH_TL_WR941ND_V6=y
+CONFIG_ATH79_MACH_TL_WR942N_V1=y
+CONFIG_ATH79_MACH_TUBE2H=y
+CONFIG_ATH79_MACH_UBNT=y
+CONFIG_ATH79_MACH_UBNT_UNIFIAC=y
+CONFIG_ATH79_MACH_UBNT_XM=y
+CONFIG_ATH79_MACH_WEIO=y
+CONFIG_ATH79_MACH_WHR_HP_G300N=y
+CONFIG_ATH79_MACH_WLAE_AG300N=y
+CONFIG_ATH79_MACH_WLR8100=y
+CONFIG_ATH79_MACH_WNDAP360=y
+CONFIG_ATH79_MACH_WNDR3700=y
+# CONFIG_ATH79_MACH_WNDR4300 is not set
+CONFIG_ATH79_MACH_WNR2000=y
+CONFIG_ATH79_MACH_WNR2000_V3=y
+CONFIG_ATH79_MACH_WNR2000_V4=y
+CONFIG_ATH79_MACH_WNR2200=y
+CONFIG_ATH79_MACH_WP543=y
+CONFIG_ATH79_MACH_WPE72=y
+CONFIG_ATH79_MACH_WPJ342=y
+CONFIG_ATH79_MACH_WPJ344=y
+CONFIG_ATH79_MACH_WPJ531=y
+CONFIG_ATH79_MACH_WPJ558=y
+CONFIG_ATH79_MACH_WPJ563=y
+CONFIG_ATH79_MACH_WRT160NL=y
+CONFIG_ATH79_MACH_WRT400N=y
+CONFIG_ATH79_MACH_WRTNODE2Q=y
+CONFIG_ATH79_MACH_WZR_450HP2=y
+CONFIG_ATH79_MACH_WZR_HP_AG300H=y
+CONFIG_ATH79_MACH_WZR_HP_G300NH=y
+CONFIG_ATH79_MACH_WZR_HP_G300NH2=y
+CONFIG_ATH79_MACH_WZR_HP_G450H=y
+CONFIG_ATH79_MACH_XD3200=y
+# CONFIG_ATH79_MACH_Z1 is not set
+CONFIG_ATH79_MACH_ZBT_WE1526=y
+CONFIG_ATH79_MACH_ZCN_1523H=y
+CONFIG_ATH79_NVRAM=y
+CONFIG_ATH79_PCI_ATH9K_FIXUP=y
+# CONFIG_ATH79_ROUTERBOOT is not set
+CONFIG_ATH79_WDT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_74X164=y
+CONFIG_GPIO_ATH79=y
+CONFIG_GPIO_GENERIC=y
+# CONFIG_GPIO_LATCH is not set
+CONFIG_GPIO_NXP_74HC153=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CBPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_GPIO=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_SOURCE="../../root"
+CONFIG_INTEL_XWAY_PHY=y
+CONFIG_IP17XX_PHY=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_WNDR3700_USB is not set
+CONFIG_LIBFDT=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MICREL_PHY=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_MIPS_CMDLINE_FROM_DTB is not set
+# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_MACHINE=y
+CONFIG_MIPS_NO_APPENDED_DTB=y
+# CONFIG_MIPS_RAW_APPENDED_DTB is not set
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CYBERTAN_PARTS=y
+CONFIG_MTD_M25P80=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+CONFIG_MTD_MYLOADER_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_EVA_FW=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_LZMA_FW=y
+CONFIG_MTD_SPLIT_MINOR_FW=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_MTD_TPLINK_PARTS=y
+CONFIG_MYLOADER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MV88E6060=y
+CONFIG_NET_DSA_MV88E6063=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PCI=y
+CONFIG_PCI_AR724X=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_RATIONAL=y
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RTL8306_PHY=y
+CONFIG_RTL8366RB_PHY=y
+CONFIG_RTL8366S_PHY=y
+CONFIG_RTL8366_SMI=y
+CONFIG_RTL8367_PHY=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_FSL is not set
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_AR933X=y
+CONFIG_SERIAL_AR933X_CONSOLE=y
+CONFIG_SERIAL_AR933X_NR_UARTS=2
+CONFIG_SOC_AR71XX=y
+CONFIG_SOC_AR724X=y
+CONFIG_SOC_AR913X=y
+CONFIG_SOC_AR933X=y
+CONFIG_SOC_AR934X=y
+CONFIG_SOC_QCA953X=y
+CONFIG_SOC_QCA955X=y
+CONFIG_SOC_QCA956X=y
+CONFIG_SPI=y
+CONFIG_SPI_ATH79=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_RB4XX is not set
+# CONFIG_SPI_VSC7385 is not set
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c25-v1.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c25-v1.c
@ -74,7 +74,7 @@ static struct spi_gpio_platform_data archer_c25_v1_spi_data = {
 	.num_chipselect	= 1,
 };

-static u8 archer_c25_v1_ssr_initdata[] __initdata = {
+static u8 archer_c25_v1_ssr_initdata[] = {
 	BIT(ARCHER_C25_V1_SSR_BIT_7) |
 	BIT(ARCHER_C25_V1_SSR_BIT_6) |
 	BIT(ARCHER_C25_V1_SSR_BIT_5) |
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c59-v1.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c59-v1.c
@ -180,7 +180,7 @@ static struct spi_gpio_platform_data archer_c59_v1_spi_data = {
 	.num_chipselect = 1,
 };

-static u8 archer_c59_v1_ssr_initdata[] __initdata = {
+static u8 archer_c59_v1_ssr_initdata[] = {
 	BIT(ARCHER_C59_V1_SSR_BIT_7) |
 	BIT(ARCHER_C59_V1_SSR_BIT_6) |
 	BIT(ARCHER_C59_V1_SSR_BIT_5) |
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
@ -141,7 +141,7 @@ static struct gpio_keys_button archer_c7_v2_gpio_keys[] __initdata = {
 	},
 };

-static const struct ar8327_led_info archer_c7_leds_ar8327[] __initconst = {
+static const struct ar8327_led_info archer_c7_leds_ar8327[] = {
 	AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"),
 	AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"),
 	AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"),
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-c60.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-c60.c
@ -22,6 +22,7 @@
 #include <linux/platform/ar934x_nfc.h>
 #include <linux/ar8216_platform.h>
 #include <linux/ath9k_platform.h>
+#include <linux/version.h>

 #include <asm/mach-ath79/ar71xx_regs.h>

@ -119,6 +120,7 @@ static struct mdio_board_info c60_mdio0_info[] = {
 	},
 };

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 static struct nand_ecclayout c60_nand_ecclayout = {
 	.eccbytes       = 7,
 	.eccpos         = { 4, 8, 9, 10, 13, 14, 15 },
@ -126,13 +128,67 @@ static struct nand_ecclayout c60_nand_ecclayout = {
 	.oobfree        = { { 0, 3 }, { 6, 2 }, { 11, 2 }, }
 };

+#else
+
+static int c60_ooblayout_ecc(struct mtd_info *mtd, int section,
+			     struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 1:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 2:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int c60_ooblayout_free(struct mtd_info *mtd, int section,
+			      struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 2:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops c60_nand_ecclayout_ops = {
+	.ecc = c60_ooblayout_ecc,
+	.free = c60_ooblayout_free,
+};
+#endif /* < 4.6 */
+
 static int c60_nand_scan_fixup(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;

 	chip->ecc.size = 512;
 	chip->ecc.strength = 4;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 	chip->ecc.layout = &c60_nand_ecclayout;
+#else
+	mtd_set_ooblayout(mtd, &c60_nand_ecclayout_ops);
+#endif
 	return 0;
 }

--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c
@ -2,7 +2,7 @@
 *  EW Dorin board support
 *  (based on Atheros Ref. Design AP121)
 *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2012-2015 Embedded Wireless GmbH    www.80211.de
+ *  Copyright (C) 2012-2017 Embedded Wireless GmbH    www.80211.de
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
@ -27,24 +27,12 @@
 #define DORIN_CALDATA_OFFSET		0x1000
 #define DORIN_WMAC_MAC_OFFSET		0x1002

-#define DORIN_GPIO_LED_21		21
-#define DORIN_GPIO_LED_22		22
-#define DORIN_GPIO_LED_STATUS	23
+#define DORIN_GPIO_LED_STATUS		21

 #define DORIN_GPIO_BTN_JUMPSTART	11
 #define DORIN_GPIO_BTN_RESET		6

 static struct gpio_led dorin_leds_gpio[] __initdata = {
-	{
-		.name		= "dorin:green:led21",
-		.gpio		= DORIN_GPIO_LED_21,
-		.active_low	= 1,
-	},
-	{
-		.name		= "dorin:green:led22",
-		.gpio		= DORIN_GPIO_LED_22,
-		.active_low	= 1,
-	},
 	{
 		.name		= "dorin:green:status",
 		.gpio		= DORIN_GPIO_LED_STATUS,
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n750.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n750.c
@ -98,7 +98,7 @@ static struct gpio_keys_button mynet_n750_gpio_keys[] __initdata = {
 	},
 };

-static const struct ar8327_led_info mynet_n750_leds_ar8327[] __initconst = {
+static const struct ar8327_led_info mynet_n750_leds_ar8327[] = {
 	AR8327_LED_INFO(PHY0_0, HW, "wd:green:lan1"),
 	AR8327_LED_INFO(PHY1_0, HW, "wd:green:lan2"),
 	AR8327_LED_INFO(PHY2_0, HW, "wd:green:lan3"),
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c
@ -23,6 +23,7 @@
 #include <linux/spi/flash.h>
 #include <linux/routerboot.h>
 #include <linux/gpio.h>
+#include <linux/version.h>

 #include <asm/prom.h>
 #include <asm/mach-ath79/ath79.h>
@ -124,7 +125,7 @@ static struct ar8327_led_cfg rb2011_ar8327_led_cfg = {
 	.open_drain = false,
 };

-static const struct ar8327_led_info rb2011_ar8327_leds[] __initconst = {
+static const struct ar8327_led_info rb2011_ar8327_leds[] = {
 	AR8327_LED_INFO(PHY0_0, HW, "rb:green:eth1"),
 	AR8327_LED_INFO(PHY1_0, HW, "rb:green:eth2"),
 	AR8327_LED_INFO(PHY2_0, HW, "rb:green:eth3"),
@ -188,6 +189,7 @@ static void rb2011_nand_select_chip(int chip_no)
 	ndelay(500);
 }

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 static struct nand_ecclayout rb2011_nand_ecclayout = {
 	.eccbytes	= 6,
 	.eccpos		= { 8, 9, 10, 13, 14, 15 },
@ -195,16 +197,72 @@ static struct nand_ecclayout rb2011_nand_ecclayout = {
 	.oobfree	= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
 };

+#else
+
+static int rb2011_ooblayout_ecc(struct mtd_info *mtd, int section,
+				struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int rb2011_ooblayout_free(struct mtd_info *mtd, int section,
+				 struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 4;
+		return 0;
+	case 1:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 2:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 3:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops rb2011_nand_ecclayout_ops = {
+	.ecc = rb2011_ooblayout_ecc,
+	.free = rb2011_ooblayout_free,
+};
+#endif /* < 4.6 */
+
 static int rb2011_nand_scan_fixup(struct mtd_info *mtd)
 {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 	struct nand_chip *chip = mtd->priv;
+#endif

 	if (mtd->writesize == 512) {
 		/*
 		 * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot
 		 * will not be able to find the kernel that we load.
 		 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 		chip->ecc.layout = &rb2011_nand_ecclayout;
+#else
+		mtd_set_ooblayout(mtd, &rb2011_nand_ecclayout_ops);
+#endif
 	}

 	return 0;
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb91x.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb91x.c
@ -140,7 +140,7 @@ static struct rb91x_nand_platform_data rb711gr100_nand_data __initdata = {
 	.gpio_nle = RB91X_GPIO_NLE,
 };

-static u8 rb711gr100_ssr_initdata[] __initdata = {
+static u8 rb711gr100_ssr_initdata[] = {
 	BIT(RB91X_SSR_BIT_PCIE_POWER) |
 	BIT(RB91X_SSR_BIT_USB_POWER) |
 	BIT(RB91X_SSR_BIT_5)
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c
@ -20,6 +20,7 @@
 #include <linux/routerboot.h>
 #include <linux/gpio.h>
 #include <linux/platform_data/phy-at803x.h>
+#include <linux/version.h>

 #include <asm/prom.h>
 #include <asm/mach-ath79/ath79.h>
@ -132,6 +133,7 @@ static void rb922gs_nand_select_chip(int chip_no)
 	ndelay(500);
 }

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 static struct nand_ecclayout rb922gs_nand_ecclayout = {
 	.eccbytes	= 6,
 	.eccpos		= { 8, 9, 10, 13, 14, 15 },
@ -139,16 +141,72 @@ static struct nand_ecclayout rb922gs_nand_ecclayout = {
 	.oobfree	= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
 };

+#else
+
+static int rb922gs_ooblayout_ecc(struct mtd_info *mtd, int section,
+				 struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int rb922gs_ooblayout_free(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 4;
+		return 0;
+	case 1:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 2:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 3:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops rb922gs_nand_ecclayout_ops = {
+	.ecc = rb922gs_ooblayout_ecc,
+	.free = rb922gs_ooblayout_free,
+};
+#endif /* < 4.6 */
+
 static int rb922gs_nand_scan_fixup(struct mtd_info *mtd)
 {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 	struct nand_chip *chip = mtd->priv;
+#endif

 	if (mtd->writesize == 512) {
 		/*
 		 * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot
 		 * will not be able to find the kernel that we load.
 		 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 		chip->ecc.layout = &rb922gs_nand_ecclayout;
+#else
+		mtd_set_ooblayout(mtd, &rb922gs_nand_ecclayout_ops);
+#endif
 	}

 	return 0;
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
@ -24,6 +24,7 @@
 #include <linux/spi/flash.h>
 #include <linux/routerboot.h>
 #include <linux/gpio.h>
+#include <linux/version.h>

 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
@ -146,6 +147,7 @@ static void rb95x_nand_select_chip(int chip_no)
 	ndelay(500);
 }

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 static struct nand_ecclayout rb95x_nand_ecclayout = {
 	.eccbytes	= 6,
 	.eccpos		= { 8, 9, 10, 13, 14, 15 },
@ -153,6 +155,56 @@ static struct nand_ecclayout rb95x_nand_ecclayout = {
 	.oobfree	= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
 };

+#else
+
+static int rb95x_ooblayout_ecc(struct mtd_info *mtd, int section,
+			       struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int rb95x_ooblayout_free(struct mtd_info *mtd, int section,
+				struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 4;
+		return 0;
+	case 1:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 2:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 3:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops rb95x_nand_ecclayout_ops = {
+	.ecc = rb95x_ooblayout_ecc,
+	.free = rb95x_ooblayout_free,
+};
+#endif /* < 4.6 */
+
 static int rb95x_nand_scan_fixup(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
@ -162,7 +214,11 @@ static int rb95x_nand_scan_fixup(struct mtd_info *mtd)
 		 * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot
 		 * will not be able to find the kernel that we load.
 		 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 		chip->ecc.layout = &rb95x_nand_ecclayout;
+#else
+		mtd_set_ooblayout(mtd, &rb95x_nand_ecclayout_ops);
+#endif
 	}

 	chip->options = NAND_NO_SUBPAGE_WRITE;
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
@ -267,7 +267,7 @@ static struct gpio_led rb962_leds_gpio[] __initdata = {
 	},
 };

-static const struct ar8327_led_info rb962_leds_ar8327[] __initconst = {
+static const struct ar8327_led_info rb962_leds_ar8327[] = {
 		AR8327_LED_INFO(PHY0_0, HW, "rb:green:port1"),
 		AR8327_LED_INFO(PHY1_0, HW, "rb:green:port2"),
 		AR8327_LED_INFO(PHY2_0, HW, "rb:green:port3"),
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbsxtlite.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbsxtlite.c
@ -24,6 +24,7 @@
 #include <linux/rle.h>
 #include <linux/routerboot.h>
 #include <linux/gpio.h>
+#include <linux/version.h>

 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
@ -163,6 +164,7 @@ static void rbsxtlite_nand_select_chip(int chip_no)
 	ndelay(500);
 }

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 static struct nand_ecclayout rbsxtlite_nand_ecclayout = {
 	.eccbytes	= 6,
 	.eccpos	 = { 8, 9, 10, 13, 14, 15 },
@ -170,16 +172,72 @@ static struct nand_ecclayout rbsxtlite_nand_ecclayout = {
 	.oobfree	= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
 };

+#else
+
+static int rbsxtlite_ooblayout_ecc(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int rbsxtlite_ooblayout_free(struct mtd_info *mtd, int section,
+				    struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 4;
+		return 0;
+	case 1:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 2:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 3:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops rbsxtlite_nand_ecclayout_ops = {
+	.ecc = rbsxtlite_ooblayout_ecc,
+	.free = rbsxtlite_ooblayout_free,
+};
+#endif /* < 4.6 */
+
 static int rbsxtlite_nand_scan_fixup(struct mtd_info *mtd)
 {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 	struct nand_chip *chip = mtd->priv;
+#endif

 	if (mtd->writesize == 512) {
 		/*
 		* Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot
 		* will not be able to find the kernel that we load.
 		*/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 		chip->ecc.layout = &rbsxtlite_nand_ecclayout;
+#else
+		mtd_set_ooblayout(mtd, &rbsxtlite_nand_ecclayout_ops);
+#endif
 	}

 	return 0;
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c
@ -107,7 +107,7 @@ static struct gpio_keys_button wdr4300_gpio_keys[] __initdata = {
 	},
 };

-static const struct ar8327_led_info wdr4300_leds_ar8327[] __initconst = {
+static const struct ar8327_led_info wdr4300_leds_ar8327[] = {
 	AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"),
 	AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"),
 	AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"),
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v4.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v4.c
@ -57,7 +57,7 @@
 #define TL_WR1043_V4_KEYS_POLL_INTERVAL		20 /* msecs */
 #define TL_WR1043_V4_KEYS_DEBOUNCE_INTERVAL	(3 * TL_WR1043_V4_KEYS_POLL_INTERVAL)

-#define TL_WR1043_V4_MAC_LOCATION		0x1ff80174
+#define TL_WR1043_V4_MAC_LOCATION		0x1ff50008

 #define TL_WR1043_V4_EEPROM_ADDR		0x1fff0000
 #define TL_WR1043_V4_WMAC_CALDATA_OFFSET	0x1000
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr942n-v1.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr942n-v1.c
@ -148,7 +148,7 @@ static struct spi_gpio_platform_data tl_wr942n_v1_spi_data = {
 	.num_chipselect	= 1,
 };

-static u8 tl_wr942n_v1_ssr_initdata[] __initdata = {
+static u8 tl_wr942n_v1_ssr_initdata[] = {
 	BIT(TL_WR942N_V1_SSR_BIT_7) |
 	BIT(TL_WR942N_V1_SSR_BIT_6) |
 	BIT(TL_WR942N_V1_SSR_BIT_5) |
--- a/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c
+++ b/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c
@ -168,7 +168,11 @@ static int nxp_74hc153_probe(struct platform_device *pdev)
 	gc->base = pdata->gpio_base;
 	gc->ngpio = NXP_74HC153_NUM_GPIOS;
 	gc->label = dev_name(nxp->parent);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 	gc->dev = nxp->parent;
+#else
+	gc->parent = nxp->parent;
+#endif
 	gc->owner = THIS_MODULE;

 	err = gpiochip_add(&nxp->gpio_chip);
--- a/target/linux/ar71xx/files/drivers/leds/leds-nu801.c
+++ b/target/linux/ar71xx/files/drivers/leds/leds-nu801.c
@ -98,7 +98,7 @@ static void led_nu801_set(struct led_classdev *led_cdev,
 	}
 }

-static int __init led_nu801_create(struct led_nu801_data *controller,
+static int led_nu801_create(struct led_nu801_data *controller,
 				    struct device *parent,
 				    int index,
 				    enum led_brightness brightness,
@ -131,7 +131,7 @@ err:
 	return ret;
 }

-static int __init
+static int
 led_nu801_create_chain(const struct led_nu801_template *template,
 			struct led_nu801_data *controller,
 			struct device *parent)
@ -237,7 +237,7 @@ static void led_nu801_delete_chain(struct led_nu801_data *controller)
 	kfree(led_chain);
 }

-static struct led_nu801_data * __init
+static struct led_nu801_data *
 leds_nu801_create_of(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node, *child;
@ -307,7 +307,7 @@ err:
 	return NULL;
 }

-static int __init led_nu801_probe(struct platform_device *pdev)
+static int led_nu801_probe(struct platform_device *pdev)
 {
 	struct led_nu801_platform_data *pdata = pdev->dev.platform_data;
 	struct led_nu801_data *controllers;
--- a/target/linux/ar71xx/files/drivers/mtd/cybertan_part.c
+++ b/target/linux/ar71xx/files/drivers/mtd/cybertan_part.c
@ -28,6 +28,7 @@

 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/version.h>

 struct cybertan_header {
 	char	magic[4];
@ -82,7 +83,11 @@ struct firmware_header {
 #define NVRAM_LEN	0x10000

 static int cybertan_parse_partitions(struct mtd_info *master,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 				     struct mtd_partition **pparts,
+#else
+				     const struct mtd_partition **pparts,
+#endif
 				     struct mtd_part_parser_data *data)
 {
 	struct firmware_header *header;
--- a/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c
+++ b/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c
@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/version.h>

 #include <linux/platform/ar934x_nfc.h>

@ -187,7 +188,9 @@ nfc_debug_data(const char *label, void *data, int len) {}
 #endif /* AR934X_NFC_DEBUG_DATA */

 struct ar934x_nfc {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 	struct mtd_info mtd;
+#endif
 	struct nand_chip nand_chip;
 	struct device *parent;
 	void __iomem *base;
@ -259,7 +262,22 @@ ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc)
 static inline struct
 ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
 {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 	return container_of(mtd, struct ar934x_nfc, mtd);
+#else
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	return container_of(chip, struct ar934x_nfc, nand_chip);
+#endif
+}
+
+static struct mtd_info *ar934x_nfc_to_mtd(struct ar934x_nfc *nfc)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
+	return &nfc->mtd;
+#else
+	return nand_to_mtd(&nfc->nand_chip);
+#endif
 }

 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
@ -648,7 +666,7 @@ ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
 		   int page_addr)
 {
 	struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
-	struct nand_chip *nand = mtd->priv;
+	struct nand_chip *nand = &nfc->nand_chip;

 	nfc->read_id = false;
 	if (command != NAND_CMD_PAGEPROG)
@ -1241,6 +1259,7 @@ ar934x_nfc_init_tail(struct mtd_info *mtd)
 	return err;
 }

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 static struct nand_ecclayout ar934x_nfc_oob_64_hwecc = {
 	.eccbytes = 28,
 	.eccpos = {
@ -1261,19 +1280,60 @@ static struct nand_ecclayout ar934x_nfc_oob_64_hwecc = {
 	},
 };

+#else
+
+static int ar934x_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
+				    struct mtd_oob_region *oobregion)
+{
+	if (section)
+		return -ERANGE;
+
+	oobregion->offset = 20;
+	oobregion->length = 28;
+
+	return 0;
+}
+
+static int ar934x_nfc_ooblayout_free(struct mtd_info *mtd, int section,
+				     struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 4;
+		oobregion->length = 16;
+		return 0;
+	case 1:
+		oobregion->offset = 48;
+		oobregion->length = 16;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops ar934x_nfc_ecclayout_ops = {
+	.ecc = ar934x_nfc_ooblayout_ecc,
+	.free = ar934x_nfc_ooblayout_free,
+};
+#endif /* < 4.6 */
+
 static int
 ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)
 {
 	struct nand_chip *nand = &nfc->nand_chip;
+	struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
 	u32 ecc_cap;
 	u32 ecc_thres;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+	struct mtd_oob_region oobregion;
+#endif

-	if (!config_enabled(CONFIG_MTD_NAND_AR934X_HW_ECC)) {
+	if (!IS_ENABLED(CONFIG_MTD_NAND_AR934X_HW_ECC)) {
 		dev_err(nfc->parent, "hardware ECC support is disabled\n");
 		return -EINVAL;
 	}

-	switch (nfc->mtd.writesize) {
+	switch (mtd->writesize) {
 	case 2048:
 		/*
 		 * Writing a subpage separately is not supported, because
@ -1284,17 +1344,25 @@ ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)
 		nand->ecc.size = 512;
 		nand->ecc.bytes = 7;
 		nand->ecc.strength = 4;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 		nand->ecc.layout = &ar934x_nfc_oob_64_hwecc;
+#else
+		mtd_set_ooblayout(mtd, &ar934x_nfc_ecclayout_ops);
+#endif
 		break;

 	default:
 		dev_err(nfc->parent,
 			"hardware ECC is not available for %d byte pages\n",
-			nfc->mtd.writesize);
+			mtd->writesize);
 		return -EINVAL;
 	}

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 	BUG_ON(!nand->ecc.layout);
+#else
+	BUG_ON(!mtd->ooblayout->ecc);
+#endif

 	switch (nand->ecc.strength) {
 	case 4:
@ -1309,12 +1377,17 @@ ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)
 	}

 	nfc->ecc_thres = ecc_thres;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 	nfc->ecc_oob_pos = nand->ecc.layout->eccpos[0];
+#else
+	mtd->ooblayout->ecc(mtd, 0, &oobregion);
+	nfc->ecc_oob_pos = oobregion.offset;
+#endif

 	nfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S;
 	nfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S;

-	nfc->ecc_offset_reg = nfc->mtd.writesize + nfc->ecc_oob_pos;
+	nfc->ecc_offset_reg = mtd->writesize + nfc->ecc_oob_pos;

 	nand->ecc.mode = NAND_ECC_HW;
 	nand->ecc.read_page = ar934x_nfc_read_page;
@ -1382,9 +1455,11 @@ ar934x_nfc_probe(struct platform_device *pdev)
 	nfc->swap_dma = pdata->swap_dma;

 	nand = &nfc->nand_chip;
-	mtd = &nfc->mtd;
+	mtd = ar934x_nfc_to_mtd(nfc);

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 	mtd->priv = nand;
+#endif
 	mtd->owner = THIS_MODULE;
 	if (pdata->name)
 		mtd->name = pdata->name;
@ -1429,10 +1504,18 @@ ar934x_nfc_probe(struct platform_device *pdev)
 	switch (pdata->ecc_mode) {
 	case AR934X_NFC_ECC_SOFT:
 		nand->ecc.mode = NAND_ECC_SOFT;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+		nand->ecc.algo = NAND_ECC_HAMMING;
+#endif
 		break;

 	case AR934X_NFC_ECC_SOFT_BCH:
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 		nand->ecc.mode = NAND_ECC_SOFT_BCH;
+#else
+		nand->ecc.mode = NAND_ECC_SOFT;
+		nand->ecc.algo = NAND_ECC_BCH;
+#endif
 		break;

 	case AR934X_NFC_ECC_HW:
@ -1474,10 +1557,12 @@ static int
 ar934x_nfc_remove(struct platform_device *pdev)
 {
 	struct ar934x_nfc *nfc;
+	struct mtd_info *mtd;

 	nfc = platform_get_drvdata(pdev);
 	if (nfc) {
-		nand_release(&nfc->mtd);
+		mtd = ar934x_nfc_to_mtd(nfc);
+		nand_release(mtd);
 		ar934x_nfc_free_buf(nfc);
 		free_irq(nfc->irq, nfc);
 	}
--- a/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c
+++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c
@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/slab.h>
+#include <linux/version.h>

 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/rb4xx_cpld.h>
@ -41,6 +42,7 @@ struct rb4xx_nand_info {
 	struct mtd_info		mtd;
 };

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 /*
 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
 * will not be able to find the kernel that we load.
@ -52,6 +54,56 @@ static struct nand_ecclayout rb4xx_nand_ecclayout = {
 	.oobfree	= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
 };

+#else
+
+static int rb4xx_ooblayout_ecc(struct mtd_info *mtd, int section,
+			       struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int rb4xx_ooblayout_free(struct mtd_info *mtd, int section,
+				struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 4;
+		return 0;
+	case 1:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 2:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 3:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops rb4xx_nand_ecclayout_ops = {
+	.ecc = rb4xx_ooblayout_ecc,
+	.free = rb4xx_ooblayout_free,
+};
+#endif /* < 4.6 */
+
 static struct mtd_partition rb4xx_nand_partitions[] = {
 	{
 		.name	= "booter",
@ -229,7 +281,11 @@ static int rb4xx_nand_probe(struct platform_device *pdev)
 	}

 	if (info->mtd.writesize == 512)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 		info->chip.ecc.layout = &rb4xx_nand_ecclayout;
+#else
+		mtd_set_ooblayout(&info->mtd, &rb4xx_nand_ecclayout_ops);
+#endif

 	ret = nand_scan_tail(&info->mtd);
 	if (ret) {
--- a/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c
+++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c
@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/version.h>

 #include <asm/mach-ath79/ar71xx_regs.h>
 #include <asm/mach-ath79/ath79.h>
@ -49,6 +50,7 @@ static inline struct rb750_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
 	return container_of(mtd, struct rb750_nand_info, mtd);
 }

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 /*
 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
 * will not be able to find the kernel that we load.
@ -60,6 +62,56 @@ static struct nand_ecclayout rb750_nand_ecclayout = {
 	.oobfree	= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
 };

+#else
+
+static int rb750_ooblayout_ecc(struct mtd_info *mtd, int section,
+			       struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int rb750_ooblayout_free(struct mtd_info *mtd, int section,
+				struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 4;
+		return 0;
+	case 1:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 2:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 3:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops rb750_nand_ecclayout_ops = {
+	.ecc = rb750_ooblayout_ecc,
+	.free = rb750_ooblayout_free,
+};
+#endif /* < 4.6 */
+
 static struct mtd_partition rb750_nand_partitions[] = {
 	{
 		.name	= "booter",
@ -292,7 +344,11 @@ static int rb750_nand_probe(struct platform_device *pdev)
 	}

 	if (info->mtd.writesize == 512)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 		info->chip.ecc.layout = &rb750_nand_ecclayout;
+#else
+		mtd_set_ooblayout(&info->mtd, &rb750_nand_ecclayout_ops);
+#endif

 	ret = nand_scan_tail(&info->mtd);
 	if (ret) {
--- a/target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c
+++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c
@ -19,6 +19,7 @@
 #include <linux/slab.h>
 #include <linux/gpio.h>
 #include <linux/platform_data/rb91x_nand.h>
+#include <linux/version.h>

 #include <asm/mach-ath79/ar71xx_regs.h>
 #include <asm/mach-ath79/ath79.h>
@ -56,6 +57,7 @@ static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
 	return container_of(mtd, struct rb91x_nand_info, mtd);
 }

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 /*
 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
 * will not be able to find the kernel that we load.
@ -67,6 +69,56 @@ static struct nand_ecclayout rb91x_nand_ecclayout = {
 	.oobfree	= { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
 };

+#else
+
+static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
+			       struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
+				struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 4;
+		return 0;
+	case 1:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 2:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 3:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
+	.ecc = rb91x_ooblayout_ecc,
+	.free = rb91x_ooblayout_free,
+};
+#endif /* < 4.6 */
+
 static struct mtd_partition rb91x_nand_partitions[] = {
 	{
 		.name	= "booter",
@ -334,7 +386,11 @@ static int rb91x_nand_probe(struct platform_device *pdev)
 		return ret;

 	if (rbni->mtd.writesize == 512)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 		rbni->chip.ecc.layout = &rb91x_nand_ecclayout;
+#else
+		mtd_set_ooblayout(&rbni->mtd, &rb91x_nand_ecclayout_ops);
+#endif

 	ret = nand_scan_tail(&rbni->mtd);
 	if (ret)
--- a/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c
+++ b/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c
@ -15,6 +15,7 @@

 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/version.h>

 #define TPLINK_NUM_PARTS	5
 #define TPLINK_HEADER_V1	0x01000000
@ -109,7 +110,11 @@ static int tplink_check_rootfs_magic(struct mtd_info *mtd, size_t offset)
 }

 static int tplink_parse_partitions_offset(struct mtd_info *master,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 				   struct mtd_partition **pparts,
+#else
+				   const struct mtd_partition **pparts,
+#endif
 				   struct mtd_part_parser_data *data,
 				   size_t offset)
 {
@ -181,7 +186,11 @@ err:
 }

 static int tplink_parse_partitions(struct mtd_info *master,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 				   struct mtd_partition **pparts,
+#else
+				   const struct mtd_partition **pparts,
+#endif
 				   struct mtd_part_parser_data *data)
 {
 	return tplink_parse_partitions_offset(master, pparts, data,
@ -189,7 +198,11 @@ static int tplink_parse_partitions(struct mtd_info *master,
 }

 static int tplink_parse_64k_partitions(struct mtd_info *master,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 				   struct mtd_partition **pparts,
+#else
+				   const struct mtd_partition **pparts,
+#endif
 				   struct mtd_part_parser_data *data)
 {
 	return tplink_parse_partitions_offset(master, pparts, data,
--- a/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c
+++ b/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c
@ -17,6 +17,7 @@
 #include <linux/netdevice.h>
 #include <linux/phy.h>
 #include <net/dsa.h>
+#include <linux/version.h>

 #define REG_BASE		0x10
 #define REG_PHY(p)		(REG_BASE + (p))
@ -26,11 +27,12 @@

 static int reg_read(struct dsa_switch *ds, int addr, int reg)
 {
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
-	return mdiobus_read(ds->master_mii_bus, addr, reg);
-#else
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
 	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
 	return mdiobus_read(bus, addr, reg);
+#else
+	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->dev);
+	return mdiobus_read(bus, addr, reg);
 #endif
 }

@ -47,14 +49,22 @@ static int reg_read(struct dsa_switch *ds, int addr, int reg)

 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
 {
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
-	return mdiobus_write(ds->master_mii_bus, addr, reg, val);
-#else
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
 	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
 	return mdiobus_write(bus, addr, reg, val);
+#else
+	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->dev);
+	return mdiobus_write(bus, addr, reg, val);
 #endif
 }

+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,8,0)
+static enum dsa_tag_protocol mv88e6063_get_tag_protocol(struct dsa_switch *ds)
+{
+	return DSA_TAG_PROTO_TRAILER;
+}
+#endif
+
 #define REG_WRITE(addr, reg, val)				\
 	({							\
 		int __ret;					\
@ -64,16 +74,20 @@ static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
 			return __ret;				\
 	})

-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
-static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr)
-{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
+static char *mv88e6063_drv_probe(struct device *host_dev, int sw_addr)
 #else
-static char *mv88e6063_probe(struct device *host_dev, int sw_addr)
+static const char *mv88e6063_drv_probe(struct device *dsa_dev,
+				       struct device *host_dev, int sw_addr,
+				       void **_priv)
+#endif
 {
 	struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
-#endif
 	int ret;

+	if (!bus)
+		return NULL;
+
 	ret = mdiobus_read(bus, REG_PORT(0), 0x03);
 	if (ret >= 0) {
 		ret &= 0xfff0;
@ -163,7 +177,11 @@ static int mv88e6063_setup_port(struct dsa_switch *ds, int p)
 	REG_WRITE(addr, 0x06,
 			((p & 0xf) << 12) |
 			 (dsa_is_cpu_port(ds, p) ?
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
 				ds->phys_port_mask :
+#else
+				ds->enabled_port_mask :
+#endif
 				(1 << ds->dst->cpu_port)));

 	/*
@ -240,72 +258,32 @@ mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
 	return reg_write(ds, addr, regnum, val);
 }

-static void mv88e6063_poll_link(struct dsa_switch *ds)
-{
-	int i;
-
-	for (i = 0; i < DSA_MAX_PORTS; i++) {
-		struct net_device *dev;
-		int uninitialized_var(port_status);
-		int link;
-		int speed;
-		int duplex;
-		int fc;
-
-		dev = ds->ports[i];
-		if (dev == NULL)
-			continue;
-
-		link = 0;
-		if (dev->flags & IFF_UP) {
-			port_status = reg_read(ds, REG_PORT(i), 0x00);
-			if (port_status < 0)
-				continue;
-
-			link = !!(port_status & 0x1000);
-		}
-
-		if (!link) {
-			if (netif_carrier_ok(dev)) {
-				printk(KERN_INFO "%s: link down\n", dev->name);
-				netif_carrier_off(dev);
-			}
-			continue;
-		}
-
-		speed = (port_status & 0x0100) ? 100 : 10;
-		duplex = (port_status & 0x0200) ? 1 : 0;
-		fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
-
-		if (!netif_carrier_ok(dev)) {
-			printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
-					 "flow control %sabled\n", dev->name,
-					 speed, duplex ? "full" : "half",
-					 fc ? "en" : "dis");
-			netif_carrier_on(dev);
-		}
-	}
-}
-
-static struct dsa_switch_driver mv88e6063_switch_driver = {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)
+static struct dsa_switch_driver mv88e6063_switch_ops = {
+#else
+static struct dsa_switch_ops mv88e6063_switch_ops = {
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0)
 	.tag_protocol	= htons(ETH_P_TRAILER),
-	.probe		= mv88e6063_probe,
+#else
+	.get_tag_protocol = mv88e6063_get_tag_protocol,
+#endif
+	.probe		= mv88e6063_drv_probe,
 	.setup		= mv88e6063_setup,
 	.set_addr	= mv88e6063_set_addr,
 	.phy_read	= mv88e6063_phy_read,
 	.phy_write	= mv88e6063_phy_write,
-	.poll_link	= mv88e6063_poll_link,
 };

 static int __init mv88e6063_init(void)
 {
-	register_switch_driver(&mv88e6063_switch_driver);
+	register_switch_driver(&mv88e6063_switch_ops);
 	return 0;
 }
 module_init(mv88e6063_init);

 static void __exit mv88e6063_cleanup(void)
 {
-	unregister_switch_driver(&mv88e6063_switch_driver);
+	unregister_switch_driver(&mv88e6063_switch_ops);
 }
 module_exit(mv88e6063_cleanup);
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@ -1089,7 +1089,7 @@ next:

 	while ((skb = __skb_dequeue(&queue)) != NULL) {
 		skb->protocol = eth_type_trans(skb, dev);
-		netif_receive_skb(skb);
+		napi_gro_receive(&ag->napi, skb);
 	}

 	DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
@ -1141,7 +1141,7 @@ static int ag71xx_poll(struct napi_struct *napi, int limit)
 		DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
 			dev->name, rx_done, tx_done, limit);

-		napi_complete(napi);
+		napi_complete_done(napi, rx_done);

 		/* enable interrupts */
 		spin_lock_irqsave(&ag->lock, flags);
@ -1160,7 +1160,7 @@ oom:
 		pr_info("%s: out of memory\n", dev->name);

 	mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
-	napi_complete(napi);
+	napi_complete_done(napi, rx_done);
 	return 0;
 }

--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c
@ -254,7 +254,11 @@ static int ag71xx_mdio_probe(struct platform_device *pdev)
 	am->mii_bus->read = ag71xx_mdio_read;
 	am->mii_bus->write = ag71xx_mdio_write;
 	am->mii_bus->reset = ag71xx_mdio_reset;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 	am->mii_bus->irq = am->mii_irq;
+#else
+	memcpy(am->mii_bus->irq, am->mii_irq, sizeof(am->mii_bus->irq));
+#endif
 	am->mii_bus->priv = am;
 	am->mii_bus->parent = &pdev->dev;
 	snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
@ -112,6 +112,7 @@ static int ag71xx_phy_connect_multi(struct ag71xx *ag)
 		if (!(pdata->phy_mask & (1 << phy_addr)))
 			continue;

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 		if (ag->mii_bus->phy_map[phy_addr] == NULL)
 			continue;

@ -122,6 +123,18 @@ static int ag71xx_phy_connect_multi(struct ag71xx *ag)

 		if (phydev == NULL)
 			phydev = ag->mii_bus->phy_map[phy_addr];
+#else
+		if (ag->mii_bus->mdio_map[phy_addr] == NULL)
+			continue;
+
+		DBG("%s: PHY found at %s, uid=%08x\n",
+			dev_name(dev),
+			dev_name(&ag->mii_bus->mdio_map[phy_addr]->dev),
+			ag->mii_bus->mdio_map[phy_addr]->phy_id);
+
+		if (phydev == NULL)
+			phydev = mdiobus_get_phy(ag->mii_bus, phy_addr);
+#endif
 	}

 	if (!phydev) {
@ -130,13 +143,21 @@ static int ag71xx_phy_connect_multi(struct ag71xx *ag)
 		return -ENODEV;
 	}

+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 	ag->phy_dev = phy_connect(ag->dev, dev_name(&phydev->dev),
+#else
+	ag->phy_dev = phy_connect(ag->dev, phydev_name(phydev),
+#endif
 				  &ag71xx_phy_link_adjust,
 				  pdata->phy_if_mode);

 	if (IS_ERR(ag->phy_dev)) {
 		dev_err(dev, "could not connect to PHY at %s\n",
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 			   dev_name(&phydev->dev));
+#else
+			   phydev_name(phydev));
+#endif
 		return PTR_ERR(ag->phy_dev);
 	}

@ -149,7 +170,12 @@ static int ag71xx_phy_connect_multi(struct ag71xx *ag)
 	phydev->advertising = phydev->supported;

 	dev_info(dev, "connected to PHY at %s [uid=%08x, driver=%s]\n",
-		    dev_name(&phydev->dev), phydev->phy_id, phydev->drv->name);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
+		    dev_name(&phydev->dev),
+#else
+		    phydev_name(phydev),
+#endif
+		    phydev->phy_id, phydev->drv->name);

 	ag->link = 0;
 	ag->speed = 0;
--- a/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c
+++ b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c
@ -21,6 +21,7 @@
 #include <linux/spi/spi.h>
 #include <linux/gpio.h>
 #include <linux/slab.h>
+#include <linux/version.h>

 #include <asm/mach-ath79/rb4xx_cpld.h>

@ -246,7 +247,11 @@ static int rb4xx_cpld_gpio_init(struct rb4xx_cpld *cpld, unsigned int base)
 	cpld->chip.base = base;
 	cpld->chip.ngpio = CPLD_NUM_GPIOS;
 	cpld->chip.can_sleep = 1;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 	cpld->chip.dev = &cpld->spi->dev;
+#else
+	cpld->chip.parent = &cpld->spi->dev;
+#endif
 	cpld->chip.owner = THIS_MODULE;

 	err = gpiochip_add(&cpld->chip);
--- a/target/linux/ar71xx/generic/config-default
+++ b/target/linux/ar71xx/generic/config-default
@ -1 +0,0 @@
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd"
--- a/target/linux/ar71xx/image/generic.mk
+++ b/target/linux/ar71xx/image/generic.mk
@ -229,6 +229,26 @@ define Device/dragino2
 endef
 TARGET_DEVICES += dragino2

+define Device/ew-dorin
+  DEVICE_TITLE := Embedded Wireless Dorin Platform
+  DEVICE_PACKAGES := kmod-usb-core kmod-usb-chipidea 
+  BOARDNAME = EW-DORIN
+  CONSOLE := ttyATH0,115200
+  IMAGE_SIZE = 16000k
+  MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env),16000k(firmware),64k(art)ro
+endef
+TARGET_DEVICES += ew-dorin
+
+define Device/ew-dorin-router
+  DEVICE_TITLE := Embedded Wireless Dorin Router Platform
+  DEVICE_PACKAGES := kmod-usb-core kmod-usb-chipidea 
+  BOARDNAME = EW-DORIN-ROUTER
+  CONSOLE := ttyATH0,115200
+  IMAGE_SIZE = 16000k
+  MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env),16000k(firmware),64k(art)ro
+endef
+TARGET_DEVICES += ew-dorin-router
+
 define Device/weio
  DEVICE_TITLE := WeIO
  DEVICE_PACKAGES := kmod-usb-core kmod-usb2
--- a/target/linux/ar71xx/image/legacy-devices.mk
+++ b/target/linux/ar71xx/image/legacy-devices.mk
@ -132,24 +132,6 @@ define LegacyDevice/DB120
 endef
 LEGACY_DEVICES += DB120

-define LegacyDevice/EWDORINAP
-  DEVICE_TITLE := Embedded Wireless Dorin Platform (4MB flash)
-  DEVICE_PACKAGES := kmod-usb-core kmod-usb2 kmod-usb-ledtrig-usbport kmod-usb-storage
-endef
-LEGACY_DEVICES += EWDORINAP
-
-define LegacyDevice/EWDORINRT
-  DEVICE_TITLE := Embedded Wireless Dorin Router
-  DEVICE_PACKAGES := kmod-usb-core kmod-usb2 kmod-usb-ledtrig-usbport kmod-usb-storage
-endef
-LEGACY_DEVICES += EWDORINRT
-
-define LegacyDevice/EWDORIN16M
-  DEVICE_TITLE := Embedded Wireless Dorin Platform (16MB flash)
-  DEVICE_PACKAGES := kmod-usb-core kmod-usb2 kmod-usb-ledtrig-usbport kmod-usb-storage
-endef
-LEGACY_DEVICES += EWDORIN16M
-
 define LegacyDevice/HORNETUBx2
  DEVICE_TITLE := ALFA Network Hornet-UB-x2 board (16MB flash, 64MB ram)
  DEVICE_PACKAGES := kmod-usb-core kmod-usb2 kmod-usb-ledtrig-usbport
--- a/target/linux/ar71xx/image/legacy.mk
+++ b/target/linux/ar71xx/image/legacy.mk
@ -258,8 +258,6 @@ cameo_ap94_mtdlayout_fat=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,7808k(firmw
 esr900_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),13248k(rootfs),1024k(manufacture)ro,64k(backup)ro,320k(storage)ro,64k(caldata)ro,14656k@0x40000(firmware)
 esr1750_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),13248k(rootfs),1024k(manufacture)ro,64k(backup)ro,320k(storage)ro,64k(caldata)ro,14656k@0x40000(firmware)
 epg5000_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),13248k(rootfs),1024k(manufacture)ro,64k(backup)ro,320k(storage)ro,64k(caldata)ro,14656k@0x40000(firmware)
-ew-dorin_mtdlayout_4M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),3712k(firmware),64k(art)ro
-ew-dorin_mtdlayout_16M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),16000k(firmware),64k(art)ro
 f9k1115v2_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),14464k(rootfs),1408k(kernel),64k(nvram)ro,64k(envram)ro,64k(art)ro,15872k@0x50000(firmware)
 dlrtdev_mtdlayout=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,6208k(firmware),64k(caldata)ro,640k(certs),960k(unknown)ro,64k@0x7f0000(caldata_copy)
 dlrtdev_mtdlayout_fat=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,7168k(firmware),640k(certs),64k(caldata)ro,64k@0x660000(caldata_orig),6208k@0x50000(firmware_orig)
@ -897,9 +895,6 @@ $(eval $(call SingleProfile,AthLzma,64k,AP152_16M,ap152-16M,AP152,ttyS0,115200,$
 $(eval $(call SingleProfile,AthLzma,64k,BXU2000N2,bxu2000n-2-a1,BXU2000n-2-A1,ttyS0,115200,$$(bxu2000n2_mtdlayout),RKuImage))
 $(eval $(call SingleProfile,AthLzma,64k,CAP4200AG,cap4200ag,CAP4200AG,ttyS0,115200,$$(cap4200ag_mtdlayout),KRuImage))
 $(eval $(call SingleProfile,AthLzma,64k,DB120,db120,DB120,ttyS0,115200,$$(db120_mtdlayout),RKuImage))
-$(eval $(call SingleProfile,AthLzma,64k,EWDORINAP,ew-dorin,EW-DORIN,ttyATH0,115200,$$(ew-dorin_mtdlayout_4M),KRuImage,65536))
-$(eval $(call SingleProfile,AthLzma,64k,EWDORINRT,ew-dorin-router,EW-DORIN-ROUTER,ttyATH0,115200,$$(ew-dorin_mtdlayout_4M),KRuImage,65536))
-$(eval $(call SingleProfile,AthLzma,64k,EWDORIN16M,ew-dorin-16M,EW-DORIN,ttyATH0,115200,$$(ew-dorin_mtdlayout_16M),KRuImage,65536))
 $(eval $(call SingleProfile,AthLzma,64k,HORNETUBx2,hornet-ub-x2,HORNET-UB,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536))
 $(eval $(call SingleProfile,AthLzma,64k,TUBE2H16M,tube2h-16M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536))
 $(eval $(call SingleProfile,AthLzma,64k,WLR8100,wlr8100,WLR8100,ttyS0,115200,$$(wlr8100_mtdlayout),KRuImage))
--- a/target/linux/ar71xx/image/tp-link.mk
+++ b/target/linux/ar71xx/image/tp-link.mk
@ -76,7 +76,7 @@ define Device/tplink-8m
  IMAGE_SIZE := 7936k
 endef

-define Device/tplink-8mlzma
+define Device/tplink-4mlzma
  $(Device/tplink)
  TPLINK_FLASHLAYOUT := 4Mlzma
  IMAGE_SIZE := 3904k
@ -486,6 +486,7 @@ endef
 define Device/tl-wa850re-v1
  $(Device/tplink-8mlzma)
  DEVICE_TITLE := TP-LINK TL-WA850RE v1
+  DEVICE_PACKAGES := rssileds
  BOARDNAME := TL-WA850RE
  DEVICE_PROFILE := TLWA850
  TPLINK_HWID := 0x08500001
--- a/target/linux/ar71xx/mikrotik/config-default
+++ b/target/linux/ar71xx/mikrotik/config-default
@ -212,11 +212,10 @@ CONFIG_ATH79_MACH_RBSXTLITE=y
 # CONFIG_ATH79_MACH_ZCN_1523H is not set
 # CONFIG_ATH79_NVRAM is not set
 CONFIG_ATH79_ROUTERBOOT=y
-CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
 CONFIG_CRC16=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_GPIO_LATCH=y
-# CONFIG_LANTIQ_PHY is not set
+# CONFIG_INTEL_XWAY_PHY is not set
 CONFIG_LEDS_RB750=y
 CONFIG_LZO_DECOMPRESS=y
 # CONFIG_MTD_CFI is not set
--- a/target/linux/ar71xx/nand/config-default
+++ b/target/linux/ar71xx/nand/config-default
@ -209,12 +209,11 @@ CONFIG_ATH79_MACH_Z1=y
 # CONFIG_ATH79_MACH_ZBT_WE1526 is not set
 # CONFIG_ATH79_MACH_ZCN_1523H is not set
 CONFIG_BCH=y
-CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
 CONFIG_CRC16=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_LZO=y
+# CONFIG_INTEL_XWAY_PHY is not set
 # CONFIG_IP17XX_PHY is not set
-# CONFIG_LANTIQ_PHY is not set
 CONFIG_LEDS_NU801=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
--- a/target/linux/ar71xx/patches-4.4/902-at803x-add-reset-gpio-pdata.patch
+++ b/target/linux/ar71xx/patches-4.4/902-at803x-add-reset-gpio-pdata.patch
@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 	 */
 	if (phydev->state == PHY_NOLINK) {
 -		if (priv->gpiod_reset && !priv->phy_reset) {
-+		if ((priv->gpiod_reset || pdata->has_reset_gpio) &&
+		if ((priv->gpiod_reset || (pdata && pdata->has_reset_gpio)) &&
 +		    !priv->phy_reset) {
 			struct at803x_context context;
 
@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 -			msleep(1);
 -			gpiod_set_value(priv->gpiod_reset, 0);
 -			msleep(1);
-+			if (pdata->has_reset_gpio) {
+			if (pdata && pdata->has_reset_gpio) {
 +				gpio_set_value_cansleep(pdata->reset_gpio, 0);
 +				msleep(1);
 +				gpio_set_value_cansleep(pdata->reset_gpio, 1);
--- a/target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch
+++ b/target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch
@ -29,7 +29,7 @@
 
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
-@@ -170,6 +173,51 @@ static void __init ar913x_usb_setup(void
+@@ -170,6 +173,67 @@ static void __init ar913x_usb_setup(void
 			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 }
 
@ -46,22 +46,29 @@
 +	iounmap(usb_ctrl_base);
 +}
 +
-+static void __init ar933x_ci_usb_setup(void)
+static void __init ar9xxx_ci_usb_setup(void)
 +{
 +	struct ci_hdrc_platform_data ci_pdata;
 +	enum usb_dr_mode dr_mode;
-+	u32 bootstrap;
+	bool host_mode = true;
 +
-+	bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-+	if (bootstrap & AR933X_BOOTSTRAP_USB_MODE_HOST) {
+	if (soc_is_ar933x())
+		host_mode = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP) &
+			    AR933X_BOOTSTRAP_USB_MODE_HOST;
+	else if (soc_is_ar934x() || soc_is_qca955x())
+		host_mode = !(ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP) &
+			      AR934X_BOOTSTRAP_USB_MODE_DEVICE);
+
+	if (host_mode) {
 +		dr_mode = USB_DR_MODE_HOST;
 +	} else {
 +		dr_mode = USB_DR_MODE_PERIPHERAL;
-+		ar933x_usb_setup_ctrl_config();
+		if (soc_is_ar933x())
+			ar933x_usb_setup_ctrl_config();
 +	}
 +
 +	memset(&ci_pdata, 0, sizeof(ci_pdata));
-+	ci_pdata.name = "ci_hdrc_ar933x";
+	ci_pdata.name = "ci_hdrc_ar9xxx";
 +	ci_pdata.capoffset = DEF_CAPOFFSET;
 +	ci_pdata.dr_mode = dr_mode;
 +	ci_pdata.flags = CI_HDRC_DUAL_ROLE_NOT_OTG | CI_HDRC_DP_ALWAYS_PULLUP;
@ -76,17 +83,41 @@
 +			   AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
 +			   ATH79_CPU_IRQ(3),
 +			   &ci_pdata, sizeof(ci_pdata));
+
+	if (!host_mode)
+		return;
+
+	ath79_usb_register("ehci-platform", -1,
+			   AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
+			   ATH79_CPU_IRQ(3),
+			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+
 +}
 +
 static void __init ar933x_usb_setup(void)
 {
 	ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
-@@ -185,6 +233,8 @@ static void __init ar933x_usb_setup(void
- 			   AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
- 			   ATH79_CPU_IRQ(3),
- 			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-+
-+	ar933x_ci_usb_setup();
+@@ -181,10 +245,7 @@ static void __init ar933x_usb_setup(void
+ 	ath79_device_reset_clear(AR933X_RESET_USB_PHY);
+ 	mdelay(10);
+ 
+-	ath79_usb_register("ehci-platform", -1,
+-			   AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
+-			   ATH79_CPU_IRQ(3),
+-			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+	ar9xxx_ci_usb_setup();
 }
 
 static void enable_tx_tx_idp_violation_fix(unsigned base)
+@@ -230,10 +291,7 @@ static void __init ar934x_usb_setup(void
+ 	if (ath79_soc_rev >= 3)
+ 		ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier;
+ 
+-	ath79_usb_register("ehci-platform", -1,
+-			   AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
+-			   ATH79_CPU_IRQ(3),
+-			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+	ar9xxx_ci_usb_setup();
+ }
+ 
+ static void __init qca953x_usb_setup(void)
--- a/target/linux/ar71xx/patches-4.9/001-spi-cs-gpio.patch
+++ b/target/linux/ar71xx/patches-4.9/001-spi-cs-gpio.patch
@ -0,0 +1,20 @@
+--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+@@ -14,6 +14,7 @@
+ struct ath79_spi_platform_data {
+ 	unsigned	bus_num;
+ 	unsigned	num_chipselect;
+	int *cs_gpios;
+ };
+ 
+ #endif /* _ATH79_SPI_PLATFORM_H */
+--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
+@@ -231,6 +231,7 @@ static int ath79_spi_probe(struct platfo
+ 	if (pdata) {
+ 		master->bus_num = pdata->bus_num;
+ 		master->num_chipselect = pdata->num_chipselect;
+		master->cs_gpios = pdata->cs_gpios;
+ 	}
+ 
+ 	sp->bitbang.master = master;
--- a/target/linux/ar71xx/patches-4.9/002-add_back_gpio_function_select.patch
+++ b/target/linux/ar71xx/patches-4.9/002-add_back_gpio_function_select.patch
@ -0,0 +1,92 @@
+--- /dev/null
+++ b/arch/mips/ath79/gpio.c
+@@ -0,0 +1,59 @@
+/*
+ *  Atheros AR71XX/AR724X/AR913X GPIO API support
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+#include "common.h"
+
+void __iomem *ath79_gpio_base;
+EXPORT_SYMBOL_GPL(ath79_gpio_base);
+
+static void __iomem *ath79_gpio_get_function_reg(void)
+{
+	u32 reg = 0;
+
+	if (soc_is_ar71xx() ||
+	    soc_is_ar724x() ||
+	    soc_is_ar913x() ||
+	    soc_is_ar933x())
+		reg = AR71XX_GPIO_REG_FUNC;
+	else if (soc_is_ar934x())
+		reg = AR934X_GPIO_REG_FUNC;
+	else
+		BUG();
+
+	return ath79_gpio_base + reg;
+}
+
+void ath79_gpio_function_setup(u32 set, u32 clear)
+{
+	void __iomem *reg = ath79_gpio_get_function_reg();
+
+	__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
+	/* flush write */
+	__raw_readl(reg);
+}
+
+void ath79_gpio_function_enable(u32 mask)
+{
+	ath79_gpio_function_setup(mask, 0);
+}
+
+void ath79_gpio_function_disable(u32 mask)
+{
+	ath79_gpio_function_setup(0, mask);
+}
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -118,6 +118,7 @@ static inline int soc_is_qca955x(void)
+ void ath79_ddr_wb_flush(unsigned int reg);
+ void ath79_ddr_set_pci_windows(void);
+ 
+extern void __iomem *ath79_gpio_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
+ 
+--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
+@@ -156,4 +156,5 @@ void __init ath79_gpio_init(void)
+ 	}
+ 
+ 	platform_device_register(&ath79_gpio_device);
+	ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+ }
+--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
+@@ -24,6 +24,9 @@ unsigned long ath79_get_sys_clk_rate(con
+ 
+ void ath79_ddr_ctrl_init(void);
+ 
+void ath79_gpio_function_enable(u32 mask);
+void ath79_gpio_function_disable(u32 mask);
+void ath79_gpio_function_setup(u32 set, u32 clear);
+ void ath79_gpio_init(void);
+ 
+ #endif /* __ATH79_COMMON_H */
--- a/target/linux/ar71xx/patches-4.9/004-register_gpio_driver_earlier.patch
+++ b/target/linux/ar71xx/patches-4.9/004-register_gpio_driver_earlier.patch
@ -0,0 +1,15 @@
+HACK: register the GPIO driver earlier to ensure that gpio_request calls
+from mach files succeed.
+
+--- a/drivers/gpio/gpio-ath79.c
+++ b/drivers/gpio/gpio-ath79.c
+@@ -322,4 +322,8 @@ static struct platform_driver ath79_gpio
+ 	.remove = ath79_gpio_remove,
+ };
+ 
+-module_platform_driver(ath79_gpio_driver);
+static int __init ath79_gpio_init(void)
+{
+	return platform_driver_register(&ath79_gpio_driver);
+}
+postcore_initcall(ath79_gpio_init);
--- a/target/linux/ar71xx/patches-4.9/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch
+++ b/target/linux/ar71xx/patches-4.9/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch
@ -0,0 +1,42 @@
+From 8b7a76e72fc819753878cd5684e243f33f847c79 Mon Sep 17 00:00:00 2001
+From: Markos Chandras <markos.chandras@imgtec.com>
+Date: Wed, 21 Aug 2013 11:47:22 +0100
+Subject: [PATCH] MIPS: ath79: Avoid using unitialized 'reg' variable
+
+Fixes the following build error:
+arch/mips/include/asm/mach-ath79/ath79.h:139:20: error: 'reg' may be used
+uninitialized in this function [-Werror=maybe-uninitialized]
+arch/mips/ath79/common.c:62:6: note: 'reg' was declared here
+In file included from arch/mips/ath79/common.c:20:0:
+arch/mips/ath79/common.c: In function 'ath79_device_reset_clear':
+arch/mips/include/asm/mach-ath79/ath79.h:139:20:
+error: 'reg' may be used uninitialized in this function
+[-Werror=maybe-uninitialized]
+arch/mips/ath79/common.c:90:6: note: 'reg' was declared here
+
+Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/common.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
+@@ -106,7 +106,7 @@ void ath79_device_reset_set(u32 mask)
+ 	else if (soc_is_qca955x())
+ 		reg = QCA955X_RESET_REG_RESET_MODULE;
+ 	else
+-		BUG();
+		panic("Reset register not defined for this SOC");
+ 
+ 	spin_lock_irqsave(&ath79_device_reset_lock, flags);
+ 	t = ath79_reset_rr(reg);
+@@ -134,7 +134,7 @@ void ath79_device_reset_clear(u32 mask)
+ 	else if (soc_is_qca955x())
+ 		reg = QCA955X_RESET_REG_RESET_MODULE;
+ 	else
+-		BUG();
+		panic("Reset register not defined for this SOC");
+ 
+ 	spin_lock_irqsave(&ath79_device_reset_lock, flags);
+ 	t = ath79_reset_rr(reg);
--- a/target/linux/ar71xx/patches-4.9/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch
+++ b/target/linux/ar71xx/patches-4.9/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch
@ -0,0 +1,23 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 18 May 2016 18:03:31 +0200
+Subject: [PATCH] MIPS: ath79: fix register address in ath79_ddr_wb_flush()
+
+ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
+need to be a multiple of 4.
+
+Cc: Alban Bedel <albeu@free.fr>
+Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
+@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
+ 
+ void ath79_ddr_wb_flush(u32 reg)
+ {
+-	void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
+	void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg * 4;
+ 
+ 	/* Flush the DDR write buffer. */
+ 	__raw_writel(0x1, flush_reg);
--- a/target/linux/ar71xx/patches-4.9/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch
+++ b/target/linux/ar71xx/patches-4.9/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch
@ -0,0 +1,70 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 9 Dec 2016 20:09:16 +0100
+Subject: [PATCH] spi: spi-ath79: support multiple internal chip select
+ lines
+
+Several devices with multiple flash chips use the internal chip select
+lines. Don't assume that chip select 1 and above are GPIO lines.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
+@@ -78,14 +78,16 @@ static void ath79_spi_chipselect(struct
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+ 	}
+ 
+-	if (spi->chip_select) {
+	if (gpio_is_valid(spi->cs_gpio)) {
+ 		/* SPI is normally active-low */
+ 		gpio_set_value(spi->cs_gpio, cs_high);
+ 	} else {
+		u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
+
+ 		if (cs_high)
+-			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
+			sp->ioc_base |= cs_bit;
+ 		else
+-			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
+			sp->ioc_base &= ~cs_bit;
+ 
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+ 	}
+@@ -118,11 +120,8 @@ static int ath79_spi_setup_cs(struct spi
+ 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+ 	int status;
+ 
+-	if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
+-		return -EINVAL;
+-
+ 	status = 0;
+-	if (spi->chip_select) {
+	if (gpio_is_valid(spi->cs_gpio)) {
+ 		unsigned long flags;
+ 
+ 		flags = GPIOF_DIR_OUT;
+@@ -134,10 +133,12 @@ static int ath79_spi_setup_cs(struct spi
+ 		status = gpio_request_one(spi->cs_gpio, flags,
+ 					  dev_name(&spi->dev));
+ 	} else {
+		u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
+
+ 		if (spi->mode & SPI_CS_HIGH)
+-			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
+			sp->ioc_base &= ~cs_bit;
+ 		else
+-			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
+			sp->ioc_base |= cs_bit;
+ 
+ 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+ 	}
+@@ -147,7 +148,7 @@ static int ath79_spi_setup_cs(struct spi
+ 
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+-	if (spi->chip_select) {
+	if (gpio_is_valid(spi->cs_gpio)) {
+ 		gpio_free(spi->cs_gpio);
+ 	}
+ }
--- a/target/linux/ar71xx/patches-4.9/105-spi-spi-ath79-use-gpio_set_value_cansleep-for-GPIO-c.patch
+++ b/target/linux/ar71xx/patches-4.9/105-spi-spi-ath79-use-gpio_set_value_cansleep-for-GPIO-c.patch
@ -0,0 +1,19 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 9 Dec 2016 20:11:35 +0100
+Subject: [PATCH] spi: spi-ath79: use gpio_set_value_cansleep for GPIO chip
+ select
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
+@@ -80,7 +80,7 @@ static void ath79_spi_chipselect(struct
+ 
+ 	if (gpio_is_valid(spi->cs_gpio)) {
+ 		/* SPI is normally active-low */
+-		gpio_set_value(spi->cs_gpio, cs_high);
+		gpio_set_value_cansleep(spi->cs_gpio, cs_high);
+ 	} else {
+ 		u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
+ 
--- a/target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch
+++ b/target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch
@ -0,0 +1,29 @@
+From 0f15814bcdf59f10b708a3fba636acb089e9a4f1 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Thu, 30 Mar 2017 15:34:39 +0200
+Subject: [PATCH] MIPS: ath79: fix AR724X_PLL_REG_PCIE_CONFIG offset
+
+According to the QCA u-boot source the "PCIE Phase Lock Loop
+Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the
+QCA955X and QCA956X at offset 0x10.
+
+Since the PCIE PLL config register is only defined for the AR724x fix
+only this value. The value is wrong since the day it was added and isn't
+yet used by any driver.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -167,7 +167,7 @@
+ #define AR71XX_AHB_DIV_MASK		0x7
+ 
+ #define AR724X_PLL_REG_CPU_CONFIG	0x00
+-#define AR724X_PLL_REG_PCIE_CONFIG	0x18
+#define AR724X_PLL_REG_PCIE_CONFIG	0x10
+ 
+ #define AR724X_PLL_FB_SHIFT		0
+ #define AR724X_PLL_FB_MASK		0x3ff
--- a/target/linux/ar71xx/patches-4.9/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch
+++ b/target/linux/ar71xx/patches-4.9/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch
@ -0,0 +1,113 @@
+From 460f382c278fe66059a773c41cbcd0db86d53983 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Thu, 13 Apr 2017 09:47:42 +0200
+Subject: [PATCH] MIPS: pci-ar724x: get PCIe controller out of reset
+
+The ar724x pci driver expects the PCIe controller to be brought out of
+reset by the bootloader.
+
+At least the AVM Fritz 300E bootloader doesn't take care of releasing
+the different PCIe controller related resets which causes an endless
+hang as soon as either the PCIE Reset register (0x180f0018) or the PCI
+Application Control register (0x180f0000) is read from.
+
+Do the full "PCIE Root Complex Initialization Sequence" if the PCIe
+host controller is still in reset during probing.
+
+The QCA u-boot sleeps 10ms after the PCIE Application Control bit is
+set to ready. It has been shown that 10ms might not be enough time if
+PCIe should be used right after setting the bit. During my tests it
+took up to 20ms till the link was up. Giving the link up to 100ms
+should work for all cases.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |  3 ++
+ arch/mips/pci/pci-ar724x.c                     | 42 ++++++++++++++++++++++++++
+ 2 files changed, 45 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -169,6 +169,9 @@
+ #define AR724X_PLL_REG_CPU_CONFIG	0x00
+ #define AR724X_PLL_REG_PCIE_CONFIG	0x10
+ 
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS	BIT(16)
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET	BIT(25)
+
+ #define AR724X_PLL_FB_SHIFT		0
+ #define AR724X_PLL_FB_MASK		0x3ff
+ #define AR724X_PLL_REF_DIV_SHIFT	10
+--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
+@@ -12,14 +12,18 @@
+ #include <linux/irq.h>
+ #include <linux/pci.h>
+ #include <linux/init.h>
+#include <linux/delay.h>
+ #include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ 
+#define AR724X_PCI_REG_APP		0x0
+ #define AR724X_PCI_REG_RESET		0x18
+ #define AR724X_PCI_REG_INT_STATUS	0x4c
+ #define AR724X_PCI_REG_INT_MASK		0x50
+ 
+#define AR724X_PCI_APP_LTSSM_ENABLE	BIT(0)
+
+ #define AR724X_PCI_RESET_LINK_UP	BIT(0)
+ 
+ #define AR724X_PCI_INT_DEV0		BIT(14)
+@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a
+ 					 apc);
+ }
+ 
+static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
+{
+	u32 ppl, app;
+	int wait = 0;
+
+	/* deassert PCIe host controller and PCIe PHY reset */
+	ath79_device_reset_clear(AR724X_RESET_PCIE);
+	ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
+
+	/* remove the reset of the PCIE PLL */
+	ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+	ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
+	ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
+
+	/* deassert bypass for the PCIE PLL */
+	ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+	ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
+	ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
+
+	/* set PCIE Application Control to ready */
+	app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
+	app |= AR724X_PCI_APP_LTSSM_ENABLE;
+	__raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
+
+	/* wait up to 100ms for PHY link up */
+	do {
+		mdelay(10);
+		wait++;
+	} while (wait < 10 && !ar724x_pci_check_link(apc));
+}
+
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
+ 	struct ar724x_pci_controller *apc;
+@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf
+ 	apc->pci_controller.io_resource = &apc->io_res;
+ 	apc->pci_controller.mem_resource = &apc->mem_res;
+ 
+	/*
+	 * Do the full PCIE Root Complex Initialization Sequence if the PCIe
+	 * host controller is in reset.
+	 */
+	if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
+		ar724x_pci_hw_init(apc);
+
+ 	apc->link_up = ar724x_pci_check_link(apc);
+ 	if (!apc->link_up)
+ 		dev_warn(&pdev->dev, "PCIe link is down\n");
--- a/target/linux/ar71xx/patches-4.9/200-MIPS-ath79-fix-ar933x-wmac-reset.patch
+++ b/target/linux/ar71xx/patches-4.9/200-MIPS-ath79-fix-ar933x-wmac-reset.patch
@ -0,0 +1,30 @@
+--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
+@@ -62,10 +62,26 @@ static void __init ar913x_wmac_setup(voi
+ 
+ static int ar933x_wmac_reset(void)
+ {
+	int retries = 20;
+
+ 	ath79_device_reset_set(AR933X_RESET_WMAC);
+ 	ath79_device_reset_clear(AR933X_RESET_WMAC);
+ 
+-	return 0;
+	while (1) {
+		u32 bootstrap;
+
+		bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+		if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
+			return 0;
+
+		if (retries-- == 0)
+			break;
+
+		udelay(10000);
+	}
+
+	pr_err("ar933x: WMAC reset timed out");
+	return -ETIMEDOUT;
+ }
+ 
+ static int ar933x_r1_get_wmac_revision(void)
--- a/target/linux/ar71xx/patches-4.9/201-ar913x_wmac_external_reset.patch
+++ b/target/linux/ar71xx/patches-4.9/201-ar913x_wmac_external_reset.patch
@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
+@@ -44,7 +44,7 @@ static struct platform_device ath79_wmac
+ 	},
+ };
+ 
+-static void __init ar913x_wmac_setup(void)
+static int ar913x_wmac_reset(void)
+ {
+ 	/* reset the WMAC */
+ 	ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
+@@ -53,10 +53,19 @@ static void __init ar913x_wmac_setup(voi
+ 	ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
+ 	mdelay(10);
+ 
+	return 0;
+}
+
+static void __init ar913x_wmac_setup(void)
+{
+	ar913x_wmac_reset();
+
+ 	ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
+ 	ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
+ 	ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
+ 	ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
+
+	ath79_wmac_data.external_reset = ar913x_wmac_reset;
+ }
+ 
+ 
--- a/target/linux/ar71xx/patches-4.9/202-MIPS-ath79-ar934x-wmac-revision.patch
+++ b/target/linux/ar71xx/patches-4.9/202-MIPS-ath79-ar934x-wmac-revision.patch
@ -0,0 +1,11 @@
+--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
+@@ -139,6 +139,8 @@ static void ar934x_wmac_setup(void)
+ 		ath79_wmac_data.is_clk_25mhz = false;
+ 	else
+ 		ath79_wmac_data.is_clk_25mhz = true;
+
+	ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
+ }
+ 
+ static void qca955x_wmac_setup(void)
--- a/target/linux/ar71xx/patches-4.9/203-MIPS-ath79-fix-restart.patch
+++ b/target/linux/ar71xx/patches-4.9/203-MIPS-ath79-fix-restart.patch
@ -0,0 +1,20 @@
+--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
+@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYP
+ 
+ static void ath79_restart(char *command)
+ {
+	local_irq_disable();
+ 	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
+ 	for (;;)
+ 		if (cpu_wait)
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -135,6 +135,7 @@ static inline u32 ath79_pll_rr(unsigned
+ static inline void ath79_reset_wr(unsigned reg, u32 val)
+ {
+ 	__raw_writel(val, ath79_reset_base + reg);
+	(void) __raw_readl(ath79_reset_base + reg); /* flush */
+ }
+ 
+ static inline u32 ath79_reset_rr(unsigned reg)
--- a/target/linux/ar71xx/patches-4.9/220-add_cpu_feature_overrides.patch
+++ b/target/linux/ar71xx/patches-4.9/220-add_cpu_feature_overrides.patch
@ -0,0 +1,28 @@
+--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+@@ -36,6 +36,7 @@
+ #define cpu_has_mdmx		0
+ #define cpu_has_mips3d		0
+ #define cpu_has_smartmips	0
+#define cpu_has_rixi		0
+ 
+ #define cpu_has_mips32r1	1
+ #define cpu_has_mips32r2	1
+@@ -43,6 +44,7 @@
+ #define cpu_has_mips64r2	0
+ 
+ #define cpu_has_mipsmt		0
+#define cpu_has_userlocal	0
+ 
+ #define cpu_has_64bits		0
+ #define cpu_has_64bit_zero_reg	0
+@@ -51,5 +53,9 @@
+ 
+ #define cpu_dcache_line_size()	32
+ #define cpu_icache_line_size()	32
+#define cpu_has_vtag_icache	0
+#define cpu_has_dc_aliases	1
+#define cpu_has_ic_fills_f_dc	0
+#define cpu_has_pindexed_dcache	0
+ 
+ #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
--- a/target/linux/ar71xx/patches-4.9/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch
+++ b/target/linux/ar71xx/patches-4.9/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch
@ -0,0 +1,21 @@
+--- a/arch/mips/include/asm/mips_machine.h
+++ b/arch/mips/include/asm/mips_machine.h
+@@ -36,6 +36,18 @@ static struct mips_machine machine_##_ty
+ 	.mach_setup	= _setup,				\
+ };
+ 
+#define MIPS_MACHINE_NONAME(_type, _id, _setup)		\
+static const char machine_id_##_type[] __initconst		\
+			__aligned(1) = _id;			\
+static struct mips_machine machine_##_type			\
+		__used __section(.mips.machines.init) =		\
+{								\
+	.mach_type	= _type,				\
+	.mach_id	= machine_id_##_type,			\
+	.mach_name	= NULL,					\
+	.mach_setup	= _setup,				\
+};
+
+ extern long __mips_machines_start;
+ extern long __mips_machines_end;
+ 
--- a/target/linux/ar71xx/patches-4.9/310-lib-add-rle-decompression.patch
+++ b/target/linux/ar71xx/patches-4.9/310-lib-add-rle-decompression.patch
@ -0,0 +1,124 @@
+--- a/lib/Kconfig
+++ b/lib/Kconfig
+@@ -247,6 +247,9 @@ config LZMA_COMPRESS
+ config LZMA_DECOMPRESS
+     tristate
+ 
+config RLE_DECOMPRESS
+	tristate
+
+ #
+ # These all provide a common interface (hence the apparent duplication with
+ # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)
+--- a/lib/Makefile
+++ b/lib/Makefile
+@@ -120,6 +120,7 @@ obj-$(CONFIG_XZ_DEC) += xz/
+ obj-$(CONFIG_RAID6_PQ) += raid6/
+ obj-$(CONFIG_LZMA_COMPRESS) += lzma/
+ obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/
+obj-$(CONFIG_RLE_DECOMPRESS) += rle.o
+ 
+ lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o
+ lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o
+--- /dev/null
+++ b/include/linux/rle.h
+@@ -0,0 +1,18 @@
+#ifndef _RLE_H_
+#define _RLE_H_
+
+#ifdef CONFIG_RLE_DECOMPRESS
+int rle_decode(const unsigned char *src, size_t srclen,
+	       unsigned char *dst, size_t dstlen,
+	       size_t *src_done, size_t *dst_done);
+#else
+static inline int
+rle_decode(const unsigned char *src, size_t srclen,
+	   unsigned char *dst, size_t dstlen,
+	   size_t *src_done, size_t *dst_done)
+{
+	return -ENOTSUPP;
+}
+#endif /* CONFIG_RLE_DECOMPRESS */
+
+#endif /* _RLE_H_ */
+--- /dev/null
+++ b/lib/rle.c
+@@ -0,0 +1,78 @@
+/*
+ *  RLE decoding routine
+ *
+ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/rle.h>
+
+int rle_decode(const unsigned char *src, size_t srclen,
+	       unsigned char *dst, size_t dstlen,
+	       size_t *src_done, size_t *dst_done)
+{
+	size_t srcpos, dstpos;
+	int ret;
+
+	srcpos = 0;
+	dstpos = 0;
+	ret = -EINVAL;
+
+	/* sanity checks */
+	if (!src || !srclen || !dst || !dstlen)
+		goto out;
+
+	while (1) {
+		char count;
+
+		if (srcpos >= srclen)
+			break;
+
+		count = (char) src[srcpos++];
+		if (count == 0) {
+			ret = 0;
+			break;
+		}
+
+		if (count > 0) {
+			unsigned char c;
+
+			if (srcpos >= srclen)
+				break;
+
+			c = src[srcpos++];
+
+			while (count--) {
+				if (dstpos >= dstlen)
+					break;
+
+				dst[dstpos++] = c;
+			}
+		} else {
+			count *= -1;
+
+			while (count--) {
+				if (srcpos >= srclen)
+					break;
+				if (dstpos >= dstlen)
+					break;
+				dst[dstpos++] = src[srcpos++];
+			}
+		}
+	}
+
+out:
+	if (src_done)
+		*src_done = srcpos;
+	if (dst_done)
+		*dst_done = dstpos;
+
+	return ret;
+}
+
+EXPORT_SYMBOL_GPL(rle_decode);
--- a/target/linux/ar71xx/patches-4.9/401-mtd-physmap-add-lock-unlock.patch
+++ b/target/linux/ar71xx/patches-4.9/401-mtd-physmap-add-lock-unlock.patch
@ -0,0 +1,94 @@
+--- a/drivers/mtd/maps/physmap.c
+++ b/drivers/mtd/maps/physmap.c
+@@ -31,6 +31,66 @@ struct physmap_flash_info {
+ 	int			vpp_refcnt;
+ };
+ 
+static struct platform_device *physmap_map2pdev(struct map_info *map)
+{
+	return (struct platform_device *) map->map_priv_1;
+}
+
+static void physmap_lock(struct map_info *map)
+{
+	struct platform_device *pdev;
+	struct physmap_flash_data *physmap_data;
+
+	pdev = physmap_map2pdev(map);
+	physmap_data = pdev->dev.platform_data;
+	physmap_data->lock(pdev);
+}
+
+static void physmap_unlock(struct map_info *map)
+{
+	struct platform_device *pdev;
+	struct physmap_flash_data *physmap_data;
+
+	pdev = physmap_map2pdev(map);
+	physmap_data = pdev->dev.platform_data;
+	physmap_data->unlock(pdev);
+}
+
+static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs)
+{
+	map_word ret;
+
+	physmap_lock(map);
+	ret = inline_map_read(map, ofs);
+	physmap_unlock(map);
+
+	return ret;
+}
+
+static void physmap_flash_write_lock(struct map_info *map, map_word d,
+				     unsigned long ofs)
+{
+	physmap_lock(map);
+	inline_map_write(map, d, ofs);
+	physmap_unlock(map);
+}
+
+static void physmap_flash_copy_from_lock(struct map_info *map, void *to,
+					 unsigned long from, ssize_t len)
+{
+	physmap_lock(map);
+	inline_map_copy_from(map, to, from, len);
+	physmap_unlock(map);
+}
+
+static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to,
+				       const void *from, ssize_t len)
+{
+	physmap_lock(map);
+	inline_map_copy_to(map, to, from, len);
+	physmap_unlock(map);
+}
+
+ static int physmap_flash_remove(struct platform_device *dev)
+ {
+ 	struct physmap_flash_info *info;
+@@ -153,6 +213,13 @@ static int physmap_flash_probe(struct pl
+ 
+ 		simple_map_init(&info->map[i]);
+ 
+		if (physmap_data->lock && physmap_data->unlock) {
+			info->map[i].read = physmap_flash_read_lock;
+			info->map[i].write = physmap_flash_write_lock;
+			info->map[i].copy_from = physmap_flash_copy_from_lock;
+			info->map[i].copy_to = physmap_flash_copy_to_lock;
+		}
+
+ 		probe_type = rom_probe_types;
+ 		if (physmap_data->probe_type == NULL) {
+ 			for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++)
+--- a/include/linux/mtd/physmap.h
+++ b/include/linux/mtd/physmap.h
+@@ -25,6 +25,8 @@ struct physmap_flash_data {
+ 	unsigned int		width;
+ 	int			(*init)(struct platform_device *);
+ 	void			(*exit)(struct platform_device *);
+	void			(*lock)(struct platform_device *);
+	void			(*unlock)(struct platform_device *);
+ 	void			(*set_vpp)(struct platform_device *, int);
+ 	unsigned int		nr_parts;
+ 	unsigned int		pfow_base;
--- a/target/linux/ar71xx/patches-4.9/402-mtd-SST39VF6401B-support.patch
+++ b/target/linux/ar71xx/patches-4.9/402-mtd-SST39VF6401B-support.patch
@ -0,0 +1,29 @@
+--- a/drivers/mtd/chips/jedec_probe.c
+++ b/drivers/mtd/chips/jedec_probe.c
+@@ -148,6 +148,7 @@
+ #define SST39LF160	0x2782
+ #define SST39VF1601	0x234b
+ #define SST39VF3201	0x235b
+#define SST39VF6401B	0x236d
+ #define SST39WF1601	0x274b
+ #define SST39WF1602	0x274a
+ #define SST39LF512	0x00D4
+@@ -1569,6 +1570,18 @@ static const struct amd_flash_info jedec
+ 			ERASEINFO(0x10000,64),
+ 		}
+ 	}, {
+		.mfr_id         = CFI_MFR_SST,
+		.dev_id         = SST39VF6401B,
+		.name           = "SST 39VF6401B",
+		.devtypes       = CFI_DEVICETYPE_X16,
+		.uaddr          = MTD_UADDR_0xAAAA_0x5555,
+		.dev_size       = SIZE_8MiB,
+		.cmd_set        = P_ID_AMD_STD,
+		.nr_regions     = 1,
+		.regions        = {
+			ERASEINFO(0x10000,128)
+		}
+	}, {
+ 		.mfr_id		= CFI_MFR_ST,
+ 		.dev_id		= M29F800AB,
+ 		.name		= "ST M29F800AB",
--- a/target/linux/ar71xx/patches-4.9/403-mtd_fix_cfi_cmdset_0002_status_check.patch
+++ b/target/linux/ar71xx/patches-4.9/403-mtd_fix_cfi_cmdset_0002_status_check.patch
@ -0,0 +1,69 @@
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -1630,8 +1630,8 @@ static int __xipram do_write_oneword(str
+ 			break;
+ 		}
+ 
+-		if (chip_ready(map, adr))
+-			break;
+		if (chip_good(map, adr, datum))
+			goto enable_xip;
+ 
+ 		/* Latency issues. Drop the lock, wait a while and retry */
+ 		UDELAY(map, chip, adr, 1);
+@@ -1647,6 +1647,8 @@ static int __xipram do_write_oneword(str
+ 
+ 		ret = -EIO;
+ 	}
+
+ enable_xip:
+ 	xip_enable(map, chip, adr);
+  op_done:
+ 	if (mode == FL_OTP_WRITE)
+@@ -2225,7 +2227,6 @@ static int cfi_amdstd_panic_write(struct
+ 	return 0;
+ }
+ 
+-
+ /*
+  * Handle devices with one erase region, that only implement
+  * the chip erase command.
+@@ -2289,8 +2290,8 @@ static int __xipram do_erase_chip(struct
+ 			chip->erase_suspended = 0;
+ 		}
+ 
+-		if (chip_ready(map, adr))
+-			break;
+		if (chip_good(map, adr, map_word_ff(map)))
+			goto op_done;
+ 
+ 		if (time_after(jiffies, timeo)) {
+ 			printk(KERN_WARNING "MTD %s(): software timeout\n",
+@@ -2310,6 +2311,7 @@ static int __xipram do_erase_chip(struct
+ 		ret = -EIO;
+ 	}
+ 
+ op_done:
+ 	chip->state = FL_READY;
+ 	xip_enable(map, chip, adr);
+ 	DISABLE_VPP(map);
+@@ -2378,9 +2380,9 @@ static int __xipram do_erase_oneblock(st
+ 			chip->erase_suspended = 0;
+ 		}
+ 
+-		if (chip_ready(map, adr)) {
+		if (chip_good(map, adr, map_word_ff(map))) {
+ 			xip_enable(map, chip, adr);
+-			break;
+			goto op_done;
+ 		}
+ 
+ 		if (time_after(jiffies, timeo)) {
+@@ -2402,6 +2404,7 @@ static int __xipram do_erase_oneblock(st
+ 		ret = -EIO;
+ 	}
+ 
+ op_done:
+ 	chip->state = FL_READY;
+ 	DISABLE_VPP(map);
+ 	put_chip(map, chip, adr);
--- a/target/linux/ar71xx/patches-4.9/404-mtd-cybertan-trx-parser.patch
+++ b/target/linux/ar71xx/patches-4.9/404-mtd-cybertan-trx-parser.patch
@ -0,0 +1,25 @@
+--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
+@@ -178,6 +178,12 @@ menu "Partition parsers"
+ source "drivers/mtd/parsers/Kconfig"
+ endmenu
+ 
+config MTD_CYBERTAN_PARTS
+	tristate "Cybertan partitioning support"
+	depends on ATH79
+	---help---
+	   Cybertan partitioning support
+
+ config MTD_MYLOADER_PARTS
+ 	tristate "MyLoader partition parsing"
+ 	depends on ADM5120 || ATH25 || ATH79
+--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
+@@ -17,6 +17,7 @@ obj-$(CONFIG_MTD_BCM63XX_PARTS)	+= bcm63
+ obj-$(CONFIG_MTD_BCM47XX_PARTS)	+= bcm47xxpart.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
+ obj-y				+= parsers/
+obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o
+ 
+ # 'Users' - code which presents functionality to userspace.
+ obj-$(CONFIG_MTD_BLKDEVS)	+= mtd_blkdevs.o
--- a/target/linux/ar71xx/patches-4.9/405-mtd-tp-link-partition-parser.patch
+++ b/target/linux/ar71xx/patches-4.9/405-mtd-tp-link-partition-parser.patch
@ -0,0 +1,25 @@
+--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
+@@ -200,6 +200,12 @@ config MTD_MYLOADER_PARTS
+ 	  You will still need the parsing functions to be called by the driver
+ 	  for your particular device. It won't happen automatically.
+ 
+config MTD_TPLINK_PARTS
+	tristate "TP-Link AR7XXX/AR9XXX partitioning support"
+	depends on ATH79
+	---help---
+	  TBD.
+
+ comment "User Modules And Translation Layers"
+ 
+ #
+--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
+@@ -17,6 +17,7 @@ obj-$(CONFIG_MTD_BCM63XX_PARTS)	+= bcm63
+ obj-$(CONFIG_MTD_BCM47XX_PARTS)	+= bcm47xxpart.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
+ obj-y				+= parsers/
+obj-$(CONFIG_MTD_TPLINK_PARTS)	+= tplinkpart.o
+ obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o
+ 
+ # 'Users' - code which presents functionality to userspace.
--- a/target/linux/ar71xx/patches-4.9/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
+++ b/target/linux/ar71xx/patches-4.9/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
@ -0,0 +1,34 @@
+--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
+@@ -192,6 +192,7 @@ static ssize_t m25p80_read(struct spi_no
+  */
+ static int m25p_probe(struct spi_device *spi)
+ {
+	struct mtd_part_parser_data	ppdata = {0,};
+ 	struct flash_platform_data	*data;
+ 	struct m25p *flash;
+ 	struct spi_nor *nor;
+@@ -244,8 +245,11 @@ static int m25p_probe(struct spi_device
+ 	if (ret)
+ 		return ret;
+ 
+-	return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
+-				   data ? data->nr_parts : 0);
+	return mtd_device_parse_register(&nor->mtd,
+			data ? data->part_probes : NULL,
+			&ppdata,
+			data ? data->parts : NULL,
+ 			data ? data->nr_parts : 0);
+ }
+ 
+ 
+--- a/include/linux/spi/flash.h
+++ b/include/linux/spi/flash.h
+@@ -24,6 +24,7 @@ struct flash_platform_data {
+ 	unsigned int	nr_parts;
+ 
+ 	char		*type;
+	const char	**part_probes;
+ 
+ 	/* we'll likely add more ... use JEDEC IDs, etc */
+ };
--- a/target/linux/ar71xx/patches-4.9/408-mtd-redboot_partition_scan.patch
+++ b/target/linux/ar71xx/patches-4.9/408-mtd-redboot_partition_scan.patch
@ -0,0 +1,44 @@
+--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
+@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru
+ 	static char nullstring[] = "unallocated";
+ #endif
+ 
+	buf = vmalloc(master->erasesize);
+	if (!buf)
+		return -ENOMEM;
+
+ restart:
+ 	if ( directory < 0 ) {
+ 		offset = master->size + directory * master->erasesize;
+ 		while (mtd_block_isbad(master, offset)) {
+ 			if (!offset) {
+ 			nogood:
+ 				printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
+				vfree(buf);
+ 				return -EIO;
+ 			}
+ 			offset -= master->erasesize;
+@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru
+ 				goto nogood;
+ 		}
+ 	}
+-	buf = vmalloc(master->erasesize);
+-
+-	if (!buf)
+-		return -ENOMEM;
+ 
+ 	printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
+ 	       master->name, offset);
+@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru
+ 	}
+ 	if (i == numslots) {
+ 		/* Didn't find it */
+		if (offset + master->erasesize < master->size) {
+			/* not at the end of the flash yet, maybe next block :) */
+			directory++;
+			goto restart;
+		}
+ 		printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
+ 		       master->name);
+ 		ret = 0;
--- a/target/linux/ar71xx/patches-4.9/409-mtd-rb4xx_nand_driver.patch
+++ b/target/linux/ar71xx/patches-4.9/409-mtd-rb4xx_nand_driver.patch
@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
+@@ -569,4 +569,8 @@ config MTD_NAND_MTK
+ 	  Enables support for NAND controller on MTK SoCs.
+ 	  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
+ 
+config MTD_NAND_RB4XX
+	tristate "NAND flash driver for RouterBoard 4xx series"
+	depends on MTD_NAND && ATH79_MACH_RB4XX
+
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
+@@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270)		+= cmx27
+ obj-$(CONFIG_MTD_NAND_PXA3xx)		+= pxa3xx_nand.o
+ obj-$(CONFIG_MTD_NAND_TMIO)		+= tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM)		+= plat_nand.o
+obj-$(CONFIG_MTD_NAND_RB4XX)		+= rb4xx_nand.o
+ obj-$(CONFIG_MTD_NAND_PASEMI)		+= pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION)		+= orion_nand.o
+ obj-$(CONFIG_MTD_NAND_FSL_ELBC)		+= fsl_elbc_nand.o
--- a/target/linux/ar71xx/patches-4.9/410-mtd-rb750-nand-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/410-mtd-rb750-nand-driver.patch
@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
+@@ -573,4 +573,8 @@ config MTD_NAND_RB4XX
+ 	tristate "NAND flash driver for RouterBoard 4xx series"
+ 	depends on MTD_NAND && ATH79_MACH_RB4XX
+ 
+config MTD_NAND_RB750
+	tristate "NAND flash driver for the RouterBoard 750"
+	depends on MTD_NAND && ATH79_MACH_RB750
+
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
+@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx)		+= pxa3xx
+ obj-$(CONFIG_MTD_NAND_TMIO)		+= tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM)		+= plat_nand.o
+ obj-$(CONFIG_MTD_NAND_RB4XX)		+= rb4xx_nand.o
+obj-$(CONFIG_MTD_NAND_RB750)		+= rb750_nand.o
+ obj-$(CONFIG_MTD_NAND_PASEMI)		+= pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION)		+= orion_nand.o
+ obj-$(CONFIG_MTD_NAND_FSL_ELBC)		+= fsl_elbc_nand.o
--- a/target/linux/ar71xx/patches-4.9/411-mtd-cfi_cmdset_0002-force-word-write.patch
+++ b/target/linux/ar71xx/patches-4.9/411-mtd-cfi_cmdset_0002-force-word-write.patch
@ -0,0 +1,61 @@
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -40,7 +40,7 @@
+ #include <linux/mtd/xip.h>
+ 
+ #define AMD_BOOTLOC_BUG
+-#define FORCE_WORD_WRITE 0
+#define FORCE_WORD_WRITE 1
+ 
+ #define MAX_WORD_RETRIES 3
+ 
+@@ -51,7 +51,9 @@
+ 
+ static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+#if !FORCE_WORD_WRITE
+ static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+#endif
+ static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
+ static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_amdstd_sync (struct mtd_info *);
+@@ -202,6 +204,7 @@ static void fixup_amd_bootblock(struct m
+ }
+ #endif
+ 
+#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ 	struct map_info *map = mtd->priv;
+@@ -211,6 +214,7 @@ static void fixup_use_write_buffers(stru
+ 		mtd->_write = cfi_amdstd_write_buffers;
+ 	}
+ }
+#endif /* !FORCE_WORD_WRITE */
+ 
+ /* Atmel chips don't use the same PRI format as AMD chips */
+ static void fixup_convert_atmel_pri(struct mtd_info *mtd)
+@@ -1789,6 +1793,7 @@ static int cfi_amdstd_write_words(struct
+ /*
+  * FIXME: interleaved mode not tested, and probably not supported!
+  */
+#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ 				    unsigned long adr, const u_char *buf,
+ 				    int len)
+@@ -1917,7 +1922,6 @@ static int __xipram do_write_buffer(stru
+ 	return ret;
+ }
+ 
+-
+ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
+ 				    size_t *retlen, const u_char *buf)
+ {
+@@ -1992,6 +1996,7 @@ static int cfi_amdstd_write_buffers(stru
+ 
+ 	return 0;
+ }
+#endif /* !FORCE_WORD_WRITE */
+ 
+ /*
+  * Wait for the flash chip to become ready to write data
--- a/target/linux/ar71xx/patches-4.9/413-mtd-ar934x-nand-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/413-mtd-ar934x-nand-driver.patch
@ -0,0 +1,25 @@
+--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
+@@ -577,4 +577,12 @@ config MTD_NAND_RB750
+ 	tristate "NAND flash driver for the RouterBoard 750"
+ 	depends on MTD_NAND && ATH79_MACH_RB750
+ 
+config MTD_NAND_AR934X
+	tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
+	depends on (SOC_AR934X || SOC_QCA955X)
+
+config MTD_NAND_AR934X_HW_ECC
+	bool "Hardware ECC support for the AR934X NAND Controller (EXPERIMENTAL)"
+	depends on MTD_NAND_AR934X
+
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_AMS_DELTA)	+= ams-
+ obj-$(CONFIG_MTD_NAND_DENALI)		+= denali.o
+ obj-$(CONFIG_MTD_NAND_DENALI_PCI)	+= denali_pci.o
+ obj-$(CONFIG_MTD_NAND_DENALI_DT)	+= denali_dt.o
+obj-$(CONFIG_MTD_NAND_AR934X)		+= ar934x_nfc.o
+ obj-$(CONFIG_MTD_NAND_AU1550)		+= au1550nd.o
+ obj-$(CONFIG_MTD_NAND_BF5XX)		+= bf5xx_nand.o
+ obj-$(CONFIG_MTD_NAND_S3C2410)		+= s3c2410.o
--- a/target/linux/ar71xx/patches-4.9/414-mtd-rb91x-nand-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/414-mtd-rb91x-nand-driver.patch
@ -0,0 +1,23 @@
+--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
+@@ -577,6 +577,10 @@ config MTD_NAND_RB750
+ 	tristate "NAND flash driver for the RouterBoard 750"
+ 	depends on MTD_NAND && ATH79_MACH_RB750
+ 
+config MTD_NAND_RB91X
+	tristate "NAND flash driver for the RouterBOARD 91x series"
+	depends on MTD_NAND && ATH79_MACH_RB91X
+
+ config MTD_NAND_AR934X
+ 	tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
+ 	depends on (SOC_AR934X || SOC_QCA955X)
+--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
+@@ -36,6 +36,7 @@ obj-$(CONFIG_MTD_NAND_TMIO)		+= tmio_nan
+ obj-$(CONFIG_MTD_NAND_PLATFORM)		+= plat_nand.o
+ obj-$(CONFIG_MTD_NAND_RB4XX)		+= rb4xx_nand.o
+ obj-$(CONFIG_MTD_NAND_RB750)		+= rb750_nand.o
+obj-$(CONFIG_MTD_NAND_RB91X)		+= rb91x_nand.o
+ obj-$(CONFIG_MTD_NAND_PASEMI)		+= pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION)		+= orion_nand.o
+ obj-$(CONFIG_MTD_NAND_FSL_ELBC)		+= fsl_elbc_nand.o
--- a/target/linux/ar71xx/patches-4.9/420-net-ar71xx_mac_driver.patch
+++ b/target/linux/ar71xx/patches-4.9/420-net-ar71xx_mac_driver.patch
@ -0,0 +1,28 @@
+--- a/drivers/net/ethernet/atheros/Kconfig
+++ b/drivers/net/ethernet/atheros/Kconfig
+@@ -5,7 +5,7 @@
+ config NET_VENDOR_ATHEROS
+ 	bool "Atheros devices"
+ 	default y
+-	depends on PCI
+	depends on (PCI || ATH79)
+ 	---help---
+ 	  If you have a network (Ethernet) card belonging to this class, say Y.
+ 
+@@ -78,4 +78,6 @@ config ALX
+ 	  To compile this driver as a module, choose M here.  The module
+ 	  will be called alx.
+ 
+source drivers/net/ethernet/atheros/ag71xx/Kconfig
+
+ endif # NET_VENDOR_ATHEROS
+--- a/drivers/net/ethernet/atheros/Makefile
+++ b/drivers/net/ethernet/atheros/Makefile
+@@ -2,6 +2,7 @@
+ # Makefile for the Atheros network device drivers.
+ #
+ 
+obj-$(CONFIG_AG71XX) += ag71xx/
+ obj-$(CONFIG_ATL1) += atlx/
+ obj-$(CONFIG_ATL2) += atlx/
+ obj-$(CONFIG_ATL1E) += atl1e/
--- a/target/linux/ar71xx/patches-4.9/423-dsa-add-88e6063-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/423-dsa-add-88e6063-driver.patch
@ -0,0 +1,24 @@
+--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
+@@ -9,6 +9,13 @@ config NET_DSA_MV88E6060
+ 	  This enables support for the Marvell 88E6060 ethernet switch
+ 	  chip.
+ 
+config NET_DSA_MV88E6063
+	bool "Marvell 88E6063 ethernet switch chip support"
+	select NET_DSA_TAG_TRAILER
+	---help---
+	  This enables support for the Marvell 88E6063 ethernet switch
+	  chip
+
+ config NET_DSA_BCM_SF2
+ 	tristate "Broadcom Starfighter 2 Ethernet switch support"
+ 	depends on HAS_IOMEM && NET_DSA
+--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
+@@ -1,4 +1,5 @@
+ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
+obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
+ obj-$(CONFIG_NET_DSA_BCM_SF2)	+= bcm_sf2.o
+ obj-$(CONFIG_NET_DSA_QCA8K)	+= qca8k.o
+ 
--- a/target/linux/ar71xx/patches-4.9/430-drivers-link-spi-before-mtd.patch
+++ b/target/linux/ar71xx/patches-4.9/430-drivers-link-spi-before-mtd.patch
@ -0,0 +1,12 @@
+--- a/drivers/Makefile
+++ b/drivers/Makefile
+@@ -77,8 +77,8 @@ obj-$(CONFIG_SCSI)		+= scsi/
+ obj-y				+= nvme/
+ obj-$(CONFIG_ATA)		+= ata/
+ obj-$(CONFIG_TARGET_CORE)	+= target/
+-obj-$(CONFIG_MTD)		+= mtd/
+ obj-$(CONFIG_SPI)		+= spi/
+obj-$(CONFIG_MTD)		+= mtd/
+ obj-$(CONFIG_SPMI)		+= spmi/
+ obj-$(CONFIG_HSI)		+= hsi/
+ obj-y				+= net/
--- a/target/linux/ar71xx/patches-4.9/432-spi-rb4xx-spi-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/432-spi-rb4xx-spi-driver.patch
@ -0,0 +1,25 @@
+--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
+@@ -533,6 +533,12 @@ config SPI_QUP
+ 	  This driver can also be built as a module.  If so, the module
+ 	  will be called spi_qup.
+ 
+config SPI_RB4XX
+	tristate "Mikrotik RB4XX SPI master"
+	depends on SPI_MASTER && ATH79_MACH_RB4XX
+	help
+	  SPI controller driver for the Mikrotik RB4xx series boards.
+
+ config SPI_S3C24XX
+ 	tristate "Samsung S3C24XX series SPI"
+ 	depends on ARCH_S3C24XX
+--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
+@@ -72,6 +72,7 @@ obj-$(CONFIG_SPI_PPC4xx)		+= spi-ppc4xx.
+ spi-pxa2xx-platform-objs		:= spi-pxa2xx.o spi-pxa2xx-dma.o
+ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx-platform.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
+obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
+ obj-$(CONFIG_SPI_QUP)			+= spi-qup.o
+ obj-$(CONFIG_SPI_ROCKCHIP)		+= spi-rockchip.o
+ obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
--- a/target/linux/ar71xx/patches-4.9/433-spi-rb4xx-cpld-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/433-spi-rb4xx-cpld-driver.patch
@ -0,0 +1,26 @@
+--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
+@@ -761,6 +761,13 @@ config SPI_TLE62X0
+ 	  sysfs interface, with each line presented as a kind of GPIO
+ 	  exposing both switch control and diagnostic feedback.
+ 
+config SPI_RB4XX_CPLD
+	tristate "MikroTik RB4XX CPLD driver"
+	depends on ATH79_MACH_RB4XX
+	help
+	  SPI driver for the Xilinx CPLD chip present on the
+	  MikroTik RB4xx boards.
+
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
+@@ -73,6 +73,7 @@ spi-pxa2xx-platform-objs		:= spi-pxa2xx.
+ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx-platform.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
+ obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
+obj-$(CONFIG_SPI_RB4XX_CPLD)		+= spi-rb4xx-cpld.o
+ obj-$(CONFIG_SPI_QUP)			+= spi-qup.o
+ obj-$(CONFIG_SPI_ROCKCHIP)		+= spi-rockchip.o
+ obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
--- a/target/linux/ar71xx/patches-4.9/435-spi-vsc7385_driver.patch
+++ b/target/linux/ar71xx/patches-4.9/435-spi-vsc7385_driver.patch
@ -0,0 +1,24 @@
+--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
+@@ -768,6 +768,11 @@ config SPI_RB4XX_CPLD
+ 	  SPI driver for the Xilinx CPLD chip present on the
+ 	  MikroTik RB4xx boards.
+ 
+config SPI_VSC7385
+	tristate "Vitesse VSC7385 ethernet switch driver"
+	help
+	  SPI driver for the Vitesse VSC7385 ethernet switch.
+
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
+@@ -99,6 +99,7 @@ spi-thunderx-objs			:= spi-cavium.o spi-
+ obj-$(CONFIG_SPI_THUNDERX)		+= spi-thunderx.o
+ obj-$(CONFIG_SPI_TOPCLIFF_PCH)		+= spi-topcliff-pch.o
+ obj-$(CONFIG_SPI_TXX9)			+= spi-txx9.o
+obj-$(CONFIG_SPI_VSC7385)		+= spi-vsc7385.o
+ obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o
+ obj-$(CONFIG_SPI_XILINX)		+= spi-xilinx.o
+ obj-$(CONFIG_SPI_XLP)			+= spi-xlp.o
--- a/target/linux/ar71xx/patches-4.9/440-leds-wndr3700-usb-led-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/440-leds-wndr3700-usb-led-driver.patch
@ -0,0 +1,26 @@
+--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
+@@ -659,6 +659,13 @@ config LEDS_MLXCPLD
+ 	  This option enabled support for the LEDs on the Mellanox
+ 	  boards. Say Y to enabled these.
+ 
+config LEDS_WNDR3700_USB
+	tristate "NETGEAR WNDR3700 USB LED driver"
+	depends on LEDS_CLASS && ATH79_MACH_WNDR3700
+	help
+	  This option enables support for the USB LED found on the
+	  NETGEAR WNDR3700 board.
+
+ comment "LED Triggers"
+ source "drivers/leds/trigger/Kconfig"
+ 
+--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
+@@ -48,6 +48,7 @@ obj-$(CONFIG_LEDS_DA9052)		+= leds-da905
+ obj-$(CONFIG_LEDS_WM831X_STATUS)	+= leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
+ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
+obj-${CONFIG_LEDS_WNDR3700_USB}		+= leds-wndr3700-usb.o
+ obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o
+ obj-$(CONFIG_LEDS_INTEL_SS4200)		+= leds-ss4200.o
+ obj-$(CONFIG_LEDS_LT3593)		+= leds-lt3593.o
--- a/target/linux/ar71xx/patches-4.9/441-leds-rb750-led-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/441-leds-rb750-led-driver.patch
@ -0,0 +1,23 @@
+--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
+@@ -666,6 +666,10 @@ config LEDS_WNDR3700_USB
+ 	  This option enables support for the USB LED found on the
+ 	  NETGEAR WNDR3700 board.
+ 
+config LEDS_RB750
+	tristate "LED driver for the Mikrotik RouterBOARD 750"
+	depends on LEDS_CLASS && ATH79_MACH_RB750
+
+ comment "LED Triggers"
+ source "drivers/leds/trigger/Kconfig"
+ 
+--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
+@@ -55,6 +55,7 @@ obj-$(CONFIG_LEDS_LT3593)		+= leds-lt359
+ obj-$(CONFIG_LEDS_ADP5520)		+= leds-adp5520.o
+ obj-$(CONFIG_LEDS_DELL_NETBOOKS)	+= dell-led.o
+ obj-$(CONFIG_LEDS_MC13783)		+= leds-mc13783.o
+obj-$(CONFIG_LEDS_RB750)		+= leds-rb750.o
+ obj-$(CONFIG_LEDS_NS2)			+= leds-ns2.o
+ obj-$(CONFIG_LEDS_NETXBIG)		+= leds-netxbig.o
+ obj-$(CONFIG_LEDS_ASIC3)		+= leds-asic3.o
--- a/target/linux/ar71xx/patches-4.9/450-gpio-nxp-74hc153-gpio-chip-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/450-gpio-nxp-74hc153-gpio-chip-driver.patch
@ -0,0 +1,25 @@
+--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
+@@ -1211,4 +1211,12 @@ config GPIO_VIPERBOARD
+ 
+ endmenu
+ 
+comment "Other GPIO expanders"
+
+config GPIO_NXP_74HC153
+	tristate "NXP 74HC153 Dual 4-input multiplexer"
+	help
+	  Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
+	  provides a GPIO interface supporting input mode only.
+
+ endif
+--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
+@@ -83,6 +83,7 @@ obj-$(CONFIG_GPIO_MSIC)		+= gpio-msic.o
+ obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
+ obj-$(CONFIG_GPIO_MXC)		+= gpio-mxc.o
+ obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
+obj-$(CONFIG_GPIO_NXP_74HC153)	+= gpio-nxp-74hc153.o
+ obj-$(CONFIG_GPIO_OCTEON)	+= gpio-octeon.o
+ obj-$(CONFIG_GPIO_OMAP)		+= gpio-omap.o
+ obj-$(CONFIG_GPIO_PCA953X)	+= gpio-pca953x.o
--- a/target/linux/ar71xx/patches-4.9/451-gpio-74x164-improve-platform-device-support.patch
+++ b/target/linux/ar71xx/patches-4.9/451-gpio-74x164-improve-platform-device-support.patch
@ -0,0 +1,117 @@
+--- a/drivers/gpio/gpio-74x164.c
+++ b/drivers/gpio/gpio-74x164.c
+@@ -12,6 +12,7 @@
+ #include <linux/init.h>
+ #include <linux/mutex.h>
+ #include <linux/spi/spi.h>
+#include <linux/spi/74x164.h>
+ #include <linux/gpio.h>
+ #include <linux/of_gpio.h>
+ #include <linux/slab.h>
+@@ -103,9 +104,16 @@ static int gen_74x164_direction_output(s
+ static int gen_74x164_probe(struct spi_device *spi)
+ {
+ 	struct gen_74x164_chip *chip;
+	struct gen_74x164_chip_platform_data *pdata = spi->dev.platform_data;
+	struct device_node *np = spi->dev.of_node;
+ 	u32 nregs;
+ 	int ret;
+ 
+	if (!np && !pdata) {
+		dev_err(&spi->dev, "No configuration data available.\n");
+		return -EINVAL;
+	}
+
+ 	/*
+ 	 * bits_per_word cannot be configured in platform data
+ 	 */
+@@ -115,17 +123,23 @@ static int gen_74x164_probe(struct spi_d
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	if (of_property_read_u32(spi->dev.of_node, "registers-number",
+-				 &nregs)) {
+-		dev_err(&spi->dev,
+-			"Missing registers-number property in the DT.\n");
+-		return -EINVAL;
+-	}
+	if (np) {
+		if (of_property_read_u32(np, "registers-number", &nregs)) {
+			dev_err(&spi->dev,
+				"Missing registers-number property in the DT.\n");
+			return -EINVAL;
+		}
+	} else if (pdata) {
+		nregs = pdata->num_registers;
+ 	}
+ 
+ 	chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL);
+ 	if (!chip)
+ 		return -ENOMEM;
+ 
+	if (pdata && pdata->init_data)
+		memcpy(chip->buffer, pdata->init_data, chip->registers);
+	
+ 	spi_set_drvdata(spi, chip);
+ 
+ 	chip->gpio_chip.label = spi->modalias;
+@@ -133,7 +147,11 @@ static int gen_74x164_probe(struct spi_d
+ 	chip->gpio_chip.get = gen_74x164_get_value;
+ 	chip->gpio_chip.set = gen_74x164_set_value;
+ 	chip->gpio_chip.set_multiple = gen_74x164_set_multiple;
+-	chip->gpio_chip.base = -1;
+	if (np)
+		chip->gpio_chip.base = -1;
+	else if (pdata)
+		chip->gpio_chip.base = pdata->base;
+
+ 
+ 	chip->registers = nregs;
+ 	chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;
+@@ -170,17 +188,19 @@ static int gen_74x164_remove(struct spi_
+ 	return 0;
+ }
+ 
+#ifdef CONFIG_OF
+ static const struct of_device_id gen_74x164_dt_ids[] = {
+ 	{ .compatible = "fairchild,74hc595" },
+ 	{ .compatible = "nxp,74lvc594" },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);
+#endif
+ 
+ static struct spi_driver gen_74x164_driver = {
+ 	.driver = {
+ 		.name		= "74x164",
+-		.of_match_table	= gen_74x164_dt_ids,
+		.of_match_table	= of_match_ptr(gen_74x164_dt_ids),
+ 	},
+ 	.probe		= gen_74x164_probe,
+ 	.remove		= gen_74x164_remove,
+--- /dev/null
+++ b/include/linux/spi/74x164.h
+@@ -0,0 +1,13 @@
+#ifndef LINUX_SPI_74X164_H
+#define LINUX_SPI_74X164_H
+
+struct gen_74x164_chip_platform_data {
+	/* number assigned to the first GPIO */
+	unsigned        base;
+	/* number of chained registers */
+	unsigned	num_registers;
+	/* address of a buffer containing initial data */
+	u8		*init_data;
+};
+
+#endif
+--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
+@@ -1154,7 +1154,6 @@ menu "SPI GPIO expanders"
+ 
+ config GPIO_74X164
+ 	tristate "74x164 serial-in/parallel-out 8-bits shift register"
+-	depends on OF_GPIO
+ 	help
+ 	  Driver for 74x164 compatible serial-in/parallel-out 8-outputs
+ 	  shift registers. This driver can be used to provide access
--- a/target/linux/ar71xx/patches-4.9/452-gpio-add-gpio-latch-driver.patch
+++ b/target/linux/ar71xx/patches-4.9/452-gpio-add-gpio-latch-driver.patch
@ -0,0 +1,22 @@
+--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
+@@ -1218,4 +1218,9 @@ config GPIO_NXP_74HC153
+ 	  Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
+ 	  provides a GPIO interface supporting input mode only.
+ 
+config GPIO_LATCH
+	tristate "GPIO latch driver"
+	help
+	  Say yes here to enable a GPIO latch driver.
+
+ endif
+--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
+@@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_JANZ_TTL)	+= gpio-janz
+ obj-$(CONFIG_GPIO_KEMPLD)	+= gpio-kempld.o
+ obj-$(CONFIG_ARCH_KS8695)	+= gpio-ks8695.o
+ obj-$(CONFIG_GPIO_INTEL_MID)	+= gpio-intel-mid.o
+obj-$(CONFIG_GPIO_LATCH)	+= gpio-latch.o
+ obj-$(CONFIG_GPIO_LOONGSON)	+= gpio-loongson.o
+ obj-$(CONFIG_GPIO_LP3943)	+= gpio-lp3943.o
+ obj-$(CONFIG_GPIO_LPC18XX)	+= gpio-lpc18xx.o
--- a/target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch
+++ b/target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch
@ -0,0 +1,54 @@
+--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
+@@ -102,9 +102,6 @@ static void ath79_spi_enable(struct ath7
+ 	/* save CTRL register */
+ 	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
+ 	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
+-
+-	/* TODO: setup speed? */
+-	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
+ }
+ 
+ static void ath79_spi_disable(struct ath79_spi *sp)
+@@ -205,6 +202,33 @@ static u32 ath79_spi_txrx_mode0(struct s
+ 	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
+ }
+ 
+static int ath79_spi_read_flash_data(struct spi_device *spi,
+				     struct spi_flash_read_message *msg)
+{
+	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+
+	if (msg->addr_width > 3)
+		return -EOPNOTSUPP;
+
+	if (spi->chip_select || gpio_is_valid(spi->cs_gpio))
+		return -EOPNOTSUPP;
+
+	/* disable GPIO mode */
+	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
+
+	memcpy_fromio(msg->buf, sp->base + msg->from, msg->len);
+
+	/* enable GPIO mode */
+	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+
+	/* restore IOC register */
+	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+
+	msg->retlen = msg->len;
+
+	return 0;
+}
+
+ static int ath79_spi_probe(struct platform_device *pdev)
+ {
+ 	struct spi_master *master;
+@@ -234,6 +258,7 @@ static int ath79_spi_probe(struct platfo
+ 		master->num_chipselect = pdata->num_chipselect;
+ 		master->cs_gpios = pdata->cs_gpios;
+ 	}
+	master->spi_flash_read = ath79_spi_read_flash_data;
+ 
+ 	sp->bitbang.master = master;
+ 	sp->bitbang.chipselect = ath79_spi_chipselect;
--- a/target/linux/ar71xx/patches-4.9/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch
+++ b/target/linux/ar71xx/patches-4.9/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch
@ -0,0 +1,111 @@
+--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
+@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
+#define __ASM_MACH_ATH79_MANGLE_PORT_H
+
+#ifdef CONFIG_PCI
+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
+#else
+#define ath79_pci_swizzle_b(port) (port)
+#define ath79_pci_swizzle_w(port) (port)
+#endif
+
+#define __swizzle_addr_b(port)	ath79_pci_swizzle_b(port)
+#define __swizzle_addr_w(port)	ath79_pci_swizzle_w(port)
+#define __swizzle_addr_l(port)	(port)
+#define __swizzle_addr_q(port)	(port)
+
+# define ioswabb(a, x)           (x)
+# define __mem_ioswabb(a, x)     (x)
+# define ioswabw(a, x)           (x)
+# define __mem_ioswabw(a, x)     cpu_to_le16(x)
+# define ioswabl(a, x)           (x)
+# define __mem_ioswabl(a, x)     cpu_to_le32(x)
+# define ioswabq(a, x)           (x)
+# define __mem_ioswabq(a, x)     cpu_to_le64(x)
+
+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
+--- a/arch/mips/ath79/pci.c
+++ b/arch/mips/ath79/pci.c
+@@ -13,6 +13,7 @@
+  */
+ 
+ #include <linux/init.h>
+#include <linux/export.h>
+ #include <linux/pci.h>
+ #include <linux/resource.h>
+ #include <linux/platform_device.h>
+@@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st
+ static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
+ static unsigned ath79_pci_nr_irqs __initdata;
+ 
+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
+
+ static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
+ 	{
+ 		.slot	= 17,
+@@ -212,12 +216,50 @@ ath79_register_pci_ar724x(int id,
+ 	return pdev;
+ }
+ 
+static inline bool ar71xx_is_pci_addr(unsigned long port)
+{
+	unsigned long phys = CPHYSADDR(port);
+
+	return (phys >= AR71XX_PCI_MEM_BASE &&
+		phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
+}
+
+static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
+{
+	return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
+}
+
+static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
+{
+	return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
+}
+
+unsigned long ath79_pci_swizzle_b(unsigned long port)
+{
+	if (__ath79_pci_swizzle_b)
+		return __ath79_pci_swizzle_b(port);
+
+	return port;
+}
+EXPORT_SYMBOL(ath79_pci_swizzle_b);
+
+unsigned long ath79_pci_swizzle_w(unsigned long port)
+{
+	if (__ath79_pci_swizzle_w)
+		return __ath79_pci_swizzle_w(port);
+
+	return port;
+}
+EXPORT_SYMBOL(ath79_pci_swizzle_w);
+
+ int __init ath79_register_pci(void)
+ {
+ 	struct platform_device *pdev = NULL;
+ 
+ 	if (soc_is_ar71xx()) {
+ 		pdev = ath79_register_pci_ar71xx();
+		__ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
+		__ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
+ 	} else if (soc_is_ar724x()) {
+ 		pdev = ath79_register_pci_ar724x(-1,
+ 						 AR724X_PCI_CFG_BASE,
--- a/target/linux/ar71xx/patches-4.9/490-usb-ehci-add-quirks-for-qca-socs.patch
+++ b/target/linux/ar71xx/patches-4.9/490-usb-ehci-add-quirks-for-qca-socs.patch
@ -0,0 +1,103 @@
+--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
+@@ -252,6 +252,37 @@ int ehci_reset(struct ehci_hcd *ehci)
+ 	command |= CMD_RESET;
+ 	dbg_cmd (ehci, "reset", command);
+ 	ehci_writel(ehci, command, &ehci->regs->command);
+
+	if (ehci->qca_force_host_mode) {
+		u32 usbmode;
+
+		udelay(1000);
+
+		usbmode = ehci_readl(ehci, &ehci->regs->usbmode);
+		usbmode |= USBMODE_CM_HC | (1 << 4);
+		ehci_writel(ehci, usbmode, &ehci->regs->usbmode);
+
+		ehci_dbg(ehci, "forced host mode, usbmode: %08x\n",
+			 ehci_readl(ehci, &ehci->regs->usbmode));
+	}
+
+	if (ehci->qca_force_16bit_ptw) {
+		u32 port_status;
+
+		udelay(1000);
+
+		/* enable 16-bit UTMI interface */
+		port_status = ehci_readl(ehci, &ehci->regs->port_status[0]);
+		port_status |= BIT(28);
+		ehci_writel(ehci, port_status, &ehci->regs->port_status[0]);
+
+		ehci_dbg(ehci, "16-bit UTMI interface enabled, status: %08x\n",
+			 ehci_readl(ehci, &ehci->regs->port_status[0]));
+	}
+
+	if (ehci->reset_notifier)
+		ehci->reset_notifier(ehci_to_hcd(ehci));
+
+ 	ehci->rh_state = EHCI_RH_HALTED;
+ 	ehci->next_statechange = jiffies;
+ 	retval = ehci_handshake(ehci, &ehci->regs->command,
+--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
+@@ -231,6 +231,10 @@ struct ehci_hcd {			/* one per controlle
+ 	unsigned		need_oc_pp_cycle:1; /* MPC834X port power */
+ 	unsigned		imx28_write_fix:1; /* For Freescale i.MX28 */
+ 	unsigned		ignore_oc:1;
+	unsigned		qca_force_host_mode:1;
+	unsigned		qca_force_16bit_ptw:1; /* force 16 bit UTMI */
+
+	void (*reset_notifier)(struct usb_hcd *hcd);
+ 
+ 	/* required for usb32 quirk */
+ 	#define OHCI_CTRL_HCFS          (3 << 6)
+--- a/include/linux/usb/ehci_pdriver.h
+++ b/include/linux/usb/ehci_pdriver.h
+@@ -50,6 +50,8 @@ struct usb_ehci_pdata {
+ 	unsigned	reset_on_resume:1;
+ 	unsigned	dma_mask_64:1;
+ 	unsigned	ignore_oc:1;
+	unsigned	qca_force_host_mode:1;
+	unsigned	qca_force_16bit_ptw:1;
+ 
+ 	/* Turn on all power and clocks */
+ 	int (*power_on)(struct platform_device *pdev);
+@@ -59,6 +61,7 @@ struct usb_ehci_pdata {
+ 	 * turn off everything else */
+ 	void (*power_suspend)(struct platform_device *pdev);
+ 	int (*pre_setup)(struct usb_hcd *hcd);
+	void (*reset_notifier)(struct platform_device *pdev);
+ };
+ 
+ #endif /* __USB_CORE_EHCI_PDRIVER_H */
+--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
+@@ -52,6 +52,14 @@ struct ehci_platform_priv {
+ 
+ static const char hcd_name[] = "ehci-platform";
+ 
+static void ehci_platform_reset_notifier(struct usb_hcd *hcd)
+{
+	struct platform_device *pdev = to_platform_device(hcd->self.controller);
+	struct usb_ehci_pdata *pdata = pdev->dev.platform_data;
+
+	pdata->reset_notifier(pdev);
+}
+
+ static int ehci_platform_reset(struct usb_hcd *hcd)
+ {
+ 	struct platform_device *pdev = to_platform_device(hcd->self.controller);
+@@ -261,6 +269,13 @@ static int ehci_platform_probe(struct pl
+ 		priv->reset_on_resume = true;
+ 	if (pdata->ignore_oc)
+ 		ehci->ignore_oc = 1;
+	if (pdata->qca_force_host_mode)
+		ehci->qca_force_host_mode = 1;
+	if (pdata->qca_force_16bit_ptw)
+		ehci->qca_force_16bit_ptw = 1;
+
+	if (pdata->reset_notifier)
+		ehci->reset_notifier = ehci_platform_reset_notifier;
+ 
+ #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
+ 	if (ehci->big_endian_mmio) {
--- a/target/linux/ar71xx/patches-4.9/500-MIPS-fw-myloader.patch
+++ b/target/linux/ar71xx/patches-4.9/500-MIPS-fw-myloader.patch
@ -0,0 +1,22 @@
+--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
+@@ -213,6 +213,7 @@ cflags-$(toolchain-virt)		+= -DTOOLCHAIN
+ #
+ libs-$(CONFIG_FW_ARC)		+= arch/mips/fw/arc/
+ libs-$(CONFIG_FW_CFE)		+= arch/mips/fw/cfe/
+libs-$(CONFIG_MYLOADER)		+= arch/mips/fw/myloader/
+ libs-$(CONFIG_FW_SNIPROM)	+= arch/mips/fw/sni/
+ libs-y				+= arch/mips/fw/lib/
+ 
+--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
+@@ -1144,6 +1144,9 @@ config MIPS_MSC
+ config MIPS_NILE4
+ 	bool
+ 
+config MYLOADER
+	bool
+
+ config SYNC_R4K
+ 	bool
+ 
--- a/target/linux/ar71xx/patches-4.9/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch
+++ b/target/linux/ar71xx/patches-4.9/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch
@ -0,0 +1,70 @@
+--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
+@@ -15,6 +15,7 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/irq.h>
+#include <linux/etherdevice.h>
+ #include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
+ 
+@@ -22,6 +23,7 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "dev-wmac.h"
+ 
+static u8 ath79_wmac_mac[ETH_ALEN];
+ static struct ath9k_platform_data ath79_wmac_data;
+ 
+ static struct resource ath79_wmac_resources[] = {
+@@ -161,7 +163,7 @@ static void qca955x_wmac_setup(void)
+ 		ath79_wmac_data.is_clk_25mhz = true;
+ }
+ 
+-void __init ath79_register_wmac(u8 *cal_data)
+void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ 	if (soc_is_ar913x())
+ 		ar913x_wmac_setup();
+@@ -178,5 +180,10 @@ void __init ath79_register_wmac(u8 *cal_
+ 		memcpy(ath79_wmac_data.eeprom_data, cal_data,
+ 		       sizeof(ath79_wmac_data.eeprom_data));
+ 
+	if (mac_addr) {
+		memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac));
+		ath79_wmac_data.macaddr = ath79_wmac_mac;
+	}
+
+ 	platform_device_register(&ath79_wmac_device);
+ }
+--- a/arch/mips/ath79/dev-wmac.h
+++ b/arch/mips/ath79/dev-wmac.h
+@@ -12,6 +12,6 @@
+ #ifndef _ATH79_DEV_WMAC_H
+ #define _ATH79_DEV_WMAC_H
+ 
+-void ath79_register_wmac(u8 *cal_data);
+void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/ath79/mach-db120.c
+++ b/arch/mips/ath79/mach-db120.c
+@@ -128,7 +128,7 @@ static void __init db120_setup(void)
+ 	ath79_register_spi(&db120_spi_data, db120_spi_info,
+ 			   ARRAY_SIZE(db120_spi_info));
+ 	ath79_register_usb();
+-	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
+	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+ 	db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
+ }
+ 
+--- a/arch/mips/ath79/mach-ap121.c
+++ b/arch/mips/ath79/mach-ap121.c
+@@ -85,7 +85,7 @@ static void __init ap121_setup(void)
+ 	ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+ 			   ARRAY_SIZE(ap121_spi_info));
+ 	ath79_register_usb();
+-	ath79_register_wmac(cal_data);
+	ath79_register_wmac(cal_data, NULL);
+ }
+ 
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
--- a/target/linux/ar71xx/patches-4.9/504-MIPS-ath79-add-ath79_device_reset_get.patch
+++ b/target/linux/ar71xx/patches-4.9/504-MIPS-ath79-add-ath79_device_reset_get.patch
@ -0,0 +1,42 @@
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -145,6 +145,7 @@ static inline u32 ath79_reset_rr(unsigne
+ 
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
+u32 ath79_device_reset_get(u32 mask);
+ 
+ void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
+ void ath79_misc_irq_init(void __iomem *regs, int irq,
+--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
+@@ -142,3 +142,29 @@ void ath79_device_reset_clear(u32 mask)
+ 	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
+
+u32 ath79_device_reset_get(u32 mask)
+{
+	unsigned long flags;
+	u32 reg;
+	u32 ret;
+
+	if (soc_is_ar71xx())
+		reg = AR71XX_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar724x())
+		reg = AR724X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar913x())
+		reg = AR913X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar933x())
+		reg = AR933X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar934x())
+		reg = AR934X_RESET_REG_RESET_MODULE;
+	else
+		BUG();
+
+	spin_lock_irqsave(&ath79_device_reset_lock, flags);
+	ret = ath79_reset_rr(reg);
+	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(ath79_device_reset_get);
--- a/target/linux/ar71xx/patches-4.9/505-MIPS-ath79-add-ath79_gpio_function_select.patch
+++ b/target/linux/ar71xx/patches-4.9/505-MIPS-ath79-add-ath79_gpio_function_select.patch
@ -0,0 +1,39 @@
+--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
+@@ -27,6 +27,7 @@ void ath79_ddr_ctrl_init(void);
+ void ath79_gpio_function_enable(u32 mask);
+ void ath79_gpio_function_disable(u32 mask);
+ void ath79_gpio_function_setup(u32 set, u32 clear);
+void ath79_gpio_output_select(unsigned gpio, u8 val);
+ void ath79_gpio_init(void);
+ 
+ #endif /* __ATH79_COMMON_H */
+--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
+@@ -57,3 +57,26 @@ void ath79_gpio_function_disable(u32 mas
+ {
+ 	ath79_gpio_function_setup(0, mask);
+ }
+
+void __init ath79_gpio_output_select(unsigned gpio, u8 val)
+{
+	void __iomem *base = ath79_gpio_base;
+	unsigned int reg;
+	u32 t, s;
+
+	BUG_ON(!soc_is_ar934x());
+
+	if (gpio >= AR934X_GPIO_COUNT)
+		return;
+
+	reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
+	s = 8 * (gpio % 4);
+
+	t = __raw_readl(base + reg);
+	t &= ~(0xff << s);
+	t |= val << s;
+	__raw_writel(t, base + reg);
+
+	/* flush write */
+	(void) __raw_readl(base + reg);
+}
--- a/target/linux/ar71xx/patches-4.9/506-MIPS-ath79-prom-parse-redboot-args.patch
+++ b/target/linux/ar71xx/patches-4.9/506-MIPS-ath79-prom-parse-redboot-args.patch
@ -0,0 +1,42 @@
+--- a/arch/mips/ath79/prom.c
+++ b/arch/mips/ath79/prom.c
+@@ -22,10 +22,39 @@
+ 
+ #include "common.h"
+ 
+static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata;
+
+static void __init ath79_prom_append_cmdline(const char *name,
+					      const char *value)
+{
+	snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf),
+		 " %s=%s", name, value);
+	strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
+}
+
+ void __init prom_init(void)
+ {
+	const char *env;
+
+ 	fw_init_cmdline();
+ 
+	env = fw_getenv("ethaddr");
+	if (env)
+		ath79_prom_append_cmdline("ethaddr", env);
+
+	env = fw_getenv("board");
+	if (env) {
+		/* Workaround for buggy bootloaders */
+		if (strcmp(env, "RouterStation") == 0 ||
+		    strcmp(env, "Ubiquiti AR71xx-based board") == 0)
+			env = "UBNT-RS";
+
+		if (strcmp(env, "RouterStation PRO") == 0)
+			env = "UBNT-RSPRO";
+
+		ath79_prom_append_cmdline("board", env);
+	}
+
+ #ifdef CONFIG_BLK_DEV_INITRD
+ 	/* Read the initrd address from the firmware environment */
+ 	initrd_start = fw_getenvl("initrd_start");
--- a/target/linux/ar71xx/patches-4.9/507-MIPS-ath79-prom-add-myloader-support.patch
+++ b/target/linux/ar71xx/patches-4.9/507-MIPS-ath79-prom-add-myloader-support.patch
@ -0,0 +1,55 @@
+--- a/arch/mips/ath79/prom.c
+++ b/arch/mips/ath79/prom.c
+@@ -19,6 +19,7 @@
+ #include <asm/bootinfo.h>
+ #include <asm/addrspace.h>
+ #include <asm/fw/fw.h>
+#include <asm/fw/myloader/myloader.h>
+ 
+ #include "common.h"
+ 
+@@ -32,10 +33,44 @@ static void __init ath79_prom_append_cmd
+ 	strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
+ }
+ 
+static int __init ath79_prom_init_myloader(void)
+{
+	struct myloader_info *mylo;
+	char mac_buf[32];
+	unsigned char *mac;
+
+	mylo = myloader_get_info();
+	if (!mylo)
+		return 0;
+
+	switch (mylo->did) {
+	case DEVID_COMPEX_WP543:
+		ath79_prom_append_cmdline("board", "WP543");
+		break;
+	case DEVID_COMPEX_WPE72:
+		ath79_prom_append_cmdline("board", "WPE72");
+		break;
+	default:
+		pr_warn("prom: unknown device id: %x\n", mylo->did);
+		return 0;
+	}
+
+	mac = mylo->macs[0];
+	snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x",
+		 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+	ath79_prom_append_cmdline("ethaddr", mac_buf);
+
+	return 1;
+}
+
+ void __init prom_init(void)
+ {
+ 	const char *env;
+ 
+	if (ath79_prom_init_myloader())
+		return;
+
+ 	fw_init_cmdline();
+ 
+ 	env = fw_getenv("ethaddr");
--- a/target/linux/ar71xx/patches-4.9/508-MIPS-ath79-prom-image-command-line-hack.patch
+++ b/target/linux/ar71xx/patches-4.9/508-MIPS-ath79-prom-image-command-line-hack.patch
@ -0,0 +1,73 @@
+--- a/arch/mips/ath79/prom.c
+++ b/arch/mips/ath79/prom.c
+@@ -33,6 +33,41 @@ static void __init ath79_prom_append_cmd
+ 	strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
+ }
+ 
+#ifdef CONFIG_IMAGE_CMDLINE_HACK
+extern char __image_cmdline[];
+
+static int __init ath79_use_image_cmdline(void)
+{
+	char *p = __image_cmdline;
+	int replace = 0;
+
+	if (*p == '-') {
+		replace = 1;
+		p++;
+	}
+
+	if (*p == '\0')
+		return 0;
+
+	if (replace) {
+		strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
+	} else {
+		strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
+		strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
+	}
+
+	/* Validate and setup environment pointer */
+	if (fw_arg2 < CKSEG0)
+		_fw_envp = NULL;
+	else
+		_fw_envp = (int *)fw_arg2;
+
+	return 1;
+}
+#else
+static inline int ath79_use_image_cmdline(void) { return 0; }
+#endif
+
+ static int __init ath79_prom_init_myloader(void)
+ {
+ 	struct myloader_info *mylo;
+@@ -61,6 +96,8 @@ static int __init ath79_prom_init_myload
+ 
+ 	ath79_prom_append_cmdline("ethaddr", mac_buf);
+ 
+	ath79_use_image_cmdline();
+
+ 	return 1;
+ }
+ 
+@@ -71,7 +108,8 @@ void __init prom_init(void)
+ 	if (ath79_prom_init_myloader())
+ 		return;
+ 
+-	fw_init_cmdline();
+	if (!ath79_use_image_cmdline())
+		fw_init_cmdline();
+ 
+ 	env = fw_getenv("ethaddr");
+ 	if (env)
+--- a/arch/mips/fw/lib/cmdline.c
+++ b/arch/mips/fw/lib/cmdline.c
+@@ -35,6 +35,7 @@ void __init fw_init_cmdline(void)
+ 	else
+ 		_fw_envp = (int *)fw_arg2;
+ 
+	arcs_cmdline[0] = '\0';
+ 	for (i = 1; i < fw_argc; i++) {
+ 		strlcat(arcs_cmdline, fw_argv(i), COMMAND_LINE_SIZE);
+ 		if (i < (fw_argc - 1))
--- a/target/linux/ar71xx/patches-4.9/509-MIPS-ath79-process-board-kernel-option.patch
+++ b/target/linux/ar71xx/patches-4.9/509-MIPS-ath79-process-board-kernel-option.patch
@ -0,0 +1,11 @@
+--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
+@@ -283,6 +283,8 @@ void __init plat_time_init(void)
+ 	mips_hpt_frequency = cpu_clk_rate / 2;
+ }
+ 
+__setup("board=", mips_machtype_setup);
+
+ static int __init ath79_setup(void)
+ {
+ 	if  (mips_machtype == ATH79_MACH_GENERIC_OF)
--- a/target/linux/ar71xx/patches-4.9/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch
+++ b/target/linux/ar71xx/patches-4.9/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch
@ -0,0 +1,14 @@
+--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
+@@ -24,7 +24,10 @@
+ #include "dev-wmac.h"
+ 
+ static u8 ath79_wmac_mac[ETH_ALEN];
+-static struct ath9k_platform_data ath79_wmac_data;
+
+static struct ath9k_platform_data ath79_wmac_data = {
+	.led_pin = -1,
+};
+ 
+ static struct resource ath79_wmac_resources[] = {
+ 	{
--- a/target/linux/ar71xx/patches-4.9/520-MIPS-ath79-enable-UART-function.patch
+++ b/target/linux/ar71xx/patches-4.9/520-MIPS-ath79-enable-UART-function.patch
@ -0,0 +1,18 @@
+--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
+@@ -81,6 +81,15 @@ void __init ath79_register_uart(void)
+ 
+ 	uart_clk_rate = ath79_get_sys_clk_rate("uart");
+ 
+	if (soc_is_ar71xx())
+		ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN);
+	else if (soc_is_ar724x())
+		ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN);
+	else if (soc_is_ar913x())
+		ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN);
+	else if (soc_is_ar933x())
+		ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN);
+
+ 	if (soc_is_ar71xx() ||
+ 	    soc_is_ar724x() ||
+ 	    soc_is_ar913x() ||
--- a/target/linux/ar71xx/patches-4.9/521-MIPS-ath79-enable-UART-for-early_serial.patch
+++ b/target/linux/ar71xx/patches-4.9/521-MIPS-ath79-enable-UART-for-early_serial.patch
@ -0,0 +1,61 @@
+--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
+@@ -58,6 +58,46 @@ static void prom_putchar_dummy(unsigned
+ 	/* nothing to do */
+ }
+ 
+static void prom_enable_uart(u32 id)
+{
+	void __iomem *gpio_base;
+	u32 uart_en;
+	u32 t;
+
+	switch (id) {
+	case REV_ID_MAJOR_AR71XX:
+		uart_en = AR71XX_GPIO_FUNC_UART_EN;
+		break;
+
+	case REV_ID_MAJOR_AR7240:
+	case REV_ID_MAJOR_AR7241:
+	case REV_ID_MAJOR_AR7242:
+		uart_en = AR724X_GPIO_FUNC_UART_EN;
+		break;
+
+	case REV_ID_MAJOR_AR913X:
+		uart_en = AR913X_GPIO_FUNC_UART_EN;
+		break;
+
+	case REV_ID_MAJOR_AR9330:
+	case REV_ID_MAJOR_AR9331:
+		uart_en = AR933X_GPIO_FUNC_UART_EN;
+		break;
+
+	case REV_ID_MAJOR_AR9341:
+	case REV_ID_MAJOR_AR9342:
+	case REV_ID_MAJOR_AR9344:
+		/* TODO */
+	default:
+		return;
+	}
+
+	gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE));
+	t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
+	t |= uart_en;
+	__raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
+}
+
+ static void prom_putchar_init(void)
+ {
+ 	void __iomem *base;
+@@ -88,8 +128,10 @@ static void prom_putchar_init(void)
+ 
+ 	default:
+ 		_prom_putchar = prom_putchar_dummy;
+-		break;
+		return;
+ 	}
+
+	prom_enable_uart(id);
+ }
+ 
+ void prom_putchar(unsigned char ch)
--- a/target/linux/ar71xx/patches-4.9/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch
+++ b/target/linux/ar71xx/patches-4.9/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch
@ -0,0 +1,21 @@
+--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
+@@ -190,3 +190,9 @@ void __init ath79_register_wmac(u8 *cal_
+ 
+ 	platform_device_register(&ath79_wmac_device);
+ }
+
+void __init ath79_register_wmac_simple(void)
+{
+	ath79_register_wmac(NULL, NULL);
+	ath79_wmac_data.eeprom_name = "soc_wmac.eeprom";
+}
+--- a/arch/mips/ath79/dev-wmac.h
+++ b/arch/mips/ath79/dev-wmac.h
+@@ -13,5 +13,6 @@
+ #define _ATH79_DEV_WMAC_H
+ 
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+void ath79_register_wmac_simple(void);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
--- a/target/linux/ar71xx/patches-4.9/523-MIPS-ath79-OTP-support.patch
+++ b/target/linux/ar71xx/patches-4.9/523-MIPS-ath79-OTP-support.patch
@ -0,0 +1,192 @@
+--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
+@@ -166,6 +166,149 @@ static void qca955x_wmac_setup(void)
+ 		ath79_wmac_data.is_clk_25mhz = true;
+ }
+ 
+#define AR93XX_WMAC_SIZE \
+	(soc_is_ar934x() ? AR934X_WMAC_SIZE : AR933X_WMAC_SIZE)
+#define AR93XX_WMAC_BASE \
+	(soc_is_ar934x() ? AR934X_WMAC_BASE : AR933X_WMAC_BASE)
+
+#define AR93XX_OTP_BASE \
+	(soc_is_ar934x() ? AR934X_OTP_BASE : AR9300_OTP_BASE)
+#define AR93XX_OTP_STATUS \
+	(soc_is_ar934x() ? AR934X_OTP_STATUS : AR9300_OTP_STATUS)
+#define AR93XX_OTP_READ_DATA \
+	(soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
+
+static bool __init
+ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
+{
+	int timeout = 1000;
+	u32 val;
+
+	__raw_readl(base + AR93XX_OTP_BASE + (4 * addr));
+	while (timeout--) {
+		val = __raw_readl(base + AR93XX_OTP_STATUS);
+		if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
+			break;
+
+		udelay(10);
+	}
+
+	if (!timeout)
+		return false;
+
+	*data = __raw_readl(base + AR93XX_OTP_READ_DATA);
+	return true;
+}
+
+static bool __init
+ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
+{
+	u32 data;
+	int i;
+
+	for (i = 0; i < len; i++) {
+		int offset = 8 * ((addr - i) % 4);
+
+		if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
+			return false;
+
+		dest[i] = (data >> offset) & 0xff;
+	}
+
+	return true;
+}
+
+static bool __init
+ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
+			   int dest_start, int dest_len)
+{
+	int dest_bytes = 0;
+	int offset = 0;
+	int end = addr - len;
+	u8 hdr[2];
+
+	while (addr > end) {
+		if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
+			return false;
+
+		addr -= 2;
+		offset += hdr[0];
+
+		if (offset <= dest_start + dest_len &&
+		    offset + len >= dest_start) {
+			int data_offset = 0;
+			int dest_offset = 0;
+			int copy_len;
+
+			if (offset < dest_start)
+				data_offset = dest_start - offset;
+			else
+				dest_offset = offset - dest_start;
+
+			copy_len = len - data_offset;
+			if (copy_len > dest_len - dest_offset)
+				copy_len = dest_len - dest_offset;
+
+			ar93xx_wmac_otp_read(base, addr - data_offset,
+					     dest + dest_offset,
+					     copy_len);
+
+			dest_bytes += copy_len;
+		}
+		addr -= hdr[1];
+	}
+	return !!dest_bytes;
+}
+
+bool __init ar93xx_wmac_read_mac_address(u8 *dest)
+{
+	void __iomem *base;
+	bool ret = false;
+	int addr = 0x1ff;
+	unsigned int len;
+	u32 hdr_u32;
+	u8 *hdr = (u8 *) &hdr_u32;
+	u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
+	int mac_start = 2, mac_end = 8;
+
+	BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
+	base = ioremap_nocache(AR93XX_WMAC_BASE, AR93XX_WMAC_SIZE);
+	while (addr > sizeof(hdr_u32)) {
+		if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr_u32)))
+			break;
+
+		if (hdr_u32 == 0 || hdr_u32 == ~0)
+			break;
+
+		len = (hdr[1] << 4) | (hdr[2] >> 4);
+		addr -= 4;
+
+		switch (hdr[0] >> 5) {
+		case 0:
+			if (len < mac_end)
+				break;
+
+			ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
+			ret = true;
+			break;
+		case 3:
+			ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
+							  mac_start, 6);
+			break;
+		default:
+			break;
+		}
+
+		addr -= len + 2;
+	}
+
+	iounmap(base);
+	if (ret)
+		memcpy(dest, mac, 6);
+
+	return ret;
+}
+
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ 	if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
+++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,5 +14,6 @@
+ 
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
+bool ar93xx_wmac_read_mac_address(u8 *dest);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -112,6 +112,14 @@
+ #define QCA955X_EHCI1_BASE	0x1b400000
+ #define QCA955X_EHCI_SIZE	0x1000
+ 
+#define AR9300_OTP_BASE		0x14000
+#define AR9300_OTP_STATUS	0x15f18
+#define AR9300_OTP_STATUS_TYPE		0x7
+#define AR9300_OTP_STATUS_VALID		0x4
+#define AR9300_OTP_STATUS_ACCESS_BUSY	0x2
+#define AR9300_OTP_STATUS_SM_BUSY	0x1
+#define AR9300_OTP_READ_DATA	0x15f1c
+
+ /*
+  * DDR_CTRL block
+  */
+@@ -149,6 +157,13 @@
+ #define AR934X_DDR_REG_FLUSH_PCIE	0xa8
+ #define AR934X_DDR_REG_FLUSH_WMAC	0xac
+ 
+#define AR934X_OTP_BASE					0x30000
+#define AR934X_OTP_STATUS				0x31018
+#define AR934X_OTP_READ_DATA				0x3101c
+#define AR934X_OTP_INTF2_ADDRESS			0x31008
+#define AR934X_OTP_INTF3_ADDRESS			0x3100c
+#define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS	0x31034
+
+ /*
+  * PLL block
+  */
--- a/target/linux/ar71xx/patches-4.9/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
+++ b/target/linux/ar71xx/patches-4.9/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
+@@ -309,6 +309,16 @@ bool __init ar93xx_wmac_read_mac_address
+ 	return ret;
+ }
+ 
+void __init ath79_wmac_disable_2ghz(void)
+{
+	ath79_wmac_data.disable_2ghz = true;
+}
+
+void __init ath79_wmac_disable_5ghz(void)
+{
+	ath79_wmac_data.disable_5ghz = true;
+}
+
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ 	if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
+++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,6 +14,9 @@
+ 
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
+void ath79_wmac_disable_2ghz(void);
+void ath79_wmac_disable_5ghz(void);
+
+ bool ar93xx_wmac_read_mac_address(u8 *dest);
+ 
+ #endif /* _ATH79_DEV_WMAC_H */
--- a/target/linux/ar71xx/patches-4.9/525-MIPS-ath79-enable-qca-usb-quirks.patch
+++ b/target/linux/ar71xx/patches-4.9/525-MIPS-ath79-enable-qca-usb-quirks.patch
@ -0,0 +1,101 @@
+--- a/arch/mips/ath79/dev-usb.c
+++ b/arch/mips/ath79/dev-usb.c
+@@ -37,6 +37,8 @@ static struct usb_ehci_pdata ath79_ehci_
+ static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
+ 	.caps_offset		= 0x100,
+ 	.has_tt			= 1,
+	.qca_force_host_mode	= 1,
+	.qca_force_16bit_ptw	= 1,
+ };
+ 
+ static void __init ath79_usb_register(const char *name, int id,
+@@ -159,6 +161,9 @@ static void __init ar913x_usb_setup(void
+ 	ath79_device_reset_clear(AR913X_RESET_USB_PHY);
+ 	mdelay(10);
+ 
+	ath79_ehci_pdata_v2.qca_force_host_mode	= 0;
+	ath79_ehci_pdata_v2.qca_force_16bit_ptw	= 0;
+
+ 	ath79_usb_register("ehci-platform", -1,
+ 			   AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
+ 			   ATH79_CPU_IRQ(3),
+@@ -182,14 +187,34 @@ static void __init ar933x_usb_setup(void
+ 			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+-static void __init ar934x_usb_setup(void)
+static void enable_tx_tx_idp_violation_fix(unsigned base)
+ {
+-	u32 bootstrap;
+	void __iomem *phy_reg;
+	u32 t;
+
+	phy_reg = ioremap(base, 4);
+	if (!phy_reg)
+		return;
+
+	t = ioread32(phy_reg);
+	t &= ~0xff;
+	t |= 0x58;
+	iowrite32(t, phy_reg);
+
+	iounmap(phy_reg);
+}
+ 
+-	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+-	if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
+static void ar934x_usb_reset_notifier(struct platform_device *pdev)
+{
+	if (pdev->id != -1)
+ 		return;
+ 
+	enable_tx_tx_idp_violation_fix(0x18116c94);
+	dev_info(&pdev->dev, "TX-TX IDP fix enabled\n");
+}
+
+static void __init ar934x_usb_setup(void)
+{
+ 	ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
+ 	udelay(1000);
+ 
+@@ -202,14 +227,40 @@ static void __init ar934x_usb_setup(void
+ 	ath79_device_reset_clear(AR934X_RESET_USB_HOST);
+ 	udelay(1000);
+ 
+	if (ath79_soc_rev >= 3)
+		ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier;
+
+ 	ath79_usb_register("ehci-platform", -1,
+ 			   AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
+ 			   ATH79_CPU_IRQ(3),
+ 			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
+static void qca955x_usb_reset_notifier(struct platform_device *pdev)
+{
+	u32 base;
+
+	switch (pdev->id) {
+	case 0:
+		base = 0x18116c94;
+		break;
+
+	case 1:
+		base = 0x18116e54;
+		break;
+
+	default:
+		return;
+	}
+
+	enable_tx_tx_idp_violation_fix(base);
+	dev_info(&pdev->dev, "TX-TX IDP fix enabled\n");
+}
+
+ static void __init qca955x_usb_setup(void)
+ {
+	ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier;
+
+ 	ath79_usb_register("ehci-platform", 0,
+ 			   QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
+ 			   ATH79_IP3_IRQ(0),
--- a/target/linux/ar71xx/patches-4.9/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-4.9/601-MIPS-ath79-add-more-register-defines.patch
@ -0,0 +1,455 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -20,6 +20,10 @@
+ #include <linux/bitops.h>
+ 
+ #define AR71XX_APB_BASE		0x18000000
+#define AR71XX_GE0_BASE		0x19000000
+#define AR71XX_GE0_SIZE		0x10000
+#define AR71XX_GE1_BASE		0x1a000000
+#define AR71XX_GE1_SIZE		0x10000
+ #define AR71XX_EHCI_BASE	0x1b000000
+ #define AR71XX_EHCI_SIZE	0x1000
+ #define AR71XX_OHCI_BASE	0x1c000000
+@@ -39,6 +43,8 @@
+ #define AR71XX_PLL_SIZE		0x100
+ #define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE	0x100
+#define AR71XX_MII_BASE		(AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE		0x100
+ 
+ #define AR71XX_PCI_MEM_BASE	0x10000000
+ #define AR71XX_PCI_MEM_SIZE	0x07000000
+@@ -81,15 +87,21 @@
+ 
+ #define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+ #define AR933X_UART_SIZE	0x14
+#define AR933X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE	0x04
+ #define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define AR933X_WMAC_SIZE	0x20000
+ #define AR933X_EHCI_BASE	0x1b000000
+ #define AR933X_EHCI_SIZE	0x1000
+ 
+#define AR934X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE	0x14
+ #define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define AR934X_WMAC_SIZE	0x20000
+ #define AR934X_EHCI_BASE	0x1b000000
+ #define AR934X_EHCI_SIZE	0x200
+#define AR934X_NFC_BASE		0x1b000200
+#define AR934X_NFC_SIZE		0xb8
+ #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE	0x1000
+ 
+@@ -106,11 +118,15 @@
+ #define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
+ #define QCA955X_PCI_CTRL_SIZE	0x100
+ 
+#define QCA955X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE	0x40
+ #define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE	0x20000
+ #define QCA955X_EHCI0_BASE	0x1b000000
+ #define QCA955X_EHCI1_BASE	0x1b400000
+ #define QCA955X_EHCI_SIZE	0x1000
+#define QCA955X_NFC_BASE	0x1b800200
+#define QCA955X_NFC_SIZE	0xb8
+ 
+ #define AR9300_OTP_BASE		0x14000
+ #define AR9300_OTP_STATUS	0x15f18
+@@ -181,6 +197,9 @@
+ #define AR71XX_AHB_DIV_SHIFT		20
+ #define AR71XX_AHB_DIV_MASK		0x7
+ 
+#define AR71XX_ETH0_PLL_SHIFT		17
+#define AR71XX_ETH1_PLL_SHIFT		19
+
+ #define AR724X_PLL_REG_CPU_CONFIG	0x00
+ #define AR724X_PLL_REG_PCIE_CONFIG	0x10
+ 
+@@ -196,6 +215,8 @@
+ #define AR724X_DDR_DIV_SHIFT		22
+ #define AR724X_DDR_DIV_MASK		0x3
+ 
+#define AR7242_PLL_REG_ETH0_INT_CLOCK	0x2c
+
+ #define AR913X_PLL_REG_CPU_CONFIG	0x00
+ #define AR913X_PLL_REG_ETH_CONFIG	0x04
+ #define AR913X_PLL_REG_ETH0_INT_CLOCK	0x14
+@@ -208,6 +229,9 @@
+ #define AR913X_AHB_DIV_SHIFT		19
+ #define AR913X_AHB_DIV_MASK		0x1
+ 
+#define AR913X_ETH0_PLL_SHIFT		20
+#define AR913X_ETH1_PLL_SHIFT		22
+
+ #define AR933X_PLL_CPU_CONFIG_REG	0x00
+ #define AR933X_PLL_CLOCK_CTRL_REG	0x08
+ 
+@@ -229,6 +253,8 @@
+ #define AR934X_PLL_CPU_CONFIG_REG		0x00
+ #define AR934X_PLL_DDR_CONFIG_REG		0x04
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG		0x2c
+ 
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+@@ -261,9 +287,13 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+ 
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
+
+ #define QCA955X_PLL_CPU_CONFIG_REG		0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG		0x04
+ #define QCA955X_PLL_CLK_CTRL_REG		0x08
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
+ 
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+@@ -388,16 +418,83 @@
+ #define AR913X_RESET_USB_HOST		BIT(5)
+ #define AR913X_RESET_USB_PHY		BIT(4)
+ 
+#define AR933X_RESET_GE1_MDIO		BIT(23)
+#define AR933X_RESET_GE0_MDIO		BIT(22)
+#define AR933X_RESET_GE1_MAC		BIT(13)
+ #define AR933X_RESET_WMAC		BIT(11)
+#define AR933X_RESET_GE0_MAC		BIT(9)
+ #define AR933X_RESET_USB_HOST		BIT(5)
+ #define AR933X_RESET_USB_PHY		BIT(4)
+ #define AR933X_RESET_USBSUS_OVERRIDE	BIT(3)
+ 
+#define AR934X_RESET_HOST		BIT(31)
+#define AR934X_RESET_SLIC		BIT(30)
+#define AR934X_RESET_HDMA		BIT(29)
+#define AR934X_RESET_EXTERNAL		BIT(28)
+#define AR934X_RESET_RTC		BIT(27)
+#define AR934X_RESET_PCIE_EP_INT	BIT(26)
+#define AR934X_RESET_CHKSUM_ACC		BIT(25)
+#define AR934X_RESET_FULL_CHIP		BIT(24)
+#define AR934X_RESET_GE1_MDIO		BIT(23)
+#define AR934X_RESET_GE0_MDIO		BIT(22)
+#define AR934X_RESET_CPU_NMI		BIT(21)
+#define AR934X_RESET_CPU_COLD		BIT(20)
+#define AR934X_RESET_HOST_RESET_INT	BIT(19)
+#define AR934X_RESET_PCIE_EP		BIT(18)
+#define AR934X_RESET_UART1		BIT(17)
+#define AR934X_RESET_DDR		BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF		BIT(14)
+#define AR934X_RESET_GE1_MAC		BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG	BIT(12)
+ #define AR934X_RESET_USB_PHY_ANALOG	BIT(11)
+#define AR934X_RESET_HOST_DMA_INT	BIT(10)
+#define AR934X_RESET_GE0_MAC		BIT(9)
+#define AR934X_RESET_ETH_SWITCH		BIT(8)
+#define AR934X_RESET_PCIE_PHY		BIT(7)
+#define AR934X_RESET_PCIE		BIT(6)
+ #define AR934X_RESET_USB_HOST		BIT(5)
+ #define AR934X_RESET_USB_PHY		BIT(4)
+ #define AR934X_RESET_USBSUS_OVERRIDE	BIT(3)
+#define AR934X_RESET_LUT		BIT(2)
+#define AR934X_RESET_MBOX		BIT(1)
+#define AR934X_RESET_I2S		BIT(0)
+
+#define QCA955X_RESET_HOST		BIT(31)
+#define QCA955X_RESET_SLIC		BIT(30)
+#define QCA955X_RESET_HDMA		BIT(29)
+#define QCA955X_RESET_EXTERNAL		BIT(28)
+#define QCA955X_RESET_RTC		BIT(27)
+#define QCA955X_RESET_PCIE_EP_INT	BIT(26)
+#define QCA955X_RESET_CHKSUM_ACC	BIT(25)
+#define QCA955X_RESET_FULL_CHIP		BIT(24)
+#define QCA955X_RESET_GE1_MDIO		BIT(23)
+#define QCA955X_RESET_GE0_MDIO		BIT(22)
+#define QCA955X_RESET_CPU_NMI		BIT(21)
+#define QCA955X_RESET_CPU_COLD		BIT(20)
+#define QCA955X_RESET_HOST_RESET_INT	BIT(19)
+#define QCA955X_RESET_PCIE_EP		BIT(18)
+#define QCA955X_RESET_UART1		BIT(17)
+#define QCA955X_RESET_DDR		BIT(16)
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA955X_RESET_NANDF		BIT(14)
+#define QCA955X_RESET_GE1_MAC		BIT(13)
+#define QCA955X_RESET_SGMII_ANALOG	BIT(12)
+#define QCA955X_RESET_USB_PHY_ANALOG	BIT(11)
+#define QCA955X_RESET_HOST_DMA_INT	BIT(10)
+#define QCA955X_RESET_GE0_MAC		BIT(9)
+#define QCA955X_RESET_SGMII		BIT(8)
+#define QCA955X_RESET_PCIE_PHY		BIT(7)
+#define QCA955X_RESET_PCIE		BIT(6)
+#define QCA955X_RESET_USB_HOST		BIT(5)
+#define QCA955X_RESET_USB_PHY		BIT(4)
+#define QCA955X_RESET_USBSUS_OVERRIDE	BIT(3)
+#define QCA955X_RESET_LUT		BIT(2)
+#define QCA955X_RESET_MBOX		BIT(1)
+#define QCA955X_RESET_I2S		BIT(0)
+ 
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN	BIT(18)
+#define AR933X_BOOTSTRAP_EEPBUSY	BIT(4)
+ #define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
+ 
+ #define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
+@@ -539,8 +636,22 @@
+ #define AR71XX_GPIO_REG_INT_ENABLE	0x24
+ #define AR71XX_GPIO_REG_FUNC		0x28
+ 
+#define AR934X_GPIO_REG_OUT_FUNC0	0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1	0x30
+#define AR934X_GPIO_REG_OUT_FUNC2	0x34
+#define AR934X_GPIO_REG_OUT_FUNC3	0x38
+#define AR934X_GPIO_REG_OUT_FUNC4	0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5	0x40
+ #define AR934X_GPIO_REG_FUNC		0x6c
+ 
+#define QCA955X_GPIO_REG_OUT_FUNC0	0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1	0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2	0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3	0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4	0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5	0x40
+#define QCA955X_GPIO_REG_FUNC		0x6c
+
+ #define AR71XX_GPIO_COUNT		16
+ #define AR7240_GPIO_COUNT		18
+ #define AR7241_GPIO_COUNT		20
+@@ -570,4 +681,235 @@
+ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
+ #define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
+ 
+#define AR71XX_GPIO_FUNC_STEREO_EN		BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN		BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN		BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN		BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN		BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN		BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN		BIT(0)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN		BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN			BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN		BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN		BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN		BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN		BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN		BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN		BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
+
+#define AR913X_GPIO_FUNC_WMAC_LED_EN		BIT(22)
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN		BIT(21)
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN		BIT(20)
+#define AR913X_GPIO_FUNC_I2S_MCKEN		BIT(19)
+#define AR913X_GPIO_FUNC_I2S1_EN		BIT(18)
+#define AR913X_GPIO_FUNC_I2S0_EN		BIT(17)
+#define AR913X_GPIO_FUNC_SLIC_EN		BIT(16)
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN		BIT(9)
+#define AR913X_GPIO_FUNC_UART_EN		BIT(8)
+#define AR913X_GPIO_FUNC_USB_CLK_EN		BIT(4)
+
+#define AR933X_GPIO_FUNC_SPDIF2TCK		BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN		BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN		BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN		BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN		BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL	BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL	BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT	BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN			BIT(18)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN		BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
+
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN		BIT(9)
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN		BIT(8)
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN		BIT(7)
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN		BIT(6)
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN		BIT(5)
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN		BIT(4)
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN		BIT(3)
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN		BIT(2)
+#define AR934X_GPIO_FUNC_JTAG_DISABLE		BIT(1)
+
+#define AR934X_GPIO_OUT_GPIO		0
+#define AR934X_GPIO_OUT_SPI_CS1	7
+#define AR934X_GPIO_OUT_LED_LINK0	41
+#define AR934X_GPIO_OUT_LED_LINK1	42
+#define AR934X_GPIO_OUT_LED_LINK2	43
+#define AR934X_GPIO_OUT_LED_LINK3	44
+#define AR934X_GPIO_OUT_LED_LINK4	45
+#define AR934X_GPIO_OUT_EXT_LNA0	46
+#define AR934X_GPIO_OUT_EXT_LNA1	47
+
+#define QCA955X_GPIO_FUNC_CLK_OBS7_EN		BIT(9)
+#define QCA955X_GPIO_FUNC_CLK_OBS6_EN		BIT(8)
+#define QCA955X_GPIO_FUNC_CLK_OBS5_EN		BIT(7)
+#define QCA955X_GPIO_FUNC_CLK_OBS4_EN		BIT(6)
+#define QCA955X_GPIO_FUNC_CLK_OBS3_EN		BIT(5)
+#define QCA955X_GPIO_FUNC_CLK_OBS2_EN		BIT(4)
+#define QCA955X_GPIO_FUNC_CLK_OBS1_EN		BIT(3)
+#define QCA955X_GPIO_FUNC_JTAG_DISABLE		BIT(1)
+
+#define QCA955X_GPIO_OUT_GPIO		0
+#define QCA955X_MII_EXT_MDI		1
+#define QCA955X_SLIC_DATA_OUT		3
+#define QCA955X_SLIC_PCM_FS		4
+#define QCA955X_SLIC_PCM_CLK		5
+#define QCA955X_SPI_CLK			8
+#define QCA955X_SPI_CS_0		9
+#define QCA955X_SPI_CS_1		10
+#define QCA955X_SPI_CS_2		11
+#define QCA955X_SPI_MISO		12
+#define QCA955X_I2S_CLK			13
+#define QCA955X_I2S_WS			14
+#define QCA955X_I2S_SD			15
+#define QCA955X_I2S_MCK			16
+#define QCA955X_SPDIF_OUT		17
+#define QCA955X_UART1_TD		18
+#define QCA955X_UART1_RTS		19
+#define QCA955X_UART1_RD		20
+#define QCA955X_UART1_CTS		21
+#define QCA955X_UART0_SOUT		22
+#define QCA955X_SPDIF2_OUT		23
+#define QCA955X_LED_SGMII_SPEED0	24
+#define QCA955X_LED_SGMII_SPEED1	25
+#define QCA955X_LED_SGMII_DUPLEX	26
+#define QCA955X_LED_SGMII_LINK_UP	27
+#define QCA955X_SGMII_SPEED0_INVERT	28
+#define QCA955X_SGMII_SPEED1_INVERT	29
+#define QCA955X_SGMII_DUPLEX_INVERT	30
+#define QCA955X_SGMII_LINK_UP_INVERT	31
+#define QCA955X_GE1_MII_MDO		32
+#define QCA955X_GE1_MII_MDC		33
+#define QCA955X_SWCOM2			38
+#define QCA955X_SWCOM3			39
+#define QCA955X_MAC2_GPIO		40
+#define QCA955X_MAC3_GPIO		41
+#define QCA955X_ATT_LED			42
+#define QCA955X_PWR_LED			43
+#define QCA955X_TX_FRAME		44
+#define QCA955X_RX_CLEAR_EXTERNAL	45
+#define QCA955X_LED_NETWORK_EN		46
+#define QCA955X_LED_POWER_EN		47
+#define QCA955X_WMAC_GLUE_WOW		68
+#define QCA955X_RX_CLEAR_EXTENSION	70
+#define QCA955X_CP_NAND_CS1		73
+#define QCA955X_USB_SUSPEND		74
+#define QCA955X_ETH_TX_ERR		75
+#define QCA955X_DDR_DQ_OE		76
+#define QCA955X_CLKREQ_N_EP		77
+#define QCA955X_CLKREQ_N_RC		78
+#define QCA955X_CLK_OBS0		79
+#define QCA955X_CLK_OBS1		80
+#define QCA955X_CLK_OBS2		81
+#define QCA955X_CLK_OBS3		82
+#define QCA955X_CLK_OBS4		83
+#define QCA955X_CLK_OBS5		84
+
+/*
+ * MII_CTRL block
+ */
+#define AR71XX_MII_REG_MII0_CTRL	0x00
+#define AR71XX_MII_REG_MII1_CTRL	0x04
+
+#define AR71XX_MII_CTRL_IF_MASK		3
+#define AR71XX_MII_CTRL_SPEED_SHIFT	4
+#define AR71XX_MII_CTRL_SPEED_MASK	3
+#define AR71XX_MII_CTRL_SPEED_10	0
+#define AR71XX_MII_CTRL_SPEED_100	1
+#define AR71XX_MII_CTRL_SPEED_1000	2
+
+#define AR71XX_MII0_CTRL_IF_GMII	0
+#define AR71XX_MII0_CTRL_IF_MII		1
+#define AR71XX_MII0_CTRL_IF_RGMII	2
+#define AR71XX_MII0_CTRL_IF_RMII	3
+
+#define AR71XX_MII1_CTRL_IF_RGMII	0
+#define AR71XX_MII1_CTRL_IF_RMII	1
+
+/*
+ * AR933X GMAC interface
+ */
+#define AR933X_GMAC_REG_ETH_CFG		0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0	BIT(0)
+#define AR933X_ETH_CFG_MII_GE0		BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0		BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER	BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN	BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP	BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0		BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10	0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100	BIT(10)
+
+/*
+ * AR934X GMAC Interface
+ */
+#define AR934X_GMAC_REG_ETH_CFG		0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0	BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0	BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0	BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER	BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE	BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN	BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE	BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP	BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS	BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0	BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY        BIT(14)
+#define AR934X_ETH_CFG_RXD_DELAY_MASK   0x3
+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT  14
+#define AR934X_ETH_CFG_RDV_DELAY        BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
+
+/*
+ * QCA955X GMAC Interface
+ */
+
+#define QCA955X_GMAC_REG_ETH_CFG	0x00
+
+#define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
+#define QCA955X_ETH_CFG_MII_GE0		BIT(1)
+#define QCA955X_ETH_CFG_GMII_GE0	BIT(2)
+#define QCA955X_ETH_CFG_MII_GE0_MASTER	BIT(3)
+#define QCA955X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
+#define QCA955X_ETH_CFG_GE0_ERR_EN	BIT(5)
+#define QCA955X_ETH_CFG_GE0_SGMII	BIT(6)
+#define QCA955X_ETH_CFG_RMII_GE0	BIT(10)
+#define QCA955X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
+#define QCA955X_ETH_CFG_RMII_GE0_MASTER	BIT(12)
+#define QCA955X_ETH_CFG_RXD_DELAY_MASK	0x3
+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT	14
+#define QCA955X_ETH_CFG_RDV_DELAY	BIT(16)
+#define QCA955X_ETH_CFG_RDV_DELAY_MASK	0x3
+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT	16
+#define QCA955X_ETH_CFG_TXD_DELAY_MASK	0x3
+#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT	18
+#define QCA955X_ETH_CFG_TXE_DELAY_MASK	0x3
+#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT	20
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
--- a/target/linux/ar71xx/patches-4.9/602-MIPS-ath79-add-openwrt-stuff.patch
+++ b/target/linux/ar71xx/patches-4.9/602-MIPS-ath79-add-openwrt-stuff.patch
@ -0,0 +1,49 @@
+--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
+@@ -98,6 +98,20 @@ config SOC_QCA955X
+ 	select PCI_AR724X if PCI
+ 	def_bool n
+ 
+config ATH79_DEV_M25P80
+	select ATH79_DEV_SPI
+	def_bool n
+
+config ATH79_DEV_AP9X_PCI
+	select ATH79_PCI_ATH9K_FIXUP
+	def_bool n
+
+config ATH79_DEV_DSA
+	def_bool n
+
+config ATH79_DEV_ETH
+	def_bool n
+
+ config PCI_AR724X
+ 	def_bool n
+ 
+@@ -107,6 +121,10 @@ config ATH79_DEV_GPIO_BUTTONS
+ config ATH79_DEV_LEDS_GPIO
+ 	def_bool n
+ 
+config ATH79_DEV_NFC
+	depends on (SOC_AR934X || SOC_QCA955X)
+	def_bool n
+
+ config ATH79_DEV_SPI
+ 	def_bool n
+ 
+@@ -117,4 +135,14 @@ config ATH79_DEV_WMAC
+ 	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+ 	def_bool n
+ 
+config ATH79_NVRAM
+	def_bool n
+
+config ATH79_PCI_ATH9K_FIXUP
+	def_bool n
+
+config ATH79_ROUTERBOOT
+	select LZO_DECOMPRESS
+	def_bool n
+
+ endif
--- a/Show More
+++ b/Show More
				`@ -1 +0,0 @@`
				`CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd"`