diff --git a/target/linux/ipq60xx/files/arch/arm64/boot/dts/qcom/ipq6018-mr7350.dts b/target/linux/ipq60xx/files/arch/arm64/boot/dts/qcom/ipq6018-mr7350.dts index 25d8d1f36..8e5cc8453 100644 --- a/target/linux/ipq60xx/files/arch/arm64/boot/dts/qcom/ipq6018-mr7350.dts +++ b/target/linux/ipq60xx/files/arch/arm64/boot/dts/qcom/ipq6018-mr7350.dts @@ -206,11 +206,23 @@ }; }; +&qusb_phy_0 { + status = "okay"; +}; + +&ssphy_0 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + &wifi { status = "okay"; }; -&i2c_1 { +&blsp1_i2c3 { pinctrl-0 = <&i2c_1_pins>; pinctrl-names = "default"; status = "okay"; diff --git a/target/linux/ipq60xx/patches-5.15/0138-arm64-dts-qcom-ipq6018-add-usb3-DT-description.patch b/target/linux/ipq60xx/patches-5.15/0138-arm64-dts-qcom-ipq6018-add-usb3-DT-description.patch index 3568a7bcd..f9f65841d 100644 --- a/target/linux/ipq60xx/patches-5.15/0138-arm64-dts-qcom-ipq6018-add-usb3-DT-description.patch +++ b/target/linux/ipq60xx/patches-5.15/0138-arm64-dts-qcom-ipq6018-add-usb3-DT-description.patch @@ -16,8 +16,6 @@ Link: https://lore.kernel.org/r/ebc2d340d566fa2d43127e253d5b8b134a87a78e.1630389 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 83 +++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) -diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -index 7b6205c180df1b..c79ba072e88f3b 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -671,6 +671,89 @@ diff --git a/target/linux/ipq60xx/patches-5.15/0139-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch b/target/linux/ipq60xx/patches-5.15/0139-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch new file mode 100644 index 000000000..ed6f131dc --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0139-arm64-dts-qcom-Correct-QMP-PHY-child-node-name.patch @@ -0,0 +1,36 @@ +From 1351512f29b4348e6b497f6343896c1033d409b4 Mon Sep 17 00:00:00 2001 +From: Shawn Guo +Date: Wed, 29 Sep 2021 11:42:47 +0800 +Subject: [PATCH] arm64: dts: qcom: Correct QMP PHY child node name + +Many child nodes of QMP PHY are named without following bindings schema +and causing dtbs_check warnings like below. + +phy@1c06000: 'lane@1c06800' does not match any of the regexes: '^phy@[0-9a-f]+$' + arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml + arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml + +Correct them to fix the warnings. + +Signed-off-by: Shawn Guo +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20210929034253.24570-5-shawn.guo@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -401,7 +401,7 @@ + reset-names = "phy", + "common"; + +- pcie_phy0: lane@84200 { ++ pcie_phy0: phy@84200 { + reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ + <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ + <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ diff --git a/target/linux/ipq60xx/patches-5.15/0140-arm64-dts-qcom-ipq6018-Remove-unused-qcom_config-pipe-trust-reg.patch b/target/linux/ipq60xx/patches-5.15/0140-arm64-dts-qcom-ipq6018-Remove-unused-qcom_config-pipe-trust-reg.patch new file mode 100644 index 000000000..36cfa2270 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0140-arm64-dts-qcom-ipq6018-Remove-unused-qcom_config-pipe-trust-reg.patch @@ -0,0 +1,42 @@ +From 62b177fcdfdfda69f3a0cb740f8b3ac24f95e8c1 Mon Sep 17 00:00:00 2001 +From: Bhupesh Sharma +Date: Wed, 13 Oct 2021 16:25:23 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq6018: Remove unused + 'qcom,config-pipe-trust-reg' property + +'qcom,config-pipe-trust-reg' property doesn't seem to be +used by the qcom, bam_dma driver, so remove the same +from 'ipq6018' dts. + +This is a preparatory patch for subsequent patch in +this series which converts the qcom_bam_dma device-tree +binding into YAML format. + +Without this change, 'make dtbs_check' leads to the following +error: + $ arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: + dma-controller@704000: 'qcom,config-pipe-trust-reg' does not match + any of the regexes: 'pinctrl-[0-9]+' + +Fix the same. + +Cc: Thara Gopinath +Cc: Bjorn Andersson +Cc: Rob Herring +Signed-off-by: Bhupesh Sharma +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20211013105541.68045-3-bhupesh.sharma@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -201,7 +201,6 @@ + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; +- qcom,config-pipe-trust-reg = <0>; + }; + + crypto: crypto@73a000 { diff --git a/target/linux/ipq60xx/patches-5.15/0141-arm64-dts-qcom-ipq6018-Remove-unused-iface_clk-property.patch b/target/linux/ipq60xx/patches-5.15/0141-arm64-dts-qcom-ipq6018-Remove-unused-iface_clk-property.patch new file mode 100644 index 000000000..459ca7ff3 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0141-arm64-dts-qcom-ipq6018-Remove-unused-iface_clk-property.patch @@ -0,0 +1,45 @@ +From 82f07cbd408993551bd3e4cf51da1bb822f61f26 Mon Sep 17 00:00:00 2001 +From: Bhupesh Sharma +Date: Wed, 13 Oct 2021 16:25:24 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq6018: Remove unused 'iface_clk' property + from dma-controller node + +'iface_clk' clock is not used by the +qcom, bam_dma driver, so remove the same from 'ipq6018' dts. + +This is a preparatory patch for subsequent patch in +this series which converts the qcom_bam_dma device-tree +binding into YAML format. + +Without this change, 'make dtbs_check' leads to the following +error: + $ arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: + dma-controller@7984000: clock-names: ['iface_clk', 'bam_clk'] + is too long + +Fix the same. + +Cc: Thara Gopinath +Cc: Bjorn Andersson +Cc: Rob Herring +Signed-off-by: Bhupesh Sharma +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20211013105541.68045-4-bhupesh.sharma@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -346,9 +346,8 @@ + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x07984000 0x0 0x1a000>; + interrupts = ; +- clocks = <&gcc GCC_QPIC_CLK>, +- <&gcc GCC_QPIC_AHB_CLK>; +- clock-names = "iface_clk", "bam_clk"; ++ clocks = <&gcc GCC_QPIC_AHB_CLK>; ++ clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; diff --git a/target/linux/ipq60xx/patches-5.15/0142-arm64-dts-qcom-ipq6018-add-pcie-max-link-speed.patch b/target/linux/ipq60xx/patches-5.15/0142-arm64-dts-qcom-ipq6018-add-pcie-max-link-speed.patch new file mode 100644 index 000000000..cc7ca39b6 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0142-arm64-dts-qcom-ipq6018-add-pcie-max-link-speed.patch @@ -0,0 +1,26 @@ +From e3e8a472429923d1c430bf388e9e3df1d9cc63a7 Mon Sep 17 00:00:00 2001 +From: Baruch Siach +Date: Mon, 27 Dec 2021 08:46:03 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add pcie max-link-speed + +Add the generic 'max-link-speed' property to describe the IPQ6018 PCIe +link generation limit. This allows the generic dwc code to configure the +link speed correctly. + +Signed-off-by: Baruch Siach +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/fcf41277cf8529437374a5c10b2b1fcad30cd7c2.1640587131.git.baruch@tkos.co.il +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -425,6 +425,7 @@ + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; ++ max-link-speed = <3>; + #address-cells = <3>; + #size-cells = <2>; + diff --git a/target/linux/ipq60xx/patches-5.15/0143-arm64-dts-qcom-ipq6018-fix-usb-reference-period.patch b/target/linux/ipq60xx/patches-5.15/0143-arm64-dts-qcom-ipq6018-fix-usb-reference-period.patch new file mode 100644 index 000000000..4a01ad51d --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0143-arm64-dts-qcom-ipq6018-fix-usb-reference-period.patch @@ -0,0 +1,29 @@ +From d1c10ab1494f09eb12fa6e58fc78bb28d44922ae Mon Sep 17 00:00:00 2001 +From: Baruch Siach +Date: Thu, 20 Jan 2022 20:43:41 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: fix usb reference period + +Reference clock period for rate of 24MHz is 41ns (0x29). + +Link: https://lore.kernel.org/r/1965fc315525b8ab26cf9f71f939c24d@codeaurora.org +Link: https://lore.kernel.org/r/a1932eba-564c-fe32-f220-53aa75250105@seco.com +Fixes: 20bb9e3dd2e4 ("arm64: dts: qcom: ipq6018: add usb3 DT description") +Reported-by: Kathiravan T +Signed-off-by: Baruch Siach +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/4f4df55cf44cd0fd7d773aca171d4f48662fb1a5.1642704221.git.baruch@tkos.co.il +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -749,7 +749,7 @@ + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; +- snps,ref-clock-period-ns = <0x32>; ++ snps,ref-clock-period-ns = <0x29>; + dr_mode = "host"; + }; + }; diff --git a/target/linux/ipq60xx/patches-5.15/0144-arm64-dts-ipq6018-Use-reference-clock-to-set-dwc3-period.patch b/target/linux/ipq60xx/patches-5.15/0144-arm64-dts-ipq6018-Use-reference-clock-to-set-dwc3-period.patch new file mode 100644 index 000000000..40f47f2b2 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0144-arm64-dts-ipq6018-Use-reference-clock-to-set-dwc3-period.patch @@ -0,0 +1,34 @@ +From 5726079cd4860c190722445e01e1007e40a9ccb4 Mon Sep 17 00:00:00 2001 +From: Sean Anderson +Date: Thu, 27 Jan 2022 15:06:36 -0500 +Subject: [PATCH] arm64: dts: ipq6018: Use reference clock to set dwc3 period + +Instead of manually setting snps,ref-clock-period-ns, we can let the +driver calculate it automatically from the "ref" clock. I haven't +reviewed this board's schematics, so please let me know if this is the +wrong 24MHz clock to use. + +Signed-off-by: Sean Anderson +Link: https://lore.kernel.org/r/20220127200636.1456175-8-sean.anderson@seco.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -744,12 +744,13 @@ + interrupts = ; + phys = <&qusb_phy_0>, <&usb0_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; ++ clocks = <&xo>; ++ clock-names = "ref"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; +- snps,ref-clock-period-ns = <0x29>; + dr_mode = "host"; + }; + }; diff --git a/target/linux/ipq60xx/patches-5.15/0145-arm64-dts-qcom-ipq6018-enable-the-GICv2m-supporte.patch b/target/linux/ipq60xx/patches-5.15/0145-arm64-dts-qcom-ipq6018-enable-the-GICv2m-supporte.patch new file mode 100644 index 000000000..b2c7f9012 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0145-arm64-dts-qcom-ipq6018-enable-the-GICv2m-supporte.patch @@ -0,0 +1,40 @@ +From 3d44861d006b18649306cbade242c865e9068b6e Mon Sep 17 00:00:00 2001 +From: Kathiravan T +Date: Tue, 8 Feb 2022 21:05:25 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq6018: enable the GICv2m support + +GIC used in the IPQ6018 SoCs has one instance of the GICv2m extension, +which supports upto 32 MSI interrupts. Lets add support for the same. + +Signed-off-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/1644334525-11577-3-git-send-email-quic_kathirav@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -373,6 +373,8 @@ + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; ++ #address-cells = <2>; ++ #size-cells = <2>; + interrupt-controller; + #interrupt-cells = <0x3>; + reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ +@@ -380,6 +382,13 @@ + <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ + <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ + interrupts = ; ++ ranges = <0 0 0 0xb00a000 0 0xffd>; ++ ++ v2m@0 { ++ compatible = "arm,gic-v2m-frame"; ++ msi-controller; ++ reg = <0x0 0x0 0x0 0xffd>; ++ }; + }; + + pcie_phy: phy@84000 { diff --git a/target/linux/ipq60xx/patches-5.15/0146-arm64-dts-qcom-ipq6018-drop-the-clock-frequency-property.patch b/target/linux/ipq60xx/patches-5.15/0146-arm64-dts-qcom-ipq6018-drop-the-clock-frequency-property.patch new file mode 100644 index 000000000..db3eff579 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0146-arm64-dts-qcom-ipq6018-drop-the-clock-frequency-property.patch @@ -0,0 +1,26 @@ +From 01b8c4aff332ecc13fbafc16550e621ba969c167 Mon Sep 17 00:00:00 2001 +From: Kathiravan T +Date: Wed, 2 Feb 2022 22:05:09 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq6018: drop the clock-frequency property + +clock-frequency for IPQ6018 SoCs should be 24MHz, not 19.2MHz. Rather +than correcting it, drop the property itself since its already +configured by the bootloader. + +Signed-off-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/1643819709-5410-3-git-send-email-quic_kathirav@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -530,7 +530,6 @@ + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0b120000 0x0 0x1000>; +- clock-frequency = <19200000>; + + frame@b120000 { + frame-number = <0>; diff --git a/target/linux/ipq60xx/patches-5.15/0147-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-schema.patch b/target/linux/ipq60xx/patches-5.15/0147-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-schema.patch new file mode 100644 index 000000000..64078bea7 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0147-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-schema.patch @@ -0,0 +1,39 @@ +From 0e1b27f4f69e86b8b62ba5bedb78936341433247 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Tue, 5 Apr 2022 08:34:43 +0200 +Subject: [PATCH] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema + +The DT schema expects dma channels in tx-rx order. No functional +change. + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 +++---- + 1 files changed, 3 insertions(+), 5 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -322,8 +322,8 @@ + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; +- dmas = <&blsp_dma 15>, <&blsp_dma 14>; +- dma-names = "rx", "tx"; ++ dmas = <&blsp_dma 14>, <&blsp_dma 15>; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + +@@ -337,8 +337,8 @@ + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; +- dmas = <&blsp_dma 17>, <&blsp_dma 16>; +- dma-names = "rx", "tx"; ++ dmas = <&blsp_dma 16>, <&blsp_dma 17>; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + diff --git a/target/linux/ipq60xx/patches-5.15/0148-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schema.patch b/target/linux/ipq60xx/patches-5.15/0148-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schema.patch new file mode 100644 index 000000000..3f1ee1629 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0148-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schema.patch @@ -0,0 +1,42 @@ +From 2374b99e19ac7f2beca2d4e62ebb96803db0e66b Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Tue, 5 Apr 2022 08:34:44 +0200 +Subject: [PATCH] arm64: dts: qcom: align clocks in I2C/SPI with DT schema + +The DT schema expects clocks core-iface order. No functional change. + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 ++--- + 1 files changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -318,9 +318,9 @@ + #size-cells = <0>; + reg = <0x0 0x078b6000 0x0 0x600>; + interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; +- clock-names = "iface", "core"; ++ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; +@@ -333,9 +333,9 @@ + #size-cells = <0>; + reg = <0x0 0x078b7000 0x0 0x600>; + interrupts = ; +- clocks = <&gcc GCC_BLSP1_AHB_CLK>, +- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; +- clock-names = "iface", "core"; ++ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; diff --git a/target/linux/ipq60xx/patches-5.15/0149-arm64-dts-qcom-ipq6018-Fix-qmp-usb3-phy-node.patch b/target/linux/ipq60xx/patches-5.15/0149-arm64-dts-qcom-ipq6018-Fix-qmp-usb3-phy-node.patch new file mode 100644 index 000000000..fb86131fe --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0149-arm64-dts-qcom-ipq6018-Fix-qmp-usb3-phy-node.patch @@ -0,0 +1,48 @@ +From 7011db96f69316e8055961b366ac92b6c28403dd Mon Sep 17 00:00:00 2001 +From: Bhupesh Sharma +Date: Mon, 28 Feb 2022 18:00:17 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq6018: Fix qmp usb3 phy node + +Fix the following 'make dtbs_check' warning(s) by +using phy@ instead of lanes@ and by moving '#clock-cells' to +sub-node: + +arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: ssphy@78000: + 'lane@78200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' + +Cc: Bjorn Andersson +Cc: Rob Herring +Signed-off-by: Bhupesh Sharma +Reviewed-by: Shawn Guo +[bjorn: s/clock-names/clock-cells/ per Shawn's feedback] +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220228123019.382037-7-bhupesh.sharma@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -683,7 +683,6 @@ + reg = <0x0 0x78000 0x0 0x1C4>; + #address-cells = <2>; + #size-cells = <2>; +- #clock-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB0_AUX_CLK>, +@@ -695,12 +694,13 @@ + reset-names = "phy","common"; + status = "disabled"; + +- usb0_ssphy: lane@78200 { ++ usb0_ssphy: phy@78200 { + reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ + <0x0 0x00078400 0x0 0x200>, /* Rx */ + <0x0 0x00078800 0x0 0x1F8>, /* PCS */ + <0x0 0x00078600 0x0 0x044>; /* PCS misc */ + #phy-cells = <0>; ++ #clock-cells = <1>; + clocks = <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_usb0_pipe_clk_src"; diff --git a/target/linux/ipq60xx/patches-5.15/0150-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addresses.patch b/target/linux/ipq60xx/patches-5.15/0150-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addresses.patch new file mode 100644 index 000000000..5fb75235c --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0150-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addresses.patch @@ -0,0 +1,45 @@ +From b77a1c4d6b058d801645a9f46030e7f8829628b2 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Wed, 4 May 2022 15:19:16 +0200 +Subject: [PATCH] arm64: dts: qcom: correct DWC3 node names and unit addresses + +Align DWC3 USB node names with DT schema ("usb" is expected) and correct +the unit addresses to match the "reg" property. This also implies +overriding nodes by label, instead of full path. + +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220504131923.214367-7-krzysztof.kozlowski@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 +++--- + 1 files changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -643,7 +643,7 @@ + status = "disabled"; + }; + +- usb2: usb2@7000000 { ++ usb2: usb@70f8800 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x070F8800 0x0 0x400>; + #address-cells = <2>; +@@ -720,7 +720,7 @@ + status = "disabled"; + }; + +- usb3: usb3@8A00000 { ++ usb3: usb@8af8800 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x8AF8800 0x0 0x400>; + #address-cells = <2>; +@@ -746,7 +746,7 @@ + resets = <&gcc GCC_USB0_BCR>; + status = "disabled"; + +- dwc_0: usb@8A00000 { ++ dwc_0: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x8A00000 0x0 0xcd00>; + interrupts = ; diff --git a/target/linux/ipq60xx/patches-5.15/0151-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch b/target/linux/ipq60xx/patches-5.15/0151-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch new file mode 100644 index 000000000..0d1fc7113 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0151-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch @@ -0,0 +1,37 @@ +From 8d5fd4e4d4e3c128d5afa925bf98c98e66a5205b Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Wed, 4 May 2022 15:19:22 +0200 +Subject: [PATCH] arm64: dts: qcom: align DWC3 USB clocks with DT schema + +Align order of clocks and their names with Qualcomm DWC3 USB DT schema. +No functional impact expected. + +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220504131923.214367-13-krzysztof.kozlowski@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 +++--- + 1 files changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -652,7 +652,7 @@ + clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_SLEEP_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; +- clock-names = "master", ++ clock-names = "core", + "sleep", + "mock_utmi"; + +@@ -731,8 +731,8 @@ + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; +- clock-names = "sys_noc_axi", +- "master", ++ clock-names = "cfg_noc", ++ "core", + "sleep", + "mock_utmi"; + diff --git a/target/linux/ipq60xx/patches-5.15/0152-arm64-dts-qcom-align-OPP-table-names-with-DT-schema.patch b/target/linux/ipq60xx/patches-5.15/0152-arm64-dts-qcom-align-OPP-table-names-with-DT-schema.patch new file mode 100644 index 000000000..6a3b4f1a2 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0152-arm64-dts-qcom-align-OPP-table-names-with-DT-schema.patch @@ -0,0 +1,32 @@ +From 0e3e654696074b304302c7cc2a67314b7875f1ae Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Mon, 27 Jun 2022 11:32:50 +0200 +Subject: [PATCH] arm64: dts: qcom: align OPP table names with DT schema + +DT schema expects names of operating points tables to start with +"opp-table": + + ipq6018-cp01-c1.dtb: cpu_opp_table: $nodename:0: 'cpu_opp_table' does not match '^opp-table(-[a-z0-9]+)?$' + +Use hyphens instead of underscores, fix the names to match DT schema or +remove the prefix entirely when it is not needed. + +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Bjorn Andersson +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220627093250.84391-1-krzysztof.kozlowski@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -87,7 +87,7 @@ + }; + }; + +- cpu_opp_table: cpu_opp_table { ++ cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + diff --git a/target/linux/ipq60xx/patches-5.15/0153-arm64-dts-qcom-timer-should-use-only-32-bit-size.patch b/target/linux/ipq60xx/patches-5.15/0153-arm64-dts-qcom-timer-should-use-only-32-bit-size.patch new file mode 100644 index 000000000..9c5cddf5a --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0153-arm64-dts-qcom-timer-should-use-only-32-bit-size.patch @@ -0,0 +1,94 @@ +From 458ebdbb8e5d596a462d8125cec74142ff5dfa97 Mon Sep 17 00:00:00 2001 +From: David Heidelberg +Date: Sun, 26 Jun 2022 12:57:59 +0200 +Subject: [PATCH] arm64: dts: qcom: timer should use only 32-bit size + +There's no reason the timer needs > 32-bits of address or size. +Since we using 32-bit size, we need to define ranges properly. + +Fixes warnings as: +``` +arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: timer@17c90000: #size-cells:0:0: 1 was expected + From schema: Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml +``` + +Signed-off-by: David Heidelberg +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220626105800.35586-1-david@ixit.cz +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 22 +++++++++++----------- + 1 files changed, 11 insertions(+), 11 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -525,9 +525,9 @@ + }; + + timer@b120000 { +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0 0x10000000>; + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0b120000 0x0 0x1000>; + +@@ -535,49 +535,49 @@ + frame-number = <0>; + interrupts = , + ; +- reg = <0x0 0x0b121000 0x0 0x1000>, +- <0x0 0x0b122000 0x0 0x1000>; ++ reg = <0x0b121000 0x1000>, ++ <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; +- reg = <0x0 0xb123000 0x0 0x1000>; ++ reg = <0x0b123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; +- reg = <0x0 0x0b124000 0x0 0x1000>; ++ reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; +- reg = <0x0 0x0b125000 0x0 0x1000>; ++ reg = <0x0b125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; +- reg = <0x0 0x0b126000 0x0 0x1000>; ++ reg = <0x0b126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; +- reg = <0x0 0x0b127000 0x0 0x1000>; ++ reg = <0x0b127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; +- reg = <0x0 0x0b128000 0x0 0x1000>; ++ reg = <0x0b128000 0x1000>; + status = "disabled"; + }; + }; diff --git a/target/linux/ipq60xx/patches-5.15/0154-arm64-dts-qcom-adjust-whitespace-around-.patch b/target/linux/ipq60xx/patches-5.15/0154-arm64-dts-qcom-adjust-whitespace-around-.patch new file mode 100644 index 000000000..5d9d06308 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0154-arm64-dts-qcom-adjust-whitespace-around-.patch @@ -0,0 +1,36 @@ +From 372cf591acbca3bd9a729742ea4c81d7f99f1b6e Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Thu, 26 May 2022 22:42:47 +0200 +Subject: [PATCH] arm64: dts: qcom: adjust whitespace around '=' + +Fix whitespace coding style: use single space instead of tabs or +multiple spaces around '=' sign in property assignment. No functional +changes (same DTB). + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- + 1 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -321,7 +321,7 @@ + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; +- clock-frequency = <400000>; ++ clock-frequency = <400000>; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + status = "disabled"; +@@ -336,7 +336,7 @@ + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; +- clock-frequency = <400000>; ++ clock-frequency = <400000>; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; + status = "disabled"; diff --git a/target/linux/ipq60xx/patches-5.15/0155-arm64-dts-qcom-ipq6018-add-label-to-remoteproc-node.patch b/target/linux/ipq60xx/patches-5.15/0155-arm64-dts-qcom-ipq6018-add-label-to-remoteproc-node.patch new file mode 100644 index 000000000..69a6f9410 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0155-arm64-dts-qcom-ipq6018-add-label-to-remoteproc-node.patch @@ -0,0 +1,26 @@ +From f0b255b4f012055ab12137ecc1b68dfe12b06107 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Tue, 17 May 2022 09:01:10 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add label to remoteproc node + +glink-edge bindings require label: + + ipq6018-cp01-c1.dtb: glink-edge: 'label' is a required property + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220517070113.18023-10-krzysztof.kozlowski@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -621,6 +621,7 @@ + + glink-edge { + interrupts = ; ++ label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + diff --git a/target/linux/ipq60xx/patches-5.15/0156-arm64-dts-qcom-ipq6018-correct-QUP-peripheral-labels.patch b/target/linux/ipq60xx/patches-5.15/0156-arm64-dts-qcom-ipq6018-correct-QUP-peripheral-labels.patch new file mode 100644 index 000000000..ed9a75ac7 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0156-arm64-dts-qcom-ipq6018-correct-QUP-peripheral-labels.patch @@ -0,0 +1,82 @@ +From f82c48d468521cd9d1a31797c6f9e6cac6f7c1b3 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 4 Jun 2022 17:30:03 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: correct QUP peripheral labels + +Current QUP peripheral labels like spi_0 and i2c_0 dont really tell what is +the exact QUP HW being used as there are actually 6 identical QUP HW blocks +for UART, SPI and I2C. +For example current i2c_0 label actually points to the QUP2 I2C HW. + +This style of labeling does not follow what the rest of Qualcomm SoC-s use, +for example IPQ8074 which has the identical QUP blocks. +It also makes it really hard to add the missing QUP DT nodes as there are +multiple missing. + +So utilize the same style as other Qualcomm SoC-s are using and update the +CP01 DTS as its the current sole user of them. + +Signed-off-by: Robert Marko +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220604153003.55172-1-robimarko@gmail.com +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++-- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 ++++---- + 2 files changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -29,13 +29,13 @@ + status = "okay"; + }; + +-&i2c_1 { ++&blsp1_i2c3 { + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + +-&spi_0 { ++&blsp1_spi1 { + cs-select = <0>; + status = "okay"; + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -282,7 +282,7 @@ + status = "disabled"; + }; + +- spi_0: spi@78b5000 { ++ blsp1_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; +@@ -297,7 +297,7 @@ + status = "disabled"; + }; + +- spi_1: spi@78b6000 { ++ blsp1_spi2: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; +@@ -312,7 +312,7 @@ + status = "disabled"; + }; + +- i2c_0: i2c@78b6000 { ++ blsp1_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; +@@ -327,7 +327,7 @@ + status = "disabled"; + }; + +- i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ ++ blsp1_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/ipq60xx/patches-5.15/0157-arm64-dts-qcom-extend-scm-compatible-strings.patch b/target/linux/ipq60xx/patches-5.15/0157-arm64-dts-qcom-extend-scm-compatible-strings.patch new file mode 100644 index 000000000..48902f55e --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0157-arm64-dts-qcom-extend-scm-compatible-strings.patch @@ -0,0 +1,26 @@ +From b9c0c0e5da43ff3aa6dd93e2f994dc889dd5b261 Mon Sep 17 00:00:00 2001 +From: David Heidelberg +Date: Sun, 26 Jun 2022 20:32:46 +0200 +Subject: [PATCH] arm64: dts: qcom: extend scm compatible strings + +First device specific compatible, then general one. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: David Heidelberg +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220626183247.142776-2-david@ixit.cz +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -125,7 +125,7 @@ + + firmware { + scm { +- compatible = "qcom,scm"; ++ compatible = "qcom,scm-ipq6018", "qcom,scm"; + }; + }; + diff --git a/target/linux/ipq60xx/patches-5.15/0158-arm64-dts-qcom-ipq6018-drop-USB-PHY-clock-index.patch b/target/linux/ipq60xx/patches-5.15/0158-arm64-dts-qcom-ipq6018-drop-USB-PHY-clock-index.patch new file mode 100644 index 000000000..f834e3abd --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0158-arm64-dts-qcom-ipq6018-drop-USB-PHY-clock-index.patch @@ -0,0 +1,27 @@ +From 9215a64a0776c4797ed08520655fba7e85530156 Mon Sep 17 00:00:00 2001 +From: Johan Hovold +Date: Tue, 5 Jul 2022 13:40:21 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: drop USB PHY clock index + +The QMP USB PHY provides a single clock so drop the redundant clock +index. + +Signed-off-by: Johan Hovold +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220705114032.22787-4-johan+linaro@kernel.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -701,7 +701,7 @@ + <0x0 0x00078800 0x0 0x1F8>, /* PCS */ + <0x0 0x00078600 0x0 0x044>; /* PCS misc */ + #phy-cells = <0>; +- #clock-cells = <1>; ++ #clock-cells = <0>; + clocks = <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_usb0_pipe_clk_src"; diff --git a/target/linux/ipq60xx/patches-5.15/0159-arm64-dts-qcom-ipq6018-add-missing-TCSR-syscon-compatible.patch b/target/linux/ipq60xx/patches-5.15/0159-arm64-dts-qcom-ipq6018-add-missing-TCSR-syscon-compatible.patch new file mode 100644 index 000000000..7f9c23684 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0159-arm64-dts-qcom-ipq6018-add-missing-TCSR-syscon-compatible.patch @@ -0,0 +1,25 @@ +From d30bcfa4408596e8dd3714dfdd90334d2bdc9856 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Fri, 9 Sep 2022 11:20:25 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add missing TCSR syscon compatible + +TCSR syscon node should come with dedicated compatible. + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220909092035.223915-6-krzysztof.kozlowski@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -258,7 +258,7 @@ + }; + + tcsr: syscon@1937000 { +- compatible = "syscon"; ++ compatible = "qcom,tcsr-ipq6018", "syscon"; + reg = <0x0 0x01937000 0x0 0x21000>; + }; + diff --git a/target/linux/ipq60xx/patches-5.15/0160-arm64-dts-qcom-ipq6018-switch-TCSR-mutex-to-MMIO.patch b/target/linux/ipq60xx/patches-5.15/0160-arm64-dts-qcom-ipq6018-switch-TCSR-mutex-to-MMIO.patch new file mode 100644 index 000000000..8b5e1662b --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0160-arm64-dts-qcom-ipq6018-switch-TCSR-mutex-to-MMIO.patch @@ -0,0 +1,49 @@ +From f5e303aefc06b7508d7a490f9a2d80e4dc134c70 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Fri, 9 Sep 2022 11:20:31 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: switch TCSR mutex to MMIO + +The TCSR mutex bindings allow device to be described only with address +space (so it uses MMIO, not syscon regmap). This seems reasonable as +TCSR mutex is actually a dedicated IO address space and it also fixes DT +schema checks: + + qcom/ipq6018-cp01-c1.dtb: hwlock: 'reg' is a required property + qcom/ipq6018-cp01-c1.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220909092035.223915-12-krzysztof.kozlowski@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 ++++--------- + 1 file changed, 4 insertions(+), 9 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -129,12 +129,6 @@ + }; + }; + +- tcsr_mutex: hwlock { +- compatible = "qcom,tcsr-mutex"; +- syscon = <&tcsr_mutex_regs 0 0x80>; +- #hwlock-cells = <1>; +- }; +- + pmuv8: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + +- tcsr_mutex_regs: syscon@1905000 { +- compatible = "syscon"; +- reg = <0x0 0x01905000 0x0 0x8000>; ++ tcsr_mutex: hwlock@1905000 { ++ compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; ++ reg = <0x0 0x01905000 0x0 0x1000>; ++ #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { diff --git a/target/linux/ipq60xx/patches-5.15/0161-arm64-dts-qcom-ipq6018-fix-NAND-node-name.patch b/target/linux/ipq60xx/patches-5.15/0161-arm64-dts-qcom-ipq6018-fix-NAND-node-name.patch new file mode 100644 index 000000000..b8fee6bb5 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0161-arm64-dts-qcom-ipq6018-fix-NAND-node-name.patch @@ -0,0 +1,24 @@ +From 00c5b40d342565ece46d23b9e124a6ecade49afd Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 27 Sep 2022 15:14:13 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: fix NAND node name + +Per schema it should be nand-controller@79b0000 instead of nand@79b0000. +Fix it to match nand-controller.yaml requirements. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -348,7 +348,7 @@ + status = "disabled"; + }; + +- qpic_nand: nand@79b0000 { ++ qpic_nand: nand-controller@79b0000 { + compatible = "qcom,ipq6018-nand"; + reg = <0x0 0x079b0000 0x0 0x10000>; + #address-cells = <1>; diff --git a/target/linux/ipq60xx/patches-5.15/0162-arm64-dts-qcom-ipq6018-move-ARMv8-timer-out-of-SoC-node.patch b/target/linux/ipq60xx/patches-5.15/0162-arm64-dts-qcom-ipq6018-move-ARMv8-timer-out-of-SoC-node.patch new file mode 100644 index 000000000..ede481641 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0162-arm64-dts-qcom-ipq6018-move-ARMv8-timer-out-of-SoC-node.patch @@ -0,0 +1,48 @@ +From 555a31aaa3c5e6d9edcb48239e87d9fa52c31284 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 27 Sep 2022 22:07:14 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node + +The ARM timer is usually considered not part of SoC node, just like +other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: + +arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'} + From schema: dtschema/schemas/simple-bus.yaml + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -511,14 +511,6 @@ + clock-names = "xo"; + }; + +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; +@@ -760,6 +752,14 @@ + }; + }; + ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; diff --git a/target/linux/ipq60xx/patches-5.15/0163-arm64-dts-qcom-ipq6018-add-QUP6-I2C-node.patch b/target/linux/ipq60xx/patches-5.15/0163-arm64-dts-qcom-ipq6018-add-QUP6-I2C-node.patch new file mode 100644 index 000000000..32d1eec53 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0163-arm64-dts-qcom-ipq6018-add-QUP6-I2C-node.patch @@ -0,0 +1,36 @@ +From 50867cfbbd1ed91870b660536ed1e459c8c4b1d2 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 4 Jun 2022 21:15:26 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add QUP6 I2C node + +Add node to support QUP6 I2C controller in IPQ6018. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -337,6 +337,21 @@ + status = "disabled"; + }; + ++ blsp1_i2c6: i2c@78ba000 { ++ compatible = "qcom,i2c-qup-v2.2.1"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x078ba000 0x0 0x600>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ clock-frequency = <400000>; ++ dmas = <&blsp_dma 22>, <&blsp_dma 23>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x07984000 0x0 0x1a000>; diff --git a/target/linux/ipq60xx/patches-5.15/0164-arm64-dts-qcom-ipq6018-add-MP5496-LDO2-node.patch b/target/linux/ipq60xx/patches-5.15/0164-arm64-dts-qcom-ipq6018-add-MP5496-LDO2-node.patch new file mode 100644 index 000000000..27ba532ad --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0164-arm64-dts-qcom-ipq6018-add-MP5496-LDO2-node.patch @@ -0,0 +1,27 @@ +From 5ef3b4abce82a56fbbfe99ee5ba112f64eef596a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 6 Jun 2022 23:16:44 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add MP5496 LDO2 node + +Add support for the MP5496 LDO2 which is the SDHCI VQMMC supply. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -817,6 +817,12 @@ + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; ++ ++ ipq6018_l2: l2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; + }; + }; + }; diff --git a/target/linux/ipq60xx/patches-5.15/0165-arm64-dts-qcom-ipq6018-add-SDHCI-controller-node.patch b/target/linux/ipq60xx/patches-5.15/0165-arm64-dts-qcom-ipq6018-add-SDHCI-controller-node.patch new file mode 100644 index 000000000..1b10a59c8 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0165-arm64-dts-qcom-ipq6018-add-SDHCI-controller-node.patch @@ -0,0 +1,47 @@ +From b5a258e564a70e0fed38ada2a03e99688fc38e85 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 6 Jun 2022 23:46:28 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add SDHCI controller node + +Add the required DT node for SDCC v5 SDHCI controller. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -257,6 +257,32 @@ + reg = <0x0 0x01937000 0x0 0x21000>; + }; + ++ sdhci: mmc@780400 { ++ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; ++ reg = <0x0 0x07804000 0x0 0x1000>, ++ <0x0 0x07805000 0x0 0x1000>, ++ <0x0 0x07808000 0x0 0x2000>; ++ reg-names = "hc", "cqhci", "ice"; ++ ++ interrupts = , ++ ; ++ interrupt-names = "hc_irq", "pwr_irq"; ++ ++ clocks = <&gcc GCC_SDCC1_AHB_CLK>, ++ <&gcc GCC_SDCC1_APPS_CLK>, ++ <&xo>, ++ <&gcc GCC_SDCC1_ICE_CORE_CLK>; ++ clock-names = "iface", "core", "xo", "ice"; ++ resets = <&gcc GCC_SDCC1_BCR>; ++ max-frequency = <192000000>; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ sd-uhs-sdr104; ++ bus-width = <8>; ++ vqmmc-supply = <&ipq6018_l2>; ++ status = "disabled"; ++ }; ++ + blsp_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x07884000 0x0 0x2b000>; diff --git a/target/linux/ipq60xx/patches-5.15/0166-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch b/target/linux/ipq60xx/patches-5.15/0166-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch new file mode 100644 index 000000000..ff9e9e51a --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0166-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch @@ -0,0 +1,33 @@ +From 3513844ff4d3057e384c5b59604462938375285a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 27 Sep 2022 12:50:08 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add QFPROM node + +Add QFPROM node to IPQ6018 and expose the CPU speed bin only for now. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -179,6 +179,18 @@ + dma-ranges; + compatible = "simple-bus"; + ++ qfprom: efuse@a4000 { ++ compatible = "qcom,ipq6018-qfprom", "qcom,qfprom"; ++ reg = <0x0 0xa4000 0x0 0x2000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpu_speed_bin: cpu_speed_bin@135 { ++ reg = <0x135 0x1>; ++ bits = <7 1>; ++ }; ++ }; ++ + prng: qrng@e1000 { + compatible = "qcom,prng-ee"; + reg = <0x0 0xe3000 0x0 0x1000>; diff --git a/target/linux/ipq60xx/patches-5.15/0167-arm64-dts-qcom-ipq6018-align-TLMM-pin-configuration-with-DT-schema.patch b/target/linux/ipq60xx/patches-5.15/0167-arm64-dts-qcom-ipq6018-align-TLMM-pin-configuration-with-DT-schema.patch new file mode 100644 index 000000000..dd0ed3717 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0167-arm64-dts-qcom-ipq6018-align-TLMM-pin-configuration-with-DT-schema.patch @@ -0,0 +1,54 @@ +From eed2617c6a237f46db3ed2b63f6dff158407e468 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Tue, 27 Sep 2022 19:36:30 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: align TLMM pin configuration with + DT schema + +DT schema expects TLMM pin configuration nodes to be named with +'-state' suffix and their optional children with '-pins' suffix. + +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Bjorn Andersson +Reviewed-by: Konrad Dybcio +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++-- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -49,13 +49,13 @@ + }; + + &tlmm { +- i2c_1_pins: i2c-1-pins { ++ i2c_1_pins: i2c-1-state { + pins = "gpio42", "gpio43"; + function = "blsp2_i2c"; + drive-strength = <8>; + }; + +- spi_0_pins: spi-0-pins { ++ spi_0_pins: spi-0-state { + pins = "gpio38", "gpio39", "gpio40", "gpio41"; + function = "blsp0_spi"; + drive-strength = <8>; +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -230,14 +230,14 @@ + interrupt-controller; + #interrupt-cells = <2>; + +- serial_3_pins: serial3-pinmux { ++ serial_3_pins: serial3-state { + pins = "gpio44", "gpio45"; + function = "blsp2_uart"; + drive-strength = <8>; + bias-pull-down; + }; + +- qpic_pins: qpic-pins { ++ qpic_pins: qpic-state { + pins = "gpio1", "gpio3", "gpio4", + "gpio5", "gpio6", "gpio7", + "gpio8", "gpio10", "gpio11", diff --git a/target/linux/ipq60xx/patches-5.15/0168-clk-qcom-ipq6018-fix-networking-resets.patch b/target/linux/ipq60xx/patches-5.15/0168-clk-qcom-ipq6018-fix-networking-resets.patch new file mode 100644 index 000000000..53e227d1e --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0168-clk-qcom-ipq6018-fix-networking-resets.patch @@ -0,0 +1,60 @@ +From a9305e6356be71bdfee35913bdf78b52cdbeaf73 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 10 Oct 2022 23:24:15 +0200 +Subject: [PATCH] clk: qcom: ipq6018: fix networking resets + +Networking resets in IPQ6018 all use bitmask as they require multiple +bits to be set and cleared instead of a single bit. + +So, current networking resets have the same register and bit 0 set which +is clearly incorrect. + +Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") +Signed-off-by: Robert Marko +--- + drivers/clk/qcom/gcc-ipq6018.c | 32 ++++++++++++++++---------------- + 1 file changed, 16 insertions(+), 16 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq6018.c ++++ b/drivers/clk/qcom/gcc-ipq6018.c +@@ -4517,24 +4517,24 @@ static const struct qcom_reset_map gcc_i + [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 }, + [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 }, + [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 }, +- [GCC_PPE_FULL_RESET] = { 0x68014, 0 }, +- [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 }, ++ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 }, ++ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 }, + [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 }, +- [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 }, ++ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 }, + [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 }, +- [GCC_EDMA_HW_RESET] = { 0x68014, 0 }, +- [GCC_NSSPORT1_RESET] = { 0x68014, 0 }, +- [GCC_NSSPORT2_RESET] = { 0x68014, 0 }, +- [GCC_NSSPORT3_RESET] = { 0x68014, 0 }, +- [GCC_NSSPORT4_RESET] = { 0x68014, 0 }, +- [GCC_NSSPORT5_RESET] = { 0x68014, 0 }, +- [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 }, +- [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 }, +- [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 }, +- [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 }, +- [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 }, +- [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 }, +- [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 }, ++ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 }, ++ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 }, ++ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c }, ++ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 }, ++ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 }, ++ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 }, ++ [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 }, ++ [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 }, ++ [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 }, ++ [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 }, ++ [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 }, ++ [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 }, ++ [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 }, + [GCC_LPASS_BCR] = {0x1F000, 0}, + [GCC_UBI32_TBU_BCR] = {0x65000, 0}, + [GCC_LPASS_TBU_BCR] = {0x6C000, 0}, diff --git a/target/linux/ipq60xx/patches-5.15/0169-arm64-dts-qcom-align-SPI-NOR-node-name-with-dtschema.patch b/target/linux/ipq60xx/patches-5.15/0169-arm64-dts-qcom-align-SPI-NOR-node-name-with-dtschema.patch new file mode 100644 index 000000000..ea47b1ba1 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0169-arm64-dts-qcom-align-SPI-NOR-node-name-with-dtschema.patch @@ -0,0 +1,25 @@ +From 2b6d37f6b7fe2f98197b77adcce81d4198aeb305 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Thu, 7 Apr 2022 16:31:12 +0200 +Subject: [PATCH] arm64: dts: qcom: align SPI NOR node name with dtschema + +The node names should be generic and SPI NOR dtschema expects "flash". + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220407143112.294930-2-krzysztof.kozlowski@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -39,7 +39,7 @@ + cs-select = <0>; + status = "okay"; + +- m25p80@0 { ++ flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; diff --git a/target/linux/ipq60xx/patches-5.15/0170-arm64-dts-qcom-ipq6018-cp01-c1-fix-Micron-SPI-NOR-compatible.patch b/target/linux/ipq60xx/patches-5.15/0170-arm64-dts-qcom-ipq6018-cp01-c1-fix-Micron-SPI-NOR-compatible.patch new file mode 100644 index 000000000..bf9df18d8 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0170-arm64-dts-qcom-ipq6018-cp01-c1-fix-Micron-SPI-NOR-compatible.patch @@ -0,0 +1,27 @@ +From 693b6207fc7fbfe81aa9759ef82c3953245641d9 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Sat, 21 May 2022 18:45:49 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018-cp01-c1: fix Micron SPI NOR + compatible + +The proper compatible for Micron n25q128a11 SPI NOR flash should include +vendor-prefix. + +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220521164550.91115-11-krzysztof.kozlowski@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -43,7 +43,7 @@ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; +- compatible = "n25q128a11"; ++ compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + }; + }; diff --git a/target/linux/ipq60xx/patches-5.15/0171-arm64-dts-qcom-ipq6018-cp01-c1-use-BLSPI1-pins.patch b/target/linux/ipq60xx/patches-5.15/0171-arm64-dts-qcom-ipq6018-cp01-c1-use-BLSPI1-pins.patch new file mode 100644 index 000000000..0f3f9b4a6 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0171-arm64-dts-qcom-ipq6018-cp01-c1-use-BLSPI1-pins.patch @@ -0,0 +1,28 @@ +From 18c806ced5fdd066d3ab03c74690348d6118b96f Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Tue, 27 Sep 2022 19:36:29 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018-cp01-c1: use BLSPI1 pins + +When BLSPI1 (originally SPI0, later renamed in commit f82c48d46852 +("arm64: dts: qcom: ipq6018: correct QUP peripheral labels")) was added, +the device node lacked respective pin configuration assignment. + +Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes") +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Bjorn Andersson +Reviewed-by: Konrad Dybcio +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -37,6 +37,8 @@ + + &blsp1_spi1 { + cs-select = <0>; ++ pinctrl-0 = <&spi_0_pins>; ++ pinctrl-names = "default"; + status = "okay"; + + flash@0 { diff --git a/target/linux/ipq60xx/patches-5.15/0172-arm64-dts-qcom-cp01-c1-enable-SDHCI-controller.patch b/target/linux/ipq60xx/patches-5.15/0172-arm64-dts-qcom-cp01-c1-enable-SDHCI-controller.patch new file mode 100644 index 000000000..7a970c36e --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0172-arm64-dts-qcom-cp01-c1-enable-SDHCI-controller.patch @@ -0,0 +1,61 @@ +From 743ac0846de33fd4e3af03b5a94689027de9c479 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 6 Jun 2022 23:47:21 +0200 +Subject: [PATCH] arm64: dts: qcom: cp01-c1: enable SDHCI controller + +Enable the SDHCI controller for onboard uSD card slot. +CD and WP GPIO-s are present. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 25 ++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -8,6 +8,7 @@ + /dts-v1/; + + #include "ipq6018.dtsi" ++#include + + / { + model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; +@@ -63,6 +64,20 @@ + drive-strength = <8>; + bias-pull-down; + }; ++ ++ sdio_pins: sdio-state { ++ cd-pins { ++ pins = "gpio62"; ++ function = "gpio"; ++ bias-pull-up; ++ }; ++ ++ wp-pins { ++ pins = "gpio63"; ++ function = "gpio"; ++ bias-pull-down; ++ }; ++ }; + }; + + &qpic_bam { +@@ -81,6 +96,16 @@ + }; + }; + ++&sdhci { ++ status = "okay"; ++ ++ pinctrl-0 = <&sdio_pins>; ++ pinctrl-names = "default"; ++ cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; ++ wp-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>; ++ bus-width = <4>; ++}; ++ + &qusb_phy_1 { + status = "ok"; + }; diff --git a/target/linux/ipq60xx/patches-5.15/0173-arm64-dts-qcom-cp01-c1-remove-bootargs-append.patch b/target/linux/ipq60xx/patches-5.15/0173-arm64-dts-qcom-cp01-c1-remove-bootargs-append.patch new file mode 100644 index 000000000..4e8c83282 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0173-arm64-dts-qcom-cp01-c1-remove-bootargs-append.patch @@ -0,0 +1,23 @@ +From 3e461b07274d5c10120c201f825cc77d2126ab8a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 7 Jun 2022 00:09:08 +0200 +Subject: [PATCH] arm64: dts: qcom: cp01-c1: remove bootargs-append + +bootargs-append is a leftover from the vendor SDK, and does not exist +in the mainline kernel at all, so remove it. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -20,7 +20,6 @@ + + chosen { + stdout-path = "serial0:115200n8"; +- bootargs-append = " swiotlb=1"; + }; + }; + diff --git a/target/linux/ipq60xx/patches-5.15/0174-arm64-dts-qcom-cp01-c1-use-okay-instead-of-ok.patch b/target/linux/ipq60xx/patches-5.15/0174-arm64-dts-qcom-cp01-c1-use-okay-instead-of-ok.patch new file mode 100644 index 000000000..430517560 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0174-arm64-dts-qcom-cp01-c1-use-okay-instead-of-ok.patch @@ -0,0 +1,26 @@ +From 381329da5b7f33a7f48d10405af65c6d68108fc1 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 7 Jun 2022 00:13:46 +0200 +Subject: [PATCH] arm64: dts: qcom: cp01-c1: use "okay" instead of "ok" + +Use "okay" instead of "ok" in USB nodes as "ok" is deprecated. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -106,9 +106,9 @@ + }; + + &qusb_phy_1 { +- status = "ok"; ++ status = "okay"; + }; + + &usb2 { +- status = "ok"; ++ status = "okay"; + }; diff --git a/target/linux/ipq60xx/patches-5.15/0175-arm64-dts-qcom-cp01-c1-enable-USB3.0.patch b/target/linux/ipq60xx/patches-5.15/0175-arm64-dts-qcom-cp01-c1-enable-USB3.0.patch new file mode 100644 index 000000000..672c7428f --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0175-arm64-dts-qcom-cp01-c1-enable-USB3.0.patch @@ -0,0 +1,33 @@ +From cb9032f20e1f3230cb761ce5cd1558471f108bd6 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 7 Jun 2022 00:14:42 +0200 +Subject: [PATCH] arm64: dts: qcom: cp01-c1: enable USB3.0 + +Enable the USB3.0 controller as Type-C port is connected to it. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -105,6 +105,18 @@ + bus-width = <4>; + }; + ++&qusb_phy_0 { ++ status = "okay"; ++}; ++ ++&ssphy_0 { ++ status = "okay"; ++}; ++ ++&usb3 { ++ status = "okay"; ++}; ++ + &qusb_phy_1 { + status = "okay"; + }; diff --git a/target/linux/ipq60xx/patches-5.15/0176-arm64-dts-qcom-cp01-c1-enable-PCIe.patch b/target/linux/ipq60xx/patches-5.15/0176-arm64-dts-qcom-cp01-c1-enable-PCIe.patch new file mode 100644 index 000000000..d92cba1e7 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0176-arm64-dts-qcom-cp01-c1-enable-PCIe.patch @@ -0,0 +1,30 @@ +From 2504aba5d9de54aef522151a86e43baeedb77436 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 7 Jun 2022 15:13:03 +0200 +Subject: [PATCH] arm64: dts: qcom: cp01-c1: enable PCIe + +CP01 has a M.2 Key E slot with a single lane PCIe 3.0. +So enable the node and add the PERST and WAKE GPIO-s. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -124,3 +124,14 @@ + &usb2 { + status = "okay"; + }; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ status = "okay"; ++ ++ perst-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>; ++}; diff --git a/target/linux/ipq60xx/patches-5.15/0177-arm64-dts-qcom-cp01-c1-add-MDIO-PHY-s.patch b/target/linux/ipq60xx/patches-5.15/0177-arm64-dts-qcom-cp01-c1-add-MDIO-PHY-s.patch new file mode 100644 index 000000000..96531f738 --- /dev/null +++ b/target/linux/ipq60xx/patches-5.15/0177-arm64-dts-qcom-cp01-c1-add-MDIO-PHY-s.patch @@ -0,0 +1,81 @@ +From 829ec1663e492824458f2b0f0cdbbe0662a65e1e Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 7 Jun 2022 15:31:00 +0200 +Subject: [PATCH] arm64: dts: qcom: cp01-c1: add MDIO PHY-s + +Add the required DT nodes for the onboard QCA8075 and QCA8081 ethernet +PHY-s. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 55 ++++++++++++++++++++ + 1 file changed, 55 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts ++++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +@@ -77,6 +77,22 @@ + bias-pull-down; + }; + }; ++ ++ mdio_pins: mdio-state { ++ mdc-pins { ++ pins = "gpio64"; ++ function = "mdc"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ ++ mdio-pins { ++ pins = "gpio65"; ++ function = "mdio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ }; + }; + + &qpic_bam { +@@ -135,3 +151,42 @@ + perst-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>; + }; ++ ++&mdio { ++ status = "okay"; ++ ++ pinctrl-0 = <&mdio_pins>; ++ pinctrl-names = "default"; ++ reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; ++ ++ ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ }; ++ ++ ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++ ++ ethernet-phy@2 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <2>; ++ }; ++ ++ ethernet-phy@3 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <3>; ++ }; ++ ++ ethernet-phy@4 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <4>; ++ }; ++ ++ ethernet-phy@24 { ++ compatible = "ethernet-phy-id004d.d101"; ++ reg = <24>; ++ reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; ++ }; ++}; diff --git a/target/linux/ipq60xx/patches-5.15/1001-arm64-dts-qcom-ipq6018-Add-mdio-bus-description.patch b/target/linux/ipq60xx/patches-5.15/1001-arm64-dts-qcom-ipq6018-Add-mdio-bus-description.patch index c3d04ad7e..7d0fd7407 100644 --- a/target/linux/ipq60xx/patches-5.15/1001-arm64-dts-qcom-ipq6018-Add-mdio-bus-description.patch +++ b/target/linux/ipq60xx/patches-5.15/1001-arm64-dts-qcom-ipq6018-Add-mdio-bus-description.patch @@ -16,7 +16,7 @@ Link: https://lore.kernel.org/r/ef01a79ccc6ef86dc3a10d0fa3331794d49e9859.1646031 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -623,6 +623,16 @@ +@@ -671,6 +671,16 @@ }; }; diff --git a/target/linux/ipq60xx/patches-5.15/1004-clk-qcom-ipq6018-add-missing-clocks.patch b/target/linux/ipq60xx/patches-5.15/1004-clk-qcom-ipq6018-add-missing-clocks.patch index 0ecfc9538..89f9e5c35 100644 --- a/target/linux/ipq60xx/patches-5.15/1004-clk-qcom-ipq6018-add-missing-clocks.patch +++ b/target/linux/ipq60xx/patches-5.15/1004-clk-qcom-ipq6018-add-missing-clocks.patch @@ -691,47 +691,6 @@ Signed-off-by: Alexandru Gagniuc [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr, [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, }; -@@ -4528,24 +5111,24 @@ static const struct qcom_reset_map gcc_i - [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 }, - [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 }, - [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 }, -- [GCC_PPE_FULL_RESET] = { 0x68014, 0 }, -- [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 }, -+ [GCC_PPE_FULL_RESET] = { 0x68014, 0, 0xf0000}, -+ [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0, 0x3ff2}, - [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 }, -- [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 }, -+ [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0, 0x32}, - [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 }, -- [GCC_EDMA_HW_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT1_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT2_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT3_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT4_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT5_RESET] = { 0x68014, 0 }, -- [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 }, -+ [GCC_EDMA_HW_RESET] = { 0x68014, 0, 0x300000}, -+ [GCC_NSSPORT1_RESET] = { 0x68014, 0, 0x1000003}, -+ [GCC_NSSPORT2_RESET] = { 0x68014, 0, 0x200000c}, -+ [GCC_NSSPORT3_RESET] = { 0x68014, 0, 0x4000030}, -+ [GCC_NSSPORT4_RESET] = { 0x68014, 0, 0x8000300}, -+ [GCC_NSSPORT5_RESET] = { 0x68014, 0, 0x10000c00}, -+ [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0, 0x30}, -+ [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0, 0xc0}, -+ [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0, 0x300}, -+ [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0, 0xc00}, -+ [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0, 0x3000}, -+ [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0, 0x3c02}, -+ [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0, 0xc02}, - [GCC_LPASS_BCR] = {0x1F000, 0}, - [GCC_UBI32_TBU_BCR] = {0x65000, 0}, - [GCC_LPASS_TBU_BCR] = {0x6C000, 0}, @@ -4597,6 +5180,10 @@ static const struct qcom_cc_desc gcc_ipq static int gcc_ipq6018_probe(struct platform_device *pdev) { diff --git a/target/linux/ipq60xx/patches-5.15/1007-arm64-dts-qcom-ipq6018-Add-missing-fixed-clocks.patch b/target/linux/ipq60xx/patches-5.15/1007-arm64-dts-qcom-ipq6018-Add-missing-fixed-clocks.patch index 0452e6a70..35c18ae88 100644 --- a/target/linux/ipq60xx/patches-5.15/1007-arm64-dts-qcom-ipq6018-Add-missing-fixed-clocks.patch +++ b/target/linux/ipq60xx/patches-5.15/1007-arm64-dts-qcom-ipq6018-Add-missing-fixed-clocks.patch @@ -29,7 +29,7 @@ Signed-off-by: Alexandru Gagniuc }; cpus: cpus { -@@ -247,8 +259,14 @@ +@@ -252,8 +264,14 @@ gcc: gcc@1800000 { compatible = "qcom,gcc-ipq6018"; reg = <0x0 0x01800000 0x0 0x80000>; diff --git a/target/linux/ipq60xx/patches-5.15/1009-ipq6018-rproc-Add-non-secure-Q6-bringup-sequence.patch b/target/linux/ipq60xx/patches-5.15/1009-ipq6018-rproc-Add-non-secure-Q6-bringup-sequence.patch index 32f57586f..67b718aa0 100644 --- a/target/linux/ipq60xx/patches-5.15/1009-ipq6018-rproc-Add-non-secure-Q6-bringup-sequence.patch +++ b/target/linux/ipq60xx/patches-5.15/1009-ipq6018-rproc-Add-non-secure-Q6-bringup-sequence.patch @@ -14,7 +14,7 @@ Signed-off-by: Manikanta Mylavarapu --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -618,8 +618,24 @@ +@@ -665,8 +665,24 @@ "wcss_reset", "wcss_q6_reset";