From c9224137975cd136ec63ca46771d666712f85e4d Mon Sep 17 00:00:00 2001 From: LEAN-ESX Date: Mon, 28 Oct 2019 21:45:35 -0700 Subject: [PATCH] ipq40xx: Qualcomm HW Crypto Engine patches --- .../182-crypto-qce-fix-ctr-blocksize.patch | 11 +++ .../183-crypto-qce-update-iv.patch | 68 ++++++++++++++ ...e-allow-building-only-hashes-ciphers.patch | 91 +++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 target/linux/ipq40xx/patches-4.14/182-crypto-qce-fix-ctr-blocksize.patch create mode 100644 target/linux/ipq40xx/patches-4.14/183-crypto-qce-update-iv.patch create mode 100644 target/linux/ipq40xx/patches-4.14/184-crypto-qce-allow-building-only-hashes-ciphers.patch diff --git a/target/linux/ipq40xx/patches-4.14/182-crypto-qce-fix-ctr-blocksize.patch b/target/linux/ipq40xx/patches-4.14/182-crypto-qce-fix-ctr-blocksize.patch new file mode 100644 index 000000000..832d679c7 --- /dev/null +++ b/target/linux/ipq40xx/patches-4.14/182-crypto-qce-fix-ctr-blocksize.patch @@ -0,0 +1,11 @@ +--- a/drivers/crypto/qce/ablkcipher.c 2019-10-21 17:18:47.311684603 -0300 ++++ b/drivers/crypto/qce/ablkcipher.c 2019-10-21 17:20:32.080765945 -0300 +@@ -292,7 +292,7 @@ + .name = "ctr(aes)", + .drv_name = "ctr-aes-qce", + .blocksize = AES_BLOCK_SIZE, +- .ivsize = AES_BLOCK_SIZE, ++ .ivsize = 1, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + }, diff --git a/target/linux/ipq40xx/patches-4.14/183-crypto-qce-update-iv.patch b/target/linux/ipq40xx/patches-4.14/183-crypto-qce-update-iv.patch new file mode 100644 index 000000000..a8e979ed3 --- /dev/null +++ b/target/linux/ipq40xx/patches-4.14/183-crypto-qce-update-iv.patch @@ -0,0 +1,68 @@ +diff --git a/drivers/crypto/qce/ablkcipher.c b/drivers/crypto/qce/ablkcipher.c +index 7a98bf5cc967..b935ce0acc1c 100644 +--- a/drivers/crypto/qce/ablkcipher.c ++++ b/drivers/crypto/qce/ablkcipher.c +@@ -14,6 +14,20 @@ + + static LIST_HEAD(ablkcipher_algs); + ++static void qce_update_ctr_iv(u8 *iv, unsigned int ivsize, u32 add) ++{ ++ __be32 *a = (__be32 *)(iv + ivsize); ++ u32 b; ++ ++ for (; ivsize >= 4; ivsize -= 4) { ++ b = be32_to_cpu(*--a) + add; ++ *a = cpu_to_be32(b); ++ if (b >= add) ++ return; ++ add = 1; ++ } ++} ++ + static void qce_ablkcipher_done(void *data) + { + struct crypto_async_request *async_req = data; +@@ -39,6 +53,18 @@ static void qce_ablkcipher_done(void *data) + dma_unmap_sg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src); + dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); + ++ if (IS_CBC(rctx->flags)) { ++ if (IS_ENCRYPT(rctx->flags)) ++ sg_pcopy_to_buffer(rctx->dst_sg, rctx->dst_nents, ++ rctx->iv, rctx->ivsize, ++ rctx->cryptlen - rctx->ivsize); ++ else ++ memcpy(rctx->iv, rctx->saved_iv, rctx->ivsize); ++ } else if (IS_CTR(rctx->flags) && IS_AES(rctx->flags)) { ++ qce_update_ctr_iv(rctx->iv, rctx->ivsize, ++ DIV_ROUND_UP(rctx->cryptlen, AES_BLOCK_SIZE)); ++ } ++ + sg_free_table(&rctx->dst_tbl); + + error = qce_check_status(qce, &status); +@@ -131,6 +157,11 @@ qce_ablkcipher_async_req_handle(struct crypto_async_request *async_req) + + qce_dma_issue_pending(&qce->dma); + ++ if (IS_CBC(rctx->flags) && IS_DECRYPT(rctx->flags)) ++ sg_pcopy_to_buffer(rctx->src_sg, rctx->src_nents, ++ rctx->saved_iv, rctx->ivsize, ++ rctx->cryptlen - rctx->ivsize); ++ + ret = qce_start(async_req, tmpl->crypto_alg_type, req->nbytes, 0); + if (ret) + goto error_terminate; +diff --git a/drivers/crypto/qce/cipher.h b/drivers/crypto/qce/cipher.h +index 5cab8f0706a8..a919022e28df 100644 +--- a/drivers/crypto/qce/cipher.h ++++ b/drivers/crypto/qce/cipher.h +@@ -43,6 +43,7 @@ struct qce_cipher_reqctx { + struct sg_table src_tbl; + struct scatterlist *src_sg; + unsigned int cryptlen; ++ u8 saved_iv[QCE_MAX_IV_SIZE]; + }; + + static inline struct qce_alg_template *to_cipher_tmpl(struct crypto_tfm *tfm) diff --git a/target/linux/ipq40xx/patches-4.14/184-crypto-qce-allow-building-only-hashes-ciphers.patch b/target/linux/ipq40xx/patches-4.14/184-crypto-qce-allow-building-only-hashes-ciphers.patch new file mode 100644 index 000000000..4b8a25604 --- /dev/null +++ b/target/linux/ipq40xx/patches-4.14/184-crypto-qce-allow-building-only-hashes-ciphers.patch @@ -0,0 +1,91 @@ +From 2f23be905522cc67505daaf4d94c0292dbddd315 Mon Sep 17 00:00:00 2001 +From: Eneas U de Queiroz +Date: Mon, 28 Oct 2019 15:17:19 -0300 +Subject: [PATCH] crypto: qce - allow building only hashes/ciphers + +Signed-off-by: Eneas U de Queiroz + +diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig +index 1fb622f2a87d..0dc4bbcfc092 100644 +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -580,5 +580,13 @@ config CRYPTO_DEV_QCE + tristate "Qualcomm crypto engine accelerator" + depends on (ARCH_QCOM || COMPILE_TEST) && HAS_DMA && HAS_IOMEM ++ help ++ This driver supports Qualcomm crypto engine accelerator ++ hardware. To compile this driver as a module, choose M here. The ++ module will be called qcrypto. ++ ++config CRYPTO_DEV_QCE_BLKCIPHER ++ bool ++ depends on CRYPTO_DEV_QCE + select CRYPTO_AES + select CRYPTO_LIB_DES + select CRYPTO_ECB +@@ -580,10 +588,29 @@ config CRYPTO_DEV_QCE + select CRYPTO_XTS + select CRYPTO_CTR + select CRYPTO_BLKCIPHER +- help +- This driver supports Qualcomm crypto engine accelerator +- hardware. To compile this driver as a module, choose M here. The +- module will be called qcrypto. ++ ++config CRYPTO_DEV_QCE_SHA ++ bool ++ depends on CRYPTO_DEV_QCE ++ ++choice ++ prompt "Algorithms enabled for QCE acceleration" ++ default CRYPTO_DEV_QCE_ENABLE_ALL ++ depends on CRYPTO_DEV_QCE ++ ++ config CRYPTO_DEV_QCE_ENABLE_ALL ++ bool "All supported algorithms" ++ select CRYPTO_DEV_QCE_BLKCIPHER ++ select CRYPTO_DEV_QCE_SHA ++ ++ config CRYPTO_DEV_QCE_ENABLE_BLKCIPHER ++ bool "Block ciphers only" ++ select CRYPTO_DEV_QCE_BLKCIPHER ++ ++ config CRYPTO_DEV_QCE_ENABLE_SHA ++ bool "Hash/HMAC only" ++ select CRYPTO_DEV_QCE_SHA ++endchoice + + config CRYPTO_DEV_QCOM_RNG + tristate "Qualcomm Random Number Generator Driver" +diff --git a/drivers/crypto/qce/Makefile b/drivers/crypto/qce/Makefile +index 19a7f899acff..f6a411c255b8 100644 +--- a/drivers/crypto/qce/Makefile ++++ b/drivers/crypto/qce/Makefile +@@ -2,6 +2,7 @@ + obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o + qcrypto-objs := core.o \ + common.o \ +- dma.o \ +- sha.o \ +- ablkcipher.o ++ dma.o ++ ++qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SHA) += sha.o ++qcrypto-$(CONFIG_CRYPTO_DEV_QCE_BLKCIPHER) += ablkcipher.o +diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c +index 08d4ce3bfddf..3428746f1869 100644 +--- a/drivers/crypto/qce/core.c ++++ b/drivers/crypto/qce/core.c +@@ -22,8 +22,12 @@ + #define QCE_QUEUE_LENGTH 1 + + static const struct qce_algo_ops *qce_ops[] = { ++#ifdef CONFIG_CRYPTO_DEV_QCE_BLKCIPHER + &ablkcipher_ops, ++#endif ++#ifdef CONFIG_CRYPTO_DEV_QCE_SHA + &ahash_ops, ++#endif + }; + + static void qce_unregister_algs(struct qce_device *qce)