diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile index 4cac4d40f..7201fedb4 100644 --- a/target/linux/rockchip/Makefile +++ b/target/linux/rockchip/Makefile @@ -16,7 +16,7 @@ endef include $(INCLUDE_DIR)/target.mk -DEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug \ +DEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug kmod-crypto-hw-rockchip \ automount autocore-arm autosamba fdisk cfdisk e2fsprogs ethtool haveged htop \ luci-app-zerotier luci-app-ipsec-vpnd luci-app-diskman usbutils diff --git a/target/linux/rockchip/armv8/config-5.18 b/target/linux/rockchip/armv8/config-5.18 index 4fe7288fa..3a88f0399 100644 --- a/target/linux/rockchip/armv8/config-5.18 +++ b/target/linux/rockchip/armv8/config-5.18 @@ -1,5 +1,16 @@ CONFIG_64BIT=y CONFIG_AF_UNIX_OOB=y +# CONFIG_AHCI_BRCM is not set +# CONFIG_AHCI_DA850 is not set +# CONFIG_AHCI_DM816 is not set +# CONFIG_AHCI_MTK is not set +# CONFIG_AHCI_SUNXI is not set +# CONFIG_AHCI_TEGRA is not set +# CONFIG_AHCI_XGENE is not set +# CONFIG_AMD_SFH_HID is not set +# CONFIG_APPLE_DART is not set +# CONFIG_APPLE_MAILBOX is not set +# CONFIG_APPLE_PMGR_PWRSTATE is not set CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y @@ -18,6 +29,7 @@ CONFIG_ARCH_STACKWALK=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_ARC_EMAC_CORE=y +# CONFIG_ARC_TIMERS is not set CONFIG_ARM64=y CONFIG_ARM64_CNP=y CONFIG_ARM64_CRYPTO=y @@ -50,12 +62,19 @@ CONFIG_ARM64_VA_BITS=48 CONFIG_ARM64_VA_BITS_48=y CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +# CONFIG_ARMADA375_USBCLUSTER_PHY is not set +# CONFIG_ARMADA_37XX_RWTM_MBOX is not set +# CONFIG_ARMADA_THERMAL is not set +# CONFIG_ARMV7M_SYSTICK is not set # CONFIG_ARMV8_DEPRECATED is not set CONFIG_ARM_AMBA=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_ARM_BRCMSTB_AVS_CPUFREQ=y +# CONFIG_ARM_CLPS711X_CPUIDLE is not set CONFIG_ARM_CPUIDLE=y +# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set CONFIG_ARM_FFA_SMCCC=y CONFIG_ARM_FFA_TRANSPORT=y CONFIG_ARM_GIC=y @@ -63,10 +82,17 @@ CONFIG_ARM_GIC_V2M=y CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set +# CONFIG_ARM_IMX_BUS_DEVFREQ is not set +# CONFIG_ARM_INTEGRATOR_LM is not set +CONFIG_ARM_MEDIATEK_CPUFREQ_HW=m CONFIG_ARM_MHU=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_QCOM_CPUFREQ_HW is not set +# CONFIG_ARM_RASPBERRYPI_CPUFREQ is not set +# CONFIG_ARM_RK3328_DMC_DEVFREQ is not set CONFIG_ARM_RK3399_DMC_DEVFREQ=y CONFIG_ARM_SCMI_CPUFREQ=y CONFIG_ARM_SCMI_HAVE_SHMEM=y @@ -85,11 +111,40 @@ CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y # CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set CONFIG_ARM_SMMU_V3=y # CONFIG_ARM_SMMU_V3_SVA is not set +# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set +# CONFIG_ARM_TEGRA_DEVFREQ is not set +# CONFIG_ASPEED_BT_IPMI_BMC is not set +# CONFIG_ASPEED_KCS_IPMI_BMC is not set +# CONFIG_ASPEED_LPC_CTRL is not set +# CONFIG_ASPEED_LPC_SNOOP is not set +# CONFIG_ASPEED_P2A_CTRL is not set +# CONFIG_ASPEED_SOCINFO is not set +# CONFIG_ASPEED_UART_ROUTING is not set +# CONFIG_AT91_SOC_ID is not set +# CONFIG_AT91_SOC_SFR is not set CONFIG_ATA=y +# CONFIG_ATMEL_ST is not set CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +# CONFIG_AXI_DMAC is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GPIO=y CONFIG_BACKLIGHT_PWM=y +# CONFIG_BATTERY_ACT8945A is not set +# CONFIG_BCM2711_THERMAL is not set +# CONFIG_BCM2835_POWER is not set +# CONFIG_BCM2835_THERMAL is not set +# CONFIG_BCM2835_TIMER is not set +# CONFIG_BCM2835_VCHIQ is not set +# CONFIG_BCM47XX_NVRAM is not set +# CONFIG_BCM4908_ENET is not set +# CONFIG_BCM_FLEXRM_MBOX is not set +# CONFIG_BCM_KONA_TIMER is not set +# CONFIG_BCM_NS_THERMAL is not set +# CONFIG_BCM_PDC_MBOX is not set +# CONFIG_BCM_PMB is not set +# CONFIG_BCM_SR_THERMAL is not set +CONFIG_BCM_VIDEOCORE=y +# CONFIG_BGMAC_PLATFORM is not set CONFIG_BINARY_PRINTF=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y @@ -110,19 +165,76 @@ CONFIG_BLK_PM=y CONFIG_BLOCK_COMPAT=y CONFIG_BLOCK_LEGACY_AUTOLOAD=y CONFIG_BRCMSTB_GISB_ARB=y +# CONFIG_BRCMSTB_THERMAL is not set +# CONFIG_BRCM_USB_PINMAP is not set CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +# CONFIG_BT1_APB is not set +# CONFIG_BT1_AXI is not set +# CONFIG_CADENCE_TTC_TIMER is not set CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_CHARGER_GPIO=y +# CONFIG_CHARGER_QCOM_SMBB is not set +# CONFIG_CHARGER_SC2731 is not set +# CONFIG_CLKSRC_DBX500_PRCMU is not set +# CONFIG_CLKSRC_EXYNOS_MCT is not set +# CONFIG_CLKSRC_IMX_GPT is not set +# CONFIG_CLKSRC_IMX_TPM is not set +# CONFIG_CLKSRC_JCORE_PIT is not set CONFIG_CLKSRC_MMIO=y +# CONFIG_CLKSRC_MPS2 is not set +# CONFIG_CLKSRC_PISTACHIO is not set +# CONFIG_CLKSRC_PXA is not set +# CONFIG_CLKSRC_SAMSUNG_PWM is not set +# CONFIG_CLKSRC_STM32_LP is not set +# CONFIG_CLKSRC_ST_LPC is not set +# CONFIG_CLKSRC_TI_32K is not set +# CONFIG_CLK_ACTIONS is not set +# CONFIG_CLK_BAIKAL_T1 is not set +# CONFIG_CLK_BCM2711_DVP is not set +# CONFIG_CLK_BCM2835 is not set +# CONFIG_CLK_BCM_63XX is not set +# CONFIG_CLK_BCM_63XX_GATE is not set +# CONFIG_CLK_BCM_CYGNUS is not set +# CONFIG_CLK_BCM_HR2 is not set +# CONFIG_CLK_BCM_KONA is not set +# CONFIG_CLK_BCM_NS2 is not set +# CONFIG_CLK_BCM_NSP is not set +# CONFIG_CLK_BCM_SR is not set +# CONFIG_CLK_IMX8MM is not set +# CONFIG_CLK_IMX8MN is not set +# CONFIG_CLK_IMX8MP is not set +# CONFIG_CLK_IMX8MQ is not set +# CONFIG_CLK_IMX8ULP is not set +# CONFIG_CLK_IMX93 is not set +# CONFIG_CLK_INTEL_SOCFPGA is not set +# CONFIG_CLK_LGM_CGU is not set +# CONFIG_CLK_LS1028A_PLLDIG is not set +# CONFIG_CLK_MT7621 is not set CONFIG_CLK_PX30=y +# CONFIG_CLK_RASPBERRYPI is not set +# CONFIG_CLK_RENESAS is not set +CONFIG_CLK_RK3036=y +CONFIG_CLK_RK312X=y +CONFIG_CLK_RK3188=y +CONFIG_CLK_RK322X=y +CONFIG_CLK_RK3288=y CONFIG_CLK_RK3308=y CONFIG_CLK_RK3328=y CONFIG_CLK_RK3368=y CONFIG_CLK_RK3399=y CONFIG_CLK_RK3568=y +CONFIG_CLK_RV110X=y +# CONFIG_CLK_SIFIVE is not set +# CONFIG_CLK_STARFIVE_JH7100 is not set +CONFIG_CLK_SUNXI=y +CONFIG_CLK_SUNXI_CLOCKS=y +CONFIG_CLK_SUNXI_PRCM_SUN6I=y +CONFIG_CLK_SUNXI_PRCM_SUN8I=y +CONFIG_CLK_SUNXI_PRCM_SUN9I=y +# CONFIG_CLK_UNIPHIER is not set CONFIG_CLONE_BACKWARDS=y +# CONFIG_CLPS711X_TIMER is not set CONFIG_CMA=y CONFIG_CMA_ALIGNMENT=8 CONFIG_CMA_AREAS=7 @@ -134,16 +246,83 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_APPLE_NCO is not set +# CONFIG_COMMON_CLK_ASPEED is not set +CONFIG_COMMON_CLK_AXG=y +# CONFIG_COMMON_CLK_AXG_AUDIO is not set +# CONFIG_COMMON_CLK_BM1880 is not set +# CONFIG_COMMON_CLK_BOSTON is not set +# CONFIG_COMMON_CLK_FSL_FLEXSPI is not set +# CONFIG_COMMON_CLK_FSL_SAI is not set +CONFIG_COMMON_CLK_G12A=y +# CONFIG_COMMON_CLK_GEMINI is not set +CONFIG_COMMON_CLK_GXBB=y +# CONFIG_COMMON_CLK_HI3516CV300 is not set +# CONFIG_COMMON_CLK_HI3519 is not set +# CONFIG_COMMON_CLK_HI3559A is not set +# CONFIG_COMMON_CLK_HI3660 is not set +# CONFIG_COMMON_CLK_HI3670 is not set +# CONFIG_COMMON_CLK_HI3798CV200 is not set +# CONFIG_COMMON_CLK_HI6220 is not set +# CONFIG_COMMON_CLK_HI655X is not set +# CONFIG_COMMON_CLK_KEYSTONE is not set +# CONFIG_COMMON_CLK_MAX77686 is not set +CONFIG_COMMON_CLK_MEDIATEK=y +CONFIG_COMMON_CLK_MESON_AO_CLKC=y +CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y +CONFIG_COMMON_CLK_MESON_DUALDIV=y +CONFIG_COMMON_CLK_MESON_EE_CLKC=y +CONFIG_COMMON_CLK_MESON_MPLL=y +CONFIG_COMMON_CLK_MESON_PLL=y +CONFIG_COMMON_CLK_MESON_REGMAP=y +CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y +# CONFIG_COMMON_CLK_MMP2_AUDIO is not set +# CONFIG_COMMON_CLK_MT2701 is not set +# CONFIG_COMMON_CLK_MT2712 is not set +# CONFIG_COMMON_CLK_MT6779 is not set +# CONFIG_COMMON_CLK_MT6797 is not set +# CONFIG_COMMON_CLK_MT7622 is not set +# CONFIG_COMMON_CLK_MT7629 is not set +# CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT8135 is not set +# CONFIG_COMMON_CLK_MT8173 is not set +# CONFIG_COMMON_CLK_MT8183 is not set +CONFIG_COMMON_CLK_MT8192=y +# CONFIG_COMMON_CLK_MT8192_AUDSYS is not set +# CONFIG_COMMON_CLK_MT8192_CAMSYS is not set +# CONFIG_COMMON_CLK_MT8192_IMGSYS is not set +# CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP is not set +# CONFIG_COMMON_CLK_MT8192_IPESYS is not set +# CONFIG_COMMON_CLK_MT8192_MDPSYS is not set +# CONFIG_COMMON_CLK_MT8192_MFGCFG is not set +# CONFIG_COMMON_CLK_MT8192_MMSYS is not set +# CONFIG_COMMON_CLK_MT8192_MSDC is not set +# CONFIG_COMMON_CLK_MT8192_SCP_ADSP is not set +# CONFIG_COMMON_CLK_MT8192_VDECSYS is not set +# CONFIG_COMMON_CLK_MT8192_VENCSYS is not set +# CONFIG_COMMON_CLK_MT8195 is not set +# CONFIG_COMMON_CLK_MT8516 is not set +# CONFIG_COMMON_CLK_OXNAS is not set +# CONFIG_COMMON_CLK_PISTACHIO is not set CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_ROCKCHIP=y # CONFIG_COMMON_CLK_RS9_PCIE is not set +# CONFIG_COMMON_CLK_S2MPS11 is not set +# CONFIG_COMMON_CLK_SAMSUNG is not set # CONFIG_COMMON_CLK_SCMI is not set CONFIG_COMMON_CLK_SCPI=y +# CONFIG_COMMON_CLK_TI_ADPLL is not set +# CONFIG_COMMON_CLK_TPS68470 is not set +# CONFIG_COMMON_CLK_VISCONTI is not set +# CONFIG_COMMON_CLK_ZYNQMP is not set +# CONFIG_COMMON_RESET_HI3660 is not set +# CONFIG_COMMON_RESET_HI6220 is not set CONFIG_COMPAT=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_COMPAT_BINFMT_ELF=y CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_COMPILE_TEST=y CONFIG_CONFIGFS_FS=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_CONTIG_ALLOC=y @@ -180,17 +359,41 @@ CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC64_ROCKSOFT=y CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_DEV_ALLWINNER is not set +# CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set +# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 is not set +# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC is not set +# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU is not set +# CONFIG_CRYPTO_DEV_OCTEONTX2_CPT is not set +# CONFIG_CRYPTO_DEV_OCTEONTX_CPT is not set +# CONFIG_CRYPTO_DEV_QCOM_RNG is not set +# CONFIG_CRYPTO_DEV_ROCKCHIP is not set +# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set +# CONFIG_CRYPTO_DEV_SA2UL is not set +# CONFIG_CRYPTO_DEV_SL3516 is not set +# CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set +# CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ENGINE=y CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SIMD=y +CONFIG_CRYPTO_SHA1=y +# CONFIG_CX_ECAT is not set +# CONFIG_DA9062_THERMAL is not set +# CONFIG_DAVINCI_TIMER is not set CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y @@ -198,6 +401,8 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEFAULT_FQ_CODEL is not set CONFIG_DEFAULT_NET_SCH="pfifo_fast" CONFIG_DEFAULT_PFIFO_FAST=y +# CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set +# CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU is not set CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y # CONFIG_DEVFREQ_GOV_PASSIVE is not set CONFIG_DEVFREQ_GOV_PERFORMANCE=y @@ -207,30 +412,43 @@ CONFIG_DEVFREQ_GOV_USERSPACE=y # CONFIG_DEVFREQ_THERMAL is not set CONFIG_DEVMEM=y # CONFIG_DEVPORT is not set +# CONFIG_DIGICOLOR_TIMER is not set # CONFIG_DM9051 is not set CONFIG_DMADEVICES=y CONFIG_DMA_CMA=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y +CONFIG_DMA_OMAP=y CONFIG_DMA_OPS=y +# CONFIG_DMA_SA11X0 is not set CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_SUN6I is not set +CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DNOTIFY=y +# CONFIG_DOVE_THERMAL is not set +CONFIG_DPAA2_CONSOLE=y CONFIG_DRM=y # CONFIG_DRM_ANALOGIX_ANX7625 is not set +# CONFIG_DRM_ASPEED_GFX is not set CONFIG_DRM_BRIDGE=y # CONFIG_DRM_CHIPONE_ICN6211 is not set +# CONFIG_DRM_CROS_EC_ANX7688 is not set CONFIG_DRM_DEBUG_MODESET_LOCK=y CONFIG_DRM_DP_HELPER=y CONFIG_DRM_DW_HDMI=y CONFIG_DRM_DW_MIPI_DSI=y CONFIG_DRM_GEM_CMA_HELPER=y +# CONFIG_DRM_INGENIC is not set # CONFIG_DRM_ITE_IT6505 is not set # CONFIG_DRM_ITE_IT66121 is not set +# CONFIG_DRM_KMB_DISPLAY is not set CONFIG_DRM_KMS_HELPER=y # CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_MESON is not set CONFIG_DRM_MIPI_DSI=y +# CONFIG_DRM_MSM is not set CONFIG_DRM_NOMODESET=y CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set @@ -255,43 +473,75 @@ CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_RCAR_DU is not set # CONFIG_DRM_RCAR_MIPI_DSI is not set # CONFIG_DRM_RCAR_USE_LVDS is not set CONFIG_DRM_ROCKCHIP=y # CONFIG_DRM_SIMPLEDRM is not set +# CONFIG_DRM_SPRD is not set # CONFIG_DRM_SSD130X is not set # CONFIG_DRM_TI_SN65DSI83 is not set +# CONFIG_DRM_V3D is not set CONFIG_DTC=y CONFIG_DT_IDLE_GENPD=y CONFIG_DT_IDLE_STATES=y CONFIG_DUMMY_CONSOLE=y +# CONFIG_DWMAC_ANARION is not set CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_DWMAC_GENERIC=y +# CONFIG_DWMAC_IMX8 is not set +# CONFIG_DWMAC_INGENIC is not set +# CONFIG_DWMAC_MEDIATEK is not set +# CONFIG_DWMAC_OXNAS is not set +# CONFIG_DWMAC_QCOM_ETHQOS is not set CONFIG_DWMAC_ROCKCHIP=y +# CONFIG_DWMAC_STM32 is not set +# CONFIG_DWMAC_SUN8I is not set +# CONFIG_DWMAC_SUNXI is not set +# CONFIG_DWMAC_VISCONTI is not set +# CONFIG_DW_APB_TIMER is not set CONFIG_EDAC_SUPPORT=y CONFIG_EEPROM_AT24=y +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EINT_MTK is not set CONFIG_EMAC_ROCKCHIP=y CONFIG_ENERGY_MODEL=y +# CONFIG_EP93XX_DMA is not set +# CONFIG_EP93XX_ETH is not set CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXTCON=y +# CONFIG_EXYNOS_IOMMU is not set +# CONFIG_EXYNOS_IRQ_COMBINER is not set +# CONFIG_EXYNOS_THERMAL is not set CONFIG_F2FS_FS=y CONFIG_FANOTIFY=y CONFIG_FB_CMDLINE=y +# CONFIG_FEC is not set CONFIG_FHANDLE=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y # CONFIG_FORTIFY_SOURCE is not set CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 +# CONFIG_FSL_DPAA2_SWITCH is not set +# CONFIG_FSL_ENETC is not set +# CONFIG_FSL_ENETC_IERB is not set +# CONFIG_FSL_ENETC_MDIO is not set +# CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_FMAN is not set +# CONFIG_FSL_FTM_TIMER is not set CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y CONFIG_FS_POSIX_ACL=y +# CONFIG_FTTMR010_TIMER is not set # CONFIG_FUN_ETH is not set CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y +# CONFIG_GEHC_ACHC is not set CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -323,53 +573,147 @@ CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y +# CONFIG_GIANFAR is not set CONFIG_GLOB=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_GPIO_ASPEED is not set +# CONFIG_GPIO_ASPEED_SGPIO is not set +# CONFIG_GPIO_ATH79 is not set +# CONFIG_GPIO_BCM_XGS_IPROC is not set +# CONFIG_GPIO_BRCMSTB is not set # CONFIG_GPIO_CASCADE is not set CONFIG_GPIO_CDEV=y +# CONFIG_GPIO_CLPS711X is not set CONFIG_GPIO_DWAPB=y +# CONFIG_GPIO_EIC_SPRD is not set CONFIG_GPIO_GENERIC=y CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_GPIO_HISI is not set +# CONFIG_GPIO_IDT3243X is not set +# CONFIG_GPIO_IOP is not set +# CONFIG_GPIO_LPC18XX is not set +# CONFIG_GPIO_LPC32XX is not set +# CONFIG_GPIO_MLXBF is not set +# CONFIG_GPIO_MLXBF2 is not set +# CONFIG_GPIO_MT7621 is not set +# CONFIG_GPIO_MXC is not set +# CONFIG_GPIO_MXS is not set +# CONFIG_GPIO_PMIC_EIC_SPRD is not set +# CONFIG_GPIO_PXA is not set +# CONFIG_GPIO_RASPBERRYPI_EXP is not set +# CONFIG_GPIO_RDA is not set CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_SIM is not set +# CONFIG_GPIO_SL28CPLD is not set +# CONFIG_GPIO_SNPS_CREG is not set +# CONFIG_GPIO_SPRD is not set +# CONFIG_GPIO_STP_XWAY is not set +# CONFIG_GPIO_TEGRA is not set +# CONFIG_GPIO_TEGRA186 is not set +# CONFIG_GPIO_THUNDERX is not set +# CONFIG_GPIO_TQMX86 is not set +# CONFIG_GPIO_TS4800 is not set +# CONFIG_GPIO_UNIPHIER is not set +# CONFIG_GPIO_VISCONTI is not set +# CONFIG_GPIO_XGENE_SB is not set +# CONFIG_GPIO_XLP is not set CONFIG_GRO_CELLS=y +# CONFIG_H8300_TMR16 is not set +# CONFIG_H8300_TMR8 is not set +# CONFIG_H8300_TPU is not set # CONFIG_HARDENED_USERCOPY is not set CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HDMI=y +# CONFIG_HI3660_MBOX is not set +# CONFIG_HI6220_MBOX is not set CONFIG_HID=y CONFIG_HID_GENERIC=y +# CONFIG_HISILICON_LPC is not set +CONFIG_HISI_THERMAL=y CONFIG_HOTPLUG_CPU=y CONFIG_HOTPLUG_PCI=y # CONFIG_HOTPLUG_PCI_CPCI is not set CONFIG_HOTPLUG_PCI_PCIE=y CONFIG_HOTPLUG_PCI_SHPC=y +# CONFIG_HSEM_U8500 is not set CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_HWMON=y CONFIG_HWSPINLOCK=y +# CONFIG_HWSPINLOCK_QCOM is not set +# CONFIG_HWSPINLOCK_SPRD is not set +# CONFIG_HWSPINLOCK_STM32 is not set +# CONFIG_HWSPINLOCK_SUN6I is not set CONFIG_HW_CONSOLE=y CONFIG_HZ=250 # CONFIG_HZ_100 is not set CONFIG_HZ_250=y CONFIG_I2C=y CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_ALTERA is not set +# CONFIG_I2C_APPLE is not set +# CONFIG_I2C_ASPEED is not set +# CONFIG_I2C_AT91 is not set +# CONFIG_I2C_AXXIA is not set +# CONFIG_I2C_BCM_KONA is not set CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_BRCMSTB=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_COMPAT=y +# CONFIG_I2C_DAVINCI is not set +# CONFIG_I2C_DIGICOLOR is not set +# CONFIG_I2C_EXYNOS5 is not set CONFIG_I2C_HELPER_AUTO=y +# CONFIG_I2C_HIGHLANDER is not set +# CONFIG_I2C_HIX5HD2 is not set +# CONFIG_I2C_IMX is not set +# CONFIG_I2C_IMX_LPI2C is not set +# CONFIG_I2C_IOP3XX is not set +# CONFIG_I2C_LPC2K is not set +# CONFIG_I2C_MESON is not set +# CONFIG_I2C_MT7621 is not set +# CONFIG_I2C_MXS is not set +# CONFIG_I2C_NPCM7XX is not set +# CONFIG_I2C_OMAP is not set +# CONFIG_I2C_OWL is not set +# CONFIG_I2C_PNX is not set +# CONFIG_I2C_PXA is not set +# CONFIG_I2C_QCOM_CCI is not set +# CONFIG_I2C_QUP is not set +# CONFIG_I2C_RIIC is not set CONFIG_I2C_RK3X=y +# CONFIG_I2C_SPRD is not set +# CONFIG_I2C_ST is not set +# CONFIG_I2C_STM32F4 is not set +# CONFIG_I2C_STM32F7 is not set +# CONFIG_I2C_SUN6I_P2WI is not set +# CONFIG_I2C_SYNQUACER is not set +# CONFIG_I2C_TEGRA is not set +# CONFIG_I2C_TEGRA_BPMP is not set +# CONFIG_I2C_UNIPHIER is not set +# CONFIG_I2C_UNIPHIER_F is not set +# CONFIG_I2C_WMT is not set +# CONFIG_I2C_XLP9XX is not set CONFIG_IGB=y CONFIG_IGB_HWMON=y CONFIG_IGC=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +# CONFIG_IMX8MM_THERMAL is not set +# CONFIG_IMX_GPCV2_PM_DOMAINS is not set +# CONFIG_IMX_INTMUX is not set +# CONFIG_IMX_IRQSTEER is not set +# CONFIG_IMX_MBOX is not set CONFIG_INDIRECT_PIO=y +# CONFIG_INGENIC_CGU_JZ4760 is not set CONFIG_INPUT=y +# CONFIG_INPUT_ARIEL_PWRBUTTON is not set CONFIG_INPUT_EVDEV=y CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_HISI_POWERKEY is not set CONFIG_INPUT_KEYBOARD=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_MATRIXKMAP=y @@ -379,7 +723,12 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_RK805_PWRKEY=y +# CONFIG_INPUT_SC27XX_VIBRA is not set CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INTEGRATOR_AP_TIMER is not set +# CONFIG_INTEL_IOP_ADMA is not set +# CONFIG_INTEL_IXP4XX_EB is not set +# CONFIG_INTEL_LDMA is not set CONFIG_IOMMU_API=y # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set @@ -393,27 +742,53 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y CONFIG_IOMMU_SUPPORT=y # CONFIG_IO_STRICT_DEVMEM is not set CONFIG_IO_URING=y +# CONFIG_IPMMU_VMSA is not set CONFIG_IRQCHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_MSI_IOMMU=y CONFIG_IRQ_TIME_ACCOUNTING=y +# CONFIG_IRQ_UNIPHIER_AIDET is not set CONFIG_IRQ_WORK=y -CONFIG_JLSEMI_JL2XX1_PHY=y +# CONFIG_IXP4XX_NPE is not set +# CONFIG_IXP4XX_QMGR is not set +# CONFIG_IXP4XX_TIMER is not set CONFIG_JBD2=y +# CONFIG_JCORE_AIC is not set CONFIG_JFFS2_ZLIB=y +CONFIG_JLSEMI_JL2XX1_PHY=y CONFIG_JUMP_LABEL=y +# CONFIG_JZ4780_EFUSE is not set +# CONFIG_K3_DMA is not set +# CONFIG_K3_THERMAL is not set CONFIG_KALLSYMS=y CONFIG_KCMP=y CONFIG_KEXEC_CORE=y CONFIG_KEXEC_FILE=y # CONFIG_KEXEC_SIG is not set +# CONFIG_KEYBOARD_CLPS711X is not set +# CONFIG_KEYBOARD_EP93XX is not set +# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set +# CONFIG_KEYBOARD_IMX is not set +# CONFIG_KEYBOARD_MT6779 is not set +# CONFIG_KEYBOARD_ST_KEYSCAN is not set +# CONFIG_KEYSTONE_TIMER is not set +# CONFIG_KEYSTONE_USB_PHY is not set +# CONFIG_KIRKWOOD_THERMAL is not set +# CONFIG_KORINA is not set CONFIG_KSM=y # CONFIG_LAN966X_SWITCH is not set +# CONFIG_LEDS_ARIEL is not set # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +# CONFIG_LEDS_COBALT_QUBE is not set +# CONFIG_LEDS_COBALT_RAQ is not set CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_IP30 is not set +# CONFIG_LEDS_LGM is not set +CONFIG_LEDS_NETXBIG=y CONFIG_LEDS_PWM=y +# CONFIG_LEDS_S3C24XX is not set CONFIG_LEDS_SYSCON=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_PANIC=y @@ -421,36 +796,77 @@ CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 CONFIG_LIBCRC32C=y CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y +CONFIG_LIB_MEMNEQ=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_LOG_BUF_SHIFT=19 +# CONFIG_LOONGSON_PCH_MSI is not set +# CONFIG_LOONGSON_PCH_PIC is not set +# CONFIG_LPC_ENET is not set CONFIG_LTO_NONE=y CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAILBOX=y # CONFIG_MAILBOX_TEST is not set +# CONFIG_MCF_EDMA is not set +# CONFIG_MCHP_CLK_MPFS is not set +# CONFIG_MCHP_EIC is not set +# CONFIG_MDIO_ASPEED is not set +# CONFIG_MDIO_BCM_IPROC is not set CONFIG_MDIO_BUS=y CONFIG_MDIO_BUS_MUX=y +# CONFIG_MDIO_BUS_MUX_BCM6368 is not set +# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set CONFIG_MDIO_BUS_MUX_GPIO=y +# CONFIG_MDIO_BUS_MUX_MESON_G12A is not set CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_MOXART is not set +# CONFIG_MDIO_SUN4I is not set +# CONFIG_MDIO_XGENE is not set CONFIG_MEDIATEK_GE_PHY=y CONFIG_MEMFD_CREATE=y CONFIG_MEMORY_ISOLATION=y +# CONFIG_MESON6_TIMER is not set +# CONFIG_MESON_CANVAS is not set +# CONFIG_MESON_CLK_MEASURE is not set +# CONFIG_MESON_EE_PM_DOMAINS is not set +# CONFIG_MESON_GXL_PHY is not set +# CONFIG_MESON_GX_PM_DOMAINS is not set +# CONFIG_MESON_GX_SOCINFO is not set +# CONFIG_MESON_IRQ_GPIO is not set +# CONFIG_MESON_MX_EFUSE is not set +# CONFIG_MESON_MX_SOCINFO is not set +# CONFIG_MFD_ACER_A500_EC is not set +# CONFIG_MFD_AT91_USART is not set CONFIG_MFD_CORE=y +# CONFIG_MFD_ENE_KB3930 is not set +# CONFIG_MFD_HI655X_PMIC is not set # CONFIG_MFD_KHADAS_MCU is not set # CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MX25_TSADC is not set +# CONFIG_MFD_MXS_LRADC is not set CONFIG_MFD_RK808=y +# CONFIG_MFD_SC27XX_PMIC is not set # CONFIG_MFD_SIMPLE_MFD_I2C is not set +# CONFIG_MFD_STM32_LPTIMER is not set +# CONFIG_MFD_STM32_TIMERS is not set +# CONFIG_MFD_STW481X is not set +# CONFIG_MFD_SUN4I_GPADC is not set +CONFIG_MFD_SUN6I_PRCM=y CONFIG_MFD_SYSCON=y CONFIG_MIGRATION=y +# CONFIG_MILBEAUT_HDMAC is not set +# CONFIG_MILBEAUT_XDMAC is not set CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y +# CONFIG_MLXBF_GIGE is not set CONFIG_MMC=y +# CONFIG_MMC_BCM2835 is not set CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_CQHCI=y +# CONFIG_MMC_DAVINCI is not set CONFIG_MMC_DW=y # CONFIG_MMC_DW_BLUEFIELD is not set # CONFIG_MMC_DW_EXYNOS is not set @@ -459,11 +875,33 @@ CONFIG_MMC_DW=y # CONFIG_MMC_DW_PCI is not set CONFIG_MMC_DW_PLTFM=y CONFIG_MMC_DW_ROCKCHIP=y +# CONFIG_MMC_LITEX is not set +# CONFIG_MMC_MESON_GX is not set +# CONFIG_MMC_MESON_MX_SDHC is not set +# CONFIG_MMC_MESON_MX_SDIO is not set +# CONFIG_MMC_MOXART is not set +# CONFIG_MMC_OMAP_HS is not set +# CONFIG_MMC_OWL is not set CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_CNS3XXX is not set +# CONFIG_MMC_SDHCI_DOVE is not set +# CONFIG_MMC_SDHCI_ESDHC_IMX is not set CONFIG_MMC_SDHCI_OF_ARASAN=y CONFIG_MMC_SDHCI_OF_DWCMSHC=y +# CONFIG_MMC_SDHCI_OF_SPARX5 is not set # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_SDHCI_SPEAR is not set +# CONFIG_MMC_SDHCI_SPRD is not set +# CONFIG_MMC_SDHCI_ST is not set +# CONFIG_MMC_SDHCI_TEGRA is not set +# CONFIG_MMC_SDHI is not set +# CONFIG_MMC_SH_MMCIF is not set +# CONFIG_MMC_TMIO is not set +# CONFIG_MMC_UNIPHIER is not set +# CONFIG_MMP_DISP is not set +# CONFIG_MMP_PDMA is not set +# CONFIG_MMP_TDMA is not set CONFIG_MODULES_USE_ELF_RELA=y CONFIG_MOTORCOMM_PHY=y # CONFIG_MOUSE_BCM5974 is not set @@ -482,19 +920,50 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set CONFIG_MQ_IOSCHED_DEADLINE=y +# CONFIG_MSC313E_TIMER is not set +# CONFIG_MSTAR_MSC313_MPLL is not set +# CONFIG_MTD_BCM63XX_PARTS is not set # CONFIG_MTD_CFI is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_NAND_ECC_MXIC is not set # CONFIG_MTD_NAND_MTK_BMT is not set +# CONFIG_MTD_OF_PARTS_BCM4908 is not set +# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set +# CONFIG_MTD_PARSER_IMAGETAG is not set +# CONFIG_MTD_PARSER_TRX is not set +# CONFIG_MTD_SHARPSL_PARTS is not set +CONFIG_MTD_SPEAR_SMI=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y CONFIG_MTD_SPLIT_FIRMWARE=y +# CONFIG_MTD_TS5500 is not set +# CONFIG_MTK_ADSP_MBOX is not set +# CONFIG_MTK_CMDQ is not set +# CONFIG_MTK_CMDQ_MBOX is not set +# CONFIG_MTK_CQDMA is not set +# CONFIG_MTK_DEVAPC is not set +# CONFIG_MTK_EFUSE is not set +# CONFIG_MTK_HSDMA is not set +# CONFIG_MTK_INFRACFG is not set +# CONFIG_MTK_IOMMU is not set +# CONFIG_MTK_PMIC_WRAP is not set +# CONFIG_MTK_SCPSYS is not set +# CONFIG_MTK_SCPSYS_PM_DOMAINS is not set +CONFIG_MTK_THERMAL=y +# CONFIG_MTK_TIMER is not set CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MVNETA is not set +# CONFIG_MVPP2 is not set +# CONFIG_MV_XOR is not set +# CONFIG_MXC_CLK is not set +# CONFIG_MXS_DMA is not set +# CONFIG_MXS_TIMER is not set CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NET_DEVLINK=y CONFIG_NET_DSA=y +# CONFIG_NET_DSA_MSCC_FELIX is not set CONFIG_NET_DSA_MT7530=y # CONFIG_NET_DSA_REALTEK is not set CONFIG_NET_DSA_TAG_MTK=y @@ -503,23 +972,42 @@ CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SELFTESTS=y CONFIG_NET_SOCK_MSG=y CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_VENDOR_ACTIONS is not set CONFIG_NET_VENDOR_DAVICOM=y CONFIG_NET_VENDOR_FUNGIBLE=y +# CONFIG_NET_VENDOR_MEDIATEK is not set +# CONFIG_NET_XGENE_V2 is not set CONFIG_NLS=y CONFIG_NLS_ISO8859_1=y CONFIG_NOP_USB_XCEIV=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y +# CONFIG_NPCM7XX_KCS_IPMI_BMC is not set +# CONFIG_NPCM7XX_TIMER is not set +# CONFIG_NSPIRE_TIMER is not set CONFIG_NTFS_FS=y CONFIG_NTFS_RW=y CONFIG_NVMEM=y +# CONFIG_NVMEM_BRCM_NVRAM is not set +# CONFIG_NVMEM_IMX_IIM is not set +# CONFIG_NVMEM_LAYERSCAPE_SFP is not set +# CONFIG_NVMEM_LPC18XX_EEPROM is not set +# CONFIG_NVMEM_LPC18XX_OTP is not set +# CONFIG_NVMEM_MXS_OCOTP is not set +# CONFIG_NVMEM_SNVS_LPGPR is not set +# CONFIG_NVMEM_STM32_ROMEM is not set +# CONFIG_NVMEM_SUNPLUS_OCOTP is not set CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_VF610_OCOTP is not set CONFIG_NVME_CORE=y # CONFIG_NVME_HWMON is not set # CONFIG_NVME_MULTIPATH is not set # CONFIG_NVME_VERBOSE_ERRORS is not set +# CONFIG_OBJAGG is not set +# CONFIG_OCTEON_ETHERNET is not set CONFIG_OF=y CONFIG_OF_ADDRESS=y +# CONFIG_OF_ALL_DTBS is not set CONFIG_OF_DYNAMIC=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_FLATTREE=y @@ -531,20 +1019,30 @@ CONFIG_OF_MDIO=y CONFIG_OF_OVERLAY=y CONFIG_OF_RESOLVE=y CONFIG_OLD_SIGSUSPEND3=y +# CONFIG_OLPC_XO175 is not set +# CONFIG_OMAP_CONTROL_PHY is not set +# CONFIG_OMAP_IOMMU is not set # CONFIG_OPEN_DICE is not set # CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OWL_PM_DOMAINS is not set +# CONFIG_OWL_TIMER is not set +# CONFIG_OXNAS_RPS_TIMER is not set CONFIG_PADATA=y CONFIG_PAGE_POOL=y # CONFIG_PAGE_POOL_STATS is not set CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_SPLIT_BTF=y -CONFIG_PAHOLE_VERSION=121 +CONFIG_PAHOLE_VERSION=0 # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PARMAN is not set # CONFIG_PARTITION_ADVANCED is not set CONFIG_PARTITION_PERCPU=y +# CONFIG_PATA_BK3710 is not set +# CONFIG_PATA_IXP4XX_CF is not set +# CONFIG_PATA_PXA is not set +# CONFIG_PATA_SAMSUNG_CF is not set CONFIG_PATA_SIS=y CONFIG_PCI=y CONFIG_PCIEAER=y @@ -554,24 +1052,115 @@ CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set CONFIG_PCIEPORTBUS=y +# CONFIG_PCIE_APPLE is not set +# CONFIG_PCIE_ARTPEC6_HOST is not set +# CONFIG_PCIE_BRCMSTB is not set CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y +# CONFIG_PCIE_FU740 is not set +# CONFIG_PCIE_HISI_STB is not set +# CONFIG_PCIE_INTEL_GW is not set +# CONFIG_PCIE_KEEMBAY_HOST is not set +# CONFIG_PCIE_MEDIATEK is not set +# CONFIG_PCIE_MEDIATEK_GEN3 is not set +# CONFIG_PCIE_MOBIVEIL_PLAT is not set +# CONFIG_PCIE_MT7621 is not set CONFIG_PCIE_PME=y +# CONFIG_PCIE_QCOM is not set +# CONFIG_PCIE_RCAR_HOST is not set CONFIG_PCIE_ROCKCHIP=y CONFIG_PCIE_ROCKCHIP_DW_HOST=y CONFIG_PCIE_ROCKCHIP_HOST=y +# CONFIG_PCIE_SPEAR13XX is not set +# CONFIG_PCIE_TEGRA194_HOST is not set +# CONFIG_PCIE_UNIPHIER is not set +# CONFIG_PCIE_VISCONTI_HOST is not set +# CONFIG_PCIE_XILINX_CPM is not set +# CONFIG_PCIE_XILINX_NWL is not set +# CONFIG_PCI_AARDVARK is not set CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y +# CONFIG_PCI_EXYNOS is not set +# CONFIG_PCI_IMX6 is not set +# CONFIG_PCI_KEYSTONE_HOST is not set +# CONFIG_PCI_LOONGSON is not set CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_STUB=y +# CONFIG_PCI_TEGRA is not set +# CONFIG_PCI_VERSATILE is not set CONFIG_PCS_XPCS=y # CONFIG_PECI is not set CONFIG_PGTABLE_LEVELS=4 CONFIG_PHYLIB=y CONFIG_PHYLINK=y CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_AM654_SERDES is not set +CONFIG_PHY_ATH79_USB=y +# CONFIG_PHY_BCM63XX_USBH is not set +# CONFIG_PHY_BCM_NS_USB2 is not set +# CONFIG_PHY_BCM_NS_USB3 is not set +# CONFIG_PHY_BCM_SR_PCIE is not set +# CONFIG_PHY_BCM_SR_USB is not set +# CONFIG_PHY_BERLIN_SATA is not set +# CONFIG_PHY_BERLIN_USB is not set +# CONFIG_PHY_BRCM_SATA is not set +# CONFIG_PHY_BRCM_USB is not set # CONFIG_PHY_CADENCE_DPHY_RX is not set +# CONFIG_PHY_CYGNUS_PCIE is not set +# CONFIG_PHY_DA8XX_USB is not set +# CONFIG_PHY_DM816X_USB is not set +# CONFIG_PHY_EXYNOS_PCIE is not set +# CONFIG_PHY_FSL_LYNX_28G is not set +# CONFIG_PHY_HI3660_USB is not set +# CONFIG_PHY_HI3670_PCIE is not set +# CONFIG_PHY_HI3670_USB is not set +# CONFIG_PHY_HI6220_USB is not set +# CONFIG_PHY_HISI_INNO_USB2 is not set +# CONFIG_PHY_HISTB_COMBPHY is not set +# CONFIG_PHY_INGENIC_USB is not set +# CONFIG_PHY_INTEL_KEEMBAY_USB is not set +# CONFIG_PHY_INTEL_LGM_COMBO is not set +# CONFIG_PHY_INTEL_LGM_EMMC is not set +# CONFIG_PHY_INTEL_THUNDERBAY_EMMC is not set +# CONFIG_PHY_J721E_WIZ is not set +# CONFIG_PHY_LANTIQ_RCU_USB2 is not set +# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set +# CONFIG_PHY_LPC18XX_USB_OTG is not set +# CONFIG_PHY_MESON8B_USB2 is not set +# CONFIG_PHY_MESON8_HDMI_TX is not set +# CONFIG_PHY_MESON_AXG_MIPI_DPHY is not set +# CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set +# CONFIG_PHY_MESON_AXG_PCIE is not set +# CONFIG_PHY_MESON_G12A_USB2 is not set +# CONFIG_PHY_MESON_G12A_USB3_PCIE is not set +# CONFIG_PHY_MESON_GXL_USB2 is not set +# CONFIG_PHY_MMP3_HSIC is not set +# CONFIG_PHY_MMP3_USB is not set +# CONFIG_PHY_MT7621_PCI is not set +# CONFIG_PHY_MTK_MIPI_DSI is not set +# CONFIG_PHY_MTK_TPHY is not set +# CONFIG_PHY_MTK_UFS is not set +# CONFIG_PHY_MTK_XSPHY is not set +CONFIG_PHY_MVEBU_A3700_COMPHY=y +CONFIG_PHY_MVEBU_A3700_UTMI=y +# CONFIG_PHY_MVEBU_A38X_COMPHY is not set +# CONFIG_PHY_MVEBU_CP110_COMPHY is not set +# CONFIG_PHY_NS2_PCIE is not set +# CONFIG_PHY_NS2_USB_DRD is not set +# CONFIG_PHY_PISTACHIO_USB is not set +# CONFIG_PHY_PXA_USB is not set +# CONFIG_PHY_QCOM_EDP is not set +# CONFIG_PHY_QCOM_IPQ4019_USB is not set +# CONFIG_PHY_QCOM_IPQ806X_USB is not set +# CONFIG_PHY_QCOM_PCIE2 is not set +# CONFIG_PHY_QCOM_QMP is not set +# CONFIG_PHY_QCOM_QUSB2 is not set +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set +# CONFIG_PHY_QCOM_USB_SS is not set +# CONFIG_PHY_RALINK_USB is not set +# CONFIG_PHY_RCAR_GEN3_USB3 is not set CONFIG_PHY_ROCKCHIP_DP=y CONFIG_PHY_ROCKCHIP_DPHY_RX0=y CONFIG_PHY_ROCKCHIP_EMMC=y @@ -584,10 +1173,152 @@ CONFIG_PHY_ROCKCHIP_PCIE=y CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y +# CONFIG_PHY_SAMSUNG_UFS is not set +# CONFIG_PHY_SPARX5_SERDES is not set +# CONFIG_PHY_STIH407_USB is not set +# CONFIG_PHY_STM32_USBPHYC is not set +# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set +# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set +# CONFIG_PHY_SUN4I_USB is not set +# CONFIG_PHY_SUN50I_USB3 is not set +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +# CONFIG_PHY_SUN9I_USB is not set +# CONFIG_PHY_TEGRA194_P2U is not set +# CONFIG_PHY_UNIPHIER_AHCI is not set +# CONFIG_PHY_UNIPHIER_PCIE is not set +# CONFIG_PHY_UNIPHIER_USB2 is not set +# CONFIG_PHY_UNIPHIER_USB3 is not set +# CONFIG_PHY_XILINX_ZYNQMP is not set CONFIG_PINCTRL=y +# CONFIG_PINCTRL_AS370 is not set +# CONFIG_PINCTRL_ASPEED_G4 is not set +# CONFIG_PINCTRL_ASPEED_G5 is not set +# CONFIG_PINCTRL_ASPEED_G6 is not set +# CONFIG_PINCTRL_AT91PIO4 is not set +# CONFIG_PINCTRL_BCM281XX is not set +# CONFIG_PINCTRL_BCM2835 is not set +# CONFIG_PINCTRL_BCM4908 is not set +# CONFIG_PINCTRL_BCM6318 is not set +# CONFIG_PINCTRL_BCM63268 is not set +# CONFIG_PINCTRL_BCM6328 is not set +# CONFIG_PINCTRL_BCM6358 is not set +# CONFIG_PINCTRL_BCM6362 is not set +# CONFIG_PINCTRL_BCM6368 is not set +# CONFIG_PINCTRL_BERLIN_BG4CT is not set +# CONFIG_PINCTRL_BM1880 is not set +# CONFIG_PINCTRL_CYGNUS_MUX is not set +# CONFIG_PINCTRL_DA850_PUPD is not set +# CONFIG_PINCTRL_EQUILIBRIUM is not set +# CONFIG_PINCTRL_IPROC_GPIO is not set +# CONFIG_PINCTRL_KEEMBAY is not set +# CONFIG_PINCTRL_LPASS_LPI is not set +# CONFIG_PINCTRL_LPC18XX is not set +# CONFIG_PINCTRL_MSM is not set +# CONFIG_PINCTRL_MT2701 is not set +# CONFIG_PINCTRL_MT2712 is not set +# CONFIG_PINCTRL_MT6397 is not set +# CONFIG_PINCTRL_MT6765 is not set +# CONFIG_PINCTRL_MT6797 is not set +# CONFIG_PINCTRL_MT7622 is not set +# CONFIG_PINCTRL_MT7623 is not set +# CONFIG_PINCTRL_MT7629 is not set +# CONFIG_PINCTRL_MT7986 is not set +# CONFIG_PINCTRL_MT8127 is not set +# CONFIG_PINCTRL_MT8135 is not set +# CONFIG_PINCTRL_MT8173 is not set +# CONFIG_PINCTRL_MT8183 is not set +# CONFIG_PINCTRL_MT8186 is not set +# CONFIG_PINCTRL_MT8195 is not set +# CONFIG_PINCTRL_MT8365 is not set +# CONFIG_PINCTRL_MT8516 is not set +# CONFIG_PINCTRL_NPCM7XX is not set +# CONFIG_PINCTRL_NS is not set +# CONFIG_PINCTRL_NS2_MUX is not set +# CONFIG_PINCTRL_NSP_GPIO is not set +# CONFIG_PINCTRL_NSP_MUX is not set +# CONFIG_PINCTRL_OWL is not set +# CONFIG_PINCTRL_PFC_EMEV2 is not set +# CONFIG_PINCTRL_PFC_R8A73A4 is not set +# CONFIG_PINCTRL_PFC_R8A7740 is not set +# CONFIG_PINCTRL_PFC_R8A7742 is not set +# CONFIG_PINCTRL_PFC_R8A7743 is not set +# CONFIG_PINCTRL_PFC_R8A7744 is not set +# CONFIG_PINCTRL_PFC_R8A7745 is not set +# CONFIG_PINCTRL_PFC_R8A77470 is not set +# CONFIG_PINCTRL_PFC_R8A774A1 is not set +# CONFIG_PINCTRL_PFC_R8A774B1 is not set +# CONFIG_PINCTRL_PFC_R8A774C0 is not set +# CONFIG_PINCTRL_PFC_R8A774E1 is not set +# CONFIG_PINCTRL_PFC_R8A7778 is not set +# CONFIG_PINCTRL_PFC_R8A7779 is not set +# CONFIG_PINCTRL_PFC_R8A7790 is not set +# CONFIG_PINCTRL_PFC_R8A7791 is not set +# CONFIG_PINCTRL_PFC_R8A7792 is not set +# CONFIG_PINCTRL_PFC_R8A7793 is not set +# CONFIG_PINCTRL_PFC_R8A7794 is not set +# CONFIG_PINCTRL_PFC_R8A77950 is not set +# CONFIG_PINCTRL_PFC_R8A77951 is not set +# CONFIG_PINCTRL_PFC_R8A77960 is not set +# CONFIG_PINCTRL_PFC_R8A77961 is not set +# CONFIG_PINCTRL_PFC_R8A77965 is not set +# CONFIG_PINCTRL_PFC_R8A77970 is not set +# CONFIG_PINCTRL_PFC_R8A77980 is not set +# CONFIG_PINCTRL_PFC_R8A77990 is not set +# CONFIG_PINCTRL_PFC_R8A77995 is not set +# CONFIG_PINCTRL_PFC_R8A779A0 is not set +# CONFIG_PINCTRL_PFC_R8A779F0 is not set +# CONFIG_PINCTRL_PFC_SH7203 is not set +# CONFIG_PINCTRL_PFC_SH7264 is not set +# CONFIG_PINCTRL_PFC_SH7269 is not set +# CONFIG_PINCTRL_PFC_SH73A0 is not set +# CONFIG_PINCTRL_PFC_SH7720 is not set +# CONFIG_PINCTRL_PFC_SH7722 is not set +# CONFIG_PINCTRL_PFC_SH7723 is not set +# CONFIG_PINCTRL_PFC_SH7724 is not set +# CONFIG_PINCTRL_PFC_SH7734 is not set +# CONFIG_PINCTRL_PFC_SH7757 is not set +# CONFIG_PINCTRL_PFC_SH7785 is not set +# CONFIG_PINCTRL_PFC_SH7786 is not set +# CONFIG_PINCTRL_PFC_SHX3 is not set +# CONFIG_PINCTRL_PISTACHIO is not set +# CONFIG_PINCTRL_PXA25X is not set +# CONFIG_PINCTRL_PXA27X is not set +# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set +# CONFIG_PINCTRL_RENESAS is not set CONFIG_PINCTRL_RK805=y CONFIG_PINCTRL_ROCKCHIP=y +# CONFIG_PINCTRL_RZA1 is not set +# CONFIG_PINCTRL_RZA2 is not set +# CONFIG_PINCTRL_RZG2L is not set +# CONFIG_PINCTRL_RZN1 is not set +# CONFIG_PINCTRL_S3C24XX is not set +# CONFIG_PINCTRL_S3C64XX is not set # CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SM8450 is not set +# CONFIG_PINCTRL_SPRD_SC9860 is not set +# CONFIG_PINCTRL_STARFIVE is not set +# CONFIG_PINCTRL_STM32F429 is not set +# CONFIG_PINCTRL_STM32F469 is not set +# CONFIG_PINCTRL_STM32F746 is not set +# CONFIG_PINCTRL_STM32F769 is not set +# CONFIG_PINCTRL_STM32H743 is not set +# CONFIG_PINCTRL_STM32MP135 is not set +# CONFIG_PINCTRL_STM32MP157 is not set +# CONFIG_PINCTRL_THUNDERBAY is not set +# CONFIG_PINCTRL_TI_IODELAY is not set +# CONFIG_PINCTRL_TMPV7700 is not set +CONFIG_PINCTRL_UNIPHIER=y +CONFIG_PINCTRL_UNIPHIER_LD11=y +CONFIG_PINCTRL_UNIPHIER_LD20=y +# CONFIG_PINCTRL_UNIPHIER_LD4 is not set +# CONFIG_PINCTRL_UNIPHIER_LD6B is not set +CONFIG_PINCTRL_UNIPHIER_NX1=y +# CONFIG_PINCTRL_UNIPHIER_PRO4 is not set +# CONFIG_PINCTRL_UNIPHIER_PRO5 is not set +# CONFIG_PINCTRL_UNIPHIER_PXS2 is not set +CONFIG_PINCTRL_UNIPHIER_PXS3=y +# CONFIG_PINCTRL_UNIPHIER_SLD8 is not set +# CONFIG_PINCTRL_WPCM450 is not set CONFIG_PL330_DMA=y CONFIG_PLATFORM_MHU=y CONFIG_PM=y @@ -597,8 +1328,14 @@ CONFIG_PM_DEVFREQ_EVENT=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_PM_OPP=y +# CONFIG_POLARFIRE_SOC_MAILBOX is not set CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_GEMINI_POWEROFF is not set +# CONFIG_POWER_RESET_KEYSTONE is not set +# CONFIG_POWER_RESET_OCELOT_RESET is not set +# CONFIG_POWER_RESET_RMOBILE is not set +# CONFIG_POWER_RESET_SC27XX is not set CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PPS=y @@ -614,10 +1351,72 @@ CONFIG_PRINTK_TIME=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_PROC_VMCORE=y CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_DTE=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PTP_1588_CLOCK_QORIQ=y CONFIG_PWM=y +# CONFIG_PWM_ATMEL is not set +# CONFIG_PWM_BCM2835 is not set +# CONFIG_PWM_BCM_IPROC is not set +# CONFIG_PWM_BCM_KONA is not set +# CONFIG_PWM_BERLIN is not set +# CONFIG_PWM_BRCMSTB is not set +# CONFIG_PWM_CLPS711X is not set +# CONFIG_PWM_EP93XX is not set +# CONFIG_PWM_HIBVT is not set +# CONFIG_PWM_IMG is not set +# CONFIG_PWM_IMX1 is not set +# CONFIG_PWM_IMX27 is not set +# CONFIG_PWM_IMX_TPM is not set +# CONFIG_PWM_INTEL_LGM is not set +# CONFIG_PWM_IQS620A is not set +# CONFIG_PWM_JZ4740 is not set +# CONFIG_PWM_KEEMBAY is not set +# CONFIG_PWM_LPC18XX_SCT is not set +# CONFIG_PWM_LPC32XX is not set +# CONFIG_PWM_LPSS_PCI is not set +# CONFIG_PWM_LPSS_PLATFORM is not set +# CONFIG_PWM_MEDIATEK is not set +# CONFIG_PWM_MESON is not set +# CONFIG_PWM_MTK_DISP is not set +# CONFIG_PWM_MXS is not set +# CONFIG_PWM_OMAP_DMTIMER is not set +# CONFIG_PWM_PXA is not set +# CONFIG_PWM_RASPBERRYPI_POE is not set +# CONFIG_PWM_RCAR is not set +# CONFIG_PWM_RENESAS_TPU is not set CONFIG_PWM_ROCKCHIP=y +# CONFIG_PWM_SAMSUNG is not set +# CONFIG_PWM_SIFIVE is not set +# CONFIG_PWM_SL28CPLD is not set +# CONFIG_PWM_SPEAR is not set +# CONFIG_PWM_SPRD is not set +# CONFIG_PWM_STI is not set +# CONFIG_PWM_STM32 is not set +# CONFIG_PWM_STM32_LP is not set +# CONFIG_PWM_SUN4I is not set CONFIG_PWM_SYSFS=y +# CONFIG_PWM_TEGRA is not set +# CONFIG_PWM_TIECAP is not set +# CONFIG_PWM_TIEHRPWM is not set +# CONFIG_PWM_VISCONTI is not set +# CONFIG_PWM_VT8500 is not set +# CONFIG_PXA168_ETH is not set +# CONFIG_QCOM_AOSS_QMP is not set +# CONFIG_QCOM_APCS_IPC is not set +# CONFIG_QCOM_COINCELL is not set +# CONFIG_QCOM_COMMAND_DB is not set +# CONFIG_QCOM_EBI2 is not set +# CONFIG_QCOM_GENI_SE is not set +# CONFIG_QCOM_GSBI is not set +# CONFIG_QCOM_IOMMU is not set +# CONFIG_QCOM_IPCC is not set +# CONFIG_QCOM_LLCC is not set +# CONFIG_QCOM_QFPROM is not set +# CONFIG_QCOM_QMI_HELPERS is not set +# CONFIG_QCOM_RPMH is not set +# CONFIG_QCOM_SMEM is not set +# CONFIG_QCOM_SPM is not set # CONFIG_QFMT_V1 is not set # CONFIG_QFMT_V2 is not set CONFIG_QUEUED_RWLOCKS=y @@ -631,8 +1430,13 @@ CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MODULE_REGION_FULL=y CONFIG_RAS=y CONFIG_RATIONAL=y +# CONFIG_RAVB is not set # CONFIG_RAVE_SP_CORE is not set +# CONFIG_RCAR_DMAC is not set +# CONFIG_RCAR_GEN3_THERMAL is not set +# CONFIG_RCAR_THERMAL is not set CONFIG_RCU_TRACE=y +# CONFIG_RDA_TIMER is not set CONFIG_REALTEK_PHY=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y @@ -643,14 +1447,58 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_MAX77650 is not set +# CONFIG_REGULATOR_MAX77686 is not set +# CONFIG_REGULATOR_MAX77693 is not set +# CONFIG_REGULATOR_MAX77802 is not set +# CONFIG_REGULATOR_MAX8907 is not set +# CONFIG_REGULATOR_PBIAS is not set CONFIG_REGULATOR_PWM=y +# CONFIG_REGULATOR_QCOM_LABIBB is not set +# CONFIG_REGULATOR_QCOM_RPMH is not set +# CONFIG_REGULATOR_QCOM_SPMI is not set +# CONFIG_REGULATOR_QCOM_USB_VBUS is not set CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT5190A is not set +# CONFIG_REGULATOR_S2MPA01 is not set +# CONFIG_REGULATOR_S2MPS11 is not set +# CONFIG_REGULATOR_S5M8767 is not set +# CONFIG_REGULATOR_SC2731 is not set +# CONFIG_REGULATOR_STM32_BOOSTER is not set +# CONFIG_REGULATOR_STM32_PWR is not set +# CONFIG_REGULATOR_STM32_VREFBUF is not set +# CONFIG_REGULATOR_STW481X_VMMC is not set # CONFIG_REGULATOR_SY7636A is not set # CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS68470 is not set +# CONFIG_REGULATOR_UNIPHIER is not set CONFIG_RELOCATABLE=y +CONFIG_RENESAS_DMA=y +# CONFIG_RENESAS_H8S_INTC is not set +# CONFIG_RENESAS_INTC_IRQPIN is not set +# CONFIG_RENESAS_IRQC is not set +# CONFIG_RENESAS_OSTM is not set +# CONFIG_RENESAS_RZA1_IRQC is not set +# CONFIG_RENESAS_USB_DMAC is not set +# CONFIG_RESET_AXS10X is not set +# CONFIG_RESET_BCM6345 is not set +# CONFIG_RESET_BRCMSTB is not set CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_HISI is not set +# CONFIG_RESET_HSDK is not set +# CONFIG_RESET_K210 is not set +# CONFIG_RESET_MESON_AUDIO_ARB is not set +# CONFIG_RESET_NPCM is not set +# CONFIG_RESET_QCOM_AOSS is not set +# CONFIG_RESET_QCOM_PDC is not set +# CONFIG_RESET_RASPBERRYPI is not set +# CONFIG_RESET_RZG2L_USBPHY_CTRL is not set CONFIG_RESET_SCMI=y +# CONFIG_RESET_SIMPLE is not set +# CONFIG_RESET_STARFIVE_JH7100 is not set +# CONFIG_RESET_TN48M_CPLD is not set +# CONFIG_RESET_UNIPHIER is not set +# CONFIG_RESET_UNIPHIER_GLUE is not set CONFIG_RFS_ACCEL=y # CONFIG_ROCKCHIP_ANALOGIX_DP is not set # CONFIG_ROCKCHIP_CDN_DP is not set @@ -676,15 +1524,59 @@ CONFIG_RODATA_FULL_DEFAULT_ENABLED=y CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_ASM9260 is not set +# CONFIG_RTC_DRV_ASPEED is not set +# CONFIG_RTC_DRV_AT91RM9200 is not set +# CONFIG_RTC_DRV_AT91SAM9 is not set +# CONFIG_RTC_DRV_BRCMSTB is not set +# CONFIG_RTC_DRV_DAVINCI is not set +# CONFIG_RTC_DRV_DIGICOLOR is not set +# CONFIG_RTC_DRV_FSL_FTM_ALARM is not set +# CONFIG_RTC_DRV_GAMECUBE is not set +# CONFIG_RTC_DRV_LPC24XX is not set +# CONFIG_RTC_DRV_LPC32XX is not set +# CONFIG_RTC_DRV_MAX77686 is not set +# CONFIG_RTC_DRV_MAX8907 is not set +# CONFIG_RTC_DRV_MESON is not set +# CONFIG_RTC_DRV_MESON_VRTC is not set +# CONFIG_RTC_DRV_MSC313 is not set +# CONFIG_RTC_DRV_MT6397 is not set +# CONFIG_RTC_DRV_MT7622 is not set +# CONFIG_RTC_DRV_MV is not set +# CONFIG_RTC_DRV_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +# CONFIG_RTC_DRV_PM8XXX is not set CONFIG_RTC_DRV_RK808=y +# CONFIG_RTC_DRV_RTD119X is not set +# CONFIG_RTC_DRV_S3C is not set +# CONFIG_RTC_DRV_S5M is not set +# CONFIG_RTC_DRV_SC27XX is not set +CONFIG_RTC_DRV_SPEAR=y +# CONFIG_RTC_DRV_STM32 is not set +# CONFIG_RTC_DRV_STMP is not set +# CONFIG_RTC_DRV_SUNXI is not set +# CONFIG_RTC_DRV_TEGRA is not set +# CONFIG_RTC_DRV_VR41XX is not set +# CONFIG_RTC_DRV_VT8500 is not set CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTC_NVMEM=y # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_RZG2L_THERMAL is not set +# CONFIG_RZ_DMAC is not set +# CONFIG_S390_AP_IOMMU is not set +# CONFIG_S390_CCW_IOMMU is not set +# CONFIG_S3C2410_COMMON_CLK is not set +# CONFIG_S3C2412_COMMON_CLK is not set +# CONFIG_S3C2443_COMMON_CLK is not set +# CONFIG_S3C24XX_DMAC is not set CONFIG_SATA_AHCI=y +# CONFIG_SATA_AHCI_SEATTLE is not set +# CONFIG_SATA_GEMINI is not set CONFIG_SATA_HOST=y CONFIG_SATA_PMP=y CONFIG_SATA_SIS=y +# CONFIG_SC27XX_EFUSE is not set CONFIG_SCHED_MC=y CONFIG_SCSI=y CONFIG_SCSI_COMMON=y @@ -697,9 +1589,15 @@ CONFIG_SCSI_SAS_LIBSAS=y # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SENSORS_ARM_SCMI is not set CONFIG_SENSORS_ARM_SCPI=y +# CONFIG_SENSORS_BT1_PVT is not set +# CONFIG_SENSORS_RASPBERRYPI_HWMON is not set +# CONFIG_SENSORS_SL28CPLD is not set +# CONFIG_SENSORS_SPARX5 is not set # CONFIG_SENSORS_SY7636A is not set # CONFIG_SENSORS_TMP464 is not set CONFIG_SERIAL_8250_ASPEED_VUART=y +# CONFIG_SERIAL_8250_BCM2835AUX is not set +# CONFIG_SERIAL_8250_BCM7271 is not set CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_DWLIB=y @@ -707,38 +1605,145 @@ CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_FINTEK=y CONFIG_SERIAL_8250_FSL=y +# CONFIG_SERIAL_8250_IOC3 is not set +# CONFIG_SERIAL_8250_LPC18XX is not set +# CONFIG_SERIAL_8250_MT6577 is not set CONFIG_SERIAL_8250_NR_UARTS=4 +# CONFIG_SERIAL_8250_OMAP is not set CONFIG_SERIAL_8250_PCI=y +# CONFIG_SERIAL_8250_PXA is not set CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_TEGRA=y +# CONFIG_SERIAL_8250_UNIPHIER is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_SERIAL_ATMEL is not set +# CONFIG_SERIAL_CLPS711X is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_SERIAL_HS_LPC32XX is not set +# CONFIG_SERIAL_ICOM is not set +# CONFIG_SERIAL_IMX is not set +# CONFIG_SERIAL_IMX_EARLYCON is not set +# CONFIG_SERIAL_LANTIQ is not set +# CONFIG_SERIAL_LITEUART is not set CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_MESON is not set +# CONFIG_SERIAL_MILBEAUT_USIO is not set +# CONFIG_SERIAL_MPS2_UART is not set +# CONFIG_SERIAL_MSM is not set +# CONFIG_SERIAL_MVEBU_UART is not set +# CONFIG_SERIAL_MXS_AUART is not set CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_OMAP is not set +# CONFIG_SERIAL_OWL is not set +# CONFIG_SERIAL_RDA is not set +# CONFIG_SERIAL_SAMSUNG is not set +# CONFIG_SERIAL_SUNPLUS is not set +# CONFIG_SERIAL_TEGRA is not set +# CONFIG_SERIAL_TEGRA_TCU is not set +# CONFIG_SERIAL_VT8500 is not set CONFIG_SERIO=y CONFIG_SERIO_AMBAKMI=y CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_OLPC_APSP is not set CONFIG_SERIO_PCIPS2=y CONFIG_SERIO_RAW=y CONFIG_SG_POOL=y +# CONFIG_SHORTCUT_FE is not set +# CONFIG_SH_DMAE is not set +CONFIG_SH_DMAE_BASE=y +# CONFIG_SL28CPLD_INTC is not set CONFIG_SLUB_DEBUG=y CONFIG_SMP=y +# CONFIG_SNI_AVE is not set +# CONFIG_SNI_NETSEC is not set CONFIG_SOCK_RX_QUEUE_MAPPING=y +# CONFIG_SOC_BCM63XX is not set CONFIG_SOC_BUS=y +# CONFIG_SOC_IMX8M is not set +# CONFIG_SOC_RENESAS is not set +# CONFIG_SOC_SAMSUNG is not set +# CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER is not set +# CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER is not set CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSE_IRQ=y +# CONFIG_SPARX5_SWITCH is not set +# CONFIG_SPEAR_THERMAL is not set CONFIG_SPI=y +# CONFIG_SPI_AR934X is not set +# CONFIG_SPI_ARMADA_3700 is not set +# CONFIG_SPI_ASPEED_SMC is not set +# CONFIG_SPI_ATH79 is not set +# CONFIG_SPI_ATMEL is not set +# CONFIG_SPI_ATMEL_QUADSPI is not set +# CONFIG_SPI_BCM2835AUX is not set +# CONFIG_SPI_BCM63XX is not set +# CONFIG_SPI_BCM63XX_HSSPI is not set CONFIG_SPI_BITBANG=y +# CONFIG_SPI_CLPS711X is not set CONFIG_SPI_DYNAMIC=y +# CONFIG_SPI_EP93XX is not set +# CONFIG_SPI_FSL_LPSPI is not set +# CONFIG_SPI_FSL_QUADSPI is not set +# CONFIG_SPI_HISI_KUNPENG is not set +# CONFIG_SPI_HISI_SFC is not set +# CONFIG_SPI_HISI_SFC_V3XX is not set +# CONFIG_SPI_IMX is not set +# CONFIG_SPI_INGENIC is not set +# CONFIG_SPI_INTEL_PCI is not set +# CONFIG_SPI_INTEL_PLATFORM is not set +# CONFIG_SPI_JCORE is not set +# CONFIG_SPI_LP8841_RTC is not set CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y +# CONFIG_SPI_MESON_SPICC is not set +# CONFIG_SPI_MESON_SPIFC is not set +# CONFIG_SPI_MT65XX is not set +# CONFIG_SPI_MT7621 is not set +# CONFIG_SPI_MTK_NOR is not set +# CONFIG_SPI_NPCM_FIU is not set +# CONFIG_SPI_NPCM_PSPI is not set +# CONFIG_SPI_NXP_SPIFI is not set +# CONFIG_SPI_OMAP24XX is not set +# CONFIG_SPI_OMAP_100K is not set +# CONFIG_SPI_PIC32 is not set +# CONFIG_SPI_PIC32_SQI is not set +# CONFIG_SPI_QUP is not set CONFIG_SPI_ROCKCHIP=y +# CONFIG_SPI_RSPI is not set +# CONFIG_SPI_SH is not set +# CONFIG_SPI_SH_HSPI is not set +# CONFIG_SPI_SH_MSIOF is not set CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_SPRD is not set +# CONFIG_SPI_SPRD_ADI is not set +# CONFIG_SPI_STM32 is not set +# CONFIG_SPI_STM32_QSPI is not set +# CONFIG_SPI_ST_SSC4 is not set +# CONFIG_SPI_SUN4I is not set +# CONFIG_SPI_SUN6I is not set +# CONFIG_SPI_SUNPLUS_SP7021 is not set +# CONFIG_SPI_SYNQUACER is not set +# CONFIG_SPI_TEGRA114 is not set +# CONFIG_SPI_TEGRA20_SFLASH is not set +# CONFIG_SPI_TEGRA20_SLINK is not set +# CONFIG_SPI_TEGRA210_QUAD is not set +# CONFIG_SPI_UNIPHIER is not set +# CONFIG_SPI_XLP is not set +# CONFIG_SPI_XTENSA_XTFPGA is not set +# CONFIG_SPI_ZYNQ_QSPI is not set +# CONFIG_SPRD_COMMON_CLK is not set +# CONFIG_SPRD_DMA is not set +# CONFIG_SPRD_EFUSE is not set +# CONFIG_SPRD_IOMMU is not set +# CONFIG_SPRD_MBOX is not set +# CONFIG_SPRD_THERMAL is not set +# CONFIG_SPRD_TIMER is not set # CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set CONFIG_SQUASHFS_DECOMP_SINGLE=y # CONFIG_SQUASHFS_EMBEDDED is not set @@ -748,14 +1753,25 @@ CONFIG_SRAM=y CONFIG_SRCU=y CONFIG_STACKDEPOT=y CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_PER_TASK=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_STACKTRACE=y +# CONFIG_STM32_DMA is not set +# CONFIG_STM32_DMAMUX is not set +# CONFIG_STM32_IPCC is not set +# CONFIG_STM32_MDMA is not set CONFIG_STMMAC_ETH=y CONFIG_STMMAC_PLATFORM=y # CONFIG_STMMAC_SELFTESTS is not set CONFIG_STRICT_DEVMEM=y # CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_STUB_CLK_HI3660 is not set +# CONFIG_STUB_CLK_HI6220 is not set +# CONFIG_SUN4I_TIMER is not set +# CONFIG_SUN50I_IOMMU is not set +# CONFIG_SUN5I_HSTIMER is not set +# CONFIG_SUN6I_MSGBOX is not set +# CONFIG_SUN8I_THERMAL is not set +# CONFIG_SUNXI_CCU is not set # CONFIG_SWAP is not set CONFIG_SWIOTLB=y CONFIG_SWPHY=y @@ -763,6 +1779,12 @@ CONFIG_SYNC_FILE=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYSFS_SYSCALL=y CONFIG_SYSVIPC_COMPAT=y +# CONFIG_TEGRA20_APB_DMA is not set +# CONFIG_TEGRA210_ADMA is not set +# CONFIG_TEGRA30_TSENSOR is not set +# CONFIG_TEGRA_BPMP_THERMAL is not set +# CONFIG_TEGRA_SOCTHERM is not set +# CONFIG_TEGRA_TIMER is not set # CONFIG_TEXTSEARCH is not set CONFIG_THERMAL=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y @@ -774,9 +1796,17 @@ CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y CONFIG_THREAD_INFO_IN_TASK=y CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_TIMER_IMX_SYS_CTR is not set CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y # CONFIG_TINYDRM_ILI9163 is not set +# CONFIG_TI_CPSW_SWITCHDEV is not set +# CONFIG_TI_DAVINCI_EMAC is not set +CONFIG_TI_DMA_CROSSBAR=y +CONFIG_TI_EDMA=y +# CONFIG_TI_PIPE3 is not set +# CONFIG_TI_SOC_THERMAL is not set +# CONFIG_TI_SYSCON_CLK is not set CONFIG_TRACE_CLOCK=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y @@ -784,11 +1814,14 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y CONFIG_TRANS_TABLE=y CONFIG_TREE_RCU=y CONFIG_TREE_SRCU=y +# CONFIG_TS4800_IRQ is not set +# CONFIG_TURRIS_MOX_RWTM is not set CONFIG_TYPEC=y # CONFIG_TYPEC_DP_ALTMODE is not set CONFIG_TYPEC_FUSB302=y # CONFIG_TYPEC_HD3SS3220 is not set # CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_QCOM_PMIC is not set # CONFIG_TYPEC_RT1719 is not set # CONFIG_TYPEC_STUSB160X is not set # CONFIG_TYPEC_TCPCI is not set @@ -799,37 +1832,72 @@ CONFIG_TYPEC_TCPM=y # CONFIG_UCLAMP_TASK is not set # CONFIG_UEVENT_HELPER is not set CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_UNIPHIER_EFUSE is not set +# CONFIG_UNIPHIER_MDMAC is not set +# CONFIG_UNIPHIER_THERMAL is not set +# CONFIG_UNIPHIER_XDMAC is not set CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_USB=y +# CONFIG_USB_BRCMSTB is not set +# CONFIG_USB_CNS3XXX_EHCI is not set +# CONFIG_USB_CNS3XXX_OHCI is not set CONFIG_USB_COMMON=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_HOST=y +CONFIG_USB_DWC3_IMX8MP=y +CONFIG_USB_DWC3_MESON_G12A=y CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_ST=y +# CONFIG_USB_EHCI_EXYNOS is not set CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_NPCM7XX is not set +# CONFIG_USB_EHCI_HCD_ORION is not set CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_EHCI_HCD_SPEAR is not set +# CONFIG_USB_EHCI_HCD_STI is not set # CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_SH is not set CONFIG_USB_HID=y +# CONFIG_USB_OHCI_EXYNOS is not set CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_AT91 is not set +# CONFIG_USB_OHCI_HCD_DAVINCI is not set +# CONFIG_USB_OHCI_HCD_OMAP3 is not set CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_OHCI_HCD_S3C2410 is not set +# CONFIG_USB_OHCI_HCD_SPEAR is not set +# CONFIG_USB_OHCI_HCD_STI is not set +# CONFIG_USB_OHCI_SH is not set CONFIG_USB_PHY=y +# CONFIG_USB_QCOM_EUD is not set CONFIG_USB_ROLE_SWITCH=y CONFIG_USB_STORAGE=y CONFIG_USB_SUPPORT=y +# CONFIG_USB_TEGRA_PHY is not set CONFIG_USB_ULPI=y CONFIG_USB_ULPI_BUS=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_HISTB is not set +# CONFIG_USB_XHCI_MTK is not set CONFIG_USB_XHCI_PLATFORM=y +# CONFIG_USB_XHCI_RCAR is not set CONFIG_USERIO=y +# CONFIG_UX500_SOC_ID is not set CONFIG_VIDEOMODE_HELPERS=y # CONFIG_VIRTIO_MENU is not set CONFIG_VMAP_STACK=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_VT=y +# CONFIG_VT8500_TIMER is not set CONFIG_VT_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_WARN_ABI_ERRORS is not set +# CONFIG_WARN_MISSING_DOCUMENTS is not set # CONFIG_WATCHDOG is not set CONFIG_XARRAY_MULTI=y +# CONFIG_XGENE_DMA is not set CONFIG_XPS=y CONFIG_XXHASH=y CONFIG_XZ_DEC_ARM=y diff --git a/target/linux/rockchip/patches-5.18/903-crypto-rockchip-permit-to-pass-self-tests.patch b/target/linux/rockchip/patches-5.18/903-crypto-rockchip-permit-to-pass-self-tests.patch new file mode 100644 index 000000000..161435577 --- /dev/null +++ b/target/linux/rockchip/patches-5.18/903-crypto-rockchip-permit-to-pass-self-tests.patch @@ -0,0 +1,8642 @@ +From patchwork Wed Jul 6 09:03:40 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907886 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.33 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:33 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 01/33] crypto: rockchip: use dev_err for error message + about interrupt +Date: Wed, 6 Jul 2022 09:03:40 +0000 +Message-Id: <20220706090412.806101-2-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020437_385385_DD262621 +X-CRM114-Status: GOOD ( 11.86 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Interrupt is mandatory so the message should be printed as error. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index 35d73061d156..45cc5f766788 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -371,8 +371,7 @@ static int rk_crypto_probe(struct platform_device *pdev) + + crypto_info->irq = platform_get_irq(pdev, 0); + if (crypto_info->irq < 0) { +- dev_warn(crypto_info->dev, +- "control Interrupt is not available.\n"); ++ dev_err(&pdev->dev, "control Interrupt is not available.\n"); + err = crypto_info->irq; + goto err_crypto; + } + +From patchwork Wed Jul 6 09:03:41 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907887 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 742A4C43334 + for ; + Wed, 6 Jul 2022 10:22:21 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20210309; h=Sender: + Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: + Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: + Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: + List-Owner; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.34 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:34 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 02/33] crypto: rockchip: do not use uninitialized variable +Date: Wed, 6 Jul 2022 09:03:41 +0000 +Message-Id: <20220706090412.806101-3-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020438_347314_8D2B1347 +X-CRM114-Status: GOOD ( 11.14 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +crypto_info->dev is not yet set, so use pdev->dev instead. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index 45cc5f766788..21d3f1458584 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -381,7 +381,7 @@ static int rk_crypto_probe(struct platform_device *pdev) + "rk-crypto", pdev); + + if (err) { +- dev_err(crypto_info->dev, "irq request failed.\n"); ++ dev_err(&pdev->dev, "irq request failed.\n"); + goto err_crypto; + } + + +From patchwork Wed Jul 6 09:03:42 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12908008 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id EBEA6C433EF + for ; + Wed, 6 Jul 2022 11:31:26 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20210309; h=Sender: + Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: + Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: + Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: + List-Owner; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.35 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:35 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 03/33] crypto: rockchip: do not do custom power management +Date: Wed, 6 Jul 2022 09:03:42 +0000 +Message-Id: <20220706090412.806101-4-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020441_003461_51A9D1D3 +X-CRM114-Status: GOOD ( 15.38 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +The clock enable/disable at tfm init/exit is fragile, +if 2 tfm are init in the same time and one is removed just after, +it will leave the hardware uncloked even if a user remains. + +Instead simply enable clocks at probe time. +We will do PM later. + +Fixes: ce0183cb6464b ("crypto: rockchip - switch to skcipher API") +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 4 ++-- + drivers/crypto/rockchip/rk3288_crypto.h | 2 -- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 3 +-- + drivers/crypto/rockchip/rk3288_crypto_skcipher.c | 5 +++-- + 4 files changed, 6 insertions(+), 8 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index 21d3f1458584..4cff49b82983 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -394,8 +394,7 @@ static int rk_crypto_probe(struct platform_device *pdev) + rk_crypto_done_task_cb, (unsigned long)crypto_info); + crypto_init_queue(&crypto_info->queue, 50); + +- crypto_info->enable_clk = rk_crypto_enable_clk; +- crypto_info->disable_clk = rk_crypto_disable_clk; ++ rk_crypto_enable_clk(crypto_info); + crypto_info->load_data = rk_load_data; + crypto_info->unload_data = rk_unload_data; + crypto_info->enqueue = rk_crypto_enqueue; +@@ -422,6 +421,7 @@ static int rk_crypto_remove(struct platform_device *pdev) + struct rk_crypto_info *crypto_tmp = platform_get_drvdata(pdev); + + rk_crypto_unregister(); ++ rk_crypto_disable_clk(crypto_tmp); + tasklet_kill(&crypto_tmp->done_task); + tasklet_kill(&crypto_tmp->queue_task); + return 0; +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index 97278c2574ff..2fa7131e4060 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -220,8 +220,6 @@ struct rk_crypto_info { + int (*start)(struct rk_crypto_info *dev); + int (*update)(struct rk_crypto_info *dev); + void (*complete)(struct crypto_async_request *base, int err); +- int (*enable_clk)(struct rk_crypto_info *dev); +- void (*disable_clk)(struct rk_crypto_info *dev); + int (*load_data)(struct rk_crypto_info *dev, + struct scatterlist *sg_src, + struct scatterlist *sg_dst); +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index ed03058497bc..49017d1fb510 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -301,7 +301,7 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) + sizeof(struct rk_ahash_rctx) + + crypto_ahash_reqsize(tctx->fallback_tfm)); + +- return tctx->dev->enable_clk(tctx->dev); ++ return 0; + } + + static void rk_cra_hash_exit(struct crypto_tfm *tfm) +@@ -309,7 +309,6 @@ static void rk_cra_hash_exit(struct crypto_tfm *tfm) + struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm); + + free_page((unsigned long)tctx->dev->addr_vir); +- return tctx->dev->disable_clk(tctx->dev); + } + + struct rk_crypto_tmp rk_ahash_sha1 = { +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 5bbf0d2722e1..8c44a19eab75 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -388,8 +388,10 @@ static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) + ctx->dev->update = rk_ablk_rx; + ctx->dev->complete = rk_crypto_complete; + ctx->dev->addr_vir = (char *)__get_free_page(GFP_KERNEL); ++ if (!ctx->dev->addr_vir) ++ return -ENOMEM; + +- return ctx->dev->addr_vir ? ctx->dev->enable_clk(ctx->dev) : -ENOMEM; ++ return 0; + } + + static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm) +@@ -397,7 +399,6 @@ static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm) + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + + free_page((unsigned long)ctx->dev->addr_vir); +- ctx->dev->disable_clk(ctx->dev); + } + + struct rk_crypto_tmp rk_ecb_aes_alg = { + +From patchwork Wed Jul 6 09:03:43 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907931 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DBC8C433EF + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.36 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:36 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 04/33] crypto: rockchip: fix privete/private typo +Date: Wed, 6 Jul 2022 09:03:43 +0000 +Message-Id: <20220706090412.806101-5-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020440_985300_D79065AD +X-CRM114-Status: GOOD ( 10.35 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +This fix a simple typo on private word. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index 2fa7131e4060..656d6795d400 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -235,7 +235,7 @@ struct rk_ahash_ctx { + struct crypto_ahash *fallback_tfm; + }; + +-/* the privete variable of hash for fallback */ ++/* the private variable of hash for fallback */ + struct rk_ahash_rctx { + struct ahash_request fallback_req; + u32 mode; + +From patchwork Wed Jul 6 09:03:44 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907932 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 6405DC433EF + for ; + Wed, 6 Jul 2022 10:27:18 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20210309; h=Sender: + Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: + Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: + Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: + List-Owner; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.37 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:37 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 05/33] crypto: rockchip: do not store mode globally +Date: Wed, 6 Jul 2022 09:03:44 +0000 +Message-Id: <20220706090412.806101-6-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020442_266221_9DCBFC59 +X-CRM114-Status: GOOD ( 16.95 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Storing the mode globally does not work if 2 requests are handled in the +same time. +We should store it in a request context. + +Fixes: ce0183cb6464b ("crypto: rockchip - switch to skcipher API") +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.h | 5 +- + .../crypto/rockchip/rk3288_crypto_skcipher.c | 58 ++++++++++++------- + 2 files changed, 41 insertions(+), 22 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index 656d6795d400..c919d9a43a08 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -245,10 +245,13 @@ struct rk_ahash_rctx { + struct rk_cipher_ctx { + struct rk_crypto_info *dev; + unsigned int keylen; +- u32 mode; + u8 iv[AES_BLOCK_SIZE]; + }; + ++struct rk_cipher_rctx { ++ u32 mode; ++}; ++ + enum alg_type { + ALG_TYPE_HASH, + ALG_TYPE_CIPHER, +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 8c44a19eab75..bbd0bf52bf07 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -76,9 +76,10 @@ static int rk_aes_ecb_encrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_AES_ECB_MODE; ++ rctx->mode = RK_CRYPTO_AES_ECB_MODE; + return rk_handle_req(dev, req); + } + +@@ -86,9 +87,10 @@ static int rk_aes_ecb_decrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_AES_ECB_MODE | RK_CRYPTO_DEC; ++ rctx->mode = RK_CRYPTO_AES_ECB_MODE | RK_CRYPTO_DEC; + return rk_handle_req(dev, req); + } + +@@ -96,9 +98,10 @@ static int rk_aes_cbc_encrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_AES_CBC_MODE; ++ rctx->mode = RK_CRYPTO_AES_CBC_MODE; + return rk_handle_req(dev, req); + } + +@@ -106,9 +109,10 @@ static int rk_aes_cbc_decrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_AES_CBC_MODE | RK_CRYPTO_DEC; ++ rctx->mode = RK_CRYPTO_AES_CBC_MODE | RK_CRYPTO_DEC; + return rk_handle_req(dev, req); + } + +@@ -116,9 +120,10 @@ static int rk_des_ecb_encrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = 0; ++ rctx->mode = 0; + return rk_handle_req(dev, req); + } + +@@ -126,9 +131,10 @@ static int rk_des_ecb_decrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_DEC; ++ rctx->mode = RK_CRYPTO_DEC; + return rk_handle_req(dev, req); + } + +@@ -136,9 +142,10 @@ static int rk_des_cbc_encrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC; ++ rctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC; + return rk_handle_req(dev, req); + } + +@@ -146,9 +153,10 @@ static int rk_des_cbc_decrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC | RK_CRYPTO_DEC; ++ rctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC | RK_CRYPTO_DEC; + return rk_handle_req(dev, req); + } + +@@ -156,9 +164,10 @@ static int rk_des3_ede_ecb_encrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_TDES_SELECT; ++ rctx->mode = RK_CRYPTO_TDES_SELECT; + return rk_handle_req(dev, req); + } + +@@ -166,9 +175,10 @@ static int rk_des3_ede_ecb_decrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_DEC; ++ rctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_DEC; + return rk_handle_req(dev, req); + } + +@@ -176,9 +186,10 @@ static int rk_des3_ede_cbc_encrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_TDES_CHAINMODE_CBC; ++ rctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_TDES_CHAINMODE_CBC; + return rk_handle_req(dev, req); + } + +@@ -186,9 +197,10 @@ static int rk_des3_ede_cbc_decrypt(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *dev = ctx->dev; + +- ctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_TDES_CHAINMODE_CBC | ++ rctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_TDES_CHAINMODE_CBC | + RK_CRYPTO_DEC; + return rk_handle_req(dev, req); + } +@@ -199,6 +211,7 @@ static void rk_ablk_hw_init(struct rk_crypto_info *dev) + skcipher_request_cast(dev->async_req); + struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req); + struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(cipher); + u32 ivsize, block, conf_reg = 0; + +@@ -206,22 +219,22 @@ static void rk_ablk_hw_init(struct rk_crypto_info *dev) + ivsize = crypto_skcipher_ivsize(cipher); + + if (block == DES_BLOCK_SIZE) { +- ctx->mode |= RK_CRYPTO_TDES_FIFO_MODE | ++ rctx->mode |= RK_CRYPTO_TDES_FIFO_MODE | + RK_CRYPTO_TDES_BYTESWAP_KEY | + RK_CRYPTO_TDES_BYTESWAP_IV; +- CRYPTO_WRITE(dev, RK_CRYPTO_TDES_CTRL, ctx->mode); ++ CRYPTO_WRITE(dev, RK_CRYPTO_TDES_CTRL, rctx->mode); + memcpy_toio(dev->reg + RK_CRYPTO_TDES_IV_0, req->iv, ivsize); + conf_reg = RK_CRYPTO_DESSEL; + } else { +- ctx->mode |= RK_CRYPTO_AES_FIFO_MODE | ++ rctx->mode |= RK_CRYPTO_AES_FIFO_MODE | + RK_CRYPTO_AES_KEY_CHANGE | + RK_CRYPTO_AES_BYTESWAP_KEY | + RK_CRYPTO_AES_BYTESWAP_IV; + if (ctx->keylen == AES_KEYSIZE_192) +- ctx->mode |= RK_CRYPTO_AES_192BIT_key; ++ rctx->mode |= RK_CRYPTO_AES_192BIT_key; + else if (ctx->keylen == AES_KEYSIZE_256) +- ctx->mode |= RK_CRYPTO_AES_256BIT_key; +- CRYPTO_WRITE(dev, RK_CRYPTO_AES_CTRL, ctx->mode); ++ rctx->mode |= RK_CRYPTO_AES_256BIT_key; ++ CRYPTO_WRITE(dev, RK_CRYPTO_AES_CTRL, rctx->mode); + memcpy_toio(dev->reg + RK_CRYPTO_AES_IV_0, req->iv, ivsize); + } + conf_reg |= RK_CRYPTO_BYTESWAP_BTFIFO | +@@ -246,6 +259,7 @@ static int rk_set_data_start(struct rk_crypto_info *dev) + struct skcipher_request *req = + skcipher_request_cast(dev->async_req); + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + u32 ivsize = crypto_skcipher_ivsize(tfm); + u8 *src_last_blk = page_address(sg_page(dev->sg_src)) + +@@ -254,7 +268,7 @@ static int rk_set_data_start(struct rk_crypto_info *dev) + /* Store the iv that need to be updated in chain mode. + * And update the IV buffer to contain the next IV for decryption mode. + */ +- if (ctx->mode & RK_CRYPTO_DEC) { ++ if (rctx->mode & RK_CRYPTO_DEC) { + memcpy(ctx->iv, src_last_blk, ivsize); + sg_pcopy_to_buffer(dev->first, dev->src_nents, req->iv, + ivsize, dev->total - ivsize); +@@ -294,11 +308,12 @@ static void rk_iv_copyback(struct rk_crypto_info *dev) + struct skcipher_request *req = + skcipher_request_cast(dev->async_req); + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + u32 ivsize = crypto_skcipher_ivsize(tfm); + + /* Update the IV buffer to contain the next IV for encryption mode. */ +- if (!(ctx->mode & RK_CRYPTO_DEC)) { ++ if (!(rctx->mode & RK_CRYPTO_DEC)) { + if (dev->aligned) { + memcpy(req->iv, sg_virt(dev->sg_dst) + + dev->sg_dst->length - ivsize, ivsize); +@@ -314,11 +329,12 @@ static void rk_update_iv(struct rk_crypto_info *dev) + struct skcipher_request *req = + skcipher_request_cast(dev->async_req); + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + u32 ivsize = crypto_skcipher_ivsize(tfm); + u8 *new_iv = NULL; + +- if (ctx->mode & RK_CRYPTO_DEC) { ++ if (rctx->mode & RK_CRYPTO_DEC) { + new_iv = ctx->iv; + } else { + new_iv = page_address(sg_page(dev->sg_dst)) + + +From patchwork Wed Jul 6 09:03:45 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907939 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 33449C43334 + for ; + Wed, 6 Jul 2022 10:29:37 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20210309; h=Sender: + Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: + Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: + Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: + List-Owner; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.38 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:38 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 06/33] crypto: rockchip: add fallback for cipher +Date: Wed, 6 Jul 2022 09:03:45 +0000 +Message-Id: <20220706090412.806101-7-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020443_860462_27205C9D +X-CRM114-Status: GOOD ( 17.85 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +The hardware does not handle 0 size length request, let's add a +fallback. +Furthermore fallback will be used for all unaligned case the hardware +cannot handle. + +Fixes: ce0183cb6464b ("crypto: rockchip - switch to skcipher API") +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/Kconfig | 4 + + drivers/crypto/rockchip/rk3288_crypto.h | 2 + + .../crypto/rockchip/rk3288_crypto_skcipher.c | 97 ++++++++++++++++--- + 3 files changed, 90 insertions(+), 13 deletions(-) + +diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig +index ee99c02c84e8..c293f801806c 100644 +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -784,6 +784,10 @@ config CRYPTO_DEV_IMGTEC_HASH + config CRYPTO_DEV_ROCKCHIP + tristate "Rockchip's Cryptographic Engine driver" + depends on OF && ARCH_ROCKCHIP ++ depends on PM ++ select CRYPTO_ECB ++ select CRYPTO_CBC ++ select CRYPTO_DES + select CRYPTO_AES + select CRYPTO_LIB_DES + select CRYPTO_MD5 +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index c919d9a43a08..8b1e15d8ddc6 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -246,10 +246,12 @@ struct rk_cipher_ctx { + struct rk_crypto_info *dev; + unsigned int keylen; + u8 iv[AES_BLOCK_SIZE]; ++ struct crypto_skcipher *fallback_tfm; + }; + + struct rk_cipher_rctx { + u32 mode; ++ struct skcipher_request fallback_req; // keep at the end + }; + + enum alg_type { +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index bbd0bf52bf07..eac5bba66e25 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -13,6 +13,63 @@ + + #define RK_CRYPTO_DEC BIT(0) + ++static int rk_cipher_need_fallback(struct skcipher_request *req) ++{ ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ unsigned int bs = crypto_skcipher_blocksize(tfm); ++ struct scatterlist *sgs, *sgd; ++ unsigned int stodo, dtodo, len; ++ ++ if (!req->cryptlen) ++ return true; ++ ++ len = req->cryptlen; ++ sgs = req->src; ++ sgd = req->dst; ++ while (sgs && sgd) { ++ if (!IS_ALIGNED(sgs->offset, sizeof(u32))) { ++ return true; ++ } ++ if (!IS_ALIGNED(sgd->offset, sizeof(u32))) { ++ return true; ++ } ++ stodo = min(len, sgs->length); ++ if (stodo % bs) { ++ return true; ++ } ++ dtodo = min(len, sgd->length); ++ if (dtodo % bs) { ++ return true; ++ } ++ if (stodo != dtodo) { ++ return true; ++ } ++ len -= stodo; ++ sgs = sg_next(sgs); ++ sgd = sg_next(sgd); ++ } ++ return false; ++} ++ ++static int rk_cipher_fallback(struct skcipher_request *areq) ++{ ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); ++ struct rk_cipher_ctx *op = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(areq); ++ int err; ++ ++ skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm); ++ skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags, ++ areq->base.complete, areq->base.data); ++ skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst, ++ areq->cryptlen, areq->iv); ++ if (rctx->mode & RK_CRYPTO_DEC) ++ err = crypto_skcipher_decrypt(&rctx->fallback_req); ++ else ++ err = crypto_skcipher_encrypt(&rctx->fallback_req); ++ return err; ++} ++ + static void rk_crypto_complete(struct crypto_async_request *base, int err) + { + if (base->complete) +@@ -22,10 +79,10 @@ static void rk_crypto_complete(struct crypto_async_request *base, int err) + static int rk_handle_req(struct rk_crypto_info *dev, + struct skcipher_request *req) + { +- if (!IS_ALIGNED(req->cryptlen, dev->align_size)) +- return -EINVAL; +- else +- return dev->enqueue(dev, &req->base); ++ if (rk_cipher_need_fallback(req)) ++ return rk_cipher_fallback(req); ++ ++ return dev->enqueue(dev, &req->base); + } + + static int rk_aes_setkey(struct crypto_skcipher *cipher, +@@ -39,7 +96,8 @@ static int rk_aes_setkey(struct crypto_skcipher *cipher, + return -EINVAL; + ctx->keylen = keylen; + memcpy_toio(ctx->dev->reg + RK_CRYPTO_AES_KEY_0, key, keylen); +- return 0; ++ ++ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); + } + + static int rk_des_setkey(struct crypto_skcipher *cipher, +@@ -54,7 +112,8 @@ static int rk_des_setkey(struct crypto_skcipher *cipher, + + ctx->keylen = keylen; + memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, key, keylen); +- return 0; ++ ++ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); + } + + static int rk_tdes_setkey(struct crypto_skcipher *cipher, +@@ -69,7 +128,7 @@ static int rk_tdes_setkey(struct crypto_skcipher *cipher, + + ctx->keylen = keylen; + memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, key, keylen); +- return 0; ++ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); + } + + static int rk_aes_ecb_encrypt(struct skcipher_request *req) +@@ -394,6 +453,7 @@ static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) + { + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ const char *name = crypto_tfm_alg_name(&tfm->base); + struct rk_crypto_tmp *algt; + + algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); +@@ -407,6 +467,16 @@ static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) + if (!ctx->dev->addr_vir) + return -ENOMEM; + ++ ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); ++ if (IS_ERR(ctx->fallback_tfm)) { ++ dev_err(ctx->dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n", ++ name, PTR_ERR(ctx->fallback_tfm)); ++ return PTR_ERR(ctx->fallback_tfm); ++ } ++ ++ tfm->reqsize = sizeof(struct rk_cipher_rctx) + ++ crypto_skcipher_reqsize(ctx->fallback_tfm); ++ + return 0; + } + +@@ -415,6 +485,7 @@ static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm) + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + + free_page((unsigned long)ctx->dev->addr_vir); ++ crypto_free_skcipher(ctx->fallback_tfm); + } + + struct rk_crypto_tmp rk_ecb_aes_alg = { +@@ -423,7 +494,7 @@ struct rk_crypto_tmp rk_ecb_aes_alg = { + .base.cra_name = "ecb(aes)", + .base.cra_driver_name = "ecb-aes-rk", + .base.cra_priority = 300, +- .base.cra_flags = CRYPTO_ALG_ASYNC, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .base.cra_blocksize = AES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct rk_cipher_ctx), + .base.cra_alignmask = 0x0f, +@@ -445,7 +516,7 @@ struct rk_crypto_tmp rk_cbc_aes_alg = { + .base.cra_name = "cbc(aes)", + .base.cra_driver_name = "cbc-aes-rk", + .base.cra_priority = 300, +- .base.cra_flags = CRYPTO_ALG_ASYNC, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .base.cra_blocksize = AES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct rk_cipher_ctx), + .base.cra_alignmask = 0x0f, +@@ -468,7 +539,7 @@ struct rk_crypto_tmp rk_ecb_des_alg = { + .base.cra_name = "ecb(des)", + .base.cra_driver_name = "ecb-des-rk", + .base.cra_priority = 300, +- .base.cra_flags = CRYPTO_ALG_ASYNC, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .base.cra_blocksize = DES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct rk_cipher_ctx), + .base.cra_alignmask = 0x07, +@@ -490,7 +561,7 @@ struct rk_crypto_tmp rk_cbc_des_alg = { + .base.cra_name = "cbc(des)", + .base.cra_driver_name = "cbc-des-rk", + .base.cra_priority = 300, +- .base.cra_flags = CRYPTO_ALG_ASYNC, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .base.cra_blocksize = DES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct rk_cipher_ctx), + .base.cra_alignmask = 0x07, +@@ -513,7 +584,7 @@ struct rk_crypto_tmp rk_ecb_des3_ede_alg = { + .base.cra_name = "ecb(des3_ede)", + .base.cra_driver_name = "ecb-des3-ede-rk", + .base.cra_priority = 300, +- .base.cra_flags = CRYPTO_ALG_ASYNC, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .base.cra_blocksize = DES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct rk_cipher_ctx), + .base.cra_alignmask = 0x07, +@@ -535,7 +606,7 @@ struct rk_crypto_tmp rk_cbc_des3_ede_alg = { + .base.cra_name = "cbc(des3_ede)", + .base.cra_driver_name = "cbc-des3-ede-rk", + .base.cra_priority = 300, +- .base.cra_flags = CRYPTO_ALG_ASYNC, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .base.cra_blocksize = DES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct rk_cipher_ctx), + .base.cra_alignmask = 0x07, + +From patchwork Wed Jul 6 09:03:46 2022 +Content-Type: text/plain; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.39 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:39 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 07/33] crypto: rockchip: add fallback for ahash +Date: Wed, 6 Jul 2022 09:03:46 +0000 +Message-Id: <20220706090412.806101-8-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020446_390573_809BF203 +X-CRM114-Status: GOOD ( 12.08 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Adds a fallback for all case hardware cannot handle. + +Fixes: ce0183cb6464b ("crypto: rockchip - switch to skcipher API") +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index 49017d1fb510..16009bb0bf16 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -16,6 +16,40 @@ + * so we put the fixed hash out when met zero message. + */ + ++static bool rk_ahash_need_fallback(struct ahash_request *req) ++{ ++ struct scatterlist *sg; ++ ++ sg = req->src; ++ while (sg) { ++ if (!IS_ALIGNED(sg->offset, sizeof(u32))) { ++ return true; ++ } ++ if (sg->length % 4) { ++ return true; ++ } ++ sg = sg_next(sg); ++ } ++ return false; ++} ++ ++static int rk_ahash_digest_fb(struct ahash_request *areq) ++{ ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct rk_ahash_ctx *tfmctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, tfmctx->fallback_tfm); ++ rctx->fallback_req.base.flags = areq->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ rctx->fallback_req.nbytes = areq->nbytes; ++ rctx->fallback_req.src = areq->src; ++ rctx->fallback_req.result = areq->result; ++ ++ return crypto_ahash_digest(&rctx->fallback_req); ++} ++ + static int zero_message_process(struct ahash_request *req) + { + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); +@@ -167,6 +201,9 @@ static int rk_ahash_digest(struct ahash_request *req) + struct rk_ahash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); + struct rk_crypto_info *dev = tctx->dev; + ++ if (rk_ahash_need_fallback(req)) ++ return rk_ahash_digest_fb(req); ++ + if (!req->nbytes) + return zero_message_process(req); + else +@@ -309,6 +346,7 @@ static void rk_cra_hash_exit(struct crypto_tfm *tfm) + struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm); + + free_page((unsigned long)tctx->dev->addr_vir); ++ crypto_free_ahash(tctx->fallback_tfm); + } + + struct rk_crypto_tmp rk_ahash_sha1 = { + +From patchwork Wed Jul 6 09:03:47 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907940 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id AE32EC43334 + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.40 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:40 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 08/33] crypto: rockchip: better handle cipher key +Date: Wed, 6 Jul 2022 09:03:47 +0000 +Message-Id: <20220706090412.806101-9-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020445_484808_FB87EEB6 +X-CRM114-Status: GOOD ( 13.23 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +The key should not be set in hardware too much in advance, this will +fail it 2 TFM with different keys generate alternative requests. +The key should be stored and used just before doing cipher operations. + +Fixes: ce0183cb6464b ("crypto: rockchip - switch to skcipher API") +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.h | 1 + + drivers/crypto/rockchip/rk3288_crypto_skcipher.c | 10 +++++++--- + 2 files changed, 8 insertions(+), 3 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index 8b1e15d8ddc6..540b81a14b9b 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -245,6 +245,7 @@ struct rk_ahash_rctx { + struct rk_cipher_ctx { + struct rk_crypto_info *dev; + unsigned int keylen; ++ u8 key[AES_MAX_KEY_SIZE]; + u8 iv[AES_BLOCK_SIZE]; + struct crypto_skcipher *fallback_tfm; + }; +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index eac5bba66e25..1ef94f8db2c5 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -95,7 +95,7 @@ static int rk_aes_setkey(struct crypto_skcipher *cipher, + keylen != AES_KEYSIZE_256) + return -EINVAL; + ctx->keylen = keylen; +- memcpy_toio(ctx->dev->reg + RK_CRYPTO_AES_KEY_0, key, keylen); ++ memcpy(ctx->key, key, keylen); + + return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); + } +@@ -111,7 +111,7 @@ static int rk_des_setkey(struct crypto_skcipher *cipher, + return err; + + ctx->keylen = keylen; +- memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, key, keylen); ++ memcpy(ctx->key, key, keylen); + + return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); + } +@@ -127,7 +127,8 @@ static int rk_tdes_setkey(struct crypto_skcipher *cipher, + return err; + + ctx->keylen = keylen; +- memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, key, keylen); ++ memcpy(ctx->key, key, keylen); ++ + return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); + } + +@@ -283,6 +284,7 @@ static void rk_ablk_hw_init(struct rk_crypto_info *dev) + RK_CRYPTO_TDES_BYTESWAP_IV; + CRYPTO_WRITE(dev, RK_CRYPTO_TDES_CTRL, rctx->mode); + memcpy_toio(dev->reg + RK_CRYPTO_TDES_IV_0, req->iv, ivsize); ++ memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, ctx->key, ctx->keylen); + conf_reg = RK_CRYPTO_DESSEL; + } else { + rctx->mode |= RK_CRYPTO_AES_FIFO_MODE | +@@ -295,6 +297,7 @@ static void rk_ablk_hw_init(struct rk_crypto_info *dev) + rctx->mode |= RK_CRYPTO_AES_256BIT_key; + CRYPTO_WRITE(dev, RK_CRYPTO_AES_CTRL, rctx->mode); + memcpy_toio(dev->reg + RK_CRYPTO_AES_IV_0, req->iv, ivsize); ++ memcpy_toio(ctx->dev->reg + RK_CRYPTO_AES_KEY_0, ctx->key, ctx->keylen); + } + conf_reg |= RK_CRYPTO_BYTESWAP_BTFIFO | + RK_CRYPTO_BYTESWAP_BRFIFO; +@@ -484,6 +487,7 @@ static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm) + { + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.41 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:41 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 09/33] crypto: rockchip: remove non-aligned handling +Date: Wed, 6 Jul 2022 09:03:48 +0000 +Message-Id: <20220706090412.806101-10-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100445_893037_68F1FA19 +X-CRM114-Status: GOOD ( 17.50 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Now driver have fallback for un-aligned cases, remove all code handling +those cases. + +Fixes: ce0183cb6464b ("crypto: rockchip - switch to skcipher API") +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 69 +++++-------------- + drivers/crypto/rockchip/rk3288_crypto.h | 4 -- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 22 ++---- + .../crypto/rockchip/rk3288_crypto_skcipher.c | 39 +++-------- + 4 files changed, 31 insertions(+), 103 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index 4cff49b82983..b3db096e2ec2 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -88,63 +88,26 @@ static int rk_load_data(struct rk_crypto_info *dev, + { + unsigned int count; + +- dev->aligned = dev->aligned ? +- check_alignment(sg_src, sg_dst, dev->align_size) : +- dev->aligned; +- if (dev->aligned) { +- count = min(dev->left_bytes, sg_src->length); +- dev->left_bytes -= count; +- +- if (!dma_map_sg(dev->dev, sg_src, 1, DMA_TO_DEVICE)) { +- dev_err(dev->dev, "[%s:%d] dma_map_sg(src) error\n", ++ count = min(dev->left_bytes, sg_src->length); ++ dev->left_bytes -= count; ++ ++ if (!dma_map_sg(dev->dev, sg_src, 1, DMA_TO_DEVICE)) { ++ dev_err(dev->dev, "[%s:%d] dma_map_sg(src) error\n", + __func__, __LINE__); +- return -EINVAL; +- } +- dev->addr_in = sg_dma_address(sg_src); ++ return -EINVAL; ++ } ++ dev->addr_in = sg_dma_address(sg_src); + +- if (sg_dst) { +- if (!dma_map_sg(dev->dev, sg_dst, 1, DMA_FROM_DEVICE)) { +- dev_err(dev->dev, ++ if (sg_dst) { ++ if (!dma_map_sg(dev->dev, sg_dst, 1, DMA_FROM_DEVICE)) { ++ dev_err(dev->dev, + "[%s:%d] dma_map_sg(dst) error\n", + __func__, __LINE__); +- dma_unmap_sg(dev->dev, sg_src, 1, +- DMA_TO_DEVICE); +- return -EINVAL; +- } +- dev->addr_out = sg_dma_address(sg_dst); +- } +- } else { +- count = (dev->left_bytes > PAGE_SIZE) ? +- PAGE_SIZE : dev->left_bytes; +- +- if (!sg_pcopy_to_buffer(dev->first, dev->src_nents, +- dev->addr_vir, count, +- dev->total - dev->left_bytes)) { +- dev_err(dev->dev, "[%s:%d] pcopy err\n", +- __func__, __LINE__); ++ dma_unmap_sg(dev->dev, sg_src, 1, ++ DMA_TO_DEVICE); + return -EINVAL; + } +- dev->left_bytes -= count; +- sg_init_one(&dev->sg_tmp, dev->addr_vir, count); +- if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1, DMA_TO_DEVICE)) { +- dev_err(dev->dev, "[%s:%d] dma_map_sg(sg_tmp) error\n", +- __func__, __LINE__); +- return -ENOMEM; +- } +- dev->addr_in = sg_dma_address(&dev->sg_tmp); +- +- if (sg_dst) { +- if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1, +- DMA_FROM_DEVICE)) { +- dev_err(dev->dev, +- "[%s:%d] dma_map_sg(sg_tmp) error\n", +- __func__, __LINE__); +- dma_unmap_sg(dev->dev, &dev->sg_tmp, 1, +- DMA_TO_DEVICE); +- return -ENOMEM; +- } +- dev->addr_out = sg_dma_address(&dev->sg_tmp); +- } ++ dev->addr_out = sg_dma_address(sg_dst); + } + dev->count = count; + return 0; +@@ -154,11 +117,11 @@ static void rk_unload_data(struct rk_crypto_info *dev) + { + struct scatterlist *sg_in, *sg_out; + +- sg_in = dev->aligned ? dev->sg_src : &dev->sg_tmp; ++ sg_in = dev->sg_src; + dma_unmap_sg(dev->dev, sg_in, 1, DMA_TO_DEVICE); + + if (dev->sg_dst) { +- sg_out = dev->aligned ? dev->sg_dst : &dev->sg_tmp; ++ sg_out = dev->sg_dst; + dma_unmap_sg(dev->dev, sg_out, 1, DMA_FROM_DEVICE); + } + } +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index 540b81a14b9b..a7de5738f6dc 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -204,12 +204,8 @@ struct rk_crypto_info { + /* the public variable */ + struct scatterlist *sg_src; + struct scatterlist *sg_dst; +- struct scatterlist sg_tmp; + struct scatterlist *first; + unsigned int left_bytes; +- void *addr_vir; +- int aligned; +- int align_size; + size_t src_nents; + size_t dst_nents; + unsigned int total; +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index 16009bb0bf16..c762e462eb57 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -236,8 +236,6 @@ static int rk_ahash_start(struct rk_crypto_info *dev) + + dev->total = req->nbytes; + dev->left_bytes = req->nbytes; +- dev->aligned = 0; +- dev->align_size = 4; + dev->sg_dst = NULL; + dev->sg_src = req->src; + dev->first = req->src; +@@ -272,15 +270,13 @@ static int rk_ahash_crypto_rx(struct rk_crypto_info *dev) + + dev->unload_data(dev); + if (dev->left_bytes) { +- if (dev->aligned) { +- if (sg_is_last(dev->sg_src)) { +- dev_warn(dev->dev, "[%s:%d], Lack of data\n", +- __func__, __LINE__); +- err = -ENOMEM; +- goto out_rx; +- } +- dev->sg_src = sg_next(dev->sg_src); ++ if (sg_is_last(dev->sg_src)) { ++ dev_warn(dev->dev, "[%s:%d], Lack of data\n", ++ __func__, __LINE__); ++ err = -ENOMEM; ++ goto out_rx; + } ++ dev->sg_src = sg_next(dev->sg_src); + err = rk_ahash_set_data_start(dev); + } else { + /* +@@ -318,11 +314,6 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) + algt = container_of(alg, struct rk_crypto_tmp, alg.hash); + + tctx->dev = algt->dev; +- tctx->dev->addr_vir = (void *)__get_free_page(GFP_KERNEL); +- if (!tctx->dev->addr_vir) { +- dev_err(tctx->dev->dev, "failed to kmalloc for addr_vir\n"); +- return -ENOMEM; +- } + tctx->dev->start = rk_ahash_start; + tctx->dev->update = rk_ahash_crypto_rx; + tctx->dev->complete = rk_ahash_crypto_complete; +@@ -345,7 +336,6 @@ static void rk_cra_hash_exit(struct crypto_tfm *tfm) + { + struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm); + +- free_page((unsigned long)tctx->dev->addr_vir); + crypto_free_ahash(tctx->fallback_tfm); + } + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 1ef94f8db2c5..d067b7f09165 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -356,7 +356,6 @@ static int rk_ablk_start(struct rk_crypto_info *dev) + dev->src_nents = sg_nents(req->src); + dev->sg_dst = req->dst; + dev->dst_nents = sg_nents(req->dst); +- dev->aligned = 1; + + spin_lock_irqsave(&dev->lock, flags); + rk_ablk_hw_init(dev); +@@ -376,13 +375,9 @@ static void rk_iv_copyback(struct rk_crypto_info *dev) + + /* Update the IV buffer to contain the next IV for encryption mode. */ + if (!(rctx->mode & RK_CRYPTO_DEC)) { +- if (dev->aligned) { +- memcpy(req->iv, sg_virt(dev->sg_dst) + +- dev->sg_dst->length - ivsize, ivsize); +- } else { +- memcpy(req->iv, dev->addr_vir + +- dev->count - ivsize, ivsize); +- } ++ memcpy(req->iv, ++ sg_virt(dev->sg_dst) + dev->sg_dst->length - ivsize, ++ ivsize); + } + } + +@@ -420,27 +415,16 @@ static int rk_ablk_rx(struct rk_crypto_info *dev) + skcipher_request_cast(dev->async_req); + + dev->unload_data(dev); +- if (!dev->aligned) { +- if (!sg_pcopy_from_buffer(req->dst, dev->dst_nents, +- dev->addr_vir, dev->count, +- dev->total - dev->left_bytes - +- dev->count)) { +- err = -EINVAL; +- goto out_rx; +- } +- } + if (dev->left_bytes) { + rk_update_iv(dev); +- if (dev->aligned) { +- if (sg_is_last(dev->sg_src)) { +- dev_err(dev->dev, "[%s:%d] Lack of data\n", ++ if (sg_is_last(dev->sg_src)) { ++ dev_err(dev->dev, "[%s:%d] Lack of data\n", + __func__, __LINE__); +- err = -ENOMEM; +- goto out_rx; +- } +- dev->sg_src = sg_next(dev->sg_src); +- dev->sg_dst = sg_next(dev->sg_dst); ++ err = -ENOMEM; ++ goto out_rx; + } ++ dev->sg_src = sg_next(dev->sg_src); ++ dev->sg_dst = sg_next(dev->sg_dst); + err = rk_set_data_start(dev); + } else { + rk_iv_copyback(dev); +@@ -462,13 +446,9 @@ static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) + algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); + + ctx->dev = algt->dev; +- ctx->dev->align_size = crypto_tfm_alg_alignmask(crypto_skcipher_tfm(tfm)) + 1; + ctx->dev->start = rk_ablk_start; + ctx->dev->update = rk_ablk_rx; + ctx->dev->complete = rk_crypto_complete; +- ctx->dev->addr_vir = (char *)__get_free_page(GFP_KERNEL); +- if (!ctx->dev->addr_vir) +- return -ENOMEM; + + ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->fallback_tfm)) { +@@ -488,7 +468,6 @@ static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm) + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + + memzero_explicit(ctx->key, ctx->keylen); +- free_page((unsigned long)ctx->dev->addr_vir); + crypto_free_skcipher(ctx->fallback_tfm); + } + + +From patchwork Wed Jul 6 09:03:49 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907850 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D039C433EF + for ; + Wed, 6 Jul 2022 09:58:22 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.42 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:42 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 10/33] crypto: rockchip: rework by using crypto_engine +Date: Wed, 6 Jul 2022 09:03:49 +0000 +Message-Id: <20220706090412.806101-11-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100446_537594_2DC5714C +X-CRM114-Status: GOOD ( 22.68 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Instead of doing manual queue management, let's use the crypto/engine +for that. +In the same time, rework the requests handling to be easier to +understand (and fix all bugs related to them). + +Fixes: ce0183cb6464b ("crypto: rockchip - switch to skcipher API") +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/Kconfig | 1 + + drivers/crypto/rockchip/rk3288_crypto.c | 152 +---------- + drivers/crypto/rockchip/rk3288_crypto.h | 39 +-- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 144 +++++----- + .../crypto/rockchip/rk3288_crypto_skcipher.c | 250 +++++++++--------- + 5 files changed, 221 insertions(+), 365 deletions(-) + +diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig +index c293f801806c..df4f0a2de098 100644 +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -789,6 +789,7 @@ config CRYPTO_DEV_ROCKCHIP + select CRYPTO_CBC + select CRYPTO_DES + select CRYPTO_AES ++ select CRYPTO_ENGINE + select CRYPTO_LIB_DES + select CRYPTO_MD5 + select CRYPTO_SHA1 +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index b3db096e2ec2..1afb65eee6c9 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -65,149 +65,24 @@ static void rk_crypto_disable_clk(struct rk_crypto_info *dev) + clk_disable_unprepare(dev->sclk); + } + +-static int check_alignment(struct scatterlist *sg_src, +- struct scatterlist *sg_dst, +- int align_mask) +-{ +- int in, out, align; +- +- in = IS_ALIGNED((uint32_t)sg_src->offset, 4) && +- IS_ALIGNED((uint32_t)sg_src->length, align_mask); +- if (!sg_dst) +- return in; +- out = IS_ALIGNED((uint32_t)sg_dst->offset, 4) && +- IS_ALIGNED((uint32_t)sg_dst->length, align_mask); +- align = in && out; +- +- return (align && (sg_src->length == sg_dst->length)); +-} +- +-static int rk_load_data(struct rk_crypto_info *dev, +- struct scatterlist *sg_src, +- struct scatterlist *sg_dst) +-{ +- unsigned int count; +- +- count = min(dev->left_bytes, sg_src->length); +- dev->left_bytes -= count; +- +- if (!dma_map_sg(dev->dev, sg_src, 1, DMA_TO_DEVICE)) { +- dev_err(dev->dev, "[%s:%d] dma_map_sg(src) error\n", +- __func__, __LINE__); +- return -EINVAL; +- } +- dev->addr_in = sg_dma_address(sg_src); +- +- if (sg_dst) { +- if (!dma_map_sg(dev->dev, sg_dst, 1, DMA_FROM_DEVICE)) { +- dev_err(dev->dev, +- "[%s:%d] dma_map_sg(dst) error\n", +- __func__, __LINE__); +- dma_unmap_sg(dev->dev, sg_src, 1, +- DMA_TO_DEVICE); +- return -EINVAL; +- } +- dev->addr_out = sg_dma_address(sg_dst); +- } +- dev->count = count; +- return 0; +-} +- +-static void rk_unload_data(struct rk_crypto_info *dev) +-{ +- struct scatterlist *sg_in, *sg_out; +- +- sg_in = dev->sg_src; +- dma_unmap_sg(dev->dev, sg_in, 1, DMA_TO_DEVICE); +- +- if (dev->sg_dst) { +- sg_out = dev->sg_dst; +- dma_unmap_sg(dev->dev, sg_out, 1, DMA_FROM_DEVICE); +- } +-} +- + static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id) + { + struct rk_crypto_info *dev = platform_get_drvdata(dev_id); + u32 interrupt_status; + +- spin_lock(&dev->lock); + interrupt_status = CRYPTO_READ(dev, RK_CRYPTO_INTSTS); + CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, interrupt_status); + ++ dev->status = 1; + if (interrupt_status & 0x0a) { + dev_warn(dev->dev, "DMA Error\n"); +- dev->err = -EFAULT; ++ dev->status = 0; + } +- tasklet_schedule(&dev->done_task); ++ complete(&dev->complete); + +- spin_unlock(&dev->lock); + return IRQ_HANDLED; + } + +-static int rk_crypto_enqueue(struct rk_crypto_info *dev, +- struct crypto_async_request *async_req) +-{ +- unsigned long flags; +- int ret; +- +- spin_lock_irqsave(&dev->lock, flags); +- ret = crypto_enqueue_request(&dev->queue, async_req); +- if (dev->busy) { +- spin_unlock_irqrestore(&dev->lock, flags); +- return ret; +- } +- dev->busy = true; +- spin_unlock_irqrestore(&dev->lock, flags); +- tasklet_schedule(&dev->queue_task); +- +- return ret; +-} +- +-static void rk_crypto_queue_task_cb(unsigned long data) +-{ +- struct rk_crypto_info *dev = (struct rk_crypto_info *)data; +- struct crypto_async_request *async_req, *backlog; +- unsigned long flags; +- int err = 0; +- +- dev->err = 0; +- spin_lock_irqsave(&dev->lock, flags); +- backlog = crypto_get_backlog(&dev->queue); +- async_req = crypto_dequeue_request(&dev->queue); +- +- if (!async_req) { +- dev->busy = false; +- spin_unlock_irqrestore(&dev->lock, flags); +- return; +- } +- spin_unlock_irqrestore(&dev->lock, flags); +- +- if (backlog) { +- backlog->complete(backlog, -EINPROGRESS); +- backlog = NULL; +- } +- +- dev->async_req = async_req; +- err = dev->start(dev); +- if (err) +- dev->complete(dev->async_req, err); +-} +- +-static void rk_crypto_done_task_cb(unsigned long data) +-{ +- struct rk_crypto_info *dev = (struct rk_crypto_info *)data; +- +- if (dev->err) { +- dev->complete(dev->async_req, dev->err); +- return; +- } +- +- dev->err = dev->update(dev); +- if (dev->err) +- dev->complete(dev->async_req, dev->err); +-} +- + static struct rk_crypto_tmp *rk_cipher_algs[] = { + &rk_ecb_aes_alg, + &rk_cbc_aes_alg, +@@ -300,8 +175,6 @@ static int rk_crypto_probe(struct platform_device *pdev) + if (err) + goto err_crypto; + +- spin_lock_init(&crypto_info->lock); +- + crypto_info->reg = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(crypto_info->reg)) { + err = PTR_ERR(crypto_info->reg); +@@ -351,17 +224,11 @@ static int rk_crypto_probe(struct platform_device *pdev) + crypto_info->dev = &pdev->dev; + platform_set_drvdata(pdev, crypto_info); + +- tasklet_init(&crypto_info->queue_task, +- rk_crypto_queue_task_cb, (unsigned long)crypto_info); +- tasklet_init(&crypto_info->done_task, +- rk_crypto_done_task_cb, (unsigned long)crypto_info); +- crypto_init_queue(&crypto_info->queue, 50); ++ crypto_info->engine = crypto_engine_alloc_init(&pdev->dev, true); ++ crypto_engine_start(crypto_info->engine); ++ init_completion(&crypto_info->complete); + + rk_crypto_enable_clk(crypto_info); +- crypto_info->load_data = rk_load_data; +- crypto_info->unload_data = rk_unload_data; +- crypto_info->enqueue = rk_crypto_enqueue; +- crypto_info->busy = false; + + err = rk_crypto_register(crypto_info); + if (err) { +@@ -373,9 +240,9 @@ static int rk_crypto_probe(struct platform_device *pdev) + return 0; + + err_register_alg: +- tasklet_kill(&crypto_info->queue_task); +- tasklet_kill(&crypto_info->done_task); ++ crypto_engine_exit(crypto_info->engine); + err_crypto: ++ dev_err(dev, "Crypto Accelerator not successfully registered\n"); + return err; + } + +@@ -385,8 +252,7 @@ static int rk_crypto_remove(struct platform_device *pdev) + + rk_crypto_unregister(); + rk_crypto_disable_clk(crypto_tmp); +- tasklet_kill(&crypto_tmp->done_task); +- tasklet_kill(&crypto_tmp->queue_task); ++ crypto_engine_exit(crypto_tmp->engine); + return 0; + } + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index a7de5738f6dc..65ed645e0168 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -5,9 +5,11 @@ + #include + #include + #include ++#include + #include + #include + #include ++#include + #include + #include + +@@ -193,39 +195,15 @@ struct rk_crypto_info { + struct reset_control *rst; + void __iomem *reg; + int irq; +- struct crypto_queue queue; +- struct tasklet_struct queue_task; +- struct tasklet_struct done_task; +- struct crypto_async_request *async_req; +- int err; +- /* device lock */ +- spinlock_t lock; +- +- /* the public variable */ +- struct scatterlist *sg_src; +- struct scatterlist *sg_dst; +- struct scatterlist *first; +- unsigned int left_bytes; +- size_t src_nents; +- size_t dst_nents; +- unsigned int total; +- unsigned int count; +- dma_addr_t addr_in; +- dma_addr_t addr_out; +- bool busy; +- int (*start)(struct rk_crypto_info *dev); +- int (*update)(struct rk_crypto_info *dev); +- void (*complete)(struct crypto_async_request *base, int err); +- int (*load_data)(struct rk_crypto_info *dev, +- struct scatterlist *sg_src, +- struct scatterlist *sg_dst); +- void (*unload_data)(struct rk_crypto_info *dev); +- int (*enqueue)(struct rk_crypto_info *dev, +- struct crypto_async_request *async_req); ++ ++ struct crypto_engine *engine; ++ struct completion complete; ++ int status; + }; + + /* the private variable of hash */ + struct rk_ahash_ctx { ++ struct crypto_engine_ctx enginectx; + struct rk_crypto_info *dev; + /* for fallback */ + struct crypto_ahash *fallback_tfm; +@@ -235,10 +213,12 @@ struct rk_ahash_ctx { + struct rk_ahash_rctx { + struct ahash_request fallback_req; + u32 mode; ++ int nrsg; + }; + + /* the private variable of cipher */ + struct rk_cipher_ctx { ++ struct crypto_engine_ctx enginectx; + struct rk_crypto_info *dev; + unsigned int keylen; + u8 key[AES_MAX_KEY_SIZE]; +@@ -247,6 +227,7 @@ struct rk_cipher_ctx { + }; + + struct rk_cipher_rctx { ++ u8 backup_iv[AES_BLOCK_SIZE]; + u32 mode; + struct skcipher_request fallback_req; // keep at the end + }; +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index c762e462eb57..edd40e16a3f0 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -9,6 +9,7 @@ + * Some ideas are from marvell/cesa.c and s5p-sss.c driver. + */ + #include ++#include + #include "rk3288_crypto.h" + + /* +@@ -72,16 +73,12 @@ static int zero_message_process(struct ahash_request *req) + return 0; + } + +-static void rk_ahash_crypto_complete(struct crypto_async_request *base, int err) ++static void rk_ahash_reg_init(struct ahash_request *req) + { +- if (base->complete) +- base->complete(base, err); +-} +- +-static void rk_ahash_reg_init(struct rk_crypto_info *dev) +-{ +- struct ahash_request *req = ahash_request_cast(dev->async_req); + struct rk_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); ++ struct rk_crypto_info *dev = tctx->dev; + int reg_status; + + reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL) | +@@ -108,7 +105,7 @@ static void rk_ahash_reg_init(struct rk_crypto_info *dev) + RK_CRYPTO_BYTESWAP_BRFIFO | + RK_CRYPTO_BYTESWAP_BTFIFO); + +- CRYPTO_WRITE(dev, RK_CRYPTO_HASH_MSG_LEN, dev->total); ++ CRYPTO_WRITE(dev, RK_CRYPTO_HASH_MSG_LEN, req->nbytes); + } + + static int rk_ahash_init(struct ahash_request *req) +@@ -206,44 +203,59 @@ static int rk_ahash_digest(struct ahash_request *req) + + if (!req->nbytes) + return zero_message_process(req); +- else +- return dev->enqueue(dev, &req->base); ++ ++ return crypto_transfer_hash_request_to_engine(dev->engine, req); + } + +-static void crypto_ahash_dma_start(struct rk_crypto_info *dev) ++static void crypto_ahash_dma_start(struct rk_crypto_info *dev, struct scatterlist *sg) + { +- CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAS, dev->addr_in); +- CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAL, (dev->count + 3) / 4); ++ CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAS, sg_dma_address(sg)); ++ CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAL, sg_dma_len(sg) / 4); + CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, RK_CRYPTO_HASH_START | + (RK_CRYPTO_HASH_START << 16)); + } + +-static int rk_ahash_set_data_start(struct rk_crypto_info *dev) ++static int rk_hash_prepare(struct crypto_engine *engine, void *breq) ++{ ++ struct ahash_request *areq = container_of(breq, struct ahash_request, base); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); ++ int ret; ++ ++ ret = dma_map_sg(tctx->dev->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); ++ if (ret <= 0) ++ return -EINVAL; ++ ++ rctx->nrsg = ret; ++ ++ return 0; ++} ++ ++static int rk_hash_unprepare(struct crypto_engine *engine, void *breq) + { +- int err; ++ struct ahash_request *areq = container_of(breq, struct ahash_request, base); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); + +- err = dev->load_data(dev, dev->sg_src, NULL); +- if (!err) +- crypto_ahash_dma_start(dev); +- return err; ++ dma_unmap_sg(tctx->dev->dev, areq->src, rctx->nrsg, DMA_TO_DEVICE); ++ return 0; + } + +-static int rk_ahash_start(struct rk_crypto_info *dev) ++static int rk_hash_run(struct crypto_engine *engine, void *breq) + { +- struct ahash_request *req = ahash_request_cast(dev->async_req); +- struct crypto_ahash *tfm; +- struct rk_ahash_rctx *rctx; +- +- dev->total = req->nbytes; +- dev->left_bytes = req->nbytes; +- dev->sg_dst = NULL; +- dev->sg_src = req->src; +- dev->first = req->src; +- dev->src_nents = sg_nents(req->src); +- rctx = ahash_request_ctx(req); ++ struct ahash_request *areq = container_of(breq, struct ahash_request, base); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); ++ struct scatterlist *sg = areq->src; ++ int err = 0; ++ int i; ++ u32 v; ++ + rctx->mode = 0; + +- tfm = crypto_ahash_reqtfm(req); + switch (crypto_ahash_digestsize(tfm)) { + case SHA1_DIGEST_SIZE: + rctx->mode = RK_CRYPTO_HASH_SHA1; +@@ -255,30 +267,26 @@ static int rk_ahash_start(struct rk_crypto_info *dev) + rctx->mode = RK_CRYPTO_HASH_MD5; + break; + default: +- return -EINVAL; ++ err = -EINVAL; ++ goto theend; + } + +- rk_ahash_reg_init(dev); +- return rk_ahash_set_data_start(dev); +-} ++ rk_ahash_reg_init(areq); + +-static int rk_ahash_crypto_rx(struct rk_crypto_info *dev) +-{ +- int err = 0; +- struct ahash_request *req = ahash_request_cast(dev->async_req); +- struct crypto_ahash *tfm; +- +- dev->unload_data(dev); +- if (dev->left_bytes) { +- if (sg_is_last(dev->sg_src)) { +- dev_warn(dev->dev, "[%s:%d], Lack of data\n", +- __func__, __LINE__); +- err = -ENOMEM; +- goto out_rx; ++ while (sg) { ++ reinit_completion(&tctx->dev->complete); ++ tctx->dev->status = 0; ++ crypto_ahash_dma_start(tctx->dev, sg); ++ wait_for_completion_interruptible_timeout(&tctx->dev->complete, ++ msecs_to_jiffies(2000)); ++ if (!tctx->dev->status) { ++ dev_err(tctx->dev->dev, "DMA timeout\n"); ++ err = -EFAULT; ++ goto theend; + } +- dev->sg_src = sg_next(dev->sg_src); +- err = rk_ahash_set_data_start(dev); +- } else { ++ sg = sg_next(sg); ++ } ++ + /* + * it will take some time to process date after last dma + * transmission. +@@ -289,18 +297,20 @@ static int rk_ahash_crypto_rx(struct rk_crypto_info *dev) + * efficiency, and make it response quickly when dma + * complete. + */ +- while (!CRYPTO_READ(dev, RK_CRYPTO_HASH_STS)) +- udelay(10); +- +- tfm = crypto_ahash_reqtfm(req); +- memcpy_fromio(req->result, dev->reg + RK_CRYPTO_HASH_DOUT_0, +- crypto_ahash_digestsize(tfm)); +- dev->complete(dev->async_req, 0); +- tasklet_schedule(&dev->queue_task); ++ while (!CRYPTO_READ(tctx->dev, RK_CRYPTO_HASH_STS)) ++ udelay(10); ++ ++ for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) { ++ v = readl(tctx->dev->reg + RK_CRYPTO_HASH_DOUT_0 + i * 4); ++ put_unaligned_le32(v, areq->result + i * 4); + } + +-out_rx: +- return err; ++theend: ++ local_bh_disable(); ++ crypto_finalize_hash_request(engine, breq, err); ++ local_bh_enable(); ++ ++ return 0; + } + + static int rk_cra_hash_init(struct crypto_tfm *tfm) +@@ -314,9 +324,6 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) + algt = container_of(alg, struct rk_crypto_tmp, alg.hash); + + tctx->dev = algt->dev; +- tctx->dev->start = rk_ahash_start; +- tctx->dev->update = rk_ahash_crypto_rx; +- tctx->dev->complete = rk_ahash_crypto_complete; + + /* for fallback */ + tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0, +@@ -325,10 +332,15 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) + dev_err(tctx->dev->dev, "Could not load fallback driver.\n"); + return PTR_ERR(tctx->fallback_tfm); + } ++ + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), + sizeof(struct rk_ahash_rctx) + + crypto_ahash_reqsize(tctx->fallback_tfm)); + ++ tctx->enginectx.op.do_one_request = rk_hash_run; ++ tctx->enginectx.op.prepare_request = rk_hash_prepare; ++ tctx->enginectx.op.unprepare_request = rk_hash_unprepare; ++ + return 0; + } + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index d067b7f09165..67a7e05d5ae3 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -9,6 +9,7 @@ + * Some ideas are from marvell-cesa.c and s5p-sss.c driver. + */ + #include ++#include + #include "rk3288_crypto.h" + + #define RK_CRYPTO_DEC BIT(0) +@@ -70,19 +71,15 @@ static int rk_cipher_fallback(struct skcipher_request *areq) + return err; + } + +-static void rk_crypto_complete(struct crypto_async_request *base, int err) +-{ +- if (base->complete) +- base->complete(base, err); +-} +- + static int rk_handle_req(struct rk_crypto_info *dev, + struct skcipher_request *req) + { ++ struct crypto_engine *engine = dev->engine; ++ + if (rk_cipher_need_fallback(req)) + return rk_cipher_fallback(req); + +- return dev->enqueue(dev, &req->base); ++ return crypto_transfer_skcipher_request_to_engine(engine, req); + } + + static int rk_aes_setkey(struct crypto_skcipher *cipher, +@@ -265,25 +262,21 @@ static int rk_des3_ede_cbc_decrypt(struct skcipher_request *req) + return rk_handle_req(dev, req); + } + +-static void rk_ablk_hw_init(struct rk_crypto_info *dev) ++static void rk_ablk_hw_init(struct rk_crypto_info *dev, struct skcipher_request *req) + { +- struct skcipher_request *req = +- skcipher_request_cast(dev->async_req); + struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req); + struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(cipher); +- u32 ivsize, block, conf_reg = 0; ++ u32 block, conf_reg = 0; + + block = crypto_tfm_alg_blocksize(tfm); +- ivsize = crypto_skcipher_ivsize(cipher); + + if (block == DES_BLOCK_SIZE) { + rctx->mode |= RK_CRYPTO_TDES_FIFO_MODE | + RK_CRYPTO_TDES_BYTESWAP_KEY | + RK_CRYPTO_TDES_BYTESWAP_IV; + CRYPTO_WRITE(dev, RK_CRYPTO_TDES_CTRL, rctx->mode); +- memcpy_toio(dev->reg + RK_CRYPTO_TDES_IV_0, req->iv, ivsize); + memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, ctx->key, ctx->keylen); + conf_reg = RK_CRYPTO_DESSEL; + } else { +@@ -296,7 +289,6 @@ static void rk_ablk_hw_init(struct rk_crypto_info *dev) + else if (ctx->keylen == AES_KEYSIZE_256) + rctx->mode |= RK_CRYPTO_AES_256BIT_key; + CRYPTO_WRITE(dev, RK_CRYPTO_AES_CTRL, rctx->mode); +- memcpy_toio(dev->reg + RK_CRYPTO_AES_IV_0, req->iv, ivsize); + memcpy_toio(ctx->dev->reg + RK_CRYPTO_AES_KEY_0, ctx->key, ctx->keylen); + } + conf_reg |= RK_CRYPTO_BYTESWAP_BTFIFO | +@@ -306,133 +298,138 @@ static void rk_ablk_hw_init(struct rk_crypto_info *dev) + RK_CRYPTO_BCDMA_ERR_ENA | RK_CRYPTO_BCDMA_DONE_ENA); + } + +-static void crypto_dma_start(struct rk_crypto_info *dev) ++static void crypto_dma_start(struct rk_crypto_info *dev, ++ struct scatterlist *sgs, ++ struct scatterlist *sgd, unsigned int todo) + { +- CRYPTO_WRITE(dev, RK_CRYPTO_BRDMAS, dev->addr_in); +- CRYPTO_WRITE(dev, RK_CRYPTO_BRDMAL, dev->count / 4); +- CRYPTO_WRITE(dev, RK_CRYPTO_BTDMAS, dev->addr_out); ++ CRYPTO_WRITE(dev, RK_CRYPTO_BRDMAS, sg_dma_address(sgs)); ++ CRYPTO_WRITE(dev, RK_CRYPTO_BRDMAL, todo); ++ CRYPTO_WRITE(dev, RK_CRYPTO_BTDMAS, sg_dma_address(sgd)); + CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, RK_CRYPTO_BLOCK_START | + _SBF(RK_CRYPTO_BLOCK_START, 16)); + } + +-static int rk_set_data_start(struct rk_crypto_info *dev) ++static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + { +- int err; +- struct skcipher_request *req = +- skcipher_request_cast(dev->async_req); +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); ++ struct skcipher_request *areq = container_of(async_req, struct skcipher_request, base); ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); +- u32 ivsize = crypto_skcipher_ivsize(tfm); +- u8 *src_last_blk = page_address(sg_page(dev->sg_src)) + +- dev->sg_src->offset + dev->sg_src->length - ivsize; +- +- /* Store the iv that need to be updated in chain mode. +- * And update the IV buffer to contain the next IV for decryption mode. +- */ +- if (rctx->mode & RK_CRYPTO_DEC) { +- memcpy(ctx->iv, src_last_blk, ivsize); +- sg_pcopy_to_buffer(dev->first, dev->src_nents, req->iv, +- ivsize, dev->total - ivsize); +- } +- +- err = dev->load_data(dev, dev->sg_src, dev->sg_dst); +- if (!err) +- crypto_dma_start(dev); +- return err; +-} +- +-static int rk_ablk_start(struct rk_crypto_info *dev) +-{ +- struct skcipher_request *req = +- skcipher_request_cast(dev->async_req); +- unsigned long flags; ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(areq); ++ struct scatterlist *sgs, *sgd; + int err = 0; ++ int ivsize = crypto_skcipher_ivsize(tfm); ++ int offset; ++ u8 iv[AES_BLOCK_SIZE]; ++ u8 biv[AES_BLOCK_SIZE]; ++ u8 *ivtouse = areq->iv; ++ unsigned int len = areq->cryptlen; ++ unsigned int todo; ++ ++ ivsize = crypto_skcipher_ivsize(tfm); ++ if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) { ++ if (rctx->mode & RK_CRYPTO_DEC) { ++ offset = areq->cryptlen - ivsize; ++ scatterwalk_map_and_copy(rctx->backup_iv, areq->src, ++ offset, ivsize, 0); ++ } ++ } + +- dev->left_bytes = req->cryptlen; +- dev->total = req->cryptlen; +- dev->sg_src = req->src; +- dev->first = req->src; +- dev->src_nents = sg_nents(req->src); +- dev->sg_dst = req->dst; +- dev->dst_nents = sg_nents(req->dst); +- +- spin_lock_irqsave(&dev->lock, flags); +- rk_ablk_hw_init(dev); +- err = rk_set_data_start(dev); +- spin_unlock_irqrestore(&dev->lock, flags); +- return err; +-} +- +-static void rk_iv_copyback(struct rk_crypto_info *dev) +-{ +- struct skcipher_request *req = +- skcipher_request_cast(dev->async_req); +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); +- u32 ivsize = crypto_skcipher_ivsize(tfm); ++ sgs = areq->src; ++ sgd = areq->dst; + +- /* Update the IV buffer to contain the next IV for encryption mode. */ +- if (!(rctx->mode & RK_CRYPTO_DEC)) { +- memcpy(req->iv, +- sg_virt(dev->sg_dst) + dev->sg_dst->length - ivsize, +- ivsize); ++ while (sgs && sgd && len) { ++ if (!sgs->length) { ++ sgs = sg_next(sgs); ++ sgd = sg_next(sgd); ++ continue; ++ } ++ if (rctx->mode & RK_CRYPTO_DEC) { ++ /* we backup last block of source to be used as IV at next step */ ++ offset = sgs->length - ivsize; ++ scatterwalk_map_and_copy(biv, sgs, offset, ivsize, 0); ++ } ++ if (sgs == sgd) { ++ err = dma_map_sg(ctx->dev->dev, sgs, 1, DMA_BIDIRECTIONAL); ++ if (err <= 0) { ++ err = -EINVAL; ++ goto theend_iv; ++ } ++ } else { ++ err = dma_map_sg(ctx->dev->dev, sgs, 1, DMA_TO_DEVICE); ++ if (err <= 0) { ++ err = -EINVAL; ++ goto theend_iv; ++ } ++ err = dma_map_sg(ctx->dev->dev, sgd, 1, DMA_FROM_DEVICE); ++ if (err <= 0) { ++ err = -EINVAL; ++ goto theend_sgs; ++ } ++ } ++ err = 0; ++ rk_ablk_hw_init(ctx->dev, areq); ++ if (ivsize) { ++ if (ivsize == DES_BLOCK_SIZE) ++ memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_IV_0, ivtouse, ivsize); ++ else ++ memcpy_toio(ctx->dev->reg + RK_CRYPTO_AES_IV_0, ivtouse, ivsize); ++ } ++ reinit_completion(&ctx->dev->complete); ++ ctx->dev->status = 0; ++ ++ todo = min(sg_dma_len(sgs), len); ++ len -= todo; ++ crypto_dma_start(ctx->dev, sgs, sgd, todo / 4); ++ wait_for_completion_interruptible_timeout(&ctx->dev->complete, ++ msecs_to_jiffies(2000)); ++ if (!ctx->dev->status) { ++ dev_err(ctx->dev->dev, "DMA timeout\n"); ++ err = -EFAULT; ++ goto theend; ++ } ++ if (sgs == sgd) { ++ dma_unmap_sg(ctx->dev->dev, sgs, 1, DMA_BIDIRECTIONAL); ++ } else { ++ dma_unmap_sg(ctx->dev->dev, sgs, 1, DMA_TO_DEVICE); ++ dma_unmap_sg(ctx->dev->dev, sgd, 1, DMA_FROM_DEVICE); ++ } ++ if (rctx->mode & RK_CRYPTO_DEC) { ++ memcpy(iv, biv, ivsize); ++ ivtouse = iv; ++ } else { ++ offset = sgd->length - ivsize; ++ scatterwalk_map_and_copy(iv, sgd, offset, ivsize, 0); ++ ivtouse = iv; ++ } ++ sgs = sg_next(sgs); ++ sgd = sg_next(sgd); + } +-} +- +-static void rk_update_iv(struct rk_crypto_info *dev) +-{ +- struct skcipher_request *req = +- skcipher_request_cast(dev->async_req); +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); +- u32 ivsize = crypto_skcipher_ivsize(tfm); +- u8 *new_iv = NULL; + +- if (rctx->mode & RK_CRYPTO_DEC) { +- new_iv = ctx->iv; +- } else { +- new_iv = page_address(sg_page(dev->sg_dst)) + +- dev->sg_dst->offset + dev->sg_dst->length - ivsize; ++ if (areq->iv && ivsize > 0) { ++ offset = areq->cryptlen - ivsize; ++ if (rctx->mode & RK_CRYPTO_DEC) { ++ memcpy(areq->iv, rctx->backup_iv, ivsize); ++ memzero_explicit(rctx->backup_iv, ivsize); ++ } else { ++ scatterwalk_map_and_copy(areq->iv, areq->dst, offset, ++ ivsize, 0); ++ } + } + +- if (ivsize == DES_BLOCK_SIZE) +- memcpy_toio(dev->reg + RK_CRYPTO_TDES_IV_0, new_iv, ivsize); +- else if (ivsize == AES_BLOCK_SIZE) +- memcpy_toio(dev->reg + RK_CRYPTO_AES_IV_0, new_iv, ivsize); +-} ++theend: ++ local_bh_disable(); ++ crypto_finalize_skcipher_request(engine, areq, err); ++ local_bh_enable(); ++ return 0; + +-/* return: +- * true some err was occurred +- * fault no err, continue +- */ +-static int rk_ablk_rx(struct rk_crypto_info *dev) +-{ +- int err = 0; +- struct skcipher_request *req = +- skcipher_request_cast(dev->async_req); +- +- dev->unload_data(dev); +- if (dev->left_bytes) { +- rk_update_iv(dev); +- if (sg_is_last(dev->sg_src)) { +- dev_err(dev->dev, "[%s:%d] Lack of data\n", +- __func__, __LINE__); +- err = -ENOMEM; +- goto out_rx; +- } +- dev->sg_src = sg_next(dev->sg_src); +- dev->sg_dst = sg_next(dev->sg_dst); +- err = rk_set_data_start(dev); ++theend_sgs: ++ if (sgs == sgd) { ++ dma_unmap_sg(ctx->dev->dev, sgs, 1, DMA_BIDIRECTIONAL); + } else { +- rk_iv_copyback(dev); +- /* here show the calculation is over without any err */ +- dev->complete(dev->async_req, 0); +- tasklet_schedule(&dev->queue_task); ++ dma_unmap_sg(ctx->dev->dev, sgs, 1, DMA_TO_DEVICE); ++ dma_unmap_sg(ctx->dev->dev, sgd, 1, DMA_FROM_DEVICE); + } +-out_rx: ++theend_iv: + return err; + } + +@@ -446,9 +443,6 @@ static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) + algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); + + ctx->dev = algt->dev; +- ctx->dev->start = rk_ablk_start; +- ctx->dev->update = rk_ablk_rx; +- ctx->dev->complete = rk_crypto_complete; + + ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->fallback_tfm)) { +@@ -460,6 +454,8 @@ static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) + tfm->reqsize = sizeof(struct rk_cipher_rctx) + + crypto_skcipher_reqsize(ctx->fallback_tfm); + ++ ctx->enginectx.op.do_one_request = rk_cipher_run; ++ + return 0; + } + + +From patchwork Wed Jul 6 09:03:50 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907851 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 62682CCA473 + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.43 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:44 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 11/33] crypto: rockchip: rewrite type +Date: Wed, 6 Jul 2022 09:03:50 +0000 +Message-Id: <20220706090412.806101-12-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100446_532724_EC696E01 +X-CRM114-Status: GOOD ( 14.91 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Instead of using a custom type for classify algorithms, let's just use +already defined ones. +And let's made a bit more verbose about what is registered. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 26 +++++++++++++------ + drivers/crypto/rockchip/rk3288_crypto.h | 7 +---- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 6 ++--- + .../crypto/rockchip/rk3288_crypto_skcipher.c | 12 ++++----- + 4 files changed, 28 insertions(+), 23 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index 1afb65eee6c9..8f9664acc78d 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -102,12 +102,22 @@ static int rk_crypto_register(struct rk_crypto_info *crypto_info) + + for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) { + rk_cipher_algs[i]->dev = crypto_info; +- if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER) +- err = crypto_register_skcipher( +- &rk_cipher_algs[i]->alg.skcipher); +- else +- err = crypto_register_ahash( +- &rk_cipher_algs[i]->alg.hash); ++ switch (rk_cipher_algs[i]->type) { ++ case CRYPTO_ALG_TYPE_SKCIPHER: ++ dev_info(crypto_info->dev, "Register %s as %s\n", ++ rk_cipher_algs[i]->alg.skcipher.base.cra_name, ++ rk_cipher_algs[i]->alg.skcipher.base.cra_driver_name); ++ err = crypto_register_skcipher(&rk_cipher_algs[i]->alg.skcipher); ++ break; ++ case CRYPTO_ALG_TYPE_AHASH: ++ dev_info(crypto_info->dev, "Register %s as %s\n", ++ rk_cipher_algs[i]->alg.hash.halg.base.cra_name, ++ rk_cipher_algs[i]->alg.hash.halg.base.cra_driver_name); ++ err = crypto_register_ahash(&rk_cipher_algs[i]->alg.hash); ++ break; ++ default: ++ dev_err(crypto_info->dev, "unknown algorithm\n"); ++ } + if (err) + goto err_cipher_algs; + } +@@ -115,7 +125,7 @@ static int rk_crypto_register(struct rk_crypto_info *crypto_info) + + err_cipher_algs: + for (k = 0; k < i; k++) { +- if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER) ++ if (rk_cipher_algs[i]->type == CRYPTO_ALG_TYPE_SKCIPHER) + crypto_unregister_skcipher(&rk_cipher_algs[k]->alg.skcipher); + else + crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash); +@@ -128,7 +138,7 @@ static void rk_crypto_unregister(void) + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) { +- if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER) ++ if (rk_cipher_algs[i]->type == CRYPTO_ALG_TYPE_SKCIPHER) + crypto_unregister_skcipher(&rk_cipher_algs[i]->alg.skcipher); + else + crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash); +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index 65ed645e0168..d924ea17402a 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -232,18 +232,13 @@ struct rk_cipher_rctx { + struct skcipher_request fallback_req; // keep at the end + }; + +-enum alg_type { +- ALG_TYPE_HASH, +- ALG_TYPE_CIPHER, +-}; +- + struct rk_crypto_tmp { ++ u32 type; + struct rk_crypto_info *dev; + union { + struct skcipher_alg skcipher; + struct ahash_alg hash; + } alg; +- enum alg_type type; + }; + + extern struct rk_crypto_tmp rk_ecb_aes_alg; +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index edd40e16a3f0..d08e2438d356 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -352,7 +352,7 @@ static void rk_cra_hash_exit(struct crypto_tfm *tfm) + } + + struct rk_crypto_tmp rk_ahash_sha1 = { +- .type = ALG_TYPE_HASH, ++ .type = CRYPTO_ALG_TYPE_AHASH, + .alg.hash = { + .init = rk_ahash_init, + .update = rk_ahash_update, +@@ -382,7 +382,7 @@ struct rk_crypto_tmp rk_ahash_sha1 = { + }; + + struct rk_crypto_tmp rk_ahash_sha256 = { +- .type = ALG_TYPE_HASH, ++ .type = CRYPTO_ALG_TYPE_AHASH, + .alg.hash = { + .init = rk_ahash_init, + .update = rk_ahash_update, +@@ -412,7 +412,7 @@ struct rk_crypto_tmp rk_ahash_sha256 = { + }; + + struct rk_crypto_tmp rk_ahash_md5 = { +- .type = ALG_TYPE_HASH, ++ .type = CRYPTO_ALG_TYPE_AHASH, + .alg.hash = { + .init = rk_ahash_init, + .update = rk_ahash_update, +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 67a7e05d5ae3..1ed297f5d809 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -468,7 +468,7 @@ static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm) + } + + struct rk_crypto_tmp rk_ecb_aes_alg = { +- .type = ALG_TYPE_CIPHER, ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher = { + .base.cra_name = "ecb(aes)", + .base.cra_driver_name = "ecb-aes-rk", +@@ -490,7 +490,7 @@ struct rk_crypto_tmp rk_ecb_aes_alg = { + }; + + struct rk_crypto_tmp rk_cbc_aes_alg = { +- .type = ALG_TYPE_CIPHER, ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher = { + .base.cra_name = "cbc(aes)", + .base.cra_driver_name = "cbc-aes-rk", +@@ -513,7 +513,7 @@ struct rk_crypto_tmp rk_cbc_aes_alg = { + }; + + struct rk_crypto_tmp rk_ecb_des_alg = { +- .type = ALG_TYPE_CIPHER, ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher = { + .base.cra_name = "ecb(des)", + .base.cra_driver_name = "ecb-des-rk", +@@ -535,7 +535,7 @@ struct rk_crypto_tmp rk_ecb_des_alg = { + }; + + struct rk_crypto_tmp rk_cbc_des_alg = { +- .type = ALG_TYPE_CIPHER, ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher = { + .base.cra_name = "cbc(des)", + .base.cra_driver_name = "cbc-des-rk", +@@ -558,7 +558,7 @@ struct rk_crypto_tmp rk_cbc_des_alg = { + }; + + struct rk_crypto_tmp rk_ecb_des3_ede_alg = { +- .type = ALG_TYPE_CIPHER, ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher = { + .base.cra_name = "ecb(des3_ede)", + .base.cra_driver_name = "ecb-des3-ede-rk", +@@ -580,7 +580,7 @@ struct rk_crypto_tmp rk_ecb_des3_ede_alg = { + }; + + struct rk_crypto_tmp rk_cbc_des3_ede_alg = { +- .type = ALG_TYPE_CIPHER, ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, + .alg.skcipher = { + .base.cra_name = "cbc(des3_ede)", + .base.cra_driver_name = "cbc-des3-ede-rk", + +From patchwork Wed Jul 6 09:03:51 2022 +Content-Type: text/plain; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.44 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:45 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 12/33] crypto: rockchip: add debugfs +Date: Wed, 6 Jul 2022 09:03:51 +0000 +Message-Id: <20220706090412.806101-13-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100448_525840_916A79E9 +X-CRM114-Status: GOOD ( 19.09 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +This patch enable to access usage stats for each algorithm. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/Kconfig | 10 ++++ + drivers/crypto/rockchip/rk3288_crypto.c | 47 +++++++++++++++++++ + drivers/crypto/rockchip/rk3288_crypto.h | 11 +++++ + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 8 ++++ + .../crypto/rockchip/rk3288_crypto_skcipher.c | 15 ++++++ + 5 files changed, 91 insertions(+) + +diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig +index df4f0a2de098..2286df229c81 100644 +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -801,6 +801,16 @@ config CRYPTO_DEV_ROCKCHIP + This driver interfaces with the hardware crypto accelerator. + Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. + ++config CRYPTO_DEV_ROCKCHIP_DEBUG ++ bool "Enable Rockchip crypto stats" ++ depends on CRYPTO_DEV_ROCKCHIP ++ depends on DEBUG_FS ++ help ++ Say y to enable Rockchip crypto debug stats. ++ This will create /sys/kernel/debug/rk3288_crypto/stats for displaying ++ the number of requests per algorithm and other internal stats. ++ ++ + config CRYPTO_DEV_ZYNQMP_AES + tristate "Support for Xilinx ZynqMP AES hw accelerator" + depends on ZYNQMP_FIRMWARE || COMPILE_TEST +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index 8f9664acc78d..3e1b4f3b2422 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -95,6 +95,41 @@ static struct rk_crypto_tmp *rk_cipher_algs[] = { + &rk_ahash_md5, + }; + ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG ++static int rk_crypto_debugfs_show(struct seq_file *seq, void *v) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) { ++ if (!rk_cipher_algs[i]->dev) ++ continue; ++ switch (rk_cipher_algs[i]->type) { ++ case CRYPTO_ALG_TYPE_SKCIPHER: ++ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n", ++ rk_cipher_algs[i]->alg.skcipher.base.cra_driver_name, ++ rk_cipher_algs[i]->alg.skcipher.base.cra_name, ++ rk_cipher_algs[i]->stat_req, rk_cipher_algs[i]->stat_fb); ++ seq_printf(seq, "\tfallback due to length: %lu\n", ++ rk_cipher_algs[i]->stat_fb_len); ++ seq_printf(seq, "\tfallback due to alignment: %lu\n", ++ rk_cipher_algs[i]->stat_fb_align); ++ seq_printf(seq, "\tfallback due to SGs: %lu\n", ++ rk_cipher_algs[i]->stat_fb_sgdiff); ++ break; ++ case CRYPTO_ALG_TYPE_AHASH: ++ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n", ++ rk_cipher_algs[i]->alg.hash.halg.base.cra_driver_name, ++ rk_cipher_algs[i]->alg.hash.halg.base.cra_name, ++ rk_cipher_algs[i]->stat_req, rk_cipher_algs[i]->stat_fb); ++ break; ++ } ++ } ++ return 0; ++} ++ ++DEFINE_SHOW_ATTRIBUTE(rk_crypto_debugfs); ++#endif ++ + static int rk_crypto_register(struct rk_crypto_info *crypto_info) + { + unsigned int i, k; +@@ -246,6 +281,15 @@ static int rk_crypto_probe(struct platform_device *pdev) + goto err_register_alg; + } + ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG ++ /* Ignore error of debugfs */ ++ crypto_info->dbgfs_dir = debugfs_create_dir("rk3288_crypto", NULL); ++ crypto_info->dbgfs_stats = debugfs_create_file("stats", 0444, ++ crypto_info->dbgfs_dir, ++ crypto_info, ++ &rk_crypto_debugfs_fops); ++#endif ++ + dev_info(dev, "Crypto Accelerator successfully registered\n"); + return 0; + +@@ -260,6 +304,9 @@ static int rk_crypto_remove(struct platform_device *pdev) + { + struct rk_crypto_info *crypto_tmp = platform_get_drvdata(pdev); + ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG ++ debugfs_remove_recursive(crypto_tmp->dbgfs_dir); ++#endif + rk_crypto_unregister(); + rk_crypto_disable_clk(crypto_tmp); + crypto_engine_exit(crypto_tmp->engine); +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index d924ea17402a..945a8184bbad 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -199,6 +200,10 @@ struct rk_crypto_info { + struct crypto_engine *engine; + struct completion complete; + int status; ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG ++ struct dentry *dbgfs_dir; ++ struct dentry *dbgfs_stats; ++#endif + }; + + /* the private variable of hash */ +@@ -239,6 +244,12 @@ struct rk_crypto_tmp { + struct skcipher_alg skcipher; + struct ahash_alg hash; + } alg; ++ unsigned long stat_req; ++ unsigned long stat_fb; ++ unsigned long stat_fb_len; ++ unsigned long stat_fb_sglen; ++ unsigned long stat_fb_align; ++ unsigned long stat_fb_sgdiff; + }; + + extern struct rk_crypto_tmp rk_ecb_aes_alg; +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index d08e2438d356..8856c6226be6 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -39,6 +39,10 @@ static int rk_ahash_digest_fb(struct ahash_request *areq) + struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + struct rk_ahash_ctx *tfmctx = crypto_ahash_ctx(tfm); ++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); ++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash); ++ ++ algt->stat_fb++; + + ahash_request_set_tfm(&rctx->fallback_req, tfmctx->fallback_tfm); + rctx->fallback_req.base.flags = areq->base.flags & +@@ -249,6 +253,8 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); + struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); ++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); ++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash); + struct scatterlist *sg = areq->src; + int err = 0; + int i; +@@ -256,6 +262,8 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + + rctx->mode = 0; + ++ algt->stat_req++; ++ + switch (crypto_ahash_digestsize(tfm)) { + case SHA1_DIGEST_SIZE: + rctx->mode = RK_CRYPTO_HASH_SHA1; +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 1ed297f5d809..91b8a4c574da 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -18,6 +18,8 @@ static int rk_cipher_need_fallback(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + unsigned int bs = crypto_skcipher_blocksize(tfm); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); + struct scatterlist *sgs, *sgd; + unsigned int stodo, dtodo, len; + +@@ -29,20 +31,25 @@ static int rk_cipher_need_fallback(struct skcipher_request *req) + sgd = req->dst; + while (sgs && sgd) { + if (!IS_ALIGNED(sgs->offset, sizeof(u32))) { ++ algt->stat_fb_align++; + return true; + } + if (!IS_ALIGNED(sgd->offset, sizeof(u32))) { ++ algt->stat_fb_align++; + return true; + } + stodo = min(len, sgs->length); + if (stodo % bs) { ++ algt->stat_fb_len++; + return true; + } + dtodo = min(len, sgd->length); + if (dtodo % bs) { ++ algt->stat_fb_len++; + return true; + } + if (stodo != dtodo) { ++ algt->stat_fb_sgdiff++; + return true; + } + len -= stodo; +@@ -57,8 +64,12 @@ static int rk_cipher_fallback(struct skcipher_request *areq) + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); + struct rk_cipher_ctx *op = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(areq); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); + int err; + ++ algt->stat_fb++; ++ + skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm); + skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags, + areq->base.complete, areq->base.data); +@@ -324,6 +335,10 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + u8 *ivtouse = areq->iv; + unsigned int len = areq->cryptlen; + unsigned int todo; ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); ++ ++ algt->stat_req++; + + ivsize = crypto_skcipher_ivsize(tfm); + if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) { + +From patchwork Wed Jul 6 09:03:52 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907840 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id CBE6BC43334 + for ; + Wed, 6 Jul 2022 09:57:21 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.45 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:46 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 13/33] crypto: rockchip: introduce PM +Date: Wed, 6 Jul 2022 09:03:52 +0000 +Message-Id: <20220706090412.806101-14-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100449_454176_07561F5C +X-CRM114-Status: GOOD ( 19.29 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Add runtime PM support for rockchip crypto. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 51 ++++++++++++++++++- + drivers/crypto/rockchip/rk3288_crypto.h | 1 + + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 10 ++++ + .../crypto/rockchip/rk3288_crypto_skcipher.c | 9 ++++ + 4 files changed, 69 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index 3e1b4f3b2422..d9258b9e71b3 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -65,6 +65,48 @@ static void rk_crypto_disable_clk(struct rk_crypto_info *dev) + clk_disable_unprepare(dev->sclk); + } + ++/* ++ * Power management strategy: The device is suspended unless a TFM exists for ++ * one of the algorithms proposed by this driver. ++ */ ++static int rk_crypto_pm_suspend(struct device *dev) ++{ ++ struct rk_crypto_info *rkdev = dev_get_drvdata(dev); ++ ++ rk_crypto_disable_clk(rkdev); ++ return 0; ++} ++ ++static int rk_crypto_pm_resume(struct device *dev) ++{ ++ struct rk_crypto_info *rkdev = dev_get_drvdata(dev); ++ ++ return rk_crypto_enable_clk(rkdev); ++} ++ ++static const struct dev_pm_ops rk_crypto_pm_ops = { ++ SET_RUNTIME_PM_OPS(rk_crypto_pm_suspend, rk_crypto_pm_resume, NULL) ++}; ++ ++static int rk_crypto_pm_init(struct rk_crypto_info *rkdev) ++{ ++ int err; ++ ++ pm_runtime_use_autosuspend(rkdev->dev); ++ pm_runtime_set_autosuspend_delay(rkdev->dev, 2000); ++ ++ err = pm_runtime_set_suspended(rkdev->dev); ++ if (err) ++ return err; ++ pm_runtime_enable(rkdev->dev); ++ return err; ++} ++ ++static void rk_crypto_pm_exit(struct rk_crypto_info *rkdev) ++{ ++ pm_runtime_disable(rkdev->dev); ++} ++ + static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id) + { + struct rk_crypto_info *dev = platform_get_drvdata(dev_id); +@@ -273,7 +315,9 @@ static int rk_crypto_probe(struct platform_device *pdev) + crypto_engine_start(crypto_info->engine); + init_completion(&crypto_info->complete); + +- rk_crypto_enable_clk(crypto_info); ++ err = rk_crypto_pm_init(crypto_info); ++ if (err) ++ goto err_pm; + + err = rk_crypto_register(crypto_info); + if (err) { +@@ -294,6 +338,8 @@ static int rk_crypto_probe(struct platform_device *pdev) + return 0; + + err_register_alg: ++ rk_crypto_pm_exit(crypto_info); ++err_pm: + crypto_engine_exit(crypto_info->engine); + err_crypto: + dev_err(dev, "Crypto Accelerator not successfully registered\n"); +@@ -308,7 +354,7 @@ static int rk_crypto_remove(struct platform_device *pdev) + debugfs_remove_recursive(crypto_tmp->dbgfs_dir); + #endif + rk_crypto_unregister(); +- rk_crypto_disable_clk(crypto_tmp); ++ rk_crypto_pm_exit(crypto_tmp); + crypto_engine_exit(crypto_tmp->engine); + return 0; + } +@@ -318,6 +364,7 @@ static struct platform_driver crypto_driver = { + .remove = rk_crypto_remove, + .driver = { + .name = "rk3288-crypto", ++ .pm = &rk_crypto_pm_ops, + .of_match_table = crypto_of_id_table, + }, + }; +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index 945a8184bbad..ddbb9246ce16 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + #include + #include +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index 8856c6226be6..137013bd4410 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -328,6 +328,7 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) + struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg); + + const char *alg_name = crypto_tfm_alg_name(tfm); ++ int err; + + algt = container_of(alg, struct rk_crypto_tmp, alg.hash); + +@@ -349,7 +350,15 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) + tctx->enginectx.op.prepare_request = rk_hash_prepare; + tctx->enginectx.op.unprepare_request = rk_hash_unprepare; + ++ err = pm_runtime_resume_and_get(tctx->dev->dev); ++ if (err < 0) ++ goto error_pm; ++ + return 0; ++error_pm: ++ crypto_free_ahash(tctx->fallback_tfm); ++ ++ return err; + } + + static void rk_cra_hash_exit(struct crypto_tfm *tfm) +@@ -357,6 +366,7 @@ static void rk_cra_hash_exit(struct crypto_tfm *tfm) + struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm); + + crypto_free_ahash(tctx->fallback_tfm); ++ pm_runtime_put_autosuspend(tctx->dev->dev); + } + + struct rk_crypto_tmp rk_ahash_sha1 = { +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 91b8a4c574da..3bdb304aa794 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -454,6 +454,7 @@ static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) + struct skcipher_alg *alg = crypto_skcipher_alg(tfm); + const char *name = crypto_tfm_alg_name(&tfm->base); + struct rk_crypto_tmp *algt; ++ int err; + + algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); + +@@ -471,7 +472,14 @@ static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) + + ctx->enginectx.op.do_one_request = rk_cipher_run; + ++ err = pm_runtime_resume_and_get(ctx->dev->dev); ++ if (err < 0) ++ goto error_pm; ++ + return 0; ++error_pm: ++ crypto_free_skcipher(ctx->fallback_tfm); ++ return err; + } + + static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm) +@@ -480,6 +488,7 @@ static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm) + + memzero_explicit(ctx->key, ctx->keylen); + crypto_free_skcipher(ctx->fallback_tfm); ++ pm_runtime_put_autosuspend(ctx->dev->dev); + } + + struct rk_crypto_tmp rk_ecb_aes_alg = { + +From patchwork Wed Jul 6 09:03:53 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907942 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E255CCA473 + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.46 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:47 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 14/33] crypto: rockchip: handle reset also in PM +Date: Wed, 6 Jul 2022 09:03:53 +0000 +Message-Id: <20220706090412.806101-15-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020448_521285_A18D28EB +X-CRM114-Status: GOOD ( 14.27 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +reset could be handled by PM functions. +We keep the initial reset pulse to be sure the hw is a know device state +after probe. + +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 22 ++++++++++------------ + 1 file changed, 10 insertions(+), 12 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index d9258b9e71b3..399829ef92e0 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -74,14 +74,23 @@ static int rk_crypto_pm_suspend(struct device *dev) + struct rk_crypto_info *rkdev = dev_get_drvdata(dev); + + rk_crypto_disable_clk(rkdev); ++ reset_control_assert(rkdev->rst); ++ + return 0; + } + + static int rk_crypto_pm_resume(struct device *dev) + { + struct rk_crypto_info *rkdev = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = rk_crypto_enable_clk(rkdev); ++ if (ret) ++ return ret; ++ ++ reset_control_deassert(rkdev->rst); ++ return 0; + +- return rk_crypto_enable_clk(rkdev); + } + + static const struct dev_pm_ops rk_crypto_pm_ops = { +@@ -222,13 +231,6 @@ static void rk_crypto_unregister(void) + } + } + +-static void rk_crypto_action(void *data) +-{ +- struct rk_crypto_info *crypto_info = data; +- +- reset_control_assert(crypto_info->rst); +-} +- + static const struct of_device_id crypto_of_id_table[] = { + { .compatible = "rockchip,rk3288-crypto" }, + {} +@@ -258,10 +260,6 @@ static int rk_crypto_probe(struct platform_device *pdev) + usleep_range(10, 20); + reset_control_deassert(crypto_info->rst); + +- err = devm_add_action_or_reset(dev, rk_crypto_action, crypto_info); +- if (err) +- goto err_crypto; +- + crypto_info->reg = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(crypto_info->reg)) { + err = PTR_ERR(crypto_info->reg); + +From patchwork Wed Jul 6 09:03:54 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907828 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id C0C79C43334 + for ; + Wed, 6 Jul 2022 09:51:20 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20210309; h=Sender: + Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: + Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: + Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: + List-Owner; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.48 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:48 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 15/33] crypto: rockchip: use clk_bulk to simplify clock + management +Date: Wed, 6 Jul 2022 09:03:54 +0000 +Message-Id: <20220706090412.806101-16-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100452_956876_B8F1F2A5 +X-CRM114-Status: GOOD ( 14.25 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +rk3328 does not have the same clock names than rk3288, instead of using a complex +clock management, let's use clk_bulk to simplify their handling. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 66 ++++--------------------- + drivers/crypto/rockchip/rk3288_crypto.h | 6 +-- + 2 files changed, 11 insertions(+), 61 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index 399829ef92e0..a635029ac71d 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -22,47 +22,16 @@ static int rk_crypto_enable_clk(struct rk_crypto_info *dev) + { + int err; + +- err = clk_prepare_enable(dev->sclk); +- if (err) { +- dev_err(dev->dev, "[%s:%d], Couldn't enable clock sclk\n", +- __func__, __LINE__); +- goto err_return; +- } +- err = clk_prepare_enable(dev->aclk); +- if (err) { +- dev_err(dev->dev, "[%s:%d], Couldn't enable clock aclk\n", +- __func__, __LINE__); +- goto err_aclk; +- } +- err = clk_prepare_enable(dev->hclk); +- if (err) { +- dev_err(dev->dev, "[%s:%d], Couldn't enable clock hclk\n", +- __func__, __LINE__); +- goto err_hclk; +- } +- err = clk_prepare_enable(dev->dmaclk); +- if (err) { +- dev_err(dev->dev, "[%s:%d], Couldn't enable clock dmaclk\n", +- __func__, __LINE__); +- goto err_dmaclk; +- } +- return err; +-err_dmaclk: +- clk_disable_unprepare(dev->hclk); +-err_hclk: +- clk_disable_unprepare(dev->aclk); +-err_aclk: +- clk_disable_unprepare(dev->sclk); +-err_return: ++ err = clk_bulk_prepare_enable(dev->num_clks, dev->clks); ++ if (err) ++ dev_err(dev->dev, "Could not enable clock clks\n"); ++ + return err; + } + + static void rk_crypto_disable_clk(struct rk_crypto_info *dev) + { +- clk_disable_unprepare(dev->dmaclk); +- clk_disable_unprepare(dev->hclk); +- clk_disable_unprepare(dev->aclk); +- clk_disable_unprepare(dev->sclk); ++ clk_bulk_disable_unprepare(dev->num_clks, dev->clks); + } + + /* +@@ -266,27 +235,10 @@ static int rk_crypto_probe(struct platform_device *pdev) + goto err_crypto; + } + +- crypto_info->aclk = devm_clk_get(&pdev->dev, "aclk"); +- if (IS_ERR(crypto_info->aclk)) { +- err = PTR_ERR(crypto_info->aclk); +- goto err_crypto; +- } +- +- crypto_info->hclk = devm_clk_get(&pdev->dev, "hclk"); +- if (IS_ERR(crypto_info->hclk)) { +- err = PTR_ERR(crypto_info->hclk); +- goto err_crypto; +- } +- +- crypto_info->sclk = devm_clk_get(&pdev->dev, "sclk"); +- if (IS_ERR(crypto_info->sclk)) { +- err = PTR_ERR(crypto_info->sclk); +- goto err_crypto; +- } +- +- crypto_info->dmaclk = devm_clk_get(&pdev->dev, "apb_pclk"); +- if (IS_ERR(crypto_info->dmaclk)) { +- err = PTR_ERR(crypto_info->dmaclk); ++ crypto_info->num_clks = devm_clk_bulk_get_all(&pdev->dev, ++ &crypto_info->clks); ++ if (crypto_info->num_clks < 3) { ++ err = -EINVAL; + goto err_crypto; + } + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index ddbb9246ce16..28bf09fe1c1d 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -190,10 +190,8 @@ + + struct rk_crypto_info { + struct device *dev; +- struct clk *aclk; +- struct clk *hclk; +- struct clk *sclk; +- struct clk *dmaclk; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct reset_control *rst; + void __iomem *reg; + int irq; + +From patchwork Wed Jul 6 09:03:55 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907943 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 82CD1C43334 + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.49 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:49 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 16/33] crypto: rockchip: add myself as maintainer +Date: Wed, 6 Jul 2022 09:03:55 +0000 +Message-Id: <20220706090412.806101-17-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020450_469095_C76F649A +X-CRM114-Status: UNSURE ( 8.50 ) +X-CRM114-Notice: Please train this message. +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Nobody is set as maintainer of rockchip crypto, I propose to do it as I +have already reworked lot of this code. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + MAINTAINERS | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/MAINTAINERS b/MAINTAINERS +index 392e59e9a03e..f8af07fa96fe 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -17449,6 +17449,13 @@ F: Documentation/ABI/*/sysfs-driver-hid-roccat* + F: drivers/hid/hid-roccat* + F: include/linux/hid-roccat* + ++ROCKCHIP CRYPTO DRIVERS ++M: Corentin Labbe ++L: linux-crypto@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml ++F: drivers/crypto/rockchip/ ++ + ROCKCHIP I2S TDM DRIVER + M: Nicolas Frattaroli + L: linux-rockchip@lists.infradead.org + +From patchwork Wed Jul 6 09:03:56 2022 +Content-Type: text/plain; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.50 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:50 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 17/33] crypto: rockchip: use read_poll_timeout +Date: Wed, 6 Jul 2022 09:03:56 +0000 +Message-Id: <20220706090412.806101-18-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020454_138978_1CB1DFA2 +X-CRM114-Status: GOOD ( 13.42 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Use read_poll_timeout instead of open coding it. +In the same time, fix indentation of related comment. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 24 +++++++++---------- + 1 file changed, 12 insertions(+), 12 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index 137013bd4410..1fbab86c9238 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -10,6 +10,7 @@ + */ + #include + #include ++#include + #include "rk3288_crypto.h" + + /* +@@ -295,18 +296,17 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + sg = sg_next(sg); + } + +- /* +- * it will take some time to process date after last dma +- * transmission. +- * +- * waiting time is relative with the last date len, +- * so cannot set a fixed time here. +- * 10us makes system not call here frequently wasting +- * efficiency, and make it response quickly when dma +- * complete. +- */ +- while (!CRYPTO_READ(tctx->dev, RK_CRYPTO_HASH_STS)) +- udelay(10); ++ /* ++ * it will take some time to process date after last dma ++ * transmission. ++ * ++ * waiting time is relative with the last date len, ++ * so cannot set a fixed time here. ++ * 10us makes system not call here frequently wasting ++ * efficiency, and make it response quickly when dma ++ * complete. ++ */ ++ readl_poll_timeout(tctx->dev->reg + RK_CRYPTO_HASH_STS, v, v == 0, 10, 1000); + + for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) { + v = readl(tctx->dev->reg + RK_CRYPTO_HASH_DOUT_0 + i * 4); + +From patchwork Wed Jul 6 09:03:57 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907838 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 74F12C43334 + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.51 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:51 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 18/33] crypto: rockchip: fix style issue +Date: Wed, 6 Jul 2022 09:03:57 +0000 +Message-Id: <20220706090412.806101-19-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100453_695846_4EB0B659 +X-CRM114-Status: GOOD ( 10.80 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +This patch fixes some warning reported by checkpatch + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index 1fbab86c9238..fae779d73c84 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -336,7 +336,7 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) + + /* for fallback */ + tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0, +- CRYPTO_ALG_NEED_FALLBACK); ++ CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(tctx->fallback_tfm)) { + dev_err(tctx->dev->dev, "Could not load fallback driver.\n"); + return PTR_ERR(tctx->fallback_tfm); +@@ -394,8 +394,8 @@ struct rk_crypto_tmp rk_ahash_sha1 = { + .cra_init = rk_cra_hash_init, + .cra_exit = rk_cra_hash_exit, + .cra_module = THIS_MODULE, +- } +- } ++ } ++ } + } + }; + +@@ -424,8 +424,8 @@ struct rk_crypto_tmp rk_ahash_sha256 = { + .cra_init = rk_cra_hash_init, + .cra_exit = rk_cra_hash_exit, + .cra_module = THIS_MODULE, +- } +- } ++ } ++ } + } + }; + +@@ -454,7 +454,7 @@ struct rk_crypto_tmp rk_ahash_md5 = { + .cra_init = rk_cra_hash_init, + .cra_exit = rk_cra_hash_exit, + .cra_module = THIS_MODULE, +- } + } ++ } + } + }; + +From patchwork Wed Jul 6 09:03:58 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907945 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F403C43334 + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.52 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:52 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 19/33] crypto: rockchip: add support for rk3328 +Date: Wed, 6 Jul 2022 09:03:58 +0000 +Message-Id: <20220706090412.806101-20-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020453_425337_EAF7A955 +X-CRM114-Status: GOOD ( 10.87 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +The rk3328 could be used as-is by the rockchip driver. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index a635029ac71d..c92559b83f7d 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -202,6 +202,7 @@ static void rk_crypto_unregister(void) + + static const struct of_device_id crypto_of_id_table[] = { + { .compatible = "rockchip,rk3288-crypto" }, ++ { .compatible = "rockchip,rk3328-crypto" }, + {} + }; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.52 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:53 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 20/33] crypto: rockchip: rename ablk functions to cipher +Date: Wed, 6 Jul 2022 09:03:59 +0000 +Message-Id: <20220706090412.806101-21-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020454_577368_B19DAAE5 +X-CRM114-Status: GOOD ( 10.42 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Some functions have still ablk in their name even if there are +not handling ablk_cipher anymore. +So let's rename them. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + .../crypto/rockchip/rk3288_crypto_skcipher.c | 32 +++++++++---------- + 1 file changed, 16 insertions(+), 16 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 3bdb304aa794..d60c206e717d 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -273,7 +273,7 @@ static int rk_des3_ede_cbc_decrypt(struct skcipher_request *req) + return rk_handle_req(dev, req); + } + +-static void rk_ablk_hw_init(struct rk_crypto_info *dev, struct skcipher_request *req) ++static void rk_cipher_hw_init(struct rk_crypto_info *dev, struct skcipher_request *req) + { + struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req); + struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); +@@ -382,7 +382,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + } + } + err = 0; +- rk_ablk_hw_init(ctx->dev, areq); ++ rk_cipher_hw_init(ctx->dev, areq); + if (ivsize) { + if (ivsize == DES_BLOCK_SIZE) + memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_IV_0, ivtouse, ivsize); +@@ -448,7 +448,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + return err; + } + +-static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) ++static int rk_cipher_tfm_init(struct crypto_skcipher *tfm) + { + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_alg *alg = crypto_skcipher_alg(tfm); +@@ -482,7 +482,7 @@ static int rk_ablk_init_tfm(struct crypto_skcipher *tfm) + return err; + } + +-static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm) ++static void rk_cipher_tfm_exit(struct crypto_skcipher *tfm) + { + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + +@@ -503,8 +503,8 @@ struct rk_crypto_tmp rk_ecb_aes_alg = { + .base.cra_alignmask = 0x0f, + .base.cra_module = THIS_MODULE, + +- .init = rk_ablk_init_tfm, +- .exit = rk_ablk_exit_tfm, ++ .init = rk_cipher_tfm_init, ++ .exit = rk_cipher_tfm_exit, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = rk_aes_setkey, +@@ -525,8 +525,8 @@ struct rk_crypto_tmp rk_cbc_aes_alg = { + .base.cra_alignmask = 0x0f, + .base.cra_module = THIS_MODULE, + +- .init = rk_ablk_init_tfm, +- .exit = rk_ablk_exit_tfm, ++ .init = rk_cipher_tfm_init, ++ .exit = rk_cipher_tfm_exit, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, +@@ -548,8 +548,8 @@ struct rk_crypto_tmp rk_ecb_des_alg = { + .base.cra_alignmask = 0x07, + .base.cra_module = THIS_MODULE, + +- .init = rk_ablk_init_tfm, +- .exit = rk_ablk_exit_tfm, ++ .init = rk_cipher_tfm_init, ++ .exit = rk_cipher_tfm_exit, + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .setkey = rk_des_setkey, +@@ -570,8 +570,8 @@ struct rk_crypto_tmp rk_cbc_des_alg = { + .base.cra_alignmask = 0x07, + .base.cra_module = THIS_MODULE, + +- .init = rk_ablk_init_tfm, +- .exit = rk_ablk_exit_tfm, ++ .init = rk_cipher_tfm_init, ++ .exit = rk_cipher_tfm_exit, + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, +@@ -593,8 +593,8 @@ struct rk_crypto_tmp rk_ecb_des3_ede_alg = { + .base.cra_alignmask = 0x07, + .base.cra_module = THIS_MODULE, + +- .init = rk_ablk_init_tfm, +- .exit = rk_ablk_exit_tfm, ++ .init = rk_cipher_tfm_init, ++ .exit = rk_cipher_tfm_exit, + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .setkey = rk_tdes_setkey, +@@ -615,8 +615,8 @@ struct rk_crypto_tmp rk_cbc_des3_ede_alg = { + .base.cra_alignmask = 0x07, + .base.cra_module = THIS_MODULE, + +- .init = rk_ablk_init_tfm, +- .exit = rk_ablk_exit_tfm, ++ .init = rk_cipher_tfm_init, ++ .exit = rk_cipher_tfm_exit, + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + +From patchwork Wed Jul 6 09:04:00 2022 +Content-Type: text/plain; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.54 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:54 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 21/33] crypto: rockchip: rework rk_handle_req function +Date: Wed, 6 Jul 2022 09:04:00 +0000 +Message-Id: <20220706090412.806101-22-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020455_543862_49A64B88 +X-CRM114-Status: GOOD ( 10.60 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +This patch rework the rk_handle_req(), simply removing the +rk_crypto_info parameter. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + .../crypto/rockchip/rk3288_crypto_skcipher.c | 68 +++++-------------- + 1 file changed, 17 insertions(+), 51 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index d60c206e717d..3187869c4c68 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -82,10 +82,12 @@ static int rk_cipher_fallback(struct skcipher_request *areq) + return err; + } + +-static int rk_handle_req(struct rk_crypto_info *dev, +- struct skcipher_request *req) ++static int rk_cipher_handle_req(struct skcipher_request *req) + { +- struct crypto_engine *engine = dev->engine; ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ struct rk_cipher_ctx *tctx = crypto_skcipher_ctx(tfm); ++ struct rk_crypto_info *rkc = tctx->dev; ++ struct crypto_engine *engine = rkc->engine; + + if (rk_cipher_need_fallback(req)) + return rk_cipher_fallback(req); +@@ -142,135 +144,99 @@ static int rk_tdes_setkey(struct crypto_skcipher *cipher, + + static int rk_aes_ecb_encrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_AES_ECB_MODE; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_aes_ecb_decrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_AES_ECB_MODE | RK_CRYPTO_DEC; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_aes_cbc_encrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_AES_CBC_MODE; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_aes_cbc_decrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_AES_CBC_MODE | RK_CRYPTO_DEC; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_des_ecb_encrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = 0; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_des_ecb_decrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_DEC; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_des_cbc_encrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_des_cbc_decrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC | RK_CRYPTO_DEC; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_des3_ede_ecb_encrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_TDES_SELECT; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_des3_ede_ecb_decrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_DEC; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_des3_ede_cbc_encrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *dev = ctx->dev; + + rctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_TDES_CHAINMODE_CBC; +- return rk_handle_req(dev, req); ++ return rk_cipher_handle_req(req); + } + + static int rk_des3_ede_cbc_decrypt(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.55 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:55 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 22/33] crypto: rockchip: use a rk_crypto_info variable + instead of lot of indirection +Date: Wed, 6 Jul 2022 09:04:01 +0000 +Message-Id: <20220706090412.806101-23-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100458_575807_3BF16CDC +X-CRM114-Status: GOOD ( 12.34 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Instead of using lot of ctx->dev->xx indirections, use an intermediate +variable for rk_crypto_info. +This will help later, when 2 different rk_crypto_info would be used. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 23 +++++++----- + .../crypto/rockchip/rk3288_crypto_skcipher.c | 37 ++++++++++--------- + 2 files changed, 32 insertions(+), 28 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index fae779d73c84..636dbcde0ca3 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -226,9 +226,10 @@ static int rk_hash_prepare(struct crypto_engine *engine, void *breq) + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); + struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); ++ struct rk_crypto_info *rkc = tctx->dev; + int ret; + +- ret = dma_map_sg(tctx->dev->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); ++ ret = dma_map_sg(rkc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); + if (ret <= 0) + return -EINVAL; + +@@ -243,8 +244,9 @@ static int rk_hash_unprepare(struct crypto_engine *engine, void *breq) + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); + struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); ++ struct rk_crypto_info *rkc = tctx->dev; + +- dma_unmap_sg(tctx->dev->dev, areq->src, rctx->nrsg, DMA_TO_DEVICE); ++ dma_unmap_sg(rkc->dev, areq->src, rctx->nrsg, DMA_TO_DEVICE); + return 0; + } + +@@ -257,6 +259,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); + struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash); + struct scatterlist *sg = areq->src; ++ struct rk_crypto_info *rkc = tctx->dev; + int err = 0; + int i; + u32 v; +@@ -283,13 +286,13 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + rk_ahash_reg_init(areq); + + while (sg) { +- reinit_completion(&tctx->dev->complete); +- tctx->dev->status = 0; +- crypto_ahash_dma_start(tctx->dev, sg); +- wait_for_completion_interruptible_timeout(&tctx->dev->complete, ++ reinit_completion(&rkc->complete); ++ rkc->status = 0; ++ crypto_ahash_dma_start(rkc, sg); ++ wait_for_completion_interruptible_timeout(&rkc->complete, + msecs_to_jiffies(2000)); +- if (!tctx->dev->status) { +- dev_err(tctx->dev->dev, "DMA timeout\n"); ++ if (!rkc->status) { ++ dev_err(rkc->dev, "DMA timeout\n"); + err = -EFAULT; + goto theend; + } +@@ -306,10 +309,10 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + * efficiency, and make it response quickly when dma + * complete. + */ +- readl_poll_timeout(tctx->dev->reg + RK_CRYPTO_HASH_STS, v, v == 0, 10, 1000); ++ readl_poll_timeout(rkc->reg + RK_CRYPTO_HASH_STS, v, v == 0, 10, 1000); + + for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) { +- v = readl(tctx->dev->reg + RK_CRYPTO_HASH_DOUT_0 + i * 4); ++ v = readl(rkc->reg + RK_CRYPTO_HASH_DOUT_0 + i * 4); + put_unaligned_le32(v, areq->result + i * 4); + } + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 3187869c4c68..6a1bea98fded 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -303,6 +303,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + unsigned int todo; + struct skcipher_alg *alg = crypto_skcipher_alg(tfm); + struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); ++ struct rk_crypto_info *rkc = ctx->dev; + + algt->stat_req++; + +@@ -330,49 +331,49 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + scatterwalk_map_and_copy(biv, sgs, offset, ivsize, 0); + } + if (sgs == sgd) { +- err = dma_map_sg(ctx->dev->dev, sgs, 1, DMA_BIDIRECTIONAL); ++ err = dma_map_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL); + if (err <= 0) { + err = -EINVAL; + goto theend_iv; + } + } else { +- err = dma_map_sg(ctx->dev->dev, sgs, 1, DMA_TO_DEVICE); ++ err = dma_map_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); + if (err <= 0) { + err = -EINVAL; + goto theend_iv; + } +- err = dma_map_sg(ctx->dev->dev, sgd, 1, DMA_FROM_DEVICE); ++ err = dma_map_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE); + if (err <= 0) { + err = -EINVAL; + goto theend_sgs; + } + } + err = 0; +- rk_cipher_hw_init(ctx->dev, areq); ++ rk_cipher_hw_init(rkc, areq); + if (ivsize) { + if (ivsize == DES_BLOCK_SIZE) +- memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_IV_0, ivtouse, ivsize); ++ memcpy_toio(rkc->reg + RK_CRYPTO_TDES_IV_0, ivtouse, ivsize); + else +- memcpy_toio(ctx->dev->reg + RK_CRYPTO_AES_IV_0, ivtouse, ivsize); ++ memcpy_toio(rkc->reg + RK_CRYPTO_AES_IV_0, ivtouse, ivsize); + } +- reinit_completion(&ctx->dev->complete); +- ctx->dev->status = 0; ++ reinit_completion(&rkc->complete); ++ rkc->status = 0; + + todo = min(sg_dma_len(sgs), len); + len -= todo; +- crypto_dma_start(ctx->dev, sgs, sgd, todo / 4); +- wait_for_completion_interruptible_timeout(&ctx->dev->complete, ++ crypto_dma_start(rkc, sgs, sgd, todo / 4); ++ wait_for_completion_interruptible_timeout(&rkc->complete, + msecs_to_jiffies(2000)); +- if (!ctx->dev->status) { +- dev_err(ctx->dev->dev, "DMA timeout\n"); ++ if (!rkc->status) { ++ dev_err(rkc->dev, "DMA timeout\n"); + err = -EFAULT; + goto theend; + } + if (sgs == sgd) { +- dma_unmap_sg(ctx->dev->dev, sgs, 1, DMA_BIDIRECTIONAL); ++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL); + } else { +- dma_unmap_sg(ctx->dev->dev, sgs, 1, DMA_TO_DEVICE); +- dma_unmap_sg(ctx->dev->dev, sgd, 1, DMA_FROM_DEVICE); ++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); ++ dma_unmap_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE); + } + if (rctx->mode & RK_CRYPTO_DEC) { + memcpy(iv, biv, ivsize); +@@ -405,10 +406,10 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + + theend_sgs: + if (sgs == sgd) { +- dma_unmap_sg(ctx->dev->dev, sgs, 1, DMA_BIDIRECTIONAL); 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.56 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:56 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 23/33] crypto: rockchip: use the rk_crypto_info given as + parameter +Date: Wed, 6 Jul 2022 09:04:02 +0000 +Message-Id: <20220706090412.806101-24-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020457_419252_3FF6B609 +X-CRM114-Status: GOOD ( 10.89 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Instead of using the crypto_info from TFM ctx, use the one given as parameter. + +Reviewed-by: John Keeping +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto_skcipher.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 6a1bea98fded..cf0dfb6029d8 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -254,7 +254,7 @@ static void rk_cipher_hw_init(struct rk_crypto_info *dev, struct skcipher_reques + RK_CRYPTO_TDES_BYTESWAP_KEY | + RK_CRYPTO_TDES_BYTESWAP_IV; + CRYPTO_WRITE(dev, RK_CRYPTO_TDES_CTRL, rctx->mode); +- memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, ctx->key, ctx->keylen); ++ memcpy_toio(dev->reg + RK_CRYPTO_TDES_KEY1_0, ctx->key, ctx->keylen); + conf_reg = RK_CRYPTO_DESSEL; + } else { + rctx->mode |= RK_CRYPTO_AES_FIFO_MODE | +@@ -266,7 +266,7 @@ static void rk_cipher_hw_init(struct rk_crypto_info *dev, struct skcipher_reques + else if (ctx->keylen == AES_KEYSIZE_256) + rctx->mode |= RK_CRYPTO_AES_256BIT_key; + CRYPTO_WRITE(dev, RK_CRYPTO_AES_CTRL, rctx->mode); +- memcpy_toio(ctx->dev->reg + RK_CRYPTO_AES_KEY_0, ctx->key, ctx->keylen); ++ memcpy_toio(dev->reg + RK_CRYPTO_AES_KEY_0, ctx->key, ctx->keylen); + } + conf_reg |= RK_CRYPTO_BYTESWAP_BTFIFO | + RK_CRYPTO_BYTESWAP_BRFIFO; + +From patchwork Wed Jul 6 09:04:03 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907724 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 76AC7C433EF + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.57 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:57 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe , + Krzysztof Kozlowski +Subject: [PATCH v8 24/33] dt-bindings: crypto: convert rockchip-crypto to YAML +Date: Wed, 6 Jul 2022 09:04:03 +0000 +Message-Id: <20220706090412.806101-25-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100518_296700_1B5B943C +X-CRM114-Status: GOOD ( 12.81 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Convert rockchip-crypto to YAML. + +Reviewed-by: John Keeping +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Corentin Labbe +--- + .../crypto/rockchip,rk3288-crypto.yaml | 64 +++++++++++++++++++ + .../bindings/crypto/rockchip-crypto.txt | 28 -------- + 2 files changed, 64 insertions(+), 28 deletions(-) + create mode 100644 Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml + delete mode 100644 Documentation/devicetree/bindings/crypto/rockchip-crypto.txt + +diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml +new file mode 100644 +index 000000000000..8a219d439d02 +--- /dev/null ++++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml +@@ -0,0 +1,64 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/crypto/rockchip,rk3288-crypto.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip Electronics Security Accelerator ++ ++maintainers: ++ - Heiko Stuebner ++ ++properties: ++ compatible: ++ enum: ++ - rockchip,rk3288-crypto ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 4 ++ ++ clock-names: ++ items: ++ - const: aclk ++ - const: hclk ++ - const: sclk ++ - const: apb_pclk ++ ++ resets: ++ maxItems: 1 ++ ++ reset-names: ++ items: ++ - const: crypto-rst ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ crypto@ff8a0000 { ++ compatible = "rockchip,rk3288-crypto"; ++ reg = <0xff8a0000 0x4000>; ++ interrupts = ; ++ clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, ++ <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; ++ clock-names = "aclk", "hclk", "sclk", "apb_pclk"; ++ resets = <&cru SRST_CRYPTO>; ++ reset-names = "crypto-rst"; ++ }; +diff --git a/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt b/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt +deleted file mode 100644 +index 5e2ba385b8c9..000000000000 +--- a/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt ++++ /dev/null +@@ -1,28 +0,0 @@ +-Rockchip Electronics And Security Accelerator +- +-Required properties: +-- compatible: Should be "rockchip,rk3288-crypto" +-- reg: Base physical address of the engine and length of memory mapped +- region +-- interrupts: Interrupt number +-- clocks: Reference to the clocks about crypto +-- clock-names: "aclk" used to clock data +- "hclk" used to clock data +- "sclk" used to clock crypto accelerator +- "apb_pclk" used to clock dma +-- resets: Must contain an entry for each entry in reset-names. +- See ../reset/reset.txt for details. +-- reset-names: Must include the name "crypto-rst". +- +-Examples: +- +- crypto: cypto-controller@ff8a0000 { +- compatible = "rockchip,rk3288-crypto"; +- reg = <0xff8a0000 0x4000>; +- interrupts = ; +- clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, +- <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; +- clock-names = "aclk", "hclk", "sclk", "apb_pclk"; +- resets = <&cru SRST_CRYPTO>; +- reset-names = "crypto-rst"; +- }; + +From patchwork Wed Jul 6 09:04:04 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907723 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 63C01C43334 + for ; + Wed, 6 Jul 2022 09:22:42 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20210309; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.58 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:58 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe , + Krzysztof Kozlowski +Subject: [PATCH v8 25/33] dt-bindings: crypto: rockchip: convert to new driver + bindings +Date: Wed, 6 Jul 2022 09:04:04 +0000 +Message-Id: <20220706090412.806101-26-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100519_228129_9F768702 +X-CRM114-Status: UNSURE ( 8.43 ) +X-CRM114-Notice: Please train this message. +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +The latest addition to the rockchip crypto driver need to update the +driver bindings. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Corentin Labbe +--- + .../crypto/rockchip,rk3288-crypto.yaml | 85 +++++++++++++++++-- + 1 file changed, 77 insertions(+), 8 deletions(-) + +diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml +index 8a219d439d02..5bb6bf4699ff 100644 +--- a/Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml ++++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml +@@ -13,6 +13,8 @@ properties: + compatible: + enum: + - rockchip,rk3288-crypto ++ - rockchip,rk3328-crypto ++ - rockchip,rk3399-crypto + + reg: + maxItems: 1 +@@ -21,21 +23,88 @@ properties: + maxItems: 1 + + clocks: ++ minItems: 3 + maxItems: 4 + + clock-names: +- items: +- - const: aclk +- - const: hclk +- - const: sclk +- - const: apb_pclk ++ minItems: 3 ++ maxItems: 4 + + resets: +- maxItems: 1 ++ minItems: 1 ++ maxItems: 3 + + reset-names: +- items: +- - const: crypto-rst ++ minItems: 1 ++ maxItems: 3 ++ ++allOf: ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: rockchip,rk3288-crypto ++ then: ++ properties: ++ clocks: ++ minItems: 4 ++ clock-names: ++ items: ++ - const: aclk ++ - const: hclk ++ - const: sclk ++ - const: apb_pclk ++ minItems: 4 ++ resets: ++ maxItems: 1 ++ reset-names: ++ items: ++ - const: crypto-rst ++ maxItems: 1 ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: rockchip,rk3328-crypto ++ then: ++ properties: ++ clocks: ++ maxItems: 3 ++ clock-names: ++ items: ++ - const: hclk_master ++ - const: hclk_slave ++ - const: sclk ++ maxItems: 3 ++ resets: ++ maxItems: 1 ++ reset-names: ++ items: ++ - const: crypto-rst ++ maxItems: 1 ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: rockchip,rk3399-crypto ++ then: ++ properties: ++ clocks: ++ maxItems: 3 ++ clock-names: ++ items: ++ - const: hclk_master ++ - const: hclk_slave ++ - const: sclk ++ maxItems: 3 ++ resets: ++ minItems: 3 ++ reset-names: ++ items: ++ - const: rst_master ++ - const: rst_slave ++ - const: crypto-rst ++ minItems: 3 + + required: + - compatible + +From patchwork Wed Jul 6 09:04:05 2022 +Content-Type: text/plain; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.04.59 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:04:59 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe , + Rob Herring +Subject: [PATCH v8 26/33] clk: rk3399: use proper crypto0 name +Date: Wed, 6 Jul 2022 09:04:05 +0000 +Message-Id: <20220706090412.806101-27-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020500_610368_F1663984 +X-CRM114-Status: GOOD ( 10.81 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +RK3399 has 2 crypto instance, named crypto0 and crypto1 in the TRM. +Only reset for crypto1 is correctly named, but crypto0 is not. +Since nobody use them , add a 0 to be consistent with the TRM and crypto1 entries. + +Acked-by: Rob Herring +Signed-off-by: Corentin Labbe +--- + include/dt-bindings/clock/rk3399-cru.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h +index 44e0a319f077..39169d94a44e 100644 +--- a/include/dt-bindings/clock/rk3399-cru.h ++++ b/include/dt-bindings/clock/rk3399-cru.h +@@ -547,8 +547,8 @@ + #define SRST_H_PERILP0 171 + #define SRST_H_PERILP0_NOC 172 + #define SRST_ROM 173 +-#define SRST_CRYPTO_S 174 +-#define SRST_CRYPTO_M 175 ++#define SRST_CRYPTO0_S 174 ++#define SRST_CRYPTO0_M 175 + + /* cru_softrst_con11 */ + #define SRST_P_DCF 176 +@@ -556,7 +556,7 @@ + #define SRST_CM0S 178 + #define SRST_CM0S_DBG 179 + #define SRST_CM0S_PO 180 +-#define SRST_CRYPTO 181 ++#define SRST_CRYPTO0 181 + #define SRST_P_PERILP1_SGRF 182 + #define SRST_P_PERILP1_GRF 183 + #define SRST_CRYPTO1_S 184 + +From patchwork Wed Jul 6 09:04:06 2022 +Content-Type: text/plain; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.05.00 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:05:00 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 27/33] arm64: dts: rockchip: add rk3328 crypto node +Date: Wed, 6 Jul 2022 09:04:06 +0000 +Message-Id: <20220706090412.806101-28-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020501_540484_F333D9C0 +X-CRM114-Status: UNSURE ( 9.82 ) +X-CRM114-Notice: Please train this message. +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +rk3328 has a crypto IP handled by the rk3288 crypto driver so adds a +node for it. + +Signed-off-by: Corentin Labbe +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 49ae15708a0b..96a7a777bae8 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -1025,6 +1025,17 @@ gic: interrupt-controller@ff811000 { + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + ++ crypto: crypto@ff060000 { ++ compatible = "rockchip,rk3328-crypto"; ++ reg = <0x0 0xff060000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, ++ <&cru SCLK_CRYPTO>; ++ clock-names = "hclk_master", "hclk_slave", "sclk"; ++ resets = <&cru SRST_CRYPTO>; ++ reset-names = "crypto-rst"; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3328-pinctrl"; + rockchip,grf = <&grf>; + +From patchwork Wed Jul 6 09:04:07 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907827 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 464CCC43334 + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.05.01 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:05:01 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 28/33] arm64: dts: rockchip: rk3399: add crypto node +Date: Wed, 6 Jul 2022 09:04:07 +0000 +Message-Id: <20220706090412.806101-29-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100519_988071_B1C2DF26 +X-CRM114-Status: UNSURE ( 8.97 ) +X-CRM114-Notice: Please train this message. +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +The rk3399 has a crypto IP handled by the rk3288 crypto driver so adds a +node for it. + +Tested-by Diederik de Haas +Signed-off-by: Corentin Labbe +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 9d5b0e8c9cca..8e5aa1ca62d1 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -582,6 +582,26 @@ saradc: saradc@ff100000 { + status = "disabled"; + }; + ++ crypto0: crypto@ff8b0000 { ++ compatible = "rockchip,rk3399-crypto"; ++ reg = <0x0 0xff8b0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>; ++ clock-names = "hclk_master", "hclk_slave", "sclk"; ++ resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>; ++ reset-names = "rst_master", "rst_slave", "crypto-rst"; ++ }; ++ ++ crypto1: crypto@ff8b8000 { ++ compatible = "rockchip,rk3399-crypto"; ++ reg = <0x0 0xff8b8000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>; ++ clock-names = "hclk_master", "hclk_slave", "sclk"; ++ resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>; ++ reset-names = "rst_master", "rst_slave", "crypto-rst"; ++ }; ++ + i2c1: i2c@ff110000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff110000 0x0 0x1000>; + +From patchwork Wed Jul 6 09:04:08 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907618 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id F339FCCA485 + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.05.02 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:05:02 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 29/33] crypto: rockchip: store crypto_info in request + context +Date: Wed, 6 Jul 2022 09:04:08 +0000 +Message-Id: <20220706090412.806101-30-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020503_569252_3FCE3A43 +X-CRM114-Status: GOOD ( 13.57 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +The crypto_info to use must be stored in the request context. +This will help when 2 crypto_info will be available on rk3399. + +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.h | 2 ++ + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 14 ++++++-------- + drivers/crypto/rockchip/rk3288_crypto_skcipher.c | 6 ++++-- + 3 files changed, 12 insertions(+), 10 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index 28bf09fe1c1d..ff9fc25972eb 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -215,6 +215,7 @@ struct rk_ahash_ctx { + + /* the private variable of hash for fallback */ + struct rk_ahash_rctx { ++ struct rk_crypto_info *dev; + struct ahash_request fallback_req; + u32 mode; + int nrsg; +@@ -231,6 +232,7 @@ struct rk_cipher_ctx { + }; + + struct rk_cipher_rctx { ++ struct rk_crypto_info *dev; + u8 backup_iv[AES_BLOCK_SIZE]; + u32 mode; + struct skcipher_request fallback_req; // keep at the end +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index 636dbcde0ca3..d1bf68cb390d 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -200,6 +200,7 @@ static int rk_ahash_export(struct ahash_request *req, void *out) + + static int rk_ahash_digest(struct ahash_request *req) + { ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(req); + struct rk_ahash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); + struct rk_crypto_info *dev = tctx->dev; + +@@ -209,6 +210,8 @@ static int rk_ahash_digest(struct ahash_request *req) + if (!req->nbytes) + return zero_message_process(req); + ++ rctx->dev = dev; ++ + return crypto_transfer_hash_request_to_engine(dev->engine, req); + } + +@@ -223,10 +226,8 @@ static void crypto_ahash_dma_start(struct rk_crypto_info *dev, struct scatterlis + static int rk_hash_prepare(struct crypto_engine *engine, void *breq) + { + struct ahash_request *areq = container_of(breq, struct ahash_request, base); +- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); +- struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); +- struct rk_crypto_info *rkc = tctx->dev; ++ struct rk_crypto_info *rkc = rctx->dev; + int ret; + + ret = dma_map_sg(rkc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); +@@ -241,10 +242,8 @@ static int rk_hash_prepare(struct crypto_engine *engine, void *breq) + static int rk_hash_unprepare(struct crypto_engine *engine, void *breq) + { + struct ahash_request *areq = container_of(breq, struct ahash_request, base); +- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); +- struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); +- struct rk_crypto_info *rkc = tctx->dev; ++ struct rk_crypto_info *rkc = rctx->dev; + + dma_unmap_sg(rkc->dev, areq->src, rctx->nrsg, DMA_TO_DEVICE); + return 0; +@@ -255,11 +254,10 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + struct ahash_request *areq = container_of(breq, struct ahash_request, base); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); +- struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); + struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); + struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash); + struct scatterlist *sg = areq->src; +- struct rk_crypto_info *rkc = tctx->dev; ++ struct rk_crypto_info *rkc = rctx->dev; + int err = 0; + int i; + u32 v; +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index cf0dfb6029d8..0b1c90ababb7 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -86,12 +86,15 @@ static int rk_cipher_handle_req(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct rk_cipher_ctx *tctx = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); + struct rk_crypto_info *rkc = tctx->dev; + struct crypto_engine *engine = rkc->engine; + + if (rk_cipher_need_fallback(req)) + return rk_cipher_fallback(req); + ++ rctx->dev = rkc; ++ + return crypto_transfer_skcipher_request_to_engine(engine, req); + } + +@@ -290,7 +293,6 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + { + struct skcipher_request *areq = container_of(async_req, struct skcipher_request, base); + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); +- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(areq); + struct scatterlist *sgs, *sgd; + int err = 0; +@@ -303,7 +305,7 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + unsigned int todo; + struct skcipher_alg *alg = crypto_skcipher_alg(tfm); + struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.05.03 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:05:03 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 30/33] crypto: rockchip: Check for clocks numbers and their + frequencies +Date: Wed, 6 Jul 2022 09:04:09 +0000 +Message-Id: <20220706090412.806101-31-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020509_427772_96179BC9 +X-CRM114-Status: GOOD ( 20.30 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +Add the number of clocks needed for each compatible. +Rockchip's datasheet give maximum frequencies for some clocks, so add +checks for verifying they are within limits. Let's start with rk3288 for +clock frequency check, other will came later. + +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 75 +++++++++++++++++++++---- + drivers/crypto/rockchip/rk3288_crypto.h | 16 +++++- + 2 files changed, 79 insertions(+), 12 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index c92559b83f7d..232dc625d6e5 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -14,10 +14,58 @@ + #include + #include + #include ++#include + #include + #include + #include + ++static const struct rk_variant rk3288_variant = { ++ .num_clks = 4, ++ .rkclks = { ++ { "sclk", 150000000}, ++ } ++}; ++ ++static const struct rk_variant rk3328_variant = { ++ .num_clks = 3, ++}; ++ ++static int rk_crypto_get_clks(struct rk_crypto_info *dev) ++{ ++ int i, j, err; ++ unsigned long cr; ++ ++ dev->num_clks = devm_clk_bulk_get_all(dev->dev, &dev->clks); ++ if (dev->num_clks < dev->variant->num_clks) { ++ dev_err(dev->dev, "Missing clocks, got %d instead of %d\n", ++ dev->num_clks, dev->variant->num_clks); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < dev->num_clks; i++) { ++ cr = clk_get_rate(dev->clks[i].clk); ++ for (j = 0; j < ARRAY_SIZE(dev->variant->rkclks); j++) { ++ if (dev->variant->rkclks[j].max == 0) ++ continue; ++ if (strcmp(dev->variant->rkclks[j].name, dev->clks[i].id)) ++ continue; ++ if (cr > dev->variant->rkclks[j].max) { ++ err = clk_set_rate(dev->clks[i].clk, ++ dev->variant->rkclks[j].max); ++ if (err) ++ dev_err(dev->dev, "Fail downclocking %s from %lu to %lu\n", ++ dev->variant->rkclks[j].name, cr, ++ dev->variant->rkclks[j].max); ++ else ++ dev_info(dev->dev, "Downclocking %s from %lu to %lu\n", ++ dev->variant->rkclks[j].name, cr, ++ dev->variant->rkclks[j].max); ++ } ++ } ++ } ++ return 0; ++} ++ + static int rk_crypto_enable_clk(struct rk_crypto_info *dev) + { + int err; +@@ -201,8 +249,12 @@ static void rk_crypto_unregister(void) + } + + static const struct of_device_id crypto_of_id_table[] = { +- { .compatible = "rockchip,rk3288-crypto" }, +- { .compatible = "rockchip,rk3328-crypto" }, ++ { .compatible = "rockchip,rk3288-crypto", ++ .data = &rk3288_variant, ++ }, ++ { .compatible = "rockchip,rk3328-crypto", ++ .data = &rk3328_variant, ++ }, + {} + }; + MODULE_DEVICE_TABLE(of, crypto_of_id_table); +@@ -220,6 +272,15 @@ static int rk_crypto_probe(struct platform_device *pdev) + goto err_crypto; + } + ++ crypto_info->dev = &pdev->dev; ++ platform_set_drvdata(pdev, crypto_info); ++ ++ crypto_info->variant = of_device_get_match_data(&pdev->dev); ++ if (!crypto_info->variant) { ++ dev_err(&pdev->dev, "Missing variant\n"); ++ return -EINVAL; ++ } ++ + crypto_info->rst = devm_reset_control_get(dev, "crypto-rst"); + if (IS_ERR(crypto_info->rst)) { + err = PTR_ERR(crypto_info->rst); +@@ -236,12 +297,9 @@ static int rk_crypto_probe(struct platform_device *pdev) + goto err_crypto; + } + +- crypto_info->num_clks = devm_clk_bulk_get_all(&pdev->dev, +- &crypto_info->clks); +- if (crypto_info->num_clks < 3) { +- err = -EINVAL; ++ err = rk_crypto_get_clks(crypto_info); ++ if (err) + goto err_crypto; +- } + + crypto_info->irq = platform_get_irq(pdev, 0); + if (crypto_info->irq < 0) { +@@ -259,9 +317,6 @@ static int rk_crypto_probe(struct platform_device *pdev) + goto err_crypto; + } + +- crypto_info->dev = &pdev->dev; +- platform_set_drvdata(pdev, crypto_info); +- + crypto_info->engine = crypto_engine_alloc_init(&pdev->dev, true); + crypto_engine_start(crypto_info->engine); + init_completion(&crypto_info->complete); +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index ff9fc25972eb..ac979d67ced9 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -188,14 +188,26 @@ + #define CRYPTO_WRITE(dev, offset, val) \ + writel_relaxed((val), ((dev)->reg + (offset))) + ++#define RK_MAX_CLKS 4 ++ ++struct rk_clks { ++ const char *name; ++ unsigned long max; ++}; ++ ++struct rk_variant { ++ int num_clks; ++ struct rk_clks rkclks[RK_MAX_CLKS]; ++}; ++ + struct rk_crypto_info { + struct device *dev; + struct clk_bulk_data *clks; +- int num_clks; ++ int num_clks; + struct reset_control *rst; + void __iomem *reg; + int irq; +- ++ const struct rk_variant *variant; + struct crypto_engine *engine; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.05.04 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:05:04 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 31/33] crypto: rockchip: rk_ahash_reg_init use crypto_info + from parameter +Date: Wed, 6 Jul 2022 09:04:10 +0000 +Message-Id: <20220706090412.806101-32-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_020505_557491_1E895A01 +X-CRM114-Status: GOOD ( 10.28 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +rk_ahash_reg_init() use crypto_info from TFM context, since we will +remove it, let's take if from parameters. + +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index d1bf68cb390d..30f78256c955 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -78,12 +78,10 @@ static int zero_message_process(struct ahash_request *req) + return 0; + } + +-static void rk_ahash_reg_init(struct ahash_request *req) ++static void rk_ahash_reg_init(struct ahash_request *req, ++ struct rk_crypto_info *dev) + { + struct rk_ahash_rctx *rctx = ahash_request_ctx(req); +- struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); +- struct rk_ahash_ctx *tctx = crypto_ahash_ctx(tfm); +- struct rk_crypto_info *dev = tctx->dev; + int reg_status; + + reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL) | +@@ -281,7 +279,7 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + goto theend; + } + +- rk_ahash_reg_init(areq); ++ rk_ahash_reg_init(areq, rkc); + + while (sg) { + reinit_completion(&rkc->complete); + +From patchwork Wed Jul 6 09:04:11 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907735 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E4B6C43334 + for ; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.05.05 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:05:05 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 32/33] crypto: rockchip: permit to have more than one reset +Date: Wed, 6 Jul 2022 09:04:11 +0000 +Message-Id: <20220706090412.806101-33-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100518_046260_25E97BAD +X-CRM114-Status: GOOD ( 10.62 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +The RK3399 has 3 resets, so the driver to handle multiple resets. +This is done by using devm_reset_control_array_get_exclusive(). + +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index 232dc625d6e5..d96f375423d5 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -281,7 +281,7 @@ static int rk_crypto_probe(struct platform_device *pdev) + return -EINVAL; + } + +- crypto_info->rst = devm_reset_control_get(dev, "crypto-rst"); ++ crypto_info->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(crypto_info->rst)) { + err = PTR_ERR(crypto_info->rst); + goto err_crypto; + +From patchwork Wed Jul 6 09:04:12 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: LABBE Corentin +X-Patchwork-Id: 12907722 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 8311AC43334 + for ; + Wed, 6 Jul 2022 09:22:22 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20210309; h=Sender: + Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: + Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: + Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: + List-Owner; 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[90.63.244.31]) + by smtp.googlemail.com with ESMTPSA id + v11-20020adfe28b000000b0021d6ef34b2asm5230223wri.51.2022.07.06.02.05.06 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 06 Jul 2022 02:05:06 -0700 (PDT) +From: Corentin Labbe +To: heiko@sntech.de, + herbert@gondor.apana.org.au, + krzysztof.kozlowski+dt@linaro.org, + mturquette@baylibre.com, + p.zabel@pengutronix.de, + robh+dt@kernel.org, + sboyd@kernel.org +Cc: linux-rockchip@lists.infradead.org, + devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-clk@vger.kernel.org, + linux-crypto@vger.kernel.org, + linux-kernel@vger.kernel.org, + john@metanate.com, + didi.debian@cknow.org, + Corentin Labbe +Subject: [PATCH v8 33/33] crypto: rockchip: Add support for RK3399 +Date: Wed, 6 Jul 2022 09:04:12 +0000 +Message-Id: <20220706090412.806101-34-clabbe@baylibre.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20220706090412.806101-1-clabbe@baylibre.com> +References: <20220706090412.806101-1-clabbe@baylibre.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220706_100519_417420_1045A328 +X-CRM114-Status: GOOD ( 25.31 ) +X-BeenThere: linux-rockchip@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: Upstream kernel work for Rockchip platforms + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Sender: "Linux-rockchip" +Errors-To: + linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org + +The RK3399 has 2 rk3288 compatible crypto device named crypto0 and +crypto1. The only difference is lack of RSA in crypto1. + +We need to add driver support for 2 parallel instance as only one need +to register crypto algorithms. +Then the driver will round robin each request on each device. + +For avoiding complexity (device bringup after a TFM is created), PM is +modified to be handled per request. +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/rk3288_crypto.c | 92 +++++++++++++++---- + drivers/crypto/rockchip/rk3288_crypto.h | 25 +++-- + drivers/crypto/rockchip/rk3288_crypto_ahash.c | 37 ++++---- + .../crypto/rockchip/rk3288_crypto_skcipher.c | 37 ++++---- + 4 files changed, 123 insertions(+), 68 deletions(-) + +diff --git a/drivers/crypto/rockchip/rk3288_crypto.c b/drivers/crypto/rockchip/rk3288_crypto.c +index d96f375423d5..6217e73ba4c4 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -19,6 +19,23 @@ + #include + #include + ++static struct rockchip_ip rocklist = { ++ .dev_list = LIST_HEAD_INIT(rocklist.dev_list), ++ .lock = __SPIN_LOCK_UNLOCKED(rocklist.lock), ++}; ++ ++struct rk_crypto_info *get_rk_crypto(void) ++{ ++ struct rk_crypto_info *first; ++ ++ spin_lock(&rocklist.lock); ++ first = list_first_entry_or_null(&rocklist.dev_list, ++ struct rk_crypto_info, list); ++ list_rotate_left(&rocklist.dev_list); ++ spin_unlock(&rocklist.lock); ++ return first; ++} ++ + static const struct rk_variant rk3288_variant = { + .num_clks = 4, + .rkclks = { +@@ -30,6 +47,10 @@ static const struct rk_variant rk3328_variant = { + .num_clks = 3, + }; + ++static const struct rk_variant rk3399_variant = { ++ .num_clks = 3, ++}; ++ + static int rk_crypto_get_clks(struct rk_crypto_info *dev) + { + int i, j, err; +@@ -83,8 +104,8 @@ static void rk_crypto_disable_clk(struct rk_crypto_info *dev) + } + + /* +- * Power management strategy: The device is suspended unless a TFM exists for +- * one of the algorithms proposed by this driver. ++ * Power management strategy: The device is suspended until a request ++ * is handled. For avoiding suspend/resume yoyo, the autosuspend is set to 2s. + */ + static int rk_crypto_pm_suspend(struct device *dev) + { +@@ -166,8 +187,17 @@ static struct rk_crypto_tmp *rk_cipher_algs[] = { + #ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG + static int rk_crypto_debugfs_show(struct seq_file *seq, void *v) + { ++ struct rk_crypto_info *dd; + unsigned int i; + ++ spin_lock(&rocklist.lock); ++ list_for_each_entry(dd, &rocklist.dev_list, list) { ++ seq_printf(seq, "%s %s requests: %lu\n", ++ dev_driver_string(dd->dev), dev_name(dd->dev), ++ dd->nreq); ++ } ++ spin_unlock(&rocklist.lock); ++ + for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) { + if (!rk_cipher_algs[i]->dev) + continue; +@@ -198,6 +228,18 @@ static int rk_crypto_debugfs_show(struct seq_file *seq, void *v) + DEFINE_SHOW_ATTRIBUTE(rk_crypto_debugfs); + #endif + ++static void register_debugfs(struct rk_crypto_info *crypto_info) ++{ ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG ++ /* Ignore error of debugfs */ ++ rocklist.dbgfs_dir = debugfs_create_dir("rk3288_crypto", NULL); ++ rocklist.dbgfs_stats = debugfs_create_file("stats", 0444, ++ rocklist.dbgfs_dir, ++ &rocklist, ++ &rk_crypto_debugfs_fops); ++#endif ++} ++ + static int rk_crypto_register(struct rk_crypto_info *crypto_info) + { + unsigned int i, k; +@@ -255,6 +297,9 @@ static const struct of_device_id crypto_of_id_table[] = { + { .compatible = "rockchip,rk3328-crypto", + .data = &rk3328_variant, + }, ++ { .compatible = "rockchip,rk3399-crypto", ++ .data = &rk3399_variant, ++ }, + {} + }; + MODULE_DEVICE_TABLE(of, crypto_of_id_table); +@@ -262,7 +307,7 @@ MODULE_DEVICE_TABLE(of, crypto_of_id_table); + static int rk_crypto_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; +- struct rk_crypto_info *crypto_info; ++ struct rk_crypto_info *crypto_info, *first; + int err = 0; + + crypto_info = devm_kzalloc(&pdev->dev, +@@ -325,22 +370,22 @@ static int rk_crypto_probe(struct platform_device *pdev) + if (err) + goto err_pm; + +- err = rk_crypto_register(crypto_info); +- if (err) { +- dev_err(dev, "err in register alg"); +- goto err_register_alg; +- } ++ spin_lock(&rocklist.lock); ++ first = list_first_entry_or_null(&rocklist.dev_list, ++ struct rk_crypto_info, list); ++ list_add_tail(&crypto_info->list, &rocklist.dev_list); ++ spin_unlock(&rocklist.lock); ++ ++ if (!first) { ++ err = rk_crypto_register(crypto_info); ++ if (err) { ++ dev_err(dev, "Fail to register crypto algorithms"); ++ goto err_register_alg; ++ } + +-#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG +- /* Ignore error of debugfs */ +- crypto_info->dbgfs_dir = debugfs_create_dir("rk3288_crypto", NULL); +- crypto_info->dbgfs_stats = debugfs_create_file("stats", 0444, +- crypto_info->dbgfs_dir, +- crypto_info, +- &rk_crypto_debugfs_fops); +-#endif ++ register_debugfs(crypto_info); ++ } + +- dev_info(dev, "Crypto Accelerator successfully registered\n"); + return 0; + + err_register_alg: +@@ -355,11 +400,20 @@ static int rk_crypto_probe(struct platform_device *pdev) + static int rk_crypto_remove(struct platform_device *pdev) + { + struct rk_crypto_info *crypto_tmp = platform_get_drvdata(pdev); ++ struct rk_crypto_info *first; ++ ++ spin_lock_bh(&rocklist.lock); ++ list_del(&crypto_tmp->list); ++ first = list_first_entry_or_null(&rocklist.dev_list, ++ struct rk_crypto_info, list); ++ spin_unlock_bh(&rocklist.lock); + ++ if (!first) { + #ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG +- debugfs_remove_recursive(crypto_tmp->dbgfs_dir); ++ debugfs_remove_recursive(rocklist.dbgfs_dir); + #endif +- rk_crypto_unregister(); ++ rk_crypto_unregister(); ++ } + rk_crypto_pm_exit(crypto_tmp); + crypto_engine_exit(crypto_tmp->engine); + return 0; +diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h +index ac979d67ced9..b2695258cade 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto.h ++++ b/drivers/crypto/rockchip/rk3288_crypto.h +@@ -190,6 +190,20 @@ + + #define RK_MAX_CLKS 4 + ++/* ++ * struct rockchip_ip - struct for managing a list of RK crypto instance ++ * @dev_list: Used for doing a list of rk_crypto_info ++ * @lock: Control access to dev_list ++ * @dbgfs_dir: Debugfs dentry for statistic directory ++ * @dbgfs_stats: Debugfs dentry for statistic counters ++ */ ++struct rockchip_ip { ++ struct list_head dev_list; ++ spinlock_t lock; /* Control access to dev_list */ ++ struct dentry *dbgfs_dir; ++ struct dentry *dbgfs_stats; ++}; ++ + struct rk_clks { + const char *name; + unsigned long max; +@@ -201,6 +215,7 @@ struct rk_variant { + }; + + struct rk_crypto_info { ++ struct list_head list; + struct device *dev; + struct clk_bulk_data *clks; + int num_clks; +@@ -208,19 +223,15 @@ struct rk_crypto_info { + void __iomem *reg; + int irq; + const struct rk_variant *variant; ++ unsigned long nreq; + struct crypto_engine *engine; + struct completion complete; + int status; +-#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG +- struct dentry *dbgfs_dir; +- struct dentry *dbgfs_stats; +-#endif + }; + + /* the private variable of hash */ + struct rk_ahash_ctx { + struct crypto_engine_ctx enginectx; +- struct rk_crypto_info *dev; + /* for fallback */ + struct crypto_ahash *fallback_tfm; + }; +@@ -236,7 +247,6 @@ struct rk_ahash_rctx { + /* the private variable of cipher */ + struct rk_cipher_ctx { + struct crypto_engine_ctx enginectx; +- struct rk_crypto_info *dev; + unsigned int keylen; + u8 key[AES_MAX_KEY_SIZE]; + u8 iv[AES_BLOCK_SIZE]; +@@ -252,7 +262,7 @@ struct rk_cipher_rctx { + + struct rk_crypto_tmp { + u32 type; +- struct rk_crypto_info *dev; ++ struct rk_crypto_info *dev; + union { + struct skcipher_alg skcipher; + struct ahash_alg hash; +@@ -276,4 +286,5 @@ extern struct rk_crypto_tmp rk_ahash_sha1; + extern struct rk_crypto_tmp rk_ahash_sha256; + extern struct rk_crypto_tmp rk_ahash_md5; + ++struct rk_crypto_info *get_rk_crypto(void); + #endif +diff --git a/drivers/crypto/rockchip/rk3288_crypto_ahash.c b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +index 30f78256c955..a78ff3dcd0b1 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c +@@ -199,8 +199,8 @@ static int rk_ahash_export(struct ahash_request *req, void *out) + static int rk_ahash_digest(struct ahash_request *req) + { + struct rk_ahash_rctx *rctx = ahash_request_ctx(req); +- struct rk_ahash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); +- struct rk_crypto_info *dev = tctx->dev; ++ struct rk_crypto_info *dev; ++ struct crypto_engine *engine; + + if (rk_ahash_need_fallback(req)) + return rk_ahash_digest_fb(req); +@@ -208,9 +208,12 @@ static int rk_ahash_digest(struct ahash_request *req) + if (!req->nbytes) + return zero_message_process(req); + ++ dev = get_rk_crypto(); ++ + rctx->dev = dev; ++ engine = dev->engine; + +- return crypto_transfer_hash_request_to_engine(dev->engine, req); ++ return crypto_transfer_hash_request_to_engine(engine, req); + } + + static void crypto_ahash_dma_start(struct rk_crypto_info *dev, struct scatterlist *sg) +@@ -260,9 +263,14 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + int i; + u32 v; + ++ err = pm_runtime_resume_and_get(rkc->dev); ++ if (err) ++ return err; ++ + rctx->mode = 0; + + algt->stat_req++; ++ rkc->nreq++; + + switch (crypto_ahash_digestsize(tfm)) { + case SHA1_DIGEST_SIZE: +@@ -313,6 +321,8 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + } + + theend: ++ pm_runtime_put_autosuspend(rkc->dev); ++ + local_bh_disable(); + crypto_finalize_hash_request(engine, breq, err); + local_bh_enable(); +@@ -323,21 +333,15 @@ static int rk_hash_run(struct crypto_engine *engine, void *breq) + static int rk_cra_hash_init(struct crypto_tfm *tfm) + { + struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm); +- struct rk_crypto_tmp *algt; +- struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg); +- + const char *alg_name = crypto_tfm_alg_name(tfm); +- int err; +- +- algt = container_of(alg, struct rk_crypto_tmp, alg.hash); +- +- tctx->dev = algt->dev; ++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg); ++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash); + + /* for fallback */ + tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0, + CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(tctx->fallback_tfm)) { +- dev_err(tctx->dev->dev, "Could not load fallback driver.\n"); ++ dev_err(algt->dev->dev, "Could not load fallback driver.\n"); + return PTR_ERR(tctx->fallback_tfm); + } + +@@ -349,15 +353,7 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) + tctx->enginectx.op.prepare_request = rk_hash_prepare; + tctx->enginectx.op.unprepare_request = rk_hash_unprepare; + +- err = pm_runtime_resume_and_get(tctx->dev->dev); +- if (err < 0) +- goto error_pm; +- + return 0; +-error_pm: +- crypto_free_ahash(tctx->fallback_tfm); +- +- return err; + } + + static void rk_cra_hash_exit(struct crypto_tfm *tfm) +@@ -365,7 +361,6 @@ static void rk_cra_hash_exit(struct crypto_tfm *tfm) + struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm); + + crypto_free_ahash(tctx->fallback_tfm); +- pm_runtime_put_autosuspend(tctx->dev->dev); + } + + struct rk_crypto_tmp rk_ahash_sha1 = { +diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +index 0b1c90ababb7..59069457582b 100644 +--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c ++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c +@@ -17,11 +17,11 @@ + static int rk_cipher_need_fallback(struct skcipher_request *req) + { + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- unsigned int bs = crypto_skcipher_blocksize(tfm); + struct skcipher_alg *alg = crypto_skcipher_alg(tfm); + struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); + struct scatterlist *sgs, *sgd; + unsigned int stodo, dtodo, len; ++ unsigned int bs = crypto_skcipher_blocksize(tfm); + + if (!req->cryptlen) + return true; +@@ -84,15 +84,16 @@ static int rk_cipher_fallback(struct skcipher_request *areq) + + static int rk_cipher_handle_req(struct skcipher_request *req) + { +- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); +- struct rk_cipher_ctx *tctx = crypto_skcipher_ctx(tfm); + struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); +- struct rk_crypto_info *rkc = tctx->dev; +- struct crypto_engine *engine = rkc->engine; ++ struct rk_crypto_info *rkc; ++ struct crypto_engine *engine; + + if (rk_cipher_need_fallback(req)) + return rk_cipher_fallback(req); + ++ rkc = get_rk_crypto(); ++ ++ engine = rkc->engine; + rctx->dev = rkc; + + return crypto_transfer_skcipher_request_to_engine(engine, req); +@@ -307,7 +308,12 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); + struct rk_crypto_info *rkc = rctx->dev; + ++ err = pm_runtime_resume_and_get(rkc->dev); ++ if (err) ++ return err; ++ + algt->stat_req++; ++ rkc->nreq++; + + ivsize = crypto_skcipher_ivsize(tfm); + if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) { +@@ -401,6 +407,8 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + } + + theend: ++ pm_runtime_put_autosuspend(rkc->dev); ++ + local_bh_disable(); + crypto_finalize_skcipher_request(engine, areq, err); + local_bh_enable(); +@@ -420,18 +428,13 @@ static int rk_cipher_run(struct crypto_engine *engine, void *async_req) + static int rk_cipher_tfm_init(struct crypto_skcipher *tfm) + { + struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); +- struct skcipher_alg *alg = crypto_skcipher_alg(tfm); + const char *name = crypto_tfm_alg_name(&tfm->base); +- struct rk_crypto_tmp *algt; +- int err; +- +- algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); +- +- ctx->dev = algt->dev; ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher); + + ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->fallback_tfm)) { +- dev_err(ctx->dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n", ++ dev_err(algt->dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n", + name, PTR_ERR(ctx->fallback_tfm)); + return PTR_ERR(ctx->fallback_tfm); + } +@@ -441,14 +444,7 @@ static int rk_cipher_tfm_init(struct crypto_skcipher *tfm) + + ctx->enginectx.op.do_one_request = rk_cipher_run; + +- err = pm_runtime_resume_and_get(ctx->dev->dev); +- if (err < 0) +- goto error_pm; +- + return 0; +-error_pm: +- crypto_free_skcipher(ctx->fallback_tfm); +- return err; + } + + static void rk_cipher_tfm_exit(struct crypto_skcipher *tfm) +@@ -457,7 +453,6 @@ static void rk_cipher_tfm_exit(struct crypto_skcipher *tfm) + + memzero_explicit(ctx->key, ctx->keylen); + crypto_free_skcipher(ctx->fallback_tfm); +- pm_runtime_put_autosuspend(ctx->dev->dev); + } + + struct rk_crypto_tmp rk_ecb_aes_alg = {