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mediatek: sync kernel 6.1 from upstream

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This commit is contained in:
coolsnowwolf 2024-07-04 02:26:54 +08:00
parent 382d2c2e3d
commit c2a01cf771
210 changed files with 16328 additions and 3214 deletions
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32
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso Normal file
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@ -0,0 +1,32 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
fragment@0 {
target = <&gmac1>;
__overlay__ {
phy-mode = "2500base-x";
phy-handle = <&phy5>;
};
};
fragment@1 {
target = <&mdio_bus>;
__overlay__ {
reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
reset-delay-us = <600>;
reset-post-delay-us = <20000>;
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};
};
};

33
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso Normal file
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@ -0,0 +1,33 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
fragment@0 {
target = <&sw_p5>;
__overlay__ {
phy-mode = "2500base-x";
phy-handle = <&phy5>;
status = "okay";
};
};
fragment@1 {
target = <&mdio_bus>;
__overlay__ {
reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
reset-delay-us = <600>;
reset-post-delay-us = <20000>;
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};
};
};

66
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso Normal file
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@ -0,0 +1,66 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
/ {
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
fragment@0 {
target = <&spi0>;
__overlay__ {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spi_nand: spi_nand@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <10000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x0200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
};
};
};
};
};
fragment@1 {
target = <&wifi>;
__overlay__ {
mediatek,mtd-eeprom = <&factory 0x0>;
status = "okay";
};
};
};

188
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts Normal file
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@ -0,0 +1,188 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7981.dtsi"
/ {
model = "MediaTek MT7981 RFB";
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0 0x40000000 0 0x20000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "gmii";
phy-handle = <&int_gbe_phy>;
};
};
&mdio_bus {
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
};
};
&crypto {
status = "okay";
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
cs-gpios = <0>, <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
sw_p5: port@5 {
reg = <5>;
label = "lan5";
status = "disabled";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&xhci {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_phy {
status = "okay";
};
&watchdog {
status = "okay";
};

1424
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
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File diff suppressed because it is too large Load Diff

4
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
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@ -15,8 +15,8 @@
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <10000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";

4
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts
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@ -15,8 +15,8 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;

2
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
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@ -99,7 +99,7 @@
reg = <6>;
};
switch: switch@0 {
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 5 0>;

18
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
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@ -14,9 +14,11 @@
/ {
model = "Bananapi BPI-R4";
compatible = "bananapi,bpi-r4",
"mediatek,mt7988";
"mediatek,mt7988a";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
serial0 = &uart0;
led-boot = &led_green;
led-failsafe = &led_green;
@ -26,7 +28,7 @@
chosen {
stdout-path = &uart0;
bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0";
bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait";
rootdisk-spim-nand = <&ubi_rootfs>;
};
@ -386,6 +388,18 @@
status = "okay";
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_2_lite_pins>;
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2_3_pins>;
};
&watchdog {
status = "okay";
};

4
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso
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@ -19,8 +19,8 @@
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <64>;

4
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
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@ -21,8 +21,8 @@
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <64>;

2
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts
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@ -13,7 +13,7 @@
/ {
model = "MediaTek MT7988A Reference Board";
compatible = "mediatek,mt7988a-rfb",
"mediatek,mt7988";
"mediatek,mt7988a";
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \

1100
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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File diff suppressed because it is too large Load Diff

113
target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c
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@ -1,113 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#define MT7988_PLL_FMAX (2500UL * MHZ)
#define MT7988_PCW_CHG_SHIFT 2
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \
_div_table) \
{ \
.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
.en_mask = _en_mask, .flags = _flags, \
.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \
.pcwbits = _pcwbits, .pd_reg = _pd_reg, \
.pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \
.pcw_chg_reg = _pcw_chg_reg, \
.pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \
.div_table = _div_table, .parent_name = "clkxtal", \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
(HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
0x0154),
PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
(HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
0x0204),
PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
};
static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
{ .compatible = "mediatek,mt7988-apmixedsys", },
{ /* sentinel */ }
};
static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
goto free_apmixed_data;
}
return r;
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
}
static struct platform_driver clk_mt7988_apmixed_drv = {
.probe = clk_mt7988_apmixed_probe,
.driver = {
.name = "clk-mt7988-apmixed",
.of_match_table = of_match_clk_mt7988_apmixed,
},
};
builtin_platform_driver(clk_mt7988_apmixed_drv);
MODULE_LICENSE("GPL");

141
target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c
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@ -1,141 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
static const struct mtk_gate_regs ethdma_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
#define GATE_ETHDMA(_id, _name, _parent, _shift) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &ethdma_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate ethdma_clks[] = {
GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel",
29),
};
static const struct mtk_clk_desc ethdma_desc = {
.clks = ethdma_clks,
.num_clks = ARRAY_SIZE(ethdma_clks),
};
static const struct mtk_gate_regs sgmii0_cg_regs = {
.set_ofs = 0xe4,
.clr_ofs = 0xe4,
.sta_ofs = 0xe4,
};
#define GATE_SGMII0(_id, _name, _parent, _shift) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &sgmii0_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate sgmii0_clks[] = {
GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
};
static const struct mtk_clk_desc sgmii0_desc = {
.clks = sgmii0_clks,
.num_clks = ARRAY_SIZE(sgmii0_clks),
};
static const struct mtk_gate_regs sgmii1_cg_regs = {
.set_ofs = 0xe4,
.clr_ofs = 0xe4,
.sta_ofs = 0xe4,
};
#define GATE_SGMII1(_id, _name, _parent, _shift) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &sgmii1_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate sgmii1_clks[] = {
GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
};
static const struct mtk_clk_desc sgmii1_desc = {
.clks = sgmii1_clks,
.num_clks = ARRAY_SIZE(sgmii1_clks),
};
static const struct mtk_gate_regs ethwarp_cg_regs = {
.set_ofs = 0x14,
.clr_ofs = 0x14,
.sta_ofs = 0x14,
};
#define GATE_ETHWARP(_id, _name, _parent, _shift) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &ethwarp_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate ethwarp_clks[] = {
GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
"netsys_mcu_sel", 13),
GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
"netsys_mcu_sel", 14),
GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
"netsys_mcu_sel", 15),
};
static const struct mtk_clk_desc ethwarp_desc = {
.clks = ethwarp_clks,
.num_clks = ARRAY_SIZE(ethwarp_clks),
};
static const struct of_device_id of_match_clk_mt7986_eth[] = {
{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
{ .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc },
{ .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc },
{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
static struct platform_driver clk_mt7988_eth_drv = {
.driver = {
.name = "clk-mt7988-eth",
.of_match_table = of_match_clk_mt7986_eth,
},
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7988_eth_drv);
MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
MODULE_LICENSE("GPL");

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target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c
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@ -1,376 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
static DEFINE_SPINLOCK(mt7988_clk_lock);
static const char *const infra_mux_uart0_parents[] __initconst = {
"csw_infra_f26m_sel", "uart_sel"
};
static const char *const infra_mux_uart1_parents[] __initconst = {
"csw_infra_f26m_sel", "uart_sel"
};
static const char *const infra_mux_uart2_parents[] __initconst = {
"csw_infra_f26m_sel", "uart_sel"
};
static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel",
"spi_sel" };
static const char *const infra_mux_spi1_parents[] __initconst = {
"i2c_sel", "spim_mst_sel"
};
static const char *const infra_pwm_bck_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
"pextp_tl_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
"pextp_tl_p1_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
"pextp_tl_p2_sel"
};
static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
"pextp_tl_p3_sel"
};
static const struct mtk_mux infra_muxes[] = {
/* MODULE_CLK_SEL_0 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
0, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014,
1, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014,
2, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
2, -1, -1, -1),
/* MODULE_CLK_SEL_1 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
"infra_pcie_gfmux_tl_o_p0_sel",
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
0x0020, 0x0024, 0, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
"infra_pcie_gfmux_tl_o_p1_sel",
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
0x0020, 0x0024, 2, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
"infra_pcie_gfmux_tl_o_p2_sel",
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
0x0020, 0x0024, 4, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
"infra_pcie_gfmux_tl_o_p3_sel",
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
0x0020, 0x0024, 6, 2, -1, -1, -1),
};
static const struct mtk_gate_regs infra0_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x14,
.sta_ofs = 0x18,
};
static const struct mtk_gate_regs infra1_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
.sta_ofs = 0x48,
};
static const struct mtk_gate_regs infra2_cg_regs = {
.set_ofs = 0x50,
.clr_ofs = 0x54,
.sta_ofs = 0x58,
};
static const struct mtk_gate_regs infra3_cg_regs = {
.set_ofs = 0x60,
.clr_ofs = 0x64,
.sta_ofs = 0x68,
};
#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &infra0_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
}
#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &infra1_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
}
#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &infra2_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
}
#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = &infra3_cg_regs, .shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
}
#define GATE_INFRA0(_id, _name, _parent, _shift) \
GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA1(_id, _name, _parent, _shift) \
GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA2(_id, _name, _parent, _shift) \
GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA3(_id, _name, _parent, _shift) \
GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) { \
.id = _id, .name = _name, .parent_name = _parent, \
.regs = _regs, .shift = _shift, \
.flags = CLK_IS_CRITICAL, \
.ops = &mtk_clk_gate_ops_setclr, \
}
static const struct mtk_gate infra_clks[] = {
/* INFRA0 */
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0,
"infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7),
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1,
"infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8),
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2,
"infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9),
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3,
"infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10),
/* INFRA1 */
GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
"sysaxi_sel", 0),
GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
"sysaxi_sel", 1),
GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
"infra_pwm_sel", 2),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
"infra_pwm_ck1_sel", 3),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
"infra_pwm_ck2_sel", 4),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
"infra_pwm_ck3_sel", 5),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
"infra_pwm_ck4_sel", 6),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
"infra_pwm_ck5_sel", 7),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
"infra_pwm_ck6_sel", 8),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
"infra_pwm_ck7_sel", 9),
GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
"infra_pwm_ck8_sel", 10),
GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
"sysaxi_sel", 12),
GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
"sysaxi_sel", 13),
GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m",
"csw_infra_f26m_sel", 14),
GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
"csw_infra_f26m_sel", 19, CLK_IS_CRITICAL),
// JTAG
GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
"sysaxi_sel", 20, CLK_IS_CRITICAL),
GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
"sysaxi_sel", 21),
GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
"sysaxi_sel", 29),
GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
"csw_infra_f26m_sel", 30),
/* INFRA2 */
GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
"csw_infra_f26m_sel", 0),
GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
"infra_mux_uart0_sel", 3),
GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
"infra_mux_uart1_sel", 4),
GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
"infra_mux_uart2_sel", 5),
GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
"sysaxi_sel", 11, CLK_IS_CRITICAL),
GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
"infra_mux_spi0_sel", 12, CLK_IS_CRITICAL),
GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
"infra_mux_spi1_sel", 13),
GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
"infra_mux_spi2_sel", 14),
GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
"sysaxi_sel", 15, CLK_IS_CRITICAL),
GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
"sysaxi_sel", 16),
GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
"sysaxi_sel", 17),
GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
"sysaxi_sel", 18),
GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19),
GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
"csw_infra_f26m_sel", 20),
GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
21),
GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel",
22),
GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel",
23),
GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
"sysaxi_sel", 24),
GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
"sysaxi_sel", 25),
GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
"sysaxi_sel", 26),
GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1,
"infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1,
"infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
/* INFRA3 */
GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel",
0),
GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
"sysaxi_sel", 1),
GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel",
2),
GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
"sysaxi_sel", 3),
GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
"usb_sys_p1_sel", 5),
GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
"usb_frmcnt_sel", 8, CLK_IS_CRITICAL),
GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
"usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL),
GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
"usb_phy_sel", 11),
GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
"top_xtal", 13),
GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
"usb_xhci_p1_sel", 15),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
"infra_pcie_gfmux_tl_o_p0_sel", 20),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
"infra_pcie_gfmux_tl_o_p1_sel", 21),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
"infra_pcie_gfmux_tl_o_p2_sel", 22),
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
"infra_pcie_gfmux_tl_o_p3_sel", 23),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
"top_xtal", 24),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
"top_xtal", 25),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
"top_xtal", 26),
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
"top_xtal", 27),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
"sysaxi_sel", 28),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
"sysaxi_sel", 29),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
"sysaxi_sel", 30),
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
"sysaxi_sel", 31),
};
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.mux_clks = infra_muxes,
.num_mux_clks = ARRAY_SIZE(infra_muxes),
.clk_lock = &mt7988_clk_lock,
};
static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
static struct platform_driver clk_mt7988_infracfg_drv = {
.driver = {
.name = "clk-mt7988-infracfg",
.of_match_table = of_match_clk_mt7988_infracfg,
},
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7988_infracfg_drv);

446
target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c
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@ -1,446 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
static DEFINE_SPINLOCK(mt7988_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
};
static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2",
"mmpll_d2" };
static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5",
"net1pll_d5_d2" };
static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll",
"mmpll" };
static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4",
"net1pll_d5" };
static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll",
"mmpll", "net1pll_d4",
"net1pll_d5", "mpll" };
static const char *const eip197_parents[] = { "top_xtal", "netsyspll",
"net2pll", "mmpll",
"net1pll_d4", "net1pll_d5" };
static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
static const char *const uart_parents[] = { "top_xtal", "mpll_d8",
"mpll_d8_d2" };
static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2",
"mmpll_d4" };
static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",
"mmpll_d2", "mpll_d2",
"mmpll_d4", "net1pll_d8_d2" };
static const char *const spi_parents[] = { "top_xtal", "mpll_d2",
"mmpll_d4", "net1pll_d8_d2",
"net2pll_d6", "net1pll_d5_d4",
"mpll_d4", "net1pll_d8_d4" };
static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4",
"net1pll_d8_d2", "net2pll_d6",
"mpll_d4", "mmpll_d8",
"net1pll_d8_d4", "mpll_d8" };
static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal",
"net1pll_d5_d4", "mpll_d4",
"mmpll_d8", "net1pll_d8_d4",
"mmpll_d6_d2", "mpll_d8" };
static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2",
"net1pll_d5_d4", "mpll_d4",
"mpll_d8_d2", "top_rtc_32k" };
static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4",
"mpll_d4", "net1pll_d8_d4" };
static const char *const pcie_mbist_250m_parents[] = { "top_xtal",
"net1pll_d5_d2" };
static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6",
"mmpll_d8", "mpll_d8_d2",
"top_rtc_32k" };
static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
static const char *const aud_parents[] = { "top_xtal", "apll2" };
static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
static const char *const aud_l_parents[] = { "top_xtal", "apll2",
"mpll_d8_d2" };
static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
static const char *const usxgmii_sbus_0_parents[] = { "top_xtal",
"net1pll_d8_d4" };
static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
static const char *const eth_refck_50m_parents[] = { "top_xtal",
"net2pll_d4_d4" };
static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
static const char *const eth_xgmii_parents[] = { "top_xtal_d2",
"net1pll_d8_d8",
"net1pll_d8_d16" };
static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5",
"net2pll_d2" };
static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2",
"wedmcupll" };
static const char *const da_xtp_glb_p0_parents[] = { "top_xtal",
"net2pll_d8" };
static const char *const mcusys_backup_625m_parents[] = { "top_xtal",
"net1pll_d4" };
static const char *const macsec_parents[] = { "top_xtal", "sgmpll",
"net1pll_d8" };
static const char *const netsys_tops_400m_parents[] = { "top_xtal",
"net2pll_d2" };
static const char *const eth_mii_parents[] = { "top_xtal_d2",
"net2pll_d4_d8" };
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2,
15, 0x1C0, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
0x1C0, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2,
31, 0x1C0, 3),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
0x1C0, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
0x1C0, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3,
23, 0x1C0, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
axi_infra_parents, 0x020, 0x024, 0x028, 0,
1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
0x024, 0x028, 8, 2, 15, 0x1c0, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
0x1C0, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
0x1C0, 11),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
0x034, 0x038, 0, 3, 7, 0x1c0, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
0x044, 0x048, 0, 3, 7, 0x1c0, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
0x044, 0x048, 8, 2, 15, 0x1c0, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL,
"pcie_mbist_250m_sel", pcie_mbist_250m_parents,
0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel",
pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
31, 0x1C0, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel",
pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
0x1C0, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel",
pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3,
15, 0x1C0, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel",
pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
23, 0x1C0, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel",
eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
0x1C0, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
0x1C0, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
0x1C0, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
0x1C0, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1,
31, 0x1C0, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
0x1C0, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
0x074, 0x078, 8, 1, 15, 0x1c0, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel",
sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23,
0x1c4, 3),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24,
1, 31, 0x1C4, 4),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
7, 0x1C4, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
usxgmii_sbus_0_parents, 0x090, 0x094, 0x098,
16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8,
0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15,
0x1C4, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23,
0x1C4, 11),
/* CLK_CFG_11 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24,
1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1,
7, 0x1c4, 13, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1,
15, 0x1C4, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1,
23, 0x1C4, 15),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel",
pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24,
1, 31, 0x1C4, 16),
/* CLK_CFG_12 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
0x1C4, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15,
0x1C4, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23,
0x1C4, 19),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1,
31, 0x1C4, 20, CLK_IS_CRITICAL),
/* CLK_CFG_13 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0,
2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(
CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23,
0x1C4, 23),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31,
0x1C4, 24),
/* CLK_CFG_14 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7,
0x1C4, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15,
0x1C4, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1,
23, 0x1C4, 27),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1,
31, 0x1C4, 28),
/* CLK_CFG_15 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1,
7, 0x1C4, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1,
15, 0x1C4, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0,
0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1),
/* CLK_CFG_16 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
0x1C8, 3),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL,
"mcusys_backup_625m_sel",
mcusys_backup_625m_parents, 0x0100, 0x104, 0x108,
16, 1, 23, 0x1C8, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL,
"netsys_sync_250m_sel", pcie_mbist_250m_parents,
0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
/* CLK_CFG_17 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL,
"netsys_tops_400m_sel", netsys_tops_400m_parents,
0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL,
"netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
0x1C8, 9),
/* CLK_CFG_18 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel",
eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7,
0x1c8, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents,
0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
};
static const struct mtk_composite top_aud_divs[] = {
DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420,
8, 8),
};
static const struct mtk_clk_desc topck_desc = {
.fixed_clks = top_fixed_clks,
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
.composite_clks = top_aud_divs,
.num_composite_clks = ARRAY_SIZE(top_aud_divs),
.clk_lock = &mt7988_clk_lock,
};
static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
"net1pll_d4" };
static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b",
"net1pll_d4" };
static struct mtk_composite mcu_muxes[] = {
/* bus_pll_divider_cfg */
MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
/* mp2_pll_divider_cfg */
MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
};
static const struct mtk_clk_desc mcusys_desc = {
.composite_clks = mcu_muxes,
.num_composite_clks = ARRAY_SIZE(mcu_muxes),
};
static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
static struct platform_driver clk_mt7988_topckgen_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7988-topckgen",
.of_match_table = of_match_clk_mt7988_topckgen,
},
};
module_platform_driver(clk_mt7988_topckgen_drv);
MODULE_LICENSE("GPL");

214
target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c
View File

@ -7,37 +7,50 @@
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/phy.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin"
#define MD32_EN_CFG 0x18
#define MD32_EN BIT(0)
#define MD32_EN BIT(0)
#define PMEM_PRIORITY BIT(8)
#define DMEM_PRIORITY BIT(16)
#define BASE100T_STATUS_EXTEND 0x10
#define BASE1000T_STATUS_EXTEND 0x11
#define EXTEND_CTRL_AND_STATUS 0x16
#define BASE100T_STATUS_EXTEND 0x10
#define BASE1000T_STATUS_EXTEND 0x11
#define EXTEND_CTRL_AND_STATUS 0x16
#define PHY_AUX_CTRL_STATUS 0x1d
#define PHY_AUX_DPX_MASK GENMASK(5, 5)
#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
#define PHY_AUX_CTRL_STATUS 0x1d
#define PHY_AUX_DPX_MASK GENMASK(5, 5)
#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
/* Registers on MDIO_MMD_VEND1 */
#define MTK_PHY_LINK_STATUS_MISC 0xa2
#define MTK_PHY_FDX_ENABLE BIT(5)
#define MTK_PHY_LINK_STATUS_MISC 0xa2
#define MTK_PHY_FDX_ENABLE BIT(5)
#define MTK_PHY_LPI_PCS_DSP_CTRL 0x121
#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8)
/* Registers on MDIO_MMD_VEND2 */
#define MTK_PHY_LED0_ON_CTRL 0x24
#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
#define MTK_PHY_LED0_ON_LINK100 BIT(1)
#define MTK_PHY_LED0_ON_LINK10 BIT(2)
#define MTK_PHY_LED0_ON_LINK2500 BIT(7)
#define MTK_PHY_LED0_POLARITY BIT(14)
#define MTK_PHY_LED0_ON_CTRL 0x24
#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
#define MTK_PHY_LED0_ON_LINK100 BIT(1)
#define MTK_PHY_LED0_ON_LINK10 BIT(2)
#define MTK_PHY_LED0_ON_LINK2500 BIT(7)
#define MTK_PHY_LED0_POLARITY BIT(14)
#define MTK_PHY_LED1_ON_CTRL 0x26
#define MTK_PHY_LED1_ON_FDX BIT(4)
#define MTK_PHY_LED1_ON_HDX BIT(5)
#define MTK_PHY_LED1_POLARITY BIT(14)
#define MTK_PHY_LED1_ON_CTRL 0x26
#define MTK_PHY_LED1_ON_FDX BIT(4)
#define MTK_PHY_LED1_ON_HDX BIT(5)
#define MTK_PHY_LED1_POLARITY BIT(14)
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
struct mtk_i2p5ge_phy_priv {
bool fw_loaded;
};
enum {
PHY_AUX_SPD_10 = 0,
@ -46,67 +59,89 @@ enum {
PHY_AUX_SPD_2500,
};
static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
static int mtk_2p5ge_phy_read_page(struct phy_device *phydev)
{
int ret;
int i;
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
}
static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page)
{
return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
}
static int mt7988_2p5ge_phy_probe(struct phy_device *phydev)
{
struct mtk_i2p5ge_phy_priv *phy_priv;
phy_priv = devm_kzalloc(&phydev->mdio.dev,
sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL);
if (!phy_priv)
return -ENOMEM;
phydev->priv = phy_priv;
return 0;
}
static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev)
{
int ret, i;
const struct firmware *fw;
struct device *dev = &phydev->mdio.dev;
struct device_node *np;
void __iomem *dmb_addr;
void __iomem *pmb_addr;
void __iomem *mcucsr_base;
void __iomem *md32_en_cfg_base;
struct mtk_i2p5ge_phy_priv *phy_priv = phydev->priv;
u16 reg;
struct pinctrl *pinctrl;
np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
if (!np)
return -ENOENT;
if (!phy_priv->fw_loaded) {
np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
if (!np)
return -ENOENT;
pmb_addr = of_iomap(np, 0);
if (!pmb_addr)
return -ENOMEM;
md32_en_cfg_base = of_iomap(np, 1);
if (!md32_en_cfg_base)
return -ENOMEM;
dmb_addr = of_iomap(np, 0);
if (!dmb_addr)
return -ENOMEM;
pmb_addr = of_iomap(np, 1);
if (!pmb_addr)
return -ENOMEM;
mcucsr_base = of_iomap(np, 2);
if (!mcucsr_base)
return -ENOMEM;
ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev);
if (ret) {
dev_err(dev, "failed to load firmware: %s, ret: %d\n",
MT7988_2P5GE_PMB, ret);
return ret;
}
ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev);
if (ret) {
dev_err(dev, "failed to load firmware: %s, ret: %d\n",
MEDAITEK_2P5GE_PHY_DMB_FW, ret);
return ret;
reg = readw(md32_en_cfg_base);
if (reg & MD32_EN) {
phy_set_bits(phydev, 0, BIT(15));
usleep_range(10000, 11000);
}
phy_set_bits(phydev, 0, BIT(11));
/* Write magic number to safely stall MCU */
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
for (i = 0; i < fw->size - 1; i += 4)
writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
release_firmware(fw);
writew(reg & ~MD32_EN, md32_en_cfg_base);
writew(reg | MD32_EN, md32_en_cfg_base);
phy_set_bits(phydev, 0, BIT(15));
dev_info(dev, "Firmware loading/trigger ok.\n");
phy_priv->fw_loaded = true;
}
for (i = 0; i < fw->size - 1; i += 4)
writel(*((uint32_t *)(fw->data + i)), dmb_addr + i);
release_firmware(fw);
ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev);
if (ret) {
dev_err(dev, "failed to load firmware: %s, ret: %d\n",
MEDIATEK_2P5GE_PHY_PMB_FW, ret);
return ret;
}
for (i = 0; i < fw->size - 1; i += 4)
writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
release_firmware(fw);
reg = readw(mcucsr_base + MD32_EN_CFG);
writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
dev_dbg(dev, "Firmware loading/trigger ok.\n");
/* Setup LED */
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED0_POLARITY);
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED0_ON_LINK10 |
MTK_PHY_LED0_ON_LINK100 |
MTK_PHY_LED0_ON_LINK1000 |
MTK_PHY_LED0_ON_LINK2500);
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
@ -116,10 +151,20 @@ static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
return PTR_ERR(pinctrl);
}
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
/* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
__phy_write(phydev, 0x11, 0xfbfa);
__phy_write(phydev, 0x12, 0xc3);
__phy_write(phydev, 0x10, 0x87f8);
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
return 0;
}
static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev)
{
bool changed = false;
u32 adv;
@ -152,7 +197,7 @@ static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
return genphy_c45_check_and_restart_aneg(phydev, changed);
}
static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev)
{
int ret;
@ -160,7 +205,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
if (ret)
return ret;
/* We don't support HDX at MAC layer on mt798x.
/* We don't support HDX at MAC layer on mt7988.
* So mask phy's HDX capabilities, too.
*/
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
@ -176,7 +221,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
return 0;
}
static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev)
{
int ret;
@ -189,9 +234,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
phydev->pause = 0;
phydev->asym_pause = 0;
if (!phydev->link)
return 0;
if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
ret = genphy_c45_read_lpa(phydev);
if (ret < 0)
@ -222,7 +264,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
break;
case PHY_AUX_SPD_2500:
phydev->speed = SPEED_2500;
phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
break;
}
@ -231,18 +272,32 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
return ret;
phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
/* FIXME: The current firmware always enables rate adaptation mode. */
phydev->rate_matching = RATE_MATCH_PAUSE;
return 0;
}
static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
phy_interface_t iface)
{
return RATE_MATCH_PAUSE;
}
static struct phy_driver mtk_gephy_driver[] = {
{
PHY_ID_MATCH_EXACT(0x00339c11),
PHY_ID_MATCH_MODEL(0x00339c11),
.name = "MediaTek MT798x 2.5GbE PHY",
.config_init = mt798x_2p5ge_phy_config_init,
.config_aneg = mt798x_2p5ge_phy_config_aneg,
.get_features = mt798x_2p5ge_phy_get_features,
.read_status = mt798x_2p5ge_phy_read_status,
.probe = mt7988_2p5ge_phy_probe,
.config_init = mt7988_2p5ge_phy_config_init,
.config_aneg = mt7988_2p5ge_phy_config_aneg,
.get_features = mt7988_2p5ge_phy_get_features,
.read_status = mt7988_2p5ge_phy_read_status,
.get_rate_matching = mt7988_2p5ge_phy_get_rate_matching,
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_page = mtk_2p5ge_phy_read_page,
.write_page = mtk_2p5ge_phy_write_page,
},
};
@ -258,5 +313,4 @@ MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW);
MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW);
MODULE_FIRMWARE(MT7988_2P5GE_PMB);

59
target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
View File

@ -596,6 +596,51 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
};
static const unsigned int mt7988_pull_type[] = {
MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/
MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/
MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/
MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/
MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/
MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/
MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/
MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/
MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/
MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/
MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/
};
static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
@ -992,11 +1037,11 @@ static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
static int mt7988_uart1_2_lite_pins[] = { 80, 81 };
static int mt7988_uart1_2_lite_funcs[] = { 1, 1 };
static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
static int mt7988_tops_uart1_2_funcs[] = {
4,
4,
};
static int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
@ -1254,6 +1299,8 @@ static const struct group_desc mt7988_groups[] = {
PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
/* @GPIO(80,81,82,83) uart1_2 */
PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
/* @GPIO(80,81) uart1_2_lite */
PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite),
/* @GPIO(80) pwm2 */
PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
/* @GPIO(81) pwm3 */
@ -1363,6 +1410,7 @@ static const char * const mt7988_uart_groups[] = {
"uart1_1",
"uart2_3",
"uart1_2",
"uart1_2_lite",
"tops_uart1_2",
"net_wo0_uart_txd_1",
"net_wo1_uart_txd_1",
@ -1433,6 +1481,9 @@ static struct mtk_pin_soc mt7988_data = {
.bias_disable_get = mtk_pinconf_bias_disable_get,
.bias_set = mtk_pinconf_bias_set,
.bias_get = mtk_pinconf_bias_get,
.pull_type = mt7988_pull_type,
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_pull_get = mtk_pinconf_adv_pull_get,

276
target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h
View File

@ -1,276 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
*/
#ifndef _DT_BINDINGS_CLK_MT7988_H
#define _DT_BINDINGS_CLK_MT7988_H
/* APMIXEDSYS */
#define CLK_APMIXED_NETSYSPLL 0
#define CLK_APMIXED_MPLL 1
#define CLK_APMIXED_MMPLL 2
#define CLK_APMIXED_APLL2 3
#define CLK_APMIXED_NET1PLL 4
#define CLK_APMIXED_NET2PLL 5
#define CLK_APMIXED_WEDMCUPLL 6
#define CLK_APMIXED_SGMPLL 7
#define CLK_APMIXED_ARM_B 8
#define CLK_APMIXED_CCIPLL2_B 9
#define CLK_APMIXED_USXGMIIPLL 10
#define CLK_APMIXED_MSDCPLL 11
/* TOPCKGEN */
#define CLK_TOP_XTAL 0
#define CLK_TOP_XTAL_D2 1
#define CLK_TOP_RTC_32K 2
#define CLK_TOP_RTC_32P7K 3
#define CLK_TOP_MPLL_D2 4
#define CLK_TOP_MPLL_D3_D2 5
#define CLK_TOP_MPLL_D4 6
#define CLK_TOP_MPLL_D8 7
#define CLK_TOP_MPLL_D8_D2 8
#define CLK_TOP_MMPLL_D2 9
#define CLK_TOP_MMPLL_D3_D5 10
#define CLK_TOP_MMPLL_D4 11
#define CLK_TOP_MMPLL_D6_D2 12
#define CLK_TOP_MMPLL_D8 13
#define CLK_TOP_APLL2_D4 14
#define CLK_TOP_NET1PLL_D4 15
#define CLK_TOP_NET1PLL_D5 16
#define CLK_TOP_NET1PLL_D5_D2 17
#define CLK_TOP_NET1PLL_D5_D4 18
#define CLK_TOP_NET1PLL_D8 19
#define CLK_TOP_NET1PLL_D8_D2 20
#define CLK_TOP_NET1PLL_D8_D4 21
#define CLK_TOP_NET1PLL_D8_D8 22
#define CLK_TOP_NET1PLL_D8_D16 23
#define CLK_TOP_NET2PLL_D2 24
#define CLK_TOP_NET2PLL_D4 25
#define CLK_TOP_NET2PLL_D4_D4 26
#define CLK_TOP_NET2PLL_D4_D8 27
#define CLK_TOP_NET2PLL_D6 28
#define CLK_TOP_NET2PLL_D8 29
#define CLK_TOP_NETSYS_SEL 30
#define CLK_TOP_NETSYS_500M_SEL 31
#define CLK_TOP_NETSYS_2X_SEL 32
#define CLK_TOP_NETSYS_GSW_SEL 33
#define CLK_TOP_ETH_GMII_SEL 34
#define CLK_TOP_NETSYS_MCU_SEL 35
#define CLK_TOP_NETSYS_PAO_2X_SEL 36
#define CLK_TOP_EIP197_SEL 37
#define CLK_TOP_AXI_INFRA_SEL 38
#define CLK_TOP_UART_SEL 39
#define CLK_TOP_EMMC_250M_SEL 40
#define CLK_TOP_EMMC_400M_SEL 41
#define CLK_TOP_SPI_SEL 42
#define CLK_TOP_SPIM_MST_SEL 43
#define CLK_TOP_NFI1X_SEL 44
#define CLK_TOP_SPINFI_SEL 45
#define CLK_TOP_PWM_SEL 46
#define CLK_TOP_I2C_SEL 47
#define CLK_TOP_PCIE_MBIST_250M_SEL 48
#define CLK_TOP_PEXTP_TL_SEL 49
#define CLK_TOP_PEXTP_TL_P1_SEL 50
#define CLK_TOP_PEXTP_TL_P2_SEL 51
#define CLK_TOP_PEXTP_TL_P3_SEL 52
#define CLK_TOP_USB_SYS_SEL 53
#define CLK_TOP_USB_SYS_P1_SEL 54
#define CLK_TOP_USB_XHCI_SEL 55
#define CLK_TOP_USB_XHCI_P1_SEL 56
#define CLK_TOP_USB_FRMCNT_SEL 57
#define CLK_TOP_USB_FRMCNT_P1_SEL 58
#define CLK_TOP_AUD_SEL 59
#define CLK_TOP_A1SYS_SEL 60
#define CLK_TOP_AUD_L_SEL 61
#define CLK_TOP_A_TUNER_SEL 62
#define CLK_TOP_SSPXTP_SEL 63
#define CLK_TOP_USB_PHY_SEL 64
#define CLK_TOP_USXGMII_SBUS_0_SEL 65
#define CLK_TOP_USXGMII_SBUS_1_SEL 66
#define CLK_TOP_SGM_0_SEL 67
#define CLK_TOP_SGM_SBUS_0_SEL 68
#define CLK_TOP_SGM_1_SEL 69
#define CLK_TOP_SGM_SBUS_1_SEL 70
#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
#define CLK_TOP_SYSAXI_SEL 73
#define CLK_TOP_SYSAPB_SEL 74
#define CLK_TOP_ETH_REFCK_50M_SEL 75
#define CLK_TOP_ETH_SYS_200M_SEL 76
#define CLK_TOP_ETH_SYS_SEL 77
#define CLK_TOP_ETH_XGMII_SEL 78
#define CLK_TOP_BUS_TOPS_SEL 79
#define CLK_TOP_NPU_TOPS_SEL 80
#define CLK_TOP_DRAMC_SEL 81
#define CLK_TOP_DRAMC_MD32_SEL 82
#define CLK_TOP_INFRA_F26M_SEL 83
#define CLK_TOP_PEXTP_P0_SEL 84
#define CLK_TOP_PEXTP_P1_SEL 85
#define CLK_TOP_PEXTP_P2_SEL 86
#define CLK_TOP_PEXTP_P3_SEL 87
#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
#define CLK_TOP_CKM_SEL 92
#define CLK_TOP_DA_SEL 93
#define CLK_TOP_PEXTP_SEL 94
#define CLK_TOP_TOPS_P2_26M_SEL 95
#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
#define CLK_TOP_MACSEC_SEL 98
#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
#define CLK_TOP_NETSYS_WARP_SEL 101
#define CLK_TOP_ETH_MII_SEL 102
#define CLK_TOP_NPU_SEL 103
#define CLK_TOP_AUD_I2S_M 104
/* MCUSYS */
#define CLK_MCU_BUS_DIV_SEL 0
#define CLK_MCU_ARM_DIV_SEL 1
/* INFRACFG_AO */
#define CLK_INFRA_MUX_UART0_SEL 0
#define CLK_INFRA_MUX_UART1_SEL 1
#define CLK_INFRA_MUX_UART2_SEL 2
#define CLK_INFRA_MUX_SPI0_SEL 3
#define CLK_INFRA_MUX_SPI1_SEL 4
#define CLK_INFRA_MUX_SPI2_SEL 5
#define CLK_INFRA_PWM_SEL 6
#define CLK_INFRA_PWM_CK1_SEL 7
#define CLK_INFRA_PWM_CK2_SEL 8
#define CLK_INFRA_PWM_CK3_SEL 9
#define CLK_INFRA_PWM_CK4_SEL 10
#define CLK_INFRA_PWM_CK5_SEL 11
#define CLK_INFRA_PWM_CK6_SEL 12
#define CLK_INFRA_PWM_CK7_SEL 13
#define CLK_INFRA_PWM_CK8_SEL 14
#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
/* INFRACFG */
#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
#define CLK_INFRA_66M_GPT_BCK 23
#define CLK_INFRA_66M_PWM_HCK 24
#define CLK_INFRA_66M_PWM_BCK 25
#define CLK_INFRA_66M_PWM_CK1 26
#define CLK_INFRA_66M_PWM_CK2 27
#define CLK_INFRA_66M_PWM_CK3 28
#define CLK_INFRA_66M_PWM_CK4 29
#define CLK_INFRA_66M_PWM_CK5 30
#define CLK_INFRA_66M_PWM_CK6 31
#define CLK_INFRA_66M_PWM_CK7 32
#define CLK_INFRA_66M_PWM_CK8 33
#define CLK_INFRA_133M_CQDMA_BCK 34
#define CLK_INFRA_66M_AUD_SLV_BCK 35
#define CLK_INFRA_AUD_26M 36
#define CLK_INFRA_AUD_L 37
#define CLK_INFRA_AUD_AUD 38
#define CLK_INFRA_AUD_EG2 39
#define CLK_INFRA_DRAMC_F26M 40
#define CLK_INFRA_133M_DBG_ACKM 41
#define CLK_INFRA_66M_AP_DMA_BCK 42
#define CLK_INFRA_66M_SEJ_BCK 43
#define CLK_INFRA_PRE_CK_SEJ_F13M 44
#define CLK_INFRA_26M_THERM_SYSTEM 45
#define CLK_INFRA_I2C_BCK 46
#define CLK_INFRA_52M_UART0_CK 47
#define CLK_INFRA_52M_UART1_CK 48
#define CLK_INFRA_52M_UART2_CK 49
#define CLK_INFRA_NFI 50
#define CLK_INFRA_SPINFI 51
#define CLK_INFRA_66M_NFI_HCK 52
#define CLK_INFRA_104M_SPI0 53
#define CLK_INFRA_104M_SPI1 54
#define CLK_INFRA_104M_SPI2_BCK 55
#define CLK_INFRA_66M_SPI0_HCK 56
#define CLK_INFRA_66M_SPI1_HCK 57
#define CLK_INFRA_66M_SPI2_HCK 58
#define CLK_INFRA_66M_FLASHIF_AXI 59
#define CLK_INFRA_RTC 60
#define CLK_INFRA_26M_ADC_BCK 61
#define CLK_INFRA_RC_ADC 62
#define CLK_INFRA_MSDC400 63
#define CLK_INFRA_MSDC2_HCK 64
#define CLK_INFRA_133M_MSDC_0_HCK 65
#define CLK_INFRA_66M_MSDC_0_HCK 66
#define CLK_INFRA_133M_CPUM_BCK 67
#define CLK_INFRA_BIST2FPC 68
#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
#define CLK_INFRA_133M_USB_HCK 71
#define CLK_INFRA_133M_USB_HCK_CK_P1 72
#define CLK_INFRA_66M_USB_HCK 73
#define CLK_INFRA_66M_USB_HCK_CK_P1 74
#define CLK_INFRA_USB_SYS 75
#define CLK_INFRA_USB_SYS_CK_P1 76
#define CLK_INFRA_USB_REF 77
#define CLK_INFRA_USB_CK_P1 78
#define CLK_INFRA_USB_FRMCNT 79
#define CLK_INFRA_USB_FRMCNT_CK_P1 80
#define CLK_INFRA_USB_PIPE 81
#define CLK_INFRA_USB_PIPE_CK_P1 82
#define CLK_INFRA_USB_UTMI 83
#define CLK_INFRA_USB_UTMI_CK_P1 84
#define CLK_INFRA_USB_XHCI 85
#define CLK_INFRA_USB_XHCI_CK_P1 86
#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
#define CLK_INFRA_PCIE_PIPE_P0 91
#define CLK_INFRA_PCIE_PIPE_P1 92
#define CLK_INFRA_PCIE_PIPE_P2 93
#define CLK_INFRA_PCIE_PIPE_P3 94
#define CLK_INFRA_133M_PCIE_CK_P0 95
#define CLK_INFRA_133M_PCIE_CK_P1 96
#define CLK_INFRA_133M_PCIE_CK_P2 97
#define CLK_INFRA_133M_PCIE_CK_P3 98
/* ETHDMA */
#define CLK_ETHDMA_XGP1_EN 0
#define CLK_ETHDMA_XGP2_EN 1
#define CLK_ETHDMA_XGP3_EN 2
#define CLK_ETHDMA_FE_EN 3
#define CLK_ETHDMA_GP2_EN 4
#define CLK_ETHDMA_GP1_EN 5
#define CLK_ETHDMA_GP3_EN 6
#define CLK_ETHDMA_ESW_EN 7
#define CLK_ETHDMA_CRYPT0_EN 8
#define CLK_ETHDMA_NR_CLK 9
/* SGMIISYS_0 */
#define CLK_SGM0_TX_EN 0
#define CLK_SGM0_RX_EN 1
#define CLK_SGMII0_NR_CLK 2
/* SGMIISYS_1 */
#define CLK_SGM1_TX_EN 0
#define CLK_SGM1_RX_EN 1
#define CLK_SGMII1_NR_CLK 2
/* ETHWARP */
#define CLK_ETHWARP_WOCPU2_EN 0
#define CLK_ETHWARP_WOCPU1_EN 1
#define CLK_ETHWARP_WOCPU0_EN 2
#define CLK_ETHWARP_NR_CLK 3
#endif /* _DT_BINDINGS_CLK_MT7988_H */

15
target/linux/mediatek/files/block/partitions/fit.c
View File

@ -73,11 +73,7 @@
int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector, u64 sectors, int *slot, int add_remain)
{
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)
struct block_device *bdev = state->disk->part0;
#else
struct block_device *bdev = state->bdev;
#endif
struct address_space *mapping = bdev->bd_inode->i_mapping;
struct page *page;
void *fit, *init_fit;
@ -104,8 +100,11 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
return -ERANGE;
page = read_mapping_page(mapping, fit_start_sector >> (PAGE_SHIFT - SECTOR_SHIFT), NULL);
if (!page)
return -ENOMEM;
if (IS_ERR(page))
return -EFAULT;
if (PageError(page))
return -EFAULT;
init_fit = page_address(page);
@ -224,8 +223,8 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
image_description = fdt_getprop(fit, node, FIT_DESC_PROP, &image_description_len);
printk(KERN_DEBUG "FIT: %16s sub-image 0x%08x - 0x%08x \"%s\" %s%s%s\n",
image_type, image_pos, image_pos + image_len, image_name,
printk(KERN_DEBUG "FIT: %16s sub-image 0x%08x..0x%08x \"%s\" %s%s%s\n",
image_type, image_pos, image_pos + image_len - 1, image_name,
image_description?"(":"", image_description?:"", image_description?") ":"");
if (strcmp(image_type, FIT_FILESYSTEM_PROP))

13
target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c
View File

@ -7,6 +7,7 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/version.h>
/**
* Driver for SmartRG RGBW LED microcontroller.
@ -159,7 +160,11 @@ srg_led_init_led(struct srg_led_ctrl *sysled_ctrl, struct device_node *np)
static int
#if LINUX_VERSION_CODE < KERNEL_VERSION(6,6,0)
srg_led_probe(struct i2c_client *client, const struct i2c_device_id *id)
#else
srg_led_probe(struct i2c_client *client)
#endif
{
struct device_node *np = client->dev.of_node, *child;
struct srg_led_ctrl *sysled_ctrl;
@ -193,13 +198,21 @@ static void srg_led_disable(struct i2c_client *client)
srg_led_i2c_write(sysled_ctrl, i, 0);
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,16,0)
static void
#else
static int
#endif
srg_led_remove(struct i2c_client *client)
{
struct srg_led_ctrl *sysled_ctrl = i2c_get_clientdata(client);
srg_led_disable(client);
mutex_destroy(&sysled_ctrl->lock);
#if LINUX_VERSION_CODE < KERNEL_VERSION(5,16,0)
return 0;
#endif
}
static const struct i2c_device_id srg_led_id[] = {

30
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c
View File

@ -144,7 +144,7 @@ static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule
* RT_ERR_SMI - SMI access error
* RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL.
* Note:
* This function enable and intialize ACL function
* This function enable and initialize ACL function
*/
rtk_api_ret_t rtk_filter_igrAcl_init(void)
{
@ -204,7 +204,7 @@ rtk_api_ret_t rtk_filter_igrAcl_init(void)
* This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg).
* Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL
* comparison rules by means of linked list. Pointer pFilter_field will be added to linked
* list keeped by structure that pFilter_cfg points to.
* list kept by structure that pFilter_cfg points to.
*/
rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t* pFilter_cfg, rtk_filter_field_t* pFilter_field)
{
@ -348,7 +348,7 @@ static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule
}
else
{
/*default acl template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/
/*default ACL template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/
aclRule[tempIdx].data_bits.field[fieldIdx] = ((ip6addr[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16));
aclRule[tempIdx].care_bits.field[fieldIdx] = ((ip6mask[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16));
}
@ -557,7 +557,7 @@ static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule
* pFilter_cfg - The ACL configuration that this function will add comparison rule
* pFilter_action - Action(s) of ACL configuration.
* Output:
* ruleNum - number of rules written in acl table
* ruleNum - number of rules written in ACL table
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
@ -1140,12 +1140,12 @@ rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void)
/* Function Name:
* rtk_filter_igrAcl_cfg_get
* Description:
* Get one ingress acl configuration from ASIC.
* Get one ingress ACL configuration from ASIC.
* Input:
* filter_id - Start index of ACL configuration.
* Output:
* pFilter_cfg - buffer pointer of ingress acl data
* pFilter_action - buffer pointer of ingress acl action
* pFilter_cfg - buffer pointer of ingress ACL data
* pFilter_action - buffer pointer of ingress ACL action
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
@ -1462,7 +1462,7 @@ rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cf
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This function sets action of packets when no ACL configruation matches.
* This function sets action of packets when no ACL configuration matches.
*/
rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action)
{
@ -1535,7 +1535,7 @@ rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_un
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This function gets action of packets when no ACL configruation matches.
* This function gets action of packets when no ACL configuration matches.
*/
rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state)
{
@ -1571,7 +1571,7 @@ rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t st
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This function gets action of packets when no ACL configruation matches.
* This function gets action of packets when no ACL configuration matches.
*/
rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState)
{
@ -1699,7 +1699,7 @@ rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate)
* RT_ERR_FAILED - Failed
* RT_ERR_SMI - SMI access error
* Note:
* System support 16 user defined field selctors.
* System support 16 user defined field selectors.
* Each selector can be enabled or disable.
* User can defined retrieving 16-bits in many predefiend
* standard l2/l3/l4 payload.
@ -1928,7 +1928,7 @@ rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *p
* Set Port Range check
* Input:
* index - index of Port Range 0-15
* type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port
* type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port
* upperPort - The upper bound of Port range
* lowerPort - The lower Bound of Port range
* Output:
@ -1977,7 +1977,7 @@ rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t
* Input:
* index - index of Port Range 0-15
* Output:
* pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port
* pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port
* pUpperPort - The upper bound of Port range
* pLowerPort - The lower Bound of Port range
* Return:
@ -2011,7 +2011,7 @@ rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t
/* Function Name:
* rtk_filter_igrAclPolarity_set
* Description:
* Set ACL Goip control palarity
* Set ACL Goip control polarity
* Input:
* polarity - 1: High, 0: Low
* Output:
@ -2034,7 +2034,7 @@ rtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity)
/* Function Name:
* rtk_filter_igrAclPolarity_get
* Description:
* Get ACL Goip control palarity
* Get ACL Goip control polarity
* Input:
* pPolarity - 1: High, 0: Low
* Output:

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c
View File

@ -113,7 +113,7 @@ rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable)
* Note:
* The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899)
* to the frame that transmitting to CPU port.
* The inset cpu tag mode is as following:
* The insert CPU tag mode is as following:
* - CPU_INSERT_TO_ALL
* - CPU_INSERT_TO_TRAPPING
* - CPU_INSERT_TO_NONE
@ -160,7 +160,7 @@ rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode)
* RT_ERR_L2_NO_CPU_PORT - CPU port is not exist
* Note:
* The API can get configured CPU port and its setting.
* The inset cpu tag mode is as following:
* The insert CPU tag mode is as following:
* - CPU_INSERT_TO_ALL
* - CPU_INSERT_TO_TRAPPING
* - CPU_INSERT_TO_NONE

10
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c
View File

@ -233,7 +233,7 @@ rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask)
* Input:
* port - Port ID
* protocol - IGMP/MLD protocol
* action - Per-port and per-protocol IGMP action seeting
* action - Per-port and per-protocol IGMP action setting
* Output:
* None.
* Return:
@ -321,7 +321,7 @@ rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protoco
* Input:
* port - Port ID
* protocol - IGMP/MLD protocol
* action - Per-port and per-protocol IGMP action seeting
* action - Per-port and per-protocol IGMP action setting
* Output:
* None.
* Return:
@ -1217,7 +1217,7 @@ rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable
* Description:
* Get IGMP/MLD Group database
* Input:
* indes - Index (0~255)
* index - Index (0~255)
* Output:
* pGroup - Group database information.
* Return:
@ -1418,7 +1418,7 @@ rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pA
/* Function Name:
* rtk_igmp_dropLeaveZeroEnable_set
* Description:
* Set the function of droppping Leave packet with group IP = 0.0.0.0
* Set the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* enabled - Action 1: drop, 0:pass
* Output:
@ -1451,7 +1451,7 @@ rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled)
/* Function Name:
* rtk_igmp_dropLeaveZeroEnable_get
* Description:
* Get the function of droppping Leave packet with group IP = 0.0.0.0
* Get the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* None
* Output:

32
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes ACL module high-layer API defination
* Feature : The file includes ACL module high-layer API definition
*
*/
@ -566,7 +566,7 @@ typedef enum rtk_filter_portrange_e
* RT_ERR_SMI - SMI access error
* RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL.
* Note:
* This function enable and intialize ACL function
* This function enable and initialize ACL function
*/
extern rtk_api_ret_t rtk_filter_igrAcl_init(void);
@ -589,7 +589,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_init(void);
* This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg).
* Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL
* comparison rules by means of linked list. Pointer pFilter_field will be added to linked
* list keeped by structure that pFilter_cfg points to.
* list kept by structure that pFilter_cfg points to.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, rtk_filter_field_t *pFilter_field);
@ -602,7 +602,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg,
* pFilter_cfg - The ACL configuration that this function will add comparison rule
* pFilter_action - Action(s) of ACL configuration.
* Output:
* ruleNum - number of rules written in acl table
* ruleNum - number of rules written in ACL table
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
@ -657,12 +657,12 @@ extern rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void);
/* Function Name:
* rtk_filter_igrAcl_cfg_get
* Description:
* Get one ingress acl configuration from ASIC.
* Get one ingress ACL configuration from ASIC.
* Input:
* filter_id - Start index of ACL configuration.
* Output:
* pFilter_cfg - buffer pointer of ingress acl data
* pFilter_action - buffer pointer of ingress acl action
* pFilter_cfg - buffer pointer of ingress ACL data
* pFilter_action - buffer pointer of ingress ACL action
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
@ -690,7 +690,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_fi
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This function sets action of packets when no ACL configruation matches.
* This function sets action of packets when no ACL configuration matches.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action);
@ -709,7 +709,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_fi
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This function gets action of packets when no ACL configruation matches.
* This function gets action of packets when no ACL configuration matches.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action);
@ -729,7 +729,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_fi
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This function gets action of packets when no ACL configruation matches.
* This function gets action of packets when no ACL configuration matches.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state);
@ -748,7 +748,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_sta
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This function gets action of packets when no ACL configruation matches.
* This function gets action of packets when no ACL configuration matches.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state);
@ -802,7 +802,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTe
* RT_ERR_FAILED - Failed
* RT_ERR_SMI - SMI access error
* Note:
* System support 16 user defined field selctors.
* System support 16 user defined field selectors.
* Each selector can be enabled or disable.
* User can defined retrieving 16-bits in many predefiend
* standard l2/l3/l4 payload.
@ -917,7 +917,7 @@ extern rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidran
* Set Port Range check
* Input:
* index - index of Port Range 0-15
* type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port
* type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port
* upperPort - The upper bound of Port range
* lowerPort - The lower Bound of Port range
* Output:
@ -940,7 +940,7 @@ extern rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portr
* Input:
* index - index of Port Range 0-15
* Output:
* pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port
* pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port
* pUpperPort - The upper bound of Port range
* pLowerPort - The lower Bound of Port range
* Return:
@ -957,7 +957,7 @@ extern rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portr
/* Function Name:
* rtk_filter_igrAclPolarity_set
* Description:
* Set ACL Goip control palarity
* Set ACL Goip control polarity
* Input:
* polarity - 1: High, 0: Low
* Output:
@ -973,7 +973,7 @@ extern rtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity);
/* Function Name:
* rtk_filter_igrAclPolarity_get
* Description:
* Get ACL Goip control palarity
* Get ACL Goip control polarity
* Input:
* pPolarity - 1: High, 0: Low
* Output:

6
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes CPU module high-layer API defination
* Feature : The file includes CPU module high-layer API definition
*
*/
@ -107,7 +107,7 @@ extern rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable);
* Note:
* The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899)
* to the frame that transmitting to CPU port.
* The inset cpu tag mode is as following:
* The insert CPU tag mode is as following:
* - CPU_INSERT_TO_ALL
* - CPU_INSERT_TO_TRAPPING
* - CPU_INSERT_TO_NONE
@ -131,7 +131,7 @@ extern rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode)
* RT_ERR_L2_NO_CPU_PORT - CPU port is not exist
* Note:
* The API can get configured CPU port and its setting.
* The inset cpu tag mode is as following:
* The insert CPU tag mode is as following:
* - CPU_INSERT_TO_ALL
* - CPU_INSERT_TO_TRAPPING
* - CPU_INSERT_TO_NONE

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes 1X module high-layer API defination
* Feature : The file includes 1X module high-layer API definition
*
*/

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes EEE module high-layer API defination
* Feature : The file includes EEE module high-layer API definition
*
*/

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes I2C module high-layer API defination
* Feature : The file includes I2C module high-layer API definition
*
*/

12
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes IGMP module high-layer API defination
* Feature : The file includes IGMP module high-layer API definition
*
*/
@ -205,7 +205,7 @@ extern rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask);
* Input:
* port - Port ID
* protocol - IGMP/MLD protocol
* action - Per-port and per-protocol IGMP action seeting
* action - Per-port and per-protocol IGMP action setting
* Output:
* None.
* Return:
@ -225,7 +225,7 @@ extern rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t
* Input:
* port - Port ID
* protocol - IGMP/MLD protocol
* action - Per-port and per-protocol IGMP action seeting
* action - Per-port and per-protocol IGMP action setting
* Output:
* None.
* Return:
@ -640,7 +640,7 @@ extern rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPk
* Description:
* Get IGMP/MLD Group database
* Input:
* indes - Index (0~255)
* index - Index (0~255)
* Output:
* pGroup - Group database information.
* Return:
@ -694,7 +694,7 @@ extern rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAc
/* Function Name:
* rtk_igmp_dropLeaveZeroEnable_set
* Description:
* Set the function of droppping Leave packet with group IP = 0.0.0.0
* Set the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* enabled - Action 1: drop, 0:pass
* Output:
@ -712,7 +712,7 @@ extern rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled);
/* Function Name:
* rtk_igmp_dropLeaveZeroEnable_get
* Description:
* Get the function of droppping Leave packet with group IP = 0.0.0.0
* Get the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* None
* Output:

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes Interrupt module high-layer API defination
* Feature : The file includes Interrupt module high-layer API definition
*
*/

50
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes L2 module high-layer API defination
* Feature : The file includes L2 module high-layer API definition
*
*/
@ -209,7 +209,7 @@ extern rtk_api_ret_t rtk_l2_init(void);
* RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* If the unicast mac address already existed in LUT, it will udpate the status of the entry.
* If the unicast mac address already existed in LUT, it will update the status of the entry.
* Otherwise, it will find an empty or asic auto learned entry to write. If all the entries
* with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.
*/
@ -307,7 +307,7 @@ extern rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_da
* RT_ERR_PORT_MASK - Invalid portmask.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* If the multicast mac address already existed in the LUT, it will udpate the
* If the multicast mac address already existed in the LUT, it will update the
* port mask of the entry. Otherwise, it will find an empty or asic auto learned
* entry to write. If all the entries with the same hash value can't be replaced,
* ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.
@ -383,7 +383,7 @@ extern rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr);
/* Function Name:
* rtk_l2_ipMcastAddr_add
* Description:
* Add Lut IP multicast entry
* Add LUT IP multicast entry
* Input:
* pIpMcastAddr - IP Multicast entry
* Output:
@ -418,7 +418,7 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr);
* RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can get Lut table of IP multicast entry.
* The API can get LUT table of IP multicast entry.
*/
extern rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr);
@ -465,7 +465,7 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr);
/* Function Name:
* rtk_l2_ipVidMcastAddr_add
* Description:
* Add Lut IP multicast+VID entry
* Add LUT IP multicast+VID entry
* Input:
* pIpVidMcastAddr - IP & VID multicast Entry
* Output:
@ -913,7 +913,7 @@ extern rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac
* Set flooding portmask
* Input:
* type - flooding type.
* pFlood_portmask - flooding porkmask
* pFlood_portmask - flooding portmask
* Output:
* None
* Return:
@ -938,7 +938,7 @@ extern rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, r
* Input:
* type - flooding type.
* Output:
* pFlood_portmask - flooding porkmask
* pFlood_portmask - flooding portmask
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
@ -956,10 +956,10 @@ extern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, r
/* Function Name:
* rtk_l2_localPktPermit_set
* Description:
* Set permittion of frames if source port and destination port are the same.
* Set permission of frames if source port and destination port are the same.
* Input:
* port - Port id.
* permit - permittion status
* permit - permission status
* Output:
* None
* Return:
@ -969,34 +969,34 @@ extern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, r
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_ENABLE - Invalid permit value.
* Note:
* This API is setted to permit frame if its source port is equal to destination port.
* This API is set to permit frame if its source port is equal to destination port.
*/
extern rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit);
/* Function Name:
* rtk_l2_localPktPermit_get
* Description:
* Get permittion of frames if source port and destination port are the same.
* Get permission of frames if source port and destination port are the same.
* Input:
* port - Port id.
* Output:
* pPermit - permittion status
* pPermit - permission status
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
* This API is to get permittion status for frames if its source port is equal to destination port.
* This API is to get permission status for frames if its source port is equal to destination port.
*/
extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit);
/* Function Name:
* rtk_l2_aging_set
* Description:
* Set LUT agging out speed
* Set LUT ageing out speed
* Input:
* aging_time - Agging out time.
* aging_time - Ageing out time.
* Output:
* None
* Return:
@ -1005,14 +1005,14 @@ extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pP
* RT_ERR_SMI - SMI access error
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
* The API can set LUT agging out period for each entry and the range is from 14s to 800s.
* The API can set LUT ageing out period for each entry and the range is from 14s to 800s.
*/
extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time);
/* Function Name:
* rtk_l2_aging_get
* Description:
* Get LUT agging out time
* Get LUT ageing out time
* Input:
* None
* Output:
@ -1023,14 +1023,14 @@ extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time);
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
* The API can get LUT agging out period for each entry.
* The API can get LUT ageing out period for each entry.
*/
extern rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time);
/* Function Name:
* rtk_l2_ipMcastAddrLookup_set
* Description:
* Set Lut IP multicast lookup function
* Set LUT IP multicast lookup function
* Input:
* type - Lookup type for IPMC packet.
* Output:
@ -1051,7 +1051,7 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type
/* Function Name:
* rtk_l2_ipMcastAddrLookup_get
* Description:
* Get Lut IP multicast lookup function
* Get LUT IP multicast lookup function
* Input:
* None.
* Output:
@ -1068,9 +1068,9 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pTy
/* Function Name:
* rtk_l2_ipMcastForwardRouterPort_set
* Description:
* Set IPMC packet forward to rounter port also or not
* Set IPMC packet forward to router port also or not
* Input:
* enabled - 1: Inlcude router port, 0, exclude router port
* enabled - 1: Include router port, 0, exclude router port
* Output:
* None.
* Return:
@ -1085,11 +1085,11 @@ extern rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled);
/* Function Name:
* rtk_l2_ipMcastForwardRouterPort_get
* Description:
* Get IPMC packet forward to rounter port also or not
* Get IPMC packet forward to router port also or not
* Input:
* None.
* Output:
* pEnabled - 1: Inlcude router port, 0, exclude router port
* pEnabled - 1: Include router port, 0, exclude router port
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes Leaky module high-layer API defination
* Feature : The file includes Leaky module high-layer API definition
*
*/

20
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes LED module high-layer API defination
* Feature : The file includes LED module high-layer API definition
*
*/
@ -107,7 +107,7 @@ typedef enum rtk_led_serialOutput_e
/* Function Name:
* rtk_led_enable_set
* Description:
* Set Led enable congiuration
* Set Led enable configuration
* Input:
* group - LED group id.
* pPortmask - LED enable port mask.
@ -126,7 +126,7 @@ extern rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *p
/* Function Name:
* rtk_led_enable_get
* Description:
* Get Led enable congiuration
* Get Led enable configuration
* Input:
* group - LED group id.
* Output:
@ -188,7 +188,7 @@ extern rtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode);
/* Function Name:
* rtk_led_modeForce_set
* Description:
* Set Led group to congiuration force mode
* Set Led group to configuration force mode
* Input:
* port - port ID
* group - Support LED group id.
@ -214,7 +214,7 @@ extern rtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t grou
/* Function Name:
* rtk_led_modeForce_get
* Description:
* Get Led group to congiuration force mode
* Get Led group to configuration force mode
* Input:
* port - port ID
* group - Support LED group id.
@ -276,7 +276,7 @@ extern rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate);
/* Function Name:
* rtk_led_groupConfig_set
* Description:
* Set per group Led to congiuration mode
* Set per group Led to configuration mode
* Input:
* group - LED group.
* config - LED configuration
@ -312,7 +312,7 @@ extern rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_cong
/* Function Name:
* rtk_led_groupConfig_get
* Description:
* Get Led group congiuration mode
* Get Led group configuration mode
* Input:
* group - LED group.
* Output:
@ -370,7 +370,7 @@ extern rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_abi
/* Function Name:
* rtk_led_serialMode_set
* Description:
* Set Led serial mode active congiuration
* Set Led serial mode active configuration
* Input:
* active - LED group.
* Output:
@ -381,14 +381,14 @@ extern rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_abi
* RT_ERR_SMI - SMI access error
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can set LED serial mode active congiuration.
* The API can set LED serial mode active configuration.
*/
extern rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active);
/* Function Name:
* rtk_led_serialMode_get
* Description:
* Get Led group congiuration mode
* Get Led group configuration mode
* Input:
* group - LED group.
* Output:

8
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes Mirror module high-layer API defination
* Feature : The file includes Mirror module high-layer API definition
*
*/
@ -81,7 +81,7 @@ extern rtk_api_ret_t rtk_mirror_portBased_get(rtk_port_t* pMirroring_port, rtk_p
* RT_ERR_SMI - SMI access error
* RT_ERR_ENABLE - Invalid enable input
* Note:
* The API is to set mirror isolation function that prevent normal forwarding packets to miror port.
* The API is to set mirror isolation function that prevent normal forwarding packets to mirror port.
*/
extern rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable);
@ -118,7 +118,7 @@ extern rtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable);
* RT_ERR_SMI - SMI access error
* RT_ERR_ENABLE - Invalid enable input
* Note:
* The API is to set mirror VLAN leaky function forwarding packets to miror port.
* The API is to set mirror VLAN leaky function forwarding packets to mirror port.
*/
extern rtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable);
@ -157,7 +157,7 @@ extern rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enabl
* RT_ERR_SMI - SMI access error
* RT_ERR_ENABLE - Invalid enable input
* Note:
* The API is to set mirror VLAN leaky function forwarding packets to miror port.
* The API is to set mirror VLAN leaky function forwarding packets to mirror port.
*/
extern rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable);

34
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes port module high-layer API defination
* Feature : The file includes port module high-layer API definition
*
*/
@ -222,7 +222,7 @@ typedef struct rtk_rtctResult_s
/* Function Name:
* rtk_port_phyAutoNegoAbility_set
* Description:
* Set ethernet PHY auto-negotiation desired ability.
* Set Ethernet PHY auto-negotiation desired ability.
* Input:
* port - port id.
* pAbility - Ability structure
@ -259,7 +259,7 @@ extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_p
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
* Note:
* Get the capablity of specified PHY.
* Get the capability of specified PHY.
*/
extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility);
@ -303,14 +303,14 @@ extern rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
* Note:
* Get the capablity of specified PHY.
* Get the capability of specified PHY.
*/
extern rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility);
/* Function Name:
* rtk_port_phyStatus_get
* Description:
* Get ethernet PHY linking status
* Get Ethernet PHY linking status
* Input:
* port - Port id.
* Output:
@ -459,7 +459,7 @@ extern rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_abilit
* For UTP port, This API will also enable the digital
* loopback bit in PHY register for sync of speed between
* PHY and MAC. For EXT port, users need to force the
* link state by themself.
* link state by themselves.
*/
extern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable);
@ -527,7 +527,7 @@ extern rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg
/* Function Name:
* rtk_port_backpressureEnable_set
* Description:
* Set the half duplex backpressure enable status of the specific port.
* Set the half duplex back-pressure enable status of the specific port.
* Input:
* port - port id.
* enable - Back pressure status.
@ -540,8 +540,8 @@ extern rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_ENABLE - Invalid enable input.
* Note:
* This API can set the half duplex backpressure enable status of the specific port.
* The half duplex backpressure enable status of the port is as following:
* This API can set the half duplex back-pressure enable status of the specific port.
* The half duplex back-pressure enable status of the port is as following:
* - DISABLE
* - ENABLE
*/
@ -550,7 +550,7 @@ extern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable
/* Function Name:
* rtk_port_backpressureEnable_get
* Description:
* Get the half duplex backpressure enable status of the specific port.
* Get the half duplex back-pressure enable status of the specific port.
* Input:
* port - Port id.
* Output:
@ -561,8 +561,8 @@ extern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
* This API can get the half duplex backpressure enable status of the specific port.
* The half duplex backpressure enable status of the port is as following:
* This API can get the half duplex back-pressure enable status of the specific port.
* The half duplex back-pressure enable status of the port is as following:
* - DISABLE
* - ENABLE
*/
@ -594,7 +594,7 @@ extern rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enab
/* Function Name:
* rtk_port_adminEnable_get
* Description:
* Get port admin configurationof the specific port.
* Get port admin configuration of the specific port.
* Input:
* port - Port id.
* Output:
@ -628,7 +628,7 @@ extern rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEn
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_PORT_MASK - Invalid portmask.
* Note:
* This API set the port mask that a port can trasmit packet to of each port
* This API set the port mask that a port can transmit packet to of each port
* A port can only transmit packet to ports included in permitted portmask
*/
extern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask);
@ -647,7 +647,7 @@ extern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPo
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
* This API get the port mask that a port can trasmit packet to of each port
* This API get the port mask that a port can transmit packet to of each port
* A port can only transmit packet to ports included in permitted portmask
*/
extern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask);
@ -669,7 +669,7 @@ extern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPo
* Note:
* This API can set external interface 2 RGMII delay.
* In TX delay, there are 2 selection: no-delay and 2ns delay.
* In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay.
* In RX delay, there are 8 steps for delay tuning. 0 for no-delay, and 7 for maximum delay.
*/
extern rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay);
@ -690,7 +690,7 @@ extern rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDe
* Note:
* This API can set external interface 2 RGMII delay.
* In TX delay, there are 2 selection: no-delay and 2ns delay.
* In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay.
* In RX delay, there are 8 steps for delay tuning. 0 for n0-delay, and 7 for maximum delay.
*/
extern rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay);

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes time module high-layer API defination
* Feature : The file includes time module high-layer API definition
*
*/
@ -310,7 +310,7 @@ extern rtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnab
/* Function Name:
* rtk_ptp_portTimestamp_get
* Description:
* Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device.
* Get PTP timestamp according to the PTP identifier on the dedicated port from the specified device.
* Input:
* unit - unit id
* port - port id

8
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes QoS module high-layer API defination
* Feature : The file includes QoS module high-layer API definition
*
*/
@ -123,7 +123,7 @@ typedef rtk_uint32 rtk_queue_num_t; /* queue number*/
/* Function Name:
* rtk_qos_init
* Description:
* Configure Qos default settings with queue number assigment to each port.
* Configure QoS default settings with queue number assignment to each port.
* Input:
* queueNum - Queue number of each port.
* Output:
@ -135,7 +135,7 @@ typedef rtk_uint32 rtk_queue_num_t; /* queue number*/
* RT_ERR_QUEUE_NUM - Invalid queue number.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This API will initialize related Qos setting with queue number assigment.
* This API will initialize related QoS setting with queue number assignment.
* The queue number is from 1 to 8.
*/
extern rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum);
@ -235,7 +235,7 @@ extern rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_p
* RT_ERR_VLAN_PRIORITY - Invalid priority.
* RT_ERR_QOS_INT_PRIORITY - Invalid priority.
* Note:
* Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling.
* Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling.
*/
extern rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri);

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h
View File

@ -9,7 +9,7 @@
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
* Feature : The file includes rate module high-layer API defination
* Feature : The file includes rate module high-layer API definition
*
*/

8
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h
View File

@ -40,7 +40,7 @@ typedef enum rt_error_code_e
RT_ERR_NULL_POINTER, /* 0x00000007, input parameter is null pointer */
RT_ERR_QUEUE_ID, /* 0x00000008, invalid queue id */
RT_ERR_QUEUE_NUM, /* 0x00000009, invalid queue number */
RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy watting time out */
RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy waiting time out */
RT_ERR_MAC, /* 0x0000000b, invalid mac address */
RT_ERR_OUT_OF_RANGE, /* 0x0000000c, input parameter out of range */
RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000000d, functions not supported by this chip model */
@ -57,7 +57,7 @@ typedef enum rt_error_code_e
/* 0x0001xxxx for vlan */
RT_ERR_VLAN_VID = 0x00010000, /* 0x00010000, invalid vid */
RT_ERR_VLAN_PRIORITY, /* 0x00010001, invalid 1p priority */
RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, emtpy entry of vlan table */
RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, empty entry of vlan table */
RT_ERR_VLAN_ACCEPT_FRAME_TYPE, /* 0x00010003, invalid accept frame type */
RT_ERR_VLAN_EXIST, /* 0x00010004, vlan is exist */
RT_ERR_VLAN_ENTRY_NOT_FOUND, /* 0x00010005, specified vlan entry not found */
@ -165,7 +165,7 @@ typedef enum rt_error_code_e
RT_ERR_INBW_TOKEN_AMOUNT, /* 0x000c0001, invalid amount of token for input bandwidth control */
RT_ERR_INBW_FCON_VALUE, /* 0x000c0002, invalid flow control ON threshold value for input bandwidth control */
RT_ERR_INBW_FCOFF_VALUE, /* 0x000c0003, invalid flow control OFF threshold value for input bandwidth control */
RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incomming packet for input bandwidth control */
RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incoming packet for input bandwidth control */
RT_ERR_INBW_RATE, /* 0x000c0005, invalid input bandwidth */
/* 0x000dxxxx for QoS */
@ -220,7 +220,7 @@ typedef enum rt_error_code_e
RT_ERR_DOT1X_PROC, /* 0x00110006, unauthorized behavior error */
RT_ERR_DOT1X_GVLANIDX, /* 0x00110007, guest vlan index error */
RT_ERR_DOT1X_GVLANTALK, /* 0x00110008, guest vlan OPDIR error */
RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch eror */
RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch error */
RT_ERR_END /* The symbol is the latest symbol */
} rt_error_code_t;

8
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h
View File

@ -185,10 +185,10 @@ typedef enum rtk_switch_maxPktLen_linkSpeed_e {
#define RTK_SCAN_ALL_LOG_PORT(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( rtk_switch_logicalPortCheck(__port__) == RT_ERR_OK)
#define RTK_SCAN_ALL_LOG_PORTMASK(__portmask__) for((__portmask__).bits[0] = 0; (__portmask__).bits[0] < 0x7FFFF; (__portmask__).bits[0]++) if( rtk_switch_isPortMaskValid(&__portmask__) == RT_ERR_OK)
/* Port mask defination */
/* Port mask definition */
#define RTK_PHY_PORTMASK_ALL (rtk_switch_phyPortMask_get())
/* Port defination*/
/* Port definition*/
#define RTK_MAX_LOGICAL_PORT_ID (rtk_switch_maxLogicalPort_get())
/* Function Name:
@ -477,7 +477,7 @@ extern rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask);
/* Function Name:
* rtk_switch_portmask_L2P_get
* Description:
* Get physicl portmask from logical portmask
* Get physical portmask from logical portmask
* Input:
* pLogicalPmask - logical port mask
* Output:
@ -546,7 +546,7 @@ rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask);
/* Function Name:
* rtk_switch_init
* Description:
* Set chip to default configuration enviroment
* Set chip to default configuration environment
* Input:
* None
* Output:

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h
View File

@ -56,13 +56,13 @@ typedef enum rtk_enable_e
#define ETHER_ADDR_LEN 6
#endif
/* ethernet address type */
/* Ethernet address type */
typedef struct rtk_mac_s
{
rtk_uint8 octet[ETHER_ADDR_LEN];
} rtk_mac_t;
typedef rtk_uint32 rtk_pri_t; /* priority vlaue */
typedef rtk_uint32 rtk_pri_t; /* priority value */
typedef rtk_uint32 rtk_qid_t; /* queue id type */
typedef rtk_uint32 rtk_data_t;
typedef rtk_uint32 rtk_dscp_t; /* dscp vlaue */

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h
View File

@ -38,7 +38,7 @@ extern ret_t rtl8367c_setAsicCputagInsertMode(rtk_uint32 mode);
extern ret_t rtl8367c_getAsicCputagInsertMode(rtk_uint32 *pMode);
extern ret_t rtl8367c_setAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 newPri);
extern ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNewPri);
extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion);
extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position);
extern ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion);
extern ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode);
extern ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode);

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h
View File

@ -11,7 +11,7 @@
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
* Feature : Green ethernet related functions
* Feature : Green Ethernet related functions
*
*/

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h
View File

@ -11,7 +11,7 @@
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
* Feature : Qos related functions
* Feature : QoS related functions
*
*/

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h
View File

@ -11,7 +11,7 @@
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
* Feature : Unkown multicast related functions
* Feature : Unknown multicast related functions
*
*/

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h
View File

@ -11,7 +11,7 @@
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
* Feature : Regsiter MACRO related definition
* Feature : Register MACRO related definition
*
*/

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h
View File

@ -20357,8 +20357,8 @@ auto-generated register address and field data
#define RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_MASK 0x2000
#define RTL8367C_REPORT_FORWARD_OFFSET 12
#define RTL8367C_REPORT_FORWARD_MASK 0x1000
#define RTL8367C_ROBURSTNESS_VAR_OFFSET 9
#define RTL8367C_ROBURSTNESS_VAR_MASK 0xE00
#define RTL8367C_ROBUSTNESS_VAR_OFFSET 9
#define RTL8367C_ROBUSTNESS_VAR_MASK 0xE00
#define RTL8367C_LEAVE_SUPPRESSION_OFFSET 8
#define RTL8367C_LEAVE_SUPPRESSION_MASK 0x100
#define RTL8367C_REPORT_SUPPRESSION_OFFSET 7

48
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c
View File

@ -86,7 +86,7 @@ rtk_api_ret_t rtk_l2_init(void)
* RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* If the unicast mac address already existed in LUT, it will udpate the status of the entry.
* If the unicast mac address already existed in LUT, it will update the status of the entry.
* Otherwise, it will find an empty or asic auto learned entry to write. If all the entries
* with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.
*/
@ -453,7 +453,7 @@ rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data)
* RT_ERR_PORT_MASK - Invalid portmask.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* If the multicast mac address already existed in the LUT, it will udpate the
* If the multicast mac address already existed in the LUT, it will update the
* port mask of the entry. Otherwise, it will find an empty or asic auto learned
* entry to write. If all the entries with the same hash value can't be replaced,
* ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.
@ -800,7 +800,7 @@ rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr)
/* Function Name:
* rtk_l2_ipMcastAddr_add
* Description:
* Add Lut IP multicast entry
* Add LUT IP multicast entry
* Input:
* pIpMcastAddr - IP Multicast entry
* Output:
@ -914,7 +914,7 @@ rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr)
* RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can get Lut table of IP multicast entry.
* The API can get LUT table of IP multicast entry.
*/
rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr)
{
@ -1080,7 +1080,7 @@ rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr)
/* Function Name:
* rtk_l2_ipVidMcastAddr_add
* Description:
* Add Lut IP multicast+VID entry
* Add LUT IP multicast+VID entry
* Input:
* pIpVidMcastAddr - IP & VID multicast Entry
* Output:
@ -2143,7 +2143,7 @@ rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt)
* Set flooding portmask
* Input:
* type - flooding type.
* pFlood_portmask - flooding porkmask
* pFlood_portmask - flooding portmask
* Output:
* None
* Return:
@ -2204,7 +2204,7 @@ rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_port
* Input:
* type - flooding type.
* Output:
* pFlood_portmask - flooding porkmask
* pFlood_portmask - flooding portmask
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
@ -2259,10 +2259,10 @@ rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_port
/* Function Name:
* rtk_l2_localPktPermit_set
* Description:
* Set permittion of frames if source port and destination port are the same.
* Set permission of frames if source port and destination port are the same.
* Input:
* port - Port id.
* permit - permittion status
* permit - permission status
* Output:
* None
* Return:
@ -2272,7 +2272,7 @@ rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_port
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_ENABLE - Invalid permit value.
* Note:
* This API is setted to permit frame if its source port is equal to destination port.
* This API is set to permit frame if its source port is equal to destination port.
*/
rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit)
{
@ -2296,18 +2296,18 @@ rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit)
/* Function Name:
* rtk_l2_localPktPermit_get
* Description:
* Get permittion of frames if source port and destination port are the same.
* Get permission of frames if source port and destination port are the same.
* Input:
* port - Port id.
* Output:
* pPermit - permittion status
* pPermit - permission status
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
* This API is to get permittion status for frames if its source port is equal to destination port.
* This API is to get permission status for frames if its source port is equal to destination port.
*/
rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit)
{
@ -2331,9 +2331,9 @@ rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit)
/* Function Name:
* rtk_l2_aging_set
* Description:
* Set LUT agging out speed
* Set LUT ageing out speed
* Input:
* aging_time - Agging out time.
* aging_time - Ageing out time.
* Output:
* None
* Return:
@ -2342,7 +2342,7 @@ rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit)
* RT_ERR_SMI - SMI access error
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
* The API can set LUT agging out period for each entry and the range is from 45s to 458s.
* The API can set LUT ageing out period for each entry and the range is from 45s to 458s.
*/
rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time)
{
@ -2371,7 +2371,7 @@ rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time)
/* Function Name:
* rtk_l2_aging_get
* Description:
* Get LUT agging out time
* Get LUT ageing out time
* Input:
* None
* Output:
@ -2382,7 +2382,7 @@ rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time)
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
* The API can get LUT agging out period for each entry.
* The API can get LUT ageing out period for each entry.
*/
rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time)
{
@ -2416,7 +2416,7 @@ rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time)
/* Function Name:
* rtk_l2_ipMcastAddrLookup_set
* Description:
* Set Lut IP multicast lookup function
* Set LUT IP multicast lookup function
* Input:
* type - Lookup type for IPMC packet.
* Output:
@ -2473,7 +2473,7 @@ rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type)
/* Function Name:
* rtk_l2_ipMcastAddrLookup_get
* Description:
* Get Lut IP multicast lookup function
* Get LUT IP multicast lookup function
* Input:
* None.
* Output:
@ -2518,9 +2518,9 @@ rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType)
/* Function Name:
* rtk_l2_ipMcastForwardRouterPort_set
* Description:
* Set IPMC packet forward to rounter port also or not
* Set IPMC packet forward to router port also or not
* Input:
* enabled - 1: Inlcude router port, 0, exclude router port
* enabled - 1: Include router port, 0, exclude router port
* Output:
* None.
* Return:
@ -2549,11 +2549,11 @@ rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled)
/* Function Name:
* rtk_l2_ipMcastForwardRouterPort_get
* Description:
* Get IPMC packet forward to rounter port also or not
* Get IPMC packet forward to router port also or not
* Input:
* None.
* Output:
* pEnabled - 1: Inlcude router port, 0, exclude router port
* pEnabled - 1: Include router port, 0, exclude router port
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed

16
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c
View File

@ -27,7 +27,7 @@
/* Function Name:
* rtk_led_enable_set
* Description:
* Set Led enable congiuration
* Set Led enable configuration
* Input:
* group - LED group id.
* pPortmask - LED enable port mask.
@ -74,7 +74,7 @@ rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmas
/* Function Name:
* rtk_led_enable_get
* Description:
* Get Led enable congiuration
* Get Led enable configuration
* Input:
* group - LED group id.
* Output:
@ -205,7 +205,7 @@ rtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode)
/* Function Name:
* rtk_led_modeForce_set
* Description:
* Set Led group to congiuration force mode
* Set Led group to configuration force mode
* Input:
* port - port ID
* group - Support LED group id.
@ -255,7 +255,7 @@ rtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_
/* Function Name:
* rtk_led_modeForce_get
* Description:
* Get Led group to congiuration force mode
* Get Led group to configuration force mode
* Input:
* port - port ID
* group - Support LED group id.
@ -369,7 +369,7 @@ rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate)
/* Function Name:
* rtk_led_groupConfig_set
* Description:
* Set per group Led to congiuration mode
* Set per group Led to configuration mode
* Input:
* group - LED group.
* config - LED configuration
@ -422,7 +422,7 @@ rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t co
/* Function Name:
* rtk_led_groupConfig_get
* Description:
* Get Led group congiuration mode
* Get Led group configuration mode
* Input:
* group - LED group.
* Output:
@ -583,7 +583,7 @@ rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t
/* Function Name:
* rtk_led_serialMode_set
* Description:
* Set Led serial mode active congiuration
* Set Led serial mode active configuration
* Input:
* active - LED group.
* Output:
@ -594,7 +594,7 @@ rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t
* RT_ERR_SMI - SMI access error
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can set LED serial mode active congiuration.
* The API can set LED serial mode active configuration.
*/
rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active)
{

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c
View File

@ -66,7 +66,7 @@ rtk_api_ret_t rtk_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t
RTK_CHK_PORTMASK_VALID(pMirrored_tx_portmask);
/*Mirror Sorce Port Mask Check*/
/*Mirror Source Port Mask Check*/
if (pMirrored_tx_portmask->bits[0]!=pMirrored_rx_portmask->bits[0]&&pMirrored_tx_portmask->bits[0]!=0&&pMirrored_rx_portmask->bits[0]!=0)
return RT_ERR_PORT_MASK;
@ -353,7 +353,7 @@ rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pR
* RT_ERR_SMI - SMI access error
* RT_ERR_ENABLE - Invalid enable input
* Note:
* The API is to set mirror VLAN leaky function forwarding packets to miror port.
* The API is to set mirror VLAN leaky function forwarding packets to mirror port.
*/
rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable)
{

38
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c
View File

@ -410,7 +410,7 @@ static rtk_api_ret_t _rtk_port_FiberModeAbility_get(rtk_port_t port, rtk_port_ph
/* Function Name:
* rtk_port_phyAutoNegoAbility_set
* Description:
* Set ethernet PHY auto-negotiation desired ability.
* Set Ethernet PHY auto-negotiation desired ability.
* Input:
* port - port id.
* pAbility - Ability structure
@ -618,7 +618,7 @@ rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_abil
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
* Note:
* Get the capablity of specified PHY.
* Get the capability of specified PHY.
*/
rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility)
{
@ -836,7 +836,7 @@ rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_abi
if (1 == pAbility->AsyFC)
{
/*Asymetric flow control in reg 4.11*/
/*Asymmetric flow control in reg 4.11*/
phyEnMsk4 = phyEnMsk4 | (1 << 11);
}
if (1 == pAbility->FC)
@ -892,7 +892,7 @@ rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_abi
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
* Note:
* Get the capablity of specified PHY.
* Get the capability of specified PHY.
*/
rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility)
{
@ -982,7 +982,7 @@ rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_abi
/* Function Name:
* rtk_port_phyStatus_get
* Description:
* Get ethernet PHY linking status
* Get Ethernet PHY linking status
* Input:
* port - Port id.
* Output:
@ -1363,7 +1363,7 @@ rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pP
* For UTP port, This API will also enable the digital
* loopback bit in PHY register for sync of speed between
* PHY and MAC. For EXT port, users need to force the
* link state by themself.
* link state by themselves.
*/
rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable)
{
@ -1508,7 +1508,7 @@ rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_p
/* Function Name:
* rtk_port_backpressureEnable_set
* Description:
* Set the half duplex backpressure enable status of the specific port.
* Set the half duplex back-pressure enable status of the specific port.
* Input:
* port - port id.
* enable - Back pressure status.
@ -1521,10 +1521,10 @@ rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_p
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_ENABLE - Invalid enable input.
* Note:
* This API can set the half duplex backpressure enable status of the specific port.
* The half duplex backpressure enable status of the port is as following:
* This API can set the half duplex back-pressure enable status of the specific port.
* The half duplex back-pressure enable status of the port is as following:
* - DISABLE(Defer)
* - ENABLE (Backpressure)
* - ENABLE (Back-pressure)
*/
rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable)
{
@ -1548,7 +1548,7 @@ rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enab
/* Function Name:
* rtk_port_backpressureEnable_get
* Description:
* Get the half duplex backpressure enable status of the specific port.
* Get the half duplex back-pressure enable status of the specific port.
* Input:
* port - Port id.
* Output:
@ -1559,10 +1559,10 @@ rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enab
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
* This API can get the half duplex backpressure enable status of the specific port.
* The half duplex backpressure enable status of the port is as following:
* This API can get the half duplex back-pressure enable status of the specific port.
* The half duplex back-pressure enable status of the port is as following:
* - DISABLE(Defer)
* - ENABLE (Backpressure)
* - ENABLE (Back-pressure)
*/
rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable)
{
@ -1643,7 +1643,7 @@ rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable)
/* Function Name:
* rtk_port_adminEnable_get
* Description:
* Get port admin configurationof the specific port.
* Get port admin configuration of the specific port.
* Input:
* port - Port id.
* Output:
@ -1704,7 +1704,7 @@ rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable)
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_PORT_MASK - Invalid portmask.
* Note:
* This API set the port mask that a port can trasmit packet to of each port
* This API set the port mask that a port can transmit packet to of each port
* A port can only transmit packet to ports included in permitted portmask
*/
rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask)
@ -1747,7 +1747,7 @@ rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask)
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
* This API get the port mask that a port can trasmit packet to of each port
* This API get the port mask that a port can transmit packet to of each port
* A port can only transmit packet to ports included in permitted portmask
*/
rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask)
@ -1790,7 +1790,7 @@ rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask)
* Note:
* This API can set external interface 2 RGMII delay.
* In TX delay, there are 2 selection: no-delay and 2ns delay.
* In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay.
* In RX delay, there are 8 steps for delay tuning. 0 for no-delay, and 7 for maximum delay.
*/
rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay)
{
@ -1841,7 +1841,7 @@ rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rt
* Note:
* This API can set external interface 2 RGMII delay.
* In TX delay, there are 2 selection: no-delay and 2ns delay.
* In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay.
* In RX delay, there are 8 steps for delay tuning. 0 for n0-delay, and 7 for maximum delay.
*/
rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay)
{

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c
View File

@ -401,7 +401,7 @@ rtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable)
/* Function Name:
* rtk_ptp_portTimestamp_get
* Description:
* Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device.
* Get PTP timestamp according to the PTP identifier on the dedicated port from the specified device.
* Input:
* unit - unit id
* port - port id

8
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c
View File

@ -28,7 +28,7 @@
/* Function Name:
* rtk_qos_init
* Description:
* Configure Qos default settings with queue number assigment to each port.
* Configure QoS default settings with queue number assignment to each port.
* Input:
* queueNum - Queue number of each port.
* Output:
@ -40,7 +40,7 @@
* RT_ERR_QUEUE_NUM - Invalid queue number.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This API will initialize related Qos setting with queue number assigment.
* This API will initialize related QoS setting with queue number assignment.
* The queue number is from 1 to 8.
*/
rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum)
@ -143,7 +143,7 @@ rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum)
return retVal;
}
/* Finetune B/T value */
/* Fine-tune B/T value */
if((retVal = rtl8367c_setAsicReg(0x1722, 0x1158)) != RT_ERR_OK)
return retVal;
@ -455,7 +455,7 @@ rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri)
* RT_ERR_VLAN_PRIORITY - Invalid priority.
* RT_ERR_QOS_INT_PRIORITY - Invalid priority.
* Note:
* Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling.
* Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling.
*/
rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri)
{

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c
View File

@ -8,7 +8,7 @@
* available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
*
* $Revision: 76306 $
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : Declaration of RLDP and RLPP API
*
@ -404,7 +404,7 @@ rtk_api_ret_t rtk_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pP
* RT_ERR_NULL_POINTER
* Note:
* Clear operation effect loop_enter and loop_leave only, other field in
* the structure are don't care. Loop status cab't be clean.
* the structure are don't care. Loop status can't be clean.
*/
rtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus)
{

10
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c
View File

@ -152,7 +152,7 @@ static rtk_switch_halCtrl_t rtl8370b_hal_Ctrl =
/* Minimum physical port number */
0,
/* Maxmum physical port number */
/* Maximum physical port number */
10,
/* Physical port mask */
@ -221,7 +221,7 @@ static rtk_switch_halCtrl_t rtl8364b_hal_Ctrl =
/* Minimum physical port number */
0,
/* Maxmum physical port number */
/* Maximum physical port number */
7,
/* Physical port mask */
@ -290,7 +290,7 @@ static rtk_switch_halCtrl_t rtl8363sc_vb_hal_Ctrl =
/* Minimum physical port number */
0,
/* Maxmum physical port number */
/* Maximum physical port number */
7,
/* Physical port mask */
@ -1215,7 +1215,7 @@ rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask)
/* Function Name:
* rtk_switch_portmask_L2P_get
* Description:
* Get physicl portmask from logical portmask
* Get physical portmask from logical portmask
* Input:
* pLogicalPmask - logical port mask
* Output:
@ -1351,7 +1351,7 @@ rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask)
/* Function Name:
* rtk_switch_init
* Description:
* Set chip to default configuration enviroment
* Set chip to default configuration environment
* Input:
* None
* Output:

34
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c
View File

@ -173,7 +173,7 @@ static void _rtl8367c_aclActStUser2Smi(rtl8367c_acl_act_t *pAclUser, rtk_uint16
/* Function Name:
* rtl8367c_setAsicAcl
* Description:
* Set port acl function enable/disable
* Set port ACL function enable/disable
* Input:
* port - Physical port number (0~10)
* enabled - 1: enabled, 0: disabled
@ -196,7 +196,7 @@ ret_t rtl8367c_setAsicAcl(rtk_uint32 port, rtk_uint32 enabled)
/* Function Name:
* rtl8367c_getAsicAcl
* Description:
* Get port acl function enable/disable
* Get port ACL function enable/disable
* Input:
* port - Physical port number (0~10)
* enabled - 1: enabled, 0: disabled
@ -219,7 +219,7 @@ ret_t rtl8367c_getAsicAcl(rtk_uint32 port, rtk_uint32* pEnabled)
/* Function Name:
* rtl8367c_setAsicAclUnmatchedPermit
* Description:
* Set port acl function unmatched permit action
* Set port ACL function unmatched permit action
* Input:
* port - Physical port number (0~10)
* enabled - 1: enabled, 0: disabled
@ -242,7 +242,7 @@ ret_t rtl8367c_setAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32 enabled)
/* Function Name:
* rtl8367c_getAsicAclUnmatchedPermit
* Description:
* Get port acl function unmatched permit action
* Get port ACL function unmatched permit action
* Input:
* port - Physical port number (0~10)
* enabled - 1: enabled, 0: disabled
@ -266,10 +266,10 @@ ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled)
/* Function Name:
* rtl8367c_setAsicAclRule
* Description:
* Set acl rule content
* Set ACL rule content
* Input:
* index - ACL rule index (0-95) of 96 ACL rules
* pAclRule - ACL rule stucture for setting
* pAclRule - ACL rule structure for setting
* Output:
* None
* Return:
@ -278,8 +278,8 @@ ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled)
* RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95)
* Note:
* System supported 95 shared 289-bit ACL ingress rule. Index was available at range 0-95 only.
* If software want to modify ACL rule, the ACL function should be disable at first or unspecify
* acl action will be executed.
* If software want to modify ACL rule, the ACL function should be disabled at first or unspecified
* ACL action will be executed.
* One ACL rule structure has three parts setting:
* Bit 0-147 Data Bits of this Rule
* Bit 148 Valid Bit
@ -410,10 +410,10 @@ ret_t rtl8367c_setAsicAclRule(rtk_uint32 index, rtl8367c_aclrule* pAclRule)
/* Function Name:
* rtl8367c_getAsicAclRule
* Description:
* Get acl rule content
* Get ACL rule content
* Input:
* index - ACL rule index (0-63) of 64 ACL rules
* pAclRule - ACL rule stucture for setting
* pAclRule - ACL rule structure for setting
* Output:
* None
* Return:
@ -588,7 +588,7 @@ ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot)
* Set fields of a ACL Template
* Input:
* index - ACL template index(0~4)
* pAclType - ACL type stucture for setting
* pAclType - ACL type structure for setting
* Output:
* None
* Return:
@ -598,7 +598,7 @@ ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot)
* Note:
* The API can set type field of the 5 ACL rule templates.
* Each type has 8 fields. One field means what data in one field of a ACL rule means
* 8 fields of ACL rule 0~95 is descripted by one type in ACL group
* 8 fields of ACL rule 0~95 is described by one type in ACL group
*/
ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAclType)
{
@ -630,7 +630,7 @@ ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAcl
* Get fields of a ACL Template
* Input:
* index - ACL template index(0~4)
* pAclType - ACL type stucture for setting
* pAclType - ACL type structure for setting
* Output:
* None
* Return:
@ -669,7 +669,7 @@ ret_t rtl8367c_getAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t *pAcl
* Set ACL rule matched Action
* Input:
* index - ACL rule index (0-95) of 96 ACL rules
* pAclAct - ACL action stucture for setting
* pAclAct - ACL action structure for setting
* Output:
* None
* Return:
@ -734,7 +734,7 @@ ret_t rtl8367c_setAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t* pAclAct)
* Get ACL rule matched Action
* Input:
* index - ACL rule index (0-95) of 96 ACL rules
* pAclAct - ACL action stucture for setting
* pAclAct - ACL action structure for setting
* Output:
* None
* Return:
@ -1137,7 +1137,7 @@ ret_t rtl8367c_getAsicAclIpRange(rtk_uint32 index, rtk_uint32* pType, ipaddr_t*
/* Function Name:
* rtl8367c_setAsicAclGpioPolarity
* Description:
* Set ACL Goip control palarity
* Set ACL Goip control polarity
* Input:
* polarity - 1: High, 0: Low
* Output:
@ -1155,7 +1155,7 @@ ret_t rtl8367c_setAsicAclGpioPolarity(rtk_uint32 polarity)
/* Function Name:
* rtl8367c_getAsicAclGpioPolarity
* Description:
* Get ACL Goip control palarity
* Get ACL Goip control polarity
* Input:
* pPolarity - 1: High, 0: Low
* Output:

26
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c
View File

@ -18,7 +18,7 @@
/* Function Name:
* rtl8367c_setAsicCputagEnable
* Description:
* Set cpu tag function enable/disable
* Set CPU tag function enable/disable
* Input:
* enabled - 1: enabled, 0: disabled
* Output:
@ -41,7 +41,7 @@ ret_t rtl8367c_setAsicCputagEnable(rtk_uint32 enabled)
/* Function Name:
* rtl8367c_getAsicCputagEnable
* Description:
* Get cpu tag function enable/disable
* Get CPU tag function enable/disable
* Input:
* pEnabled - 1: enabled, 0: disabled
* Output:
@ -59,7 +59,7 @@ ret_t rtl8367c_getAsicCputagEnable(rtk_uint32 *pEnabled)
/* Function Name:
* rtl8367c_setAsicCputagTrapPort
* Description:
* Set cpu tag trap port
* Set CPU tag trap port
* Input:
* port - port number
* Output:
@ -91,7 +91,7 @@ ret_t rtl8367c_setAsicCputagTrapPort(rtk_uint32 port)
/* Function Name:
* rtl8367c_getAsicCputagTrapPort
* Description:
* Get cpu tag trap port
* Get CPU tag trap port
* Input:
* pPort - port number
* Output:
@ -248,9 +248,9 @@ ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNe
/* Function Name:
* rtl8367c_setAsicCputagPosition
* Description:
* Set cpu tag insert position
* Set CPU tag insert position
* Input:
* postion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default)
* position - 1: After entire packet(before CRC field), 0: After MAC_SA (Default)
* Output:
* None
* Return:
@ -259,14 +259,14 @@ ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNe
* Note:
* None
*/
ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion)
ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position)
{
return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, postion);
return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, position);
}
/* Function Name:
* rtl8367c_getAsicCputagPosition
* Description:
* Get cpu tag insert position
* Get CPU tag insert position
* Input:
* pPostion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default)
* Output:
@ -285,7 +285,7 @@ ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion)
/* Function Name:
* rtl8367c_setAsicCputagMode
* Description:
* Set cpu tag mode
* Set CPU tag mode
* Input:
* mode - 1: 4bytes mode, 0: 8bytes mode
* Output:
@ -308,7 +308,7 @@ ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode)
/* Function Name:
* rtl8367c_getAsicCputagMode
* Description:
* Get cpu tag mode
* Get CPU tag mode
* Input:
* pMode - 1: 4bytes mode, 0: 8bytes mode
* Output:
@ -326,7 +326,7 @@ ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode)
/* Function Name:
* rtl8367c_setAsicCputagRxMinLength
* Description:
* Set cpu tag mode
* Set CPU tag mode
* Input:
* mode - 1: 64bytes, 0: 72bytes
* Output:
@ -349,7 +349,7 @@ ret_t rtl8367c_setAsicCputagRxMinLength(rtk_uint32 mode)
/* Function Name:
* rtl8367c_getAsicCputagRxMinLength
* Description:
* Get cpu tag mode
* Get CPU tag mode
* Input:
* pMode - 1: 64bytes, 0: 72bytes
* Output:

18
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c
View File

@ -100,7 +100,7 @@ ret_t rtl8367c_getAsicEavMacAddress(ether_addr_t *pMac)
* Description:
* Set PTP parser tag TPID.
* Input:
* outerTag - outter tag TPID
* outerTag - outer tag TPID
* innerTag - inner tag TPID
* Output:
* None
@ -128,7 +128,7 @@ ret_t rtl8367c_setAsicEavTpid(rtk_uint32 outerTag, rtk_uint32 innerTag)
* Input:
* None
* Output:
* pOuterTag - outter tag TPID
* pOuterTag - outer tag TPID
* pInnerTag - inner tag TPID
* Return:
* RT_ERR_OK - Success
@ -161,7 +161,7 @@ ret_t rtl8367c_getAsicEavTpid(rtk_uint32* pOuterTag, rtk_uint32* pInnerTag)
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
* The time granuality is 8 nano seconds.
* The time granularity is 8 nano seconds.
*/
ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond)
{
@ -218,7 +218,7 @@ ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond)
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
* The time granuality is 8 nano seconds.
* The time granularity is 8 nano seconds.
*/
ret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond)
{
@ -265,7 +265,7 @@ ret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond)
* Description:
* Set PTP system time adjust
* Input:
* type - incresae or decrease
* type - increase or decrease
* second - seconds
* nanoSecond - nano seconds
* Output:
@ -481,7 +481,7 @@ ret_t rtl8367c_getAsicEavInterruptStatus(rtk_uint32* pIms)
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
* This API can be used to clear ASIC interrupt status and register will be cleared by writting 1.
* This API can be used to clear ASIC interrupt status and register will be cleared by writing 1.
* [0]:TX_SYNC,
* [1]:TX_DELAY,
* [2]:TX_PDELAY_REQ,
@ -570,7 +570,7 @@ ret_t rtl8367c_getAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32* pIms)
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number
* Note:
* If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping
* If EAV function is enabled, PTP event message packet will be attached PTP timestamp for trapping
*/
ret_t rtl8367c_setAsicEavPortEnable(rtk_uint32 port, rtk_uint32 enabled)
{
@ -646,7 +646,7 @@ ret_t rtl8367c_getAsicEavPortEnable(rtk_uint32 port, rtk_uint32 *pEnabled)
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
* The time granuality is 8 nano seconds.
* The time granularity is 8 nano seconds.
*/
ret_t rtl8367c_getAsicEavPortTimeStamp(rtk_uint32 port, rtk_uint32 type, rtl8367c_ptp_time_stamp_t* timeStamp)
{
@ -796,7 +796,7 @@ ret_t rtl8367c_getAsicEavTrap(rtk_uint32 port, rtk_uint32 *pEnabled)
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number
* Note:
* If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping
* If EAV function is enabled, PTP event message packet will be attached PTP timestamp for trapping
*/
ret_t rtl8367c_setAsicEavEnable(rtk_uint32 port, rtk_uint32 enabled)
{

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c
View File

@ -55,7 +55,7 @@ ret_t rtl8367c_getAsicFlowControlSelect(rtk_uint32 *pSelect)
/* Function Name:
* rtl8367c_setAsicFlowControlJumboMode
* Description:
* Set Jumbo threhsold for flow control
* Set Jumbo threshold for flow control
* Input:
* enabled - Jumbo mode flow control 1: Enable 0:Disable
* Output:
@ -73,7 +73,7 @@ ret_t rtl8367c_setAsicFlowControlJumboMode(rtk_uint32 enabled)
/* Function Name:
* rtl8367c_getAsicFlowControlJumboMode
* Description:
* Get Jumbo threhsold for flow control
* Get Jumbo threshold for flow control
* Input:
* pEnabled - Jumbo mode flow control 1: Enable 0:Disable
* Output:

16
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c
View File

@ -11,7 +11,7 @@
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
* Feature : Green ethernet related functions
* Feature : Green Ethernet related functions
*
*/
#include <rtl8367c_asicdrv_green.h>
@ -22,7 +22,7 @@
* Get per-Port ingress page usage per second
* Input:
* port - Physical port number (0~7)
* pPage - page number of ingress packet occuping per second
* pPage - page number of ingress packet occurring per second
* Output:
* None
* Return:
@ -30,7 +30,7 @@
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number
* Note:
* Ingress traffic occuping page number per second for high layer green feature usage
* Ingress traffic occurring page number per second for high layer green feature usage
*/
ret_t rtl8367c_getAsicGreenPortPage(rtk_uint32 port, rtk_uint32* pPage)
{
@ -134,7 +134,7 @@ ret_t rtl8367c_setAsicGreenHighPriorityTraffic(rtk_uint32 port)
* Get indicator which ASIC had received high priority traffic or not
* Input:
* port - Physical port number (0~7)
* pIndicator - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking priod
* pIndicator - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking period
* Output:
* None
* Return:
@ -153,14 +153,14 @@ ret_t rtl8367c_getAsicGreenHighPriorityTraffic(rtk_uint32 port, rtk_uint32* pInd
}
/*
@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green ethernet function.
@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green Ethernet function.
@parm rtk_uint32 | green | Green feature function usage 1:enable 0:disable.
@rvalue RT_ERR_OK | Success.
@rvalue RT_ERR_SMI | SMI access error.
@comm
The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic
detect the cable length and then select different power mode for best performance with minimums power consumption. Link down
ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled.
ports will enter power saving mode in 10 seconds after the cable disconnected if power saving function is enabled.
*/
ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green)
{
@ -286,14 +286,14 @@ ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green)
}
/*
@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green ethernet function.
@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green Ethernet function.
@parm rtk_uint32 | *green | Green feature function usage 1:enable 0:disable.
@rvalue RT_ERR_OK | Success.
@rvalue RT_ERR_SMI | SMI access error.
@comm
The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic
detect the cable length and then select different power mode for best performance with minimums power consumption. Link down
ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled.
ports will enter power saving mode in 10 seconds after the cable disconnected if power saving function is enabled.
*/
ret_t rtl8367c_getAsicGreenEthernet(rtk_uint32 port, rtk_uint32* green)
{

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c
View File

@ -30,7 +30,7 @@
* RT_ERR_SMI - SMI access error
* RT_ERR_OUT_OF_RANGE - input parameter out of range
* Note:
* System support 16 user defined field selctors.
* System support 16 user defined field selectors.
* Each selector can be enabled or disable. User can defined retrieving 16-bits in many predefiend
* standard l2/l3/l4 payload.
*/

20
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c
View File

@ -429,8 +429,8 @@ ret_t rtl8367c_setAsicIGMPRobVar(rtk_uint32 rob_var)
if(rob_var > RTL8367C_MAX_ROB_VAR)
return RT_ERR_OUT_OF_RANGE;
/* Bourstness variable */
retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, rob_var);
/* Robustness variable */
retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, rob_var);
if(retVal != RT_ERR_OK)
return retVal;
@ -456,8 +456,8 @@ ret_t rtl8367c_getAsicIGMPRobVar(rtk_uint32 *prob_var)
ret_t retVal;
rtk_uint32 value;
/* Bourstness variable */
retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, &value);
/* Robustness variable */
retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, &value);
if(retVal != RT_ERR_OK)
return retVal;
@ -1813,7 +1813,7 @@ ret_t rtl8367c_getAsicIGMPReportLeaveFlood(rtk_uint32 *pFlood)
/* Function Name:
* rtl8367c_setAsicIGMPDropLeaveZero
* Description:
* Set the function of droppping Leave packet with group IP = 0.0.0.0
* Set the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* drop - 1: Drop, 0:Bypass
* Output:
@ -1838,7 +1838,7 @@ ret_t rtl8367c_setAsicIGMPDropLeaveZero(rtk_uint32 drop)
/* Function Name:
* rtl8367c_getAsicIGMPDropLeaveZero
* Description:
* Get the function of droppping Leave packet with group IP = 0.0.0.0
* Get the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* None
* Output:
@ -1865,7 +1865,7 @@ ret_t rtl8367c_getAsicIGMPDropLeaveZero(rtk_uint32 *pDrop)
/* Function Name:
* rtl8367c_setAsicIGMPBypassStormCTRL
* Description:
* Set the function of bypass strom control for IGMP/MLD packet
* Set the function of bypass storm control for IGMP/MLD packet
* Input:
* bypass - 1: Bypass, 0:not bypass
* Output:
@ -1890,7 +1890,7 @@ ret_t rtl8367c_setAsicIGMPBypassStormCTRL(rtk_uint32 bypass)
/* Function Name:
* rtl8367c_getAsicIGMPBypassStormCTRL
* Description:
* Set the function of bypass strom control for IGMP/MLD packet
* Set the function of bypass storm control for IGMP/MLD packet
* Input:
* None
* Output:
@ -1944,7 +1944,7 @@ ret_t rtl8367c_setAsicIGMPIsoLeaky(rtk_uint32 leaky)
* Description:
* Get Port Isolation leaky for IGMP/MLD packet
* Input:
* Noen
* None
* Output:
* pLeaky - 1: Leaky, 0:not leaky
* Return:
@ -1996,7 +1996,7 @@ ret_t rtl8367c_setAsicIGMPVLANLeaky(rtk_uint32 leaky)
* Description:
* Get VLAN leaky for IGMP/MLD packet
* Input:
* Noen
* None
* Output:
* pLeaky - 1: Leaky, 0:not leaky
* Return:

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c
View File

@ -128,7 +128,7 @@ ret_t rtl8367c_getAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32* pBandwid
/* Function Name:
* rtl8367c_setAsicPortIngressBandwidthBypass
* Description:
* Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP
* Set ingress bandwidth control bypass 8899, RMA 01-80-C2-00-00-xx and IGMP
* Input:
* enabled - 1: enabled, 0: disabled
* Output:
@ -146,7 +146,7 @@ ret_t rtl8367c_setAsicPortIngressBandwidthBypass(rtk_uint32 enabled)
/* Function Name:
* rtl8367c_getAsicPortIngressBandwidthBypass
* Description:
* Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP
* Set ingress bandwidth control bypass 8899, RMA 01-80-C2-00-00-xx and IGMP
* Input:
* pEnabled - 1: enabled, 0: disabled
* Output:

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c
View File

@ -99,10 +99,10 @@ ret_t rtl8367c_getAsicInterruptMask(rtk_uint32* pImr)
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
* This API can be used to clear ASIC interrupt status and register will be cleared by writting 1.
* This API can be used to clear ASIC interrupt status and register will be cleared by writing 1.
* [0]:Link change,
* [1]:Share meter exceed,
* [2]:Learn number overed,
* [2]:Learn number over,
* [3]:Speed Change,
* [4]:Tx special congestion
* [5]:1 second green feature

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c
View File

@ -607,7 +607,7 @@ ret_t rtl8367c_getAsicLedSerialModeConfig(rtk_uint32 *active, rtk_uint32 *serimo
/*
@func ret_t | rtl8367c_setAsicLedOutputEnable | Set LED output enable
@parm rtk_uint32 | enabled | enable or disalbe.
@parm rtk_uint32 | enabled | enable or disable.
@rvalue RT_ERR_OK | Success.
@rvalue RT_ERR_SMI | SMI access error.
@rvalue RT_ERR_INPUT | Invalid input value.

60
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c
View File

@ -207,7 +207,7 @@ static void _rtl8367c_fdbStSmi2User( rtl8367c_luttb *pLutSt, rtk_uint16 *pFdbSmi
/* Function Name:
* rtl8367c_setAsicLutIpMulticastLookup
* Description:
* Set Lut IP multicast lookup function
* Set LUT IP multicast lookup function
* Input:
* enabled - 1: enabled, 0: disabled
* Output:
@ -225,7 +225,7 @@ ret_t rtl8367c_setAsicLutIpMulticastLookup(rtk_uint32 enabled)
/* Function Name:
* rtl8367c_getAsicLutIpMulticastLookup
* Description:
* Get Lut IP multicast lookup function
* Get LUT IP multicast lookup function
* Input:
* pEnabled - 1: enabled, 0: disabled
* Output:
@ -244,7 +244,7 @@ ret_t rtl8367c_getAsicLutIpMulticastLookup(rtk_uint32* pEnabled)
/* Function Name:
* rtl8367c_setAsicLutIpMulticastLookup
* Description:
* Set Lut IP multicast + VID lookup function
* Set LUT IP multicast + VID lookup function
* Input:
* enabled - 1: enabled, 0: disabled
* Output:
@ -263,7 +263,7 @@ ret_t rtl8367c_setAsicLutIpMulticastVidLookup(rtk_uint32 enabled)
/* Function Name:
* rtl8367c_getAsicLutIpMulticastVidLookup
* Description:
* Get Lut IP multicast lookup function
* Get LUT IP multicast lookup function
* Input:
* pEnabled - 1: enabled, 0: disabled
* Output:
@ -282,7 +282,7 @@ ret_t rtl8367c_getAsicLutIpMulticastVidLookup(rtk_uint32* pEnabled)
/* Function Name:
* rtl8367c_setAsicLutIpLookupMethod
* Description:
* Set Lut IP lookup hash with DIP or {DIP,SIP} pair
* Set LUT IP lookup hash with DIP or {DIP,SIP} pair
* Input:
* type - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash.
* 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash.
@ -301,7 +301,7 @@ ret_t rtl8367c_setAsicLutIpLookupMethod(rtk_uint32 type)
/* Function Name:
* rtl8367c_getAsicLutIpLookupMethod
* Description:
* Get Lut IP lookup hash with DIP or {DIP,SIP} pair
* Get LUT IP lookup hash with DIP or {DIP,SIP} pair
* Input:
* pType - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash.
* 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash.
@ -320,10 +320,10 @@ ret_t rtl8367c_getAsicLutIpLookupMethod(rtk_uint32* pType)
/* Function Name:
* rtl8367c_setAsicLutAgeTimerSpeed
* Description:
* Set LUT agging out speed
* Set LUT ageing out speed
* Input:
* timer - Agging out timer 0:Has been aged out
* speed - Agging out speed 0-fastest 3-slowest
* timer - Ageing out timer 0:Has been aged out
* speed - Ageing out speed 0-fastest 3-slowest
* Output:
* None
* Return:
@ -346,10 +346,10 @@ ret_t rtl8367c_setAsicLutAgeTimerSpeed(rtk_uint32 timer, rtk_uint32 speed)
/* Function Name:
* rtl8367c_getAsicLutAgeTimerSpeed
* Description:
* Get LUT agging out speed
* Get LUT ageing out speed
* Input:
* pTimer - Agging out timer 0:Has been aged out
* pSpeed - Agging out speed 0-fastest 3-slowest
* pTimer - Ageing out timer 0:Has been aged out
* pSpeed - Ageing out speed 0-fastest 3-slowest
* Output:
* None
* Return:
@ -378,7 +378,7 @@ ret_t rtl8367c_getAsicLutAgeTimerSpeed(rtk_uint32* pTimer, rtk_uint32* pSpeed)
/* Function Name:
* rtl8367c_setAsicLutCamTbUsage
* Description:
* Configure Lut CAM table usage
* Configure LUT CAM table usage
* Input:
* enabled - L2 CAM table usage 1: enabled, 0: disabled
* Output:
@ -400,7 +400,7 @@ ret_t rtl8367c_setAsicLutCamTbUsage(rtk_uint32 enabled)
/* Function Name:
* rtl8367c_getAsicLutCamTbUsage
* Description:
* Get Lut CAM table usage
* Get LUT CAM table usage
* Input:
* pEnabled - L2 CAM table usage 1: enabled, 0: disabled
* Output:
@ -439,7 +439,7 @@ ret_t rtl8367c_getAsicLutCamTbUsage(rtk_uint32* pEnabled)
* Note:
* None
*/
/*修改: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/
/*modification: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/
ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number)
{
if(port > RTL8367C_PORTIDMAX)
@ -470,7 +470,7 @@ ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number)
* Note:
* None
*/
/*修改: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/
/*modification: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/
ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber)
{
if(port > RTL8367C_PORTIDMAX)
@ -498,7 +498,7 @@ ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber)
* Note:
* None
*/
/*修改: RTL8367C_LUT_LEARNLIMITMAX*/
/*modification: RTL8367C_LUT_LEARNLIMITMAX*/
ret_t rtl8367c_setAsicSystemLutLearnLimitNo(rtk_uint32 number)
{
if(number > RTL8367C_LUT_LEARNLIMITMAX)
@ -632,7 +632,7 @@ ret_t rtl8367c_getAsicSystemLutLearnOverAct(rtk_uint32 *pAction)
* Note:
* None
*/
/*修改: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/
/*modification: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/
ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask)
{
ret_t retVal;
@ -666,7 +666,7 @@ ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask)
* Note:
* None
*/
/*修改: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/
/*modification: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/
ret_t rtl8367c_getAsicSystemLutLearnPortMask(rtk_uint32 *pPortmask)
{
rtk_uint32 tmpmask;
@ -966,7 +966,7 @@ ret_t rtl8367c_getAsicL2LookupTb(rtk_uint32 method, rtl8367c_luttb *pL2Table)
* Note:
* None
*/
/*修改RTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not contnious, wait for updating of base.h*/
/*modification:RTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not continuous, wait for updating of base.h*/
ret_t rtl8367c_getAsicLutLearnNo(rtk_uint32 port, rtk_uint32* pNumber)
{
ret_t retVal;
@ -1047,7 +1047,7 @@ ret_t rtl8367c_getAsicLutFlushAllStatus(rtk_uint32 *pBusyStatus)
* Note:
* None
*/
/*port8~port10的设置在另外一个register, wait for updating of base.h, reg.h*/
/*port8~port10 setup is done in a separate register, wait for updating of base.h, reg.h*/
ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask)
{
ret_t retVal;
@ -1079,7 +1079,7 @@ ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask)
* Note:
* None
*/
/*port8~port10的设置在另外一个register, wait for updating of base.h, reg.h*/
/*port8~port10 setup is done in a separate register, wait for updating of base.h, reg.h*/
ret_t rtl8367c_getAsicLutForceFlushStatus(rtk_uint32 *pPortmask)
{
rtk_uint32 tmpMask;
@ -1142,7 +1142,7 @@ ret_t rtl8367c_getAsicLutFlushMode(rtk_uint32* pMode)
* Description:
* Get L2 LUT flush type
* Input:
* type - 0: dynamice unicast; 1: both dynamic and static unicast entry
* type - 0: dynamic unicast; 1: both dynamic and static unicast entry
* Output:
* None
* Return:
@ -1160,7 +1160,7 @@ ret_t rtl8367c_setAsicLutFlushType(rtk_uint32 type)
* Description:
* Set L2 LUT flush type
* Input:
* pType - 0: dynamice unicast; 1: both dynamic and static unicast entry
* pType - 0: dynamic unicast; 1: both dynamic and static unicast entry
* Output:
* None
* Return:
@ -1271,7 +1271,7 @@ ret_t rtl8367c_getAsicLutFlushFid(rtk_uint32* pFid)
* Note:
* None
*/
/*修改RTL8367C_PORTIDMAX*/
/*modification:RTL8367C_PORTIDMAX*/
ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled)
{
if(port > RTL8367C_PORTIDMAX)
@ -1295,7 +1295,7 @@ ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled)
* Note:
* None
*/
/*修改RTL8367C_PORTIDMAX*/
/*modification:RTL8367C_PORTIDMAX*/
ret_t rtl8367c_getAsicLutDisableAging(rtk_uint32 port, rtk_uint32 *pDisabled)
{
if(port > RTL8367C_PORTIDMAX)
@ -1504,9 +1504,9 @@ ret_t rtl8367c_getAsicLutLinkDownForceAging(rtk_uint32 *pEnable)
/* Function Name:
* rtl8367c_setAsicLutIpmcFwdRouterPort
* Description:
* Set IPMC packet forward to rounter port also or not
* Set IPMC packet forward to router port also or not
* Input:
* enable - 1: Inlcude router port, 0, exclude router port
* enable - 1: Include router port, 0, exclude router port
* Output:
* None
* Return:
@ -1527,11 +1527,11 @@ ret_t rtl8367c_setAsicLutIpmcFwdRouterPort(rtk_uint32 enable)
/* Function Name:
* rtl8367c_getAsicLutIpmcFwdRouterPort
* Description:
* Get IPMC packet forward to rounter port also or not
* Get IPMC packet forward to router port also or not
* Input:
* None
* Output:
* pEnable - 1: Inlcude router port, 0, exclude router port
* pEnable - 1: Include router port, 0, exclude router port
* Return:
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error

18
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c
View File

@ -22,7 +22,7 @@
* Reset global/queue manage or per-port MIB counter
* Input:
* greset - Global reset
* qmreset - Queue maganement reset
* qmreset - Queue management reset
* portmask - Port reset mask
* Output:
* None
@ -59,7 +59,7 @@ ret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rt
* Input:
* port - Physical port number (0~7)
* mibIdx - MIB counter index
* pCounter - MIB retrived counter
* pCounter - MIB retrieved counter
* Output:
* None
* Return:
@ -69,9 +69,9 @@ ret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rt
* RT_ERR_BUSYWAIT_TIMEOUT - MIB is busy at retrieving
* RT_ERR_STAT_CNTR_FAIL - MIB is resetting
* Note:
* Before MIBs counter retrieving, writting accessing address to ASIC at first and check the MIB
* Before MIBs counter retrieving, writing accessing address to ASIC at first and check the MIB
* control register status. If busy bit of MIB control is set, that means MIB counter have been
* waiting for preparing, then software must wait atfer this busy flag reset by ASIC. This driver
* waiting for preparing, then software must wait after this busy flag reset by ASIC. This driver
* did not recycle reading user desired counter. Software must use driver again to get MIB counter
* if return value is not RT_ERR_OK.
*/
@ -124,7 +124,7 @@ ret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port, RTL8367C_MIBCOUNTER mibIdx, r
/*writing access counter address first*/
/*This address is SRAM address, and SRAM address = MIB register address >> 2*/
/*then ASIC will prepare 64bits counter wait for being retrived*/
/*then ASIC will prepare 64bits counter wait for being retrieved*/
/*Write Mib related address to access control register*/
retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2));
if(retVal != RT_ERR_OK)
@ -183,7 +183,7 @@ ret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port, RTL8367C_MIBCOUNTER mibIdx, r
/* Function Name:
* rtl8367c_getAsicMIBsLogCounter
* Description:
* Get MIBs Loggin counter
* Get MIBs Logging counter
* Input:
* index - The index of 32 logging counter (0 ~ 31)
* Output:
@ -260,7 +260,7 @@ ret_t rtl8367c_getAsicMIBsLogCounter(rtk_uint32 index, rtk_uint32 *pCounter)
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
* Software need to check this control register atfer doing port resetting or global resetting
* Software need to check this control register after doing port resetting or global resetting
*/
ret_t rtl8367c_getAsicMIBsControl(rtk_uint32* pMask)
{
@ -513,7 +513,7 @@ ret_t rtl8367c_setAsicMIBsResetLoggingCounter(rtk_uint32 index)
/* Function Name:
* rtl8367c_setAsicMIBsLength
* Description:
* Set MIB length couting mode
* Set MIB length counting mode
* Input:
* txLengthMode - 0: tag length doesn't be counted. 1: tag length is counted.
* rxLengthMode - 0: tag length doesn't be counted. 1: tag length is counted.
@ -542,7 +542,7 @@ ret_t rtl8367c_setAsicMIBsLength(rtk_uint32 txLengthMode, rtk_uint32 rxLengthMod
/* Function Name:
* rtl8367c_setAsicMIBsLength
* Description:
* Set MIB length couting mode
* Set MIB length counting mode
* Input:
* None.
* Output:

8
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c
View File

@ -951,7 +951,7 @@ rtk_uint8 Sgmii_Init[SGMII_INIT_SIZE] = {
* Set UNDA behavior
* Input:
* port - port ID
* behavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding
* behavior - 0: flooding to unknown DA portmask; 1: drop; 2:trap; 3: flooding
* Output:
* None
* Return:
@ -981,7 +981,7 @@ ret_t rtl8367c_setAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 behavior
* Input:
* port - port ID
* Output:
* pBehavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding
* pBehavior - 0: flooding to unknown DA portmask; 1: drop; 2:trap; 3: flooding
* Return:
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
@ -3724,7 +3724,7 @@ ret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode)
return retVal;
/*
1: MAC link = SGMII SerDes link
0: MAC link = SGMII config link £¨cfg_sgmii_link£©
0: MAC link = SGMII config link (cfg_sgmii_link)
*/
if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK)
return retVal;
@ -4032,7 +4032,7 @@ ret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode)
if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK)
return retVal;
/*select MAC link source when port6/7 be set sgmii mode £¨cfg_sgmii_link£©*/
/*select MAC link source when port6/7 be set sgmii mode (cfg_sgmii_link)*/
if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK)
return retVal;
}

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c
View File

@ -11,7 +11,7 @@
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
* Feature : Qos related functions
* Feature : QoS related functions
*
*/

8
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c
View File

@ -19,7 +19,7 @@
/* Function Name:
* rtl8367c_setAsicLeakyBucketParameter
* Description:
* Set Leaky Bucket Paramters
* Set Leaky Bucket Parameters
* Input:
* tick - Tick is used for time slot size unit
* token - Token is used for adding budget in each time slot
@ -55,7 +55,7 @@ ret_t rtl8367c_setAsicLeakyBucketParameter(rtk_uint32 tick, rtk_uint32 token)
/* Function Name:
* rtl8367c_getAsicLeakyBucketParameter
* Description:
* Get Leaky Bucket Paramters
* Get Leaky Bucket Parameters
* Input:
* tick - Tick is used for time slot size unit
* token - Token is used for adding budget in each time slot
@ -166,7 +166,7 @@ ret_t rtl8367c_getAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *apri
* Set per-port APR enable
* Input:
* port - Physical port number (0~7)
* aprEnable - APR enable seting 1:enable 0:disable
* aprEnable - APR enable setting 1:enable 0:disable
* Output:
* None
* Return:
@ -193,7 +193,7 @@ ret_t rtl8367c_setAsicAprEnable(rtk_uint32 port, rtk_uint32 aprEnable)
* Get per-port APR enable
* Input:
* port - Physical port number (0~7)
* aprEnable - APR enable seting 1:enable 0:disable
* aprEnable - APR enable setting 1:enable 0:disable
* Output:
* None
* Return:

16
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c
View File

@ -140,7 +140,7 @@ ret_t rtl8367c_getAsicSvlanUplinkPortMask(rtk_uint32* pPortmask)
* RT_ERR_SMI - SMI access error
* Note:
* Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200
* for Q-in-Q SLAN design. User can set mathced ether type as service provider supported protocol
* for Q-in-Q SLAN design. User can set matched ether type as service provider supported protocol
*/
ret_t rtl8367c_setAsicSvlanTpid(rtk_uint32 protocolType)
{
@ -344,7 +344,7 @@ ret_t rtl8367c_getAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32* pIndex)
/* Function Name:
* rtl8367c_setAsicSvlanIngressUntag
* Description:
* Set action received un-Stag frame from unplink port
* Set action received un-Stag frame from uplink port
* Input:
* mode - 0:Drop 1:Trap 2:Assign SVLAN
* Output:
@ -362,7 +362,7 @@ ret_t rtl8367c_setAsicSvlanIngressUntag(rtk_uint32 mode)
/* Function Name:
* rtl8367c_getAsicSvlanIngressUntag
* Description:
* Get action received un-Stag frame from unplink port
* Get action received un-Stag frame from uplink port
* Input:
* pMode - 0:Drop 1:Trap 2:Assign SVLAN
* Output:
@ -380,7 +380,7 @@ ret_t rtl8367c_getAsicSvlanIngressUntag(rtk_uint32* pMode)
/* Function Name:
* rtl8367c_setAsicSvlanIngressUnmatch
* Description:
* Set action received unmatched Stag frame from unplink port
* Set action received unmatched Stag frame from uplink port
* Input:
* mode - 0:Drop 1:Trap 2:Assign SVLAN
* Output:
@ -398,7 +398,7 @@ ret_t rtl8367c_setAsicSvlanIngressUnmatch(rtk_uint32 mode)
/* Function Name:
* rtl8367c_getAsicSvlanIngressUnmatch
* Description:
* Get action received unmatched Stag frame from unplink port
* Get action received unmatched Stag frame from uplink port
* Input:
* pMode - 0:Drop 1:Trap 2:Assign SVLAN
* Output:
@ -417,7 +417,7 @@ ret_t rtl8367c_getAsicSvlanIngressUnmatch(rtk_uint32* pMode)
/* Function Name:
* rtl8367c_setAsicSvlanEgressUnassign
* Description:
* Set unplink stream without egress SVID action
* Set uplink stream without egress SVID action
* Input:
* enabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID
* Output:
@ -435,7 +435,7 @@ ret_t rtl8367c_setAsicSvlanEgressUnassign(rtk_uint32 enabled)
/* Function Name:
* rtl8367c_getAsicSvlanEgressUnassign
* Description:
* Get unplink stream without egress SVID action
* Get uplink stream without egress SVID action
* Input:
* pEnabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID
* Output:
@ -580,7 +580,7 @@ ret_t rtl8367c_getAsicSvlanMemberConfiguration(rtk_uint32 index,rtl8367c_svlan_m
* RT_ERR_SMI - SMI access error
* RT_ERR_ENTRY_INDEX - Invalid entry index
* Note:
* ASIC will check upstream's VID and assign related SVID to mathed packet
* ASIC will check upstream's VID and assign related SVID to matched packet
*/
ret_t rtl8367c_setAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32 evid, rtk_uint32 portmask, rtk_uint32 svidx)
{

2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c
View File

@ -11,7 +11,7 @@
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
* Feature : Unkown multicast related functions
* Feature : Unknown multicast related functions
*
*/

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c
View File

@ -421,7 +421,7 @@ rtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData)
con = 0;
do {
con++;
_smi_readBit(1, &ACK); /* ACK for writting data [7:0] */
_smi_readBit(1, &ACK); /* ACK for writing data [7:0] */
} while ((ACK != 0) && (con < ack_timer));
if (ACK != 0) ret = RT_ERR_FAILED;
@ -430,7 +430,7 @@ rtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData)
con = 0;
do {
con++;
_smi_readBit(1, &ACK); /* ACK for writting data [15:8] */
_smi_readBit(1, &ACK); /* ACK for writing data [15:8] */
} while ((ACK != 0) && (con < ack_timer));
if (ACK != 0) ret = RT_ERR_FAILED;

8
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c
View File

@ -140,7 +140,7 @@ rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_coun
if (cntr_idx!=DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX)
return RT_ERR_STAT_INVALID_GLOBAL_CNTR;
if ((retVal = rtl8367c_getAsicMIBsCounter(0, cntr_idx, pCntr)) != RT_ERR_OK)
if ((retVal = rtl8367c_getAsicMIBsCounter(0, (RTL8367C_MIBCOUNTER)cntr_idx, pCntr)) != RT_ERR_OK)
return retVal;
return RT_ERR_OK;
@ -172,7 +172,7 @@ rtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs)
if(NULL == pGlobal_cntrs)
return RT_ERR_NULL_POINTER;
if ((retVal = rtl8367c_getAsicMIBsCounter(0,DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK)
if ((retVal = rtl8367c_getAsicMIBsCounter(0, dot1dTpLearnedEntryDiscards, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK)
return retVal;
return RT_ERR_OK;
@ -265,7 +265,7 @@ static rtk_api_ret_t _get_asic_mib_idx(rtk_stat_port_type_t cnt_idx, RTL8367C_MI
* port - port id.
* cntr_idx - port counter index.
* Output:
* pCntr - MIB retrived counter.
* pCntr - MIB retrieved counter.
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
@ -592,7 +592,7 @@ rtk_api_ret_t rtk_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_len
/* Function Name:
* rtk_stat_lengthMode_get
* Description:
* Get Legnth mode.
* Get Length mode.
* Input:
* None.
* Output:

24
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c
View File

@ -279,7 +279,7 @@ rtk_api_ret_t rtk_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_stor
* RT_ERR_ENABLE - Invalid IFG parameter
* Note:
*
* This API can set per-port bypass stomr filter control frame type including RMA and igmp.
* This API can set per-port bypass storm filter control frame type including RMA and IGMP.
* The bypass frame type is as following:
* - BYPASS_BRG_GROUP,
* - BYPASS_FD_PAUSE,
@ -414,7 +414,7 @@ rtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable)
* RT_ERR_SMI - SMI access error
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* This API can get per-port bypass stomr filter control frame type including RMA and igmp.
* This API can get per-port bypass storm filter control frame type including RMA and IGMP.
* The bypass frame type is as following:
* - BYPASS_BRG_GROUP,
* - BYPASS_FD_PAUSE,
@ -526,7 +526,7 @@ rtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnabl
/* Function Name:
* rtk_rate_stormControlExtPortmask_set
* Description:
* Set externsion storm control port mask
* Set extension storm control port mask
* Input:
* pPortmask - port mask
* Output:
@ -562,7 +562,7 @@ rtk_api_ret_t rtk_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask)
/* Function Name:
* rtk_rate_stormControlExtPortmask_get
* Description:
* Set externsion storm control port mask
* Set extension storm control port mask
* Input:
* None
* Output:
@ -598,10 +598,10 @@ rtk_api_ret_t rtk_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask)
/* Function Name:
* rtk_rate_stormControlExtEnable_set
* Description:
* Set externsion storm control state
* Set extension storm control state
* Input:
* stormType - storm group type
* enable - externsion storm control state
* enable - extension storm control state
* Output:
* None
* Return:
@ -653,11 +653,11 @@ rtk_api_ret_t rtk_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormTyp
/* Function Name:
* rtk_rate_stormControlExtEnable_get
* Description:
* Get externsion storm control state
* Get extension storm control state
* Input:
* stormType - storm group type
* Output:
* pEnable - externsion storm control state
* pEnable - extension storm control state
* Return:
* RT_ERR_OK
* RT_ERR_FAILED
@ -707,10 +707,10 @@ rtk_api_ret_t rtk_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormTyp
/* Function Name:
* rtk_rate_stormControlExtMeterIdx_set
* Description:
* Set externsion storm control meter index
* Set extension storm control meter index
* Input:
* stormType - storm group type
* index - externsion storm control state
* index - extension storm control state
* Output:
* None
* Return:
@ -762,10 +762,10 @@ rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormT
/* Function Name:
* rtk_rate_stormControlExtMeterIdx_get
* Description:
* Get externsion storm control meter index
* Get extension storm control meter index
* Input:
* stormType - storm group type
* pIndex - externsion storm control state
* pIndex - extension storm control state
* Output:
* None
* Return:

40
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c
View File

@ -41,7 +41,7 @@ rtk_svlan_lookupType_t svlan_lookupType;
* RT_ERR_SMI - SMI access error
* Note:
* Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design.
* User can set mathced ether type as service provider supported protocol.
* User can set matched ether type as service provider supported protocol.
*/
rtk_api_ret_t rtk_svlan_init(void)
{
@ -250,7 +250,7 @@ rtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port)
* RT_ERR_INPUT - Invalid input parameter.
* Note:
* Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design.
* User can set mathced ether type as service provider supported protocol.
* User can set matched ether type as service provider supported protocol.
*/
rtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_svlan_tpid_t svlan_tag_id)
{
@ -391,8 +391,8 @@ rtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef)
* RT_ERR_PORT_MASK - Invalid portmask.
* RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full.
* Note:
* The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted
* to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup.
* The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted
* to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped by default setup.
* - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration.
* - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration.
* - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration.
@ -626,8 +626,8 @@ rtk_api_ret_t rtk_svlan_memberPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg
* RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted
* to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped.
* The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted
* to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped.
*/
rtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg)
{
@ -794,8 +794,8 @@ rtk_api_ret_t rtk_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_member
* RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted
* to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped.
* The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted
* to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped.
*/
rtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg)
{
@ -948,7 +948,7 @@ rtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid)
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can set system C2S configuration. ASIC will check upstream's VID and assign related
* SVID to mathed packet. There are 128 SVLAN C2S configurations.
* SVID to matched packet. There are 128 SVLAN C2S configurations.
*/
rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid)
{
@ -1011,7 +1011,7 @@ rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t
}
else
{
/* New svidx, remove src_port and find a new slot to add a new enrty */
/* New svidx, remove src_port and find a new slot to add a new entry */
pmsk = pmsk & ~(1 << phyPort);
if(pmsk == 0)
c2s_svidx = 0;
@ -1263,7 +1263,7 @@ rtk_api_ret_t rtk_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vl
* Note:
* The API can Get action of downstream Un-Stag packet. A SVID assigned
* to the un-stag is also retrieved by this API. The parameter pSvid is
* only refernced when the action is UNTAG_ASSIGN
* only referenced when the action is UNTAG_ASSIGN
*/
rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid)
{
@ -1313,8 +1313,8 @@ rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can configure action of downstream Un-match packet. A SVID assigned
* to the un-match is also supported by this API. The parameter od svid is
* only refernced when the action is set to UNMATCH_ASSIGN
* to the un-match is also supported by this API. The parameter of svid is
* only referenced when the action is set to UNMATCH_ASSIGN
*/
rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid)
{
@ -1379,7 +1379,7 @@ rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rt
* Note:
* The API can Get action of downstream Un-match packet. A SVID assigned
* to the un-match is also retrieved by this API. The parameter pSvid is
* only refernced when the action is UNMATCH_ASSIGN
* only referenced when the action is UNMATCH_ASSIGN
*/
rtk_api_ret_t rtk_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid)
{
@ -1567,7 +1567,7 @@ rtk_api_ret_t rtk_svlan_dmac_vidsel_get(rtk_port_t port, rtk_enable_t *pEnable)
* RT_ERR_OUT_OF_RANGE - input out of range.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast
* The API can set IP multicast to SVID configuration. If upstream packet is IPv4 multicast
* packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet.
* There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
@ -1662,7 +1662,7 @@ rtk_api_ret_t rtk_svlan_ipmc2s_add(ipaddr_t ipmc, ipaddr_t ipmcMsk,rtk_vlan_t sv
* RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter.
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
* The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
* The API can delete IP multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk)
{
@ -1714,7 +1714,7 @@ rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk)
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
* The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
* The API can get IP multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid)
{
@ -1771,7 +1771,7 @@ rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *
* RT_ERR_OUT_OF_RANGE - input out of range.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast
* The API can set L2 Multicast to SVID configuration. If upstream packet is L2 multicast
* packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32
* SVLAN multicast configurations for IP and L2 multicast.
*/
@ -1868,7 +1868,7 @@ rtk_api_ret_t rtk_svlan_l2mc2s_add(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t s
* RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter.
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
* The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
* The API can delete Multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk)
{
@ -1924,7 +1924,7 @@ rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk)
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
* The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
* The API can get L2 multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
rtk_api_ret_t rtk_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid)
{

12
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c
View File

@ -106,7 +106,7 @@ rtk_api_ret_t rtk_vlan_init(void)
return retVal;
}
/* Updata Databse */
/* Update Database */
vlan_mbrCfgUsage[0] = MBRCFG_USED_BY_VLAN;
vlan_mbrCfgVid[0] = 1;
@ -950,7 +950,7 @@ rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_proto
{
if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK)
return retVal;
tmp = pInfo->frame_type;
tmp = (rtl8367c_provlan_frametype)pInfo->frame_type;
if (ppb_data_cfg.etherType == pInfo->proto_type && ppb_data_cfg.frameType == tmp)
{
/*Already exist*/
@ -976,7 +976,7 @@ rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_proto
else if (empty<RTL8367C_PROTOVLAN_GROUPNO)
{
/*No exist index, but have empty index*/
ppb_data_cfg.frameType = pInfo->frame_type;
ppb_data_cfg.frameType = (rtl8367c_provlan_frametype)pInfo->frame_type;
ppb_data_cfg.etherType = pInfo->proto_type;
if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(empty, &ppb_data_cfg)) != RT_ERR_OK)
return retVal;
@ -1267,7 +1267,7 @@ rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode)
if (tag_mode >= VLAN_TAG_MODE_END)
return RT_ERR_PORT_ID;
if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), tag_mode)) != RT_ERR_OK)
if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), (rtl8367c_egtagmode)tag_mode)) != RT_ERR_OK)
return retVal;
return RT_ERR_OK;
@ -1576,7 +1576,7 @@ rtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg)
* Set port-based filtering database
* Input:
* port - Port id.
* enable - ebable port-based FID
* enable - enable port-based FID
* fid - Specified filtering database.
* Output:
* None
@ -1624,7 +1624,7 @@ rtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid
* Input:
* port - Port id.
* Output:
* pEnable - ebable port-based FID
* pEnable - enable port-based FID
* pFid - Specified filtering database.
* Return:
* RT_ERR_OK - OK

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c
View File

@ -211,7 +211,7 @@ void init_gsw(void)
set_rtl8367s_rgmii();
}
// bleow are platform driver
// below are platform driver
static const struct of_device_id rtk_gsw_match[] = {
{ .compatible = "mediatek,rtk-gsw" },
{},
@ -258,7 +258,7 @@ static int rtk_gsw_probe(struct platform_device *pdev)
init_gsw();
//init default vlan or init swocnfig
//init default vlan or init swconfig
if(!of_property_read_string(pdev->dev.of_node,
"mediatek,port_map", &pm)) {

12
target/linux/mediatek/filogic/config-6.1
View File

@ -82,7 +82,7 @@ CONFIG_CONTEXT_TRACKING_IDLE=y
# CONFIG_CPUFREQ_DT is not set
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
@ -189,6 +189,8 @@ CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_GRO_CELLS=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
@ -212,6 +214,7 @@ CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_JUMP_LABEL=y
CONFIG_LEDS_SMARTRG_LED=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
@ -230,6 +233,7 @@ CONFIG_MEMFD_CREATE=y
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
@ -263,6 +267,9 @@ CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
# CONFIG_MTK_SVS is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_SOC_THERMAL=y
CONFIG_MTK_LVTS_THERMAL=y
CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y
CONFIG_MTK_TIMER=y
# CONFIG_MTK_UART_APDMA is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
@ -276,7 +283,6 @@ CONFIG_NET_DSA_MT7530_MMIO=y
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_USXGMII=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
@ -323,6 +329,7 @@ CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PCS_MTK_USXGMII=y
CONFIG_PERF_EVENTS=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
@ -333,6 +340,7 @@ CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
CONFIG_PHY_MTK_XFI_TPHY=y
CONFIG_PHY_MTK_XSPHY=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_MT2712 is not set

2
target/linux/mediatek/filogic/target.mk
View File

@ -2,7 +2,7 @@ ARCH:=aarch64
SUBTARGET:=filogic
BOARDNAME:=Filogic 8x0 (MT798x)
CPU_TYPE:=cortex-a53
DEFAULT_PACKAGES += kmod-crypto-hw-safexcel kmod-mt7915e wpad-openssl uboot-envtools
DEFAULT_PACKAGES += fitblk kmod-crypto-hw-safexcel kmod-mt7915e wpad-openssl uboot-envtools
KERNELNAME:=Image dtbs
define Target/Description

8
target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch
View File

@ -52,8 +52,8 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
@ -140,8 +140,8 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+

6
target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch
View File

@ -103,8 +103,8 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
@ -405,7 +405,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+};
+
+&mdio {
+ switch: switch@31 {
+ switch: switch@1f {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ interrupt-controller;

0
target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch → target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch
View File

0
target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch → target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch
View File

0
target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch → target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch
View File

2
target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch
View File

@ -19,7 +19,7 @@ Subject: [PATCH] kernel: add block fit partition parser
--- a/block/blk.h
+++ b/block/blk.h
@@ -415,6 +415,8 @@ void blk_free_ext_minor(unsigned int min
@@ -414,6 +414,8 @@ void blk_free_ext_minor(unsigned int min
#define ADDPART_FLAG_NONE 0
#define ADDPART_FLAG_RAID 1
#define ADDPART_FLAG_WHOLEDISK 2

2
target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -575,6 +575,7 @@
@@ -578,6 +578,7 @@
compatible = "mediatek,mt7622-nor",
"mediatek,mt8173-nor";
reg = <0 0x11014000 0 0xe0>;

26
target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch Normal file
View File

@ -0,0 +1,26 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -109,10 +109,6 @@
status = "disabled";
};
-&btif {
- status = "okay";
-};
-
&cir {
pinctrl-names = "default";
pinctrl-0 = <&irrx_pins>;
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -90,10 +90,6 @@
status = "disabled";
};
-&btif {
- status = "okay";
-};
-
&cir {
pinctrl-names = "default";
pinctrl-0 = <&irrx_pins>;

2
target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch
View File

@ -8,7 +8,7 @@
};
chosen {
@@ -165,22 +166,22 @@
@@ -161,22 +162,22 @@
port@1 {
reg = <1>;

8
target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -21,6 +21,10 @@
@@ -21,6 +21,12 @@
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
@ -8,10 +8,12 @@
+ led-failsafe = &led_system_blue;
+ led-running = &led_system_green;
+ led-upgrade = &led_system_blue;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
};
chosen {
@@ -44,8 +48,8 @@
@@ -44,8 +50,8 @@
compatible = "gpio-keys";
factory-key {
@ -22,7 +24,7 @@
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
@@ -59,17 +63,17 @@
@@ -59,17 +65,17 @@
leds {
compatible = "gpio-leds";

2
target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -559,12 +559,16 @@
@@ -557,12 +557,16 @@
status = "okay";
};

50
target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch
View File

@ -1,50 +0,0 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -256,14 +256,42 @@
status = "disabled";
};
-&nor_flash {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_nor_pins>;
- status = "disabled";
+&bch {
+ status = "okay";
+};
+&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial_nand_pins>;
+ status = "okay";
flash@0 {
- compatible = "jedec,spi-nor";
+ compatible = "spi-nand";
reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ nand-ecc-engine = <&snfi>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "fip";
+ reg = <0x80000 0x200000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "ubi";
+ reg = <0x280000 0x7d80000>;
+ };
+ };
};
};

70
target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch Normal file
View File

@ -0,0 +1,70 @@
From d278f43f25beedfd0cb784d1dd0a9e7e8c8f123f Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 19 Apr 2023 20:15:53 +0100
Subject: [PATCH] arm64: dts: mt7622: declare SPI-NAND present on BPI-R64
The SPI-NOR node in the device tree of the BananaPi R64 has most likely
been copied from the reference board's device tree even though the R64
comes with an SPI-NAND chip rather than SPI-NOR.
Setup the Serial NAND Flash Interface (SNFI) controller, enable
hardware BCH error detection and correction engine and add the SPI-NAND
chip including basic partitions,
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/ZEA96dmaXqTpk8u8@makrotopia.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
.../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 38 ++++++++++++++++---
1 file changed, 33 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -254,14 +254,42 @@
status = "disabled";
};
-&nor_flash {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_nor_pins>;
- status = "disabled";
+&bch {
+ status = "okay";
+};
+&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial_nand_pins>;
+ status = "okay";
flash@0 {
- compatible = "jedec,spi-nor";
+ compatible = "spi-nand";
reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ nand-ecc-engine = <&snfi>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "fip";
+ reg = <0x80000 0x200000>;
+ read-only;
+ };
+
+ ubi: partition@280000 {
+ label = "ubi";
+ reg = <0x280000 0x7d80000>;
+ };
+ };
};
};

2
target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -539,6 +539,65 @@
@@ -535,6 +535,65 @@
status = "disabled";
};

4
target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -580,7 +580,7 @@
@@ -576,7 +576,7 @@
reg = <0x140000 0x0080000>;
};
@ -9,7 +9,7 @@
label = "Factory";
reg = <0x1c0000 0x0100000>;
};
@@ -641,5 +641,6 @@
@@ -637,5 +637,6 @@
&wmac {
pinctrl-names = "default";
pinctrl-0 = <&wmac_pins>;

55
target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch Normal file
View File

@ -0,0 +1,55 @@
--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -26,7 +26,9 @@
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
+ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
+ rootdisk-emmc = <&emmc_rootdisk>;
+ rootdisk-sd = <&sd_rootdisk>;
};
connector {
@@ -315,6 +317,20 @@
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
+
+ card@0 {
+ compatible = "mmc-card";
+ reg = <0>;
+
+ block {
+ compatible = "block-device";
+ partitions {
+ emmc_rootdisk: block-partition-fit {
+ partno = <3>;
+ };
+ };
+ };
+ };
};
&mmc1 {
@@ -328,6 +344,20 @@
cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
+
+ card@0 {
+ compatible = "mmc-card";
+ reg = <0>;
+
+ block {
+ compatible = "block-device";
+ partitions {
+ sd_rootdisk: block-partition-fit {
+ partno = <3>;
+ };
+ };
+ };
+ };
};
&mt6323_leds {

13
target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
View File

@ -1,13 +0,0 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -157,6 +157,10 @@
switch@0 {
compatible = "mediatek,mt7531";
reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 54 0>;
ports {

32
target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch Normal file
View File

@ -0,0 +1,32 @@
From 983f37ee08acb60435744f1b1e2afea2d2a09c48 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 19 Apr 2023 20:16:29 +0100
Subject: [PATCH] arm64: dts: mt7622: handle interrupts from MT7531 switch on
BPI-R64
Since commit ba751e28d442 ("net: dsa: mt7530: add interrupt support")
the mt7530 driver can act as an interrupt controller. Wire up irq line
of the MT7531 switch on the BananaPi BPi-R64 board, so the status of
the PHYs of the five 1000Base-T ports doesn't need to be polled any
more.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/ZEA-DV_OsmFg5egL@makrotopia.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -155,6 +155,10 @@
switch@0 {
compatible = "mediatek,mt7531";
reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 54 0>;
ports {

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