From c06859e50faa585b4de79150a9d23f2ccf0c1c82 Mon Sep 17 00:00:00 2001 From: lean Date: Fri, 2 Sep 2022 02:40:00 +0800 Subject: [PATCH] rockchip: enable hwrng for R66S/R68S --- target/linux/rockchip/armv8/config-5.15 | 2 ++ .../boot/dts/rockchip/rk3568-fastrhino.dtsi | 4 ++++ ...ip-add-hardware-random-number-genera.patch | 19 +++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/target/linux/rockchip/armv8/config-5.15 b/target/linux/rockchip/armv8/config-5.15 index 88dab52a2..ad084b492 100644 --- a/target/linux/rockchip/armv8/config-5.15 +++ b/target/linux/rockchip/armv8/config-5.15 @@ -289,6 +289,8 @@ CONFIG_HUGETLB_PAGE=y CONFIG_HWMON=y CONFIG_HWSPINLOCK=y CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ROCKCHIP=y CONFIG_HZ=250 # CONFIG_HZ_100 is not set CONFIG_HZ_250=y diff --git a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-fastrhino.dtsi b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-fastrhino.dtsi index 6abaabf3f..3aae462da 100644 --- a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-fastrhino.dtsi +++ b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-fastrhino.dtsi @@ -463,6 +463,10 @@ status = "okay"; }; +&rng { + status = "okay"; +}; + &saradc { vref-supply = <&vcca_1v8>; status = "okay"; diff --git a/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch index 8eea25381..7157acd2a 100644 --- a/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch +++ b/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -48,3 +48,22 @@ Signed-off-by: wevsty gpu: gpu@ff9a0000 { compatible = "rockchip,rk3399-mali", "arm,mali-t860"; reg = <0x0 0xff9a0000 0x0 0x10000>; +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -211,6 +211,16 @@ + }; + }; + ++ rng: rng@fe388000 { ++ compatible = "rockchip,cryptov2-rng"; ++ reg = <0x0 0xfe388000 0x0 0x2000>; ++ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; ++ clock-names = "clk_trng", "hclk_trng"; ++ resets = <&cru SRST_TRNG_NS>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>;