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update kernel to 4.9.57

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coolsnowwolf 2017-10-19 22:23:41 +08:00
parent 198c8edd4a
commit bfacc172f0
394 changed files with 157726 additions and 124645 deletions
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4
include/kernel-version.mk
View File

@ -4,11 +4,11 @@ LINUX_RELEASE?=1
LINUX_VERSION-3.18 = .71 LINUX_VERSION-3.18 = .71
LINUX_VERSION-4.4 = .92 LINUX_VERSION-4.4 = .92
LINUX_VERSION-4.9 = .54 LINUX_VERSION-4.9 = .57
LINUX_KERNEL_HASH-3.18.71 = 5abc9778ad44ce02ed6c8ab52ece8a21c6d20d21f6ed8a19287b4a38a50c1240 LINUX_KERNEL_HASH-3.18.71 = 5abc9778ad44ce02ed6c8ab52ece8a21c6d20d21f6ed8a19287b4a38a50c1240
LINUX_KERNEL_HASH-4.4.92 = 53f8cd8b024444df0f242f8e6ab5147b0b009d7a30e8b2ed3854e8d17937460d LINUX_KERNEL_HASH-4.4.92 = 53f8cd8b024444df0f242f8e6ab5147b0b009d7a30e8b2ed3854e8d17937460d
LINUX_KERNEL_HASH-4.9.54 = 651005db6efbce4fcd607415ebd697dd8d2f5a2abc2c632b11ece03a1a210fc5 LINUX_KERNEL_HASH-4.9.57 = 09230554ec6a34a12e2d2a6b32733aed3c9bc90b1662cc1b06dd67bf726c96a6
ifdef KERNEL_PATCHVER ifdef KERNEL_PATCHVER
LINUX_VERSION:=$(KERNEL_PATCHVER)$(strip $(LINUX_VERSION-$(KERNEL_PATCHVER))) LINUX_VERSION:=$(KERNEL_PATCHVER)$(strip $(LINUX_VERSION-$(KERNEL_PATCHVER)))

2
package/network/services/hostapd/Makefile
View File

@ -7,7 +7,7 @@
include $(TOPDIR)/rules.mk include $(TOPDIR)/rules.mk
PKG_NAME:=hostapd PKG_NAME:=hostapd
PKG_RELEASE:=1 PKG_RELEASE:=3
PKG_SOURCE_URL:=http://w1.fi/hostap.git PKG_SOURCE_URL:=http://w1.fi/hostap.git
PKG_SOURCE_PROTO:=git PKG_SOURCE_PROTO:=git

5
package/network/services/hostapd/files/hostapd.sh
View File

@ -149,6 +149,7 @@ hostapd_common_add_bss_config() {
config_add_int \ config_add_int \
wep_rekey eap_reauth_period \ wep_rekey eap_reauth_period \
wpa_group_rekey wpa_pair_rekey wpa_master_rekey wpa_group_rekey wpa_pair_rekey wpa_master_rekey
config_add_boolean wpa_disable_eapol_key_retries
config_add_boolean rsn_preauth auth_cache config_add_boolean rsn_preauth auth_cache
config_add_int ieee80211w config_add_int ieee80211w
@ -214,6 +215,7 @@ hostapd_set_bss_options() {
json_get_vars \ json_get_vars \
wep_rekey wpa_group_rekey wpa_pair_rekey wpa_master_rekey \ wep_rekey wpa_group_rekey wpa_pair_rekey wpa_master_rekey \
wpa_disable_eapol_key_retries \
maxassoc max_inactivity disassoc_low_ack isolate auth_cache \ maxassoc max_inactivity disassoc_low_ack isolate auth_cache \
wps_pushbutton wps_label ext_registrar wps_pbc_in_m1 wps_ap_setup_locked \ wps_pushbutton wps_label ext_registrar wps_pbc_in_m1 wps_ap_setup_locked \
wps_independent wps_device_type wps_device_name wps_manufacturer wps_pin \ wps_independent wps_device_type wps_device_name wps_manufacturer wps_pin \
@ -229,6 +231,7 @@ hostapd_set_bss_options() {
set_default hidden 0 set_default hidden 0
set_default wmm 1 set_default wmm 1
set_default uapsd 1 set_default uapsd 1
set_default wpa_disable_eapol_key_retries 0
set_default eapol_version 0 set_default eapol_version 0
set_default acct_port 1813 set_default acct_port 1813
@ -416,6 +419,8 @@ hostapd_set_bss_options() {
done done
fi fi
append bss_conf "wpa_disable_eapol_key_retries=$wpa_disable_eapol_key_retries" "$N"
hostapd_append_wpa_key_mgmt hostapd_append_wpa_key_mgmt
[ -n "$wpa_key_mgmt" ] && append bss_conf "wpa_key_mgmt=$wpa_key_mgmt" "$N" [ -n "$wpa_key_mgmt" ] && append bss_conf "wpa_key_mgmt=$wpa_key_mgmt" "$N"
fi fi

34
package/network/services/hostapd/patches/008-WPA-Extra-defense-against-PTK-reinstalls-in-4-way-ha.patch Normal file
View File

@ -0,0 +1,34 @@
From a00e946c1c9a1f9cc65c72900d2a444ceb1f872e Mon Sep 17 00:00:00 2001
From: Mathy Vanhoef <Mathy.Vanhoef@cs.kuleuven.be>
Date: Thu, 5 Oct 2017 23:53:01 +0200
Subject: [PATCH] WPA: Extra defense against PTK reinstalls in 4-way handshake
Currently, reinstallations of the PTK are prevented by (1) assuring the
same TPTK is only set once as the PTK, and (2) that one particular PTK
is only installed once. This patch makes it more explicit that point (1)
is required to prevent key reinstallations. At the same time, this patch
hardens wpa_supplicant such that future changes do not accidentally
break this property.
Signed-off-by: Mathy Vanhoef <Mathy.Vanhoef@cs.kuleuven.be>
---
src/rsn_supp/wpa.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/src/rsn_supp/wpa.c
+++ b/src/rsn_supp/wpa.c
@@ -1728,6 +1728,14 @@ static int wpa_supplicant_verify_eapol_k
sm->ptk_set = 1;
os_memcpy(&sm->ptk, &sm->tptk, sizeof(sm->ptk));
os_memset(&sm->tptk, 0, sizeof(sm->tptk));
+ /*
+ * This assures the same TPTK in sm->tptk can never be
+ * copied twice to sm->pkt as the new PTK. In
+ * combination with the installed flag in the wpa_ptk
+ * struct, this assures the same PTK is only installed
+ * once.
+ */
+ sm->renew_snonce = 1;
}
}

53
package/network/services/hostapd/patches/009-Clear-PMK-length-and-check-for-this-when-deriving-PT.patch Normal file
View File

@ -0,0 +1,53 @@
From b488a12948751f57871f09baa345e59b23959a41 Mon Sep 17 00:00:00 2001
From: Jouni Malinen <j@w1.fi>
Date: Sun, 8 Oct 2017 13:18:02 +0300
Subject: [PATCH] Clear PMK length and check for this when deriving PTK
Instead of setting the default PMK length for the cleared PMK, set the
length to 0 and explicitly check for this when deriving PTK to avoid
unexpected key derivation with an all-zeroes key should it be possible
to somehow trigger PTK derivation to happen before PMK derivation.
Signed-off-by: Jouni Malinen <j@w1.fi>
---
src/common/wpa_common.c | 5 +++++
src/rsn_supp/wpa.c | 7 ++++---
2 files changed, 9 insertions(+), 3 deletions(-)
--- a/src/common/wpa_common.c
+++ b/src/common/wpa_common.c
@@ -225,6 +225,11 @@ int wpa_pmk_to_ptk(const u8 *pmk, size_t
u8 tmp[WPA_KCK_MAX_LEN + WPA_KEK_MAX_LEN + WPA_TK_MAX_LEN];
size_t ptk_len;
+ if (pmk_len == 0) {
+ wpa_printf(MSG_ERROR, "WPA: No PMK set for PT derivation");
+ return -1;
+ }
+
if (os_memcmp(addr1, addr2, ETH_ALEN) < 0) {
os_memcpy(data, addr1, ETH_ALEN);
os_memcpy(data + ETH_ALEN, addr2, ETH_ALEN);
--- a/src/rsn_supp/wpa.c
+++ b/src/rsn_supp/wpa.c
@@ -584,7 +584,8 @@ static void wpa_supplicant_process_1_of_
/* Calculate PTK which will be stored as a temporary PTK until it has
* been verified when processing message 3/4. */
ptk = &sm->tptk;
- wpa_derive_ptk(sm, src_addr, key, ptk);
+ if (wpa_derive_ptk(sm, src_addr, key, ptk) < 0)
+ goto failed;
if (sm->pairwise_cipher == WPA_CIPHER_TKIP) {
u8 buf[8];
/* Supplicant: swap tx/rx Mic keys */
@@ -2705,8 +2706,8 @@ void wpa_sm_set_pmk_from_pmksa(struct wp
sm->pmk_len = sm->cur_pmksa->pmk_len;
os_memcpy(sm->pmk, sm->cur_pmksa->pmk, sm->pmk_len);
} else {
- sm->pmk_len = PMK_LEN;
- os_memset(sm->pmk, 0, PMK_LEN);
+ sm->pmk_len = 0;
+ os_memset(sm->pmk, 0, PMK_LEN_MAX);
}
}

221
package/network/services/hostapd/patches/010-Optional-AP-side-workaround-for-key-reinstallation-a.patch Normal file
View File

@ -0,0 +1,221 @@
From 6f234c1e2ee1ede29f2412b7012b3345ed8e52d3 Mon Sep 17 00:00:00 2001
From: Jouni Malinen <j@w1.fi>
Date: Mon, 16 Oct 2017 18:37:43 +0300
Subject: [PATCH] Optional AP side workaround for key reinstallation attacks
This adds a new hostapd configuration parameter
wpa_disable_eapol_key_retries=1 that can be used to disable
retransmission of EAPOL-Key frames that are used to install
keys (EAPOL-Key message 3/4 and group message 1/2). This is
similar to setting wpa_group_update_count=1 and
wpa_pairwise_update_count=1, but with no impact to message 1/4
retries and with extended timeout for messages 4/4 and group
message 2/2 to avoid causing issues with stations that may use
aggressive power saving have very long time in replying to the
EAPOL-Key messages.
This option can be used to work around key reinstallation attacks
on the station (supplicant) side in cases those station devices
cannot be updated for some reason. By removing the
retransmissions the attacker cannot cause key reinstallation with
a delayed frame transmission. This is related to the station side
vulnerabilities CVE-2017-13077, CVE-2017-13078, CVE-2017-13079,
CVE-2017-13080, and CVE-2017-13081.
This workaround might cause interoperability issues and reduced
robustness of key negotiation especially in environments with
heavy traffic load due to the number of attempts to perform the
key exchange is reduced significantly. As such, this workaround
is disabled by default (unless overridden in build
configuration). To enable this, set the parameter to 1.
It is also possible to enable this in the build by default by
adding the following to the build configuration:
CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1
Signed-off-by: Jouni Malinen <j@w1.fi>
---
hostapd/config_file.c | 2 ++
hostapd/defconfig | 4 ++++
hostapd/hostapd.conf | 24 ++++++++++++++++++++++++
src/ap/ap_config.c | 6 ++++++
src/ap/ap_config.h | 1 +
src/ap/wpa_auth.c | 22 ++++++++++++++++++++--
src/ap/wpa_auth.h | 1 +
src/ap/wpa_auth_glue.c | 2 ++
8 files changed, 60 insertions(+), 2 deletions(-)
--- a/hostapd/config_file.c
+++ b/hostapd/config_file.c
@@ -2542,6 +2542,8 @@ static int hostapd_config_fill(struct ho
return 1;
}
bss->wpa_pairwise_update_count = (u32) val;
+ } else if (os_strcmp(buf, "wpa_disable_eapol_key_retries") == 0) {
+ bss->wpa_disable_eapol_key_retries = atoi(pos);
} else if (os_strcmp(buf, "wpa_passphrase") == 0) {
int len = os_strlen(pos);
if (len < 8 || len > 63) {
--- a/hostapd/defconfig
+++ b/hostapd/defconfig
@@ -372,3 +372,7 @@ CONFIG_IPV6=y
# Opportunistic Wireless Encryption (OWE)
# Experimental implementation of draft-harkins-owe-07.txt
#CONFIG_OWE=y
+
+# Override default value for the wpa_disable_eapol_key_retries configuration
+# parameter. See that parameter in hostapd.conf for more details.
+#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1
--- a/hostapd/hostapd.conf
+++ b/hostapd/hostapd.conf
@@ -1315,6 +1315,30 @@ own_ip_addr=127.0.0.1
# Range 1..4294967295; default: 4
#wpa_pairwise_update_count=4
+# Workaround for key reinstallation attacks
+#
+# This parameter can be used to disable retransmission of EAPOL-Key frames that
+# are used to install keys (EAPOL-Key message 3/4 and group message 1/2). This
+# is similar to setting wpa_group_update_count=1 and
+# wpa_pairwise_update_count=1, but with no impact to message 1/4 and with
+# extended timeout on the response to avoid causing issues with stations that
+# may use aggressive power saving have very long time in replying to the
+# EAPOL-Key messages.
+#
+# This option can be used to work around key reinstallation attacks on the
+# station (supplicant) side in cases those station devices cannot be updated
+# for some reason. By removing the retransmissions the attacker cannot cause
+# key reinstallation with a delayed frame transmission. This is related to the
+# station side vulnerabilities CVE-2017-13077, CVE-2017-13078, CVE-2017-13079,
+# CVE-2017-13080, and CVE-2017-13081.
+#
+# This workaround might cause interoperability issues and reduced robustness of
+# key negotiation especially in environments with heavy traffic load due to the
+# number of attempts to perform the key exchange is reduced significantly. As
+# such, this workaround is disabled by default (unless overridden in build
+# configuration). To enable this, set the parameter to 1.
+#wpa_disable_eapol_key_retries=1
+
# Enable IEEE 802.11i/RSN/WPA2 pre-authentication. This is used to speed up
# roaming be pre-authenticating IEEE 802.1X/EAP part of the full RSN
# authentication and key handshake before actually associating with a new AP.
--- a/src/ap/ap_config.c
+++ b/src/ap/ap_config.c
@@ -37,6 +37,10 @@ static void hostapd_config_free_vlan(str
}
+#ifndef DEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES
+#define DEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES 0
+#endif /* DEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES */
+
void hostapd_config_defaults_bss(struct hostapd_bss_config *bss)
{
dl_list_init(&bss->anqp_elem);
@@ -58,6 +62,8 @@ void hostapd_config_defaults_bss(struct
bss->wpa_gmk_rekey = 86400;
bss->wpa_group_update_count = 4;
bss->wpa_pairwise_update_count = 4;
+ bss->wpa_disable_eapol_key_retries =
+ DEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES;
bss->wpa_key_mgmt = WPA_KEY_MGMT_PSK;
bss->wpa_pairwise = WPA_CIPHER_TKIP;
bss->wpa_group = WPA_CIPHER_TKIP;
--- a/src/ap/ap_config.h
+++ b/src/ap/ap_config.h
@@ -333,6 +333,7 @@ struct hostapd_bss_config {
int wpa_ptk_rekey;
u32 wpa_group_update_count;
u32 wpa_pairwise_update_count;
+ int wpa_disable_eapol_key_retries;
int rsn_pairwise;
int rsn_preauth;
char *rsn_preauth_interfaces;
--- a/src/ap/wpa_auth.c
+++ b/src/ap/wpa_auth.c
@@ -65,6 +65,7 @@ static u8 * ieee80211w_kde_add(struct wp
static const u32 eapol_key_timeout_first = 100; /* ms */
static const u32 eapol_key_timeout_subseq = 1000; /* ms */
static const u32 eapol_key_timeout_first_group = 500; /* ms */
+static const u32 eapol_key_timeout_no_retrans = 4000; /* ms */
/* TODO: make these configurable */
static const int dot11RSNAConfigPMKLifetime = 43200;
@@ -1653,6 +1654,9 @@ static void wpa_send_eapol(struct wpa_au
eapol_key_timeout_first_group;
else
timeout_ms = eapol_key_timeout_subseq;
+ if (wpa_auth->conf.wpa_disable_eapol_key_retries &&
+ (!pairwise || (key_info & WPA_KEY_INFO_MIC)))
+ timeout_ms = eapol_key_timeout_no_retrans;
if (pairwise && ctr == 1 && !(key_info & WPA_KEY_INFO_MIC))
sm->pending_1_of_4_timeout = 1;
wpa_printf(MSG_DEBUG, "WPA: Use EAPOL-Key timeout of %u ms (retry "
@@ -2882,6 +2886,11 @@ SM_STATE(WPA_PTK, PTKINITNEGOTIATING)
sm->TimeoutEvt = FALSE;
sm->TimeoutCtr++;
+ if (sm->wpa_auth->conf.wpa_disable_eapol_key_retries &&
+ sm->TimeoutCtr > 1) {
+ /* Do not allow retransmission of EAPOL-Key msg 3/4 */
+ return;
+ }
if (sm->TimeoutCtr > sm->wpa_auth->conf.wpa_pairwise_update_count) {
/* No point in sending the EAPOL-Key - we will disconnect
* immediately following this. */
@@ -3220,7 +3229,9 @@ SM_STEP(WPA_PTK)
sm->EAPOLKeyPairwise && sm->MICVerified)
SM_ENTER(WPA_PTK, PTKINITDONE);
else if (sm->TimeoutCtr >
- sm->wpa_auth->conf.wpa_pairwise_update_count) {
+ sm->wpa_auth->conf.wpa_pairwise_update_count ||
+ (sm->wpa_auth->conf.wpa_disable_eapol_key_retries &&
+ sm->TimeoutCtr > 1)) {
wpa_auth->dot11RSNA4WayHandshakeFailures++;
wpa_auth_vlogger(
sm->wpa_auth, sm->addr, LOGGER_DEBUG,
@@ -3260,6 +3271,11 @@ SM_STATE(WPA_PTK_GROUP, REKEYNEGOTIATING
SM_ENTRY_MA(WPA_PTK_GROUP, REKEYNEGOTIATING, wpa_ptk_group);
sm->GTimeoutCtr++;
+ if (sm->wpa_auth->conf.wpa_disable_eapol_key_retries &&
+ sm->GTimeoutCtr > 1) {
+ /* Do not allow retransmission of EAPOL-Key group msg 1/2 */
+ return;
+ }
if (sm->GTimeoutCtr > sm->wpa_auth->conf.wpa_group_update_count) {
/* No point in sending the EAPOL-Key - we will disconnect
* immediately following this. */
@@ -3363,7 +3379,9 @@ SM_STEP(WPA_PTK_GROUP)
!sm->EAPOLKeyPairwise && sm->MICVerified)
SM_ENTER(WPA_PTK_GROUP, REKEYESTABLISHED);
else if (sm->GTimeoutCtr >
- sm->wpa_auth->conf.wpa_group_update_count)
+ sm->wpa_auth->conf.wpa_group_update_count ||
+ (sm->wpa_auth->conf.wpa_disable_eapol_key_retries &&
+ sm->GTimeoutCtr > 1))
SM_ENTER(WPA_PTK_GROUP, KEYERROR);
else if (sm->TimeoutEvt)
SM_ENTER(WPA_PTK_GROUP, REKEYNEGOTIATING);
--- a/src/ap/wpa_auth.h
+++ b/src/ap/wpa_auth.h
@@ -165,6 +165,7 @@ struct wpa_auth_config {
int wpa_ptk_rekey;
u32 wpa_group_update_count;
u32 wpa_pairwise_update_count;
+ int wpa_disable_eapol_key_retries;
int rsn_pairwise;
int rsn_preauth;
int eapol_version;
--- a/src/ap/wpa_auth_glue.c
+++ b/src/ap/wpa_auth_glue.c
@@ -45,6 +45,8 @@ static void hostapd_wpa_auth_conf(struct
wconf->wpa_gmk_rekey = conf->wpa_gmk_rekey;
wconf->wpa_ptk_rekey = conf->wpa_ptk_rekey;
wconf->wpa_group_update_count = conf->wpa_group_update_count;
+ wconf->wpa_disable_eapol_key_retries =
+ conf->wpa_disable_eapol_key_retries;
wconf->wpa_pairwise_update_count = conf->wpa_pairwise_update_count;
wconf->rsn_pairwise = conf->rsn_pairwise;
wconf->rsn_preauth = conf->rsn_preauth;

100
package/network/services/hostapd/patches/011-Additional-consistentcy-checks-for-PTK-component-len.patch Normal file
View File

@ -0,0 +1,100 @@
From a6ea665300919d6a3af22b1f4237203647fda93a Mon Sep 17 00:00:00 2001
From: Jouni Malinen <j@w1.fi>
Date: Tue, 17 Oct 2017 00:01:11 +0300
Subject: [PATCH] Additional consistentcy checks for PTK component lengths
Verify that TK, KCK, and KEK lengths are set to consistent values within
struct wpa_ptk before using them in supplicant. This is an additional
layer of protection against unexpected states.
Signed-off-by: Jouni Malinen <j@w1.fi>
---
src/common/wpa_common.c | 6 ++++++
src/rsn_supp/wpa.c | 26 ++++++++++++++++++++------
2 files changed, 26 insertions(+), 6 deletions(-)
--- a/src/common/wpa_common.c
+++ b/src/common/wpa_common.c
@@ -100,6 +100,12 @@ int wpa_eapol_key_mic(const u8 *key, siz
{
u8 hash[SHA512_MAC_LEN];
+ if (key_len == 0) {
+ wpa_printf(MSG_DEBUG,
+ "WPA: KCK not set - cannot calculate MIC");
+ return -1;
+ }
+
switch (ver) {
#ifndef CONFIG_FIPS
case WPA_KEY_INFO_TYPE_HMAC_MD5_RC4:
--- a/src/rsn_supp/wpa.c
+++ b/src/rsn_supp/wpa.c
@@ -725,6 +725,11 @@ static int wpa_supplicant_install_ptk(st
alg = wpa_cipher_to_alg(sm->pairwise_cipher);
keylen = wpa_cipher_key_len(sm->pairwise_cipher);
+ if (keylen <= 0 || (unsigned int) keylen != sm->ptk.tk_len) {
+ wpa_printf(MSG_DEBUG, "WPA: TK length mismatch: %d != %lu",
+ keylen, (long unsigned int) sm->ptk.tk_len);
+ return -1;
+ }
rsclen = wpa_cipher_rsc_len(sm->pairwise_cipher);
if (sm->proto == WPA_PROTO_RSN || sm->proto == WPA_PROTO_OSEN) {
@@ -745,6 +750,7 @@ static int wpa_supplicant_install_ptk(st
/* TK is not needed anymore in supplicant */
os_memset(sm->ptk.tk, 0, WPA_TK_MAX_LEN);
+ sm->ptk.tk_len = 0;
sm->ptk.installed = 1;
if (sm->wpa_ptk_rekey) {
@@ -1717,9 +1723,10 @@ static int wpa_supplicant_verify_eapol_k
os_memcpy(mic, key + 1, mic_len);
if (sm->tptk_set) {
os_memset(key + 1, 0, mic_len);
- wpa_eapol_key_mic(sm->tptk.kck, sm->tptk.kck_len, sm->key_mgmt,
- ver, buf, len, (u8 *) (key + 1));
- if (os_memcmp_const(mic, key + 1, mic_len) != 0) {
+ if (wpa_eapol_key_mic(sm->tptk.kck, sm->tptk.kck_len,
+ sm->key_mgmt,
+ ver, buf, len, (u8 *) (key + 1)) < 0 ||
+ os_memcmp_const(mic, key + 1, mic_len) != 0) {
wpa_msg(sm->ctx->msg_ctx, MSG_WARNING,
"WPA: Invalid EAPOL-Key MIC "
"when using TPTK - ignoring TPTK");
@@ -1742,9 +1749,10 @@ static int wpa_supplicant_verify_eapol_k
if (!ok && sm->ptk_set) {
os_memset(key + 1, 0, mic_len);
- wpa_eapol_key_mic(sm->ptk.kck, sm->ptk.kck_len, sm->key_mgmt,
- ver, buf, len, (u8 *) (key + 1));
- if (os_memcmp_const(mic, key + 1, mic_len) != 0) {
+ if (wpa_eapol_key_mic(sm->ptk.kck, sm->ptk.kck_len,
+ sm->key_mgmt,
+ ver, buf, len, (u8 *) (key + 1)) < 0 ||
+ os_memcmp_const(mic, key + 1, mic_len) != 0) {
wpa_msg(sm->ctx->msg_ctx, MSG_WARNING,
"WPA: Invalid EAPOL-Key MIC - "
"dropping packet");
@@ -4167,6 +4175,11 @@ int fils_process_assoc_resp(struct wpa_s
alg = wpa_cipher_to_alg(sm->pairwise_cipher);
keylen = wpa_cipher_key_len(sm->pairwise_cipher);
+ if (keylen <= 0 || (unsigned int) keylen != sm->ptk.tk_len) {
+ wpa_printf(MSG_DEBUG, "FILS: TK length mismatch: %u != %lu",
+ keylen, (long unsigned int) sm->ptk.tk_len);
+ goto fail;
+ }
rsclen = wpa_cipher_rsc_len(sm->pairwise_cipher);
wpa_hexdump_key(MSG_DEBUG, "FILS: Set TK to driver",
sm->ptk.tk, keylen);
@@ -4183,6 +4196,7 @@ int fils_process_assoc_resp(struct wpa_s
* takes care of association frame encryption/decryption. */
/* TK is not needed anymore in supplicant */
os_memset(sm->ptk.tk, 0, WPA_TK_MAX_LEN);
+ sm->ptk.tk_len = 0;
sm->ptk.installed = 1;
/* FILS HLP Container */

25
package/network/services/hostapd/patches/012-Clear-BSSID-information-in-supplicant-state-machine-.patch Normal file
View File

@ -0,0 +1,25 @@
From c0fe5f125a9d4a6564e1f4956ccc3809bf2fd69d Mon Sep 17 00:00:00 2001
From: Jouni Malinen <j@w1.fi>
Date: Tue, 17 Oct 2017 01:15:24 +0300
Subject: [PATCH] Clear BSSID information in supplicant state machine on
disconnection
This fixes a corner case where RSN pre-authentication candidate from
scan results was ignored if the station was associated with that BSS
just before running the new scan for the connection.
Signed-off-by: Jouni Malinen <j@w1.fi>
---
src/rsn_supp/wpa.c | 1 +
1 file changed, 1 insertion(+)
--- a/src/rsn_supp/wpa.c
+++ b/src/rsn_supp/wpa.c
@@ -2662,6 +2662,7 @@ void wpa_sm_notify_disassoc(struct wpa_s
wpa_sm_drop_sa(sm);
sm->msg_3_of_4_ok = 0;
+ os_memset(sm->bssid, 0, ETH_ALEN);
}

4
package/network/services/hostapd/patches/300-noscan.patch
View File

@ -1,6 +1,6 @@
--- a/hostapd/config_file.c --- a/hostapd/config_file.c
+++ b/hostapd/config_file.c +++ b/hostapd/config_file.c
@@ -3014,6 +3014,10 @@ static int hostapd_config_fill(struct ho @@ -3016,6 +3016,10 @@ static int hostapd_config_fill(struct ho
} }
#endif /* CONFIG_IEEE80211W */ #endif /* CONFIG_IEEE80211W */
#ifdef CONFIG_IEEE80211N #ifdef CONFIG_IEEE80211N
@ -13,7 +13,7 @@
} else if (os_strcmp(buf, "ht_capab") == 0) { } else if (os_strcmp(buf, "ht_capab") == 0) {
--- a/src/ap/ap_config.h --- a/src/ap/ap_config.h
+++ b/src/ap/ap_config.h +++ b/src/ap/ap_config.h
@@ -734,6 +734,8 @@ struct hostapd_config { @@ -735,6 +735,8 @@ struct hostapd_config {
int ht_op_mode_fixed; int ht_op_mode_fixed;
u16 ht_capab; u16 ht_capab;

8
package/network/services/hostapd/patches/380-disable_ctrl_iface_mib.patch
View File

@ -129,7 +129,7 @@
static void ieee802_1x_wnm_notif_send(void *eloop_ctx, void *timeout_ctx) static void ieee802_1x_wnm_notif_send(void *eloop_ctx, void *timeout_ctx)
--- a/src/ap/wpa_auth.c --- a/src/ap/wpa_auth.c
+++ b/src/ap/wpa_auth.c +++ b/src/ap/wpa_auth.c
@@ -3762,6 +3762,7 @@ static const char * wpa_bool_txt(int val @@ -3780,6 +3780,7 @@ static const char * wpa_bool_txt(int val
return val ? "TRUE" : "FALSE"; return val ? "TRUE" : "FALSE";
} }
@ -137,7 +137,7 @@
#define RSN_SUITE "%02x-%02x-%02x-%d" #define RSN_SUITE "%02x-%02x-%02x-%d"
#define RSN_SUITE_ARG(s) \ #define RSN_SUITE_ARG(s) \
@@ -3906,7 +3907,7 @@ int wpa_get_mib_sta(struct wpa_state_mac @@ -3924,7 +3925,7 @@ int wpa_get_mib_sta(struct wpa_state_mac
return len; return len;
} }
@ -148,7 +148,7 @@
{ {
--- a/src/rsn_supp/wpa.c --- a/src/rsn_supp/wpa.c
+++ b/src/rsn_supp/wpa.c +++ b/src/rsn_supp/wpa.c
@@ -2339,6 +2339,8 @@ static u32 wpa_key_mgmt_suite(struct wpa @@ -2356,6 +2356,8 @@ static u32 wpa_key_mgmt_suite(struct wpa
} }
@ -157,7 +157,7 @@
#define RSN_SUITE "%02x-%02x-%02x-%d" #define RSN_SUITE "%02x-%02x-%02x-%d"
#define RSN_SUITE_ARG(s) \ #define RSN_SUITE_ARG(s) \
((s) >> 24) & 0xff, ((s) >> 16) & 0xff, ((s) >> 8) & 0xff, (s) & 0xff ((s) >> 24) & 0xff, ((s) >> 16) & 0xff, ((s) >> 8) & 0xff, (s) & 0xff
@@ -2422,6 +2424,7 @@ int wpa_sm_get_mib(struct wpa_sm *sm, ch @@ -2439,6 +2441,7 @@ int wpa_sm_get_mib(struct wpa_sm *sm, ch
return (int) len; return (int) len;
} }

4
package/network/services/hostapd/patches/390-wpa_ie_cap_workaround.patch
View File

@ -1,6 +1,6 @@
--- a/src/common/wpa_common.c --- a/src/common/wpa_common.c
+++ b/src/common/wpa_common.c +++ b/src/common/wpa_common.c
@@ -1664,6 +1664,31 @@ u32 wpa_akm_to_suite(int akm) @@ -1675,6 +1675,31 @@ u32 wpa_akm_to_suite(int akm)
} }
@ -32,7 +32,7 @@
int wpa_compare_rsn_ie(int ft_initial_assoc, int wpa_compare_rsn_ie(int ft_initial_assoc,
const u8 *ie1, size_t ie1len, const u8 *ie1, size_t ie1len,
const u8 *ie2, size_t ie2len) const u8 *ie2, size_t ie2len)
@@ -1671,8 +1696,19 @@ int wpa_compare_rsn_ie(int ft_initial_as @@ -1682,8 +1707,19 @@ int wpa_compare_rsn_ie(int ft_initial_as
if (ie1 == NULL || ie2 == NULL) if (ie1 == NULL || ie2 == NULL)
return -1; return -1;

2
package/network/services/hostapd/patches/600-ubus_support.patch
View File

@ -298,7 +298,7 @@
} }
--- a/src/ap/wpa_auth_glue.c --- a/src/ap/wpa_auth_glue.c
+++ b/src/ap/wpa_auth_glue.c +++ b/src/ap/wpa_auth_glue.c
@@ -173,6 +173,7 @@ static void hostapd_wpa_auth_psk_failure @@ -175,6 +175,7 @@ static void hostapd_wpa_auth_psk_failure
struct hostapd_data *hapd = ctx; struct hostapd_data *hapd = ctx;
wpa_msg(hapd->msg_ctx, MSG_INFO, AP_STA_POSSIBLE_PSK_MISMATCH MACSTR, wpa_msg(hapd->msg_ctx, MSG_INFO, AP_STA_POSSIBLE_PSK_MISMATCH MACSTR,
MAC2STR(addr)); MAC2STR(addr));

6
target/linux/apm821xx/patches-4.9/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch
View File

@ -44,7 +44,7 @@ Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
#include "xhci.h" #include "xhci.h"
#include "xhci-trace.h" #include "xhci-trace.h"
@@ -248,6 +250,458 @@ static void xhci_pme_acpi_rtd3_enable(st @@ -236,6 +238,458 @@ static void xhci_pme_acpi_rtd3_enable(st
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
#endif /* CONFIG_ACPI */ #endif /* CONFIG_ACPI */
@ -503,7 +503,7 @@ Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
/* called during probe() after chip reset completes */ /* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd) static int xhci_pci_setup(struct usb_hcd *hcd)
{ {
@@ -287,6 +741,22 @@ static int xhci_pci_probe(struct pci_dev @@ -275,6 +729,22 @@ static int xhci_pci_probe(struct pci_dev
struct hc_driver *driver; struct hc_driver *driver;
struct usb_hcd *hcd; struct usb_hcd *hcd;
@ -526,7 +526,7 @@ Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
driver = (struct hc_driver *)id->driver_data; driver = (struct hc_driver *)id->driver_data;
/* Prevent runtime suspending between USB-2 and USB-3 initialization */ /* Prevent runtime suspending between USB-2 and USB-3 initialization */
@@ -344,6 +814,16 @@ static void xhci_pci_remove(struct pci_d @@ -332,6 +802,16 @@ static void xhci_pci_remove(struct pci_d
{ {
struct xhci_hcd *xhci; struct xhci_hcd *xhci;

2
target/linux/apm821xx/patches-4.9/802-usb-xhci-force-msi-renesas-xhci.patch
View File

@ -13,7 +13,7 @@ produce a noisy warning.
--- a/drivers/usb/host/xhci-pci.c --- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c
@@ -205,7 +205,7 @@ static void xhci_pci_quirks(struct devic @@ -193,7 +193,7 @@ static void xhci_pci_quirks(struct devic
} }
if (pdev->vendor == PCI_VENDOR_ID_RENESAS && if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
pdev->device == 0x0015) pdev->device == 0x0015)

2
target/linux/bcm53xx/patches-4.9/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
View File

@ -129,7 +129,7 @@ it on BCM4708 family.
+++ b/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h
@@ -1662,6 +1662,7 @@ struct xhci_hcd { @@ -1662,6 +1662,7 @@ struct xhci_hcd {
#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26) #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26)
#define XHCI_U2_DISABLE_WAKE (1 << 27) /* Reserved. It was XHCI_U2_DISABLE_WAKE */
#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28)
+#define XHCI_FAKE_DOORBELL (1 << 29) +#define XHCI_FAKE_DOORBELL (1 << 29)

2
target/linux/brcm2708/patches-4.9/950-0061-hid-Reduce-default-mouse-polling-interval-to-60Hz.patch
View File

@ -19,7 +19,7 @@ Reduces overhead when using X
module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644); module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644);
MODULE_PARM_DESC(mousepoll, "Polling interval of mice"); MODULE_PARM_DESC(mousepoll, "Polling interval of mice");
@@ -1083,8 +1083,12 @@ static int usbhid_start(struct hid_devic @@ -1093,8 +1093,12 @@ static int usbhid_start(struct hid_devic
} }
/* Change the polling interval of mice. */ /* Change the polling interval of mice. */

2
target/linux/brcm2708/patches-4.9/950-0101-staging-vchi-Update-for-rename-of-page_cache_release.patch
View File

@ -21,7 +21,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net>
} }
kfree(pagelist); kfree(pagelist);
if (actual_pages == 0) if (actual_pages == 0)
@@ -577,7 +577,7 @@ free_pagelist(PAGELIST_T *pagelist, int @@ -579,7 +579,7 @@ free_pagelist(PAGELIST_T *pagelist, int
offset = 0; offset = 0;
set_page_dirty(pg); set_page_dirty(pg);
} }

2
target/linux/cns3xxx/patches-4.9/200-broadcom_phy_reinit.patch
View File

@ -1,6 +1,6 @@
--- a/drivers/net/phy/broadcom.c --- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c
@@ -414,6 +414,11 @@ static int bcm5481_config_aneg(struct ph @@ -420,6 +420,11 @@ static int bcm5481_config_aneg(struct ph
/* Write bits 14:0. */ /* Write bits 14:0. */
reg |= (1 << 15); reg |= (1 << 15);
phy_write(phydev, 0x18, reg); phy_write(phydev, 0x18, reg);

90
target/linux/generic/backport-4.9/024-1-tcp-tsq-add-tsq_flags-tsq_enum.patch Normal file
View File

@ -0,0 +1,90 @@
From 40fc3423b983b864bf70b03199191260ae9b2ea6 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Sat, 3 Dec 2016 11:14:50 -0800
Subject: [PATCH 01/10] tcp: tsq: add tsq_flags / tsq_enum
This is a cleanup, to ease code review of following patches.
Old 'enum tsq_flags' is renamed, and a new enumeration is added
with the flags used in cmpxchg() operations as opposed to
single bit operations.
Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
include/linux/tcp.h | 11 ++++++++++-
net/ipv4/tcp_output.c | 16 ++++++++--------
2 files changed, 18 insertions(+), 9 deletions(-)
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -367,7 +367,7 @@ struct tcp_sock {
u32 *saved_syn;
};
-enum tsq_flags {
+enum tsq_enum {
TSQ_THROTTLED,
TSQ_QUEUED,
TCP_TSQ_DEFERRED, /* tcp_tasklet_func() found socket was owned */
@@ -378,6 +378,15 @@ enum tsq_flags {
*/
};
+enum tsq_flags {
+ TSQF_THROTTLED = (1UL << TSQ_THROTTLED),
+ TSQF_QUEUED = (1UL << TSQ_QUEUED),
+ TCPF_TSQ_DEFERRED = (1UL << TCP_TSQ_DEFERRED),
+ TCPF_WRITE_TIMER_DEFERRED = (1UL << TCP_WRITE_TIMER_DEFERRED),
+ TCPF_DELACK_TIMER_DEFERRED = (1UL << TCP_DELACK_TIMER_DEFERRED),
+ TCPF_MTU_REDUCED_DEFERRED = (1UL << TCP_MTU_REDUCED_DEFERRED),
+};
+
static inline struct tcp_sock *tcp_sk(const struct sock *sk)
{
return (struct tcp_sock *)sk;
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -784,10 +784,10 @@ static void tcp_tasklet_func(unsigned lo
}
}
-#define TCP_DEFERRED_ALL ((1UL << TCP_TSQ_DEFERRED) | \
- (1UL << TCP_WRITE_TIMER_DEFERRED) | \
- (1UL << TCP_DELACK_TIMER_DEFERRED) | \
- (1UL << TCP_MTU_REDUCED_DEFERRED))
+#define TCP_DEFERRED_ALL (TCPF_TSQ_DEFERRED | \
+ TCPF_WRITE_TIMER_DEFERRED | \
+ TCPF_DELACK_TIMER_DEFERRED | \
+ TCPF_MTU_REDUCED_DEFERRED)
/**
* tcp_release_cb - tcp release_sock() callback
* @sk: socket
@@ -808,7 +808,7 @@ void tcp_release_cb(struct sock *sk)
nflags = flags & ~TCP_DEFERRED_ALL;
} while (cmpxchg(&tp->tsq_flags, flags, nflags) != flags);
- if (flags & (1UL << TCP_TSQ_DEFERRED))
+ if (flags & TCPF_TSQ_DEFERRED)
tcp_tsq_handler(sk);
/* Here begins the tricky part :
@@ -822,15 +822,15 @@ void tcp_release_cb(struct sock *sk)
*/
sock_release_ownership(sk);
- if (flags & (1UL << TCP_WRITE_TIMER_DEFERRED)) {
+ if (flags & TCPF_WRITE_TIMER_DEFERRED) {
tcp_write_timer_handler(sk);
__sock_put(sk);
}
- if (flags & (1UL << TCP_DELACK_TIMER_DEFERRED)) {
+ if (flags & TCPF_DELACK_TIMER_DEFERRED) {
tcp_delack_timer_handler(sk);
__sock_put(sk);
}
- if (flags & (1UL << TCP_MTU_REDUCED_DEFERRED)) {
+ if (flags & TCPF_MTU_REDUCED_DEFERRED) {
inet_csk(sk)->icsk_af_ops->mtu_reduced(sk);
__sock_put(sk);
}

48
target/linux/generic/backport-4.9/024-2-tcp-tsq-remove-one-locked-operation-in-tcp_wfree.patch Normal file
View File

@ -0,0 +1,48 @@
From 408f0a6c21e124cc4f6c7aa370b38aa47e55428d Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Sat, 3 Dec 2016 11:14:51 -0800
Subject: [PATCH 02/10] tcp: tsq: remove one locked operation in tcp_wfree()
Instead of atomically clear TSQ_THROTTLED and atomically set TSQ_QUEUED
bits, use one cmpxchg() to perform a single locked operation.
Since the following patch will also set TCP_TSQ_DEFERRED here,
this cmpxchg() will make this addition free.
Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
net/ipv4/tcp_output.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -860,6 +860,7 @@ void tcp_wfree(struct sk_buff *skb)
{
struct sock *sk = skb->sk;
struct tcp_sock *tp = tcp_sk(sk);
+ unsigned long flags, nval, oval;
int wmem;
/* Keep one reference on sk_wmem_alloc.
@@ -877,11 +878,17 @@ void tcp_wfree(struct sk_buff *skb)
if (wmem >= SKB_TRUESIZE(1) && this_cpu_ksoftirqd() == current)
goto out;
- if (test_and_clear_bit(TSQ_THROTTLED, &tp->tsq_flags) &&
- !test_and_set_bit(TSQ_QUEUED, &tp->tsq_flags)) {
- unsigned long flags;
+ for (oval = READ_ONCE(tp->tsq_flags);; oval = nval) {
struct tsq_tasklet *tsq;
+ if (!(oval & TSQF_THROTTLED) || (oval & TSQF_QUEUED))
+ goto out;
+
+ nval = (oval & ~TSQF_THROTTLED) | TSQF_QUEUED;
+ nval = cmpxchg(&tp->tsq_flags, oval, nval);
+ if (nval != oval)
+ continue;
+
/* queue this socket to tasklet queue */
local_irq_save(flags);
tsq = this_cpu_ptr(&tsq_tasklet);

71
target/linux/generic/backport-4.9/024-3-tcp-tsq-add-shortcut-in-tcp_tasklet_func.patch Normal file
View File

@ -0,0 +1,71 @@
From b223feb9de2a65c533ff95c08e834fa732906ea5 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Sat, 3 Dec 2016 11:14:52 -0800
Subject: [PATCH 03/10] tcp: tsq: add shortcut in tcp_tasklet_func()
Under high stress, I've seen tcp_tasklet_func() consuming
~700 usec, handling ~150 tcp sockets.
By setting TCP_TSQ_DEFERRED in tcp_wfree(), we give a chance
for other cpus/threads entering tcp_write_xmit() to grab it,
allowing tcp_tasklet_func() to skip sockets that already did
an xmit cycle.
In the future, we might give to ACK processing an increased
budget to reduce even more tcp_tasklet_func() amount of work.
Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
net/ipv4/tcp_output.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -767,19 +767,19 @@ static void tcp_tasklet_func(unsigned lo
list_for_each_safe(q, n, &list) {
tp = list_entry(q, struct tcp_sock, tsq_node);
list_del(&tp->tsq_node);
+ clear_bit(TSQ_QUEUED, &tp->tsq_flags);
sk = (struct sock *)tp;
- bh_lock_sock(sk);
-
- if (!sock_owned_by_user(sk)) {
- tcp_tsq_handler(sk);
- } else {
- /* defer the work to tcp_release_cb() */
- set_bit(TCP_TSQ_DEFERRED, &tp->tsq_flags);
+ if (!sk->sk_lock.owned &&
+ test_bit(TCP_TSQ_DEFERRED, &tp->tsq_flags)) {
+ bh_lock_sock(sk);
+ if (!sock_owned_by_user(sk)) {
+ clear_bit(TCP_TSQ_DEFERRED, &tp->tsq_flags);
+ tcp_tsq_handler(sk);
+ }
+ bh_unlock_sock(sk);
}
- bh_unlock_sock(sk);
- clear_bit(TSQ_QUEUED, &tp->tsq_flags);
sk_free(sk);
}
}
@@ -884,7 +884,7 @@ void tcp_wfree(struct sk_buff *skb)
if (!(oval & TSQF_THROTTLED) || (oval & TSQF_QUEUED))
goto out;
- nval = (oval & ~TSQF_THROTTLED) | TSQF_QUEUED;
+ nval = (oval & ~TSQF_THROTTLED) | TSQF_QUEUED | TCPF_TSQ_DEFERRED;
nval = cmpxchg(&tp->tsq_flags, oval, nval);
if (nval != oval)
continue;
@@ -2182,6 +2182,8 @@ static bool tcp_write_xmit(struct sock *
unlikely(tso_fragment(sk, skb, limit, mss_now, gfp)))
break;
+ if (test_bit(TCP_TSQ_DEFERRED, &tp->tsq_flags))
+ clear_bit(TCP_TSQ_DEFERRED, &tp->tsq_flags);
if (tcp_small_queue_check(sk, skb, 0))
break;

38
target/linux/generic/backport-4.9/024-4-tcp-tsq-avoid-one-atomic-in-tcp_wfree.patch Normal file
View File

@ -0,0 +1,38 @@
From a9b204d1564702b704ad6fe74f10a102c7b87ba3 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Sat, 3 Dec 2016 11:14:53 -0800
Subject: [PATCH 04/10] tcp: tsq: avoid one atomic in tcp_wfree()
Under high load, tcp_wfree() has an atomic operation trying
to schedule a tasklet over and over.
We can schedule it only if our per cpu list was empty.
Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
net/ipv4/tcp_output.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -880,6 +880,7 @@ void tcp_wfree(struct sk_buff *skb)
for (oval = READ_ONCE(tp->tsq_flags);; oval = nval) {
struct tsq_tasklet *tsq;
+ bool empty;
if (!(oval & TSQF_THROTTLED) || (oval & TSQF_QUEUED))
goto out;
@@ -892,8 +893,10 @@ void tcp_wfree(struct sk_buff *skb)
/* queue this socket to tasklet queue */
local_irq_save(flags);
tsq = this_cpu_ptr(&tsq_tasklet);
+ empty = list_empty(&tsq->head);
list_add(&tp->tsq_node, &tsq->head);
- tasklet_schedule(&tsq->tasklet);
+ if (empty)
+ tasklet_schedule(&tsq->tasklet);
local_irq_restore(flags);
return;
}

37
target/linux/generic/backport-4.9/024-5-tcp-tsq-add-a-shortcut-in-tcp_small_queue_check.patch Normal file
View File

@ -0,0 +1,37 @@
From 75eefc6c59fd2c5f1ab95a3a113c217237d12a31 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Sat, 3 Dec 2016 11:14:54 -0800
Subject: [PATCH 05/10] tcp: tsq: add a shortcut in tcp_small_queue_check()
Always allow the two first skbs in write queue to be sent,
regardless of sk_wmem_alloc/sk_pacing_rate values.
This helps a lot in situations where TX completions are delayed either
because of driver latencies or softirq latencies.
Test is done with no cache line misses.
Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
net/ipv4/tcp_output.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -2087,6 +2087,15 @@ static bool tcp_small_queue_check(struct
limit <<= factor;
if (atomic_read(&sk->sk_wmem_alloc) > limit) {
+ /* Always send the 1st or 2nd skb in write queue.
+ * No need to wait for TX completion to call us back,
+ * after softirq/tasklet schedule.
+ * This helps when TX completions are delayed too much.
+ */
+ if (skb == sk->sk_write_queue.next ||
+ skb->prev == sk->sk_write_queue.next)
+ return false;
+
set_bit(TSQ_THROTTLED, &tcp_sk(sk)->tsq_flags);
/* It is possible TX completion already happened
* before we set TSQ_THROTTLED, so we must

55
target/linux/generic/backport-4.9/024-6-tcp-tcp_mtu_probe-is-likely-to-exit-early.patch Normal file
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@ -0,0 +1,55 @@
From 12a59abc22d6664f7d3944f625ceefee92de8820 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Sat, 3 Dec 2016 11:14:55 -0800
Subject: [PATCH 06/10] tcp: tcp_mtu_probe() is likely to exit early
Adding a likely() in tcp_mtu_probe() moves its code which used to
be inlined in front of tcp_write_xmit()
We still have a cache line miss to access icsk->icsk_mtup.enabled,
we will probably have to reorganize fields to help data locality.
Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
net/ipv4/tcp_output.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -1928,26 +1928,26 @@ static inline void tcp_mtu_check_reprobe
*/
static int tcp_mtu_probe(struct sock *sk)
{
- struct tcp_sock *tp = tcp_sk(sk);
struct inet_connection_sock *icsk = inet_csk(sk);
+ struct tcp_sock *tp = tcp_sk(sk);
struct sk_buff *skb, *nskb, *next;
struct net *net = sock_net(sk);
- int len;
int probe_size;
int size_needed;
- int copy;
+ int copy, len;
int mss_now;
int interval;
/* Not currently probing/verifying,
* not in recovery,
* have enough cwnd, and
- * not SACKing (the variable headers throw things off) */
- if (!icsk->icsk_mtup.enabled ||
- icsk->icsk_mtup.probe_size ||
- inet_csk(sk)->icsk_ca_state != TCP_CA_Open ||
- tp->snd_cwnd < 11 ||
- tp->rx_opt.num_sacks || tp->rx_opt.dsack)
+ * not SACKing (the variable headers throw things off)
+ */
+ if (likely(!icsk->icsk_mtup.enabled ||
+ icsk->icsk_mtup.probe_size ||
+ inet_csk(sk)->icsk_ca_state != TCP_CA_Open ||
+ tp->snd_cwnd < 11 ||
+ tp->rx_opt.num_sacks || tp->rx_opt.dsack))
return -1;
/* Use binary search for probe_size between tcp_mss_base,

157
target/linux/generic/backport-4.9/024-7-net-reorganize-struct-sock-for-better-data-locality.patch Normal file
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@ -0,0 +1,157 @@
From 9115e8cd2a0c6eaaa900c462721f12e1d45f326c Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Sat, 3 Dec 2016 11:14:56 -0800
Subject: [PATCH 07/10] net: reorganize struct sock for better data locality
Group fields used in TX path, and keep some cache lines mostly read
to permit sharing among cpus.
Gained two 4 bytes holes on 64bit arches.
Added a place holder for tcp tsq_flags, next to sk_wmem_alloc
to speed up tcp_wfree() in the following patch.
I have not added ____cacheline_aligned_in_smp, this might be done later.
I prefer doing this once inet and tcp/udp sockets reorg is also done.
Tested with both TCP and UDP.
UDP receiver performance under flood increased by ~20 % :
Accessing sk_filter/sk_wq/sk_napi_id no longer stalls because sk_drops
was moved away from a critical cache line, now mostly read and shared.
/* --- cacheline 4 boundary (256 bytes) --- */
unsigned int sk_napi_id; /* 0x100 0x4 */
int sk_rcvbuf; /* 0x104 0x4 */
struct sk_filter * sk_filter; /* 0x108 0x8 */
union {
struct socket_wq * sk_wq; /* 0x8 */
struct socket_wq * sk_wq_raw; /* 0x8 */
}; /* 0x110 0x8 */
struct xfrm_policy * sk_policy[2]; /* 0x118 0x10 */
struct dst_entry * sk_rx_dst; /* 0x128 0x8 */
struct dst_entry * sk_dst_cache; /* 0x130 0x8 */
atomic_t sk_omem_alloc; /* 0x138 0x4 */
int sk_sndbuf; /* 0x13c 0x4 */
/* --- cacheline 5 boundary (320 bytes) --- */
int sk_wmem_queued; /* 0x140 0x4 */
atomic_t sk_wmem_alloc; /* 0x144 0x4 */
long unsigned int sk_tsq_flags; /* 0x148 0x8 */
struct sk_buff * sk_send_head; /* 0x150 0x8 */
struct sk_buff_head sk_write_queue; /* 0x158 0x18 */
__s32 sk_peek_off; /* 0x170 0x4 */
int sk_write_pending; /* 0x174 0x4 */
long int sk_sndtimeo; /* 0x178 0x8 */
Signed-off-by: Eric Dumazet <edumazet@google.com>
Tested-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
include/net/sock.h | 51 +++++++++++++++++++++++++++------------------------
1 file changed, 27 insertions(+), 24 deletions(-)
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -343,6 +343,9 @@ struct sock {
#define sk_rxhash __sk_common.skc_rxhash
socket_lock_t sk_lock;
+ atomic_t sk_drops;
+ int sk_rcvlowat;
+ struct sk_buff_head sk_error_queue;
struct sk_buff_head sk_receive_queue;
/*
* The backlog queue is special, it is always used with
@@ -359,14 +362,13 @@ struct sock {
struct sk_buff *tail;
} sk_backlog;
#define sk_rmem_alloc sk_backlog.rmem_alloc
- int sk_forward_alloc;
- __u32 sk_txhash;
+ int sk_forward_alloc;
#ifdef CONFIG_NET_RX_BUSY_POLL
- unsigned int sk_napi_id;
unsigned int sk_ll_usec;
+ /* ===== mostly read cache line ===== */
+ unsigned int sk_napi_id;
#endif
- atomic_t sk_drops;
int sk_rcvbuf;
struct sk_filter __rcu *sk_filter;
@@ -379,11 +381,30 @@ struct sock {
#endif
struct dst_entry *sk_rx_dst;
struct dst_entry __rcu *sk_dst_cache;
- /* Note: 32bit hole on 64bit arches */
- atomic_t sk_wmem_alloc;
atomic_t sk_omem_alloc;
int sk_sndbuf;
+
+ /* ===== cache line for TX ===== */
+ int sk_wmem_queued;
+ atomic_t sk_wmem_alloc;
+ unsigned long sk_tsq_flags;
+ struct sk_buff *sk_send_head;
struct sk_buff_head sk_write_queue;
+ __s32 sk_peek_off;
+ int sk_write_pending;
+ long sk_sndtimeo;
+ struct timer_list sk_timer;
+ __u32 sk_priority;
+ __u32 sk_mark;
+ u32 sk_pacing_rate; /* bytes per second */
+ u32 sk_max_pacing_rate;
+ struct page_frag sk_frag;
+ netdev_features_t sk_route_caps;
+ netdev_features_t sk_route_nocaps;
+ int sk_gso_type;
+ unsigned int sk_gso_max_size;
+ gfp_t sk_allocation;
+ __u32 sk_txhash;
/*
* Because of non atomicity rules, all
@@ -399,41 +420,23 @@ struct sock {
#define SK_PROTOCOL_MAX U8_MAX
kmemcheck_bitfield_end(flags);
- int sk_wmem_queued;
- gfp_t sk_allocation;
- u32 sk_pacing_rate; /* bytes per second */
- u32 sk_max_pacing_rate;
- netdev_features_t sk_route_caps;
- netdev_features_t sk_route_nocaps;
- int sk_gso_type;
- unsigned int sk_gso_max_size;
u16 sk_gso_max_segs;
- int sk_rcvlowat;
unsigned long sk_lingertime;
- struct sk_buff_head sk_error_queue;
struct proto *sk_prot_creator;
rwlock_t sk_callback_lock;
int sk_err,
sk_err_soft;
u32 sk_ack_backlog;
u32 sk_max_ack_backlog;
- __u32 sk_priority;
- __u32 sk_mark;
struct pid *sk_peer_pid;
const struct cred *sk_peer_cred;
long sk_rcvtimeo;
- long sk_sndtimeo;
- struct timer_list sk_timer;
ktime_t sk_stamp;
u16 sk_tsflags;
u8 sk_shutdown;
u32 sk_tskey;
struct socket *sk_socket;
void *sk_user_data;
- struct page_frag sk_frag;
- struct sk_buff *sk_send_head;
- __s32 sk_peek_off;
- int sk_write_pending;
#ifdef CONFIG_SECURITY
void *sk_security;
#endif

176
target/linux/generic/backport-4.9/024-8-tcp-tsq-move-tsq_flags-close-to-sk_wmem_alloc.patch Normal file
View File

@ -0,0 +1,176 @@
From 7aa5470c2c09265902b5e4289afa82e4e7c2987e Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Sat, 3 Dec 2016 11:14:57 -0800
Subject: [PATCH 08/10] tcp: tsq: move tsq_flags close to sk_wmem_alloc
tsq_flags being in the same cache line than sk_wmem_alloc
makes a lot of sense. Both fields are changed from tcp_wfree()
and more generally by various TSQ related functions.
Prior patch made room in struct sock and added sk_tsq_flags,
this patch deletes tsq_flags from struct tcp_sock.
Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
include/linux/tcp.h | 1 -
net/ipv4/tcp.c | 4 ++--
net/ipv4/tcp_ipv4.c | 2 +-
net/ipv4/tcp_output.c | 24 +++++++++++-------------
net/ipv4/tcp_timer.c | 4 ++--
net/ipv6/tcp_ipv6.c | 2 +-
6 files changed, 17 insertions(+), 20 deletions(-)
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -192,7 +192,6 @@ struct tcp_sock {
u32 tsoffset; /* timestamp offset */
struct list_head tsq_node; /* anchor in tsq_tasklet.head list */
- unsigned long tsq_flags;
/* Data for direct copy to user */
struct {
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -665,9 +665,9 @@ static void tcp_push(struct sock *sk, in
if (tcp_should_autocork(sk, skb, size_goal)) {
/* avoid atomic op if TSQ_THROTTLED bit is already set */
- if (!test_bit(TSQ_THROTTLED, &tp->tsq_flags)) {
+ if (!test_bit(TSQ_THROTTLED, &sk->sk_tsq_flags)) {
NET_INC_STATS(sock_net(sk), LINUX_MIB_TCPAUTOCORKING);
- set_bit(TSQ_THROTTLED, &tp->tsq_flags);
+ set_bit(TSQ_THROTTLED, &sk->sk_tsq_flags);
}
/* It is possible TX completion already happened
* before we set TSQ_THROTTLED.
--- a/net/ipv4/tcp_ipv4.c
+++ b/net/ipv4/tcp_ipv4.c
@@ -446,7 +446,7 @@ void tcp_v4_err(struct sk_buff *icmp_skb
if (!sock_owned_by_user(sk)) {
tcp_v4_mtu_reduced(sk);
} else {
- if (!test_and_set_bit(TCP_MTU_REDUCED_DEFERRED, &tp->tsq_flags))
+ if (!test_and_set_bit(TCP_MTU_REDUCED_DEFERRED, &sk->sk_tsq_flags))
sock_hold(sk);
}
goto out;
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -767,14 +767,15 @@ static void tcp_tasklet_func(unsigned lo
list_for_each_safe(q, n, &list) {
tp = list_entry(q, struct tcp_sock, tsq_node);
list_del(&tp->tsq_node);
- clear_bit(TSQ_QUEUED, &tp->tsq_flags);
sk = (struct sock *)tp;
+ clear_bit(TSQ_QUEUED, &sk->sk_tsq_flags);
+
if (!sk->sk_lock.owned &&
- test_bit(TCP_TSQ_DEFERRED, &tp->tsq_flags)) {
+ test_bit(TCP_TSQ_DEFERRED, &sk->sk_tsq_flags)) {
bh_lock_sock(sk);
if (!sock_owned_by_user(sk)) {
- clear_bit(TCP_TSQ_DEFERRED, &tp->tsq_flags);
+ clear_bit(TCP_TSQ_DEFERRED, &sk->sk_tsq_flags);
tcp_tsq_handler(sk);
}
bh_unlock_sock(sk);
@@ -797,16 +798,15 @@ static void tcp_tasklet_func(unsigned lo
*/
void tcp_release_cb(struct sock *sk)
{
- struct tcp_sock *tp = tcp_sk(sk);
unsigned long flags, nflags;
/* perform an atomic operation only if at least one flag is set */
do {
- flags = tp->tsq_flags;
+ flags = sk->sk_tsq_flags;
if (!(flags & TCP_DEFERRED_ALL))
return;
nflags = flags & ~TCP_DEFERRED_ALL;
- } while (cmpxchg(&tp->tsq_flags, flags, nflags) != flags);
+ } while (cmpxchg(&sk->sk_tsq_flags, flags, nflags) != flags);
if (flags & TCPF_TSQ_DEFERRED)
tcp_tsq_handler(sk);
@@ -878,7 +878,7 @@ void tcp_wfree(struct sk_buff *skb)
if (wmem >= SKB_TRUESIZE(1) && this_cpu_ksoftirqd() == current)
goto out;
- for (oval = READ_ONCE(tp->tsq_flags);; oval = nval) {
+ for (oval = READ_ONCE(sk->sk_tsq_flags);; oval = nval) {
struct tsq_tasklet *tsq;
bool empty;
@@ -886,7 +886,7 @@ void tcp_wfree(struct sk_buff *skb)
goto out;
nval = (oval & ~TSQF_THROTTLED) | TSQF_QUEUED | TCPF_TSQ_DEFERRED;
- nval = cmpxchg(&tp->tsq_flags, oval, nval);
+ nval = cmpxchg(&sk->sk_tsq_flags, oval, nval);
if (nval != oval)
continue;
@@ -2096,7 +2096,7 @@ static bool tcp_small_queue_check(struct
skb->prev == sk->sk_write_queue.next)
return false;
- set_bit(TSQ_THROTTLED, &tcp_sk(sk)->tsq_flags);
+ set_bit(TSQ_THROTTLED, &sk->sk_tsq_flags);
/* It is possible TX completion already happened
* before we set TSQ_THROTTLED, so we must
* test again the condition.
@@ -2194,8 +2194,8 @@ static bool tcp_write_xmit(struct sock *
unlikely(tso_fragment(sk, skb, limit, mss_now, gfp)))
break;
- if (test_bit(TCP_TSQ_DEFERRED, &tp->tsq_flags))
- clear_bit(TCP_TSQ_DEFERRED, &tp->tsq_flags);
+ if (test_bit(TCP_TSQ_DEFERRED, &sk->sk_tsq_flags))
+ clear_bit(TCP_TSQ_DEFERRED, &sk->sk_tsq_flags);
if (tcp_small_queue_check(sk, skb, 0))
break;
@@ -3508,8 +3508,6 @@ void tcp_send_ack(struct sock *sk)
/* We do not want pure acks influencing TCP Small Queues or fq/pacing
* too much.
* SKB_TRUESIZE(max(1 .. 66, MAX_TCP_HEADER)) is unfortunately ~784
- * We also avoid tcp_wfree() overhead (cache line miss accessing
- * tp->tsq_flags) by using regular sock_wfree()
*/
skb_set_tcp_pure_ack(buff);
--- a/net/ipv4/tcp_timer.c
+++ b/net/ipv4/tcp_timer.c
@@ -311,7 +311,7 @@ static void tcp_delack_timer(unsigned lo
inet_csk(sk)->icsk_ack.blocked = 1;
__NET_INC_STATS(sock_net(sk), LINUX_MIB_DELAYEDACKLOCKED);
/* deleguate our work to tcp_release_cb() */
- if (!test_and_set_bit(TCP_DELACK_TIMER_DEFERRED, &tcp_sk(sk)->tsq_flags))
+ if (!test_and_set_bit(TCP_DELACK_TIMER_DEFERRED, &sk->sk_tsq_flags))
sock_hold(sk);
}
bh_unlock_sock(sk);
@@ -594,7 +594,7 @@ static void tcp_write_timer(unsigned lon
tcp_write_timer_handler(sk);
} else {
/* delegate our work to tcp_release_cb() */
- if (!test_and_set_bit(TCP_WRITE_TIMER_DEFERRED, &tcp_sk(sk)->tsq_flags))
+ if (!test_and_set_bit(TCP_WRITE_TIMER_DEFERRED, &sk->sk_tsq_flags))
sock_hold(sk);
}
bh_unlock_sock(sk);
--- a/net/ipv6/tcp_ipv6.c
+++ b/net/ipv6/tcp_ipv6.c
@@ -404,7 +404,7 @@ static void tcp_v6_err(struct sk_buff *s
if (!sock_owned_by_user(sk))
tcp_v6_mtu_reduced(sk);
else if (!test_and_set_bit(TCP_MTU_REDUCED_DEFERRED,
- &tp->tsq_flags))
+ &sk->sk_tsq_flags))
sock_hold(sk);
goto out;
}

40
target/linux/generic/backport-4.9/024-9-tcp-add-a-missing-barrier-in-tcp_tasklet_func.patch Normal file
View File

@ -0,0 +1,40 @@
From 0a9648f1293966c838dc570da73c15a76f4c89d6 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Wed, 21 Dec 2016 05:42:43 -0800
Subject: [PATCH 09/10] tcp: add a missing barrier in tcp_tasklet_func()
Madalin reported crashes happening in tcp_tasklet_func() on powerpc64
Before TSQ_QUEUED bit is cleared, we must ensure the changes done
by list_del(&tp->tsq_node); are committed to memory, otherwise
corruption might happen, as an other cpu could catch TSQ_QUEUED
clearance too soon.
We can notice that old kernels were immune to this bug, because
TSQ_QUEUED was cleared after a bh_lock_sock(sk)/bh_unlock_sock(sk)
section, but they could have missed a kick to write additional bytes,
when NIC interrupts for a given flow are spread to multiple cpus.
Affected TCP flows would need an incoming ACK or RTO timer to add more
packets to the pipe. So overall situation should be better now.
Fixes: b223feb9de2a ("tcp: tsq: add shortcut in tcp_tasklet_func()")
Signed-off-by: Eric Dumazet <edumazet@google.com>
Reported-by: Madalin Bucur <madalin.bucur@nxp.com>
Tested-by: Madalin Bucur <madalin.bucur@nxp.com>
Tested-by: Xing Lei <xing.lei@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
net/ipv4/tcp_output.c | 1 +
1 file changed, 1 insertion(+)
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -769,6 +769,7 @@ static void tcp_tasklet_func(unsigned lo
list_del(&tp->tsq_node);
sk = (struct sock *)tp;
+ smp_mb__before_atomic();
clear_bit(TSQ_QUEUED, &sk->sk_tsq_flags);
if (!sk->sk_lock.owned &&

1412
target/linux/generic/backport-4.9/090-net-generalize-napi_complete_done.patch Normal file
View File

File diff suppressed because it is too large Load Diff

2
target/linux/generic/hack-4.9/661-use_fq_codel_by_default.patch
View File

@ -83,7 +83,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
EXPORT_SYMBOL(default_qdisc_ops); EXPORT_SYMBOL(default_qdisc_ops);
/* Main transmission queue. */ /* Main transmission queue. */
@@ -759,7 +759,7 @@ static void attach_one_default_qdisc(str @@ -760,7 +760,7 @@ static void attach_one_default_qdisc(str
void *_unused) void *_unused)
{ {
struct Qdisc *qdisc; struct Qdisc *qdisc;

2
target/linux/generic/hack-4.9/902-debloat_proc.patch
View File

@ -327,7 +327,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/core/sock.c --- a/net/core/sock.c
+++ b/net/core/sock.c +++ b/net/core/sock.c
@@ -3082,6 +3082,8 @@ static __net_initdata struct pernet_oper @@ -3084,6 +3084,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void) static int __init proto_init(void)
{ {

16
target/linux/generic/pending-4.9/630-packet_socket_type.patch
View File

@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
#define PACKET_FANOUT_LB 1 #define PACKET_FANOUT_LB 1
--- a/net/packet/af_packet.c --- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c +++ b/net/packet/af_packet.c
@@ -1772,6 +1772,7 @@ static int packet_rcv_spkt(struct sk_buf @@ -1778,6 +1778,7 @@ static int packet_rcv_spkt(struct sk_buf
{ {
struct sock *sk; struct sock *sk;
struct sockaddr_pkt *spkt; struct sockaddr_pkt *spkt;
@ -38,7 +38,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
/* /*
* When we registered the protocol we saved the socket in the data * When we registered the protocol we saved the socket in the data
@@ -1779,6 +1780,7 @@ static int packet_rcv_spkt(struct sk_buf @@ -1785,6 +1786,7 @@ static int packet_rcv_spkt(struct sk_buf
*/ */
sk = pt->af_packet_priv; sk = pt->af_packet_priv;
@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
/* /*
* Yank back the headers [hope the device set this * Yank back the headers [hope the device set this
@@ -1791,7 +1793,7 @@ static int packet_rcv_spkt(struct sk_buf @@ -1797,7 +1799,7 @@ static int packet_rcv_spkt(struct sk_buf
* so that this procedure is noop. * so that this procedure is noop.
*/ */
@ -55,7 +55,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
goto out; goto out;
if (!net_eq(dev_net(dev), sock_net(sk))) if (!net_eq(dev_net(dev), sock_net(sk)))
@@ -2029,12 +2031,12 @@ static int packet_rcv(struct sk_buff *sk @@ -2035,12 +2037,12 @@ static int packet_rcv(struct sk_buff *sk
unsigned int snaplen, res; unsigned int snaplen, res;
bool is_drop_n_account = false; bool is_drop_n_account = false;
@ -71,7 +71,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
if (!net_eq(dev_net(dev), sock_net(sk))) if (!net_eq(dev_net(dev), sock_net(sk)))
goto drop; goto drop;
@@ -2160,12 +2162,12 @@ static int tpacket_rcv(struct sk_buff *s @@ -2166,12 +2168,12 @@ static int tpacket_rcv(struct sk_buff *s
BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32); BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32);
BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48); BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48);
@ -87,7 +87,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
if (!net_eq(dev_net(dev), sock_net(sk))) if (!net_eq(dev_net(dev), sock_net(sk)))
goto drop; goto drop;
@@ -3240,6 +3242,7 @@ static int packet_create(struct net *net @@ -3250,6 +3252,7 @@ static int packet_create(struct net *net
mutex_init(&po->pg_vec_lock); mutex_init(&po->pg_vec_lock);
po->rollover = NULL; po->rollover = NULL;
po->prot_hook.func = packet_rcv; po->prot_hook.func = packet_rcv;
@ -95,7 +95,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
if (sock->type == SOCK_PACKET) if (sock->type == SOCK_PACKET)
po->prot_hook.func = packet_rcv_spkt; po->prot_hook.func = packet_rcv_spkt;
@@ -3826,6 +3829,16 @@ packet_setsockopt(struct socket *sock, i @@ -3836,6 +3839,16 @@ packet_setsockopt(struct socket *sock, i
po->xmit = val ? packet_direct_xmit : dev_queue_xmit; po->xmit = val ? packet_direct_xmit : dev_queue_xmit;
return 0; return 0;
} }
@ -112,7 +112,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
default: default:
return -ENOPROTOOPT; return -ENOPROTOOPT;
} }
@@ -3878,6 +3891,13 @@ static int packet_getsockopt(struct sock @@ -3888,6 +3901,13 @@ static int packet_getsockopt(struct sock
case PACKET_VNET_HDR: case PACKET_VNET_HDR:
val = po->has_vnet_hdr; val = po->has_vnet_hdr;
break; break;

22
target/linux/generic/pending-4.9/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
View File

@ -300,7 +300,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
/** /**
* ip6_tnl_addr_conflict - compare packet addresses to tunnel's own * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own
* @t: the outgoing tunnel device * @t: the outgoing tunnel device
@@ -1285,6 +1425,7 @@ ip6ip6_tnl_xmit(struct sk_buff *skb, str @@ -1286,6 +1426,7 @@ ip6ip6_tnl_xmit(struct sk_buff *skb, str
{ {
struct ip6_tnl *t = netdev_priv(dev); struct ip6_tnl *t = netdev_priv(dev);
struct ipv6hdr *ipv6h = ipv6_hdr(skb); struct ipv6hdr *ipv6h = ipv6_hdr(skb);
@ -308,7 +308,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
int encap_limit = -1; int encap_limit = -1;
__u16 offset; __u16 offset;
struct flowi6 fl6; struct flowi6 fl6;
@@ -1343,6 +1484,18 @@ ip6ip6_tnl_xmit(struct sk_buff *skb, str @@ -1344,6 +1485,18 @@ ip6ip6_tnl_xmit(struct sk_buff *skb, str
fl6.flowi6_mark = skb->mark; fl6.flowi6_mark = skb->mark;
} }
@ -327,7 +327,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6)) if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6))
return -1; return -1;
@@ -1470,6 +1623,14 @@ ip6_tnl_change(struct ip6_tnl *t, const @@ -1471,6 +1624,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
t->parms.flowinfo = p->flowinfo; t->parms.flowinfo = p->flowinfo;
t->parms.link = p->link; t->parms.link = p->link;
t->parms.proto = p->proto; t->parms.proto = p->proto;
@ -342,7 +342,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
dst_cache_reset(&t->dst_cache); dst_cache_reset(&t->dst_cache);
ip6_tnl_link_config(t); ip6_tnl_link_config(t);
return 0; return 0;
@@ -1508,6 +1669,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_ @@ -1509,6 +1670,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_
p->flowinfo = u->flowinfo; p->flowinfo = u->flowinfo;
p->link = u->link; p->link = u->link;
p->proto = u->proto; p->proto = u->proto;
@ -350,7 +350,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
memcpy(p->name, u->name, sizeof(u->name)); memcpy(p->name, u->name, sizeof(u->name));
} }
@@ -1885,6 +2047,15 @@ static int ip6_tnl_validate(struct nlatt @@ -1886,6 +2048,15 @@ static int ip6_tnl_validate(struct nlatt
return 0; return 0;
} }
@ -366,7 +366,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
static void ip6_tnl_netlink_parms(struct nlattr *data[], static void ip6_tnl_netlink_parms(struct nlattr *data[],
struct __ip6_tnl_parm *parms) struct __ip6_tnl_parm *parms)
{ {
@@ -1919,6 +2090,46 @@ static void ip6_tnl_netlink_parms(struct @@ -1920,6 +2091,46 @@ static void ip6_tnl_netlink_parms(struct
if (data[IFLA_IPTUN_COLLECT_METADATA]) if (data[IFLA_IPTUN_COLLECT_METADATA])
parms->collect_md = true; parms->collect_md = true;
@ -413,7 +413,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
} }
static bool ip6_tnl_netlink_encap_parms(struct nlattr *data[], static bool ip6_tnl_netlink_encap_parms(struct nlattr *data[],
@@ -2028,6 +2239,12 @@ static void ip6_tnl_dellink(struct net_d @@ -2029,6 +2240,12 @@ static void ip6_tnl_dellink(struct net_d
static size_t ip6_tnl_get_size(const struct net_device *dev) static size_t ip6_tnl_get_size(const struct net_device *dev)
{ {
@ -426,7 +426,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
return return
/* IFLA_IPTUN_LINK */ /* IFLA_IPTUN_LINK */
nla_total_size(4) + nla_total_size(4) +
@@ -2055,6 +2272,24 @@ static size_t ip6_tnl_get_size(const str @@ -2056,6 +2273,24 @@ static size_t ip6_tnl_get_size(const str
nla_total_size(2) + nla_total_size(2) +
/* IFLA_IPTUN_COLLECT_METADATA */ /* IFLA_IPTUN_COLLECT_METADATA */
nla_total_size(0) + nla_total_size(0) +
@ -451,7 +451,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
0; 0;
} }
@@ -2062,6 +2297,9 @@ static int ip6_tnl_fill_info(struct sk_b @@ -2063,6 +2298,9 @@ static int ip6_tnl_fill_info(struct sk_b
{ {
struct ip6_tnl *tunnel = netdev_priv(dev); struct ip6_tnl *tunnel = netdev_priv(dev);
struct __ip6_tnl_parm *parm = &tunnel->parms; struct __ip6_tnl_parm *parm = &tunnel->parms;
@ -461,7 +461,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) ||
nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) ||
@@ -2070,9 +2308,27 @@ static int ip6_tnl_fill_info(struct sk_b @@ -2071,9 +2309,27 @@ static int ip6_tnl_fill_info(struct sk_b
nla_put_u8(skb, IFLA_IPTUN_ENCAP_LIMIT, parm->encap_limit) || nla_put_u8(skb, IFLA_IPTUN_ENCAP_LIMIT, parm->encap_limit) ||
nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) ||
nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) ||
@ -490,7 +490,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) || if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) ||
nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) ||
nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) ||
@@ -2110,6 +2366,7 @@ static const struct nla_policy ip6_tnl_p @@ -2111,6 +2367,7 @@ static const struct nla_policy ip6_tnl_p
[IFLA_IPTUN_ENCAP_SPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_ENCAP_SPORT] = { .type = NLA_U16 },
[IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 },
[IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG },

152
target/linux/layerscape/32b/config-default
View File

@ -1,152 +0,0 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_ARCH_AXXIA is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
# CONFIG_ARCH_MULTI_CPU_AUTO is not set
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MXC=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_REQUIRE_GPIOLIB=y
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_ARM=y
# CONFIG_ARM_CPU_SUSPEND is not set
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_LPAE=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_PMU=y
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
CONFIG_ARM_VIRT_EXT=y
CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_CACHE_L2X0=y
CONFIG_CLKSRC_IMX_GPT=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_STAT_DETAILS=y
CONFIG_CPU_HAS_ASID=y
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_PABRT_V7=y
# CONFIG_CPU_THERMAL is not set
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_DEBUG_IMX_UART_PORT=1
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
# CONFIG_DEBUG_UART_8250 is not set
# CONFIG_DEBUG_USER is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
CONFIG_EXTCON=y
CONFIG_FEC=y
# CONFIG_FSL_QMAN_FQ_LOOKUP is not set
# CONFIG_FTRACE_SYSCALLS is not set
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GPIO_MXC=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IMX_SRC=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_SMP=y
CONFIG_HZ_FIXED=0
# CONFIG_IMX_WEIM is not set
CONFIG_MICREL_PHY=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGHT_HAVE_PCI=y
# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
# CONFIG_MMC_MXC is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MULTI_IRQ_HANDLER=y
CONFIG_NEON=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_OLD_SIGACTION=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PAGE_OFFSET=0x80000000
# CONFIG_PATA_IMX is not set
CONFIG_PERF_EVENTS=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PL310_ERRATA_588369=y
CONFIG_PL310_ERRATA_727915=y
# CONFIG_PL310_ERRATA_753970 is not set
CONFIG_PL310_ERRATA_769419=y
CONFIG_PM_OPP=y
CONFIG_PPS=y
# CONFIG_PROBE_EVENTS is not set
CONFIG_PTP_1588_CLOCK=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_IMXDI is not set
# CONFIG_RTC_DRV_MXC is not set
# CONFIG_SERIAL_IMX is not set
CONFIG_SMP_ON_UP=y
CONFIG_SOC_BUS=y
# CONFIG_SOC_IMX50 is not set
# CONFIG_SOC_IMX51 is not set
# CONFIG_SOC_IMX53 is not set
# CONFIG_SOC_IMX6Q is not set
# CONFIG_SOC_IMX6SL is not set
# CONFIG_SOC_IMX6SX is not set
# CONFIG_SOC_IMX6UL is not set
# CONFIG_SOC_IMX7D is not set
# CONFIG_SOC_LS1021A is not set
# CONFIG_SOC_VF610 is not set
# CONFIG_SPI_IMX is not set
CONFIG_SRAM=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THUMB2_KERNEL is not set
CONFIG_TRACING_EVENTS_GPIO=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
# CONFIG_USB_IMX21_HCD is not set
CONFIG_USE_OF=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZONE_DMA_FLAG=0

1
target/linux/layerscape/32b/profiles/00-default.mk
View File

@ -1 +0,0 @@
../../64b/profiles/00-default.mk

183
target/linux/layerscape/64b/config-default
View File

@ -1,183 +0,0 @@
CONFIG_64BIT=y
CONFIG_ACPI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_CONTAINER is not set
# CONFIG_ACPI_CUSTOM_DSDT is not set
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_DEBUGGER is not set
# CONFIG_ACPI_DOCK is not set
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_FAN=y
CONFIG_ACPI_GENERIC_GSI=y
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_ACPI_THERMAL=y
# CONFIG_ARCH_BCM_IPROC is not set
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
# CONFIG_ARCH_EXYNOS7 is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
# CONFIG_ARCH_SEATTLE is not set
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_STRATIX10 is not set
# CONFIG_ARCH_THUNDER is not set
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
CONFIG_ARM64=y
# CONFIG_ARM64_16K_PAGES is not set
CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_CRYPTO is not set
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_HW_AFDBM=y
# CONFIG_ARM64_LSE_ATOMICS is not set
CONFIG_ARM64_PAN=y
# CONFIG_ARM64_PTDUMP is not set
# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
# CONFIG_ARMV8_DEPRECATED is not set
CONFIG_ARM_AMBA=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_SP805_WATCHDOG is not set
CONFIG_ATOMIC64_SELFTEST=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BLOCK_COMPAT=y
CONFIG_BOUNCE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_BUILD_BIN2C=y
# CONFIG_CAVIUM_ERRATUM_22375 is not set
# CONFIG_CAVIUM_ERRATUM_23154 is not set
CONFIG_CLKSRC_ACPI=y
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=y
CONFIG_CMDLINE="console=ttyAMA0"
CONFIG_COMMON_CLK_VERSATILE=y
CONFIG_COMMON_CLK_XGENE=y
CONFIG_COMPAT=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_COMPAT_OLD_SIGACTION=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CUSE=y
CONFIG_DEBUG_INFO=y
CONFIG_DEFAULT_IOSCHED="noop"
CONFIG_DEFAULT_NOOP=y
CONFIG_DMI=y
CONFIG_DMIID=y
# CONFIG_DMI_SYSFS is not set
CONFIG_EFI=y
# CONFIG_EFIVAR_FS is not set
CONFIG_EFI_ARMSTUB=y
CONFIG_EFI_ESRT=y
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_STUB=y
# CONFIG_EFI_VARS is not set
CONFIG_FSL_MC_BUS=y
CONFIG_FSL_QMAN_FQ_LOOKUP=y
CONFIG_FS_MBCACHE=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIO_ACPI=y
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_XGENE is not set
CONFIG_GRACE_PERIOD=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_DEBUG_BUGVERBOSE=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_HAVE_PATA_PLATFORM=y
# CONFIG_HPET is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_RARP is not set
CONFIG_JBD2=y
# CONFIG_LIQUIDIO is not set
CONFIG_LOCKD=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_CLUT224=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MFD_CORE=y
CONFIG_MFD_VEXPRESS_SYSREG=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NFS_FS=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NO_HZ=y
CONFIG_PCI_BUS_ADDR_T_64BIT=y
# CONFIG_PCI_HISI is not set
CONFIG_PCI_LABEL=y
# CONFIG_PHY_XGENE is not set
# CONFIG_PMIC_OPREGION is not set
CONFIG_PNP=y
CONFIG_PNPACPI=y
CONFIG_PNP_DEBUG_MESSAGES=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_PROFILING=y
# CONFIG_POWER_RESET_VEXPRESS is not set
CONFIG_ROOT_NFS=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_AMBA_PL010 is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SMC91X=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SUNRPC=y
# CONFIG_SWAP is not set
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYSVIPC_COMPAT=y
# CONFIG_THUNDER_NIC_BGX is not set
# CONFIG_THUNDER_NIC_PF is not set
# CONFIG_THUNDER_NIC_VF is not set
CONFIG_UCS2_STRING=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_VEXPRESS_SYSCFG=y
CONFIG_VFAT_FS=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_BLK=y
# CONFIG_VIRTIO_CONSOLE is not set
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_NET=y

13
target/linux/layerscape/Makefile
View File

@ -9,18 +9,17 @@ include $(TOPDIR)/rules.mk
BOARD:=layerscape BOARD:=layerscape
BOARDNAME:=NXP Layerscape BOARDNAME:=NXP Layerscape
DEVICE_TYPE:=developerboard DEVICE_TYPE:=developerboard
KERNEL_PATCHVER:=4.4 KERNEL_PATCHVER:=4.9
KERNELNAME:=Image dtbs
FEATURES:=squashfs nand usb pcie gpio FEATURES:=squashfs nand usb pcie gpio
SUBTARGETS:=64b 32b SUBTARGETS:=armv8_64b armv8_32b
MAINTAINER:=Jiang Yutang <jiangyutang1978@gmail.com> MAINTAINER:=Yangbo Lu <yangbo.lu@nxp.com>
include $(INCLUDE_DIR)/target.mk
define Target/Description define Target/Description
Build firmware images for $(BOARDNAME) SoC devices. Build firmware images for NXP Layerscape based boards.
endef endef
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += kmod-usb3 kmod-usb-dwc3 kmod-usb-storage DEFAULT_PACKAGES += kmod-usb3 kmod-usb-dwc3 kmod-usb-storage
$(eval $(call BuildTarget)) $(eval $(call BuildTarget))

1444
target/linux/layerscape/armv8_32b/config-4.9 Normal file
View File

File diff suppressed because it is too large Load Diff

0
target/linux/layerscape/64b/profiles/00-default.mk → target/linux/layerscape/armv8_32b/profiles/00-default.mk
View File

8
target/linux/layerscape/32b/target.mk → target/linux/layerscape/armv8_32b/target.mk
View File

@ -6,9 +6,11 @@
# #
ARCH:=arm ARCH:=arm
BOARDNAME:=layerscape 32b boards BOARDNAME:=ARMv8 32-bit based boards
CPU_TYPE:=cortex-a9 CPU_TYPE:=cortex-a15
CPU_SUBTYPE:=neon-vfpv4
KERNELNAME:=zImage dtbs
define Target/Description define Target/Description
Build firmware images for $(BOARDNAME) SoC devices. Build firmware images for NXP Layerscape ARMv8 32-bit based boards.
endef endef

1346
target/linux/layerscape/armv8_64b/config-4.9 Normal file
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File diff suppressed because it is too large Load Diff

18
target/linux/layerscape/armv8_64b/profiles/00-default.mk Normal file
View File

@ -0,0 +1,18 @@
define Profile/Default
NAME:=Default Profile
PRIORITY:=1
endef
define Profile/Default/Description
Default package set compatible with most boards.
endef
DEFAULT_PACKAGES+= \
rcw-layerscape-ls1043ardb uboot-layerscape-$(SUBTARGET)-ls1043ardb \
fman-layerscape-ls1043ardb \
rcw-layerscape-ls1046ardb uboot-layerscape-$(SUBTARGET)-ls1046ardb \
fman-layerscape-ls1046ardb \
rcw-layerscape-ls1012ardb uboot-layerscape-$(SUBTARGET)-ls1012ardb \
kmod-ppfe ppfe-ls1012ardb
$(eval $(call Profile,Default))

6
target/linux/layerscape/64b/target.mk → target/linux/layerscape/armv8_64b/target.mk
View File

@ -6,9 +6,9 @@
# #
ARCH:=aarch64 ARCH:=aarch64
BOARDNAME:=layerscape 64b boards BOARDNAME:=ARMv8 64-bit based boards
KERNELNAME:=Image dtbs
define Target/Description define Target/Description
Build firmware images for $(BOARDNAME) SoC devices. Build firmware images for NXP Layerscape ARMv8 64-bit based boards.
endef endef

310
target/linux/layerscape/config-4.4
View File

@ -1,310 +0,0 @@
CONFIG_AQUANTIA_PHY=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_LAYERSCAPE=y
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GIC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
# CONFIG_CAVIUM_ERRATUM_27456 is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLKSRC_OF=y
CONFIG_CLKSRC_PROBE=y
CONFIG_CLK_QORIQ=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_CPU_RMAP=y
CONFIG_CRC16=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DTC=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EXT4_FS=y
CONFIG_FAT_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FMAN_ARM=y
# CONFIG_FMAN_MIB_CNT_OVF_IRQ_EN is not set
# CONFIG_FMAN_P1023 is not set
# CONFIG_FMAN_P3040_P4080_P5020 is not set
# CONFIG_FMAN_PFC is not set
# CONFIG_FMAN_V3H is not set
# CONFIG_FMAN_V3L is not set
CONFIG_FRAME_POINTER=y
CONFIG_FSL_BMAN=y
CONFIG_FSL_BMAN_CONFIG=y
CONFIG_FSL_BMAN_DEBUGFS=y
# CONFIG_FSL_BMAN_TEST is not set
CONFIG_FSL_DPA=y
# CONFIG_FSL_DPAA_1588 is not set
CONFIG_FSL_DPAA_ADVANCED_DRIVERS=y
# CONFIG_FSL_DPAA_CEETM is not set
CONFIG_FSL_DPAA_CS_THRESHOLD_10G=0x10000000
CONFIG_FSL_DPAA_CS_THRESHOLD_1G=0x06000000
# CONFIG_FSL_DPAA_DBG_LOOP is not set
# CONFIG_FSL_DPAA_ETH_DEBUG is not set
CONFIG_FSL_DPAA_ETH_DEBUGFS=y
CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT=128
CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD=80
CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE=y
CONFIG_FSL_DPAA_GENERIC_DRIVER=y
# CONFIG_FSL_DPAA_HOOKS is not set
CONFIG_FSL_DPAA_INGRESS_CS_THRESHOLD=0x10000000
# CONFIG_FSL_DPAA_MACSEC is not set
CONFIG_FSL_DPAA_OFFLINE_PORTS=y
# CONFIG_FSL_DPAA_TS is not set
CONFIG_FSL_DPA_CAN_WAIT=y
CONFIG_FSL_DPA_CAN_WAIT_SYNC=y
# CONFIG_FSL_DPA_CHECKING is not set
CONFIG_FSL_DPA_PIRQ_FAST=y
CONFIG_FSL_DPA_PIRQ_SLOW=y
CONFIG_FSL_DPA_PORTAL_SHARE=y
CONFIG_FSL_FM_MAX_FRAME_SIZE=1522
CONFIG_FSL_FM_RX_EXTRA_HEADROOM=64
CONFIG_FSL_IFC=y
CONFIG_FSL_QMAN=y
CONFIG_FSL_QMAN_CI_SCHED_CFG_BMAN_W=2
CONFIG_FSL_QMAN_CI_SCHED_CFG_RW_W=2
CONFIG_FSL_QMAN_CI_SCHED_CFG_SRCCIV=4
CONFIG_FSL_QMAN_CI_SCHED_CFG_SRQ_W=3
CONFIG_FSL_QMAN_CONFIG=y
CONFIG_FSL_QMAN_DEBUGFS=y
CONFIG_FSL_QMAN_FQD_SZ=10
CONFIG_FSL_QMAN_INIT_TIMEOUT=10
CONFIG_FSL_QMAN_PFDR_SZ=13
CONFIG_FSL_QMAN_PIRQ_DQRR_ITHRESH=12
CONFIG_FSL_QMAN_PIRQ_IPERIOD=100
CONFIG_FSL_QMAN_PIRQ_MR_ITHRESH=4
CONFIG_FSL_QMAN_POLL_LIMIT=32
# CONFIG_FSL_QMAN_TEST is not set
CONFIG_FSL_SDK_DPAA_ETH=y
CONFIG_FSL_SDK_FMAN=y
# CONFIG_FSL_SDK_FMAN_TEST is not set
CONFIG_FSL_USDPAA=y
CONFIG_FSL_XGMAC_MDIO=y
# CONFIG_FTL is not set
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
# CONFIG_GIANFAR is not set
CONFIG_GPIOLIB=y
CONFIG_GPIO_DEVRES=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_MPC8XXX=y
CONFIG_GPIO_SYSFS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_FSL_QBMAN=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_BPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_GENERIC_RCU_GUP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_RCU_TABLE_FREE=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_UID16=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
# CONFIG_HUGETLBFS is not set
CONFIG_I2C=y
# CONFIG_ACPI_I2C_OPREGION is not set
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_IMX2_WDT is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IOMMU_HELPER=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_LIBFDT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LS_SCFG_MSI=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BOARDINFO=y
CONFIG_MEMORY=y
CONFIG_MFD_SYSCON=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ESDHC=y
# CONFIG_MMC_SDHCI_PCI is not set
# CONFIG_MMC_TIFM_SD is not set
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_BE_BYTE_SWAP=y
# CONFIG_MTD_CFI_GEOMETRY is not set
# CONFIG_MTD_CFI_NOSWAP is not set
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_FSL_IFC=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NO_BOOTMEM=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_ADDRESS_PCI=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_MDIO=y
CONFIG_OF_MTD=y
CONFIG_OF_NET=y
CONFIG_OF_PCI=y
CONFIG_OF_PCI_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEBUG is not set
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_LAYERSCAPE=y
# CONFIG_POWER_RESET_XGENE is not set
CONFIG_POWER_SUPPLY=y
CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_REALTEK_PHY=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
# CONFIG_SCHED_INFO is not set
CONFIG_SCSI=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SMP=y
CONFIG_SPARSE_IRQ=y
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_SQUASHFS_XATTR is not set
# CONFIG_SQUASHFS_ZLIB is not set
# CONFIG_SQUASHFS_LZ4 is not set
# CONFIG_SQUASHFS_LZO is not set
CONFIG_SQUASHFS_XZ=y
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
CONFIG_SRCU=y
CONFIG_SWIOTLB=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TREE_RCU=y
CONFIG_USB_SUPPORT=y
CONFIG_USB=y
CONFIG_VITESSE_PHY=y
CONFIG_XPS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_MTD_SPI_NOR=y
CONFIG_SPI_FSL_QUADSPI=y
CONFIG_FSL_MC_BUS=y
CONFIG_FSL_MC_RESTOOL=y
CONFIG_FSL_MC_DPIO=y
# CONFIG_FSL_QBMAN_DEBUG is not set
CONFIG_FSL_DPAA2=y
CONFIG_FSL_DPAA2_ETH=y
# CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE is not set
CONFIG_FSL_DPAA2_MAC=y
# CONFIG_FSL_DPAA2_MAC_NETDEVS is not set
CONFIG_FSL_DPAA2_EVB=y
CONFIG_FSL_DPAA2_ETHSW=y

75
target/linux/layerscape/image/Makefile
View File

@ -33,15 +33,17 @@ endef
define Device/Default define Device/Default
PROFILES = Default PROFILES = Default
FILESYSTEMS := squashfs FILESYSTEMS := squashfs
KERNEL := kernel-bin | gzip | uImage gzip
DEVICE_DTS := DEVICE_DTS :=
IMAGES = firmware.bin IMAGES = firmware.bin
ifeq ($(SUBTARGET),64b) ifeq ($(SUBTARGET),armv8_64b)
KERNEL := kernel-bin | gzip | uImage gzip
KERNEL_LOADADDR = 0x80080000 KERNEL_LOADADDR = 0x80080000
KERNEL_ENTRY_POINT = 0x80080000 KERNEL_ENTRY_POINT = 0x80080000
endif endif
ifeq ($(SUBTARGET),32b) ifeq ($(SUBTARGET),armv8_32b)
KERNEL := kernel-bin | uImage none
KERNEL_NAME := zImage
KERNEL_LOADADDR = 0x80008000 KERNEL_LOADADDR = 0x80008000
KERNEL_ENTRY_POINT = 0x80008000 KERNEL_ENTRY_POINT = 0x80008000
endif endif
@ -50,74 +52,61 @@ endef
define Device/ls1043ardb define Device/ls1043ardb
DEVICE_TITLE := ls1043ardb-$(SUBTARGET) DEVICE_TITLE := ls1043ardb-$(SUBTARGET)
DEVICE_PACKAGES += rcw-layerscape-ls1043ardb uboot-layerscape-$(SUBTARGET)-ls1043ardb fman-layerscape-ls1043ardb DEVICE_PACKAGES += rcw-layerscape-ls1043ardb uboot-layerscape-$(SUBTARGET)-ls1043ardb fman-layerscape-ls1043ardb
ifeq ($(SUBTARGET),64b) DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk
DEVICE_DTS = freescale/fsl-ls1043a-rdb IMAGE/firmware.bin = append-ls-rcw $(1) | pad-to 1M | \
endif append-ls-uboot $(1) | pad-to 9M | \
ifeq ($(SUBTARGET),32b) append-ls-fman $(1) | pad-to 15M | \
DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1043a-rdb append-ls-dtb $$(DEVICE_DTS) | pad-to 16M | \
endif append-kernel | pad-to 32M | \
IMAGE/firmware.bin = append-ls-rcw $(1) | pad-to 1M | append-ls-uboot $(1) | pad-to 3M | \ append-rootfs | pad-rootfs | check-size 67108865
append-ls-fman $(1) | pad-to 4M | append-ls-dtb $$(DEVICE_DTS) | pad-to 5M | \
append-kernel | pad-to 10M | append-rootfs | pad-rootfs | check-size 67108865
endef endef
TARGET_DEVICES += ls1043ardb TARGET_DEVICES += ls1043ardb
define Device/ls1046ardb define Device/ls1046ardb
DEVICE_TITLE := ls1046ardb-$(SUBTARGET) DEVICE_TITLE := ls1046ardb-$(SUBTARGET)
DEVICE_PACKAGES += rcw-layerscape-ls1046ardb uboot-layerscape-$(SUBTARGET)-ls1046ardb fman-layerscape-ls1046ardb DEVICE_PACKAGES += rcw-layerscape-ls1046ardb uboot-layerscape-$(SUBTARGET)-ls1046ardb fman-layerscape-ls1046ardb
ifeq ($(SUBTARGET),64b) DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk
DEVICE_DTS = freescale/fsl-ls1046a-rdb IMAGE/firmware.bin = append-ls-rcw $(1) | pad-to 1M | \
endif append-ls-uboot $(1) | pad-to 9M | \
ifeq ($(SUBTARGET),32b) append-ls-fman $(1) | pad-to 15M | \
DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1046a-rdb append-ls-dtb $$(DEVICE_DTS) | pad-to 16M | \
endif append-kernel | pad-to 32M | \
IMAGE/firmware.bin = append-ls-rcw $(1) | pad-to 1M | append-ls-uboot $(1) | pad-to 3M | \ append-ls-rootfs-ext4 $(1) 22M | check-size 67108865
append-ls-fman $(1) | pad-to 4M | append-ls-dtb $$(DEVICE_DTS) | pad-to 5M | \
append-kernel | pad-to 10M | append-ls-rootfs-ext4 $(1) 22M | check-size 33554433
endef endef
TARGET_DEVICES += ls1046ardb TARGET_DEVICES += ls1046ardb
define Device/ls1012ardb define Device/ls1012ardb
DEVICE_TITLE := ls1012ardb-$(SUBTARGET) DEVICE_TITLE := ls1012ardb-$(SUBTARGET)
DEVICE_PACKAGES += rcw-layerscape-ls1012ardb uboot-layerscape-$(SUBTARGET)-ls1012ardb kmod-ppfe ppfe-ls1012ardb DEVICE_PACKAGES += rcw-layerscape-ls1012ardb uboot-layerscape-$(SUBTARGET)-ls1012ardb kmod-ppfe ppfe-ls1012ardb
ifeq ($(SUBTARGET),64b)
DEVICE_DTS = freescale/fsl-ls1012a-rdb
endif
ifeq ($(SUBTARGET),32b)
DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1012a-rdb DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1012a-rdb
endif IMAGE/firmware.bin = append-ls-rcw $(1) | pad-to 1M | \
IMAGE/firmware.bin = append-ls-rcw $(1) | pad-to 1M | append-ls-uboot $(1) | pad-to 3M | \ append-ls-uboot $(1) | pad-to 15M | \
append-ls-dtb $$(DEVICE_DTS) | pad-to 4M | append-kernel | pad-to 9M | \ append-ls-dtb $$(DEVICE_DTS) | pad-to 16M | \
append-ls-rootfs-ext4 $(1) 23M | check-size 33554433 append-kernel | pad-to 32M | \
append-ls-rootfs-ext4 $(1) 23M | check-size 67108865
endef endef
TARGET_DEVICES += ls1012ardb TARGET_DEVICES += ls1012ardb
ifeq ($(SUBTARGET),armv8_64b)
define Device/ls1088ardb define Device/ls1088ardb
DEVICE_TITLE := ls1088ardb-$(SUBTARGET) DEVICE_TITLE := ls1088ardb-$(SUBTARGET)
DEVICE_PACKAGES += rcw-layerscape-ls1088ardb uboot-layerscape-$(SUBTARGET)-ls1088ardb mc-binary-ls1088ardb DEVICE_PACKAGES += rcw-layerscape-ls1088ardb uboot-layerscape-$(SUBTARGET)-ls1088ardb mc-binary-ls1088ardb
ifeq ($(SUBTARGET),64b)
DEVICE_DTS = freescale/fsl-ls1088a-rdb
endif
ifeq ($(SUBTARGET),32b)
DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1088a-rdb DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1088a-rdb
endif IMAGE/firmware.bin = append-ls-dtb $$(DEVICE_DTS) | pad-to 1M | \
IMAGE/firmware.bin = append-ls-dtb $$(DEVICE_DTS) | pad-to 1M | append-kernel | pad-to 6M | \ append-kernel | pad-to 17M | \
append-ls-rootfs-ext4 $(1) 17M | check-size 24117249 append-ls-rootfs-ext4 $(1) 17M | check-size 51380225
endef endef
TARGET_DEVICES += ls1088ardb TARGET_DEVICES += ls1088ardb
define Device/ls2088ardb define Device/ls2088ardb
DEVICE_TITLE := ls2088ardb-$(SUBTARGET) DEVICE_TITLE := ls2088ardb-$(SUBTARGET)
DEVICE_PACKAGES += rcw-layerscape-ls2088ardb uboot-layerscape-$(SUBTARGET)-ls2088ardb mc-binary-ls2088ardb DEVICE_PACKAGES += rcw-layerscape-ls2088ardb uboot-layerscape-$(SUBTARGET)-ls2088ardb mc-binary-ls2088ardb
ifeq ($(SUBTARGET),64b)
DEVICE_DTS = freescale/fsl-ls2088a-rdb
endif
ifeq ($(SUBTARGET),32b)
DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls2088a-rdb DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls2088a-rdb
endif IMAGE/firmware.bin = append-ls-dtb $$(DEVICE_DTS) | pad-to 1M | \
IMAGE/firmware.bin = append-ls-dtb $$(DEVICE_DTS) | pad-to 1M | append-kernel | pad-to 6M | \ append-kernel | pad-to 17M | \
append-rootfs | pad-rootfs | check-size 24117249 append-rootfs | pad-rootfs | check-size 51380225
endef endef
TARGET_DEVICES += ls2088ardb TARGET_DEVICES += ls2088ardb
endif
$(eval $(call BuildImage)) $(eval $(call BuildImage))

43
target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch
View File

@ -1,43 +0,0 @@
From 7f434723cdb6823443330cd4847d5c3b8dd30bd7 Mon Sep 17 00:00:00 2001
From: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Date: Fri, 18 Dec 2015 14:38:55 +0200
Subject: [PATCH 51/70] PCI: designware: Ensure ATU is enabled before IO/conf
space accesses
Read back the ATU CR2 register to ensure ATU programming is effective
before any subsequent I/O or config space accesses.
Without this, PCI device enumeration is unreliable.
[bhelgaas: changelog, comment]
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
---
drivers/pci/host/pcie-designware.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -154,6 +154,8 @@ static int dw_pcie_wr_own_conf(struct pc
static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
int type, u64 cpu_addr, u64 pci_addr, u32 size)
{
+ u32 val;
+
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
@@ -164,6 +166,12 @@ static void dw_pcie_prog_outbound_atu(st
dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+
+ /*
+ * Make sure ATU enable takes effect before any subsequent config
+ * and I/O accesses.
+ */
+ dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
}
static struct irq_chip dw_msi_irq_chip = {

121
target/linux/layerscape/patches-4.4/0052-PCI-designware-Simplify-control-flow.patch
View File

@ -1,121 +0,0 @@
From 610b32220391c9d271290bdf8f2b8fe1cf8da9a0 Mon Sep 17 00:00:00 2001
From: Bjorn Helgaas <bhelgaas@google.com>
Date: Tue, 5 Jan 2016 15:48:11 -0600
Subject: [PATCH 52/70] PCI: designware: Simplify control flow
Return values immediately when possible to simplify the control flow.
No functional change intended. Folded in unused variable removal as
pointed out by Fabio Estevam <fabio.estevam@nxp.com>, Arnd Bergmann
<arnd@arndb.de>, and Thierry Reding <thierry.reding@gmail.com>.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
---
drivers/pci/host/pcie-designware.c | 54 ++++++++++++------------------------
1 file changed, 18 insertions(+), 36 deletions(-)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -128,27 +128,19 @@ static inline void dw_pcie_writel_rc(str
static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
u32 *val)
{
- int ret;
-
if (pp->ops->rd_own_conf)
- ret = pp->ops->rd_own_conf(pp, where, size, val);
- else
- ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
+ return pp->ops->rd_own_conf(pp, where, size, val);
- return ret;
+ return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
}
static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
u32 val)
{
- int ret;
-
if (pp->ops->wr_own_conf)
- ret = pp->ops->wr_own_conf(pp, where, size, val);
- else
- ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
+ return pp->ops->wr_own_conf(pp, where, size, val);
- return ret;
+ return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
}
static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
@@ -392,8 +384,8 @@ int dw_pcie_link_up(struct pcie_port *pp
{
if (pp->ops->link_up)
return pp->ops->link_up(pp);
- else
- return 0;
+
+ return 0;
}
static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
@@ -666,46 +658,36 @@ static int dw_pcie_rd_conf(struct pci_bu
int size, u32 *val)
{
struct pcie_port *pp = bus->sysdata;
- int ret;
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
- if (bus->number != pp->root_bus_nr)
- if (pp->ops->rd_other_conf)
- ret = pp->ops->rd_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = dw_pcie_rd_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = dw_pcie_rd_own_conf(pp, where, size, val);
+ if (bus->number == pp->root_bus_nr)
+ return dw_pcie_rd_own_conf(pp, where, size, val);
- return ret;
+ if (pp->ops->rd_other_conf)
+ return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
+
+ return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
}
static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
struct pcie_port *pp = bus->sysdata;
- int ret;
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
- if (bus->number != pp->root_bus_nr)
- if (pp->ops->wr_other_conf)
- ret = pp->ops->wr_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = dw_pcie_wr_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = dw_pcie_wr_own_conf(pp, where, size, val);
+ if (bus->number == pp->root_bus_nr)
+ return dw_pcie_wr_own_conf(pp, where, size, val);
- return ret;
+ if (pp->ops->wr_other_conf)
+ return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
+
+ return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
}
static struct pci_ops dw_pcie_ops = {

71
target/linux/layerscape/patches-4.4/0053-PCI-designware-Make-config-accessor-override-checkin.patch
View File

@ -1,71 +0,0 @@
From 6882f9eef932e6f5cc3c57115e3d7d4b5bc19662 Mon Sep 17 00:00:00 2001
From: Bjorn Helgaas <bhelgaas@google.com>
Date: Tue, 5 Jan 2016 15:56:30 -0600
Subject: [PATCH 53/70] PCI: designware: Make config accessor override
checking symmetric
Drivers based on the DesignWare core can override the config read accessors
by supplying rd_own_conf() and rd_other_conf() function pointers.
dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root
bus) or dw_pcie_rd_other_conf():
dw_pcie_rd_conf
dw_pcie_rd_own_conf # if on root bus
dw_pcie_rd_other_conf # if not on root bus
Previously we checked for rd_other_conf() directly in dw_pcie_rd_conf(),
but we checked for rd_own_conf() in dw_pcie_rd_own_conf().
Check for rd_other_conf() in dw_pcie_rd_other_conf() to make this symmetric
with the rd_own_conf() checking, and similarly for the write path.
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
---
drivers/pci/host/pcie-designware.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -571,6 +571,9 @@ static int dw_pcie_rd_other_conf(struct
u64 cpu_addr;
void __iomem *va_cfg_base;
+ if (pp->ops->rd_other_conf)
+ return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
+
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn));
@@ -605,6 +608,9 @@ static int dw_pcie_wr_other_conf(struct
u64 cpu_addr;
void __iomem *va_cfg_base;
+ if (pp->ops->wr_other_conf)
+ return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
+
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn));
@@ -667,9 +673,6 @@ static int dw_pcie_rd_conf(struct pci_bu
if (bus->number == pp->root_bus_nr)
return dw_pcie_rd_own_conf(pp, where, size, val);
- if (pp->ops->rd_other_conf)
- return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
-
return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
}
@@ -684,9 +687,6 @@ static int dw_pcie_wr_conf(struct pci_bu
if (bus->number == pp->root_bus_nr)
return dw_pcie_wr_own_conf(pp, where, size, val);
- if (pp->ops->wr_other_conf)
- return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
-
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
}

34
target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch
View File

@ -1,34 +0,0 @@
From 481b1bc4ce0d58107887558342e50d6323a9601d Mon Sep 17 00:00:00 2001
From: Jisheng Zhang <jszhang@marvell.com>
Date: Thu, 7 Jan 2016 14:12:38 +0800
Subject: [PATCH 54/70] PCI: designware: Explain why we don't program ATU for
some platforms
Some platforms don't support ATU, e.g., pci-keystone.c. These platforms
use their own address translation component rather than ATU, and they
provide the rd_other_conf and wr_other_conf methods to program the
translation component and perform the access.
Add a comment to explain why we don't program the ATU for these platforms.
[bhelgaas: changelog]
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-designware.c | 5 +++++
1 file changed, 5 insertions(+)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -517,6 +517,11 @@ int dw_pcie_host_init(struct pcie_port *
if (pp->ops->host_init)
pp->ops->host_init(pp);
+ /*
+ * If the platform provides ->rd_other_conf, it means the platform
+ * uses its own address translation component rather than ATU, so
+ * we should not program the ATU here.
+ */
if (!pp->ops->rd_other_conf)
dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
PCIE_ATU_TYPE_MEM, pp->mem_base,

41
target/linux/layerscape/patches-4.4/0055-PCI-designware-Remove-PCI_PROBE_ONLY-handling.patch
View File

@ -1,41 +0,0 @@
From ee2a430c1691d0bac3098e8db3c29d8f023b04c2 Mon Sep 17 00:00:00 2001
From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Date: Fri, 29 Jan 2016 11:29:32 +0000
Subject: [PATCH 55/70] PCI: designware: Remove PCI_PROBE_ONLY handling
The PCIe designware host driver is not used in system configurations
requiring the PCI_PROBE_ONLY flag to be set to prevent resources
assignment, therefore the driver code handling the flag can be removed
from the kernel.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
Acked-by: Jingoo Han Jingoo Han <jingoohan1@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
---
drivers/pci/host/pcie-designware.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -556,13 +556,11 @@ int dw_pcie_host_init(struct pcie_port *
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
#endif
- if (!pci_has_flag(PCI_PROBE_ONLY)) {
- pci_bus_size_bridges(bus);
- pci_bus_assign_resources(bus);
+ pci_bus_size_bridges(bus);
+ pci_bus_assign_resources(bus);
- list_for_each_entry(child, &bus->children, node)
- pcie_bus_configure_settings(child);
- }
+ list_for_each_entry(child, &bus->children, node)
+ pcie_bus_configure_settings(child);
pci_bus_add_devices(bus);
return 0;

249
target/linux/layerscape/patches-4.4/0056-PCI-designware-Add-generic-dw_pcie_wait_for_link.patch
View File

@ -1,249 +0,0 @@
From f0c3f31a8bd81b8e7354a187c49200f3ce52740d Mon Sep 17 00:00:00 2001
From: Joao Pinto <Joao.Pinto@synopsys.com>
Date: Thu, 10 Mar 2016 14:44:35 -0600
Subject: [PATCH 56/70] PCI: designware: Add generic dw_pcie_wait_for_link()
commit 886bc5ceb5cc3ad4b219502d72b277e3c3255a32 upstream
[context adjustment]
[remove drivers/pci/host/pcie-qcom.c related changes]
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.
Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.
[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
---
drivers/pci/host/pci-dra7xx.c | 11 +----------
drivers/pci/host/pci-exynos.c | 13 +++----------
drivers/pci/host/pci-imx6.c | 13 ++++---------
drivers/pci/host/pci-keystone.c | 10 ++++------
drivers/pci/host/pcie-designware.c | 19 +++++++++++++++++++
drivers/pci/host/pcie-designware.h | 6 ++++++
drivers/pci/host/pcie-spear13xx.c | 14 +-------------
7 files changed, 38 insertions(+), 48 deletions(-)
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -10,7 +10,6 @@
* published by the Free Software Foundation.
*/
-#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
@@ -108,7 +107,6 @@ static int dra7xx_pcie_establish_link(st
{
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
u32 reg;
- unsigned int retries;
if (dw_pcie_link_up(pp)) {
dev_err(pp->dev, "link is already up\n");
@@ -119,14 +117,7 @@ static int dra7xx_pcie_establish_link(st
reg |= LTSSM_EN;
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
- for (retries = 0; retries < 1000; retries++) {
- if (dw_pcie_link_up(pp))
- return 0;
- usleep_range(10, 20);
- }
-
- dev_err(pp->dev, "link is not up\n");
- return -EINVAL;
+ return dw_pcie_wait_for_link(pp);
}
static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -318,7 +318,6 @@ static int exynos_pcie_establish_link(st
{
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
u32 val;
- unsigned int retries;
if (dw_pcie_link_up(pp)) {
dev_err(pp->dev, "Link already up\n");
@@ -357,13 +356,8 @@ static int exynos_pcie_establish_link(st
PCIE_APP_LTSSM_ENABLE);
/* check if the link is up or not */
- for (retries = 0; retries < 10; retries++) {
- if (dw_pcie_link_up(pp)) {
- dev_info(pp->dev, "Link up\n");
- return 0;
- }
- mdelay(100);
- }
+ if (!dw_pcie_wait_for_link(pp))
+ return 0;
while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
@@ -372,8 +366,7 @@ static int exynos_pcie_establish_link(st
/* power off phy */
exynos_pcie_power_off_phy(pp);
- dev_err(pp->dev, "PCIe Link Fail\n");
- return -EINVAL;
+ return -ETIMEDOUT;
}
static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -330,19 +330,14 @@ static void imx6_pcie_init_phy(struct pc
static int imx6_pcie_wait_for_link(struct pcie_port *pp)
{
- unsigned int retries;
+ /* check if the link is up or not */
+ if (!dw_pcie_wait_for_link(pp))
+ return 0;
- for (retries = 0; retries < 200; retries++) {
- if (dw_pcie_link_up(pp))
- return 0;
- usleep_range(100, 1000);
- }
-
- dev_err(pp->dev, "phy link never came up\n");
dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
- return -EINVAL;
+ return -ETIMEDOUT;
}
static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
@@ -97,17 +97,15 @@ static int ks_pcie_establish_link(struct
return 0;
}
- ks_dw_pcie_initiate_link_train(ks_pcie);
/* check if the link is up or not */
- for (retries = 0; retries < 200; retries++) {
- if (dw_pcie_link_up(pp))
- return 0;
- usleep_range(100, 1000);
+ for (retries = 0; retries < 5; retries++) {
ks_dw_pcie_initiate_link_train(ks_pcie);
+ if (!dw_pcie_wait_for_link(pp))
+ return 0;
}
dev_err(pp->dev, "phy link never came up\n");
- return -EINVAL;
+ return -ETIMEDOUT;
}
static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -22,6 +22,7 @@
#include <linux/pci_regs.h>
#include <linux/platform_device.h>
#include <linux/types.h>
+#include <linux/delay.h>
#include "pcie-designware.h"
@@ -380,6 +381,24 @@ static struct msi_controller dw_pcie_msi
.teardown_irq = dw_msi_teardown_irq,
};
+int dw_pcie_wait_for_link(struct pcie_port *pp)
+{
+ int retries;
+
+ /* check if the link is up or not */
+ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+ if (dw_pcie_link_up(pp)) {
+ dev_info(pp->dev, "link up\n");
+ return 0;
+ }
+ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
+ }
+
+ dev_err(pp->dev, "phy link never came up\n");
+
+ return -ETIMEDOUT;
+}
+
int dw_pcie_link_up(struct pcie_port *pp)
{
if (pp->ops->link_up)
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -22,6 +22,11 @@
#define MAX_MSI_IRQS 32
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
+/* Parameters for the waiting for link up routine */
+#define LINK_WAIT_MAX_RETRIES 10
+#define LINK_WAIT_USLEEP_MIN 90000
+#define LINK_WAIT_USLEEP_MAX 100000
+
struct pcie_port {
struct device *dev;
u8 root_bus_nr;
@@ -76,6 +81,7 @@ int dw_pcie_cfg_read(void __iomem *addr,
int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
void dw_pcie_msi_init(struct pcie_port *pp);
+int dw_pcie_wait_for_link(struct pcie_port *pp);
int dw_pcie_link_up(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);
--- a/drivers/pci/host/pcie-spear13xx.c
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -13,7 +13,6 @@
*/
#include <linux/clk.h>
-#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
@@ -149,7 +148,6 @@ static int spear13xx_pcie_establish_link
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
u32 exp_cap_off = EXP_CAP_ID_OFFSET;
- unsigned int retries;
if (dw_pcie_link_up(pp)) {
dev_err(pp->dev, "link already up\n");
@@ -200,17 +198,7 @@ static int spear13xx_pcie_establish_link
| ((u32)1 << REG_TRANSLATION_ENABLE),
&app_reg->app_ctrl_0);
- /* check if the link is up or not */
- for (retries = 0; retries < 10; retries++) {
- if (dw_pcie_link_up(pp)) {
- dev_info(pp->dev, "link up\n");
- return 0;
- }
- mdelay(100);
- }
-
- dev_err(pp->dev, "link Fail\n");
- return -EINVAL;
+ return dw_pcie_wait_for_link(pp);
}
static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)

46
target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch
View File

@ -1,46 +0,0 @@
From a0a4f406c7e90b2be66e88ea8b21699940c0823f Mon Sep 17 00:00:00 2001
From: Joao Pinto <Joao.Pinto@synopsys.com>
Date: Thu, 10 Mar 2016 14:44:44 -0600
Subject: [PATCH 57/70] PCI: designware: Add default link up check if
sub-driver doesn't override
Add a default DesignWare "link_up" test for use when a sub-driver doesn't
supply its own pcie_host_ops.link_up() method.
[bhelgaas: changelog, split into its own patch]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
---
drivers/pci/host/pcie-designware.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -70,6 +70,11 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
+/* PCIe Port Logic registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
+#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
+
static struct pci_ops dw_pcie_ops;
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
@@ -401,10 +406,13 @@ int dw_pcie_wait_for_link(struct pcie_po
int dw_pcie_link_up(struct pcie_port *pp)
{
+ u32 val;
+
if (pp->ops->link_up)
return pp->ops->link_up(pp);
- return 0;
+ val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
+ return val & PCIE_PHY_DEBUG_R1_LINK_UP;
}
static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,

109
target/linux/layerscape/patches-4.4/0058-PCI-designware-Move-Root-Complex-setup-code-to-dw_pc.patch
View File

@ -1,109 +0,0 @@
From 892a427f8a2b25b561298941cf1fc0373a98b269 Mon Sep 17 00:00:00 2001
From: Jisheng Zhang <jszhang@marvell.com>
Date: Wed, 16 Mar 2016 19:40:33 +0800
Subject: [PATCH 58/70] PCI: designware: Move Root Complex setup code to
dw_pcie_setup_rc()
dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates
IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc()
programs the Root Complex registers. The Root Complex may lose power
during suspend-to-RAM, and when we resume, we want to redo the latter but
not the former.
Move some Root Complex programming from dw_pcie_host_init() to
dw_pcie_setup_rc() where it belongs. DesignWare-based drivers can call
dw_pcie_setup_rc() in their resume paths.
[Niklas Cassel <niklas.cassel@axis.com>: This change moves outbound ATU
programming, which uses pp->mem_base, to dw_pcie_setup_rc(). Apply the
dra7xx pp->mem_base update before calling dw_pcie_setup_rc().]
[bhelgaas: changelog, fold in dra7xx fix from Niklas]
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
---
drivers/pci/host/pci-dra7xx.c | 4 ++--
drivers/pci/host/pcie-designware.c | 39 ++++++++++++++++++------------------
2 files changed, 21 insertions(+), 22 deletions(-)
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -142,13 +142,13 @@ static void dra7xx_pcie_enable_interrupt
static void dra7xx_pcie_host_init(struct pcie_port *pp)
{
- dw_pcie_setup_rc(pp);
-
pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
+ dw_pcie_setup_rc(pp);
+
dra7xx_pcie_establish_link(pp);
if (IS_ENABLED(CONFIG_PCI_MSI))
dw_pcie_msi_init(pp);
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -434,7 +434,6 @@ int dw_pcie_host_init(struct pcie_port *
struct platform_device *pdev = to_platform_device(pp->dev);
struct pci_bus *bus, *child;
struct resource *cfg_res;
- u32 val;
int i, ret;
LIST_HEAD(res);
struct resource_entry *win;
@@ -544,25 +543,6 @@ int dw_pcie_host_init(struct pcie_port *
if (pp->ops->host_init)
pp->ops->host_init(pp);
- /*
- * If the platform provides ->rd_other_conf, it means the platform
- * uses its own address translation component rather than ATU, so
- * we should not program the ATU here.
- */
- if (!pp->ops->rd_other_conf)
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_MEM, pp->mem_base,
- pp->mem_bus_addr, pp->mem_size);
-
- dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
-
- /* program correct class for RC */
- dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
-
- dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
- val |= PORT_LOGIC_SPEED_CHANGE;
- dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
-
pp->root_bus_nr = pp->busn->start;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
@@ -800,6 +780,25 @@ void dw_pcie_setup_rc(struct pcie_port *
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+
+ /*
+ * If the platform provides ->rd_other_conf, it means the platform
+ * uses its own address translation component rather than ATU, so
+ * we should not program the ATU here.
+ */
+ if (!pp->ops->rd_other_conf)
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_MEM, pp->mem_base,
+ pp->mem_bus_addr, pp->mem_size);
+
+ dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
+
+ /* program correct class for RC */
+ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+
+ dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
+ val |= PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
}
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");

45
target/linux/layerscape/patches-4.4/0059-PCI-designware-Remove-incorrect-RC-memory-base-limit.patch
View File

@ -1,45 +0,0 @@
From ae717a9744a3e18f2ed0a6aa44e279c89ad5052c Mon Sep 17 00:00:00 2001
From: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Date: Sat, 16 Apr 2016 12:03:39 +0100
Subject: [PATCH 59/70] PCI: designware: Remove incorrect RC memory base/limit
configuration
Currently dw_pcie_setup_rc() configures memory base and memory limit in the
type1 configuration header for the root complex. In doing so it uses the
CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
This is wrong and it is useless since the configuration is overwritten
later on when pci_bus_assign_resources() is called.
Remove this configuration from dw_pcie_setup_rc().
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
---
drivers/pci/host/pcie-designware.c | 8 --------
1 file changed, 8 deletions(-)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -708,8 +708,6 @@ static struct pci_ops dw_pcie_ops = {
void dw_pcie_setup_rc(struct pcie_port *pp)
{
u32 val;
- u32 membase;
- u32 memlimit;
/* set the number of lanes */
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
@@ -768,12 +766,6 @@ void dw_pcie_setup_rc(struct pcie_port *
val |= 0x00010100;
dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
- /* setup memory base, memory limit */
- membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
- memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
- val = memlimit | membase;
- dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
-
/* setup command register */
dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
val &= 0xffff0000;

148
target/linux/layerscape/patches-4.4/0140-config-add-freescale-config-for-amr64.patch
View File

@ -1,148 +0,0 @@
From 880b7aa2e2c62e54245fb77d92db502175232d86 Mon Sep 17 00:00:00 2001
From: Zhao Qiang <qiang.zhao@nxp.com>
Date: Wed, 12 Oct 2016 11:01:17 +0800
Subject: [PATCH 140/141] config: add freescale config for amr64
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
arch/arm64/configs/freescale.config | 134 +++++++++++++++++++++++++++++++++++
1 file changed, 134 insertions(+)
create mode 100644 arch/arm64/configs/freescale.config
--- /dev/null
+++ b/arch/arm64/configs/freescale.config
@@ -0,0 +1,134 @@
+# general options
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SLAB=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_PRINTK_TIME=y
+CONFIG_PID_IN_CONTEXTIDR=y
+CONFIG_IPV6=y
+# iommu
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_ARM_SMMU=y
+# dpaa2
+CONFIG_STAGING=y
+CONFIG_FSL_MC_BUS=y
+CONFIG_FSL_MC_RESTOOL=y
+CONFIG_FSL_MC_DPIO=y
+CONFIG_FSL_DPAA2=y
+CONFIG_NET_NS=y
+CONFIG_FSL_DPAA2_DCE=y
+CONFIG_FSL_DCE_FLOW_LIMIT=65536
+CONFIG_FSL_DCE_API_TIME_TRIAL=m
+CONFIG_LS_SOC_DRIVERS=y
+# mdio
+CONFIG_FSL_XGMAC_MDIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+# phy
+CONFIG_AQUANTIA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_FIXED_PHY=y
+# reset support
+CONFIG_POWER_RESET_LAYERSCAPE=y
+# pci
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_E1000=y
+CONFIG_E1000E=y
+# clock driver
+CONFIG_CLK_QORIQ=y
+# usb
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_DMADEVICES=y
+# ahci/sata
+CONFIG_AHCI_QORIQ=y
+# esdhc
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# virtualization
+CONFIG_VHOST_NET=y
+CONFIG_KVM_ARM_MAX_VCPUS=8
+# I2C
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_IMX=y
+# hardware monitor
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_INA2XX=y
+# DPAA 1
+CONFIG_HAS_FSL_QBMAN=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+# network
+CONFIG_BRIDGE=m
+CONFIG_MACVLAN=y
+CONFIG_FSL_SDK_FMAN=y
+CONFIG_FMAN_ARM=y
+CONFIG_FSL_SDK_DPAA_ETH=y
+CONFIG_INET_ESP=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+# vfio
+CONFIG_VFIO=y
+CONFIG_VFIO_PCI=y
+CONFIG_VFIO_FSL_MC=y
+# CPU Frequency scaling
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_QORIQ_CPUFREQ=y
+#ifc
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSL_IFC=y
+#spi
+CONFIG_SPI_FSL_DSPI=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SST25L=y
+#RTC
+CONFIG_RTC_DRV_DS3232=y
+#CryptoAPI
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# ls1046a
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_RTC_DRV_PCF2127=y
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_HWMON=y
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_INA2XX=y
+CONFIG_EEPROM_AT24=y
+# lpuart
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+# ftm
+CONFIG_FTM_ALARM=y
+# qDMA
+CONFIG_FSL_QDMA=y
+CONFIG_DMATEST=y
+#NVMe
+CONFIG_BLK_DEV_NVME=y

24
target/linux/layerscape/patches-4.4/0238-arm64-disable-CONFIG_EEPROM_AT24-for-freescale.confi.patch
View File

@ -1,24 +0,0 @@
From fbc31a61b7bcfbc9ae1a8acda547de891f4b8ee4 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Mon, 31 Oct 2016 17:50:03 +0800
Subject: [PATCH 238/238] arm64: disable CONFIG_EEPROM_AT24 for
freescale.config
Disable CONFIG_EEPROM_AT24 in freescale.config. Otherwise, i2cdump
for EEPROM will get resource busy issue.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
arch/arm64/configs/freescale.config | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/configs/freescale.config
+++ b/arch/arm64/configs/freescale.config
@@ -121,7 +121,6 @@ CONFIG_IMX2_WDT=y
CONFIG_HWMON=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_INA2XX=y
-CONFIG_EEPROM_AT24=y
# lpuart
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y

68
target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch
View File

@ -1,68 +0,0 @@
From 1f58043afef0dca3d12dc23ac3a35d7074412939 Mon Sep 17 00:00:00 2001
From: Minghuan Lian <Minghuan.Lian@nxp.com>
Date: Tue, 2 Feb 2016 16:30:07 +0800
Subject: [PATCH 01/13] ARM: dts: ls1021a: add PCIe dts node
Cherry-pick upstream patch.
LS1021a contains two PCIe controllers. The patch adds their node to
dts file.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -539,5 +539,49 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
};
+
+ pcie@3400000 {
+ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ fsl,pcie-scfg = <&scfg 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,pcie-scfg = <&scfg 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};

56
target/linux/layerscape/patches-4.4/0240-ARM-dts-ls1021a-add-SCFG-MSI-dts-node.patch
View File

@ -1,56 +0,0 @@
From b57dcab78fdc76a6c56c2df71518fb022429e244 Mon Sep 17 00:00:00 2001
From: Minghuan Lian <Minghuan.Lian@nxp.com>
Date: Wed, 6 Apr 2016 19:02:07 +0800
Subject: [PATCH 02/13] ARM: dts: ls1021a: add SCFG MSI dts node
Cherry-pick upstream patch.
Add SCFG MSI dts node and add msi-parent property to PCIe dts node
that points to the corresponding MSI node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -119,6 +119,20 @@
};
+ msi1: msi-controller@1570e00 {
+ compatible = "fsl,1s1021a-msi";
+ reg = <0x0 0x1570e00 0x0 0x8>;
+ msi-controller;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ msi2: msi-controller@1570e08 {
+ compatible = "fsl,1s1021a-msi";
+ reg = <0x0 0x1570e08 0x0 0x8>;
+ msi-controller;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
@@ -554,6 +568,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -576,6 +591,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,

53
target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch
View File

@ -1,53 +0,0 @@
From 066320dd0643e66bc5afe0d0984e77b2e938a6f4 Mon Sep 17 00:00:00 2001
From: Minghuan Lian <Minghuan.Lian@nxp.com>
Date: Wed, 23 Mar 2016 19:08:19 +0800
Subject: [PATCH 03/13] dt/bindings: Add bindings for Layerscape SCFG MSI
Cherry-pick upstream patch.
Some Layerscape SoCs use a simple MSI controller implementation.
It contains only two SCFG register to trigger and describe a
group 32 MSI interrupts. The patch adds bindings to describe
the controller.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -0,0 +1,30 @@
+* Freescale Layerscape SCFG PCIe MSI controller
+
+Required properties:
+
+- compatible: should be "fsl,<soc-name>-msi" to identify
+ Layerscape PCIe MSI controller block such as:
+ "fsl,1s1021a-msi"
+ "fsl,1s1043a-msi"
+- msi-controller: indicates that this is a PCIe MSI controller node
+- reg: physical base address of the controller and length of memory mapped.
+- interrupts: an interrupt to the parent interrupt controller.
+
+Optional properties:
+- interrupt-parent: the phandle to the parent interrupt controller.
+
+This interrupt controller hardware is a second level interrupt controller that
+is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
+platforms. If interrupt-parent is not provided, the default parent interrupt
+controller will be used.
+Each PCIe node needs to have property msi-parent that points to
+MSI controller node
+
+Examples:
+
+ msi1: msi-controller@1571000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1571000 0x0 0x8>,
+ msi-controller;
+ interrupts = <0 116 0x4>;
+ };

31
target/linux/layerscape/patches-4.4/1074-mtd-nand-spi-nor-assign-MTD-of_node.patch
View File

@ -1,31 +0,0 @@
From f560fdb9d71aaf3adc54341a1650577c78495df9 Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Fri, 30 Oct 2015 20:33:22 -0700
Subject: [PATCH 074/113] mtd: {nand,spi-nor}: assign MTD of_node
We should pass along our flash DT node to the MTD layer, so it can set
up ofpart for us.
cherry-pick{
remove the code:
drivers/mtd/nand/nand_base.c | 3 +
commit:3e63b26bdd4069c3df2cd7ce7217a21d06801b41
}
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
---
drivers/mtd/spi-nor/spi-nor.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1228,6 +1228,7 @@ int spi_nor_scan(struct spi_nor *nor, co
mtd->flags |= MTD_NO_ERASE;
mtd->dev.parent = dev;
+ mtd_set_of_node(mtd, np);
nor->page_size = info->page_size;
mtd->writebufsize = nor->page_size;

80
target/linux/layerscape/patches-4.4/1075-mtd-spi-nor-convert-to-spi_nor_-get-set-_flash_node.patch
View File

@ -1,80 +0,0 @@
From f906ec330da9aa83de5382653436be36273c63d3 Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Fri, 30 Oct 2015 20:33:24 -0700
Subject: [PATCH 075/113] mtd: spi-nor: convert to spi_nor_{get,
set}_flash_node()
Used semantic patch with 'make coccicheck MODE=patch COCCI=script.cocci':
---8<----
virtual patch
@@
struct spi_nor b;
struct spi_nor *c;
expression d;
@@
(
-(b).flash_node = (d)
+spi_nor_set_flash_node(&b, d)
|
-(c)->flash_node = (d)
+spi_nor_set_flash_node(c, d)
)
---8<----
And a manual conversion for the one use of spi_nor_get_flash_node().
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
drivers/mtd/devices/m25p80.c | 2 +-
drivers/mtd/spi-nor/fsl-quadspi.c | 2 +-
drivers/mtd/spi-nor/nxp-spifi.c | 2 +-
drivers/mtd/spi-nor/spi-nor.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -221,7 +221,7 @@ static int m25p_probe(struct spi_device
nor->read_reg = m25p80_read_reg;
nor->dev = &spi->dev;
- nor->flash_node = spi->dev.of_node;
+ spi_nor_set_flash_node(nor, spi->dev.of_node);
nor->priv = flash;
spi_set_drvdata(spi, flash);
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -1013,7 +1013,7 @@ static int fsl_qspi_probe(struct platfor
mtd = &nor->mtd;
nor->dev = dev;
- nor->flash_node = np;
+ spi_nor_set_flash_node(nor, np);
nor->priv = q;
/* fill the hooks */
--- a/drivers/mtd/spi-nor/nxp-spifi.c
+++ b/drivers/mtd/spi-nor/nxp-spifi.c
@@ -330,7 +330,7 @@ static int nxp_spifi_setup_flash(struct
writel(ctrl, spifi->io_base + SPIFI_CTRL);
spifi->nor.dev = spifi->dev;
- spifi->nor.flash_node = np;
+ spi_nor_set_flash_node(&spifi->nor, np);
spifi->nor.priv = spifi;
spifi->nor.read = nxp_spifi_read;
spifi->nor.write = nxp_spifi_write;
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1120,7 +1120,7 @@ int spi_nor_scan(struct spi_nor *nor, co
const struct flash_info *info = NULL;
struct device *dev = nor->dev;
struct mtd_info *mtd = &nor->mtd;
- struct device_node *np = nor->flash_node;
+ struct device_node *np = spi_nor_get_flash_node(nor);
int ret;
int i;

83
target/linux/layerscape/patches-4.4/1076-mtd-spi-nor-drop-unnecessary-partition-parser-data.patch
View File

@ -1,83 +0,0 @@
From e36da6d0a0841ea3a75d5189057bd020d737e71a Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Fri, 30 Oct 2015 20:33:26 -0700
Subject: [PATCH 076/113] mtd: spi-nor: drop unnecessary partition parser data
Now that the SPI-NOR/MTD framework pass the 'flash_node' through to the
partition parsing code, we don't have to do it ourselves.
Also convert to mtd_device_register(), since we don't need the 2nd and
3rd parameters anymore.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
drivers/mtd/devices/m25p80.c | 8 ++------
drivers/mtd/spi-nor/fsl-quadspi.c | 4 +---
drivers/mtd/spi-nor/nxp-spifi.c | 4 +---
3 files changed, 4 insertions(+), 12 deletions(-)
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -197,7 +197,6 @@ static int m25p80_erase(struct spi_nor *
*/
static int m25p_probe(struct spi_device *spi)
{
- struct mtd_part_parser_data ppdata;
struct flash_platform_data *data;
struct m25p *flash;
struct spi_nor *nor;
@@ -249,11 +248,8 @@ static int m25p_probe(struct spi_device
if (ret)
return ret;
- ppdata.of_node = spi->dev.of_node;
-
- return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
- data ? data->parts : NULL,
- data ? data->nr_parts : 0);
+ return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
+ data ? data->nr_parts : 0);
}
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -927,7 +927,6 @@ static void fsl_qspi_unprep(struct spi_n
static int fsl_qspi_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
- struct mtd_part_parser_data ppdata;
struct device *dev = &pdev->dev;
struct fsl_qspi *q;
struct resource *res;
@@ -1038,8 +1037,7 @@ static int fsl_qspi_probe(struct platfor
if (ret)
goto mutex_failed;
- ppdata.of_node = np;
- ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
+ ret = mtd_device_register(mtd, NULL, 0);
if (ret)
goto mutex_failed;
--- a/drivers/mtd/spi-nor/nxp-spifi.c
+++ b/drivers/mtd/spi-nor/nxp-spifi.c
@@ -271,7 +271,6 @@ static void nxp_spifi_dummy_id_read(stru
static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
struct device_node *np)
{
- struct mtd_part_parser_data ppdata;
enum read_mode flash_read;
u32 ctrl, property;
u16 mode = 0;
@@ -361,8 +360,7 @@ static int nxp_spifi_setup_flash(struct
return ret;
}
- ppdata.of_node = np;
- ret = mtd_device_parse_register(&spifi->nor.mtd, NULL, &ppdata, NULL, 0);
+ ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
if (ret) {
dev_err(spifi->dev, "mtd device parse failed\n");
return ret;

62
target/linux/layerscape/patches-4.4/1077-mtd-add-get-set-of_node-flash_node-helpers.patch
View File

@ -1,62 +0,0 @@
From a2f87e7df641b482e217f5b0efbaf41f6b8a0cf6 Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Fri, 30 Oct 2015 20:33:20 -0700
Subject: [PATCH 077/113] mtd: add get/set of_node/flash_node helpers
We are going to begin using the mtd->dev.of_node field for MTD device
nodes, so let's add helpers for it. Also, we'll be making some
conversions on spi_nor (and nand_chip eventually) too, so get that ready
with their own helpers.
commit:28b8b26b308e656edfa9467867d5f79212da2ec3
delete the include/linux/mtd/nand.h
just upgrade the code about spi.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
---
include/linux/mtd/mtd.h | 11 +++++++++++
include/linux/mtd/spi-nor.h | 11 +++++++++++
2 files changed, 22 insertions(+)
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -258,6 +258,17 @@ struct mtd_info {
int usecount;
};
+static inline void mtd_set_of_node(struct mtd_info *mtd,
+ struct device_node *np)
+{
+ mtd->dev.of_node = np;
+}
+
+static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd)
+{
+ return mtd->dev.of_node;
+}
+
int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
void **virt, resource_size_t *phys);
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -184,6 +184,17 @@ struct spi_nor {
void *priv;
};
+static inline void spi_nor_set_flash_node(struct spi_nor *nor,
+ struct device_node *np)
+{
+ nor->flash_node = np;
+}
+
+static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
+{
+ return nor->flash_node;
+}
+
/**
* spi_nor_scan() - scan the SPI NOR
* @nor: the spi_nor structure

57
target/linux/layerscape/patches-4.4/1078-mtd-spi-nor-drop-flash_node-field.patch
View File

@ -1,57 +0,0 @@
From df36b4601bc9f84684249a26eb39b818d6785fb8 Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Fri, 30 Oct 2015 20:33:27 -0700
Subject: [PATCH 078/113] mtd: spi-nor: drop flash_node field
We can just alias to the MTD of_node.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
drivers/mtd/spi-nor/spi-nor.c | 1 -
include/linux/mtd/spi-nor.h | 6 ++----
2 files changed, 2 insertions(+), 5 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1228,7 +1228,6 @@ int spi_nor_scan(struct spi_nor *nor, co
mtd->flags |= MTD_NO_ERASE;
mtd->dev.parent = dev;
- mtd_set_of_node(mtd, np);
nor->page_size = info->page_size;
mtd->writebufsize = nor->page_size;
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -123,7 +123,6 @@ enum spi_nor_option_flags {
* @mtd: point to a mtd_info structure
* @lock: the lock for the read/write/erase/lock/unlock operations
* @dev: point to a spi device, or a spi nor controller device.
- * @flash_node: point to a device node describing this flash instance.
* @page_size: the page size of the SPI NOR
* @addr_width: number of address bytes
* @erase_opcode: the opcode for erasing a sector
@@ -154,7 +153,6 @@ struct spi_nor {
struct mtd_info mtd;
struct mutex lock;
struct device *dev;
- struct device_node *flash_node;
u32 page_size;
u8 addr_width;
u8 erase_opcode;
@@ -187,12 +185,12 @@ struct spi_nor {
static inline void spi_nor_set_flash_node(struct spi_nor *nor,
struct device_node *np)
{
- nor->flash_node = np;
+ mtd_set_of_node(&nor->mtd, np);
}
static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
{
- return nor->flash_node;
+ return mtd_get_of_node(&nor->mtd);
}
/**

27
target/linux/layerscape/patches-4.4/1079-mtd-spi-nor-remove-unnecessary-leading-space-from-db.patch
View File

@ -1,27 +0,0 @@
From 3ea419cf269832f5743d9b5ad75ece5178b02b09 Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Fri, 30 Oct 2015 12:56:22 -0700
Subject: [PATCH 079/113] mtd: spi-nor: remove unnecessary leading space from
dbg print
As Cyrille noted [1], this line is wrong.
[1] http://lists.infradead.org/pipermail/linux-mtd/2015-September/061725.html
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -862,7 +862,7 @@ static const struct flash_info *spi_nor_
tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
if (tmp < 0) {
- dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
+ dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
return ERR_PTR(tmp);
}

50
target/linux/layerscape/patches-4.4/1080-mtd-fsl-quadspi-possible-NULL-dereference.patch
View File

@ -1,50 +0,0 @@
From bd02decd1ad7cc883ce388e769a34a3c402b90c4 Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Mon, 16 Nov 2015 10:45:30 -0800
Subject: [PATCH 080/113] mtd: fsl-quadspi: possible NULL dereference
It is theoretically possible to probe this driver without a matching
device tree, so let's guard against this.
Also, use the of_device_get_match_data() helper to make this a bit
simpler.
Coverity complained about this one.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Han xu <han.xu@freescale.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -269,7 +269,7 @@ struct fsl_qspi {
struct clk *clk, *clk_en;
struct device *dev;
struct completion c;
- struct fsl_qspi_devtype_data *devtype_data;
+ const struct fsl_qspi_devtype_data *devtype_data;
u32 nor_size;
u32 nor_num;
u32 clk_rate;
@@ -933,8 +933,6 @@ static int fsl_qspi_probe(struct platfor
struct spi_nor *nor;
struct mtd_info *mtd;
int ret, i = 0;
- const struct of_device_id *of_id =
- of_match_device(fsl_qspi_dt_ids, &pdev->dev);
q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
if (!q)
@@ -945,7 +943,9 @@ static int fsl_qspi_probe(struct platfor
return -ENODEV;
q->dev = dev;
- q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
+ q->devtype_data = of_device_get_match_data(dev);
+ if (!q->devtype_data)
+ return -ENODEV;
platform_set_drvdata(pdev, q);
/* find the resources */

105
target/linux/layerscape/patches-4.4/1081-mtd-spi-nor-provide-default-erase_sector-implementat.patch
View File

@ -1,105 +0,0 @@
From 56bd0e13d8bc3b4486251b10ac9d2ba7434c21ee Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Tue, 10 Nov 2015 12:15:27 -0800
Subject: [PATCH 081/113] mtd: spi-nor: provide default erase_sector
implementation
Some spi-nor drivers perform sector erase by duplicating their
write_reg() command. Let's not require that the driver fill this out,
and provide a default instead.
Tested on m25p80.c and Medatek's MT8173 SPI NOR flash driver.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
drivers/mtd/spi-nor/spi-nor.c | 37 +++++++++++++++++++++++++++++++++----
include/linux/mtd/spi-nor.h | 3 ++-
2 files changed, 35 insertions(+), 5 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -38,6 +38,7 @@
#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
#define SPI_NOR_MAX_ID_LEN 6
+#define SPI_NOR_MAX_ADDR_WIDTH 4
struct flash_info {
char *name;
@@ -314,6 +315,29 @@ static void spi_nor_unlock_and_unprep(st
}
/*
+ * Initiate the erasure of a single sector
+ */
+static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
+{
+ u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
+ int i;
+
+ if (nor->erase)
+ return nor->erase(nor, addr);
+
+ /*
+ * Default implementation, if driver doesn't have a specialized HW
+ * control
+ */
+ for (i = nor->addr_width - 1; i >= 0; i--) {
+ buf[i] = addr & 0xff;
+ addr >>= 8;
+ }
+
+ return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
+}
+
+/*
* Erase an address range on the nor chip. The address range may extend
* one or more erase sectors. Return an error is there is a problem erasing.
*/
@@ -372,10 +396,9 @@ static int spi_nor_erase(struct mtd_info
while (len) {
write_enable(nor);
- if (nor->erase(nor, addr)) {
- ret = -EIO;
+ ret = spi_nor_erase_sector(nor, addr);
+ if (ret)
goto erase_err;
- }
addr += mtd->erasesize;
len -= mtd->erasesize;
@@ -1107,7 +1130,7 @@ static int set_quad_mode(struct spi_nor
static int spi_nor_check(struct spi_nor *nor)
{
if (!nor->dev || !nor->read || !nor->write ||
- !nor->read_reg || !nor->write_reg || !nor->erase) {
+ !nor->read_reg || !nor->write_reg) {
pr_err("spi-nor: please fill all the necessary fields!\n");
return -EINVAL;
}
@@ -1310,6 +1333,12 @@ int spi_nor_scan(struct spi_nor *nor, co
nor->addr_width = 3;
}
+ if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
+ dev_err(dev, "address width is too large: %u\n",
+ nor->addr_width);
+ return -EINVAL;
+ }
+
nor->read_dummy = spi_nor_read_dummy_cycles(nor);
dev_info(dev, "%s (%lld Kbytes)\n", info->name,
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -142,7 +142,8 @@ enum spi_nor_option_flags {
* @read: [DRIVER-SPECIFIC] read data from the SPI NOR
* @write: [DRIVER-SPECIFIC] write data to the SPI NOR
* @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
- * at the offset @offs
+ * at the offset @offs; if not provided by the driver,
+ * spi-nor will send the erase opcode via write_reg()
* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is

31
target/linux/layerscape/patches-4.4/1083-mtd-spi-nor-Fix-error-message-with-unrecognized-JEDE.patch
View File

@ -1,31 +0,0 @@
From 30e609daed95664824e95344e85c7eaedd1bfcf3 Mon Sep 17 00:00:00 2001
From: Ricardo Ribalda <ricardo.ribalda@gmail.com>
Date: Mon, 30 Nov 2015 20:41:17 +0100
Subject: [PATCH 083/113] mtd: spi-nor: Fix error message with unrecognized
JEDEC
The error message was:
m25p80 spi32766.0: unrecognized JEDEC id bytes: 00, 0, 0
The new error message:
m25p80 spi32766.0: unrecognized JEDEC id bytes: 00, 00, 00
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -896,7 +896,7 @@ static const struct flash_info *spi_nor_
return &spi_nor_ids[tmp];
}
}
- dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
+ dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
id[0], id[1], id[2]);
return ERR_PTR(-ENODEV);
}

39
target/linux/layerscape/patches-4.4/1084-mtd-spi-nor-fix-error-handling-in-spi_nor_erase.patch
View File

@ -1,39 +0,0 @@
From 9e473594776da97245049019f1d1e9608ff1214a Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Tue, 17 Nov 2015 20:18:54 +0100
Subject: [PATCH 084/113] mtd: spi-nor: fix error handling in spi_nor_erase
The documenting comment of mtd_erase in mtdcore.c states:
Device drivers are supposed to call instr->callback() whenever
the operation completes, even if it completes with a failure.
Currently the callback isn't called in case of failure. Fix this.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
drivers/mtd/spi-nor/spi-nor.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -411,17 +411,13 @@ static int spi_nor_erase(struct mtd_info
write_disable(nor);
+erase_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
- instr->state = MTD_ERASE_DONE;
+ instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
mtd_erase_callback(instr);
return ret;
-
-erase_err:
- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
- instr->state = MTD_ERASE_FAILED;
- return ret;
}
static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,

58
target/linux/layerscape/patches-4.4/1085-mtd-spi-nor-Check-the-return-value-from-read_sr.patch
View File

@ -1,58 +0,0 @@
From d05c68e35f42a46b352d2a4bdaef9954c946e20a Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Fri, 20 Nov 2015 16:26:11 -0200
Subject: [PATCH 085/113] mtd: spi-nor: Check the return value from read_sr()
[context adjustment]
We should better check the return value from read_sr() and
propagate it in the case of error.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
---
drivers/mtd/spi-nor/spi-nor.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -479,11 +479,13 @@ static int stm_is_locked_sr(struct spi_n
static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
- u8 status_old, status_new;
+ int status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
status_old = read_sr(nor);
+ if (status_old < 0)
+ return status_old;
/* SPI NOR always locks to the end */
if (ofs + len != mtd->size) {
@@ -529,11 +531,13 @@ static int stm_lock(struct spi_nor *nor,
static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
- uint8_t status_old, status_new;
+ int status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
status_old = read_sr(nor);
+ if (status_old < 0)
+ return status_old;
/* Cannot unlock; would unlock larger region than requested */
if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize,
@@ -1038,6 +1042,8 @@ static int macronix_quad_enable(struct s
int ret, val;
val = read_sr(nor);
+ if (val < 0)
+ return val;
write_enable(nor);
write_sr(nor, val | SR_QUAD_EN_MX);

66
target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch
View File

@ -1,66 +0,0 @@
From 3a06c61b48fbc23046928275e37a693e1055ae74 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ezequiel=20Garc=C3=ADa?= <ezequiel@vanguardiasur.com.ar>
Date: Mon, 28 Dec 2015 17:54:51 -0300
Subject: [PATCH 086/113] mtd: spi-nor: wait until lock/unlock operations are
ready
On Micron and Numonyx devices, the status register write command
(WRSR), raises a work-in-progress bit (WIP) on the status register.
The datasheets for these devices specify that while the status
register write is in progress, the status register WIP bit can still
be read to check the end of the operation.
This commit adds a wait_till_ready call on lock/unlock operations,
which is required for Micron and Numonyx but should be harmless for
others. This is needed to prevent applications from issuing erase or
program operations before the unlock operation is completed.
Reported-by: Stas Sergeev <stsp@list.ru>
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
drivers/mtd/spi-nor/spi-nor.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -482,6 +482,7 @@ static int stm_lock(struct spi_nor *nor,
int status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
+ int ret;
status_old = read_sr(nor);
if (status_old < 0)
@@ -520,7 +521,10 @@ static int stm_lock(struct spi_nor *nor,
return -EINVAL;
write_enable(nor);
- return write_sr(nor, status_new);
+ ret = write_sr(nor, status_new);
+ if (ret)
+ return ret;
+ return spi_nor_wait_till_ready(nor);
}
/*
@@ -534,6 +538,7 @@ static int stm_unlock(struct spi_nor *no
int status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
+ int ret;
status_old = read_sr(nor);
if (status_old < 0)
@@ -570,7 +575,10 @@ static int stm_unlock(struct spi_nor *no
return -EINVAL;
write_enable(nor);
- return write_sr(nor, status_new);
+ ret = write_sr(nor, status_new);
+ if (ret)
+ return ret;
+ return spi_nor_wait_till_ready(nor);
}
/*

400
target/linux/layerscape/patches-4.4/1087-mtd-spi-nor-fsl-quadspi-add-big-endian-support.patch
View File

@ -1,400 +0,0 @@
From c58b398221d88ac0db29c3bb7522a4f48dfa102c Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@freescale.com>
Date: Tue, 17 Nov 2015 16:13:47 +0800
Subject: [PATCH 087/113] mtd: spi-nor: fsl-quadspi: add big-endian support
Add R/W functions for big- or little-endian registers:
The qSPI controller's endian is independent of the CPU core's endian.
So far, the qSPI have two versions for big-endian and little-endian.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Acked-by: Han xu <han.xu@freescale.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++++++++++++++++++++++--------------
1 file changed, 97 insertions(+), 60 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -275,6 +275,7 @@ struct fsl_qspi {
u32 clk_rate;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
+ bool big_endian;
struct mutex lock;
struct pm_qos_request pm_qos_req;
};
@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode
}
/*
+ * R/W functions for big- or little-endian registers:
+ * The qSPI controller's endian is independent of the CPU core's endian.
+ * So far, although the CPU core is little-endian but the qSPI have two
+ * versions for big-endian and little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+ if (q->big_endian)
+ iowrite32be(val, addr);
+ else
+ iowrite32(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+ if (q->big_endian)
+ return ioread32be(addr);
+ else
+ return ioread32(addr);
+}
+
+/*
* An IC bug makes us to re-arrange the 32-bit data.
* The following chips, such as IMX6SLX, have fixed this bug.
*/
@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(s
static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
{
- writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
- writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
}
static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
{
- writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
- writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+ qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
}
static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(
u32 reg;
/* clear interrupt */
- reg = readl(q->iobase + QUADSPI_FR);
- writel(reg, q->iobase + QUADSPI_FR);
+ reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+ qspi_writel(q, reg, q->iobase + QUADSPI_FR);
if (reg & QUADSPI_FR_TFF_MASK)
complete(&q->c);
@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl
/* Clear all the LUT table */
for (i = 0; i < QUADSPI_LUT_NUM; i++)
- writel(0, base + QUADSPI_LUT_BASE + i * 4);
+ qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl
dummy = 8;
}
- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
- writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+ qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
/* Write enable */
lut_base = SEQID_WREN * 4;
- writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+ base + QUADSPI_LUT(lut_base));
/* Page Program */
lut_base = SEQID_PP * 4;
@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl
addrlen = ADDR32BIT;
}
- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
- writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+ base + QUADSPI_LUT(lut_base + 1));
/* Read Status */
lut_base = SEQID_RDSR * 4;
- writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
+ LUT1(FSL_READ, PAD1, 0x1),
base + QUADSPI_LUT(lut_base));
/* Erase a sector */
@@ -400,40 +426,46 @@ static void fsl_qspi_init_lut(struct fsl
cmd = q->nor[0].erase_opcode;
addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
/* Erase the whole chip */
lut_base = SEQID_CHIP_ERASE * 4;
- writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
base + QUADSPI_LUT(lut_base));
/* READ ID */
lut_base = SEQID_RDID * 4;
- writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8),
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
+ LUT1(FSL_READ, PAD1, 0x8),
base + QUADSPI_LUT(lut_base));
/* Write Register */
lut_base = SEQID_WRSR * 4;
- writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2),
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
+ LUT1(FSL_WRITE, PAD1, 0x2),
base + QUADSPI_LUT(lut_base));
/* Read Configuration Register */
lut_base = SEQID_RDCR * 4;
- writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1),
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
+ LUT1(FSL_READ, PAD1, 0x1),
base + QUADSPI_LUT(lut_base));
/* Write disable */
lut_base = SEQID_WRDI * 4;
- writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
+ base + QUADSPI_LUT(lut_base));
/* Enter 4 Byte Mode (Micron) */
lut_base = SEQID_EN4B * 4;
- writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
+ base + QUADSPI_LUT(lut_base));
/* Enter 4 Byte Mode (Spansion) */
lut_base = SEQID_BRWR * 4;
- writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
+ base + QUADSPI_LUT(lut_base));
fsl_qspi_lock_lut(q);
}
@@ -488,15 +520,16 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
q->chip_base_addr, addr, len, cmd);
/* save the reg */
- reg = readl(base + QUADSPI_MCR);
+ reg = qspi_readl(q, base + QUADSPI_MCR);
- writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
- writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+ qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
+ base + QUADSPI_SFAR);
+ qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
base + QUADSPI_RBCT);
- writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
+ qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
do {
- reg2 = readl(base + QUADSPI_SR);
+ reg2 = qspi_readl(q, base + QUADSPI_SR);
if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
udelay(1);
dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
@@ -507,21 +540,22 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
/* trigger the LUT now */
seqid = fsl_qspi_get_seqid(q, cmd);
- writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
+ qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
+ base + QUADSPI_IPCR);
/* Wait for the interrupt. */
if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
dev_err(q->dev,
"cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
- cmd, addr, readl(base + QUADSPI_FR),
- readl(base + QUADSPI_SR));
+ cmd, addr, qspi_readl(q, base + QUADSPI_FR),
+ qspi_readl(q, base + QUADSPI_SR));
err = -ETIMEDOUT;
} else {
err = 0;
}
/* restore the MCR */
- writel(reg, base + QUADSPI_MCR);
+ qspi_writel(q, reg, base + QUADSPI_MCR);
return err;
}
@@ -533,7 +567,7 @@ static void fsl_qspi_read_data(struct fs
int i = 0;
while (len > 0) {
- tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
+ tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
tmp = fsl_qspi_endian_xchg(q, tmp);
dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
q->chip_base_addr, tmp);
@@ -561,9 +595,9 @@ static inline void fsl_qspi_invalid(stru
{
u32 reg;
- reg = readl(q->iobase + QUADSPI_MCR);
+ reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
- writel(reg, q->iobase + QUADSPI_MCR);
+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
/*
* The minimum delay : 1 AHB + 2 SFCK clocks.
@@ -572,7 +606,7 @@ static inline void fsl_qspi_invalid(stru
udelay(1);
reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
- writel(reg, q->iobase + QUADSPI_MCR);
+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
}
static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
@@ -586,20 +620,20 @@ static int fsl_qspi_nor_write(struct fsl
q->chip_base_addr, to, count);
/* clear the TX FIFO. */
- tmp = readl(q->iobase + QUADSPI_MCR);
- writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
+ tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
+ qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
/* fill the TX data to the FIFO */
for (j = 0, i = ((count + 3) / 4); j < i; j++) {
tmp = fsl_qspi_endian_xchg(q, *txbuf);
- writel(tmp, q->iobase + QUADSPI_TBDR);
+ qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
txbuf++;
}
/* fill the TXFIFO upto 16 bytes for i.MX7d */
if (needs_fill_txfifo(q))
for (; i < 4; i++)
- writel(tmp, q->iobase + QUADSPI_TBDR);
+ qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
/* Trigger it */
ret = fsl_qspi_runcmd(q, opcode, to, count);
@@ -615,10 +649,10 @@ static void fsl_qspi_set_map_addr(struct
int nor_size = q->nor_size;
void __iomem *base = q->iobase;
- writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
- writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
- writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
- writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
+ qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
+ qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
+ qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
+ qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
}
/*
@@ -640,24 +674,26 @@ static void fsl_qspi_init_abh_read(struc
int seqid;
/* AHB configuration for access buffer 0/1/2 .*/
- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
/*
* Set ADATSZ with the maximum AHB buffer size to improve the
* read performance.
*/
- writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
- << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+ ((q->devtype_data->ahb_buf_size / 8)
+ << QUADSPI_BUF3CR_ADATSZ_SHIFT),
+ base + QUADSPI_BUF3CR);
/* We only use the buffer3 */
- writel(0, base + QUADSPI_BUF0IND);
- writel(0, base + QUADSPI_BUF1IND);
- writel(0, base + QUADSPI_BUF2IND);
+ qspi_writel(q, 0, base + QUADSPI_BUF0IND);
+ qspi_writel(q, 0, base + QUADSPI_BUF1IND);
+ qspi_writel(q, 0, base + QUADSPI_BUF2IND);
/* Set the default lut sequence for AHB Read. */
seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
- writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
+ qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
q->iobase + QUADSPI_BFGENCR);
}
@@ -713,7 +749,7 @@ static int fsl_qspi_nor_setup(struct fsl
return ret;
/* Reset the module */
- writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
+ qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
base + QUADSPI_MCR);
udelay(1);
@@ -721,24 +757,24 @@ static int fsl_qspi_nor_setup(struct fsl
fsl_qspi_init_lut(q);
/* Disable the module */
- writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
base + QUADSPI_MCR);
- reg = readl(base + QUADSPI_SMPR);
- writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
+ reg = qspi_readl(q, base + QUADSPI_SMPR);
+ qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
| QUADSPI_SMPR_FSPHS_MASK
| QUADSPI_SMPR_HSENA_MASK
| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
/* Enable the module */
- writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
+ qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
base + QUADSPI_MCR);
/* clear all interrupt status */
- writel(0xffffffff, q->iobase + QUADSPI_FR);
+ qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
/* enable the interrupt */
- writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
+ qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
return 0;
}
@@ -954,6 +990,7 @@ static int fsl_qspi_probe(struct platfor
if (IS_ERR(q->iobase))
return PTR_ERR(q->iobase);
+ q->big_endian = of_property_read_bool(np, "big-endian");
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"QuadSPI-memory");
if (!devm_request_mem_region(dev, res->start, resource_size(res),
@@ -1101,8 +1138,8 @@ static int fsl_qspi_remove(struct platfo
}
/* disable the hardware */
- writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
- writel(0x0, q->iobase + QUADSPI_RSER);
+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
+ qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
mutex_destroy(&q->lock);

63
target/linux/layerscape/patches-4.4/1088-mtd-spi-nor-fsl-quadspi-add-support-for-ls1021a.patch
View File

@ -1,63 +0,0 @@
From da44c1517526822e73642fc71b034de8fc7d2b43 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@freescale.com>
Date: Tue, 17 Nov 2015 16:44:45 +0800
Subject: [PATCH 088/113] mtd: spi-nor: fsl-quadspi: add support for ls1021a
[context adjustment]
LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Acked-by: Han xu <han.xu@freescale.com>
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
---
drivers/mtd/spi-nor/Kconfig | 2 +-
drivers/mtd/spi-nor/fsl-quadspi.c | 10 ++++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -23,7 +23,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
- depends on ARCH_MXC || COMPILE_TEST
+ depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
depends on HAS_IOMEM
help
This enables support for the Quad SPI controller in master mode.
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -213,6 +213,7 @@ enum fsl_qspi_devtype {
FSL_QUADSPI_IMX6SX,
FSL_QUADSPI_IMX7D,
FSL_QUADSPI_IMX6UL,
+ FSL_QUADSPI_LS1021A,
};
struct fsl_qspi_devtype_data {
@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6
| QUADSPI_QUIRK_4X_INT_CLK,
};
+static struct fsl_qspi_devtype_data ls1021a_data = {
+ .devtype = FSL_QUADSPI_LS1021A,
+ .rxfifo = 128,
+ .txfifo = 64,
+ .ahb_buf_size = 1024,
+ .driver_data = 0,
+};
+
#define FSL_QSPI_MAX_CHIP 4
struct fsl_qspi {
struct spi_nor nor[FSL_QSPI_MAX_CHIP];
@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qsp
{ .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
+ { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);

28
target/linux/layerscape/patches-4.4/1089-mtd-spi-nor-fsl-quadspi-add-support-for-layerscape.patch
View File

@ -1,28 +0,0 @@
From 9c6153130081ef2c109e2a243a598f2bc0dc6413 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@freescale.com>
Date: Tue, 17 Nov 2015 17:06:47 +0800
Subject: [PATCH 089/113] mtd: spi-nor: fsl-quadspi: add support for
layerscape
[context adjustment]
LS1043a and LS2080A in the Layerscape family also support Freescale Quad
SPI, make Quad SPI selectable for these hardwares.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
---
drivers/mtd/spi-nor/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -23,7 +23,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
config SPI_FSL_QUADSPI
tristate "Freescale Quad SPI controller"
- depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
+ depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
depends on HAS_IOMEM
help
This enables support for the Quad SPI controller in master mode.

138
target/linux/layerscape/patches-4.4/1090-mtd-spi-nor-Add-SPI-NOR-layer-PM-support.patch
View File

@ -1,138 +0,0 @@
From 2c5a3db21926e9ebfd7a32e3c36a3256ed84903c Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
Date: Thu, 19 Nov 2015 20:25:24 +0800
Subject: [PATCH 090/113] mtd: spi-nor: Add SPI NOR layer PM support
[context adjustment]
Add the Power Management API in SPI NOR framework.
The Power Management system will turn off power supply to SPI flash
when system suspending, and then the SPI flash will be in the reset
state after system resuming. As a result, the status&configurations
of SPI flash driver will mismatch with its current hardware state.
So reinitialize SPI flash to make sure it is resumed to the correct
state.
And the SPI NOR layer just do common configuration depending on the
records in structure spi_nor.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
---
drivers/mtd/spi-nor/spi-nor.c | 74 ++++++++++++++++++++++++++++++++++-------
include/linux/mtd/spi-nor.h | 9 +++++
2 files changed, 71 insertions(+), 12 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1148,6 +1148,26 @@ static int spi_nor_check(struct spi_nor
return 0;
}
+/*
+ * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
+ * with the software protection bits set
+ */
+static int spi_nor_unprotect_on_powerup(struct spi_nor *nor)
+{
+ const struct flash_info *info = NULL;
+ int ret = 0;
+
+ info = spi_nor_read_id(nor);
+ if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
+ JEDEC_MFR(info) == SNOR_MFR_INTEL ||
+ JEDEC_MFR(info) == SNOR_MFR_SST) {
+ write_enable(nor);
+ ret = write_sr(nor, 0);
+ }
+
+ return ret;
+}
+
int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
{
const struct flash_info *info = NULL;
@@ -1195,19 +1215,9 @@ int spi_nor_scan(struct spi_nor *nor, co
mutex_init(&nor->lock);
- /*
- * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
- * with the software protection bits set
- */
-
- if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
- JEDEC_MFR(info) == SNOR_MFR_INTEL ||
- JEDEC_MFR(info) == SNOR_MFR_MACRONIX ||
- JEDEC_MFR(info) == SNOR_MFR_SST ||
- info->flags & SPI_NOR_HAS_LOCK) {
- write_enable(nor);
- write_sr(nor, 0);
- }
+ ret = spi_nor_unprotect_on_powerup(nor);
+ if (ret)
+ return ret;
if (!mtd->name)
mtd->name = dev_name(dev);
@@ -1374,6 +1384,45 @@ int spi_nor_scan(struct spi_nor *nor, co
}
EXPORT_SYMBOL_GPL(spi_nor_scan);
+static int spi_nor_hw_reinit(struct spi_nor *nor)
+{
+ const struct flash_info *info = NULL;
+ struct device *dev = nor->dev;
+ int ret;
+
+ info = spi_nor_read_id(nor);
+
+ ret = spi_nor_unprotect_on_powerup(nor);
+ if (ret)
+ return ret;
+
+ if (nor->flash_read == SPI_NOR_QUAD) {
+ ret = set_quad_mode(nor, info);
+ if (ret) {
+ dev_err(dev, "quad mode not supported\n");
+ return ret;
+ }
+ }
+
+ if (nor->addr_width == 4 &&
+ JEDEC_MFR(info) != SNOR_MFR_SPANSION)
+ set_4byte(nor, info, 1);
+
+ return 0;
+}
+
+int spi_nor_suspend(struct spi_nor *nor)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(spi_nor_suspend);
+
+int spi_nor_resume(struct spi_nor *nor)
+{
+ return spi_nor_hw_reinit(nor);
+}
+EXPORT_SYMBOL_GPL(spi_nor_resume);
+
static const struct flash_info *spi_nor_match_id(const char *name)
{
const struct flash_info *id = spi_nor_ids;
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -210,4 +210,13 @@ static inline struct device_node *spi_no
*/
int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode);
+/**
+ * spi_nor_suspend/resume() - the SPI NOR layer PM API
+ * @nor: the spi_nor structure
+ *
+ * Return: 0 for success, others for failure.
+ */
+int spi_nor_suspend(struct spi_nor *nor);
+int spi_nor_resume(struct spi_nor *nor);
+
#endif

82
target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch
View File

@ -1,82 +0,0 @@
From 0a8079b232e9188ba267e37e20f192bed6c2b29b Mon Sep 17 00:00:00 2001
From: Michal Suchanek <hramrach@gmail.com>
Date: Wed, 2 Dec 2015 10:38:19 +0000
Subject: [PATCH 091/113] mtd: spi-nor: change return value of read/write
Change the return value of spi-nor device read and write methods to
allow returning amount of data transferred and errors as
read(2)/write(2) does.
Signed-off-by: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
---
drivers/mtd/devices/m25p80.c | 5 +++--
drivers/mtd/spi-nor/fsl-quadspi.c | 5 +++--
include/linux/mtd/spi-nor.h | 4 ++--
3 files changed, 8 insertions(+), 6 deletions(-)
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -73,7 +73,7 @@ static int m25p80_write_reg(struct spi_n
return spi_write(spi, flash->command, len + 1);
}
-static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
+static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
struct m25p *flash = nor->priv;
@@ -101,6 +101,7 @@ static void m25p80_write(struct spi_nor
spi_sync(spi, &m);
*retlen += m.actual_length - cmd_sz;
+ return 0;
}
static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
@@ -119,7 +120,7 @@ static inline unsigned int m25p80_rx_nbi
* Read an address range from the nor chip. The address range
* may be any size provided it is within the physical boundaries.
*/
-static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
+static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
struct m25p *flash = nor->priv;
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -868,7 +868,7 @@ static int fsl_qspi_write_reg(struct spi
return ret;
}
-static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
+static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
size_t len, size_t *retlen, const u_char *buf)
{
struct fsl_qspi *q = nor->priv;
@@ -878,9 +878,10 @@ static void fsl_qspi_write(struct spi_no
/* invalid the data in the AHB buffer. */
fsl_qspi_invalid(q);
+ return 0;
}
-static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
+static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
size_t len, size_t *retlen, u_char *buf)
{
struct fsl_qspi *q = nor->priv;
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -170,9 +170,9 @@ struct spi_nor {
int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
- int (*read)(struct spi_nor *nor, loff_t from,
+ ssize_t (*read)(struct spi_nor *nor, loff_t from,
size_t len, size_t *retlen, u_char *read_buf);
- void (*write)(struct spi_nor *nor, loff_t to,
+ ssize_t (*write)(struct spi_nor *nor, loff_t to,
size_t len, size_t *retlen, const u_char *write_buf);
int (*erase)(struct spi_nor *nor, loff_t offs);

73
target/linux/layerscape/patches-4.4/1092-mtd-fsl-quadspi-return-amount-of-data-read-written-o.patch
View File

@ -1,73 +0,0 @@
From 99768b3062501b05810fb62545279da3a4371ca0 Mon Sep 17 00:00:00 2001
From: Michal Suchanek <hramrach@gmail.com>
Date: Wed, 2 Dec 2015 10:38:19 +0000
Subject: [PATCH 092/113] mtd: fsl-quadspi: return amount of data read/written
or error
Return amount of data read/written or error as read(2)/write(2) does.
Signed-off-by: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -618,7 +618,7 @@ static inline void fsl_qspi_invalid(stru
qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
}
-static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
+static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
u8 opcode, unsigned int to, u32 *txbuf,
unsigned count, size_t *retlen)
{
@@ -647,8 +647,11 @@ static int fsl_qspi_nor_write(struct fsl
/* Trigger it */
ret = fsl_qspi_runcmd(q, opcode, to, count);
- if (ret == 0 && retlen)
- *retlen += count;
+ if (ret == 0) {
+ if (retlen)
+ *retlen += count;
+ return count;
+ }
return ret;
}
@@ -860,6 +863,8 @@ static int fsl_qspi_write_reg(struct spi
} else if (len > 0) {
ret = fsl_qspi_nor_write(q, nor, opcode, 0,
(u32 *)buf, len, NULL);
+ if (ret > 0)
+ return 0;
} else {
dev_err(q->dev, "invalid cmd %d\n", opcode);
ret = -EINVAL;
@@ -873,12 +878,12 @@ static ssize_t fsl_qspi_write(struct spi
{
struct fsl_qspi *q = nor->priv;
- fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
+ ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
(u32 *)buf, len, retlen);
/* invalid the data in the AHB buffer. */
fsl_qspi_invalid(q);
- return 0;
+ return ret;
}
static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
@@ -924,8 +929,7 @@ static ssize_t fsl_qspi_read(struct spi_
memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
len);
- *retlen += len;
- return 0;
+ return len;
}
static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)

127
target/linux/layerscape/patches-4.4/1093-mtd-spi-nor-check-return-value-from-read-write.patch
View File

@ -1,127 +0,0 @@
From 8527843351169d999995d331bbdad75560ccafb2 Mon Sep 17 00:00:00 2001
From: Michal Suchanek <hramrach@gmail.com>
Date: Wed, 2 Dec 2015 10:38:20 +0000
Subject: [PATCH 093/113] mtd: spi-nor: check return value from read/write
SPI NOR hardware drivers now return useful value from their read/write
functions so check them.
Signed-off-by: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
---
drivers/mtd/spi-nor/spi-nor.c | 50 +++++++++++++++++++++++++++++------------
1 file changed, 36 insertions(+), 14 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -924,7 +924,10 @@ static int spi_nor_read(struct mtd_info
ret = nor->read(nor, from, len, retlen, buf);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
- return ret;
+ if (ret < 0)
+ return ret;
+
+ return 0;
}
static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
@@ -950,10 +953,14 @@ static int sst_write(struct mtd_info *mt
nor->program_opcode = SPINOR_OP_BP;
/* write one byte. */
- nor->write(nor, to, 1, retlen, buf);
+ ret = nor->write(nor, to, 1, retlen, buf);
+ if (ret < 0)
+ goto sst_write_err;
+ WARN(ret != 1, "While writing 1 byte written %i bytes\n",
+ (int)ret);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto time_out;
+ goto sst_write_err;
}
to += actual;
@@ -962,10 +969,14 @@ static int sst_write(struct mtd_info *mt
nor->program_opcode = SPINOR_OP_AAI_WP;
/* write two bytes. */
- nor->write(nor, to, 2, retlen, buf + actual);
+ ret = nor->write(nor, to, 2, retlen, buf + actual);
+ if (ret < 0)
+ goto sst_write_err;
+ WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
+ (int)ret);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto time_out;
+ goto sst_write_err;
to += 2;
nor->sst_write_second = true;
}
@@ -974,21 +985,24 @@ static int sst_write(struct mtd_info *mt
write_disable(nor);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto time_out;
+ goto sst_write_err;
/* Write out trailing byte if it exists. */
if (actual != len) {
write_enable(nor);
nor->program_opcode = SPINOR_OP_BP;
- nor->write(nor, to, 1, retlen, buf + actual);
-
+ ret = nor->write(nor, to, 1, retlen, buf + actual);
+ if (ret < 0)
+ goto sst_write_err;
+ WARN(ret != 1, "While writing 1 byte written %i bytes\n",
+ (int)ret);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto time_out;
+ goto sst_write_err;
write_disable(nor);
}
-time_out:
+sst_write_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
return ret;
}
@@ -1017,14 +1031,18 @@ static int spi_nor_write(struct mtd_info
/* do all the bytes fit onto one page? */
if (page_offset + len <= nor->page_size) {
- nor->write(nor, to, len, retlen, buf);
+ ret = nor->write(nor, to, len, retlen, buf);
+ if (ret < 0)
+ goto write_err;
} else {
/* the size of data remaining on the first page */
page_size = nor->page_size - page_offset;
- nor->write(nor, to, page_size, retlen, buf);
+ ret = nor->write(nor, to, page_size, retlen, buf);
+ if (ret < 0)
+ goto write_err;
/* write everything in nor->page_size chunks */
- for (i = page_size; i < len; i += page_size) {
+ for (i = ret; i < len; ) {
page_size = len - i;
if (page_size > nor->page_size)
page_size = nor->page_size;
@@ -1035,7 +1053,11 @@ static int spi_nor_write(struct mtd_info
write_enable(nor);
- nor->write(nor, to + i, page_size, retlen, buf + i);
+ ret = nor->write(nor, to + i, page_size, retlen,
+ buf + i);
+ if (ret < 0)
+ goto write_err;
+ i += ret;
}
}

215
target/linux/layerscape/patches-4.4/1094-mtd-spi-nor-stop-passing-around-retlen.patch
View File

@ -1,215 +0,0 @@
From a99477d72b500b48cb3614aad0ce096fe4e3f437 Mon Sep 17 00:00:00 2001
From: Michal Suchanek <hramrach@gmail.com>
Date: Wed, 2 Dec 2015 10:38:20 +0000
Subject: [PATCH 094/113] mtd: spi-nor: stop passing around retlen
[context adjustment]
not apply changes of drivers/mtd/devices/m25p80.c
#################
@@ -74,7 +74,7 @@ static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
}
static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
- size_t *retlen, const u_char *buf)
+ const u_char *buf)
{
struct m25p *flash = nor->priv;
struct spi_device *spi = flash->spi;
@@ -106,7 +106,6 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
ret = m.actual_length - cmd_sz;
if (ret < 0)
return -EIO;
- *retlen += ret;
return ret;
}
@@ -127,7 +126,7 @@ static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
* may be any size provided it is within the physical boundaries.
*/
static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
- size_t *retlen, u_char *buf)
+ u_char *buf)
{
struct m25p *flash = nor->priv;
struct spi_device *spi = flash->spi;
@@ -161,7 +160,6 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
ret = m.actual_length - m25p_cmdsz(nor) - dummy;
if (ret < 0)
return -EIO;
- *retlen += ret;
return ret;
}
#################
Do not pass retlen to hardware driver read/write functions. Update it in
spi-nor generic driver instead.
Signed-off-by: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 16 ++++++----------
drivers/mtd/spi-nor/spi-nor.c | 21 +++++++++++++--------
include/linux/mtd/spi-nor.h | 4 ++--
3 files changed, 21 insertions(+), 20 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -620,7 +620,7 @@ static inline void fsl_qspi_invalid(stru
static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
u8 opcode, unsigned int to, u32 *txbuf,
- unsigned count, size_t *retlen)
+ unsigned count)
{
int ret, i, j;
u32 tmp;
@@ -647,11 +647,8 @@ static ssize_t fsl_qspi_nor_write(struct
/* Trigger it */
ret = fsl_qspi_runcmd(q, opcode, to, count);
- if (ret == 0) {
- if (retlen)
- *retlen += count;
+ if (ret == 0)
return count;
- }
return ret;
}
@@ -862,7 +859,7 @@ static int fsl_qspi_write_reg(struct spi
} else if (len > 0) {
ret = fsl_qspi_nor_write(q, nor, opcode, 0,
- (u32 *)buf, len, NULL);
+ (u32 *)buf, len);
if (ret > 0)
return 0;
} else {
@@ -874,12 +871,11 @@ static int fsl_qspi_write_reg(struct spi
}
static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
- size_t len, size_t *retlen, const u_char *buf)
+ size_t len, const u_char *buf)
{
struct fsl_qspi *q = nor->priv;
-
ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
- (u32 *)buf, len, retlen);
+ (u32 *)buf, len);
/* invalid the data in the AHB buffer. */
fsl_qspi_invalid(q);
@@ -887,7 +883,7 @@ static ssize_t fsl_qspi_write(struct spi
}
static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
- size_t len, size_t *retlen, u_char *buf)
+ size_t len, u_char *buf)
{
struct fsl_qspi *q = nor->priv;
u8 cmd = nor->read_opcode;
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -921,12 +921,13 @@ static int spi_nor_read(struct mtd_info
if (ret)
return ret;
- ret = nor->read(nor, from, len, retlen, buf);
+ ret = nor->read(nor, from, len, buf);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
if (ret < 0)
return ret;
+ *retlen += ret;
return 0;
}
@@ -953,7 +954,7 @@ static int sst_write(struct mtd_info *mt
nor->program_opcode = SPINOR_OP_BP;
/* write one byte. */
- ret = nor->write(nor, to, 1, retlen, buf);
+ ret = nor->write(nor, to, 1, buf);
if (ret < 0)
goto sst_write_err;
WARN(ret != 1, "While writing 1 byte written %i bytes\n",
@@ -969,7 +970,7 @@ static int sst_write(struct mtd_info *mt
nor->program_opcode = SPINOR_OP_AAI_WP;
/* write two bytes. */
- ret = nor->write(nor, to, 2, retlen, buf + actual);
+ ret = nor->write(nor, to, 2, buf + actual);
if (ret < 0)
goto sst_write_err;
WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
@@ -992,7 +993,7 @@ static int sst_write(struct mtd_info *mt
write_enable(nor);
nor->program_opcode = SPINOR_OP_BP;
- ret = nor->write(nor, to, 1, retlen, buf + actual);
+ ret = nor->write(nor, to, 1, buf + actual);
if (ret < 0)
goto sst_write_err;
WARN(ret != 1, "While writing 1 byte written %i bytes\n",
@@ -1001,8 +1002,10 @@ static int sst_write(struct mtd_info *mt
if (ret)
goto sst_write_err;
write_disable(nor);
+ actual += 1;
}
sst_write_err:
+ *retlen += actual;
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
return ret;
}
@@ -1031,15 +1034,17 @@ static int spi_nor_write(struct mtd_info
/* do all the bytes fit onto one page? */
if (page_offset + len <= nor->page_size) {
- ret = nor->write(nor, to, len, retlen, buf);
+ ret = nor->write(nor, to, len, buf);
if (ret < 0)
goto write_err;
+ *retlen += ret;
} else {
/* the size of data remaining on the first page */
page_size = nor->page_size - page_offset;
- ret = nor->write(nor, to, page_size, retlen, buf);
+ ret = nor->write(nor, to, page_size, buf);
if (ret < 0)
goto write_err;
+ *retlen += ret;
/* write everything in nor->page_size chunks */
for (i = ret; i < len; ) {
@@ -1053,10 +1058,10 @@ static int spi_nor_write(struct mtd_info
write_enable(nor);
- ret = nor->write(nor, to + i, page_size, retlen,
- buf + i);
+ ret = nor->write(nor, to + i, page_size, buf + i);
if (ret < 0)
goto write_err;
+ *retlen += ret;
i += ret;
}
}
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -171,9 +171,9 @@ struct spi_nor {
int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
ssize_t (*read)(struct spi_nor *nor, loff_t from,
- size_t len, size_t *retlen, u_char *read_buf);
+ size_t len, u_char *read_buf);
ssize_t (*write)(struct spi_nor *nor, loff_t to,
- size_t len, size_t *retlen, const u_char *write_buf);
+ size_t len, const u_char *write_buf);
int (*erase)(struct spi_nor *nor, loff_t offs);
int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);

100
target/linux/layerscape/patches-4.4/1095-mtd-spi-nor-simplify-write-loop.patch
View File

@ -1,100 +0,0 @@
From 93b40e12f7e580a41c4aee5597579cc539fd8544 Mon Sep 17 00:00:00 2001
From: Michal Suchanek <hramrach@gmail.com>
Date: Wed, 2 Dec 2015 10:38:20 +0000
Subject: [PATCH 095/113] mtd: spi-nor: simplify write loop
The spi-nor write loop assumes that what is passed to the hardware
driver write() is what gets written.
When write() writes less than page size at once data is dropped on the
floor. Check the amount of data writen and exit if it does not match
requested amount.
Signed-off-by: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
---
drivers/mtd/spi-nor/spi-nor.c | 58 ++++++++++++++++++-----------------------
1 file changed, 25 insertions(+), 33 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1019,8 +1019,8 @@ static int spi_nor_write(struct mtd_info
size_t *retlen, const u_char *buf)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
- u32 page_offset, page_size, i;
- int ret;
+ size_t page_offset, page_remain, i;
+ ssize_t ret;
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
@@ -1028,45 +1028,37 @@ static int spi_nor_write(struct mtd_info
if (ret)
return ret;
- write_enable(nor);
+ for (i = 0; i < len; ) {
+ ssize_t written;
- page_offset = to & (nor->page_size - 1);
-
- /* do all the bytes fit onto one page? */
- if (page_offset + len <= nor->page_size) {
- ret = nor->write(nor, to, len, buf);
- if (ret < 0)
- goto write_err;
- *retlen += ret;
- } else {
+ page_offset = to & (nor->page_size - 1);
+ WARN_ONCE(page_offset,
+ "Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.",
+ page_offset);
/* the size of data remaining on the first page */
- page_size = nor->page_size - page_offset;
- ret = nor->write(nor, to, page_size, buf);
+ page_remain = min_t(size_t,
+ nor->page_size - page_offset, len - i);
+
+ write_enable(nor);
+ ret = nor->write(nor, to + i, page_remain, buf + i);
if (ret < 0)
goto write_err;
- *retlen += ret;
+ written = ret;
- /* write everything in nor->page_size chunks */
- for (i = ret; i < len; ) {
- page_size = len - i;
- if (page_size > nor->page_size)
- page_size = nor->page_size;
-
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto write_err;
-
- write_enable(nor);
-
- ret = nor->write(nor, to + i, page_size, buf + i);
- if (ret < 0)
- goto write_err;
- *retlen += ret;
- i += ret;
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ goto write_err;
+ *retlen += written;
+ i += written;
+ if (written != page_remain) {
+ dev_err(nor->dev,
+ "While writing %zu bytes written %zd bytes\n",
+ page_remain, written);
+ ret = -EIO;
+ goto write_err;
}
}
- ret = spi_nor_wait_till_ready(nor);
write_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
return ret;

46
target/linux/layerscape/patches-4.4/1096-mtd-spi-nor-add-read-loop.patch
View File

@ -1,46 +0,0 @@
From b5929f91416d64afacf46c649f38cc8f0eea50d2 Mon Sep 17 00:00:00 2001
From: Michal Suchanek <hramrach@gmail.com>
Date: Wed, 2 Dec 2015 10:38:20 +0000
Subject: [PATCH 096/113] mtd: spi-nor: add read loop
mtdblock and ubi do not handle the situation when read returns less data
than requested. Loop in spi-nor until buffer is filled or an error is
returned.
Signed-off-by: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
---
drivers/mtd/spi-nor/spi-nor.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -921,14 +921,22 @@ static int spi_nor_read(struct mtd_info
if (ret)
return ret;
- ret = nor->read(nor, from, len, buf);
+ while (len) {
+ ret = nor->read(nor, from, len, buf);
+ if (ret <= 0)
+ goto read_err;
- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
- if (ret < 0)
- return ret;
+ WARN_ON(ret > len);
+ *retlen += ret;
+ buf += ret;
+ from += ret;
+ len -= ret;
+ }
+ ret = 0;
- *retlen += ret;
- return 0;
+read_err:
+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
+ return ret;
}
static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,

87
target/linux/layerscape/patches-4.4/1097-mtd-fsl-quadspi-use-the-property-fields-of-SPI-NOR.patch
View File

@ -1,87 +0,0 @@
From 5c315652c1b43a6a3abe48c2842cde822ac0ff3c Mon Sep 17 00:00:00 2001
From: Yunhui Cui <B56489@freescale.com>
Date: Wed, 20 Jan 2016 18:40:31 +0800
Subject: [PATCH 097/113] mtd:fsl-quadspi:use the property fields of SPI-NOR
We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().
Signed-off-by: Yunhui Cui <B56489@freescale.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 40 +++++++++++--------------------------
1 file changed, 12 insertions(+), 28 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl
void __iomem *base = q->iobase;
int rxfifo = q->devtype_data->rxfifo;
u32 lut_base;
- u8 cmd, addrlen, dummy;
int i;
+ struct spi_nor *nor = &q->nor[0];
+ u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
+ u8 read_op = nor->read_opcode;
+ u8 read_dm = nor->read_dummy;
+
fsl_qspi_unlock_lut(q);
/* Clear all the LUT table */
@@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl
/* Quad Read */
lut_base = SEQID_QUAD_READ * 4;
- if (q->nor_size <= SZ_16M) {
- cmd = SPINOR_OP_READ_1_1_4;
- addrlen = ADDR24BIT;
- dummy = 8;
- } else {
- /* use the 4-byte address */
- cmd = SPINOR_OP_READ_1_1_4;
- addrlen = ADDR32BIT;
- dummy = 8;
- }
-
- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
- qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
+ LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
/* Write enable */
@@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl
/* Page Program */
lut_base = SEQID_PP * 4;
- if (q->nor_size <= SZ_16M) {
- cmd = SPINOR_OP_PP;
- addrlen = ADDR24BIT;
- } else {
- /* use the 4-byte address */
- cmd = SPINOR_OP_PP;
- addrlen = ADDR32BIT;
- }
-
- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
+ LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
base + QUADSPI_LUT(lut_base + 1));
@@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl
/* Erase a sector */
lut_base = SEQID_SE * 4;
- cmd = q->nor[0].erase_opcode;
- addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
-
- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
+ LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
/* Erase the whole chip */

46
target/linux/layerscape/patches-4.4/1098-mtd-fsl-quadspi-Rename-SEQID_QUAD_READ-to-SEQID_READ.patch
View File

@ -1,46 +0,0 @@
From c8f9be7df954fce18e96074af3f07aa5f75399e0 Mon Sep 17 00:00:00 2001
From: Yunhui Cui <B56489@freescale.com>
Date: Wed, 20 Jan 2016 15:52:25 +0800
Subject: [PATCH 098/113] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to
SEQID_READ
There are some read modes for flash, such as NORMAL, FAST,
QUAD, DDR QUAD. These modes will use the identical lut table base
So rename SEQID_QUAD_READ to SEQID_READ.
Signed-off-by: Yunhui Cui <B56489@freescale.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -193,7 +193,7 @@
#define QUADSPI_LUT_NUM 64
/* SEQID -- we can have 16 seqids at most. */
-#define SEQID_QUAD_READ 0
+#define SEQID_READ 0
#define SEQID_WREN 1
#define SEQID_WRDI 2
#define SEQID_RDSR 3
@@ -386,8 +386,8 @@ static void fsl_qspi_init_lut(struct fsl
for (i = 0; i < QUADSPI_LUT_NUM; i++)
qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
- /* Quad Read */
- lut_base = SEQID_QUAD_READ * 4;
+ /* Read */
+ lut_base = SEQID_READ * 4;
qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
base + QUADSPI_LUT(lut_base));
@@ -468,7 +468,7 @@ static int fsl_qspi_get_seqid(struct fsl
{
switch (cmd) {
case SPINOR_OP_READ_1_1_4:
- return SEQID_QUAD_READ;
+ return SEQID_READ;
case SPINOR_OP_WREN:
return SEQID_WREN;
case SPINOR_OP_WRDI:

72
target/linux/layerscape/patches-4.4/1099-mtd-spi-nor-fsl-quadspi-Add-fast-read-mode-support.patch
View File

@ -1,72 +0,0 @@
From c501cdf57682265b72a8180c06e4a01dc2978375 Mon Sep 17 00:00:00 2001
From: Yunhui Cui <B56489@freescale.com>
Date: Mon, 1 Feb 2016 18:26:23 +0800
Subject: [PATCH 099/113] mtd:spi-nor:fsl-quadspi:Add fast-read mode support
The qspi driver add generic fast-read mode for different
flash venders. There are some different board flash work on
different mode, such fast-read, quad-mode.
So we have to modify the third entrace parameter of spi_nor_scan().
Signed-off-by: Yunhui Cui <B56489@freescale.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------
1 file changed, 21 insertions(+), 6 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -389,11 +389,21 @@ static void fsl_qspi_init_lut(struct fsl
/* Read */
lut_base = SEQID_READ * 4;
- qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
- base + QUADSPI_LUT(lut_base));
- qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
- LUT1(FSL_READ, PAD4, rxfifo),
- base + QUADSPI_LUT(lut_base + 1));
+ if (nor->flash_read == SPI_NOR_FAST) {
+ qspi_writel(q, LUT0(CMD, PAD1, read_op) |
+ LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
+ LUT1(FSL_READ, PAD1, rxfifo),
+ base + QUADSPI_LUT(lut_base + 1));
+ } else if (nor->flash_read == SPI_NOR_QUAD) {
+ qspi_writel(q, LUT0(CMD, PAD1, read_op) |
+ LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
+ LUT1(FSL_READ, PAD4, rxfifo),
+ base + QUADSPI_LUT(lut_base + 1));
+ }
/* Write enable */
lut_base = SEQID_WREN * 4;
@@ -468,6 +478,7 @@ static int fsl_qspi_get_seqid(struct fsl
{
switch (cmd) {
case SPINOR_OP_READ_1_1_4:
+ case SPINOR_OP_READ_FAST:
return SEQID_READ;
case SPINOR_OP_WREN:
return SEQID_WREN;
@@ -964,6 +975,7 @@ static int fsl_qspi_probe(struct platfor
struct spi_nor *nor;
struct mtd_info *mtd;
int ret, i = 0;
+ enum read_mode mode = SPI_NOR_QUAD;
q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
if (!q)
@@ -1065,7 +1077,10 @@ static int fsl_qspi_probe(struct platfor
/* set the chip address for READID */
fsl_qspi_set_base_addr(q, nor);
- ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
+ ret = of_property_read_bool(np, "m25p,fast-read");
+ mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
+
+ ret = spi_nor_scan(nor, NULL, mode);
if (ret)
goto mutex_failed;

41
target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch
View File

@ -1,41 +0,0 @@
From e892dea7229d56b75c46a76b9039f9e179584a91 Mon Sep 17 00:00:00 2001
From: Yunhui Cui <B56489@freescale.com>
Date: Mon, 1 Feb 2016 18:48:49 +0800
Subject: [PATCH 100/113] mtd:spi_nor: Disable Micron flash HW protection
For Micron family ,The status register write enable/disable bit,
provides hardware data protection for the device.
When the enable/disable bit is set to 1, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute.
Signed-off-by: Yunhui Cui <B56489@freescale.com>
---
drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -39,6 +39,7 @@
#define SPI_NOR_MAX_ID_LEN 6
#define SPI_NOR_MAX_ADDR_WIDTH 4
+#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
struct flash_info {
char *name;
@@ -1246,6 +1247,14 @@ int spi_nor_scan(struct spi_nor *nor, co
if (ret)
return ret;
+ if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
+ ret = read_sr(nor);
+ ret &= SPI_NOR_MICRON_WRITE_ENABLE;
+
+ write_enable(nor);
+ write_sr(nor, ret);
+ }
+
if (!mtd->name)
mtd->name = dev_name(dev);
mtd->priv = nor;

122
target/linux/layerscape/patches-4.4/1101-mtd-spi-nor-fsl-quadspi-extend-support-for-some-spec.patch
View File

@ -1,122 +0,0 @@
From acfc6e9b34b3b3ca0d8bbe366dd08b0fac21c740 Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Tue, 2 Feb 2016 12:21:12 +0800
Subject: [PATCH 101/113] mtd: spi-nor: fsl-quadspi: extend support for some
special requerment.
Add extra info in LUT table to support some special requerments.
Spansion S25FS-S family flash need some special operations.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 44 +++++++++++++++++++++++++++++++++++--
include/linux/mtd/spi-nor.h | 4 ++++
2 files changed, 46 insertions(+), 2 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -205,6 +205,9 @@
#define SEQID_RDCR 9
#define SEQID_EN4B 10
#define SEQID_BRWR 11
+#define SEQID_RDAR 12
+#define SEQID_WRAR 13
+
#define QUADSPI_MIN_IOMAP SZ_4M
@@ -470,6 +473,28 @@ static void fsl_qspi_init_lut(struct fsl
qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
base + QUADSPI_LUT(lut_base));
+ /*
+ * Read any device register.
+ * Used for Spansion S25FS-S family flash only.
+ */
+ lut_base = SEQID_RDAR * 4;
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
+ LUT1(ADDR, PAD1, ADDR24BIT),
+ base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
+ base + QUADSPI_LUT(lut_base + 1));
+
+ /*
+ * Write any device register.
+ * Used for Spansion S25FS-S family flash only.
+ */
+ lut_base = SEQID_WRAR * 4;
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
+ LUT1(ADDR, PAD1, ADDR24BIT),
+ base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
+ base + QUADSPI_LUT(lut_base + 1));
+
fsl_qspi_lock_lut(q);
}
@@ -477,9 +502,15 @@ static void fsl_qspi_init_lut(struct fsl
static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
{
switch (cmd) {
+ case SPINOR_OP_READ4_1_1_4:
case SPINOR_OP_READ_1_1_4:
case SPINOR_OP_READ_FAST:
+ case SPINOR_OP_READ4_FAST:
return SEQID_READ;
+ case SPINOR_OP_SPANSION_RDAR:
+ return SEQID_RDAR;
+ case SPINOR_OP_SPANSION_WRAR:
+ return SEQID_WRAR;
case SPINOR_OP_WREN:
return SEQID_WREN;
case SPINOR_OP_WRDI:
@@ -491,6 +522,7 @@ static int fsl_qspi_get_seqid(struct fsl
case SPINOR_OP_CHIP_ERASE:
return SEQID_CHIP_ERASE;
case SPINOR_OP_PP:
+ case SPINOR_OP_PP_4B:
return SEQID_PP;
case SPINOR_OP_RDID:
return SEQID_RDID;
@@ -830,8 +862,12 @@ static int fsl_qspi_read_reg(struct spi_
{
int ret;
struct fsl_qspi *q = nor->priv;
+ u32 to = 0;
+
+ if (opcode == SPINOR_OP_SPANSION_RDAR)
+ memcpy(&to, nor->cmd_buf, 4);
- ret = fsl_qspi_runcmd(q, opcode, 0, len);
+ ret = fsl_qspi_runcmd(q, opcode, to, len);
if (ret)
return ret;
@@ -843,9 +879,13 @@ static int fsl_qspi_write_reg(struct spi
{
struct fsl_qspi *q = nor->priv;
int ret;
+ u32 to = 0;
+
+ if (opcode == SPINOR_OP_SPANSION_WRAR)
+ memcpy(&to, nor->cmd_buf, 4);
if (!buf) {
- ret = fsl_qspi_runcmd(q, opcode, 0, 1);
+ ret = fsl_qspi_runcmd(q, opcode, to, 1);
if (ret)
return ret;
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -74,6 +74,10 @@
/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
+/* Used for Spansion S25FS-S family flash only. */
+#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */
+#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */
+
/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */

83
target/linux/layerscape/patches-4.4/1102-mtd-spi-nor-fsl-quadspi-Support-qspi-for-ls2080a.patch
View File

@ -1,83 +0,0 @@
From d2d88e3432d68b11b0add84bd15a3aadaf44f1c1 Mon Sep 17 00:00:00 2001
From: Yunhui Cui <B56489@freescale.com>
Date: Mon, 28 Dec 2015 18:25:56 +0800
Subject: [PATCH 102/113] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a
There is a hardware feature that qspi_amba_base is added
internally by SOC design on ls2080a. So as to software, the driver
need support to the feature.
Signed-off-by: Yunhui Cui <B56489@freescale.com>
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -41,6 +41,8 @@
#define QUADSPI_QUIRK_TKT253890 (1 << 2)
/* Controller cannot wake up from wait mode, TKT245618 */
#define QUADSPI_QUIRK_TKT245618 (1 << 3)
+/* QSPI_AMBA_BASE is internally added by SOC design */
+#define QUADSPI_AMBA_BASE_INTERNAL (0x10000)
/* The registers */
#define QUADSPI_MCR 0x00
@@ -217,6 +219,7 @@ enum fsl_qspi_devtype {
FSL_QUADSPI_IMX7D,
FSL_QUADSPI_IMX6UL,
FSL_QUADSPI_LS1021A,
+ FSL_QUADSPI_LS2080A,
};
struct fsl_qspi_devtype_data {
@@ -270,6 +273,14 @@ static struct fsl_qspi_devtype_data ls10
.driver_data = 0,
};
+static struct fsl_qspi_devtype_data ls2080a_data = {
+ .devtype = FSL_QUADSPI_LS2080A,
+ .rxfifo = 128,
+ .txfifo = 64,
+ .ahb_buf_size = 1024,
+ .driver_data = QUADSPI_AMBA_BASE_INTERNAL,
+};
+
#define FSL_QSPI_MAX_CHIP 4
struct fsl_qspi {
struct spi_nor nor[FSL_QSPI_MAX_CHIP];
@@ -312,6 +323,11 @@ static inline int needs_wakeup_wait_mode
return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
}
+static inline int has_added_amba_base_internal(struct fsl_qspi *q)
+{
+ return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
+}
+
/*
* R/W functions for big- or little-endian registers:
* The qSPI controller's endian is independent of the CPU core's endian.
@@ -558,8 +574,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
/* save the reg */
reg = qspi_readl(q, base + QUADSPI_MCR);
- qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
- base + QUADSPI_SFAR);
+ if (has_added_amba_base_internal(q))
+ qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR);
+ else
+ qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
+ base + QUADSPI_SFAR);
qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
base + QUADSPI_RBCT);
qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
@@ -849,6 +868,7 @@ static const struct of_device_id fsl_qsp
{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
+ { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);

110
target/linux/layerscape/patches-4.4/1103-mtd-spi-nor-Support-R-W-for-S25FS-S-family-flash.patch
View File

@ -1,110 +0,0 @@
From 0878404f549021e7fe0a49ae0454cf53fd452add Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Tue, 2 Feb 2016 12:00:27 +0800
Subject: [PATCH 103/113] mtd: spi-nor: Support R/W for S25FS-S family flash
With the physical sectors combination, S25FS-S family flash
requires some special operations for read/write functions.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/spi-nor.c | 60 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -40,6 +40,10 @@
#define SPI_NOR_MAX_ID_LEN 6
#define SPI_NOR_MAX_ADDR_WIDTH 4
#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
+/* Added for S25FS-S family flash */
+#define SPINOR_CONFIG_REG3_OFFSET 0x800004
+#define CR3V_4KB_ERASE_UNABLE 0x8
+#define SPINOR_S25FS_FAMILY_ID 0x81
struct flash_info {
char *name;
@@ -74,6 +78,8 @@ struct flash_info {
};
#define JEDEC_MFR(info) ((info)->id[0])
+#define EXT_ID(info) ((info)->id[5])
+
static const struct flash_info *spi_nor_match_id(const char *name);
@@ -786,6 +792,7 @@ static const struct flash_info spi_nor_i
*/
{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
@@ -910,6 +917,53 @@ static const struct flash_info *spi_nor_
return ERR_PTR(-ENODEV);
}
+/*
+ * The S25FS-S family physical sectors may be configured as a
+ * hybrid combination of eight 4-kB parameter sectors
+ * at the top or bottom of the address space with all
+ * but one of the remaining sectors being uniform size.
+ * The Parameter Sector Erase commands (20h or 21h) must
+ * be used to erase the 4-kB parameter sectors individually.
+ * The Sector (uniform sector) Erase commands (D8h or DCh)
+ * must be used to erase any of the remaining
+ * sectors, including the portion of highest or lowest address
+ * sector that is not overlaid by the parameter sectors.
+ * The uniform sector erase command has no effect on parameter sectors.
+ */
+static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor)
+{
+ struct fsl_qspi *q;
+ u32 cr3v_addr = SPINOR_CONFIG_REG3_OFFSET;
+ u8 cr3v = 0x0;
+ int ret = 0x0;
+
+ q = nor->priv;
+
+ nor->cmd_buf[2] = cr3v_addr >> 16;
+ nor->cmd_buf[1] = cr3v_addr >> 8;
+ nor->cmd_buf[0] = cr3v_addr >> 0;
+
+ ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
+ if (ret)
+ return ret;
+ if (cr3v & CR3V_4KB_ERASE_UNABLE)
+ return 0;
+ ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
+ if (ret)
+ return ret;
+ cr3v = CR3V_4KB_ERASE_UNABLE;
+ nor->program_opcode = SPINOR_OP_SPANSION_WRAR;
+ nor->write(nor, cr3v_addr, 1, &cr3v);
+
+ ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
+ if (ret)
+ return ret;
+ if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
+ return -EPERM;
+
+ return 0;
+}
+
static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
@@ -1255,6 +1309,12 @@ int spi_nor_scan(struct spi_nor *nor, co
write_sr(nor, ret);
}
+ if (EXT_ID(info) == SPINOR_S25FS_FAMILY_ID) {
+ ret = spansion_s25fs_disable_4kb_erase(nor);
+ if (ret)
+ return ret;
+ }
+
if (!mtd->name)
mtd->name = dev_name(dev);
mtd->priv = nor;

112
target/linux/layerscape/patches-4.4/1104-mtd-fsl-quadspi-Add-quad-mode-for-flash-n25q128.patch
View File

@ -1,112 +0,0 @@
From 23cd071c47c064d56921975d196dc22177069dea Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Wed, 24 Feb 2016 15:14:01 +0800
Subject: [PATCH 104/113] mtd: fsl-quadspi: Add quad mode for flash n25q128
Add some lut_tables to support quad mode for flash n25q128
on the board ls1021a-twr and solve flash Spansion and Micron
command conflict.
In switch {}, The value of command SPINOR_OP_RD_EVCR and
SPINOR_OP_SPANSION_RDAR is the same. They have to share
the same seq_id: SEQID_RDAR_OR_RD_EVCR.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++---------
1 file changed, 36 insertions(+), 11 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -207,9 +207,9 @@
#define SEQID_RDCR 9
#define SEQID_EN4B 10
#define SEQID_BRWR 11
-#define SEQID_RDAR 12
+#define SEQID_RDAR_OR_RD_EVCR 12
#define SEQID_WRAR 13
-
+#define SEQID_WD_EVCR 14
#define QUADSPI_MIN_IOMAP SZ_4M
@@ -393,6 +393,7 @@ static void fsl_qspi_init_lut(struct fsl
int rxfifo = q->devtype_data->rxfifo;
u32 lut_base;
int i;
+ const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
struct spi_nor *nor = &q->nor[0];
u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
@@ -489,16 +490,26 @@ static void fsl_qspi_init_lut(struct fsl
qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
base + QUADSPI_LUT(lut_base));
+
/*
- * Read any device register.
- * Used for Spansion S25FS-S family flash only.
+ * Flash Micron and Spansion command confilict
+ * use the same value 0x65. But it indicates different meaning.
*/
- lut_base = SEQID_RDAR * 4;
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
- LUT1(ADDR, PAD1, ADDR24BIT),
- base + QUADSPI_LUT(lut_base));
- qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
- base + QUADSPI_LUT(lut_base + 1));
+ lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
+ if (devtype_data->devtype == FSL_QUADSPI_LS2080A) {
+ /*
+ * Read any device register.
+ * Used for Spansion S25FS-S family flash only.
+ */
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
+ LUT1(ADDR, PAD1, ADDR24BIT),
+ base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
+ base + QUADSPI_LUT(lut_base + 1));
+ } else {
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
+ base + QUADSPI_LUT(lut_base));
+ }
/*
* Write any device register.
@@ -511,6 +522,11 @@ static void fsl_qspi_init_lut(struct fsl
qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
base + QUADSPI_LUT(lut_base + 1));
+ /* Write EVCR register */
+ lut_base = SEQID_WD_EVCR * 4;
+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
+ base + QUADSPI_LUT(lut_base));
+
fsl_qspi_lock_lut(q);
}
@@ -523,8 +539,15 @@ static int fsl_qspi_get_seqid(struct fsl
case SPINOR_OP_READ_FAST:
case SPINOR_OP_READ4_FAST:
return SEQID_READ;
+ /*
+ * Spansion & Micron use the same command value 0x65
+ * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
+ * Micron: SPINOR_OP_RD_EVCR,
+ * read enhanced volatile configuration register.
+ * case SPINOR_OP_RD_EVCR:
+ */
case SPINOR_OP_SPANSION_RDAR:
- return SEQID_RDAR;
+ return SEQID_RDAR_OR_RD_EVCR;
case SPINOR_OP_SPANSION_WRAR:
return SEQID_WRAR;
case SPINOR_OP_WREN:
@@ -550,6 +573,8 @@ static int fsl_qspi_get_seqid(struct fsl
return SEQID_EN4B;
case SPINOR_OP_BRWR:
return SEQID_BRWR;
+ case SPINOR_OP_WD_EVCR:
+ return SEQID_WD_EVCR;
default:
if (cmd == q->nor[0].erase_opcode)
return SEQID_SE;

181
target/linux/layerscape/patches-4.4/1105-mtd-spi-nor-add-DDR-quad-read-support.patch
View File

@ -1,181 +0,0 @@
From 924f021c0344554a4b61746e5c4dcfc91d618ce2 Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Thu, 18 Feb 2016 16:41:53 +0800
Subject: [PATCH 105/113] mtd: spi-nor: add DDR quad read support
This patch adds the DDR quad read support by the following:
[1] add SPI_NOR_DDR_QUAD read mode.
[2] add DDR Quad read opcodes:
SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D
[3] add set_ddr_quad_mode() to initialize for the DDR quad read.
Currently it only works for Spansion NOR.
[4] set dummy with 6 for Spansion family
Test this patch for Spansion s25fl128s NOR flash.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/spi-nor.c | 53 ++++++++++++++++++++++++++++++++++++-----
include/linux/mtd/spi-nor.h | 8 +++++--
2 files changed, 53 insertions(+), 8 deletions(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -73,7 +73,8 @@ struct flash_info {
#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
-#define USE_FSR 0x80 /* use flag status register */
+#define SPI_NOR_DDR_QUAD_READ 0x80 /* Flash supports DDR Quad Read */
+#define USE_FSR 0x100 /* use flag status register */
#define SPI_NOR_HAS_LOCK 0x100 /* Flash supports lock/unlock via SR */
};
@@ -145,13 +146,17 @@ static int read_cr(struct spi_nor *nor)
* It can be used to support more commands with
* different dummy cycle requirements.
*/
-static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
+static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor,
+ const struct flash_info *info)
{
switch (nor->flash_read) {
case SPI_NOR_FAST:
case SPI_NOR_DUAL:
case SPI_NOR_QUAD:
return 8;
+ case SPI_NOR_DDR_QUAD:
+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION)
+ return 6;
case SPI_NOR_NORMAL:
return 0;
}
@@ -799,7 +804,8 @@ static const struct flash_info spi_nor_i
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
- { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
+ { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ
+ | SPI_NOR_DDR_QUAD_READ) },
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
@@ -1195,6 +1201,23 @@ static int spansion_quad_enable(struct s
return 0;
}
+static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info)
+{
+ int status;
+
+ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_SPANSION:
+ status = spansion_quad_enable(nor);
+ if (status) {
+ dev_err(nor->dev, "Spansion DDR quad-read not enabled\n");
+ return status;
+ }
+ return status;
+ default:
+ return -EINVAL;
+ }
+}
+
static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
{
int status;
@@ -1385,8 +1408,15 @@ int spi_nor_scan(struct spi_nor *nor, co
if (info->flags & SPI_NOR_NO_FR)
nor->flash_read = SPI_NOR_NORMAL;
- /* Quad/Dual-read mode takes precedence over fast/normal */
- if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
+ /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
+ if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
+ ret = set_ddr_quad_mode(nor, info);
+ if (ret) {
+ dev_err(dev, "DDR quad mode not supported\n");
+ return ret;
+ }
+ nor->flash_read = SPI_NOR_DDR_QUAD;
+ } else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
ret = set_quad_mode(nor, info);
if (ret) {
dev_err(dev, "quad mode not supported\n");
@@ -1399,6 +1429,14 @@ int spi_nor_scan(struct spi_nor *nor, co
/* Default commands */
switch (nor->flash_read) {
+ case SPI_NOR_DDR_QUAD:
+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { /* Spansion */
+ nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
+ } else {
+ dev_err(dev, "DDR Quad Read is not supported.\n");
+ return -EINVAL;
+ }
+ break;
case SPI_NOR_QUAD:
nor->read_opcode = SPINOR_OP_READ_1_1_4;
break;
@@ -1426,6 +1464,9 @@ int spi_nor_scan(struct spi_nor *nor, co
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
/* Dedicated 4-byte command set */
switch (nor->flash_read) {
+ case SPI_NOR_DDR_QUAD:
+ nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
+ break;
case SPI_NOR_QUAD:
nor->read_opcode = SPINOR_OP_READ4_1_1_4;
break;
@@ -1455,7 +1496,7 @@ int spi_nor_scan(struct spi_nor *nor, co
return -EINVAL;
}
- nor->read_dummy = spi_nor_read_dummy_cycles(nor);
+ nor->read_dummy = spi_nor_read_dummy_cycles(nor, info);
dev_info(dev, "%s (%lld Kbytes)\n", info->name,
(long long)mtd->size >> 10);
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -30,10 +30,11 @@
/*
* Note on opcode nomenclature: some opcodes have a format like
- * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
+ * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y,and z stand for the number
* of I/O lines used for the opcode, address, and data (respectively). The
* FUNCTION has an optional suffix of '4', to represent an opcode which
- * requires a 4-byte (32-bit) address.
+ * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the
+ * DDR mode.
*/
/* Flash opcodes. */
@@ -44,6 +45,7 @@
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
+#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
@@ -59,6 +61,7 @@
#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
+#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
@@ -107,6 +110,7 @@ enum read_mode {
SPI_NOR_FAST,
SPI_NOR_DUAL,
SPI_NOR_QUAD,
+ SPI_NOR_DDR_QUAD,
};
#define SPI_NOR_MAX_CMD_SIZE 8

122
target/linux/layerscape/patches-4.4/1106-mtd-fsl-quadspi-add-DDR-quad-read-for-Spansion.patch
View File

@ -1,122 +0,0 @@
From 16eb35ceea5b43e6f64c1a869721ea86c0da5260 Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Thu, 25 Feb 2016 10:19:15 +0800
Subject: [PATCH 106/113] mtd: fsl-quadspi: add DDR quad read for Spansion
Add the DDR quad read support for the fsl-quadspi driver.
And, add the Spansion s25fl128s NOR flash ddr quad mode
support.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 57 +++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -296,6 +296,7 @@ struct fsl_qspi {
u32 nor_size;
u32 nor_num;
u32 clk_rate;
+ u32 ddr_smp;
unsigned int chip_base_addr; /* We may support two chips. */
bool has_second_chip;
bool big_endian;
@@ -423,6 +424,19 @@ static void fsl_qspi_init_lut(struct fsl
qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
LUT1(FSL_READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
+ } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
+ /* read mode : 1-4-4, such as Spansion s25fl128s. */
+ qspi_writel(q, LUT0(CMD, PAD1, read_op)
+ | LUT1(ADDR_DDR, PAD4, addrlen),
+ base + QUADSPI_LUT(lut_base));
+
+ qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff)
+ | LUT1(DUMMY, PAD1, read_dm),
+ base + QUADSPI_LUT(lut_base + 1));
+
+ qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
+ | LUT1(JMP_ON_CS, PAD1, 0),
+ base + QUADSPI_LUT(lut_base + 2));
}
/* Write enable */
@@ -534,6 +548,8 @@ static void fsl_qspi_init_lut(struct fsl
static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
{
switch (cmd) {
+ case SPINOR_OP_READ_1_4_4_D:
+ case SPINOR_OP_READ4_1_4_4_D:
case SPINOR_OP_READ4_1_1_4:
case SPINOR_OP_READ_1_1_4:
case SPINOR_OP_READ_FAST:
@@ -736,6 +752,32 @@ static void fsl_qspi_set_map_addr(struct
}
/*
+ * enable controller ddr quad mode to support different
+ * vender flashes ddr quad mode.
+ */
+static void set_ddr_quad_mode(struct fsl_qspi *q)
+{
+ u32 reg, reg2;
+
+ reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
+
+ /* Firstly, disable the module */
+ qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
+
+ /* Set the Sampling Register for DDR */
+ reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR);
+ reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
+ reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) &
+ QUADSPI_SMPR_DDRSMP_MASK);
+ qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
+
+ /* Enable the module again (enable the DDR too) */
+ reg |= QUADSPI_MCR_DDR_EN_MASK;
+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
+
+}
+
+/*
* There are two different ways to read out the data from the flash:
* the "IP Command Read" and the "AHB Command Read".
*
@@ -775,6 +817,11 @@ static void fsl_qspi_init_abh_read(struc
seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
q->iobase + QUADSPI_BFGENCR);
+
+ /* enable the DDR quad read */
+ if (q->nor->flash_read == SPI_NOR_DDR_QUAD)
+ set_ddr_quad_mode(q);
+
}
/* This function was used to prepare and enable QSPI clock */
@@ -1108,6 +1155,12 @@ static int fsl_qspi_probe(struct platfor
goto clk_failed;
}
+ /* find ddrsmp value */
+ ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point",
+ &q->ddr_smp);
+ if (ret)
+ q->ddr_smp = 0;
+
/* find the irq */
ret = platform_get_irq(pdev, 0);
if (ret < 0) {
@@ -1164,6 +1217,10 @@ static int fsl_qspi_probe(struct platfor
ret = of_property_read_bool(np, "m25p,fast-read");
mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
+ /* Can we enable the DDR Quad Read? */
+ ret = of_property_read_bool(np, "ddr-quad-read");
+ if (ret)
+ mode = SPI_NOR_DDR_QUAD;
ret = spi_nor_scan(nor, NULL, mode);
if (ret)

67
target/linux/layerscape/patches-4.4/1107-mtd-fsl-quadspi-disable-AHB-buffer-prefetch.patch
View File

@ -1,67 +0,0 @@
From 50aac689d5be0a086f076cd4bc8b14ee0b9ab995 Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Tue, 8 Mar 2016 14:38:52 +0800
Subject: [PATCH 107/113] mtd: fsl-quadspi: disable AHB buffer prefetch
A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
Affects: QuadSPI
Description: With AHB buffer prefetch enabled, the QuadSPI may return
incorrect data on the AHB
interface. The buffer pre-fetch is enabled if the fetch size as
configured either in the LUT or in
the BUFxCR register is greater than 8 bytes.
Impact: Only 64 bit read allowed.
Workaround: Keep the read data size to 64 bits (8 Bytes), which disables
the prefetch on the AHB buffer,
and prevents this issue from occurring.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 29 +++++++++++++++++++++++------
1 file changed, 23 insertions(+), 6 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -794,19 +794,36 @@ static void fsl_qspi_init_abh_read(struc
{
void __iomem *base = q->iobase;
int seqid;
+ const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
/* AHB configuration for access buffer 0/1/2 .*/
qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
+
/*
- * Set ADATSZ with the maximum AHB buffer size to improve the
- * read performance.
+ * Errata: A-009282: QuadSPI data prefetch may result in incorrect data
+ * Workaround: Keep the read data size to 64 bits (8 bytes).
+ * This disables the prefetch on the AHB buffer and
+ * prevents this issue from occurring.
*/
- qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
- ((q->devtype_data->ahb_buf_size / 8)
- << QUADSPI_BUF3CR_ADATSZ_SHIFT),
- base + QUADSPI_BUF3CR);
+ if (devtype_data->devtype == FSL_QUADSPI_LS2080A ||
+ devtype_data->devtype == FSL_QUADSPI_LS1021A) {
+
+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+ (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
+ base + QUADSPI_BUF3CR);
+
+ } else {
+ /*
+ * Set ADATSZ with the maximum AHB buffer size to improve the
+ * read performance.
+ */
+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+ ((q->devtype_data->ahb_buf_size / 8)
+ << QUADSPI_BUF3CR_ADATSZ_SHIFT),
+ base + QUADSPI_BUF3CR);
+ }
/* We only use the buffer3 */
qspi_writel(q, 0, base + QUADSPI_BUF0IND);

42
target/linux/layerscape/patches-4.4/1108-mtd-fsl-quadspi-add-multi-flash-chip-R-W-on-ls2080a.patch
View File

@ -1,42 +0,0 @@
From d3a8ee41170ff9e5298ff354c77ff99439dfe2bf Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Thu, 10 Mar 2016 11:33:40 +0800
Subject: [PATCH 108/113] mtd: fsl-quadspi: add multi flash chip R/W on
ls2080a
There is a hardware feature that qspi_amba_base is added
internally by SOC design on ls2080a. so memmap_phy need not
be added in driver. If memmap_phy is added, the flash A1
addr space is [0, memmap_phy] which far more than flash size.
The AMBA memory will be divided into four parts and assign to
every chipselect. Every channel will has two valid chipselects.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -744,11 +744,17 @@ static void fsl_qspi_set_map_addr(struct
{
int nor_size = q->nor_size;
void __iomem *base = q->iobase;
+ u32 mem_base;
- qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
- qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
- qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
- qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
+ if (has_added_amba_base_internal(q))
+ mem_base = 0x0;
+ else
+ mem_base = q->memmap_phy;
+
+ qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
+ qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
+ qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
+ qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD);
}
/*

36
target/linux/layerscape/patches-4.4/1109-drivers-mtd-spi-nor-Enable-QSPI-Flash-in-Kernel.patch
View File

@ -1,36 +0,0 @@
From 70516f60de441829e7813c0b26567c8bda39c011 Mon Sep 17 00:00:00 2001
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Date: Sun, 24 Apr 2016 23:20:26 +0530
Subject: [PATCH 109/113] drivers: mtd: spi-nor: Enable QSPI Flash in Kernel
Enable read from QSPI flash, Write onto QSPI Flash and
erase QSPI Flash in Fast mode in Kernel.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
drivers/mtd/spi-nor/spi-nor.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -798,6 +798,7 @@ static const struct flash_info spi_nor_i
{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
+ { "s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, 0)},
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
@@ -964,9 +965,11 @@ static int spansion_s25fs_disable_4kb_er
ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
if (ret)
return ret;
+/*
if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
return -EPERM;
+*/
return 0;
}

157
target/linux/layerscape/patches-4.4/1110-mtd-spi-nor-fsl-quad-add-flash-S25FS-extra-support.patch
View File

@ -1,157 +0,0 @@
From 034dd6241b55ab2256eecb845e941fa9b45da38e Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Thu, 28 Apr 2016 17:03:57 +0800
Subject: [PATCH 110/113] mtd: spi-nor: fsl-quad: add flash S25FS extra
support
[context adjustment]
not apply changes of arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
There are some boards have the same QSPI controller but have
different vendor flash, So, the controller can use the same
compatible and share the driver, just for a different flash to do
the appropriate adaptation. Based on this, we need add the vendor
field in spi-nor, Because we will use the field to distribute
corresponding LUT for different flash operations.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++++-------
drivers/mtd/spi-nor/spi-nor.c | 5 ++--
include/linux/mtd/spi-nor.h | 1 +
3 files changed, 42 insertions(+), 11 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -213,6 +213,9 @@
#define QUADSPI_MIN_IOMAP SZ_4M
+#define FLASH_VENDOR_SPANSION_FS "s25fs"
+#define SPANSION_S25FS_FAMILY (1 << 1)
+
enum fsl_qspi_devtype {
FSL_QUADSPI_VYBRID,
FSL_QUADSPI_IMX6SX,
@@ -329,6 +332,18 @@ static inline int has_added_amba_base_in
return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
}
+static u32 fsl_get_nor_vendor(struct spi_nor *nor)
+{
+ u32 vendor_id;
+
+ if (nor->vendor) {
+ if (memcmp(nor->vendor, FLASH_VENDOR_SPANSION_FS,
+ sizeof(FLASH_VENDOR_SPANSION_FS) - 1))
+ vendor_id = SPANSION_S25FS_FAMILY;
+ }
+ return vendor_id;
+}
+
/*
* R/W functions for big- or little-endian registers:
* The qSPI controller's endian is independent of the CPU core's endian.
@@ -394,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl
int rxfifo = q->devtype_data->rxfifo;
u32 lut_base;
int i;
- const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
+ u32 vendor;
struct spi_nor *nor = &q->nor[0];
u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
u8 read_op = nor->read_opcode;
u8 read_dm = nor->read_dummy;
+ vendor = fsl_get_nor_vendor(nor);
+
fsl_qspi_unlock_lut(q);
/* Clear all the LUT table */
@@ -418,12 +435,25 @@ static void fsl_qspi_init_lut(struct fsl
LUT1(FSL_READ, PAD1, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
} else if (nor->flash_read == SPI_NOR_QUAD) {
- qspi_writel(q, LUT0(CMD, PAD1, read_op) |
- LUT1(ADDR, PAD1, addrlen),
- base + QUADSPI_LUT(lut_base));
- qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
- LUT1(FSL_READ, PAD4, rxfifo),
- base + QUADSPI_LUT(lut_base + 1));
+ if (q->nor_size == 0x4000000) {
+ read_op = 0xEC;
+ qspi_writel(q,
+ LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD4, addrlen),
+ base + QUADSPI_LUT(lut_base));
+ qspi_writel(q,
+ LUT0(MODE, PAD4, 0xff) | LUT1(DUMMY, PAD4, read_dm),
+ base + QUADSPI_LUT(lut_base + 1));
+ qspi_writel(q,
+ LUT0(FSL_READ, PAD4, rxfifo),
+ base + QUADSPI_LUT(lut_base + 2));
+ } else {
+ qspi_writel(q, LUT0(CMD, PAD1, read_op) |
+ LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
+ LUT1(FSL_READ, PAD4, rxfifo),
+ base + QUADSPI_LUT(lut_base + 1));
+ }
} else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
/* read mode : 1-4-4, such as Spansion s25fl128s. */
qspi_writel(q, LUT0(CMD, PAD1, read_op)
@@ -510,7 +540,8 @@ static void fsl_qspi_init_lut(struct fsl
* use the same value 0x65. But it indicates different meaning.
*/
lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
- if (devtype_data->devtype == FSL_QUADSPI_LS2080A) {
+
+ if (vendor == SPANSION_S25FS_FAMILY) {
/*
* Read any device register.
* Used for Spansion S25FS-S family flash only.
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -798,7 +798,6 @@ static const struct flash_info spi_nor_i
{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
- { "s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, 0)},
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
@@ -965,11 +964,9 @@ static int spansion_s25fs_disable_4kb_er
ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
if (ret)
return ret;
-/*
if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
return -EPERM;
-*/
return 0;
}
@@ -1343,6 +1340,8 @@ int spi_nor_scan(struct spi_nor *nor, co
if (!mtd->name)
mtd->name = dev_name(dev);
+ if (info->name)
+ nor->vendor = info->name;
mtd->priv = nor;
mtd->type = MTD_NORFLASH;
mtd->writesize = 1;
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -172,6 +172,7 @@ struct spi_nor {
bool sst_write_second;
u32 flags;
u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
+ char *vendor;
int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);

27
target/linux/layerscape/patches-4.4/1111-mtd-spi-nor-disable-4kb-sector-erase-for-s25fl128.patch
View File

@ -1,27 +0,0 @@
From 30d34abc80b0a602a1327bdfbddd42d250887049 Mon Sep 17 00:00:00 2001
From: Yutang Jiang <yutang.jiang@nxp.com>
Date: Fri, 9 Sep 2016 22:56:12 +0800
Subject: [PATCH 111/113] mtd: spi-nor: disable 4kb sector erase for s25fl128
As for s25fl128s flash, the sectors are organized either as a hybrid
combination of 4-kB and 64-kB sectors, or as uniform 256-kbyte sectors.
we should use the command 0xd8 to erase all bits, not the Parameter 4-kB
Sector Erase (P4E) command 0x20.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Integrated-by: Yutang Jiang <yutang.jiang@nxp.com>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -804,7 +804,7 @@ static const struct flash_info spi_nor_i
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
- { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ
+ { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ
| SPI_NOR_DDR_QUAD_READ) },
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

29
target/linux/layerscape/patches-4.4/1112-driver-spi-fsl-quad-Hang-memcpy-Unhandled-fault-alig.patch
View File

@ -1,29 +0,0 @@
From f1b7824a42505669476f203e126fc26dd1006af2 Mon Sep 17 00:00:00 2001
From: Yutang Jiang <yutang.jiang@nxp.com>
Date: Fri, 9 Sep 2016 22:57:55 +0800
Subject: [PATCH 112/113] driver: spi: fsl-quad: Hang memcpy: Unhandled fault:
alignment fault
vmap/iomap based on whether the buffer is in memory region or reserved region.
However, both map it as non-cacheable memory.
For armv8 specifically, non-cacheable mapping requests use a memory type
that has to be accessed aligned to the request size. memcpy() doesn't guarantee
that. memcpy_toio() can guarantee 4-bytes alignment.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Integrated-by: Yutang Jiang <yutang.jiang@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -1103,7 +1103,7 @@ static ssize_t fsl_qspi_read(struct spi_
len);
/* Read out the data directly from the AHB buffer.*/
- memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
+ memcpy_toio(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
len);
return len;

49
target/linux/layerscape/patches-4.4/1113-mtd-spi-nor-fsl-quad-move-mtd_device_register-to-the.patch
View File

@ -1,49 +0,0 @@
From 6f1195d231ab576809fe2f4cff44a6e48cff2457 Mon Sep 17 00:00:00 2001
From: Yutang Jiang <yutang.jiang@nxp.com>
Date: Fri, 2 Sep 2016 22:00:16 +0800
Subject: [PATCH 113/113] mtd: spi-nor: fsl-quad: move mtd_device_register to
the last of probe
After call mtd_device_register, the mtd devices should be workable immediately.
If before finish all of init work call the mtd_device_register, it will not
respond work request timely.
For example, openwrt/lede have a AUTO split special flash partitions mechanism
while mtd driver register. So, before call mtd_device_register, must let all of
init work ready.
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -1280,10 +1280,6 @@ static int fsl_qspi_probe(struct platfor
if (ret)
goto mutex_failed;
- ret = mtd_device_register(mtd, NULL, 0);
- if (ret)
- goto mutex_failed;
-
/* Set the correct NOR size now. */
if (q->nor_size == 0) {
q->nor_size = mtd->size;
@@ -1313,6 +1309,16 @@ static int fsl_qspi_probe(struct platfor
goto last_init_failed;
fsl_qspi_clk_disable_unprep(q);
+
+ for (i = 0; i < q->nor_num; i++) {
+ /* skip the holes */
+ if (!q->has_second_chip)
+ i *= 2;
+
+ ret = mtd_device_register(&q->nor[i].mtd, NULL, 0);
+ if (ret)
+ goto last_init_failed;
+ }
return 0;
last_init_failed:

85
target/linux/layerscape/patches-4.4/1239-mtd-extend-physmap_of-to-let-the-device-tree-specify.patch
View File

@ -1,85 +0,0 @@
From 6b54054c4053215fe4add195c67daca9a466ba92 Mon Sep 17 00:00:00 2001
From: "ying.zhang" <ying.zhang22455@nxp.com>
Date: Fri, 23 Dec 2016 22:21:22 +0800
Subject: [PATCH] mtd: extend physmap_of to let the device tree specify the
parition probe
This is to support custom partitioning schemes for embedded PPC. To use
define your own mtd_part_parser and then add something like:
linux,part-probe = "my_probe", "cmdlinepart";
To the board's dts file.
If linux,part-probe is not specified then this behaves the same as before.
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
---
drivers/mtd/maps/physmap_of.c | 46 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
--- a/drivers/mtd/maps/physmap_of.c
+++ b/drivers/mtd/maps/physmap_of.c
@@ -112,9 +112,47 @@ static struct mtd_info *obsolete_probe(s
static const char * const part_probe_types_def[] = {
"cmdlinepart", "RedBoot", "ofpart", "ofoldpart", NULL };
+static const char * const *of_get_probes(struct device_node *dp)
+{
+ const char *cp;
+ int cplen;
+ unsigned int l;
+ unsigned int count;
+ const char **res;
+
+ cp = of_get_property(dp, "linux,part-probe", &cplen);
+ if (cp == NULL)
+ return part_probe_types_def;
+
+ count = 0;
+ for (l = 0; l != cplen; l++)
+ if (cp[l] == 0)
+ count++;
+
+ res = kzalloc((count + 1)*sizeof(*res), GFP_KERNEL);
+ if (!res)
+ return NULL;
+ count = 0;
+ while (cplen > 0) {
+ res[count] = cp;
+ l = strlen(cp) + 1;
+ cp += l;
+ cplen -= l;
+ count++;
+ }
+ return res;
+}
+
+static void of_free_probes(const char * const *probes)
+{
+ if (probes != part_probe_types_def)
+ kfree(probes);
+}
+
static const struct of_device_id of_flash_match[];
static int of_flash_probe(struct platform_device *dev)
{
+ const char * const *part_probe_types;
const struct of_device_id *match;
struct device_node *dp = dev->dev.of_node;
struct resource res;
@@ -273,8 +311,14 @@ static int of_flash_probe(struct platfor
goto err_out;
ppdata.of_node = dp;
- mtd_device_parse_register(info->cmtd, part_probe_types_def, &ppdata,
+ part_probe_types = of_get_probes(dp);
+ if (!part_probe_types) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+ mtd_device_parse_register(info->cmtd, part_probe_types, &ppdata,
NULL, 0);
+ of_free_probes(part_probe_types);
kfree(mtd_list);

209
target/linux/layerscape/patches-4.4/2006-armv8-aarch32-Add-the-default-config-ls_aarch32_defc.patch
View File

@ -1,209 +0,0 @@
From 4c4e5c275a0e37570d6267802e66a350b0b93dcd Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Tue, 17 May 2016 17:30:19 +0800
Subject: [PATCH 06/70] armv8: aarch32: Add the default config
ls_aarch32_defconfig
ls_aarch32_defconfig is used as the default config for running 32-bit
Linux.
Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
---
arch/arm/configs/ls_aarch32_defconfig | 190 +++++++++++++++++++++++++++++++++
1 file changed, 190 insertions(+)
create mode 100644 arch/arm/configs/ls_aarch32_defconfig
--- /dev/null
+++ b/arch/arm/configs/ls_aarch32_defconfig
@@ -0,0 +1,190 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_CMDLINE_PARSER=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARM_LPAE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_SMP=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_CLEANCACHE=y
+CONFIG_FRONTSWAP=y
+CONFIG_CMDLINE="console=ttyS0,115200"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_CAN=y
+# CONFIG_CAN_BCM is not set
+# CONFIG_CAN_GW is not set
+CONFIG_CAN_FLEXCAN=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=8
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_FREESCALE is not set
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_PHYLIB=y
+CONFIG_AT803X_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+CONFIG_SERIO_SERPORT=m
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_FSL_DSPI=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_SENSORS_LTC2945=y
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_INA2XX=y
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_SYSCON=y
+CONFIG_FB=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_DMADEVICES=y
+CONFIG_FSL_EDMA=y
+CONFIG_CLK_QORIQ=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_MEMORY=y
+CONFIG_PWM=y
+CONFIG_PWM_FSL_FTM=y
+# CONFIG_RESET_CONTROLLER is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=m
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_PID_IN_CONTEXTIDR=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m

101
target/linux/layerscape/patches-4.4/2027-armv8-aarch32-update-defconfig-for-LayerScape-SoC.patch
View File

@ -1,101 +0,0 @@
From 0cc4fd2e52f23f9b35dfdac80021da97ac6c2c52 Mon Sep 17 00:00:00 2001
From: Pan Jiafei <Jiafei.Pan@nxp.com>
Date: Tue, 24 May 2016 16:15:49 +0800
Subject: [PATCH 27/70] armv8: aarch32: update defconfig for LayerScape SoC
Enable QBMan, FMD, DPAA ethernet, kernel bridge, ATA,
DMA_CMA, USB_STORAGE, PHY etc.
Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
---
arch/arm/configs/ls_aarch32_defconfig | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
--- a/arch/arm/configs/ls_aarch32_defconfig
+++ b/arch/arm/configs/ls_aarch32_defconfig
@@ -26,6 +26,7 @@ CONFIG_ARCH_MXC=y
CONFIG_ARCH_LAYERSCAPE=y
CONFIG_ARM_LPAE=y
# CONFIG_CACHE_L2X0 is not set
+CONFIG_HAS_FSL_QBMAN=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_HOST_GENERIC=y
@@ -36,6 +37,7 @@ CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_CLEANCACHE=y
+CONFIG_CMA=y
CONFIG_FRONTSWAP=y
CONFIG_CMDLINE="console=ttyS0,115200"
CONFIG_CPU_FREQ=y
@@ -62,6 +64,7 @@ CONFIG_INET_IPCOMP=y
CONFIG_INET_UDP_DIAG=y
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
+CONFIG_BRIDGE=y
CONFIG_CAN=y
# CONFIG_CAN_BCM is not set
# CONFIG_CAN_GW is not set
@@ -69,6 +72,7 @@ CONFIG_CAN_FLEXCAN=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FW_LOADER is not set
+CONFIG_DMA_CMA=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -81,17 +85,26 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSL_IFC=y
CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=8
CONFIG_BLK_DEV_RAM_SIZE=262144
CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_FREESCALE is not set
+CONFIG_NET_VENDOR_FREESCALE is not set
+CONFIG_FSL_BMAN=y
+CONFIG_FSL_QMAN=y
+CONFIG_FSL_SDK_FMAN=y
+CONFIG_FMAN_ARM=y
+CONFIG_FSL_SDK_DPAA_ETH=y
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_PHYLIB=y
@@ -101,6 +114,8 @@ CONFIG_BROADCOM_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_NATIONAL_PHY=y
CONFIG_MICREL_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_FSL_XGMAC_MDIO=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_INPUT_EVDEV=y
# CONFIG_MOUSE_PS2_TRACKPOINT is not set
@@ -135,6 +150,8 @@ CONFIG_MFD_SYSCON=y
CONFIG_FB=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
@@ -143,6 +160,7 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS3232=y
CONFIG_DMADEVICES=y
CONFIG_FSL_EDMA=y
+CONFIG_STAGING=y
CONFIG_CLK_QORIQ=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y

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