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uboot-rockchip: remove prebuilt of-platdata (#9747)
With this change you need have swig and libpython3-dev installed on your host, which should be done already. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
GitHub
parent
9a3ab942b0
commit
bd522ba3a1
@ -32,7 +32,6 @@ define U-Boot/nanopi-r2c-rk3328
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DEPENDS:=+PACKAGE_u-boot-nanopi-r2c-rk3328:arm-trusted-firmware-rk3328
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DEPENDS:=+PACKAGE_u-boot-nanopi-r2c-rk3328:arm-trusted-firmware-rk3328
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk322xh_bl31_v1.46.elf
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ATF:=rk322xh_bl31_v1.46.elf
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OF_PLATDATA:=$(1)
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USE_RKBIN:=1
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USE_RKBIN:=1
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endef
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endef
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@ -45,7 +44,6 @@ define U-Boot/nanopi-r2s-rk3328
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DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rk3328
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DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rk3328
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk322xh_bl31_v1.46.elf
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ATF:=rk322xh_bl31_v1.46.elf
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OF_PLATDATA:=$(1)
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USE_RKBIN:=1
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USE_RKBIN:=1
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endef
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endef
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@ -57,7 +55,6 @@ define U-Boot/orangepi-r1-plus-rk3328
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DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-rk3328:arm-trusted-firmware-rk3328
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DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-rk3328:arm-trusted-firmware-rk3328
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk322xh_bl31_v1.46.elf
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ATF:=rk322xh_bl31_v1.46.elf
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OF_PLATDATA:=$(1)
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USE_RKBIN:=1
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USE_RKBIN:=1
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endef
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endef
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@ -69,7 +66,6 @@ define U-Boot/orangepi-r1-plus-lts-rk3328
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DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-lts-rk3328:arm-trusted-firmware-rk3328
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DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-lts-rk3328:arm-trusted-firmware-rk3328
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk322xh_bl31_v1.46.elf
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ATF:=rk322xh_bl31_v1.46.elf
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OF_PLATDATA:=$(1)
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USE_RKBIN:=1
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USE_RKBIN:=1
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endef
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endef
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@ -81,7 +77,6 @@ define U-Boot/doornet1-rk3328
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DEPENDS:=+PACKAGE_u-boot-doornet1-rk3328:arm-trusted-firmware-rk3328
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DEPENDS:=+PACKAGE_u-boot-doornet1-rk3328:arm-trusted-firmware-rk3328
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk322xh_bl31_v1.46.elf
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ATF:=rk322xh_bl31_v1.46.elf
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OF_PLATDATA:=$(1)
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USE_RKBIN:=1
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USE_RKBIN:=1
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endef
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endef
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@ -171,15 +166,7 @@ UBOOT_MAKE_FLAGS += \
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define Build/Configure
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define Build/Configure
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$(call Build/Configure/U-Boot)
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$(call Build/Configure/U-Boot)
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ifneq ($(OF_PLATDATA),)
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$(SED) 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
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mkdir -p $(PKG_BUILD_DIR)/tpl/dts
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mkdir -p $(PKG_BUILD_DIR)/include/generated
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$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c
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$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h
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$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h
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endif
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$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
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$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
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echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config
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echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config
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endef
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endef
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@ -1,21 +0,0 @@
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From d585719ad3f737ca5e5186fe55be964340ecfcc7 Mon Sep 17 00:00:00 2001
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From: Marty Jones <mj8263788@gmail.com>
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Date: Mon, 4 Oct 2021 16:46:32 -0400
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Subject: [PATCH] tools:disable TOOLS_LIBCRYPTO
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Signed-off-by: Marty Jones <mj8263788@gmail.com>
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---
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tools/Kconfig | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/tools/Kconfig
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+++ b/tools/Kconfig
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@@ -16,7 +16,7 @@ config TOOLS_CRC32
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config TOOLS_LIBCRYPTO
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bool "Use OpenSSL's libcrypto library for host tools"
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- default y
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+ default n
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help
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Cryptographic signature, verification, and encryption of images is
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provided by host tools using OpenSSL's libcrypto. Select 'n' here if
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@ -1,24 +0,0 @@
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From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001
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From: David Bauer <mail@david-bauer.net>
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Date: Mon, 13 Jul 2020 23:37:37 +0200
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Subject: [PATCH] scripts: remove dependency on swig
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Don't build the libfdt tool, as it has a dependency on swig (which
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OpenWrt does not ship).
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This requires more hacks, as of-platdata generation does not work
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without it.
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Signed-off-by: David Bauer <mail@david-bauer.net>
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---
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scripts/dtc/Makefile | 2 --
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1 file changed, 2 deletions(-)
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--- a/scripts/dtc/Makefile
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+++ b/scripts/dtc/Makefile
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@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src)
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# dependencies on generated files need to be listed explicitly
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$(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h
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-# Added for U-Boot
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-subdir-$(CONFIG_PYLIBFDT) += pylibfdt
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@ -1,28 +0,0 @@
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From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001
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From: David Bauer <mail@david-bauer.net>
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Date: Tue, 14 Jul 2020 22:44:22 +0200
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Subject: [PATCH] spl: remove dtoc of-pdata generation
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Remove the dtoc of-pdata generation. This generation is dependant on
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libpython-dev. As OpenWrt does not ship with this dependency, use
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pre-generated pdata files and remove the generation from the
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build-process.
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This only affects RK3328 boards.
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Signed-off-by: David Bauer <mail@david-bauer.net>
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---
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scripts/Makefile.spl | 6 ------
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1 file changed, 6 deletions(-)
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--- a/scripts/Makefile.spl
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+++ b/scripts/Makefile.spl
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@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c)
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@# of OF_PLATDATA_INST and this might change between builds. Leaving old
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@# ones around is confusing and it is possible that switching the
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@# setting again will use the old one instead of regenerating it.
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- @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata)
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- $(call if_changed,dtoc)
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ifdef CONFIG_SAMSUNG
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ifdef CONFIG_VAR_SIZE_SPL
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@ -1,23 +0,0 @@
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/*
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* DO NOT MODIFY
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*
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* Declares externs for all device/uclass instances.
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* This was generated by dtoc from a .dtb (device tree binary) file.
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*/
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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/* driver declarations - these allow DM_DRIVER_GET() to be used */
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extern U_BOOT_DRIVER(rockchip_rk3328_cru);
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extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
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extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
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extern U_BOOT_DRIVER(ns16550_serial);
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extern U_BOOT_DRIVER(rockchip_rk3328_grf);
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/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
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extern UCLASS_DRIVER(clk);
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extern UCLASS_DRIVER(mmc);
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extern UCLASS_DRIVER(ram);
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extern UCLASS_DRIVER(serial);
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extern UCLASS_DRIVER(syscon);
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@ -1,127 +0,0 @@
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/*
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* DO NOT MODIFY
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*
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* Declares the U_BOOT_DRIVER() records and platform data.
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* This was generated by dtoc from a .dtb (device tree binary) file.
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*/
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/* Allow use of U_BOOT_DRVINFO() in this file */
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#define DT_PLAT_C
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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/* Node /clock-controller@ff440000 index 0 */
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static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
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.reg = {0xff440000, 0x1000},
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.rockchip_grf = 0x3a,
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};
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U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
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.name = "rockchip_rk3328_cru",
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.plat = &dtv_clock_controller_at_ff440000,
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.plat_size = sizeof(dtv_clock_controller_at_ff440000),
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.parent_idx = -1,
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};
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/* Node /dmc index 1 */
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static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
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.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
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0xff720000, 0x1000, 0xff798000, 0x1000},
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.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
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0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
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0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
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0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
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0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
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0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
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0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
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0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
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0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
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0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
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0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
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0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
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0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
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0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
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0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
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0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
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0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
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0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
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0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
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0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
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0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
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0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
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0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
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0x77, 0x77, 0x79, 0x9},
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};
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U_BOOT_DRVINFO(dmc) = {
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.name = "rockchip_rk3328_dmc",
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.plat = &dtv_dmc,
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.plat_size = sizeof(dtv_dmc),
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.parent_idx = -1,
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};
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/* Node /mmc@ff500000 index 2 */
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static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
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.bus_width = 0x4,
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.cap_sd_highspeed = true,
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.clocks = {
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{0, {317}},
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{0, {33}},
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{0, {74}},
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{0, {78}},},
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.disable_wp = true,
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.fifo_depth = 0x100,
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.interrupts = {0x0, 0xc, 0x4},
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.max_frequency = 0x8f0d180,
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.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
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.pinctrl_names = "default",
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.reg = {0xff500000, 0x4000},
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.sd_uhs_sdr104 = true,
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.sd_uhs_sdr12 = true,
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.sd_uhs_sdr25 = true,
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.sd_uhs_sdr50 = true,
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.u_boot_spl_fifo_mode = true,
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.vmmc_supply = 0x4b,
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.vqmmc_supply = 0x1e,
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};
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U_BOOT_DRVINFO(mmc_at_ff500000) = {
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.name = "rockchip_rk3288_dw_mshc",
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.plat = &dtv_mmc_at_ff500000,
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.plat_size = sizeof(dtv_mmc_at_ff500000),
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.parent_idx = -1,
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};
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/* Node /serial@ff130000 index 3 */
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static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
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.clock_frequency = 0x16e3600,
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.clocks = {
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{0, {40}},
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{0, {212}},},
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.dma_names = {"tx", "rx"},
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.dmas = {0x10, 0x6, 0x10, 0x7},
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.interrupts = {0x0, 0x39, 0x4},
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.pinctrl_0 = 0x26,
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.pinctrl_names = "default",
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.reg = {0xff130000, 0x100},
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.reg_io_width = 0x4,
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.reg_shift = 0x2,
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};
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U_BOOT_DRVINFO(serial_at_ff130000) = {
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.name = "ns16550_serial",
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.plat = &dtv_serial_at_ff130000,
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.plat_size = sizeof(dtv_serial_at_ff130000),
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.parent_idx = -1,
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};
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/* Node /syscon@ff100000 index 4 */
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static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
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.reg = {0xff100000, 0x1000},
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};
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U_BOOT_DRVINFO(syscon_at_ff100000) = {
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.name = "rockchip_rk3328_grf",
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|
||||||
.plat = &dtv_syscon_at_ff100000,
|
|
||||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Defines the structs used to hold devicetree data.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdbool.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
struct dtd_ns16550_serial {
|
|
||||||
fdt32_t clock_frequency;
|
|
||||||
struct phandle_1_arg clocks[2];
|
|
||||||
const char * dma_names[2];
|
|
||||||
fdt32_t dmas[4];
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t pinctrl_0;
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t reg_io_width;
|
|
||||||
fdt32_t reg_shift;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3288_dw_mshc {
|
|
||||||
fdt32_t bus_width;
|
|
||||||
bool cap_sd_highspeed;
|
|
||||||
struct phandle_1_arg clocks[4];
|
|
||||||
bool disable_wp;
|
|
||||||
fdt32_t fifo_depth;
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t max_frequency;
|
|
||||||
fdt32_t pinctrl_0[4];
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
bool sd_uhs_sdr104;
|
|
||||||
bool sd_uhs_sdr12;
|
|
||||||
bool sd_uhs_sdr25;
|
|
||||||
bool sd_uhs_sdr50;
|
|
||||||
bool u_boot_spl_fifo_mode;
|
|
||||||
fdt32_t vmmc_supply;
|
|
||||||
fdt32_t vqmmc_supply;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_cru {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t rockchip_grf;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_dmc {
|
|
||||||
fdt64_t reg[12];
|
|
||||||
fdt32_t rockchip_sdram_params[196];
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_grf {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
};
|
|
||||||
@ -1,23 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Declares externs for all device/uclass instances.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <dm/device-internal.h>
|
|
||||||
#include <dm/uclass-internal.h>
|
|
||||||
|
|
||||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
|
||||||
extern U_BOOT_DRIVER(ns16550_serial);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
|
||||||
|
|
||||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
|
||||||
extern UCLASS_DRIVER(clk);
|
|
||||||
extern UCLASS_DRIVER(mmc);
|
|
||||||
extern UCLASS_DRIVER(ram);
|
|
||||||
extern UCLASS_DRIVER(serial);
|
|
||||||
extern UCLASS_DRIVER(syscon);
|
|
||||||
@ -1,155 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Declares the U_BOOT_DRIVER() records and platform data.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Allow use of U_BOOT_DRVINFO() in this file */
|
|
||||||
#define DT_PLAT_C
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <dm.h>
|
|
||||||
#include <dt-structs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
|
||||||
*
|
|
||||||
* idx driver_info driver
|
|
||||||
* --- -------------------- --------------------
|
|
||||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
|
||||||
* 1: dmc rockchip_rk3328_dmc
|
|
||||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
|
||||||
* 3: serial_at_ff130000 ns16550_serial
|
|
||||||
* 4: syscon_at_ff100000 rockchip_rk3328_grf
|
|
||||||
* --- -------------------- --------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /clock-controller@ff440000 index 0
|
|
||||||
* driver rockchip_rk3328_cru parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
|
||||||
.reg = {0xff440000, 0x1000},
|
|
||||||
.rockchip_grf = 0x3a,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
|
||||||
.name = "rockchip_rk3328_cru",
|
|
||||||
.plat = &dtv_clock_controller_at_ff440000,
|
|
||||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /dmc index 1
|
|
||||||
* driver rockchip_rk3328_dmc parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
|
||||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
|
||||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
|
||||||
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
|
|
||||||
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
|
|
||||||
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
|
|
||||||
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
|
|
||||||
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
|
|
||||||
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
|
|
||||||
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
|
|
||||||
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
|
|
||||||
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
|
|
||||||
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
|
|
||||||
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
|
|
||||||
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
|
|
||||||
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
|
|
||||||
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
|
|
||||||
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
|
|
||||||
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
|
|
||||||
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
|
|
||||||
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
|
|
||||||
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
|
|
||||||
0x77, 0x77, 0x79, 0x9},
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(dmc) = {
|
|
||||||
.name = "rockchip_rk3328_dmc",
|
|
||||||
.plat = &dtv_dmc,
|
|
||||||
.plat_size = sizeof(dtv_dmc),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /mmc@ff500000 index 2
|
|
||||||
* driver rockchip_rk3288_dw_mshc parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
|
||||||
.bus_width = 0x4,
|
|
||||||
.cap_sd_highspeed = true,
|
|
||||||
.clocks = {
|
|
||||||
{0, {317}},
|
|
||||||
{0, {33}},
|
|
||||||
{0, {74}},
|
|
||||||
{0, {78}},},
|
|
||||||
.disable_wp = true,
|
|
||||||
.fifo_depth = 0x100,
|
|
||||||
.interrupts = {0x0, 0xc, 0x4},
|
|
||||||
.max_frequency = 0x8f0d180,
|
|
||||||
.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
|
|
||||||
.pinctrl_names = "default",
|
|
||||||
.reg = {0xff500000, 0x4000},
|
|
||||||
.sd_uhs_sdr104 = true,
|
|
||||||
.sd_uhs_sdr12 = true,
|
|
||||||
.sd_uhs_sdr25 = true,
|
|
||||||
.sd_uhs_sdr50 = true,
|
|
||||||
.u_boot_spl_fifo_mode = true,
|
|
||||||
.vmmc_supply = 0x4b,
|
|
||||||
.vqmmc_supply = 0x1e,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
|
||||||
.name = "rockchip_rk3288_dw_mshc",
|
|
||||||
.plat = &dtv_mmc_at_ff500000,
|
|
||||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /serial@ff130000 index 3
|
|
||||||
* driver ns16550_serial parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
|
||||||
.clock_frequency = 0x16e3600,
|
|
||||||
.clocks = {
|
|
||||||
{0, {40}},
|
|
||||||
{0, {212}},},
|
|
||||||
.dma_names = {"tx", "rx"},
|
|
||||||
.dmas = {0x10, 0x6, 0x10, 0x7},
|
|
||||||
.interrupts = {0x0, 0x39, 0x4},
|
|
||||||
.pinctrl_0 = 0x26,
|
|
||||||
.pinctrl_names = "default",
|
|
||||||
.reg = {0xff130000, 0x100},
|
|
||||||
.reg_io_width = 0x4,
|
|
||||||
.reg_shift = 0x2,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
|
||||||
.name = "ns16550_serial",
|
|
||||||
.plat = &dtv_serial_at_ff130000,
|
|
||||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /syscon@ff100000 index 4
|
|
||||||
* driver rockchip_rk3328_grf parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
|
||||||
.reg = {0xff100000, 0x1000},
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
|
||||||
.name = "rockchip_rk3328_grf",
|
|
||||||
.plat = &dtv_syscon_at_ff100000,
|
|
||||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Defines the structs used to hold devicetree data.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdbool.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
struct dtd_ns16550_serial {
|
|
||||||
fdt32_t clock_frequency;
|
|
||||||
struct phandle_1_arg clocks[2];
|
|
||||||
const char * dma_names[2];
|
|
||||||
fdt32_t dmas[4];
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t pinctrl_0;
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t reg_io_width;
|
|
||||||
fdt32_t reg_shift;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3288_dw_mshc {
|
|
||||||
fdt32_t bus_width;
|
|
||||||
bool cap_sd_highspeed;
|
|
||||||
struct phandle_1_arg clocks[4];
|
|
||||||
bool disable_wp;
|
|
||||||
fdt32_t fifo_depth;
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t max_frequency;
|
|
||||||
fdt32_t pinctrl_0[4];
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
bool sd_uhs_sdr104;
|
|
||||||
bool sd_uhs_sdr12;
|
|
||||||
bool sd_uhs_sdr25;
|
|
||||||
bool sd_uhs_sdr50;
|
|
||||||
bool u_boot_spl_fifo_mode;
|
|
||||||
fdt32_t vmmc_supply;
|
|
||||||
fdt32_t vqmmc_supply;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_cru {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t rockchip_grf;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_dmc {
|
|
||||||
fdt64_t reg[12];
|
|
||||||
fdt32_t rockchip_sdram_params[196];
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_grf {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
};
|
|
||||||
@ -1,23 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Declares externs for all device/uclass instances.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <dm/device-internal.h>
|
|
||||||
#include <dm/uclass-internal.h>
|
|
||||||
|
|
||||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
|
||||||
extern U_BOOT_DRIVER(ns16550_serial);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
|
||||||
|
|
||||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
|
||||||
extern UCLASS_DRIVER(clk);
|
|
||||||
extern UCLASS_DRIVER(mmc);
|
|
||||||
extern UCLASS_DRIVER(ram);
|
|
||||||
extern UCLASS_DRIVER(serial);
|
|
||||||
extern UCLASS_DRIVER(syscon);
|
|
||||||
@ -1,155 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Declares the U_BOOT_DRIVER() records and platform data.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Allow use of U_BOOT_DRVINFO() in this file */
|
|
||||||
#define DT_PLAT_C
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <dm.h>
|
|
||||||
#include <dt-structs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
|
||||||
*
|
|
||||||
* idx driver_info driver
|
|
||||||
* --- -------------------- --------------------
|
|
||||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
|
||||||
* 1: dmc rockchip_rk3328_dmc
|
|
||||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
|
||||||
* 3: serial_at_ff130000 ns16550_serial
|
|
||||||
* 4: syscon_at_ff100000 rockchip_rk3328_grf
|
|
||||||
* --- -------------------- --------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /clock-controller@ff440000 index 0
|
|
||||||
* driver rockchip_rk3328_cru parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
|
||||||
.reg = {0xff440000, 0x1000},
|
|
||||||
.rockchip_grf = 0x3a,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
|
||||||
.name = "rockchip_rk3328_cru",
|
|
||||||
.plat = &dtv_clock_controller_at_ff440000,
|
|
||||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /dmc index 1
|
|
||||||
* driver rockchip_rk3328_dmc parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
|
||||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
|
||||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
|
||||||
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
|
|
||||||
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
|
|
||||||
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
|
|
||||||
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
|
|
||||||
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
|
|
||||||
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
|
|
||||||
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
|
|
||||||
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
|
|
||||||
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
|
|
||||||
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
|
|
||||||
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
|
|
||||||
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
|
|
||||||
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
|
|
||||||
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
|
|
||||||
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
|
|
||||||
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
|
|
||||||
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
|
|
||||||
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
|
|
||||||
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
|
|
||||||
0x77, 0x77, 0x79, 0x9},
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(dmc) = {
|
|
||||||
.name = "rockchip_rk3328_dmc",
|
|
||||||
.plat = &dtv_dmc,
|
|
||||||
.plat_size = sizeof(dtv_dmc),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /mmc@ff500000 index 2
|
|
||||||
* driver rockchip_rk3288_dw_mshc parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
|
||||||
.bus_width = 0x4,
|
|
||||||
.cap_sd_highspeed = true,
|
|
||||||
.clocks = {
|
|
||||||
{0, {317}},
|
|
||||||
{0, {33}},
|
|
||||||
{0, {74}},
|
|
||||||
{0, {78}},},
|
|
||||||
.disable_wp = true,
|
|
||||||
.fifo_depth = 0x100,
|
|
||||||
.interrupts = {0x0, 0xc, 0x4},
|
|
||||||
.max_frequency = 0x8f0d180,
|
|
||||||
.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
|
|
||||||
.pinctrl_names = "default",
|
|
||||||
.reg = {0xff500000, 0x4000},
|
|
||||||
.sd_uhs_sdr104 = true,
|
|
||||||
.sd_uhs_sdr12 = true,
|
|
||||||
.sd_uhs_sdr25 = true,
|
|
||||||
.sd_uhs_sdr50 = true,
|
|
||||||
.u_boot_spl_fifo_mode = true,
|
|
||||||
.vmmc_supply = 0x4b,
|
|
||||||
.vqmmc_supply = 0x1e,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
|
||||||
.name = "rockchip_rk3288_dw_mshc",
|
|
||||||
.plat = &dtv_mmc_at_ff500000,
|
|
||||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /serial@ff130000 index 3
|
|
||||||
* driver ns16550_serial parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
|
||||||
.clock_frequency = 0x16e3600,
|
|
||||||
.clocks = {
|
|
||||||
{0, {40}},
|
|
||||||
{0, {212}},},
|
|
||||||
.dma_names = {"tx", "rx"},
|
|
||||||
.dmas = {0x10, 0x6, 0x10, 0x7},
|
|
||||||
.interrupts = {0x0, 0x39, 0x4},
|
|
||||||
.pinctrl_0 = 0x26,
|
|
||||||
.pinctrl_names = "default",
|
|
||||||
.reg = {0xff130000, 0x100},
|
|
||||||
.reg_io_width = 0x4,
|
|
||||||
.reg_shift = 0x2,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
|
||||||
.name = "ns16550_serial",
|
|
||||||
.plat = &dtv_serial_at_ff130000,
|
|
||||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /syscon@ff100000 index 4
|
|
||||||
* driver rockchip_rk3328_grf parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
|
||||||
.reg = {0xff100000, 0x1000},
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
|
||||||
.name = "rockchip_rk3328_grf",
|
|
||||||
.plat = &dtv_syscon_at_ff100000,
|
|
||||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Defines the structs used to hold devicetree data.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdbool.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
struct dtd_ns16550_serial {
|
|
||||||
fdt32_t clock_frequency;
|
|
||||||
struct phandle_1_arg clocks[2];
|
|
||||||
const char * dma_names[2];
|
|
||||||
fdt32_t dmas[4];
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t pinctrl_0;
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t reg_io_width;
|
|
||||||
fdt32_t reg_shift;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3288_dw_mshc {
|
|
||||||
fdt32_t bus_width;
|
|
||||||
bool cap_sd_highspeed;
|
|
||||||
struct phandle_1_arg clocks[4];
|
|
||||||
bool disable_wp;
|
|
||||||
fdt32_t fifo_depth;
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t max_frequency;
|
|
||||||
fdt32_t pinctrl_0[4];
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
bool sd_uhs_sdr104;
|
|
||||||
bool sd_uhs_sdr12;
|
|
||||||
bool sd_uhs_sdr25;
|
|
||||||
bool sd_uhs_sdr50;
|
|
||||||
bool u_boot_spl_fifo_mode;
|
|
||||||
fdt32_t vmmc_supply;
|
|
||||||
fdt32_t vqmmc_supply;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_cru {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t rockchip_grf;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_dmc {
|
|
||||||
fdt64_t reg[12];
|
|
||||||
fdt32_t rockchip_sdram_params[196];
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_grf {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
};
|
|
||||||
@ -1,23 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Declares externs for all device/uclass instances.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <dm/device-internal.h>
|
|
||||||
#include <dm/uclass-internal.h>
|
|
||||||
|
|
||||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
|
||||||
extern U_BOOT_DRIVER(ns16550_serial);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
|
||||||
|
|
||||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
|
||||||
extern UCLASS_DRIVER(clk);
|
|
||||||
extern UCLASS_DRIVER(mmc);
|
|
||||||
extern UCLASS_DRIVER(ram);
|
|
||||||
extern UCLASS_DRIVER(serial);
|
|
||||||
extern UCLASS_DRIVER(syscon);
|
|
||||||
@ -1,154 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Declares the U_BOOT_DRIVER() records and platform data.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Allow use of U_BOOT_DRVINFO() in this file */
|
|
||||||
#define DT_PLAT_C
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <dm.h>
|
|
||||||
#include <dt-structs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
|
||||||
*
|
|
||||||
* idx driver_info driver
|
|
||||||
* --- -------------------- --------------------
|
|
||||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
|
||||||
* 1: dmc rockchip_rk3328_dmc
|
|
||||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
|
||||||
* 3: serial_at_ff130000 ns16550_serial
|
|
||||||
* 4: syscon_at_ff100000 rockchip_rk3328_grf
|
|
||||||
* --- -------------------- --------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /clock-controller@ff440000 index 0
|
|
||||||
* driver rockchip_rk3328_cru parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
|
||||||
.reg = {0xff440000, 0x1000},
|
|
||||||
.rockchip_grf = 0x3a,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
|
||||||
.name = "rockchip_rk3328_cru",
|
|
||||||
.plat = &dtv_clock_controller_at_ff440000,
|
|
||||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /dmc index 1
|
|
||||||
* driver rockchip_rk3328_dmc parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
|
||||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
|
||||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
|
||||||
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
|
|
||||||
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
|
|
||||||
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
|
|
||||||
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
|
|
||||||
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
|
|
||||||
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
|
|
||||||
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
|
|
||||||
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
|
|
||||||
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
|
|
||||||
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
|
|
||||||
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
|
|
||||||
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
|
|
||||||
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
|
|
||||||
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
|
|
||||||
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
|
|
||||||
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
|
|
||||||
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
|
|
||||||
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
|
|
||||||
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
|
|
||||||
0x77, 0x77, 0x79, 0x9},
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(dmc) = {
|
|
||||||
.name = "rockchip_rk3328_dmc",
|
|
||||||
.plat = &dtv_dmc,
|
|
||||||
.plat_size = sizeof(dtv_dmc),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /mmc@ff500000 index 2
|
|
||||||
* driver rockchip_rk3288_dw_mshc parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
|
||||||
.bus_width = 0x4,
|
|
||||||
.cap_sd_highspeed = true,
|
|
||||||
.clocks = {
|
|
||||||
{0, {317}},
|
|
||||||
{0, {33}},
|
|
||||||
{0, {74}},
|
|
||||||
{0, {78}},},
|
|
||||||
.disable_wp = true,
|
|
||||||
.fifo_depth = 0x100,
|
|
||||||
.interrupts = {0x0, 0xc, 0x4},
|
|
||||||
.max_frequency = 0x8f0d180,
|
|
||||||
.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
|
|
||||||
.pinctrl_names = "default",
|
|
||||||
.reg = {0xff500000, 0x4000},
|
|
||||||
.sd_uhs_sdr104 = true,
|
|
||||||
.sd_uhs_sdr12 = true,
|
|
||||||
.sd_uhs_sdr25 = true,
|
|
||||||
.sd_uhs_sdr50 = true,
|
|
||||||
.u_boot_spl_fifo_mode = true,
|
|
||||||
.vmmc_supply = 0x4b,
|
|
||||||
.vqmmc_supply = 0x1e,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
|
||||||
.name = "rockchip_rk3288_dw_mshc",
|
|
||||||
.plat = &dtv_mmc_at_ff500000,
|
|
||||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /serial@ff130000 index 3
|
|
||||||
* driver ns16550_serial parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
|
||||||
.clock_frequency = 0x16e3600,
|
|
||||||
.clocks = {
|
|
||||||
{0, {40}},
|
|
||||||
{0, {212}},},
|
|
||||||
.dma_names = {"tx", "rx"},
|
|
||||||
.dmas = {0x10, 0x6, 0x10, 0x7},
|
|
||||||
.interrupts = {0x0, 0x39, 0x4},
|
|
||||||
.pinctrl_0 = 0x26,
|
|
||||||
.pinctrl_names = "default",
|
|
||||||
.reg = {0xff130000, 0x100},
|
|
||||||
.reg_io_width = 0x4,
|
|
||||||
.reg_shift = 0x2,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
|
||||||
.name = "ns16550_serial",
|
|
||||||
.plat = &dtv_serial_at_ff130000,
|
|
||||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /syscon@ff100000 index 4
|
|
||||||
* driver rockchip_rk3328_grf parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
|
||||||
.reg = {0xff100000, 0x1000},
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
|
||||||
.name = "rockchip_rk3328_grf",
|
|
||||||
.plat = &dtv_syscon_at_ff100000,
|
|
||||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Defines the structs used to hold devicetree data.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdbool.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
struct dtd_ns16550_serial {
|
|
||||||
fdt32_t clock_frequency;
|
|
||||||
struct phandle_1_arg clocks[2];
|
|
||||||
const char * dma_names[2];
|
|
||||||
fdt32_t dmas[4];
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t pinctrl_0;
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t reg_io_width;
|
|
||||||
fdt32_t reg_shift;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3288_dw_mshc {
|
|
||||||
fdt32_t bus_width;
|
|
||||||
bool cap_sd_highspeed;
|
|
||||||
struct phandle_1_arg clocks[4];
|
|
||||||
bool disable_wp;
|
|
||||||
fdt32_t fifo_depth;
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t max_frequency;
|
|
||||||
fdt32_t pinctrl_0[4];
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
bool sd_uhs_sdr104;
|
|
||||||
bool sd_uhs_sdr12;
|
|
||||||
bool sd_uhs_sdr25;
|
|
||||||
bool sd_uhs_sdr50;
|
|
||||||
bool u_boot_spl_fifo_mode;
|
|
||||||
fdt32_t vmmc_supply;
|
|
||||||
fdt32_t vqmmc_supply;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_cru {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t rockchip_grf;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_dmc {
|
|
||||||
fdt64_t reg[12];
|
|
||||||
fdt32_t rockchip_sdram_params[196];
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_grf {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
};
|
|
||||||
@ -1,23 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Declares externs for all device/uclass instances.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <dm/device-internal.h>
|
|
||||||
#include <dm/uclass-internal.h>
|
|
||||||
|
|
||||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
|
||||||
extern U_BOOT_DRIVER(ns16550_serial);
|
|
||||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
|
||||||
|
|
||||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
|
||||||
extern UCLASS_DRIVER(clk);
|
|
||||||
extern UCLASS_DRIVER(mmc);
|
|
||||||
extern UCLASS_DRIVER(ram);
|
|
||||||
extern UCLASS_DRIVER(serial);
|
|
||||||
extern UCLASS_DRIVER(syscon);
|
|
||||||
@ -1,155 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Declares the U_BOOT_DRIVER() records and platform data.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Allow use of U_BOOT_DRVINFO() in this file */
|
|
||||||
#define DT_PLAT_C
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <dm.h>
|
|
||||||
#include <dt-structs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
|
||||||
*
|
|
||||||
* idx driver_info driver
|
|
||||||
* --- -------------------- --------------------
|
|
||||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
|
||||||
* 1: dmc rockchip_rk3328_dmc
|
|
||||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
|
||||||
* 3: serial_at_ff130000 ns16550_serial
|
|
||||||
* 4: syscon_at_ff100000 rockchip_rk3328_grf
|
|
||||||
* --- -------------------- --------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /clock-controller@ff440000 index 0
|
|
||||||
* driver rockchip_rk3328_cru parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
|
||||||
.reg = {0xff440000, 0x1000},
|
|
||||||
.rockchip_grf = 0x3a,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
|
||||||
.name = "rockchip_rk3328_cru",
|
|
||||||
.plat = &dtv_clock_controller_at_ff440000,
|
|
||||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /dmc index 1
|
|
||||||
* driver rockchip_rk3328_dmc parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
|
||||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
|
||||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
|
||||||
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
|
|
||||||
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
|
|
||||||
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
|
|
||||||
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
|
|
||||||
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
|
|
||||||
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
|
|
||||||
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
|
|
||||||
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
|
|
||||||
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
|
|
||||||
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
|
|
||||||
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
|
|
||||||
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
|
|
||||||
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
|
|
||||||
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
|
|
||||||
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
|
|
||||||
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
|
|
||||||
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
|
||||||
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
|
|
||||||
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
|
|
||||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
|
|
||||||
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
|
|
||||||
0x77, 0x77, 0x79, 0x9},
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(dmc) = {
|
|
||||||
.name = "rockchip_rk3328_dmc",
|
|
||||||
.plat = &dtv_dmc,
|
|
||||||
.plat_size = sizeof(dtv_dmc),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /mmc@ff500000 index 2
|
|
||||||
* driver rockchip_rk3288_dw_mshc parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
|
||||||
.bus_width = 0x4,
|
|
||||||
.cap_sd_highspeed = true,
|
|
||||||
.clocks = {
|
|
||||||
{0, {317}},
|
|
||||||
{0, {33}},
|
|
||||||
{0, {74}},
|
|
||||||
{0, {78}},},
|
|
||||||
.disable_wp = true,
|
|
||||||
.fifo_depth = 0x100,
|
|
||||||
.interrupts = {0x0, 0xc, 0x4},
|
|
||||||
.max_frequency = 0x8f0d180,
|
|
||||||
.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
|
|
||||||
.pinctrl_names = "default",
|
|
||||||
.reg = {0xff500000, 0x4000},
|
|
||||||
.sd_uhs_sdr104 = true,
|
|
||||||
.sd_uhs_sdr12 = true,
|
|
||||||
.sd_uhs_sdr25 = true,
|
|
||||||
.sd_uhs_sdr50 = true,
|
|
||||||
.u_boot_spl_fifo_mode = true,
|
|
||||||
.vmmc_supply = 0x4b,
|
|
||||||
.vqmmc_supply = 0x1e,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
|
||||||
.name = "rockchip_rk3288_dw_mshc",
|
|
||||||
.plat = &dtv_mmc_at_ff500000,
|
|
||||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /serial@ff130000 index 3
|
|
||||||
* driver ns16550_serial parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
|
||||||
.clock_frequency = 0x16e3600,
|
|
||||||
.clocks = {
|
|
||||||
{0, {40}},
|
|
||||||
{0, {212}},},
|
|
||||||
.dma_names = {"tx", "rx"},
|
|
||||||
.dmas = {0x10, 0x6, 0x10, 0x7},
|
|
||||||
.interrupts = {0x0, 0x39, 0x4},
|
|
||||||
.pinctrl_0 = 0x26,
|
|
||||||
.pinctrl_names = "default",
|
|
||||||
.reg = {0xff130000, 0x100},
|
|
||||||
.reg_io_width = 0x4,
|
|
||||||
.reg_shift = 0x2,
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
|
||||||
.name = "ns16550_serial",
|
|
||||||
.plat = &dtv_serial_at_ff130000,
|
|
||||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Node /syscon@ff100000 index 4
|
|
||||||
* driver rockchip_rk3328_grf parent None
|
|
||||||
*/
|
|
||||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
|
||||||
.reg = {0xff100000, 0x1000},
|
|
||||||
};
|
|
||||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
|
||||||
.name = "rockchip_rk3328_grf",
|
|
||||||
.plat = &dtv_syscon_at_ff100000,
|
|
||||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
|
||||||
.parent_idx = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
/*
|
|
||||||
* DO NOT MODIFY
|
|
||||||
*
|
|
||||||
* Defines the structs used to hold devicetree data.
|
|
||||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdbool.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
struct dtd_ns16550_serial {
|
|
||||||
fdt32_t clock_frequency;
|
|
||||||
struct phandle_1_arg clocks[2];
|
|
||||||
const char * dma_names[2];
|
|
||||||
fdt32_t dmas[4];
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t pinctrl_0;
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t reg_io_width;
|
|
||||||
fdt32_t reg_shift;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3288_dw_mshc {
|
|
||||||
fdt32_t bus_width;
|
|
||||||
bool cap_sd_highspeed;
|
|
||||||
struct phandle_1_arg clocks[4];
|
|
||||||
bool disable_wp;
|
|
||||||
fdt32_t fifo_depth;
|
|
||||||
fdt32_t interrupts[3];
|
|
||||||
fdt32_t max_frequency;
|
|
||||||
fdt32_t pinctrl_0[4];
|
|
||||||
const char * pinctrl_names;
|
|
||||||
fdt64_t reg[2];
|
|
||||||
bool sd_uhs_sdr104;
|
|
||||||
bool sd_uhs_sdr12;
|
|
||||||
bool sd_uhs_sdr25;
|
|
||||||
bool sd_uhs_sdr50;
|
|
||||||
bool u_boot_spl_fifo_mode;
|
|
||||||
fdt32_t vmmc_supply;
|
|
||||||
fdt32_t vqmmc_supply;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_cru {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
fdt32_t rockchip_grf;
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_dmc {
|
|
||||||
fdt64_t reg[12];
|
|
||||||
fdt32_t rockchip_sdram_params[196];
|
|
||||||
};
|
|
||||||
struct dtd_rockchip_rk3328_grf {
|
|
||||||
fdt64_t reg[2];
|
|
||||||
};
|
|
||||||
Loading…
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