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https://github.com/coolsnowwolf/lede.git
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uboot-rockchip: bump to v2023.04
For the python problem, just make clean. Skip the gpio patch due to it may broken boot.
This commit is contained in:
AmadeusGhost
parent
88989f2722
commit
bb084c1d09
@ -5,10 +5,10 @@
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_VERSION:=2022.07
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PKG_VERSION:=2023.04
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PKG_RELEASE:=$(AUTORELEASE)
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PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e
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PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
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PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
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@ -77,7 +77,7 @@ define U-Boot/guangmiao-g4c-rk3399
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NAME:=GuangMiao G4C
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BUILD_DEVICES:= \
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sharevdi_guangmiao-g4c
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DEPENDS:=+PACKAGE_u-boot-guangmiao-g4c-rk3399:arm-trusted-firmware-rockchip
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DEPENDS:=+PACKAGE_u-boot-guangmiao-g4c-rk3399:trusted-firmware-a-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3399_bl31.elf
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endef
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@ -109,7 +109,7 @@ define U-Boot/rock-pi-4-rk3399
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NAME:=Rock Pi 4
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BUILD_DEVICES:= \
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radxa_rock-pi-4
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DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:arm-trusted-firmware-rockchip
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DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:trusted-firmware-a-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3399_bl31.elf
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endef
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@ -119,7 +119,7 @@ define U-Boot/rockpro64-rk3399
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NAME:=RockPro64
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BUILD_DEVICES:= \
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pine64_rockpro64
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DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip
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DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:trusted-firmware-a-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3399_bl31.elf
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endef
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@ -165,9 +165,9 @@ define U-Boot/mrkaio-m68s-rk3568
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BUILD_DEVICES:= \
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ezpro_mrkaio-m68s \
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ezpro_mrkaio-m68s-plus
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DEPENDS:=+PACKAGE_u-boot-mrkaio-m68s-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DEPENDS:=+PACKAGE_u-boot-mrkaio-m68s-rk3568:trusted-firmware-a-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3568_bl31.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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@ -177,9 +177,9 @@ define U-Boot/nanopi-r5s-rk3568
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BUILD_DEVICES:= \
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friendlyarm_nanopi-r5c \
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friendlyarm_nanopi-r5s
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DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:trusted-firmware-a-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3568_bl31.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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@ -190,9 +190,9 @@ define U-Boot/opc-h68k-rk3568
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hinlink_opc-h66k \
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hinlink_opc-h68k \
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hinlink_opc-h69k
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DEPENDS:=+PACKAGE_u-boot-opc-h68k-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DEPENDS:=+PACKAGE_u-boot-opc-h68k-rk3568:trusted-firmware-a-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3568_bl31.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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@ -201,9 +201,9 @@ define U-Boot/photonicat-rk3568
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NAME:=Ariaboard Photonicat
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BUILD_DEVICES:= \
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ariaboard_photonicat
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DEPENDS:=+PACKAGE_u-boot-photonicat-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DEPENDS:=+PACKAGE_u-boot-photonicat-rk3568:trusted-firmware-a-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3568_bl31.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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@ -212,9 +212,9 @@ define U-Boot/radxa-e25-rk3568
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NAME:=Radxa E25
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BUILD_DEVICES:= \
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radxa_e25
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DEPENDS:=+PACKAGE_u-boot-radxa-e25-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DEPENDS:=+PACKAGE_u-boot-radxa-e25-rk3568:trusted-firmware-a-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3568_bl31.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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@ -223,9 +223,9 @@ define U-Boot/rock-3a-rk3568
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NAME:=ROCK3 Model A
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BUILD_DEVICES:= \
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radxa_rock-3a
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DEPENDS:=+PACKAGE_u-boot-rock-3a-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DEPENDS:=+PACKAGE_u-boot-rock-3a-rk3568:trusted-firmware-a-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3568_bl31.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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@ -235,9 +235,9 @@ define U-Boot/r66s-rk3568
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BUILD_DEVICES:= \
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fastrhino_r66s \
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fastrhino_r68s
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DEPENDS:=+PACKAGE_u-boot-r66s-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DEPENDS:=+PACKAGE_u-boot-r66s-rk3568:trusted-firmware-a-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3568_bl31.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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@ -246,9 +246,9 @@ define U-Boot/station-p2-rk3568
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NAME:=StationP2
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BUILD_DEVICES:= \
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firefly_station-p2
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DEPENDS:=+PACKAGE_u-boot-station-p2-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.34.elf
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DEPENDS:=+PACKAGE_u-boot-station-p2-rk3568:trusted-firmware-a-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
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ATF:=rk3568_bl31.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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@ -279,15 +279,39 @@ UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
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UBOOT_MAKE_FLAGS += \
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BL31=$(STAGING_DIR_IMAGE)/$(ATF)
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ifeq ($(CONFIG_PACKAGE_trusted-firmware-a-rk3568),y)
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UBOOT_MAKE_FLAGS += \
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ROCKCHIP_TPL=$(PKG_BUILD_DIR)/$(DDR)
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endif
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RKBIN_URL:=https://raw.githubusercontent.com/rockchip-linux/rkbin/b0c100f1a260d807df450019774993c761beb79d
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define Download/rk3566-ddr
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FILE:=rk3566_ddr_1056MHz_v1.13.bin
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URL:=$(RKBIN_URL)/bin/rk35/
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HASH:=6f165b37640eb876b5f41297bcce6451eb8a86fa56649633d4aca76047136a36
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endef
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$(eval $(call Download,rk3566-ddr))
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define Download/rk3568-ddr
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FILE:=rk3568_ddr_1560MHz_v1.13.bin
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URL:=$(RKBIN_URL)/bin/rk35/
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HASH:=53d5e893916e647ccb8c5a2a51f749e9e11bf7329e61a2f94d8c089a333d7812
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endef
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$(eval $(call Download,rk3568-ddr))
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define Build/Prepare
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$(call Build/Prepare/Default)
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$(CP) $(DL_DIR)/rk3566_ddr_1056MHz_v1.13.bin $(PKG_BUILD_DIR)/
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$(CP) $(DL_DIR)/rk3568_ddr_1560MHz_v1.13.bin $(PKG_BUILD_DIR)/
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endef
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define Build/Configure
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$(call Build/Configure/U-Boot)
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$(SED) 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
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$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
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echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config
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ifneq ($(DDR),)
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$(CP) $(STAGING_DIR_IMAGE)/$(DDR) $(PKG_BUILD_DIR)/ram_init.bin
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endif
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endef
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define Build/InstallDev
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@ -1,43 +0,0 @@
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From 9b92a43a4f5acf4cba14fd9d473b3120688532dc Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 19 Dec 2021 08:10:24 -0500
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Subject: [PATCH 01/11] rockchip: rk3568: add boot device detection
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Enable spl to detect which device it was booted from.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
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+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
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@@ -7,6 +7,7 @@
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#include <dm.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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+#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/grf_rk3568.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <dt-bindings/clock/rk3568-cru.h>
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@@ -23,6 +24,7 @@
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#define SGRF_SOC_CON4 0x10
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#define EMMC_HPROT_SECURE_CTRL 0x03
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#define SDMMC0_HPROT_SECURE_CTRL 0x01
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+
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/* PMU_GRF_GPIO0D_IOMUX_L */
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enum {
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GPIO0D1_SHIFT = 4,
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@@ -43,6 +45,12 @@ enum {
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UART2_IO_SEL_M0 = 0,
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};
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+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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+ [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
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+ [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
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+ [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
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+};
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+
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static struct mm_region rk3568_mem_map[] = {
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{
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.virt = 0x0UL,
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@ -1,52 +0,0 @@
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From 09d877cf076cbb67c79054e12bbb7c63a91faa71 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 19 Dec 2021 08:11:56 -0500
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Subject: [PATCH 02/11] rockchip: rk3568: enable automatic power savings
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Enable automatic clock gating, solves the 7c temperature difference on
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SoQuartz.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
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+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
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@@ -25,6 +25,15 @@
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#define EMMC_HPROT_SECURE_CTRL 0x03
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#define SDMMC0_HPROT_SECURE_CTRL 0x01
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+#define PMU_BASE_ADDR 0xfdd90000
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+#define PMU_NOC_AUTO_CON0 (0x70)
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+#define PMU_NOC_AUTO_CON1 (0x74)
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+#define EDP_PHY_GRF_BASE 0xfdcb0000
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+#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
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+#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
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+#define CPU_GRF_BASE 0xfdc30000
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+#define GRF_CORE_PVTPLL_CON0 (0x10)
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+
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/* PMU_GRF_GPIO0D_IOMUX_L */
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enum {
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GPIO0D1_SHIFT = 4,
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@@ -99,6 +108,20 @@ void board_debug_uart_init(void)
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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+ /*
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+ * When perform idle operation, corresponding clock can
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+ * be opened or gated automatically.
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+ */
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+ writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
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+ writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
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+
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+ /* Disable eDP phy by default */
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+ writel(0x00070007, EDP_PHY_GRF_CON10);
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+ writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
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+
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+ /* Set core pvtpll ring length */
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+ writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
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+
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/* Set the emmc sdmmc0 to secure */
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rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
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| SDMMC0_HPROT_SECURE_CTRL << 4));
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@ -1,47 +0,0 @@
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From ddbcec939789d1f7264134b3628ffb649ec88168 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 19 Dec 2021 08:20:33 -0500
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Subject: [PATCH 03/11] Makefile: rockchip: HACK: build rk3568 images
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This is a hack to build rk3568 images.
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It seems makefile can't cope with the format mkimage expects for
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multiple file entries, so hack around the situation.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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Makefile | 10 ++++++++++
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1 file changed, 10 insertions(+)
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--- a/Makefile
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+++ b/Makefile
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@@ -1047,6 +1047,9 @@ quiet_cmd_mkimage = MKIMAGE $@
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cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
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>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
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+cmd_mkimage_combined = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $(COMBINED_FILE):$< $@ \
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+ >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
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+
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quiet_cmd_mkfitimage = MKIMAGE $@
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cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) \
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-f $(U_BOOT_ITS) -p $(CONFIG_FIT_EXTERNAL_OFFSET) $@ \
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@@ -1491,6 +1494,7 @@ u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_
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ifeq ($(CONFIG_ARCH_ROCKCHIP),y)
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# TPL + SPL
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+ifneq ($(CONFIG_SYS_SOC),$(filter $(CONFIG_SYS_SOC),"rk3568" "rk3566"))
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ifeq ($(CONFIG_SPL)$(CONFIG_TPL),yy)
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MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T rksd
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tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE
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@@ -1502,6 +1506,12 @@ MKIMAGEFLAGS_idbloader.img = -n $(CONFIG
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idbloader.img: spl/u-boot-spl.bin FORCE
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$(call if_changed,mkimage)
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endif
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+else
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+MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T rksd
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+COMBINED_FILE = ram_init.bin
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+idbloader.img: spl/u-boot-spl.bin FORCE
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+ $(call if_changed,mkimage_combined)
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+endif
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ifeq ($(CONFIG_ARM64),y)
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OBJCOPYFLAGS_u-boot-rockchip.bin = -I binary -O binary \
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File diff suppressed because it is too large
Load Diff
@ -1,50 +0,0 @@
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From 01e8a38985a90043abddc5c5bcd049c74bb29a53 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 19 Dec 2021 18:52:18 -0500
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Subject: [PATCH 05/11] rockchip: rk356x: HACK: fix sdmmc support
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HACK: lock mmc0 to initial frequency and disable dw-mmc control of power
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line.
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The sdmmc on quartz64-a is powered by the sdmmc0 power line, which is
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active low.
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Even though it is set as a gpio, it still seems to be triggered by the
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dw-mmc driver toggling the power line.
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Downstream fixes this by setting this to "0" instead of "1" using
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kconfigs.
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Also, for some reason the controller will only operate at initial
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frequencies.
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||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 4 +++-
|
||||
drivers/mmc/dw_mmc.c | 3 ++-
|
||||
2 files changed, 5 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
|
||||
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
|
||||
@@ -13,8 +13,10 @@
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
+ max-frequency = <400000>;
|
||||
+ bus-width = <4>;
|
||||
u-boot,dm-spl;
|
||||
- status = "okay";
|
||||
+ u-boot,spl-fifo-mode;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
--- a/drivers/mmc/dw_mmc.c
|
||||
+++ b/drivers/mmc/dw_mmc.c
|
||||
@@ -529,7 +529,8 @@ static int dwmci_init(struct mmc *mmc)
|
||||
if (host->board_init)
|
||||
host->board_init(host);
|
||||
|
||||
- dwmci_writel(host, DWMCI_PWREN, 1);
|
||||
+// dwmci_writel(host, DWMCI_PWREN, 1);
|
||||
+ dwmci_writel(host, DWMCI_PWREN, 0);
|
||||
|
||||
if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
|
||||
debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
|
||||
@ -1,214 +0,0 @@
|
||||
From 9f623c0e96fc7c3b5c9b7a81f0a3017c47033ec7 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sun, 19 Dec 2021 18:57:36 -0500
|
||||
Subject: [PATCH 06/11] rockchip: rk356x: add quartz64-a board
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
arch/arm/mach-rockchip/rk3568/Kconfig | 12 ++-
|
||||
board/pine64/quartz64-a-rk3566/Kconfig | 15 ++++
|
||||
board/pine64/quartz64-a-rk3566/Makefile | 4 +
|
||||
.../quartz64-a-rk3566/quartz64-a-rk3566.c | 1 +
|
||||
configs/quartz64-a-rk3566_defconfig | 77 +++++++++++++++++++
|
||||
include/configs/quartz64-a-rk3566.h | 14 ++++
|
||||
include/dt-bindings/power/rk3568-power.h | 32 ++++++++
|
||||
7 files changed, 154 insertions(+), 1 deletion(-)
|
||||
create mode 100644 board/pine64/quartz64-a-rk3566/Kconfig
|
||||
create mode 100644 board/pine64/quartz64-a-rk3566/Makefile
|
||||
create mode 100644 board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c
|
||||
create mode 100644 configs/quartz64-a-rk3566_defconfig
|
||||
create mode 100644 include/configs/quartz64-a-rk3566.h
|
||||
create mode 100644 include/dt-bindings/power/rk3568-power.h
|
||||
|
||||
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
|
||||
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
|
||||
@@ -1,11 +1,20 @@
|
||||
if ROCKCHIP_RK3568
|
||||
|
||||
+choice
|
||||
+ prompt "RK3568/RK3566 board select"
|
||||
+
|
||||
config TARGET_EVB_RK3568
|
||||
bool "RK3568 evaluation board"
|
||||
- select BOARD_LATE_INIT
|
||||
help
|
||||
RK3568 EVB is a evaluation board for Rockchp RK3568.
|
||||
|
||||
+config TARGET_QUARTZ64_A_RK3566
|
||||
+ bool "Quartz64 Model A RK3566 development board"
|
||||
+ help
|
||||
+ Quartz64 Model A RK3566 is a development board from Pine64.
|
||||
+
|
||||
+endchoice
|
||||
+
|
||||
config ROCKCHIP_BOOT_MODE_REG
|
||||
default 0xfdc20200
|
||||
|
||||
@@ -19,5 +28,6 @@ config SYS_MALLOC_F_LEN
|
||||
default 0x2000
|
||||
|
||||
source "board/rockchip/evb_rk3568/Kconfig"
|
||||
+source "board/pine64/quartz64-a-rk3566/Kconfig"
|
||||
|
||||
endif
|
||||
--- /dev/null
|
||||
+++ b/board/pine64/quartz64-a-rk3566/Kconfig
|
||||
@@ -0,0 +1,15 @@
|
||||
+if TARGET_QUARTZ64_A_RK3566
|
||||
+
|
||||
+config SYS_BOARD
|
||||
+ default "quartz64-a-rk3566"
|
||||
+
|
||||
+config SYS_VENDOR
|
||||
+ default "pine64"
|
||||
+
|
||||
+config SYS_CONFIG_NAME
|
||||
+ default "quartz64-a-rk3566"
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
+ def_bool y
|
||||
+
|
||||
+endif
|
||||
--- /dev/null
|
||||
+++ b/board/pine64/quartz64-a-rk3566/Makefile
|
||||
@@ -0,0 +1,4 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+obj-y += quartz64-a-rk3566.o
|
||||
--- /dev/null
|
||||
+++ b/board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c
|
||||
@@ -0,0 +1 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
--- /dev/null
|
||||
+++ b/configs/quartz64-a-rk3566_defconfig
|
||||
@@ -0,0 +1,77 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_QUARTZ64_A_RK3566=y
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_API=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_SYSRESET_PSCI=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
--- /dev/null
|
||||
+++ b/include/configs/quartz64-a-rk3566.h
|
||||
@@ -0,0 +1,14 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+
|
||||
+#ifndef __QUARTZ64_A_RK3566_H
|
||||
+#define __QUARTZ64_A_RK3566_H
|
||||
+
|
||||
+#include <configs/rk3568_common.h>
|
||||
+
|
||||
+#define CONFIG_SUPPORT_EMMC_RPMB
|
||||
+
|
||||
+#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
+ "stdout=serial,vidconsole\0" \
|
||||
+ "stderr=serial,vidconsole\0"
|
||||
+
|
||||
+#endif
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/power/rk3568-power.h
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 */
|
||||
+#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||
+#define __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||
+
|
||||
+/* VD_CORE */
|
||||
+#define RK3568_PD_CPU_0 0
|
||||
+#define RK3568_PD_CPU_1 1
|
||||
+#define RK3568_PD_CPU_2 2
|
||||
+#define RK3568_PD_CPU_3 3
|
||||
+#define RK3568_PD_CORE_ALIVE 4
|
||||
+
|
||||
+/* VD_PMU */
|
||||
+#define RK3568_PD_PMU 5
|
||||
+
|
||||
+/* VD_NPU */
|
||||
+#define RK3568_PD_NPU 6
|
||||
+
|
||||
+/* VD_GPU */
|
||||
+#define RK3568_PD_GPU 7
|
||||
+
|
||||
+/* VD_LOGIC */
|
||||
+#define RK3568_PD_VI 8
|
||||
+#define RK3568_PD_VO 9
|
||||
+#define RK3568_PD_RGA 10
|
||||
+#define RK3568_PD_VPU 11
|
||||
+#define RK3568_PD_CENTER 12
|
||||
+#define RK3568_PD_RKVDEC 13
|
||||
+#define RK3568_PD_RKVENC 14
|
||||
+#define RK3568_PD_PIPE 15
|
||||
+#define RK3568_PD_LOGIC_ALIVE 16
|
||||
+
|
||||
+#endif
|
||||
@ -1,755 +0,0 @@
|
||||
From 3a4d973a743bc76cc734db9616f9053f45fa922f Mon Sep 17 00:00:00 2001
|
||||
From: Jianqun Xu <jay.xu@rock-chips.com>
|
||||
Date: Thu, 28 May 2020 11:01:58 +0800
|
||||
Subject: [PATCH 07/11] gpio/rockchip: rk_gpio support v2 gpio controller
|
||||
|
||||
The v2 gpio controller add write enable bit for some register,
|
||||
such as data register, data direction register and so on.
|
||||
|
||||
This patch support v2 gpio controller by redefine the read and
|
||||
write operation functions.
|
||||
|
||||
Also adds support for the rk3568 pinctrl device.
|
||||
|
||||
Squash all fixes into this commit.
|
||||
|
||||
Change-Id: I2adbcca06a37c48e6f494b89833cd034ba0dae29
|
||||
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
arch/arm/include/asm/arch-rockchip/gpio.h | 36 ++
|
||||
drivers/gpio/Kconfig | 13 +
|
||||
drivers/gpio/rk_gpio.c | 89 ++++-
|
||||
drivers/pinctrl/rockchip/Makefile | 1 +
|
||||
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 360 ++++++++++++++++++
|
||||
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 11 +-
|
||||
drivers/pinctrl/rockchip/pinctrl-rockchip.h | 42 ++
|
||||
7 files changed, 530 insertions(+), 22 deletions(-)
|
||||
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
|
||||
|
||||
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
|
||||
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
|
||||
@@ -6,6 +6,7 @@
|
||||
#ifndef _ASM_ARCH_GPIO_H
|
||||
#define _ASM_ARCH_GPIO_H
|
||||
|
||||
+#ifndef CONFIG_ROCKCHIP_GPIO_V2
|
||||
struct rockchip_gpio_regs {
|
||||
u32 swport_dr;
|
||||
u32 swport_ddr;
|
||||
@@ -23,6 +24,41 @@ struct rockchip_gpio_regs {
|
||||
u32 ls_sync;
|
||||
};
|
||||
check_member(rockchip_gpio_regs, ls_sync, 0x60);
|
||||
+#else
|
||||
+struct rockchip_gpio_regs {
|
||||
+ u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */
|
||||
+ u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */
|
||||
+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
|
||||
+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
|
||||
+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
|
||||
+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
|
||||
+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
|
||||
+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
|
||||
+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
|
||||
+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
|
||||
+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
|
||||
+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
|
||||
+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
|
||||
+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
|
||||
+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
|
||||
+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
|
||||
+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
|
||||
+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
|
||||
+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
|
||||
+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
|
||||
+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */
|
||||
+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
|
||||
+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
|
||||
+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
|
||||
+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
|
||||
+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
|
||||
+ u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */
|
||||
+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
|
||||
+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
|
||||
+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
|
||||
+};
|
||||
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
|
||||
+#endif
|
||||
|
||||
enum gpio_pu_pd {
|
||||
GPIO_PULL_NORMAL = 0,
|
||||
--- a/drivers/gpio/Kconfig
|
||||
+++ b/drivers/gpio/Kconfig
|
||||
@@ -341,6 +341,19 @@ config ROCKCHIP_GPIO
|
||||
The GPIOs for a device are defined in the device tree with one node
|
||||
for each bank.
|
||||
|
||||
+config ROCKCHIP_GPIO_V2
|
||||
+ bool "Rockchip GPIO driver version 2.0"
|
||||
+ depends on ROCKCHIP_GPIO
|
||||
+ default n
|
||||
+ help
|
||||
+ Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
|
||||
+ a number of banks (different for each SoC type) each with 32 GPIOs.
|
||||
+ The GPIOs for a device are defined in the device tree with one node
|
||||
+ for each bank.
|
||||
+
|
||||
+ Support version 2.0 GPIO controller, which support write enable bits
|
||||
+ for some registers, such as dr, ddr.
|
||||
+
|
||||
config SANDBOX_GPIO
|
||||
bool "Enable sandbox GPIO driver"
|
||||
depends on SANDBOX && DM && DM_GPIO
|
||||
--- a/drivers/gpio/rk_gpio.c
|
||||
+++ b/drivers/gpio/rk_gpio.c
|
||||
@@ -2,12 +2,15 @@
|
||||
/*
|
||||
* (C) Copyright 2015 Google, Inc
|
||||
*
|
||||
- * (C) Copyright 2008-2014 Rockchip Electronics
|
||||
+ * (C) Copyright 2008-2020 Rockchip Electronics
|
||||
* Peter, Software Engineering, <superpeter.cai@gmail.com>.
|
||||
+ * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
+#include <dm/of_access.h>
|
||||
+#include <dm/device_compat.h>
|
||||
#include <syscon.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
@@ -17,12 +20,34 @@
|
||||
#include <dm/pinctrl.h>
|
||||
#include <dt-bindings/clock/rk3288-cru.h>
|
||||
|
||||
-enum {
|
||||
- ROCKCHIP_GPIOS_PER_BANK = 32,
|
||||
-};
|
||||
+#include "../pinctrl/rockchip/pinctrl-rockchip.h"
|
||||
|
||||
#define OFFSET_TO_BIT(bit) (1UL << (bit))
|
||||
|
||||
+#ifdef CONFIG_ROCKCHIP_GPIO_V2
|
||||
+#define REG_L(R) (R##_l)
|
||||
+#define REG_H(R) (R##_h)
|
||||
+#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
|
||||
+ ((readl(REG_H(REG)) & 0xFFFF) << 16))
|
||||
+#define WRITE_REG(REG, VAL) \
|
||||
+{\
|
||||
+ writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
|
||||
+ writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
|
||||
+}
|
||||
+#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
|
||||
+#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
|
||||
+#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
|
||||
+ (READ_REG(REG) & ~(MASK)) | (VAL))
|
||||
+
|
||||
+#else
|
||||
+#define READ_REG(REG) readl(REG)
|
||||
+#define WRITE_REG(REG, VAL) writel(VAL, REG)
|
||||
+#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
|
||||
+#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
|
||||
+#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
|
||||
+#endif
|
||||
+
|
||||
+
|
||||
struct rockchip_gpio_priv {
|
||||
struct rockchip_gpio_regs *regs;
|
||||
struct udevice *pinctrl;
|
||||
@@ -35,7 +60,7 @@ static int rockchip_gpio_direction_input
|
||||
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
|
||||
struct rockchip_gpio_regs *regs = priv->regs;
|
||||
|
||||
- clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset));
|
||||
+ CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset));
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -47,8 +72,8 @@ static int rockchip_gpio_direction_outpu
|
||||
struct rockchip_gpio_regs *regs = priv->regs;
|
||||
int mask = OFFSET_TO_BIT(offset);
|
||||
|
||||
- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
|
||||
- setbits_le32(®s->swport_ddr, mask);
|
||||
+ CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
|
||||
+ SETBITS_LE32(®s->swport_ddr, mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -68,7 +93,7 @@ static int rockchip_gpio_set_value(struc
|
||||
struct rockchip_gpio_regs *regs = priv->regs;
|
||||
int mask = OFFSET_TO_BIT(offset);
|
||||
|
||||
- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
|
||||
+ CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -86,8 +111,8 @@ static int rockchip_gpio_get_function(st
|
||||
ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
|
||||
if (ret)
|
||||
return ret;
|
||||
- is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset);
|
||||
-
|
||||
+ is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset);
|
||||
+
|
||||
return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
|
||||
#endif
|
||||
}
|
||||
@@ -142,19 +167,49 @@ static int rockchip_gpio_probe(struct ud
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
|
||||
- char *end;
|
||||
- int ret;
|
||||
+ struct rockchip_pinctrl_priv *pctrl_priv;
|
||||
+ struct rockchip_pin_bank *bank;
|
||||
+ char *end = NULL;
|
||||
+ static int gpio;
|
||||
+ int id = -1, ret;
|
||||
|
||||
priv->regs = dev_read_addr_ptr(dev);
|
||||
ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
|
||||
- if (ret)
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to get pinctrl device %d\n", ret);
|
||||
return ret;
|
||||
+ }
|
||||
+
|
||||
+ pctrl_priv = dev_get_priv(priv->pinctrl);
|
||||
+ if (!pctrl_priv) {
|
||||
+ dev_err(dev, "failed to get pinctrl priv\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
|
||||
- uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
|
||||
end = strrchr(dev->name, '@');
|
||||
- priv->bank = trailing_strtoln(dev->name, end);
|
||||
- priv->name[0] = 'A' + priv->bank;
|
||||
- uc_priv->bank_name = priv->name;
|
||||
+ if (end)
|
||||
+ id = trailing_strtoln(dev->name, end);
|
||||
+ else
|
||||
+ dev_read_alias_seq(dev, &id);
|
||||
+
|
||||
+ if (id < 0)
|
||||
+ id = gpio++;
|
||||
+
|
||||
+ if (id >= pctrl_priv->ctrl->nr_banks) {
|
||||
+ dev_err(dev, "bank id invalid\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ bank = &pctrl_priv->ctrl->pin_banks[id];
|
||||
+ if (bank->bank_num != id) {
|
||||
+ dev_err(dev, "bank id mismatch with pinctrl\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv->bank = bank->bank_num;
|
||||
+ uc_priv->gpio_count = bank->nr_pins;
|
||||
+ uc_priv->gpio_base = bank->pin_base;
|
||||
+ uc_priv->bank_name = bank->name;
|
||||
|
||||
return 0;
|
||||
}
|
||||
--- a/drivers/pinctrl/rockchip/Makefile
|
||||
+++ b/drivers/pinctrl/rockchip/Makefile
|
||||
@@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl
|
||||
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
|
||||
+obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
|
||||
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
|
||||
@@ -0,0 +1,360 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <dm.h>
|
||||
+#include <dm/pinctrl.h>
|
||||
+#include <regmap.h>
|
||||
+#include <syscon.h>
|
||||
+
|
||||
+#include "pinctrl-rockchip.h"
|
||||
+
|
||||
+static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */
|
||||
+ MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */
|
||||
+};
|
||||
+
|
||||
+static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
||||
+{
|
||||
+ struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
+ int iomux_num = (pin / 8);
|
||||
+ struct regmap *regmap;
|
||||
+ int reg, ret, mask;
|
||||
+ u8 bit;
|
||||
+ u32 data;
|
||||
+
|
||||
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
|
||||
+
|
||||
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
|
||||
+ regmap = priv->regmap_pmu;
|
||||
+ else
|
||||
+ regmap = priv->regmap_base;
|
||||
+
|
||||
+ reg = bank->iomux[iomux_num].offset;
|
||||
+ if ((pin % 8) >= 4)
|
||||
+ reg += 0x4;
|
||||
+ bit = (pin % 4) * 4;
|
||||
+ mask = 0xf;
|
||||
+
|
||||
+ data = (mask << (bit + 16));
|
||||
+ data |= (mux & mask) << bit;
|
||||
+ ret = regmap_write(regmap, reg, data);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+#define RK3568_PULL_PMU_OFFSET 0x20
|
||||
+#define RK3568_PULL_GRF_OFFSET 0x80
|
||||
+#define RK3568_PULL_BITS_PER_PIN 2
|
||||
+#define RK3568_PULL_PINS_PER_REG 8
|
||||
+#define RK3568_PULL_BANK_STRIDE 0x10
|
||||
+
|
||||
+static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
+ int pin_num, struct regmap **regmap,
|
||||
+ int *reg, u8 *bit)
|
||||
+{
|
||||
+ struct rockchip_pinctrl_priv *info = bank->priv;
|
||||
+
|
||||
+ if (bank->bank_num == 0) {
|
||||
+ *regmap = info->regmap_pmu;
|
||||
+ *reg = RK3568_PULL_PMU_OFFSET;
|
||||
+ *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
|
||||
+ } else {
|
||||
+ *regmap = info->regmap_base;
|
||||
+ *reg = RK3568_PULL_GRF_OFFSET;
|
||||
+ *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
|
||||
+ }
|
||||
+
|
||||
+ *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
|
||||
+ *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
|
||||
+ *bit *= RK3568_PULL_BITS_PER_PIN;
|
||||
+}
|
||||
+
|
||||
+#define RK3568_DRV_PMU_OFFSET 0x70
|
||||
+#define RK3568_DRV_GRF_OFFSET 0x200
|
||||
+#define RK3568_DRV_BITS_PER_PIN 8
|
||||
+#define RK3568_DRV_PINS_PER_REG 2
|
||||
+#define RK3568_DRV_BANK_STRIDE 0x40
|
||||
+
|
||||
+static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
+ int pin_num, struct regmap **regmap,
|
||||
+ int *reg, u8 *bit)
|
||||
+{
|
||||
+ struct rockchip_pinctrl_priv *info = bank->priv;
|
||||
+
|
||||
+ /* The first 32 pins of the first bank are located in PMU */
|
||||
+ if (bank->bank_num == 0) {
|
||||
+ *regmap = info->regmap_pmu;
|
||||
+ *reg = RK3568_DRV_PMU_OFFSET;
|
||||
+ } else {
|
||||
+ *regmap = info->regmap_base;
|
||||
+ *reg = RK3568_DRV_GRF_OFFSET;
|
||||
+ *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
|
||||
+ }
|
||||
+
|
||||
+ *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
|
||||
+ *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
|
||||
+ *bit *= RK3568_DRV_BITS_PER_PIN;
|
||||
+}
|
||||
+
|
||||
+#define RK3568_SCHMITT_BITS_PER_PIN 2
|
||||
+#define RK3568_SCHMITT_PINS_PER_REG 8
|
||||
+#define RK3568_SCHMITT_BANK_STRIDE 0x10
|
||||
+#define RK3568_SCHMITT_GRF_OFFSET 0xc0
|
||||
+#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
|
||||
+
|
||||
+static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
+ int pin_num, struct regmap **regmap,
|
||||
+ int *reg, u8 *bit)
|
||||
+{
|
||||
+ struct rockchip_pinctrl_priv *info = bank->priv;
|
||||
+
|
||||
+ if (bank->bank_num == 0) {
|
||||
+ *regmap = info->regmap_pmu;
|
||||
+ *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
|
||||
+ } else {
|
||||
+ *regmap = info->regmap_base;
|
||||
+ *reg = RK3568_SCHMITT_GRF_OFFSET;
|
||||
+ *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
|
||||
+ }
|
||||
+
|
||||
+ *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
|
||||
+ *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
|
||||
+ *bit *= RK3568_SCHMITT_BITS_PER_PIN;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3568_set_pull(struct rockchip_pin_bank *bank,
|
||||
+ int pin_num, int pull)
|
||||
+{
|
||||
+ struct regmap *regmap;
|
||||
+ int reg, ret;
|
||||
+ u8 bit, type;
|
||||
+ u32 data;
|
||||
+
|
||||
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
|
||||
+ return -ENOTSUPP;
|
||||
+
|
||||
+ rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
+ type = bank->pull_type[pin_num / 8];
|
||||
+ ret = rockchip_translate_pull_value(type, pull);
|
||||
+ if (ret < 0) {
|
||||
+ debug("unsupported pull setting %d\n", pull);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* enable the write to the equivalent lower bits */
|
||||
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
+
|
||||
+ data |= (ret << bit);
|
||||
+ ret = regmap_write(regmap, reg, data);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rk3568_set_drive(struct rockchip_pin_bank *bank,
|
||||
+ int pin_num, int strength)
|
||||
+{
|
||||
+ struct regmap *regmap;
|
||||
+ int reg;
|
||||
+ u32 data;
|
||||
+ u8 bit;
|
||||
+ int drv = (1 << (strength + 1)) - 1;
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
+
|
||||
+ /* enable the write to the equivalent lower bits */
|
||||
+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
+ data |= (drv << bit);
|
||||
+
|
||||
+ ret = regmap_write(regmap, reg, data);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (bank->bank_num == 1 && pin_num == 21)
|
||||
+ reg = 0x0840;
|
||||
+ else if (bank->bank_num == 2 && pin_num == 2)
|
||||
+ reg = 0x0844;
|
||||
+ else if (bank->bank_num == 2 && pin_num == 8)
|
||||
+ reg = 0x0848;
|
||||
+ else if (bank->bank_num == 3 && pin_num == 0)
|
||||
+ reg = 0x084c;
|
||||
+ else if (bank->bank_num == 3 && pin_num == 6)
|
||||
+ reg = 0x0850;
|
||||
+ else if (bank->bank_num == 4 && pin_num == 0)
|
||||
+ reg = 0x0854;
|
||||
+ else
|
||||
+ return 0;
|
||||
+
|
||||
+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
|
||||
+ data |= drv;
|
||||
+
|
||||
+ return regmap_write(regmap, reg, data);
|
||||
+}
|
||||
+
|
||||
+static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
|
||||
+ int pin_num, int enable)
|
||||
+{
|
||||
+ struct regmap *regmap;
|
||||
+ int reg;
|
||||
+ u32 data;
|
||||
+ u8 bit;
|
||||
+
|
||||
+ rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
+
|
||||
+ /* enable the write to the equivalent lower bits */
|
||||
+ data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
+ data |= (enable << bit);
|
||||
+
|
||||
+ return regmap_write(regmap, reg, data);
|
||||
+}
|
||||
+static struct rockchip_pin_bank rk3568_pin_banks[] = {
|
||||
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
|
||||
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT),
|
||||
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT),
|
||||
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT),
|
||||
+ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT,
|
||||
+ IOMUX_WIDTH_4BIT),
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
|
||||
+ .pin_banks = rk3568_pin_banks,
|
||||
+ .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
|
||||
+ .nr_pins = 160,
|
||||
+ .grf_mux_offset = 0x0,
|
||||
+ .pmu_mux_offset = 0x0,
|
||||
+ .iomux_routes = rk3568_mux_route_data,
|
||||
+ .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
|
||||
+ .set_mux = rk3568_set_mux,
|
||||
+ .set_pull = rk3568_set_pull,
|
||||
+ .set_drive = rk3568_set_drive,
|
||||
+ .set_schmitt = rk3568_set_schmitt,
|
||||
+};
|
||||
+
|
||||
+static const struct udevice_id rk3568_pinctrl_ids[] = {
|
||||
+ {
|
||||
+ .compatible = "rockchip,rk3568-pinctrl",
|
||||
+ .data = (ulong)&rk3568_pin_ctrl
|
||||
+ },
|
||||
+ { }
|
||||
+};
|
||||
+
|
||||
+U_BOOT_DRIVER(pinctrl_rk3568) = {
|
||||
+ .name = "rockchip_rk3568_pinctrl",
|
||||
+ .id = UCLASS_PINCTRL,
|
||||
+ .of_match = rk3568_pinctrl_ids,
|
||||
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
|
||||
+ .ops = &rockchip_pinctrl_ops,
|
||||
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
+ .bind = dm_scan_fdt_dev,
|
||||
+#endif
|
||||
+ .probe = rockchip_pinctrl_probe,
|
||||
+};
|
||||
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
|
||||
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
|
||||
@@ -400,7 +400,7 @@ static int rockchip_pinctrl_set_state(st
|
||||
int prop_len, param;
|
||||
const u32 *data;
|
||||
ofnode node;
|
||||
-#ifdef CONFIG_OF_LIVE
|
||||
+#if CONFIG_IS_ENABLED(OF_LIVE)
|
||||
const struct device_node *np;
|
||||
struct property *pp;
|
||||
#else
|
||||
@@ -440,7 +440,7 @@ static int rockchip_pinctrl_set_state(st
|
||||
node = ofnode_get_by_phandle(conf);
|
||||
if (!ofnode_valid(node))
|
||||
return -ENODEV;
|
||||
-#ifdef CONFIG_OF_LIVE
|
||||
+#if CONFIG_IS_ENABLED(OF_LIVE)
|
||||
np = ofnode_to_np(node);
|
||||
for (pp = np->properties; pp; pp = pp->next) {
|
||||
prop_name = pp->name;
|
||||
@@ -515,13 +515,14 @@ static struct rockchip_pin_ctrl *rockchi
|
||||
|
||||
/* preset iomux offset value, set new start value */
|
||||
if (iom->offset >= 0) {
|
||||
- if (iom->type & IOMUX_SOURCE_PMU)
|
||||
+ if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
|
||||
pmu_offs = iom->offset;
|
||||
else
|
||||
grf_offs = iom->offset;
|
||||
} else { /* set current iomux offset */
|
||||
- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
|
||||
- pmu_offs : grf_offs;
|
||||
+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
|
||||
+ (iom->type & IOMUX_L_SOURCE_PMU)) ?
|
||||
+ pmu_offs : grf_offs;
|
||||
}
|
||||
|
||||
/* preset drv offset value, set new start value */
|
||||
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
|
||||
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
|
||||
@@ -6,9 +6,13 @@
|
||||
#ifndef __DRIVERS_PINCTRL_ROCKCHIP_H
|
||||
#define __DRIVERS_PINCTRL_ROCKCHIP_H
|
||||
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
+#define RK_GENMASK_VAL(h, l, v) \
|
||||
+ (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
|
||||
+
|
||||
/**
|
||||
* Encode variants of iomux registers into a type variable
|
||||
*/
|
||||
@@ -18,6 +22,8 @@
|
||||
#define IOMUX_UNROUTED BIT(3)
|
||||
#define IOMUX_WIDTH_3BIT BIT(4)
|
||||
#define IOMUX_8WIDTH_2BIT BIT(5)
|
||||
+#define IOMUX_WRITABLE_32BIT BIT(6)
|
||||
+#define IOMUX_L_SOURCE_PMU BIT(7)
|
||||
|
||||
/**
|
||||
* Defined some common pins constants
|
||||
@@ -63,6 +69,21 @@ enum rockchip_pin_pull_type {
|
||||
};
|
||||
|
||||
/**
|
||||
+ * enum mux route register type, should be invalid/default/topgrf/pmugrf.
|
||||
+ * INVALID: means do not need to set mux route
|
||||
+ * DEFAULT: means same regmap as pin iomux
|
||||
+ * TOPGRF: means mux route setting in topgrf
|
||||
+ * PMUGRF: means mux route setting in pmugrf
|
||||
+ */
|
||||
+enum rockchip_pin_route_type {
|
||||
+ ROUTE_TYPE_DEFAULT = 0,
|
||||
+ ROUTE_TYPE_TOPGRF = 1,
|
||||
+ ROUTE_TYPE_PMUGRF = 2,
|
||||
+
|
||||
+ ROUTE_TYPE_INVALID = -1,
|
||||
+};
|
||||
+
|
||||
+/**
|
||||
* @drv_type: drive strength variant using rockchip_perpin_drv_type
|
||||
* @offset: if initialized to -1 it will be autocalculated, by specifying
|
||||
* an initial offset value the relevant source offset can be reset
|
||||
@@ -220,6 +241,25 @@ struct rockchip_pin_bank {
|
||||
.pull_type[3] = pull3, \
|
||||
}
|
||||
|
||||
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
|
||||
+ { \
|
||||
+ .bank_num = ID, \
|
||||
+ .pin = PIN, \
|
||||
+ .func = FUNC, \
|
||||
+ .route_offset = REG, \
|
||||
+ .route_val = VAL, \
|
||||
+ .route_type = FLAG, \
|
||||
+ }
|
||||
+
|
||||
+#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \
|
||||
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
|
||||
+
|
||||
+#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \
|
||||
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
|
||||
+
|
||||
+#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \
|
||||
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
|
||||
+
|
||||
/**
|
||||
* struct rockchip_mux_recalced_data: recalculate a pin iomux data.
|
||||
* @num: bank number.
|
||||
@@ -241,6 +281,7 @@ struct rockchip_mux_recalced_data {
|
||||
* @bank_num: bank number.
|
||||
* @pin: index at register or used to calc index.
|
||||
* @func: the min pin.
|
||||
+ * @route_type: the register type.
|
||||
* @route_offset: the max pin.
|
||||
* @route_val: the register offset.
|
||||
*/
|
||||
@@ -248,6 +289,7 @@ struct rockchip_mux_route_data {
|
||||
u8 bank_num;
|
||||
u8 pin;
|
||||
u8 func;
|
||||
+ enum rockchip_pin_route_type route_type : 8;
|
||||
u32 route_offset;
|
||||
u32 route_val;
|
||||
};
|
||||
@ -1,22 +0,0 @@
|
||||
From 16cc17fc2cf2f308f5ac20b829d427114c6e59fa Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Mon, 20 Dec 2021 08:50:48 -0500
|
||||
Subject: [PATCH 08/11] rockchip: allow sdmmc at full speed
|
||||
|
||||
Adding pinctrl and gpio support fixed quartz64-a sdmmc.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
|
||||
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
|
||||
@@ -13,7 +13,6 @@
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
- max-frequency = <400000>;
|
||||
bus-width = <4>;
|
||||
u-boot,dm-spl;
|
||||
u-boot,spl-fifo-mode;
|
||||
@ -1,25 +0,0 @@
|
||||
From d3b3e9c1045e9fa0aff987a036b30cf380809e35 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Mon, 20 Dec 2021 10:11:52 -0500
|
||||
Subject: [PATCH 09/11] rockchip: defconfig: add gpio-v2 to quartz64
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
configs/quartz64-a-rk3566_defconfig | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/configs/quartz64-a-rk3566_defconfig
|
||||
+++ b/configs/quartz64-a-rk3566_defconfig
|
||||
@@ -42,10 +42,12 @@ CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
@ -1,97 +0,0 @@
|
||||
From 981df845d960a9078893dad88e1dd82dfcb4a148 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 22 Dec 2021 19:40:32 -0500
|
||||
Subject: [PATCH 10/11] rockchip: rk356x: enable usb2 support on quartz64-a
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 22 ++++++++++++++++++++++
|
||||
configs/quartz64-a-rk3566_defconfig | 17 +++++++++++++++++
|
||||
include/configs/quartz64-a-rk3566.h | 3 +++
|
||||
3 files changed, 42 insertions(+)
|
||||
|
||||
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
|
||||
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
|
||||
@@ -12,12 +12,34 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
u-boot,dm-spl;
|
||||
u-boot,spl-fifo-mode;
|
||||
};
|
||||
|
||||
+&usb_host0_ehci {
|
||||
+ vbus-supply = <&vcc5v0_usb20_host>;
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ vbus-supply = <&vcc5v0_usb20_host>;
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ vbus-supply = <&vcc5v0_usb20_host>;
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ vbus-supply = <&vcc5v0_usb20_host>;
|
||||
+};
|
||||
+
|
||||
&uart2 {
|
||||
clock-frequency = <24000000>;
|
||||
u-boot,dm-spl;
|
||||
--- a/configs/quartz64-a-rk3566_defconfig
|
||||
+++ b/configs/quartz64-a-rk3566_defconfig
|
||||
@@ -22,6 +22,7 @@ CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
@@ -35,6 +36,7 @@ CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
@@ -76,4 +78,19 @@ CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
--- a/include/configs/quartz64-a-rk3566.h
|
||||
+++ b/include/configs/quartz64-a-rk3566.h
|
||||
@@ -11,4 +11,7 @@
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
|
||||
+#define CONFIG_USB_OHCI_NEW
|
||||
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
+
|
||||
#endif
|
||||
@ -1,173 +0,0 @@
|
||||
From ea6da572fe3cee637319f1e7e588c059622c815e Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 22 Dec 2021 19:52:38 -0500
|
||||
Subject: [PATCH 11/11] rockchip: rk356x: attempt to fix ram detection
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++++++++++++++++++++++++
|
||||
arch/arm/mach-rockchip/sdram.c | 31 ++++++++++++++------------
|
||||
common/board_f.c | 7 ++++++
|
||||
configs/quartz64-a-rk3566_defconfig | 1 +
|
||||
include/configs/rk3568_common.h | 5 +++++
|
||||
5 files changed, 59 insertions(+), 14 deletions(-)
|
||||
|
||||
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
|
||||
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
+#include <fdt_support.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-rockchip/bootrom.h>
|
||||
@@ -135,3 +136,31 @@ int arch_cpu_init(void)
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
+
|
||||
+#ifdef CONFIG_OF_SYSTEM_SETUP
|
||||
+int ft_system_setup(void *blob, struct bd_info *bd)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int areas = 1;
|
||||
+ u64 start[2], size[2];
|
||||
+
|
||||
+ /* Reserve the io address space. */
|
||||
+ if (gd->ram_top > SDRAM_UPPER_ADDR_MIN) {
|
||||
+ start[0] = gd->bd->bi_dram[0].start;
|
||||
+ size[0] = SDRAM_LOWER_ADDR_MAX - gd->bd->bi_dram[0].start;
|
||||
+
|
||||
+ /* Add the upper 4GB address space */
|
||||
+ start[1] = SDRAM_UPPER_ADDR_MIN;
|
||||
+ size[1] = gd->ram_top - SDRAM_UPPER_ADDR_MIN;
|
||||
+ areas = 2;
|
||||
+
|
||||
+ ret = fdt_set_usable_memory(blob, start, size, areas);
|
||||
+ if (ret) {
|
||||
+ printf("Cannot set usable memory\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+};
|
||||
+#endif
|
||||
--- a/arch/arm/mach-rockchip/sdram.c
|
||||
+++ b/arch/arm/mach-rockchip/sdram.c
|
||||
@@ -3,6 +3,8 @@
|
||||
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
+#define DEBUG
|
||||
+
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <init.h>
|
||||
@@ -98,8 +100,7 @@ size_t rockchip_sdram_size(phys_addr_t r
|
||||
SYS_REG_COL_MASK);
|
||||
cs1_col = cs0_col;
|
||||
bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
|
||||
- if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
|
||||
- SYS_REG_VERSION_MASK) == 0x2) {
|
||||
+ if ((sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) >= 0x2) {
|
||||
cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
|
||||
SYS_REG_CS1_COL_MASK);
|
||||
if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
|
||||
@@ -136,7 +137,7 @@ size_t rockchip_sdram_size(phys_addr_t r
|
||||
SYS_REG_BW_MASK));
|
||||
row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
|
||||
SYS_REG_ROW_3_4_MASK;
|
||||
- if (dram_type == DDR4) {
|
||||
+ if ((dram_type == DDR4) && (sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) != 0x3){
|
||||
dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
|
||||
SYS_REG_DBW_MASK;
|
||||
bg = (dbw == 2) ? 2 : 1;
|
||||
@@ -150,15 +151,11 @@ size_t rockchip_sdram_size(phys_addr_t r
|
||||
chipsize_mb = chipsize_mb * 3 / 4;
|
||||
size_mb += chipsize_mb;
|
||||
if (rank > 1)
|
||||
- debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
|
||||
- cs1_row %d bw %d row_3_4 %d\n",
|
||||
- rank, cs0_col, cs1_col, bk, cs0_row,
|
||||
- cs1_row, bw, row_3_4);
|
||||
+ debug("rank=%d cs0_col=%d cs1_col=%d bk=%d cs0_row=%d cs1_row=%d bg=%d bw=%d row_3_4=%d\n",
|
||||
+ rank, cs0_col, cs1_col, bk, cs0_row, cs1_row, bg, bw, row_3_4);
|
||||
else
|
||||
- debug("rank %d cs0_col %d bk %d cs0_row %d\
|
||||
- bw %d row_3_4 %d\n",
|
||||
- rank, cs0_col, bk, cs0_row,
|
||||
- bw, row_3_4);
|
||||
+ debug("rank %d cs0_col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
|
||||
+ rank, cs0_col, bk, cs0_row, bw, row_3_4);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -176,9 +173,11 @@ size_t rockchip_sdram_size(phys_addr_t r
|
||||
* 2. update board_get_usable_ram_top() and dram_init_banksize()
|
||||
* to reserve memory for peripheral space after previous update.
|
||||
*/
|
||||
+
|
||||
+#ifndef __aarch64__
|
||||
if (size_mb > (SDRAM_MAX_SIZE >> 20))
|
||||
size_mb = (SDRAM_MAX_SIZE >> 20);
|
||||
-
|
||||
+#endif
|
||||
return (size_t)size_mb << 20;
|
||||
}
|
||||
|
||||
@@ -208,6 +207,10 @@ int dram_init(void)
|
||||
ulong board_get_usable_ram_top(ulong total_size)
|
||||
{
|
||||
unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
|
||||
-
|
||||
- return (gd->ram_top > top) ? top : gd->ram_top;
|
||||
+#ifdef SDRAM_UPPER_ADDR_MIN
|
||||
+ if (gd->ram_top > SDRAM_UPPER_ADDR_MIN)
|
||||
+ return gd->ram_top;
|
||||
+ else
|
||||
+#endif
|
||||
+ return (gd->ram_top > top) ? top : gd->ram_top;
|
||||
}
|
||||
--- a/common/board_f.c
|
||||
+++ b/common/board_f.c
|
||||
@@ -345,7 +345,14 @@ static int setup_dest_addr(void)
|
||||
#endif
|
||||
gd->ram_top = gd->ram_base + get_effective_memsize();
|
||||
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
|
||||
+#ifdef SDRAM_LOWER_ADDR_MAX
|
||||
+ if (gd->ram_top > SDRAM_LOWER_ADDR_MAX)
|
||||
+ gd->relocaddr = SDRAM_LOWER_ADDR_MAX;
|
||||
+ else
|
||||
+ gd->relocaddr = gd->ram_top;
|
||||
+#else
|
||||
gd->relocaddr = gd->ram_top;
|
||||
+#endif
|
||||
debug("Ram top: %08lX\n", (ulong)gd->ram_top);
|
||||
#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
|
||||
/*
|
||||
--- a/configs/quartz64-a-rk3566_defconfig
|
||||
+++ b/configs/quartz64-a-rk3566_defconfig
|
||||
@@ -21,6 +21,7 @@ CONFIG_API=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
|
||||
# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
--- a/include/configs/rk3568_common.h
|
||||
+++ b/include/configs/rk3568_common.h
|
||||
@@ -24,6 +24,11 @@
|
||||
#define CONFIG_SYS_SDRAM_BASE 0
|
||||
#define SDRAM_MAX_SIZE 0xf0000000
|
||||
|
||||
+#ifdef CONFIG_OF_SYSTEM_SETUP
|
||||
+#define SDRAM_LOWER_ADDR_MAX 0xf0000000
|
||||
+#define SDRAM_UPPER_ADDR_MIN 0x100000000
|
||||
+#endif
|
||||
+
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define ENV_MEM_LAYOUT_SETTINGS \
|
||||
"scriptaddr=0x00c00000\0" \
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,795 +0,0 @@
|
||||
From 89d609d74e4ef84e0e3d399d8763b268b60302fc Mon Sep 17 00:00:00 2001
|
||||
From: Marty Jones <mj8263788@gmail.com>
|
||||
Date: Sat, 28 May 2022 20:19:38 -0400
|
||||
Subject: [PATCH] rockchip: rk356x: add bpi r2 pro board
|
||||
|
||||
Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
---
|
||||
arch/arm/dts/Makefile | 1 +
|
||||
arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi | 47 ++
|
||||
arch/arm/dts/rk3568-bpi-r2-pro.dts | 532 ++++++++++++++++++
|
||||
arch/arm/mach-rockchip/rk3568/Kconfig | 6 +
|
||||
board/rockchip/bpi-r2-pro-rk3568/Kconfig | 15 +
|
||||
board/rockchip/bpi-r2-pro-rk3568/Makefile | 7 +
|
||||
.../bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c | 4 +
|
||||
configs/bpi-r2-pro-rk3568_defconfig | 97 ++++
|
||||
include/configs/bpi-r2-pro-rk3568.h | 15 +
|
||||
9 files changed, 724 insertions(+)
|
||||
create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
|
||||
create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro.dts
|
||||
create mode 100644 board/rockchip/bpi-r2-pro-rk3568/Kconfig
|
||||
create mode 100644 board/rockchip/bpi-r2-pro-rk3568/Makefile
|
||||
create mode 100644 board/rockchip/bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c
|
||||
create mode 100644 configs/bpi-r2-pro-rk3568_defconfig
|
||||
create mode 100644 include/configs/bpi-r2-pro-rk3568.h
|
||||
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -164,6 +164,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
rk3399pro-rock-pi-n10.dtb
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
+ rk3568-bpi-r2-pro.dtb \
|
||||
rk3568-evb.dtb \
|
||||
rk3566-quartz64-a.dtb
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
|
||||
@@ -0,0 +1,47 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
+ */
|
||||
+
|
||||
+#include "rk3568-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &uart2;
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ u-boot,dm-spl;
|
||||
+ u-boot,spl-fifo-mode;
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ vbus-supply = <&vcc5v0_usb_host>;
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ vbus-supply = <&vcc5v0_usb_host>;
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ vbus-supply = <&vcc5v0_usb_host>;
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ vbus-supply = <&vcc5v0_usb_host>;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ clock-frequency = <24000000>;
|
||||
+ u-boot,dm-spl;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts
|
||||
@@ -0,0 +1,532 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Author: Frank Wunderlich <frank-w@public-files.de>
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
|
||||
+ compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac0;
|
||||
+ ethernet1 = &gmac1;
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&blue_led_pin &green_led_pin>;
|
||||
+
|
||||
+ blue_led: led-0 {
|
||||
+ color = <LED_COLOR_ID_BLUE>;
|
||||
+ default-state = "off";
|
||||
+ function = LED_FUNCTION_STATUS;
|
||||
+ gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ green_led: led-1 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ default-state = "on";
|
||||
+ function = LED_FUNCTION_POWER;
|
||||
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ dc_12v: dc-12v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "dc_12v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <12000000>;
|
||||
+ regulator-max-microvolt = <12000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb: vcc5v0_usb {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
+ regulator-name = "vcc5v0_usb_host";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
+ regulator-name = "vcc5v0_usb_otg";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0 {
|
||||
+ /* used for USB3 */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ /* used for USB3 */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy2 {
|
||||
+ /* used for SATA */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac0 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-mode = "rgmii";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac0_miim
|
||||
+ &gmac0_tx_bus2
|
||||
+ &gmac0_rx_bus2
|
||||
+ &gmac0_rgmii_clk
|
||||
+ &gmac0_rgmii_bus>;
|
||||
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 20ms, 100ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 20000 100000>;
|
||||
+ tx_delay = <0x4f>;
|
||||
+ rx_delay = <0x0f>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ fixed-link {
|
||||
+ speed = <1000>;
|
||||
+ full-duplex;
|
||||
+ pause;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m1_miim
|
||||
+ &gmac1m1_tx_bus2
|
||||
+ &gmac1m1_rx_bus2
|
||||
+ &gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_rgmii_bus>;
|
||||
+
|
||||
+ snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 20ms, 100ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 20000 100000>;
|
||||
+
|
||||
+ tx_delay = <0x3c>;
|
||||
+ rx_delay = <0x2f>;
|
||||
+
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+ regulator-always-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c5 {
|
||||
+ /* pin 3 (SDA) + 4 (SCL) of header con2 */
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0x0>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ leds {
|
||||
+ blue_led_pin: blue-led-pin {
|
||||
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ green_led_pin: green-led-pin {
|
||||
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic_int {
|
||||
+ rockchip,pins =
|
||||
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_3v3>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm8 {
|
||||
+ /* fan 5v - gnd - pwm */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm10 {
|
||||
+ /* pin 7 of header con2 */
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&pwm11 {
|
||||
+ /* pin 15 of header con2 */
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+
|
||||
+&pwm13 {
|
||||
+ /* pin 24 of header con2 */
|
||||
+ /* shared with uart9 */
|
||||
+ pinctrl-0 = <&pwm13m1_pins>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sata2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
+ disable-wp;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ /* debug-uart */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart7 {
|
||||
+ /* pin 11 (TX) + 13 (RX) of header con2 */
|
||||
+ pinctrl-0 = <&uart7m1_xfer>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
|
||||
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
|
||||
@@ -3,6 +3,11 @@ if ROCKCHIP_RK3568
|
||||
choice
|
||||
prompt "RK3568/RK3566 board select"
|
||||
|
||||
+config TARGET_BPI_R2_PRO_RK3568
|
||||
+ bool "Banana Pi R2 Pro RK3566 development board"
|
||||
+ help
|
||||
+ Banana Pi R2 Pro is a development board Rockchp RK3568.
|
||||
+
|
||||
config TARGET_EVB_RK3568
|
||||
bool "RK3568 evaluation board"
|
||||
help
|
||||
@@ -27,6 +32,7 @@ config SYS_SOC
|
||||
config SYS_MALLOC_F_LEN
|
||||
default 0x2000
|
||||
|
||||
+source "board/rockchip/bpi-r2-pro-rk3568/Kconfig"
|
||||
source "board/rockchip/evb_rk3568/Kconfig"
|
||||
source "board/pine64/quartz64-a-rk3566/Kconfig"
|
||||
|
||||
--- /dev/null
|
||||
+++ b/board/rockchip/bpi-r2-pro-rk3568/Kconfig
|
||||
@@ -0,0 +1,15 @@
|
||||
+if TARGET_BPI_R2_PRO_RK3568
|
||||
+
|
||||
+config SYS_BOARD
|
||||
+ default "bpi-r2-pro-rk3568"
|
||||
+
|
||||
+config SYS_VENDOR
|
||||
+ default "rockchip"
|
||||
+
|
||||
+config SYS_CONFIG_NAME
|
||||
+ default "bpi-r2-pro-rk3568"
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
+ def_bool y
|
||||
+
|
||||
+endif
|
||||
--- /dev/null
|
||||
+++ b/board/rockchip/bpi-r2-pro-rk3568/Makefile
|
||||
@@ -0,0 +1,7 @@
|
||||
+#
|
||||
+# (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+obj-y += bpi-r2-pro-rk3568.o
|
||||
--- /dev/null
|
||||
+++ b/board/rockchip/bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c
|
||||
@@ -0,0 +1,4 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
+ */
|
||||
--- /dev/null
|
||||
+++ b/configs/bpi-r2-pro-rk3568_defconfig
|
||||
@@ -0,0 +1,97 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_BPI_R2_PRO_RK3568=y
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_API=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_SYSRESET_PSCI=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
--- /dev/null
|
||||
+++ b/include/configs/bpi-r2-pro-rk3568.h
|
||||
@@ -0,0 +1,15 @@
|
||||
+#ifndef __BPI_R2_PRO_RK3568_H
|
||||
+#define __BPI_R2_PRO_RK3568_H
|
||||
+
|
||||
+#include <configs/rk3568_common.h>
|
||||
+
|
||||
+#define CONFIG_SUPPORT_EMMC_RPMB
|
||||
+
|
||||
+#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
+ "stdout=serial,vidconsole\0" \
|
||||
+ "stderr=serial,vidconsole\0"
|
||||
+
|
||||
+#define CONFIG_USB_OHCI_NEW
|
||||
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
+
|
||||
+#endif
|
||||
@ -1,690 +0,0 @@
|
||||
From 443eb96a82563a3b38a3c9548853a5a266dfd072 Mon Sep 17 00:00:00 2001
|
||||
From: Marty Jones <mj8263788@gmail.com>
|
||||
Date: Sun, 29 May 2022 06:09:59 -0400
|
||||
Subject: [PATCH] uboot: add Radxa ROCK 3A board
|
||||
|
||||
Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
---
|
||||
arch/arm/dts/Makefile | 3 +-
|
||||
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 25 +
|
||||
arch/arm/dts/rk3568-rock-3a.dts | 525 ++++++++++++++++++++
|
||||
arch/arm/mach-rockchip/rk3568/Kconfig | 6 +
|
||||
board/radxa/rock-3a-rk3568/Kconfig | 15 +
|
||||
board/radxa/rock-3a-rk3568/Makefile | 4 +
|
||||
board/radxa/rock-3a-rk3568/rock-3a-rk3568.c | 1 +
|
||||
configs/rock-3a-rk3568_defconfig | 97 ++++
|
||||
include/configs/rock-3a-rk3568.h | 17 +
|
||||
9 files changed, 692 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
|
||||
create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
|
||||
create mode 100644 configs/rock-3a-rk3568_defconfig
|
||||
create mode 100644 include/configs/rock-3a-rk3568.h
|
||||
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -166,7 +166,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
rk3568-bpi-r2-pro.dtb \
|
||||
rk3568-evb.dtb \
|
||||
- rk3566-quartz64-a.dtb
|
||||
+ rk3566-quartz64-a.dtb \
|
||||
+ rk3568-rock-3a.dtb
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
|
||||
rv1108-elgin-r1.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
|
||||
@@ -0,0 +1,24 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
+ */
|
||||
+
|
||||
+#include "rk3568-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &uart2;
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ u-boot,spl-fifo-mode;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ u-boot,dm-spl;
|
||||
+ clock-frequency = <24000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-rock-3a.dts
|
||||
@@ -0,0 +1,525 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa ROCK3 Model A";
|
||||
+ compatible = "radxa,rock3a", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac1;
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led_user: led-0 {
|
||||
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ function = LED_FUNCTION_HEARTBEAT;
|
||||
+ color = <LED_COLOR_ID_BLUE>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&led_user_en>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,name = "Analog RK809";
|
||||
+ simple-audio-card,mclk-fs = <256>;
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s1_8ch>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&rk809>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc12v_dcin: vcc12v-dcin {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc12v_dcin";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc12v_dcin>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc12v_dcin>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb: vcc5v0-usb {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc12v_dcin>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
+ regulator-name = "vcc5v0_usb_host";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_hub_en>;
|
||||
+ regulator-name = "vcc5v0_usb_hub";
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
+ regulator-name = "vcc5v0_usb_otg";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
+ assigned-clock-rates = <0>, <125000000>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m1_miim
|
||||
+ &gmac1m1_tx_bus2
|
||||
+ &gmac1m1_rx_bus2
|
||||
+ &gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_rgmii_bus>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-names = "mclk";
|
||||
+ clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ codec {
|
||||
+ mic-in-differential;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s1_8ch {
|
||||
+ rockchip,trcm-sync-tx-only;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0x0>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <ð_phy_rst>;
|
||||
+ reset-assert-us = <20000>;
|
||||
+ reset-deassert-us = <100000>;
|
||||
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ ethernet {
|
||||
+ eth_phy_rst: eth_phy_rst {
|
||||
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ led_user_en: led_user_en {
|
||||
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic_int {
|
||||
+ rockchip,pins =
|
||||
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
|
||||
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio2-supply = <&vcc_1v8>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ vmmc-supply = <&vcc_3v3>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
+ disable-wp;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/rock-3a-rk3568_defconfig
|
||||
@@ -0,0 +1,98 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_API=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_SYSRESET_PSCI=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
@ -26,11 +26,11 @@ Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
rk3568-bpi-r2-pro.dtb \
|
||||
rk3568-evb.dtb \
|
||||
+ rk3568-nanopi-r5s.dtb \
|
||||
rk3566-quartz64-a.dtb \
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
rk3568-rock-3a.dtb
|
||||
|
||||
--- /dev/null
|
||||
@ -41,7 +41,7 @@ Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
+ */
|
||||
+
|
||||
+#include "rk3568-u-boot.dtsi"
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
@ -73,175 +73,97 @@ Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
+ model = "FriendlyElec NanoPi R5S";
|
||||
+ compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
|
||||
+};
|
||||
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
|
||||
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
|
||||
@@ -13,6 +13,11 @@ config TARGET_EVB_RK3568
|
||||
help
|
||||
RK3568 EVB is a evaluation board for Rockchp RK3568.
|
||||
|
||||
+config TARGET_NANOPI_R5S_RK3568
|
||||
+ bool "NanoPi R5S board"
|
||||
+ help
|
||||
+ NanoPi R5S FriendlyElec is a board for Rockchp RK3568.
|
||||
+
|
||||
config TARGET_QUARTZ64_A_RK3566
|
||||
bool "Quartz64 Model A RK3566 development board"
|
||||
help
|
||||
@@ -39,6 +44,7 @@ config SYS_MALLOC_F_LEN
|
||||
|
||||
source "board/rockchip/bpi-r2-pro-rk3568/Kconfig"
|
||||
source "board/rockchip/evb_rk3568/Kconfig"
|
||||
+source "board/friendlyelec/nanopi-r5s-rk3568/Kconfig"
|
||||
source "board/pine64/quartz64-a-rk3566/Kconfig"
|
||||
source "board/radxa/rock-3a-rk3568/Kconfig"
|
||||
|
||||
--- /dev/null
|
||||
+++ b/board/friendlyelec/nanopi-r5s-rk3568/Kconfig
|
||||
@@ -0,0 +1,15 @@
|
||||
+if TARGET_NANOPI_R5S_RK3568
|
||||
+
|
||||
+config SYS_BOARD
|
||||
+ default "nanopi-r5s-rk3568"
|
||||
+
|
||||
+config SYS_VENDOR
|
||||
+ default "friendlyelec"
|
||||
+
|
||||
+config SYS_CONFIG_NAME
|
||||
+ default "nanopi-r5s-rk3568"
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
+ def_bool y
|
||||
+
|
||||
+endif
|
||||
--- /dev/null
|
||||
+++ b/board/friendlyelec/nanopi-r5s-rk3568/Makefile
|
||||
@@ -0,0 +1,4 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+obj-y += nanopi-r5s-rk3568.o
|
||||
--- /dev/null
|
||||
+++ b/board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c
|
||||
@@ -0,0 +1,4 @@
|
||||
+ // SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ *
|
||||
+ */
|
||||
--- /dev/null
|
||||
+++ b/configs/nanopi-r5s-rk3568_defconfig
|
||||
@@ -0,0 +1,98 @@
|
||||
@@ -0,0 +1,91 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_NANOPI_R5S_RK3568=y
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
|
||||
+CONFIG_API=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_SYSRESET_PSCI=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
--- /dev/null
|
||||
+++ b/include/configs/nanopi-r5s-rk3568.h
|
||||
@@ -0,0 +1,14 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+
|
||||
+#ifndef __NANOPI_R5S_RK3568_H
|
||||
+#define __NANOPI_R5S_RK3568_H
|
||||
+
|
||||
+#include <configs/rk3568_common.h>
|
||||
+
|
||||
+#define CONFIG_SUPPORT_EMMC_RPMB
|
||||
+
|
||||
+#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
+ "stdout=serial,vidconsole\0" \
|
||||
+ "stderr=serial,vidconsole\0"
|
||||
+
|
||||
+#endif
|
||||
|
||||
@ -1,42 +0,0 @@
|
||||
From c9a8a3b5fb4ae210c5a5acb1538b0e961c5d1421 Mon Sep 17 00:00:00 2001
|
||||
From: Tang Yun ping <typ@rock-chips.com>
|
||||
Date: Wed, 23 Jun 2021 19:48:59 +0800
|
||||
Subject: [PATCH] rk356x: ddr: fix dbw detect bug
|
||||
|
||||
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
|
||||
Change-Id: Ifadad00853eb0ad43a68f12335fd243e6a1bc04b
|
||||
---
|
||||
drivers/ram/rockchip/sdram_common.c | 12 ++++++------
|
||||
1 file changed, 6 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/ram/rockchip/sdram_common.c
|
||||
+++ b/drivers/ram/rockchip/sdram_common.c
|
||||
@@ -299,22 +299,22 @@ int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type)
|
||||
bw = cap_info->bw;
|
||||
cs_cap = (1 << (row + col + bk + bw - 20));
|
||||
if (bw == 2) {
|
||||
- if (cs_cap <= 0x2000000) /* 256Mb */
|
||||
+ if (cs_cap <= 0x20) /* 256Mb */
|
||||
die_bw_0 = (col < 9) ? 2 : 1;
|
||||
- else if (cs_cap <= 0x10000000) /* 2Gb */
|
||||
+ else if (cs_cap <= 0x100) /* 2Gb */
|
||||
die_bw_0 = (col < 10) ? 2 : 1;
|
||||
- else if (cs_cap <= 0x40000000) /* 8Gb */
|
||||
+ else if (cs_cap <= 0x400) /* 8Gb */
|
||||
die_bw_0 = (col < 11) ? 2 : 1;
|
||||
else
|
||||
die_bw_0 = (col < 12) ? 2 : 1;
|
||||
if (cs > 1) {
|
||||
row = cap_info->cs1_row;
|
||||
cs_cap = (1 << (row + col + bk + bw - 20));
|
||||
- if (cs_cap <= 0x2000000) /* 256Mb */
|
||||
+ if (cs_cap <= 0x20) /* 256Mb */
|
||||
die_bw_0 = (col < 9) ? 2 : 1;
|
||||
- else if (cs_cap <= 0x10000000) /* 2Gb */
|
||||
+ else if (cs_cap <= 0x100) /* 2Gb */
|
||||
die_bw_0 = (col < 10) ? 2 : 1;
|
||||
- else if (cs_cap <= 0x40000000) /* 8Gb */
|
||||
+ else if (cs_cap <= 0x400) /* 8Gb */
|
||||
die_bw_0 = (col < 11) ? 2 : 1;
|
||||
else
|
||||
die_bw_0 = (col < 12) ? 2 : 1;
|
||||
@ -1,44 +0,0 @@
|
||||
From c7496009386dbac8f8d18a94258031f30683d7c6 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sun, 20 Feb 2022 07:59:02 -0500
|
||||
Subject: [PATCH] gpio: rockchip: fix building for spl
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
drivers/gpio/rk_gpio.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/common/spl/Kconfig
|
||||
+++ b/common/spl/Kconfig
|
||||
@@ -454,6 +454,11 @@ config SPL_FIT_IMAGE_TINY
|
||||
ensure this information is available to the next image
|
||||
invoked).
|
||||
|
||||
+config SPL_ADC
|
||||
+ bool "Support ADC drivers in SPL"
|
||||
+ help
|
||||
+ Enable ADC drivers in SPL.
|
||||
+
|
||||
config SPL_CACHE
|
||||
bool "Support CACHE drivers"
|
||||
help
|
||||
--- a/drivers/Makefile
|
||||
+++ b/drivers/Makefile
|
||||
@@ -1,5 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
+obj-$(CONFIG_$(SPL_)ADC) += adc/
|
||||
obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
|
||||
obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
|
||||
obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/
|
||||
--- a/drivers/gpio/rk_gpio.c
|
||||
+++ b/drivers/gpio/rk_gpio.c
|
||||
@@ -118,7 +118,7 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
|
||||
}
|
||||
|
||||
/* Simple SPL interface to GPIOs */
|
||||
-#ifdef CONFIG_SPL_BUILD
|
||||
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ROCKCHIP_GPIO_V2)
|
||||
|
||||
enum {
|
||||
PULL_NONE_1V8 = 0,
|
||||
@ -1,28 +0,0 @@
|
||||
From 5011ceb0da47f7c3d54d20b45b7df884e6e92ac5 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sun, 20 Feb 2022 07:58:38 -0500
|
||||
Subject: [PATCH] clk: rockchip: rk3568: fix reset handler
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
---
|
||||
drivers/clk/rockchip/clk_rk3568.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk_rk3568.c
|
||||
+++ b/drivers/clk/rockchip/clk_rk3568.c
|
||||
@@ -14,6 +14,7 @@
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
#include <asm/arch-rockchip/hardware.h>
|
||||
#include <asm/io.h>
|
||||
+#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
#include <dt-bindings/clock/rk3568-cru.h>
|
||||
|
||||
@@ -2934,6 +2935,7 @@ static int rk3568_clk_bind(struct udevice *dev)
|
||||
glb_srst_fst);
|
||||
priv->glb_srst_snd_value = offsetof(struct rk3568_cru,
|
||||
glb_srsr_snd);
|
||||
+ dev_set_priv(sys_child, priv);
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
|
||||
@ -0,0 +1,35 @@
|
||||
From 2d7c904f271ffd19086cafe7cd6548ec5b1a5a83 Mon Sep 17 00:00:00 2001
|
||||
From: Jason Zhu <jason.zhu@rock-chips.com>
|
||||
Date: Thu, 12 Mar 2020 15:04:51 +0800
|
||||
Subject: [PATCH] driver: Makefile: support adc in SPL
|
||||
|
||||
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
|
||||
Change-Id: I915becbf9597aa070001d3368d8daf9079565fc9
|
||||
---
|
||||
common/spl/Kconfig | 6 ++++++
|
||||
drivers/Makefile | 2 +-
|
||||
2 files changed, 7 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/common/spl/Kconfig
|
||||
+++ b/common/spl/Kconfig
|
||||
@@ -587,6 +587,11 @@ config SPL_FIT_IMAGE_TINY
|
||||
ensure this information is available to the next image
|
||||
invoked).
|
||||
|
||||
+config SPL_ADC
|
||||
+ bool "Support ADC drivers in SPL"
|
||||
+ help
|
||||
+ Enable ADC drivers in SPL.
|
||||
+
|
||||
config SPL_CACHE
|
||||
bool "Support CACHE drivers"
|
||||
help
|
||||
--- a/drivers/Makefile
|
||||
+++ b/drivers/Makefile
|
||||
@@ -1,5 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
+obj-$(CONFIG_$(SPL_)ADC) += adc/
|
||||
obj-$(CONFIG_$(SPL_TPL_)BLK) += block/
|
||||
obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
|
||||
obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
|
||||
@ -19,7 +19,7 @@ Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
|
||||
-
|
||||
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
|
||||
# inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way,
|
||||
# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way,
|
||||
# we can have the preprocessor correctly recognise both 0x0 and 0
|
||||
# meaning "turn it off".
|
||||
-obj-y += boot_mode.o
|
||||
@ -116,9 +116,9 @@ Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
return 0;
|
||||
}
|
||||
@@ -164,3 +193,26 @@ int ft_system_setup(void *blob, struct bd_info *bd)
|
||||
return 0;
|
||||
};
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
+
|
||||
+#ifdef CONFIG_SPL_BUILD
|
||||
+
|
||||
|
||||
@ -1,282 +0,0 @@
|
||||
From cd6a45a41fb2c19884ac87afade87b4d53601929 Mon Sep 17 00:00:00 2001
|
||||
From: Tom Rini <trini@konsulko.com>
|
||||
Date: Sat, 25 Jun 2022 11:02:31 -0400
|
||||
Subject: [PATCH] Convert CONFIG_USB_OHCI_NEW et al to Kconfig
|
||||
|
||||
This converts the following to Kconfig:
|
||||
CONFIG_SYS_OHCI_SWAP_REG_ACCESS
|
||||
CONFIG_SYS_USB_OHCI_CPU_INIT
|
||||
CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
|
||||
CONFIG_SYS_USB_OHCI_SLOT_NAME
|
||||
CONFIG_USB_ATMEL
|
||||
CONFIG_USB_ATMEL_CLK_SEL_PLLB
|
||||
CONFIG_USB_ATMEL_CLK_SEL_UPLL
|
||||
CONFIG_USB_OHCI_LPC32XX
|
||||
CONFIG_USB_OHCI_NEW
|
||||
|
||||
Signed-off-by: Tom Rini <trini@konsulko.com>
|
||||
---
|
||||
|
||||
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
|
||||
index 4d6d235cb125..c81437300c74 100644
|
||||
--- a/configs/evb-rk3328_defconfig
|
||||
+++ b/configs/evb-rk3328_defconfig
|
||||
@@ -99,6 +99,7 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_DWC3=y
|
||||
# CONFIG_USB_DWC3_GADGET is not set
|
||||
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
|
||||
index 41793ca7e486..15c2e1698c20 100644
|
||||
--- a/configs/nanopi-r2s-rk3328_defconfig
|
||||
+++ b/configs/nanopi-r2s-rk3328_defconfig
|
||||
@@ -102,6 +102,7 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_DWC3=y
|
||||
# CONFIG_USB_DWC3_GADGET is not set
|
||||
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
|
||||
index ab25abc1a031..43b90c7879b7 100644
|
||||
--- a/configs/roc-cc-rk3328_defconfig
|
||||
+++ b/configs/roc-cc-rk3328_defconfig
|
||||
@@ -108,6 +108,7 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_DWC3=y
|
||||
# CONFIG_USB_DWC3_GADGET is not set
|
||||
diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
|
||||
index 1d51a267b93a..7d95e171f7f4 100644
|
||||
--- a/configs/rock-pi-e-rk3328_defconfig
|
||||
+++ b/configs/rock-pi-e-rk3328_defconfig
|
||||
@@ -109,6 +109,7 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_DWC3=y
|
||||
# CONFIG_USB_DWC3_GADGET is not set
|
||||
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
|
||||
index 640fe558d414..bc333a5e2a6a 100644
|
||||
--- a/configs/rock64-rk3328_defconfig
|
||||
+++ b/configs/rock64-rk3328_defconfig
|
||||
@@ -106,6 +106,7 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_DWC3=y
|
||||
# CONFIG_USB_DWC3_GADGET is not set
|
||||
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
|
||||
index 78e50dbfbcb7..bb5b2143691d 100644
|
||||
--- a/configs/rock960-rk3399_defconfig
|
||||
+++ b/configs/rock960-rk3399_defconfig
|
||||
@@ -74,6 +74,7 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_KEYBOARD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
|
||||
index 4d2a5b32e31c..ef28fe6a937a 100644
|
||||
--- a/configs/rockpro64-rk3399_defconfig
|
||||
+++ b/configs/rockpro64-rk3399_defconfig
|
||||
@@ -87,6 +87,7 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_KEYBOARD=y
|
||||
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
|
||||
index 0b82c2fdaf71..31ae9f74e7ac 100644
|
||||
--- a/drivers/usb/host/Kconfig
|
||||
+++ b/drivers/usb/host/Kconfig
|
||||
@@ -297,10 +297,17 @@ config USB_EHCI_TXFIFO_THRESH
|
||||
Enables support for the on-chip EHCI controller on FSL chips.
|
||||
endif # USB_EHCI_HCD
|
||||
|
||||
+config USB_OHCI_NEW
|
||||
+ bool
|
||||
+
|
||||
+config SYS_USB_OHCI_CPU_INIT
|
||||
+ bool
|
||||
+
|
||||
config USB_OHCI_HCD
|
||||
bool "OHCI HCD (USB 1.1) support"
|
||||
depends on DM && OF_CONTROL
|
||||
select USB_HOST
|
||||
+ select USB_OHCI_NEW
|
||||
---help---
|
||||
The Open Host Controller Interface (OHCI) is a standard for accessing
|
||||
USB 1.1 host controller hardware. It does more in hardware than Intel's
|
||||
@@ -332,6 +339,19 @@ config USB_OHCI_DA8XX
|
||||
|
||||
endif # USB_OHCI_HCD
|
||||
|
||||
+config SYS_USB_OHCI_SLOT_NAME
|
||||
+ string "Display name for the OHCI controller"
|
||||
+ depends on USB_OHCI_NEW && !DM_USB
|
||||
+
|
||||
+config SYS_USB_OHCI_MAX_ROOT_PORTS
|
||||
+ int "Maximal number of ports of the root hub"
|
||||
+ depends on USB_OHCI_NEW
|
||||
+ default 1 if ARCH_SUNXI
|
||||
+
|
||||
+config SYS_OHCI_SWAP_REG_ACCESS
|
||||
+ bool "Perform byte swapping on OHCI controller register accesses"
|
||||
+ depends on USB_OHCI_NEW
|
||||
+
|
||||
config USB_UHCI_HCD
|
||||
bool "UHCI HCD (most Intel and VIA) support"
|
||||
select USB_HOST
|
||||
@@ -381,3 +401,27 @@ config USB_R8A66597_HCD
|
||||
---help---
|
||||
This enables support for the on-chip Renesas R8A66597 USB 2.0
|
||||
controller, present in various RZ and SH SoCs.
|
||||
+
|
||||
+config USB_ATMEL
|
||||
+ bool "AT91 OHCI USB support"
|
||||
+ depends on ARCH_AT91
|
||||
+ select SYS_USB_OHCI_CPU_INIT
|
||||
+ select USB_OHCI_NEW
|
||||
+
|
||||
+choice
|
||||
+ prompt "Clock for OHCI"
|
||||
+ depends on USB_ATMEL
|
||||
+
|
||||
+config USB_ATMEL_CLK_SEL_PLLB
|
||||
+ bool "PLLB"
|
||||
+
|
||||
+config USB_ATMEL_CLK_SEL_UPLL
|
||||
+ bool "UPLL"
|
||||
+
|
||||
+endchoice
|
||||
+
|
||||
+config USB_OHCI_LPC32XX
|
||||
+ bool "LPC32xx USB OHCI support"
|
||||
+ depends on ARCH_LPC32XX
|
||||
+ select SYS_USB_OHCI_CPU_INIT
|
||||
+ select USB_OHCI_NEW
|
||||
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
|
||||
index 8ceabaf45c1b..9b955c1bd678 100644
|
||||
--- a/drivers/usb/host/ohci-at91.c
|
||||
+++ b/drivers/usb/host/ohci-at91.c
|
||||
@@ -5,9 +5,6 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
-
|
||||
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
|
||||
-
|
||||
#include <asm/arch/clk.h>
|
||||
|
||||
int usb_cpu_init(void)
|
||||
@@ -65,5 +62,3 @@ int usb_cpu_init_fail(void)
|
||||
{
|
||||
return usb_cpu_stop();
|
||||
}
|
||||
-
|
||||
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
|
||||
diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
|
||||
index 163f0ef17b11..5d23058aaf6a 100644
|
||||
--- a/drivers/usb/host/ohci-generic.c
|
||||
+++ b/drivers/usb/host/ohci-generic.c
|
||||
@@ -14,10 +14,6 @@
|
||||
#include <reset.h>
|
||||
#include "ohci.h"
|
||||
|
||||
-#if !defined(CONFIG_USB_OHCI_NEW)
|
||||
-# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
|
||||
-#endif
|
||||
-
|
||||
struct generic_ohci {
|
||||
ohci_t ohci;
|
||||
struct clk *clocks; /* clock list */
|
||||
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
|
||||
index a38cd25eb85f..7699f2e6b15a 100644
|
||||
--- a/drivers/usb/host/ohci.h
|
||||
+++ b/drivers/usb/host/ohci.h
|
||||
@@ -151,7 +151,7 @@ struct ohci_hcca {
|
||||
* Maximum number of root hub ports.
|
||||
*/
|
||||
#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
|
||||
-# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
|
||||
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
|
||||
index 492b7b4df128..b7e850370b31 100644
|
||||
--- a/include/configs/evb_rk3399.h
|
||||
+++ b/include/configs/evb_rk3399.h
|
||||
@@ -15,7 +15,4 @@
|
||||
|
||||
#define SDRAM_BANK_SIZE (2UL << 30)
|
||||
|
||||
-#define CONFIG_USB_OHCI_NEW
|
||||
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
-
|
||||
#endif
|
||||
diff --git a/include/configs/gru.h b/include/configs/gru.h
|
||||
index b1084bb21d4d..be2dc79968c0 100644
|
||||
--- a/include/configs/gru.h
|
||||
+++ b/include/configs/gru.h
|
||||
@@ -13,7 +13,4 @@
|
||||
|
||||
#include <configs/rk3399_common.h>
|
||||
|
||||
-#define CONFIG_USB_OHCI_NEW
|
||||
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
-
|
||||
#endif
|
||||
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
|
||||
index 90183579202d..165b78ff3309 100644
|
||||
--- a/include/configs/rk3328_common.h
|
||||
+++ b/include/configs/rk3328_common.h
|
||||
@@ -30,8 +30,4 @@
|
||||
"partitions=" PARTS_DEFAULT \
|
||||
BOOTENV
|
||||
|
||||
-/* rockchip ohci host driver */
|
||||
-#define CONFIG_USB_OHCI_NEW
|
||||
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
|
||||
-
|
||||
#endif
|
||||
diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h
|
||||
index 2edad710284f..6099d2fa55a6 100644
|
||||
--- a/include/configs/rock960_rk3399.h
|
||||
+++ b/include/configs/rock960_rk3399.h
|
||||
@@ -14,7 +14,4 @@
|
||||
#include <configs/rk3399_common.h>
|
||||
|
||||
#define SDRAM_BANK_SIZE (2UL << 30)
|
||||
-
|
||||
-#define CONFIG_USB_OHCI_NEW
|
||||
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#endif
|
||||
diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h
|
||||
index 903e9df527c1..9195b9b99e41 100644
|
||||
--- a/include/configs/rockpro64_rk3399.h
|
||||
+++ b/include/configs/rockpro64_rk3399.h
|
||||
@@ -14,7 +14,4 @@
|
||||
#include <configs/rk3399_common.h>
|
||||
|
||||
#define SDRAM_BANK_SIZE (2UL << 30)
|
||||
-
|
||||
-#define CONFIG_USB_OHCI_NEW
|
||||
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#endif
|
||||
@ -1,166 +0,0 @@
|
||||
--- a/include/image.h
|
||||
+++ b/include/image.h
|
||||
@@ -1020,21 +1020,6 @@ int fit_image_hash_get_value(const void
|
||||
|
||||
int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
|
||||
|
||||
-/**
|
||||
- * fit_pre_load_data() - add public key to fdt blob
|
||||
- *
|
||||
- * Adds public key to the node pre load.
|
||||
- *
|
||||
- * @keydir: Directory containing keys
|
||||
- * @keydest: FDT blob to write public key
|
||||
- * @fit: Pointer to the FIT format image header
|
||||
- *
|
||||
- * returns:
|
||||
- * 0, on success
|
||||
- * < 0, on failure
|
||||
- */
|
||||
-int fit_pre_load_data(const char *keydir, void *keydest, void *fit);
|
||||
-
|
||||
int fit_cipher_data(const char *keydir, void *keydest, void *fit,
|
||||
const char *comment, int require_keys,
|
||||
const char *engine_id, const char *cmdname);
|
||||
--- a/tools/fit_image.c
|
||||
+++ b/tools/fit_image.c
|
||||
@@ -59,9 +59,6 @@ static int fit_add_file_data(struct imag
|
||||
ret = fit_set_timestamp(ptr, 0, time);
|
||||
}
|
||||
|
||||
- if (!ret)
|
||||
- ret = fit_pre_load_data(params->keydir, dest_blob, ptr);
|
||||
-
|
||||
if (!ret) {
|
||||
ret = fit_cipher_data(params->keydir, dest_blob, ptr,
|
||||
params->comment,
|
||||
--- a/tools/image-host.c
|
||||
+++ b/tools/image-host.c
|
||||
@@ -14,11 +14,6 @@
|
||||
#include <image.h>
|
||||
#include <version.h>
|
||||
|
||||
-#include <openssl/pem.h>
|
||||
-#include <openssl/evp.h>
|
||||
-
|
||||
-#define IMAGE_PRE_LOAD_PATH "/image/pre-load/sig"
|
||||
-
|
||||
/**
|
||||
* fit_set_hash_value - set hash value in requested has node
|
||||
* @fit: pointer to the FIT format image header
|
||||
@@ -1116,115 +1111,6 @@ static int fit_config_add_verification_d
|
||||
return 0;
|
||||
}
|
||||
|
||||
-/*
|
||||
- * 0) open file (open)
|
||||
- * 1) read certificate (PEM_read_X509)
|
||||
- * 2) get public key (X509_get_pubkey)
|
||||
- * 3) provide der format (d2i_RSAPublicKey)
|
||||
- */
|
||||
-static int read_pub_key(const char *keydir, const void *name,
|
||||
- unsigned char **pubkey, int *pubkey_len)
|
||||
-{
|
||||
- char path[1024];
|
||||
- EVP_PKEY *key = NULL;
|
||||
- X509 *cert;
|
||||
- FILE *f;
|
||||
- int ret;
|
||||
-
|
||||
- memset(path, 0, 1024);
|
||||
- snprintf(path, sizeof(path), "%s/%s.crt", keydir, (char *)name);
|
||||
-
|
||||
- /* Open certificate file */
|
||||
- f = fopen(path, "r");
|
||||
- if (!f) {
|
||||
- fprintf(stderr, "Couldn't open RSA certificate: '%s': %s\n",
|
||||
- path, strerror(errno));
|
||||
- return -EACCES;
|
||||
- }
|
||||
-
|
||||
- /* Read the certificate */
|
||||
- cert = NULL;
|
||||
- if (!PEM_read_X509(f, &cert, NULL, NULL)) {
|
||||
- printf("Couldn't read certificate");
|
||||
- ret = -EINVAL;
|
||||
- goto err_cert;
|
||||
- }
|
||||
-
|
||||
- /* Get the public key from the certificate. */
|
||||
- key = X509_get_pubkey(cert);
|
||||
- if (!key) {
|
||||
- printf("Couldn't read public key\n");
|
||||
- ret = -EINVAL;
|
||||
- goto err_pubkey;
|
||||
- }
|
||||
-
|
||||
- /* Get DER form */
|
||||
- ret = i2d_PublicKey(key, pubkey);
|
||||
- if (ret < 0) {
|
||||
- printf("Couldn't get DER form\n");
|
||||
- ret = -EINVAL;
|
||||
- goto err_pubkey;
|
||||
- }
|
||||
-
|
||||
- *pubkey_len = ret;
|
||||
- ret = 0;
|
||||
-
|
||||
-err_pubkey:
|
||||
- X509_free(cert);
|
||||
-err_cert:
|
||||
- fclose(f);
|
||||
- return ret;
|
||||
-}
|
||||
-
|
||||
-int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
|
||||
-{
|
||||
- int pre_load_noffset;
|
||||
- const void *algo_name;
|
||||
- const void *key_name;
|
||||
- unsigned char *pubkey = NULL;
|
||||
- int ret, pubkey_len;
|
||||
-
|
||||
- if (!keydir || !keydest || !fit)
|
||||
- return 0;
|
||||
-
|
||||
- /* Search node pre-load sig */
|
||||
- pre_load_noffset = fdt_path_offset(keydest, IMAGE_PRE_LOAD_PATH);
|
||||
- if (pre_load_noffset < 0) {
|
||||
- ret = 0;
|
||||
- goto out;
|
||||
- }
|
||||
-
|
||||
- algo_name = fdt_getprop(keydest, pre_load_noffset, "algo-name", NULL);
|
||||
- key_name = fdt_getprop(keydest, pre_load_noffset, "key-name", NULL);
|
||||
-
|
||||
- /* Check that all mandatory properties are present */
|
||||
- if (!algo_name || !key_name) {
|
||||
- if (!algo_name)
|
||||
- printf("The property algo-name is missing in the node %s\n",
|
||||
- IMAGE_PRE_LOAD_PATH);
|
||||
- if (!key_name)
|
||||
- printf("The property key-name is missing in the node %s\n",
|
||||
- IMAGE_PRE_LOAD_PATH);
|
||||
- ret = -EINVAL;
|
||||
- goto out;
|
||||
- }
|
||||
-
|
||||
- /* Read public key */
|
||||
- ret = read_pub_key(keydir, key_name, &pubkey, &pubkey_len);
|
||||
- if (ret < 0)
|
||||
- goto out;
|
||||
-
|
||||
- /* Add the public key to the device tree */
|
||||
- ret = fdt_setprop(keydest, pre_load_noffset, "public-key",
|
||||
- pubkey, pubkey_len);
|
||||
- if (ret)
|
||||
- printf("Can't set public-key in node %s (ret = %d)\n",
|
||||
- IMAGE_PRE_LOAD_PATH, ret);
|
||||
-
|
||||
- out:
|
||||
- return ret;
|
||||
-}
|
||||
-
|
||||
int fit_cipher_data(const char *keydir, void *keydest, void *fit,
|
||||
const char *comment, int require_keys,
|
||||
const char *engine_id, const char *cmdname)
|
||||
@ -1,125 +0,0 @@
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -413,13 +413,7 @@ PERL = perl
|
||||
PYTHON ?= python
|
||||
PYTHON2 = python2
|
||||
PYTHON3 ?= python3
|
||||
-
|
||||
-# The devicetree compiler and pylibfdt are automatically built unless DTC is
|
||||
-# provided. If DTC is provided, it is assumed the pylibfdt is available too.
|
||||
-DTC_INTREE := $(objtree)/scripts/dtc/dtc
|
||||
-DTC ?= $(DTC_INTREE)
|
||||
-DTC_MIN_VERSION := 010406
|
||||
-
|
||||
+DTC ?= $(objtree)/scripts/dtc/dtc
|
||||
CHECK = sparse
|
||||
|
||||
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
|
||||
@@ -2070,29 +2064,9 @@ endif
|
||||
|
||||
endif
|
||||
|
||||
-# Check dtc and pylibfdt, if DTC is provided, else build them
|
||||
PHONY += scripts_dtc
|
||||
scripts_dtc: scripts_basic
|
||||
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
|
||||
- $(MAKE) $(build)=scripts/dtc; \
|
||||
- else \
|
||||
- if ! $(DTC) -v >/dev/null; then \
|
||||
- echo '*** Failed to check dtc version: $(DTC)'; \
|
||||
- false; \
|
||||
- else \
|
||||
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
|
||||
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
|
||||
- false; \
|
||||
- else \
|
||||
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
|
||||
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
|
||||
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
|
||||
- false; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi
|
||||
+ $(Q)$(MAKE) $(build)=scripts/dtc
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
quiet_cmd_cpp_lds = LDS $@
|
||||
--- a/doc/build/gcc.rst
|
||||
+++ b/doc/build/gcc.rst
|
||||
@@ -131,27 +131,6 @@ Further important build parameters are
|
||||
* O=<dir> - generate all output files in directory <dir>, including .config
|
||||
* V=1 - verbose build
|
||||
|
||||
-Devicetree compiler
|
||||
-~~~~~~~~~~~~~~~~~~~
|
||||
-
|
||||
-Boards that use `CONFIG_OF_CONTROL` (i.e. almost all of them) need the
|
||||
-devicetree compiler (dtc). Those with `CONFIG_PYLIBFDT` need pylibfdt, a Python
|
||||
-library for accessing devicetree data. Suitable versions of these are included
|
||||
-in the U-Boot tree in `scripts/dtc` and built automatically as needed.
|
||||
-
|
||||
-To use the system versions of these, use the DTC parameter, for example
|
||||
-
|
||||
-.. code-block:: bash
|
||||
-
|
||||
- DTC=/usr/bin/dtc make
|
||||
-
|
||||
-In this case, dtc and pylibfdt are not built. The build checks that the version
|
||||
-of dtc is new enough. It also makes sure that pylibfdt is present, if needed
|
||||
-(see `scripts_dtc` in the Makefile).
|
||||
-
|
||||
-Note that the :doc:`tools` are always built with the included version of libfdt
|
||||
-so it is not possible to build U-Boot tools with a system libfdt, at present.
|
||||
-
|
||||
Other build targets
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
--- a/dts/Kconfig
|
||||
+++ b/dts/Kconfig
|
||||
@@ -5,6 +5,9 @@
|
||||
config SUPPORT_OF_CONTROL
|
||||
bool
|
||||
|
||||
+config DTC
|
||||
+ bool
|
||||
+
|
||||
config PYLIBFDT
|
||||
bool
|
||||
|
||||
@@ -21,6 +24,7 @@ menu "Device Tree Control"
|
||||
|
||||
config OF_CONTROL
|
||||
bool "Run-time configuration via Device Tree"
|
||||
+ select DTC
|
||||
select OF_LIBFDT if !OF_PLATDATA
|
||||
select OF_REAL if !OF_PLATDATA
|
||||
help
|
||||
--- a/scripts/Makefile
|
||||
+++ b/scripts/Makefile
|
||||
@@ -10,3 +10,4 @@ always := $(hostprogs-y)
|
||||
|
||||
# Let clean descend into subdirs
|
||||
subdir- += basic kconfig dtc
|
||||
+subdir-$(CONFIG_DTC) += dtc
|
||||
--- a/scripts/dtc-version.sh
|
||||
+++ b/scripts/dtc-version.sh
|
||||
@@ -10,16 +10,11 @@
|
||||
dtc="$*"
|
||||
|
||||
if [ ${#dtc} -eq 0 ]; then
|
||||
- echo "Error: No dtc command specified"
|
||||
+ echo "Error: No dtc command specified."
|
||||
printf "Usage:\n\t$0 <dtc-command>\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
-if ! which $dtc >/dev/null ; then
|
||||
- echo "Error: Cannot find dtc: $dtc"
|
||||
- exit 1
|
||||
-fi
|
||||
-
|
||||
MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1)
|
||||
MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2)
|
||||
PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1)
|
||||
@ -1,6 +1,6 @@
|
||||
--- a/tools/Makefile
|
||||
+++ b/tools/Makefile
|
||||
@@ -119,7 +119,6 @@ dumpimage-mkimage-objs := aisimage.o \
|
||||
@@ -113,7 +113,6 @@ dumpimage-mkimage-objs := aisimage.o \
|
||||
imximage.o \
|
||||
imx8image.o \
|
||||
imx8mimage.o \
|
||||
|
||||
@ -0,0 +1,30 @@
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -2000,26 +2000,7 @@ endif
|
||||
# Check dtc and pylibfdt, if DTC is provided, else build them
|
||||
PHONY += scripts_dtc
|
||||
scripts_dtc: scripts_basic
|
||||
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
|
||||
- $(MAKE) $(build)=scripts/dtc; \
|
||||
- else \
|
||||
- if ! $(DTC) -v >/dev/null; then \
|
||||
- echo '*** Failed to check dtc version: $(DTC)'; \
|
||||
- false; \
|
||||
- else \
|
||||
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
|
||||
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
|
||||
- false; \
|
||||
- else \
|
||||
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
|
||||
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
|
||||
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
|
||||
- false; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi
|
||||
+ $(MAKE) $(build)=scripts/dtc
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
quiet_cmd_cpp_lds = LDS $@
|
||||
@ -0,0 +1,24 @@
|
||||
--- a/tools/image-host.c
|
||||
+++ b/tools/image-host.c
|
||||
@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
|
||||
* 2) get public key (X509_get_pubkey)
|
||||
* 3) provide der format (d2i_RSAPublicKey)
|
||||
*/
|
||||
+#ifdef CONFIG_TOOLS_LIBCRYPTO
|
||||
static int read_pub_key(const char *keydir, const void *name,
|
||||
unsigned char **pubkey, int *pubkey_len)
|
||||
{
|
||||
@@ -1178,6 +1179,13 @@ err_cert:
|
||||
fclose(f);
|
||||
return ret;
|
||||
}
|
||||
+#else
|
||||
+static int read_pub_key(const char *keydir, const void *name,
|
||||
+ unsigned char **pubkey, int *pubkey_len)
|
||||
+{
|
||||
+ return -ENOSYS;
|
||||
+}
|
||||
+#endif
|
||||
|
||||
int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
|
||||
{
|
||||
@ -0,0 +1,72 @@
|
||||
From 734b9d9e33919efbec63b1bfe48f25ce16dbd59a Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Fri, 17 Mar 2023 19:16:45 +0000
|
||||
Subject: [PATCH] clk: scmi: Add Kconfig option for SPL
|
||||
|
||||
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options
|
||||
enabled and SPL_FIRMWARE disabled result in the following error.
|
||||
|
||||
drivers/clk/clk_scmi.o: in function `scmi_clk_gate':
|
||||
drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg'
|
||||
drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno'
|
||||
drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate':
|
||||
drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg'
|
||||
drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno'
|
||||
drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate':
|
||||
drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg'
|
||||
drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno'
|
||||
drivers/clk/clk_scmi.o: in function `scmi_clk_probe':
|
||||
drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel'
|
||||
make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
|
||||
make: *** [Makefile:2043: spl/u-boot-spl] Error 2
|
||||
|
||||
Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
||||
Link: https://patchwork.ozlabs.org/project/uboot/patch/20230317191638.2558279-2-jonas@kwiboo.se/
|
||||
---
|
||||
drivers/clk/Kconfig | 8 ++++++++
|
||||
drivers/clk/Makefile | 2 +-
|
||||
drivers/firmware/scmi/scmi_agent-uclass.c | 2 +-
|
||||
3 files changed, 10 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/clk/Kconfig
|
||||
+++ b/drivers/clk/Kconfig
|
||||
@@ -166,6 +166,14 @@ config CLK_SCMI
|
||||
by a SCMI agent based on SCMI clock protocol communication
|
||||
with a SCMI server.
|
||||
|
||||
+config SPL_CLK_SCMI
|
||||
+ bool "Enable SCMI clock driver in SPL"
|
||||
+ depends on SCMI_FIRMWARE && SPL_FIRMWARE
|
||||
+ help
|
||||
+ Enable this option if you want to support clock devices exposed
|
||||
+ by a SCMI agent based on SCMI clock protocol communication
|
||||
+ with a SCMI server in SPL.
|
||||
+
|
||||
config CLK_HSDK
|
||||
bool "Enable cgu clock driver for HSDK boards"
|
||||
depends on CLK && TARGET_HSDK
|
||||
--- a/drivers/clk/Makefile
|
||||
+++ b/drivers/clk/Makefile
|
||||
@@ -39,7 +39,7 @@ obj-$(CONFIG_CLK_MVEBU) += mvebu/
|
||||
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
|
||||
obj-$(CONFIG_CLK_OWL) += owl/
|
||||
obj-$(CONFIG_CLK_RENESAS) += renesas/
|
||||
-obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
|
||||
+obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
|
||||
obj-$(CONFIG_CLK_SIFIVE) += sifive/
|
||||
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
|
||||
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
|
||||
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
|
||||
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
|
||||
@@ -75,7 +75,7 @@ static int scmi_bind_protocols(struct udevice *dev)
|
||||
name = ofnode_get_name(node);
|
||||
switch (protocol_id) {
|
||||
case SCMI_PROTOCOL_ID_CLOCK:
|
||||
- if (IS_ENABLED(CONFIG_CLK_SCMI))
|
||||
+ if (CONFIG_IS_ENABLED(CLK_SCMI))
|
||||
drv = DM_DRIVER_GET(scmi_clock);
|
||||
break;
|
||||
case SCMI_PROTOCOL_ID_RESET_DOMAIN:
|
||||
@ -0,0 +1,126 @@
|
||||
From 7db635cf638dfad08a50e26a6d02e1b6e7a9d7c5 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sat, 18 Mar 2023 23:30:42 +0000
|
||||
Subject: [PATCH] pinctrl: rockchip: Fix IO mux selection on RK3568
|
||||
|
||||
IO mux selection is not working correctly for all pins. Sync mux route
|
||||
data from linux to add any missing and update wrong trigger pins to fix
|
||||
this. Also apply the pull-up fix needed for GPIO0 D3-D6.
|
||||
|
||||
Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver")
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://patchwork.ozlabs.org/project/uboot/patch/20230318233039.799975-1-jonas@kwiboo.se/
|
||||
---
|
||||
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 66 +++++++++++++----------
|
||||
1 file changed, 38 insertions(+), 28 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c
|
||||
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
|
||||
@@ -13,6 +13,12 @@
|
||||
#include "pinctrl-rockchip.h"
|
||||
|
||||
static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */
|
||||
+ MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */
|
||||
@@ -33,30 +39,22 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */
|
||||
@@ -68,7 +66,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */
|
||||
@@ -81,7 +79,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */
|
||||
@@ -94,8 +92,11 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
|
||||
MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */
|
||||
- MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */
|
||||
- MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */
|
||||
+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */
|
||||
MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */
|
||||
MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */
|
||||
MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */
|
||||
@@ -237,6 +238,15 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank,
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
|
||||
+ * where that pull up value becomes 3.
|
||||
+ */
|
||||
+ if (bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
|
||||
+ if (ret == 1)
|
||||
+ ret = 3;
|
||||
+ }
|
||||
+
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
|
||||
@ -17,10 +17,10 @@ Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
|
||||
--- a/configs/rockpro64-rk3399_defconfig
|
||||
+++ b/configs/rockpro64-rk3399_defconfig
|
||||
@@ -12,7 +12,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
|
||||
@@ -21,7 +21,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_BOOTSTAGE=y
|
||||
CONFIG_BOOTSTAGE_REPORT=y
|
||||
-CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
|
||||
@ -13,7 +13,7 @@
|
||||
@@ -0,0 +1,57 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
|
||||
@ -42,27 +42,31 @@
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
|
||||
@@ -0,0 +1,104 @@
|
||||
@@ -0,0 +1,112 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO=y
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_ROCKCHIP_RK3328=y
|
||||
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
@ -71,13 +75,19 @@
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x2000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_I2C=y
|
||||
+CONFIG_SPL_POWER=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
@ -108,7 +118,6 @@
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
@ -125,9 +134,9 @@
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSINFO=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+# CONFIG_TPL_SYSRESET is not set
|
||||
@ -138,7 +147,6 @@
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
+CONFIG_USB_DWC2=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+# CONFIG_USB_DWC3_GADGET is not set
|
||||
|
||||
@ -37,27 +37,31 @@ Subject: [PATCH] Add support for Orangepi R1 Plus LTS
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
|
||||
@@ -0,0 +1,104 @@
|
||||
@@ -0,0 +1,112 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO=y
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_ROCKCHIP_RK3328=y
|
||||
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
@ -66,13 +70,19 @@ Subject: [PATCH] Add support for Orangepi R1 Plus LTS
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x2000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_I2C=y
|
||||
+CONFIG_SPL_POWER=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
@ -103,7 +113,6 @@ Subject: [PATCH] Add support for Orangepi R1 Plus LTS
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
@ -120,9 +129,9 @@ Subject: [PATCH] Add support for Orangepi R1 Plus LTS
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSINFO=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+# CONFIG_TPL_SYSRESET is not set
|
||||
@ -133,7 +142,6 @@ Subject: [PATCH] Add support for Orangepi R1 Plus LTS
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
+CONFIG_USB_DWC2=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+# CONFIG_USB_DWC3_GADGET is not set
|
||||
@ -142,5 +150,3 @@ Subject: [PATCH] Add support for Orangepi R1 Plus LTS
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_TPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -81,25 +81,31 @@ new file mode 100644
|
||||
index 0000000000..7bc7a3274f
|
||||
--- /dev/null
|
||||
+++ b/configs/nanopi-r2c-rk3328_defconfig
|
||||
@@ -0,0 +1,100 @@
|
||||
@@ -0,0 +1,112 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO_SUPPORT=y
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO=y
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_ROCKCHIP_RK3328=y
|
||||
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
@ -108,13 +114,19 @@ index 0000000000..7bc7a3274f
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x2000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_I2C_SUPPORT=y
|
||||
+CONFIG_SPL_POWER_SUPPORT=y
|
||||
+CONFIG_SPL_I2C=y
|
||||
+CONFIG_SPL_POWER=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
@ -127,6 +139,7 @@ index 0000000000..7bc7a3274f
|
||||
+CONFIG_TPL_OF_PLATDATA=y
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_SYS_MMC_ENV_DEV=1
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_TPL_DM=y
|
||||
+CONFIG_REGMAP=y
|
||||
@ -144,13 +157,13 @@ index 0000000000..7bc7a3274f
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_DM_REGULATOR=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
@ -160,9 +173,9 @@ index 0000000000..7bc7a3274f
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSINFO=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+# CONFIG_TPL_SYSRESET is not set
|
||||
@ -173,7 +186,6 @@ index 0000000000..7bc7a3274f
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
+CONFIG_USB_DWC2=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+# CONFIG_USB_DWC3_GADGET is not set
|
||||
|
||||
@ -50,7 +50,7 @@
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se"
|
||||
|
||||
@ -723,7 +723,7 @@
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
|
||||
@ -863,7 +863,7 @@
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_TEXT_BASE=0x00200000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
|
||||
@ -1,19 +1,19 @@
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
rk3568-bpi-r2-pro.dtb \
|
||||
rk3568-evb.dtb \
|
||||
+ rk3568-mrkaio-m68s.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
rk3566-quartz64-a.dtb \
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
rk3568-rock-3a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk3568-u-boot.dtsi"
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
@ -305,103 +305,95 @@
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/mrkaio-m68s-rk3568_defconfig
|
||||
@@ -0,0 +1,99 @@
|
||||
@@ -0,0 +1,91 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-mrkaio-m68s"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_API=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-mrkaio-m68s.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
||||
@ -1,19 +1,19 @@
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
rk3568-bpi-r2-pro.dtb \
|
||||
rk3568-evb.dtb \
|
||||
+ rk3568-opc-h68k.dtb \
|
||||
rk3568-mrkaio-m68s.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
rk3566-quartz64-a.dtb \
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-opc-h68k-u-boot.dtsi
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk3568-u-boot.dtsi"
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
@ -314,103 +314,95 @@
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/opc-h68k-rk3568_defconfig
|
||||
@@ -0,0 +1,99 @@
|
||||
@@ -0,0 +1,91 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h68k"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_API=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h68k.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
|
||||
rk3568-bpi-r2-pro.dtb \
|
||||
rk3568-evb.dtb \
|
||||
+ rk3568-r66s.dtb \
|
||||
rk3568-opc-h68k.dtb \
|
||||
@ -13,7 +13,7 @@
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk3568-u-boot.dtsi"
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
@ -39,103 +39,95 @@
|
||||
+#include "rk3568-evb.dts"
|
||||
--- /dev/null
|
||||
+++ b/configs/r66s-rk3568_defconfig
|
||||
@@ -0,0 +1,99 @@
|
||||
@@ -0,0 +1,91 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-r66s"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_API=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-r66s.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
||||
@ -8,19 +8,19 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2
|
||||
1 file changed, 59 insertions(+)
|
||||
create mode 100644 configs/station-p2-rk3568_defconfig
|
||||
|
||||
diff --git a/configs/station-p2-rk3568_defconfig b/configs/station-p2-rk3568_defconfig
|
||||
new file mode 100644
|
||||
index 0000000000..435be99edf
|
||||
--- /dev/null
|
||||
+++ b/configs/station-p2-rk3568_defconfig
|
||||
@@ -0,0 +1,59 @@
|
||||
@@ -0,0 +1,87 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
@ -29,22 +29,32 @@ index 0000000000..435be99edf
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
@ -53,6 +63,8 @@ index 0000000000..435be99edf
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
@ -62,16 +74,27 @@ index 0000000000..435be99edf
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
--
|
||||
2.20.1
|
||||
|
||||
@ -5,15 +5,15 @@
|
||||
rk3568-mrkaio-m68s.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
+ rk3568-photonicat.dtb \
|
||||
rk3566-quartz64-a.dtb \
|
||||
rk3568-rock-3a.dtb \
|
||||
rk3568-rock-pi-e25.dtb
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
rk3568-rock-3a.dtb
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-photonicat-u-boot.dtsi
|
||||
@@ -0,0 +1,33 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk3568-u-boot.dtsi"
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
@ -103,14 +103,17 @@
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/photonicat-rk3568_defconfig
|
||||
@@ -0,0 +1,101 @@
|
||||
@@ -0,0 +1,94 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-photonicat"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
@ -120,89 +123,78 @@
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_API=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-photonicat.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_IO_VOLTAGE=y
|
||||
+CONFIG_SPL_MMC_IO_VOLTAGE=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
||||
@ -1,21 +1,21 @@
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -177,7 +177,8 @@ rk3568-evb.dtb \
|
||||
rk3568-mrkaio-m68s.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
rk3566-quartz64-a.dtb \
|
||||
rk3568-photonicat.dtb \
|
||||
rk3566-radxa-cm3-io.dtb \
|
||||
- rk3568-rock-3a.dtb
|
||||
+ rk3568-rock-3a.dtb \
|
||||
+ rk3568-radxa-e25.dtb
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
|
||||
rv1108-elgin-r1.dtb \
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
|
||||
rk3588-edgeble-neu6a-io.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk3568-u-boot.dtsi"
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
@ -47,103 +47,93 @@
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/radxa-e25-rk3568_defconfig
|
||||
@@ -0,0 +1,99 @@
|
||||
@@ -0,0 +1,89 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_EVB_RK3568=y
|
||||
+CONFIG_SPL_STACK=0x400000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_API=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
+CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_RESET_SCMI=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
||||
Loading…
Reference in New Issue
Block a user