From b9905af67305d5b660db5f30308a295850571c6e Mon Sep 17 00:00:00 2001 From: aiamadeus <2789289348@qq.com> Date: Fri, 14 Jul 2023 23:09:26 +0800 Subject: [PATCH] uboot-rockchip: bump to v2023.07 Drop upstream patches as bug fixed on rk3568. --- package/boot/uboot-rockchip/Makefile | 4 +- ...vert-rockchip-rk3399-Drop-altbootcmd.patch | 26 -- ...Disable-DISTRO_DEFAULTS-for-rk3399-b.patch | 24 -- ...Convert-rockpro64-rk3399-to-use-stan.patch | 50 --- .../015-uboot-add-NanoPi-R5S-board.patch | 46 +-- ...8-driver-Makefile-support-adc-in-SPL.patch | 35 -- ...-rockchip-handle-bootrom-mode-in-spl.patch | 144 -------- .../020-update-rock-3a-defconfig.patch | 51 +-- ...-clk-scmi-Add-Kconfig-option-for-SPL.patch | 72 ---- ...trl-rockchip-Fix-IO-mux-selection-on.patch | 126 ------- ...k35xx-Fix-boot-with-a-large-fdt-blob.patch | 43 --- ...Add-support-for-FriendlyARM-NanoPi-R.patch | 196 ----------- ...99-Add-support-for-dilusense-dlfr100.patch | 2 +- ...68-Add-support-for-ezpro_mrkaio-m68s.patch | 302 +---------------- ...568-Add-support-for-hinlink-opc-h68k.patch | 315 ++---------------- ...k3568-Add-support-for-fastrhino-r66s.patch | 42 +-- ...ip-rk3568-Add-support-for-Station-P2.patch | 24 +- ...ip-rk3568-Add-support-for-photonicat.patch | 58 ++-- ...hip-rk3568-Add-support-for-radxa_e25.patch | 41 +-- ...chip-rk3568-Add-support-for-lyt_t68m.patch | 315 ++---------------- 20 files changed, 153 insertions(+), 1763 deletions(-) delete mode 100644 package/boot/uboot-rockchip/patches/001-Revert-rockchip-rk3399-Drop-altbootcmd.patch delete mode 100644 package/boot/uboot-rockchip/patches/002-Revert-rockchip-Disable-DISTRO_DEFAULTS-for-rk3399-b.patch delete mode 100644 package/boot/uboot-rockchip/patches/003-Revert-rockchip-Convert-rockpro64-rk3399-to-use-stan.patch delete mode 100644 package/boot/uboot-rockchip/patches/018-driver-Makefile-support-adc-in-SPL.patch delete mode 100644 package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch delete mode 100644 package/boot/uboot-rockchip/patches/120-clk-scmi-Add-Kconfig-option-for-SPL.patch delete mode 100644 package/boot/uboot-rockchip/patches/121-pinctrl-rockchip-Fix-IO-mux-selection-on.patch delete mode 100644 package/boot/uboot-rockchip/patches/210-rockchip-rk35xx-Fix-boot-with-a-large-fdt-blob.patch delete mode 100644 package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index dff7a396a..3aade8bf4 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,10 +5,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2023.04 +PKG_VERSION:=2023.07 PKG_RELEASE:=$(AUTORELEASE) -PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341 +PKG_HASH:=12e921b466ae731cdbc355e6832b7f22bc90b01aeceef9886f98aaba7b394300 PKG_MAINTAINER:=Tobias Maedel diff --git a/package/boot/uboot-rockchip/patches/001-Revert-rockchip-rk3399-Drop-altbootcmd.patch b/package/boot/uboot-rockchip/patches/001-Revert-rockchip-rk3399-Drop-altbootcmd.patch deleted file mode 100644 index 09df37fb0..000000000 --- a/package/boot/uboot-rockchip/patches/001-Revert-rockchip-rk3399-Drop-altbootcmd.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 1ab5d2b9cf1b9c1c7ccb58243992fb163c64a14d Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 5 Apr 2023 21:06:19 +0800 -Subject: [PATCH 1/3] Revert "rockchip: rk3399: Drop altbootcmd" - -This reverts commit d00fb6421c8fad639f608f55f9291305061ffb17. - -Signed-off-by: Tianling Shen ---- - include/configs/rk3399_common.h | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/include/configs/rk3399_common.h -+++ b/include/configs/rk3399_common.h -@@ -52,7 +52,10 @@ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ -- "boot_targets=" BOOT_TARGETS "\0" -+ "boot_targets=" BOOT_TARGETS "\0" \ -+ "altbootcmd=" \ -+ "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \ -+ "run distro_bootcmd\0" - - #endif - diff --git a/package/boot/uboot-rockchip/patches/002-Revert-rockchip-Disable-DISTRO_DEFAULTS-for-rk3399-b.patch b/package/boot/uboot-rockchip/patches/002-Revert-rockchip-Disable-DISTRO_DEFAULTS-for-rk3399-b.patch deleted file mode 100644 index a9dc5556a..000000000 --- a/package/boot/uboot-rockchip/patches/002-Revert-rockchip-Disable-DISTRO_DEFAULTS-for-rk3399-b.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 535b09f84be0660ef5e85431328746e74cc8e6b7 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 5 Apr 2023 21:08:21 +0800 -Subject: [PATCH 2/3] Revert "rockchip: Disable DISTRO_DEFAULTS for rk3399 - boards" - -This reverts commit 2b9cc7845cf96955db363519faab9a78e166c453. - -Signed-off-by: Tianling Shen ---- - arch/arm/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1955,7 +1955,7 @@ config ARCH_ROCKCHIP - imply ADC - imply CMD_DM - imply DEBUG_UART_BOARD_INIT -- imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399 -+ imply DISTRO_DEFAULTS - imply BOOTSTD_DEFAULTS if !DISTRO_DEFAULTS - imply FAT_WRITE - imply SARADC_ROCKCHIP diff --git a/package/boot/uboot-rockchip/patches/003-Revert-rockchip-Convert-rockpro64-rk3399-to-use-stan.patch b/package/boot/uboot-rockchip/patches/003-Revert-rockchip-Convert-rockpro64-rk3399-to-use-stan.patch deleted file mode 100644 index 2b7fb8dd6..000000000 --- a/package/boot/uboot-rockchip/patches/003-Revert-rockchip-Convert-rockpro64-rk3399-to-use-stan.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 93ac12531f7c672ef1fe7689cf8b67ec2372efef Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Wed, 5 Apr 2023 21:08:27 +0800 -Subject: [PATCH 3/3] Revert "rockchip: Convert rockpro64-rk3399 to use - standard boot" - -This reverts commit 3891c68ef50eda38d78c95ecd03aed030aa6bb53. - -Signed-off-by: Tianling Shen ---- - include/configs/rk3399_common.h | 5 ++++- - include/configs/rockchip-common.h | 2 -- - 2 files changed, 4 insertions(+), 3 deletions(-) - ---- a/include/configs/rk3399_common.h -+++ b/include/configs/rk3399_common.h -@@ -47,12 +47,15 @@ - #define ROCKCHIP_DEVICE_SETTINGS - #endif - -+#include -+#include - #define CFG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ -- "boot_targets=" BOOT_TARGETS "\0" \ -+ BOOTENV \ -+ BOOTENV_SF \ - "altbootcmd=" \ - "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \ - "run distro_bootcmd\0" ---- a/include/configs/rockchip-common.h -+++ b/include/configs/rockchip-common.h -@@ -67,14 +67,12 @@ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) \ - BOOT_TARGET_SF(func) --#define BOOT_TARGETS "mmc1 mmc0 nvme scsi usb pxe dhcp spi" - #else - #define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_MMC(func) \ - BOOT_TARGET_USB(func) \ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) --#define BOOT_TARGETS "mmc1 mmc0 usb pxe dhcp" - #endif - - #ifdef CONFIG_ARM64 diff --git a/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch b/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch index f85455cba..86172d632 100644 --- a/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch +++ b/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch @@ -25,17 +25,17 @@ Signed-off-by: Marty Jones --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - +@@ -168,6 +168,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-evb.dtb \ -+ rk3568-nanopi-r5s.dtb \ + rk3566-anbernic-rgxx3.dtb \ rk3566-radxa-cm3-io.dtb \ ++ rk3568-nanopi-r5s.dtb \ + rk3568-evb.dtb \ rk3568-rock-3a.dtb --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -@@ -0,0 +1,25 @@ +@@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd @@ -50,15 +50,9 @@ Signed-off-by: Marty Jones + }; +}; + -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,dm-spl; -+ u-boot,spl-fifo-mode; -+}; -+ +&uart2 { + clock-frequency = <24000000>; -+ u-boot,dm-spl; ++ bootph-pre-ram; + status = "okay"; +}; --- /dev/null @@ -75,7 +69,7 @@ Signed-off-by: Marty Jones +}; --- /dev/null +++ b/configs/nanopi-r5s-rk3568_defconfig -@@ -0,0 +1,91 @@ +@@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 @@ -88,13 +82,9 @@ Signed-off-by: Marty Jones +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 @@ -103,6 +93,7 @@ Signed-off-by: Marty Jones +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -114,25 +105,22 @@ Signed-off-by: Marty Jones +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ADC=y +CONFIG_SPL_ATF=y -+CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y @@ -144,14 +132,11 @@ Signed-off-by: Marty Jones +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y @@ -164,6 +149,7 @@ Signed-off-by: Marty Jones +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/018-driver-Makefile-support-adc-in-SPL.patch b/package/boot/uboot-rockchip/patches/018-driver-Makefile-support-adc-in-SPL.patch deleted file mode 100644 index 072abfc2e..000000000 --- a/package/boot/uboot-rockchip/patches/018-driver-Makefile-support-adc-in-SPL.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 2d7c904f271ffd19086cafe7cd6548ec5b1a5a83 Mon Sep 17 00:00:00 2001 -From: Jason Zhu -Date: Thu, 12 Mar 2020 15:04:51 +0800 -Subject: [PATCH] driver: Makefile: support adc in SPL - -Signed-off-by: Jason Zhu -Change-Id: I915becbf9597aa070001d3368d8daf9079565fc9 ---- - common/spl/Kconfig | 6 ++++++ - drivers/Makefile | 2 +- - 2 files changed, 7 insertions(+), 1 deletion(-) - ---- a/common/spl/Kconfig -+++ b/common/spl/Kconfig -@@ -587,6 +587,11 @@ config SPL_FIT_IMAGE_TINY - ensure this information is available to the next image - invoked). - -+config SPL_ADC -+ bool "Support ADC drivers in SPL" -+ help -+ Enable ADC drivers in SPL. -+ - config SPL_CACHE - bool "Support CACHE drivers" - help ---- a/drivers/Makefile -+++ b/drivers/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0+ - -+obj-$(CONFIG_$(SPL_)ADC) += adc/ - obj-$(CONFIG_$(SPL_TPL_)BLK) += block/ - obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ - obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ diff --git a/package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch b/package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch deleted file mode 100644 index 54a452d7b..000000000 --- a/package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 79cb33b9da0c9475486ca0759341057854b25e38 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 20 Feb 2022 07:57:50 -0500 -Subject: [PATCH] rockchip: handle bootrom mode in spl - -Signed-off-by: Peter Geis ---- - arch/arm/mach-rockchip/Makefile | 6 +-- - arch/arm/mach-rockchip/boot_mode.c | 4 +- - arch/arm/mach-rockchip/rk3568/rk3568.c | 54 +++++++++++++++++++++++++- - 3 files changed, 59 insertions(+), 5 deletions(-) - ---- a/arch/arm/mach-rockchip/Makefile -+++ b/arch/arm/mach-rockchip/Makefile -@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o - - obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o - --ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) -- - # Always include boot_mode.o, as we bypass it (i.e. turn it off) - # inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way, - # we can have the preprocessor correctly recognise both 0x0 and 0 - # meaning "turn it off". --obj-y += boot_mode.o -+obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o -+ -+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) - obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o - obj-$(CONFIG_MISC_INIT_R) += misc.o - endif ---- a/arch/arm/mach-rockchip/boot_mode.c -+++ b/arch/arm/mach-rockchip/boot_mode.c -@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void) - ret = -ENODEV; - uclass_foreach_dev(dev, uc) { - if (!strncmp(dev->name, "saradc", 6)) { -- ret = adc_channel_single_shot(dev->name, 1, &val); -+ ret = adc_channel_single_shot(dev->name, 0, &val); - break; - } - } -@@ -89,6 +89,7 @@ int setup_boot_mode(void) - boot_mode = readl(reg); - debug("%s: boot mode 0x%08x\n", __func__, boot_mode); - -+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) - /* Clear boot mode */ - writel(BOOT_NORMAL, reg); - -@@ -102,6 +103,7 @@ int setup_boot_mode(void) - env_set("preboot", "setenv preboot; ums mmc 0"); - break; - } -+#endif - - return 0; - } ---- a/arch/arm/mach-rockchip/rk3568/rk3568.c -+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c -@@ -9,19 +9,30 @@ - #include - #include - #include -+#include - #include - #include - #include - - #define PMUGRF_BASE 0xfdc20000 - #define GRF_BASE 0xfdc60000 -+#define GRF_GPIO1B_IOMUX_H 0x0c -+#define GRF_GPIO1C_IOMUX_L 0x10 -+#define GRF_GPIO1C_IOMUX_H 0x14 -+#define GRF_GPIO1D_IOMUX_L 0x18 -+#define GRF_GPIO1D_IOMUX_H 0x1c -+#define GRF_GPIO2A_IOMUX_L 0x20 - #define GRF_GPIO1B_DS_2 0x218 - #define GRF_GPIO1B_DS_3 0x21c - #define GRF_GPIO1C_DS_0 0x220 - #define GRF_GPIO1C_DS_1 0x224 - #define GRF_GPIO1C_DS_2 0x228 - #define GRF_GPIO1C_DS_3 0x22c --#define SGRF_BASE 0xFDD18000 -+#define GRF_GPIO1D_DS_0 0x230 -+#define GRF_GPIO1D_DS_1 0x234 -+#define GRF_GPIO1D_DS_2 0x238 -+#define SGRF_BASE 0xfdd18000 -+#define SGRF_SOC_CON3 0x0c - #define SGRF_SOC_CON4 0x10 - #define EMMC_HPROT_SECURE_CTRL 0x03 - #define SDMMC0_HPROT_SECURE_CTRL 0x01 -@@ -133,6 +144,24 @@ int arch_cpu_init(void) - writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); - writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); - writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); -+ -+ /* emmc, sfc, and sdmmc iomux */ -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H); -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L); -+ writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H); -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L); -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_H); -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO2A_IOMUX_L); -+ -+ /* set the fspi d0~3 cs0 to level 2 */ -+ writel(0x3f000700, GRF_BASE + GRF_GPIO1C_DS_3); -+ writel(0x3f000700, GRF_BASE + GRF_GPIO1D_DS_0); -+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1D_DS_1); -+ writel(0x003f0007, GRF_BASE + GRF_GPIO1D_DS_2); -+ -+ /* Set the fspi to secure */ -+ writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3); -+ - #endif - return 0; - } -@@ -164,3 +193,26 @@ int ft_system_setup(void *blob, struct bd_info *bd) - #endif - return 0; - } -+ -+#ifdef CONFIG_SPL_BUILD -+ -+void __weak led_setup(void) -+{ -+} -+ -+void spl_board_init(void) -+{ -+ led_setup(); -+ -+#if defined(SPL_DM_REGULATOR) -+ /* -+ * Turning the eMMC and SPI back on (if disabled via the Qseven -+ * BIOS_ENABLE) signal is done through a always-on regulator). -+ */ -+ if (regulators_enable_boot_on(false)) -+ debug("%s: Cannot enable boot on regulator\n", __func__); -+#endif -+ -+ setup_boot_mode(); -+} -+#endif diff --git a/package/boot/uboot-rockchip/patches/020-update-rock-3a-defconfig.patch b/package/boot/uboot-rockchip/patches/020-update-rock-3a-defconfig.patch index 6f16a266b..df99a80b0 100644 --- a/package/boot/uboot-rockchip/patches/020-update-rock-3a-defconfig.patch +++ b/package/boot/uboot-rockchip/patches/020-update-rock-3a-defconfig.patch @@ -1,45 +1,10 @@ --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig -@@ -39,6 +39,8 @@ - CONFIG_CMD_GPT=y - CONFIG_CMD_I2C=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y - # CONFIG_CMD_SETEXPR is not set - # CONFIG_SPL_DOS_PARTITION is not set - CONFIG_SPL_OF_CONTROL=y -@@ -47,6 +49,8 @@ - CONFIG_SPL_REGMAP=y - CONFIG_SPL_SYSCON=y - CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MISC=y -@@ -61,7 +65,11 @@ - CONFIG_DM_PMIC=y - CONFIG_PMIC_RK8XX=y - CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y - CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y - CONFIG_REGULATOR_RK8XX=y - CONFIG_PWM_ROCKCHIP=y - CONFIG_SPL_RAM=y -@@ -69,5 +77,11 @@ - CONFIG_DEBUG_UART_SHIFT=2 - CONFIG_SYS_NS16550_MEM32=y - CONFIG_SYSRESET=y --# CONFIG_BINMAN_FDT is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y - CONFIG_ERRNO_STR=y +@@ -25,7 +25,6 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +-CONFIG_SPL_FIT_SIGNATURE=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_LEGACY_IMAGE_FORMAT=y + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb" diff --git a/package/boot/uboot-rockchip/patches/120-clk-scmi-Add-Kconfig-option-for-SPL.patch b/package/boot/uboot-rockchip/patches/120-clk-scmi-Add-Kconfig-option-for-SPL.patch deleted file mode 100644 index bb6d96515..000000000 --- a/package/boot/uboot-rockchip/patches/120-clk-scmi-Add-Kconfig-option-for-SPL.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 734b9d9e33919efbec63b1bfe48f25ce16dbd59a Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 17 Mar 2023 19:16:45 +0000 -Subject: [PATCH] clk: scmi: Add Kconfig option for SPL - -Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options -enabled and SPL_FIRMWARE disabled result in the following error. - - drivers/clk/clk_scmi.o: in function `scmi_clk_gate': - drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg' - drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno' - drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate': - drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg' - drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno' - drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate': - drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg' - drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno' - drivers/clk/clk_scmi.o: in function `scmi_clk_probe': - drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel' - make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 - make: *** [Makefile:2043: spl/u-boot-spl] Error 2 - -Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this. - -Signed-off-by: Jonas Karlman -Reviewed-by: Kever Yang -Link: https://patchwork.ozlabs.org/project/uboot/patch/20230317191638.2558279-2-jonas@kwiboo.se/ ---- - drivers/clk/Kconfig | 8 ++++++++ - drivers/clk/Makefile | 2 +- - drivers/firmware/scmi/scmi_agent-uclass.c | 2 +- - 3 files changed, 10 insertions(+), 2 deletions(-) - ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -166,6 +166,14 @@ config CLK_SCMI - by a SCMI agent based on SCMI clock protocol communication - with a SCMI server. - -+config SPL_CLK_SCMI -+ bool "Enable SCMI clock driver in SPL" -+ depends on SCMI_FIRMWARE && SPL_FIRMWARE -+ help -+ Enable this option if you want to support clock devices exposed -+ by a SCMI agent based on SCMI clock protocol communication -+ with a SCMI server in SPL. -+ - config CLK_HSDK - bool "Enable cgu clock driver for HSDK boards" - depends on CLK && TARGET_HSDK ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -39,7 +39,7 @@ obj-$(CONFIG_CLK_MVEBU) += mvebu/ - obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o - obj-$(CONFIG_CLK_OWL) += owl/ - obj-$(CONFIG_CLK_RENESAS) += renesas/ --obj-$(CONFIG_CLK_SCMI) += clk_scmi.o -+obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o - obj-$(CONFIG_CLK_SIFIVE) += sifive/ - obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ - obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o ---- a/drivers/firmware/scmi/scmi_agent-uclass.c -+++ b/drivers/firmware/scmi/scmi_agent-uclass.c -@@ -75,7 +75,7 @@ static int scmi_bind_protocols(struct udevice *dev) - name = ofnode_get_name(node); - switch (protocol_id) { - case SCMI_PROTOCOL_ID_CLOCK: -- if (IS_ENABLED(CONFIG_CLK_SCMI)) -+ if (CONFIG_IS_ENABLED(CLK_SCMI)) - drv = DM_DRIVER_GET(scmi_clock); - break; - case SCMI_PROTOCOL_ID_RESET_DOMAIN: diff --git a/package/boot/uboot-rockchip/patches/121-pinctrl-rockchip-Fix-IO-mux-selection-on.patch b/package/boot/uboot-rockchip/patches/121-pinctrl-rockchip-Fix-IO-mux-selection-on.patch deleted file mode 100644 index e6a15ce3c..000000000 --- a/package/boot/uboot-rockchip/patches/121-pinctrl-rockchip-Fix-IO-mux-selection-on.patch +++ /dev/null @@ -1,126 +0,0 @@ -From 7db635cf638dfad08a50e26a6d02e1b6e7a9d7c5 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 18 Mar 2023 23:30:42 +0000 -Subject: [PATCH] pinctrl: rockchip: Fix IO mux selection on RK3568 - -IO mux selection is not working correctly for all pins. Sync mux route -data from linux to add any missing and update wrong trigger pins to fix -this. Also apply the pull-up fix needed for GPIO0 D3-D6. - -Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") -Signed-off-by: Jonas Karlman -Link: https://patchwork.ozlabs.org/project/uboot/patch/20230318233039.799975-1-jonas@kwiboo.se/ ---- - drivers/pinctrl/rockchip/pinctrl-rk3568.c | 66 +++++++++++++---------- - 1 file changed, 38 insertions(+), 28 deletions(-) - ---- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c -+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c -@@ -13,6 +13,12 @@ - #include "pinctrl-rockchip.h" - - static struct rockchip_mux_route_data rk3568_mux_route_data[] = { -+ MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ -+ MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ -+ MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ -+ MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */ -+ MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */ -+ MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ -@@ -33,30 +39,22 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ -@@ -68,7 +66,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ -@@ -81,7 +79,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ -+ MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ -@@ -94,8 +92,11 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ -- MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */ -- MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */ - MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ -@@ -237,6 +238,15 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank, - return ret; - } - -+ /* -+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, -+ * where that pull up value becomes 3. -+ */ -+ if (bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { -+ if (ret == 1) -+ ret = 3; -+ } -+ - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); - diff --git a/package/boot/uboot-rockchip/patches/210-rockchip-rk35xx-Fix-boot-with-a-large-fdt-blob.patch b/package/boot/uboot-rockchip/patches/210-rockchip-rk35xx-Fix-boot-with-a-large-fdt-blob.patch deleted file mode 100644 index ea7d5ddef..000000000 --- a/package/boot/uboot-rockchip/patches/210-rockchip-rk35xx-Fix-boot-with-a-large-fdt-blob.patch +++ /dev/null @@ -1,43 +0,0 @@ -From c13b8e588bd2da6381a6d337df51acb2a61f03b8 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 21 Mar 2023 21:43:07 +0000 -Subject: [PATCH] rockchip: rk35xx: Fix boot with a large fdt blob - -The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf -v2.3. Mainline atf v2.3 contains an issue that could lead to a crash -when it fails to parse the fdt blob being passed as the platform param. -An issue that was fixed in atf v2.4. - -The vendor TF-A seem to suffer from a similar issue, and this prevents -booting when fdt blob is large enough to trigger this condition. - -Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a -NULL pointer instead of the fdt blob as the platform param. - -This fixes booting Radxa ROCK 3A after recent sync of device tree. - -Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux") -Signed-off-by: Jonas Karlman -Link: https://patchwork.ozlabs.org/project/uboot/patch/20230321214301.2590326-4-jonas@kwiboo.se/ ---- - arch/arm/mach-rockchip/Kconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/mach-rockchip/Kconfig -+++ b/arch/arm/mach-rockchip/Kconfig -@@ -288,6 +288,7 @@ config ROCKCHIP_RK3568 - select BOARD_LATE_INIT - select DM_REGULATOR_FIXED - select DM_RESET -+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD - imply ROCKCHIP_OTP - imply MISC_INIT_R -@@ -309,6 +310,7 @@ config ROCKCHIP_RK3588 - select REGMAP - select SYSCON - select BOARD_LATE_INIT -+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - imply ROCKCHIP_COMMON_BOARD - imply ROCKCHIP_OTP - imply MISC_INIT_R diff --git a/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch deleted file mode 100644 index 02291e29b..000000000 --- a/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ /dev/null @@ -1,196 +0,0 @@ -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index d3e89ca3ba..d5f64ac432 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ -+ rk3328-nanopi-r2c.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-orangepi-r1-plus.dtb \ - rk3328-roc-cc.dtb \ -diff --git a/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi -new file mode 100644 -index 0000000000..c2e86d0f0e ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd -+ * (C) Copyright 2021 Tianling Shen -+ */ -+ -+#include "rk3328-nanopi-r2s-u-boot.dtsi" -diff --git a/arch/arm/dts/rk3328-nanopi-r2c.dts b/arch/arm/dts/rk3328-nanopi-r2c.dts -new file mode 100644 -index 0000000000..adf91a0306 ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2021 Tianling Shen -+ */ -+ -+/dts-v1/; -+ -+#include "rk3328-nanopi-r2s.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R2C"; -+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8521s>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8521s: ethernet-phy@3 { -+ compatible = "ethernet-phy-id0000.011a", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&lan_led { -+ label = "nanopi-r2c:green:lan"; -+}; -+ -+&sys_led { -+ label = "nanopi-r2c:red:sys"; -+}; -+ -+&wan_led { -+ label = "nanopi-r2c:green:wan"; -+}; -diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig -new file mode 100644 -index 0000000000..7bc7a3274f ---- /dev/null -+++ b/configs/nanopi-r2c-rk3328_defconfig -@@ -0,0 +1,112 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" -+CONFIG_DM_RESET=y -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x2000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C=y -+CONFIG_SPL_POWER=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_SYS_MMC_ENV_DEV=1 -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSINFO=y -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/309-rockchip-rk3399-Add-support-for-dilusense-dlfr100.patch b/package/boot/uboot-rockchip/patches/309-rockchip-rk3399-Add-support-for-dilusense-dlfr100.patch index f4bf46212..cdfd93495 100644 --- a/package/boot/uboot-rockchip/patches/309-rockchip-rk3399-Add-support-for-dilusense-dlfr100.patch +++ b/package/boot/uboot-rockchip/patches/309-rockchip-rk3399-Add-support-for-dilusense-dlfr100.patch @@ -695,7 +695,7 @@ +}; + +&sdmmc { -+ u-boot,dm-pre-reloc; ++ bootph-all; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; diff --git a/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch b/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch index fc6fa5c43..f3ac8489d 100644 --- a/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch +++ b/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch @@ -1,16 +1,16 @@ --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-evb.dtb \ + rk3566-anbernic-rgxx3.dtb \ + rk3566-radxa-cm3-io.dtb \ + rk3568-mrkaio-m68s.dtb \ rk3568-nanopi-r5s.dtb \ - rk3566-radxa-cm3-io.dtb \ + rk3568-evb.dtb \ rk3568-rock-3a.dtb --- /dev/null +++ b/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi -@@ -0,0 +1,21 @@ +@@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" @@ -22,19 +22,14 @@ + }; +}; + -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ +&uart2 { -+ u-boot,dm-spl; + clock-frequency = <24000000>; ++ bootph-pre-ram; + status = "okay"; +}; --- /dev/null +++ b/arch/arm/dts/rk3568-mrkaio-m68s.dts -@@ -0,0 +1,263 @@ +@@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3568-evb.dts" @@ -43,264 +38,9 @@ + model = "EZPRO Mrkaio M68S"; + compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568"; +}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ rockchip,system-power-controller; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; --- /dev/null +++ b/configs/mrkaio-m68s-rk3568_defconfig -@@ -0,0 +1,91 @@ +@@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 @@ -313,13 +53,9 @@ +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-mrkaio-m68s" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 @@ -328,6 +64,7 @@ +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-mrkaio-m68s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -339,25 +76,22 @@ +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ADC=y +CONFIG_SPL_ATF=y -+CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y @@ -369,14 +103,11 @@ +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y @@ -389,6 +120,7 @@ +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch b/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch index accaa38d7..0d9c207e6 100644 --- a/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch +++ b/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch @@ -1,16 +1,16 @@ --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-evb.dtb \ -+ rk3568-opc-h68k.dtb \ +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-radxa-cm3-io.dtb \ rk3568-mrkaio-m68s.dtb \ rk3568-nanopi-r5s.dtb \ - rk3566-radxa-cm3-io.dtb \ ++ rk3568-opc-h68k.dtb \ + rk3568-evb.dtb \ + rk3568-rock-3a.dtb + --- /dev/null +++ b/arch/arm/dts/rk3568-opc-h68k-u-boot.dtsi -@@ -0,0 +1,21 @@ +@@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" @@ -22,19 +22,14 @@ + }; +}; + -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ +&uart2 { -+ u-boot,dm-spl; + clock-frequency = <24000000>; ++ bootph-pre-ram; + status = "okay"; +}; --- /dev/null +++ b/arch/arm/dts/rk3568-opc-h68k.dts -@@ -0,0 +1,272 @@ +@@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3568-evb.dts" @@ -44,272 +39,24 @@ + compatible = "hinlink,opc-h68k", "rockchip,rk3568"; +}; + -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_otg>; +}; + -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb_otg>; +}; + -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_usb_otg>; +}; + -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; -+ #clock-cells = <1>; -+ clock-names = "mclk"; -+ clocks = <&cru I2S1_MCLKOUT_TX>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; -+ rockchip,system-power-controller; -+ #sound-dai-cells = <0>; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ -+ codec { -+ mic-in-differential; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; ++&vcc5v0_usb_host { ++ status = "disabled"; +}; --- /dev/null +++ b/configs/opc-h68k-rk3568_defconfig -@@ -0,0 +1,91 @@ +@@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 @@ -322,13 +69,9 @@ +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h68k" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 @@ -337,6 +80,7 @@ +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h68k.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -348,25 +92,22 @@ +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ADC=y +CONFIG_SPL_ATF=y -+CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y @@ -378,14 +119,11 @@ +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y @@ -398,6 +136,7 @@ +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch b/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch index de01269e5..7c2cee6ea 100644 --- a/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch +++ b/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch @@ -1,13 +1,13 @@ --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ +@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3568-nanopi-r5s.dtb \ + rk3568-opc-h68k.dtb \ rk3568-evb.dtb \ + rk3568-r66s.dtb \ - rk3568-opc-h68k.dtb \ - rk3568-mrkaio-m68s.dtb \ - rk3568-nanopi-r5s.dtb \ + rk3568-rock-3a.dtb + + dtb-$(CONFIG_ROCKCHIP_RK3588) += \ --- /dev/null +++ b/arch/arm/dts/rk3568-r66s-u-boot.dtsi @@ -0,0 +1,21 @@ @@ -28,7 +28,7 @@ +}; + +&uart2 { -+ u-boot,dm-spl; ++ bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; @@ -39,7 +39,7 @@ +#include "rk3568-evb.dts" --- /dev/null +++ b/configs/r66s-rk3568_defconfig -@@ -0,0 +1,91 @@ +@@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 @@ -52,13 +52,9 @@ +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-r66s" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 @@ -67,6 +63,7 @@ +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-r66s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -78,25 +75,22 @@ +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ADC=y +CONFIG_SPL_ATF=y -+CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y @@ -108,14 +102,11 @@ +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y @@ -128,6 +119,7 @@ +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch b/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch index 26531f379..65196c4ad 100644 --- a/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch +++ b/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch @@ -10,7 +10,7 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 --- /dev/null +++ b/configs/station-p2-rk3568_defconfig -@@ -0,0 +1,87 @@ +@@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 @@ -23,12 +23,9 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 @@ -37,6 +34,7 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -54,17 +52,16 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y @@ -76,16 +73,14 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_REGULATOR_PWM=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y @@ -95,6 +90,7 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-photonicat.patch b/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-photonicat.patch index 35dd32e67..f8d3f50ff 100644 --- a/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-photonicat.patch +++ b/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-photonicat.patch @@ -1,16 +1,16 @@ --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3568-opc-h68k.dtb \ +@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-radxa-cm3-io.dtb \ rk3568-mrkaio-m68s.dtb \ rk3568-nanopi-r5s.dtb \ + rk3568-photonicat.dtb \ - rk3566-radxa-cm3-io.dtb \ - rk3568-rock-3a.dtb - + rk3568-opc-h68k.dtb \ + rk3568-evb.dtb \ + rk3568-r66s.dtb \ --- /dev/null +++ b/arch/arm/dts/rk3568-photonicat-u-boot.dtsi -@@ -0,0 +1,33 @@ +@@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" @@ -23,26 +23,21 @@ +}; + +&gpio0 { -+ u-boot,dm-spl; ++ bootph-all; +}; + +&pinctrl { -+ u-boot,dm-spl; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; ++ bootph-all; +}; + +&uart2 { -+ u-boot,dm-spl; + clock-frequency = <24000000>; ++ bootph-pre-ram; + status = "okay"; +}; + +&vcc3v3_sd { -+ u-boot,dm-spl; ++ bootph-all; +}; --- /dev/null +++ b/arch/arm/dts/rk3568-photonicat.dts @@ -62,7 +57,7 @@ + stdout-path = "serial2:1500000n8"; + }; + -+ vcc3v3_sd: vcc3v3_sd { ++ vcc3v3_sd: vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; @@ -103,7 +98,7 @@ +}; --- /dev/null +++ b/configs/photonicat-rk3568_defconfig -@@ -0,0 +1,94 @@ +@@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 @@ -116,13 +111,9 @@ +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-photonicat" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_GPIO=y -+CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 @@ -131,6 +122,7 @@ +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-photonicat.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -142,31 +134,25 @@ +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ADC=y +CONFIG_SPL_ATF=y -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y -+CONFIG_MMC_IO_VOLTAGE=y -+CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y @@ -175,14 +161,11 @@ +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y @@ -195,6 +178,7 @@ +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch b/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch index f07e184af..2ad62954f 100644 --- a/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch +++ b/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch @@ -1,9 +1,9 @@ --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -177,7 +177,8 @@ rk3568-evb.dtb \ - rk3568-nanopi-r5s.dtb \ - rk3568-photonicat.dtb \ - rk3566-radxa-cm3-io.dtb \ + rk3568-opc-h68k.dtb \ + rk3568-evb.dtb \ + rk3568-r66s.dtb \ - rk3568-rock-3a.dtb + rk3568-rock-3a.dtb \ + rk3568-radxa-e25.dtb @@ -12,7 +12,7 @@ rk3588-edgeble-neu6a-io.dtb \ --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi -@@ -0,0 +1,21 @@ +@@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" @@ -24,14 +24,9 @@ + }; +}; + -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ +&uart2 { -+ u-boot,dm-spl; + clock-frequency = <24000000>; ++ bootph-pre-ram; + status = "okay"; +}; --- /dev/null @@ -47,7 +42,7 @@ +}; --- /dev/null +++ b/configs/radxa-e25-rk3568_defconfig -@@ -0,0 +1,89 @@ +@@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 @@ -60,13 +55,9 @@ +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 @@ -75,6 +66,7 @@ +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -86,25 +78,22 @@ +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ADC=y +CONFIG_SPL_ATF=y -+CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y @@ -116,12 +105,11 @@ +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_REGULATOR_PWM=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y @@ -134,6 +122,7 @@ +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/316-rockchip-rk3568-Add-support-for-lyt_t68m.patch b/package/boot/uboot-rockchip/patches/316-rockchip-rk3568-Add-support-for-lyt_t68m.patch index 409f35feb..09eccc3d8 100644 --- a/package/boot/uboot-rockchip/patches/316-rockchip-rk3568-Add-support-for-lyt_t68m.patch +++ b/package/boot/uboot-rockchip/patches/316-rockchip-rk3568-Add-support-for-lyt_t68m.patch @@ -1,16 +1,16 @@ --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ +@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3568-nanopi-r5s.dtb \ + rk3568-photonicat.dtb \ + rk3568-opc-h68k.dtb \ ++ rk3568-lyt-t68m.dtb \ rk3568-evb.dtb \ rk3568-r66s.dtb \ -+ rk3568-lyt-t68m.dtb \ - rk3568-opc-h68k.dtb \ - rk3568-mrkaio-m68s.dtb \ - rk3568-nanopi-r5s.dtb \ + rk3568-rock-3a.dtb \ --- /dev/null +++ b/arch/arm/dts/rk3568-lyt-t68m-u-boot.dtsi -@@ -0,0 +1,21 @@ +@@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" @@ -22,19 +22,14 @@ + }; +}; + -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ +&uart2 { -+ u-boot,dm-spl; + clock-frequency = <24000000>; ++ bootph-pre-ram; + status = "okay"; +}; --- /dev/null +++ b/arch/arm/dts/rk3568-lyt-t68m.dts -@@ -0,0 +1,272 @@ +@@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3568-evb.dts" @@ -43,273 +38,9 @@ + model = "LYT T68M"; + compatible = "lyt,t68m", "rockchip,rk3568"; +}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; -+ #clock-cells = <1>; -+ clock-names = "mclk"; -+ clocks = <&cru I2S1_MCLKOUT_TX>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; -+ rockchip,system-power-controller; -+ #sound-dai-cells = <0>; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ -+ codec { -+ mic-in-differential; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; --- /dev/null +++ b/configs/lyt-t68m-rk3568_defconfig -@@ -0,0 +1,91 @@ +@@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 @@ -322,13 +53,9 @@ +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-lyt-t68m" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 @@ -337,6 +64,7 @@ +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lyt-t68m.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -348,25 +76,22 @@ +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ADC=y +CONFIG_SPL_ATF=y -+CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y @@ -378,14 +103,11 @@ +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y @@ -398,6 +120,7 @@ +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y