From b5fa901e0bd563cc399ba905c759b7ce30946e6e Mon Sep 17 00:00:00 2001 From: CN_SZTL <22235437+1715173329@users.noreply.github.com> Date: Sat, 3 Oct 2020 00:27:34 +0800 Subject: [PATCH] rockchip: improve FriendlyElec NanoPi R2S support (#5578) * rockchip: refresh NanoPi R2S patches Update the patches for the NanoPi R2S to the v3 sent (and accepted) upstream. Signed-off-by: David Bauer * rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY This adds the compatible property to the NanoPi R2S ethernet PHY node. Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff when it is still in reset. Signed-off-by: David Bauer * uboot-rockchip: update NanoPi R2S patches Update the patches required for the NanoPi R2S to match the DTS accepted for upstream Linux. The U-Boot patch meanwhile is still pending upstream. Signed-off-by: David Bauer * rockchip: refresh target patches Signed-off-by: CN_SZTL Co-authored-by: CN_SZTL Co-authored-by: wevsty * rockchip: fix NanoPi R2S PHY ID Fix the PHY ID for the NanoPi R2S PHY compatible to match the used PHY. The ID was wrong as I've accidentally picked the wrong upstream patch. Signed-off-by: David Bauer Co-authored-by: David Bauer Co-authored-by: wevsty --- package/boot/uboot-rockchip/Makefile | 1 + ...Add-support-for-FriendlyARM-NanoPi-R.patch | 295 +++++++------ .../nanopi-r2s-rk3328/dt-platdata.c | 18 +- .../nanopi-r2s-rk3328/dt-structs-gen.h | 6 +- ...Add-support-for-FriendlyARM-NanoPi-R.patch | 276 +++++++------ ...add-hwmon-support-for-SoCs-and-GPUs.patch} | 0 ...nable-i2c0-on-FriendlyARM-NanoPi-R2S.patch | 15 - ...ip-add-more-cpu-operating-points-for.patch | 44 ++ ...ckchip-rk3328-allow-higher-frequency.patch | 20 - ...hip-Add-txpbl-node-for-RK3399-RK3328.patch | 4 +- ...4-dts-rockchip-Add-RK3328-idle-state.patch | 74 ++++ ...add-compatible-to-NanoPi-R2S-etherne.patch | 25 ++ ...r8152-add-LED-configuration-from-OF.patch} | 0 ...t-add-RTL8152-binding-documentation.patch} | 0 ...-rockchip-use-system-LED-for-OpenWrt.patch | 29 +- ...usb3-controller-node-for-RK3328-SoCs.patch | 2 +- ...ckchip-enable-LAN-port-on-NanoPi-R2S.patch | 18 +- ...dd-OF-node-for-USB-eth-on-NanoPi-R2S.patch | 2 +- ...8-add-i2c0-controller-for-nanopi-r2s.patch | 22 + ...-for-rockchip-hardware-random-number.patch | 388 ++++++++++++++++++ ...ip-add-hardware-random-number-genera.patch | 50 +++ ...p-enable-hardware-rng-for-NanoPi-R2S.patch | 19 + 22 files changed, 994 insertions(+), 314 deletions(-) rename target/linux/rockchip/patches-5.4/{104-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch => 002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch} (100%) delete mode 100644 target/linux/rockchip/patches-5.4/002-rockchip-rk3328-Enable-i2c0-on-FriendlyARM-NanoPi-R2S.patch create mode 100644 target/linux/rockchip/patches-5.4/003-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch delete mode 100644 target/linux/rockchip/patches-5.4/003-rockchip-rk3328-allow-higher-frequency.patch create mode 100644 target/linux/rockchip/patches-5.4/005-arm64-dts-rockchip-Add-RK3328-idle-state.patch create mode 100644 target/linux/rockchip/patches-5.4/006-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch rename target/linux/rockchip/patches-5.4/{005-net-usb-r8152-add-LED-configuration-from-OF.patch => 007-net-usb-r8152-add-LED-configuration-from-OF.patch} (100%) rename target/linux/rockchip/patches-5.4/{006-dt-bindings-net-add-RTL8152-binding-documentation.patch => 008-dt-bindings-net-add-RTL8152-binding-documentation.patch} (100%) create mode 100644 target/linux/rockchip/patches-5.4/104-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch create mode 100644 target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch create mode 100644 target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch create mode 100644 target/linux/rockchip/patches-5.4/107-rockchip-enable-hardware-rng-for-NanoPi-R2S.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index e5c49d00b..1dbdcb531 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -6,6 +6,7 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_VERSION:=2020.07 +PKG_RELEASE:=2 PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a diff --git a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch index bc65fb69e..ddda14693 100644 --- a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -1,4 +1,4 @@ -From 67f4c228c2bf515386cd54073104dc2e6eae85ea Mon Sep 17 00:00:00 2001 +From 64d37d74519eb5d4dcff8e9164d18f524aa72c8d Mon Sep 17 00:00:00 2001 From: David Bauer Date: Fri, 10 Jul 2020 14:58:30 +0200 Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S @@ -17,11 +17,11 @@ WAN - LAN - SYS LED Signed-off-by: David Bauer --- arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 34 +++ - arch/arm/dts/rk3328-nanopi-r2s.dts | 334 +++++++++++++++++++++ + arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 40 +++ + arch/arm/dts/rk3328-nanopi-r2s.dts | 387 +++++++++++++++++++++ board/rockchip/evb_rk3328/MAINTAINERS | 7 + configs/nanopi-r2s-rk3328_defconfig | 99 ++++++ - 5 files changed, 475 insertions(+) + 5 files changed, 534 insertions(+) create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts create mode 100644 configs/nanopi-r2s-rk3328_defconfig @@ -38,7 +38,7 @@ Signed-off-by: David Bauer rk3328-rock-pi-e.dtb --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi -@@ -0,0 +1,34 @@ +@@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd @@ -73,9 +73,15 @@ Signed-off-by: David Bauer +&vcc_sd { + u-boot,dm-spl; +}; ++ ++&gmac2io { ++ snps,reset-active-low; ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-delays-us = <0 10000 50000>; ++}; --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts -@@ -0,0 +1,334 @@ +@@ -0,0 +1,387 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 David Bauer @@ -88,92 +94,103 @@ Signed-off-by: David Bauer +#include "rk3328.dtsi" + +/ { -+ model = "FriendlyARM NanoPi R2S"; ++ model = "FriendlyElec NanoPi R2S"; + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + -+ gmac_clkin: external-gmac-clock { ++ gmac_clk: gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; ++ clock-output-names = "gmac_clk"; + #clock-cells = <0>; + }; + -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&reset_button_pin>; + pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0m1_gpio>; -+ regulator-name = "vcc_sd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_io>; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <50>; ++ }; + }; + -+ vcc_sdio: sdmmcio-regulator { -+ compatible = "regulator-gpio"; -+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio_vcc_pin>; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_sdio"; -+ regulator-settling-time-us = <5000>; -+ regulator-type = "voltage"; -+ vin-supply = <&vcc_io>; -+ }; -+ -+ vcc_sys: vcc-sys { ++ vcc_rtl8153: vcc-rtl8153-regulator { + compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; ++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtl8153_en_drv>; + regulator-always-on; -+ regulator-boot-on; ++ regulator-name = "vcc_rtl8153"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; ++ enable-active-high; + }; + + leds { + compatible = "gpio-leds"; -+ ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; -+ pinctrl-0 = <&led_pins>; + -+ sys { -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r2s:red:sys"; -+ }; -+ -+ lan { ++ lan_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:lan"; + }; + -+ wan { ++ sys_led: led-1 { ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r2s:red:sys"; ++ }; ++ ++ wan_led: led-2 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:wan"; + }; + }; + -+ gpio_keys { -+ compatible = "gpio-keys-polled"; -+ poll-interval = <100>; -+ ++ vcc_io_sdio: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&sdio_vcc_pin>; + pinctrl-names = "default"; -+ pinctrl-0 = <&button_pins>; ++ regulator-name = "vcc_io_sdio"; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-settling-time-us = <5000>; ++ regulator-type = "voltage"; ++ startup-delay-us = <2000>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ vin-supply = <&vcc_io_33>; ++ }; + -+ reset { -+ label = "Reset Button"; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <50>; -+ }; ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_gpio>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_sd"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io_33>; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; + }; +}; + @@ -195,19 +212,16 @@ Signed-off-by: David Bauer + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; + clock_in_out = "input"; -+ phy-supply = <&vcc_io>; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; -+ pinctrl-names = "default"; ++ phy-supply = <&vcc_io_33>; + pinctrl-0 = <&rgmiim1_pins>; -+ snps,aal; -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ tx_delay = <0x24>; ++ pinctrl-names = "default"; + rx_delay = <0x18>; ++ snps,aal; ++ tx_delay = <0x24>; + status = "okay"; + + mdio { @@ -215,8 +229,13 @@ Signed-off-by: David Bauer + #address-cells = <1>; + #size-cells = <0>; + -+ rtl8211e: ethernet-phy@0 { -+ reg = <0>; ++ rtl8211e: ethernet-phy@1 { ++ reg = <1>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -224,35 +243,36 @@ Signed-off-by: David Bauer +&i2c1 { + status = "okay"; + -+ rk805: rk805@18 { ++ rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; -+ interrupt-parent = <&gpio2>; -+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; -+ pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; ++ pinctrl-names = "default"; + rockchip,system-power-controller; + wakeup-source; + -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_io>; -+ vcc6-supply = <&vcc_sys>; ++ vcc1-supply = <&vdd_5v>; ++ vcc2-supply = <&vdd_5v>; ++ vcc3-supply = <&vdd_5v>; ++ vcc4-supply = <&vdd_5v>; ++ vcc5-supply = <&vcc_io_33>; ++ vcc6-supply = <&vdd_5v>; + + regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; ++ vdd_log: DCDC_REG1 { ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; -+ regulator-always-on; -+ regulator-boot-on; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; @@ -261,11 +281,12 @@ Signed-off-by: David Bauer + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; ++ regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; -+ regulator-always-on; -+ regulator-boot-on; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; @@ -276,17 +297,19 @@ Signed-off-by: David Bauer + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; ++ + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + -+ vcc_io: DCDC_REG4 { -+ regulator-name = "vcc_io"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; ++ vcc_io_33: DCDC_REG4 { ++ regulator-name = "vcc_io_33"; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; @@ -295,10 +318,11 @@ Signed-off-by: David Bauer + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; @@ -307,10 +331,11 @@ Signed-off-by: David Bauer + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; @@ -319,10 +344,11 @@ Signed-off-by: David Bauer + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; @@ -330,38 +356,55 @@ Signed-off-by: David Bauer + }; + }; + }; ++ ++ usb { ++ rtl8153_en_drv: rtl8153-en-drv { ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; +}; + +&io_domains { -+ status = "okay"; -+ -+ vccio1-supply = <&vcc_io>; ++ pmuio-supply = <&vcc_io_33>; ++ vccio1-supply = <&vcc_io_33>; + vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_sdio>; ++ vccio3-supply = <&vcc_io_sdio>; + vccio4-supply = <&vcc_18>; -+ vccio5-supply = <&vcc_io>; -+ vccio6-supply = <&vcc_io>; -+ pmuio-supply = <&vcc_io>; ++ vccio5-supply = <&vcc_io_33>; ++ vccio6-supply = <&vcc_io_33>; ++ status = "okay"; +}; + +&pinctrl { -+ leds { -+ led_pins: led-pins { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, -+ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, -+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ button { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + -+ button { -+ button_pins: button-pins { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ ethernet-phy { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { -+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + @@ -372,16 +415,22 @@ Signed-off-by: David Bauer + }; +}; + ++&pwm2 { ++ status = "okay"; ++}; ++ +&sdmmc { + bus-width = <4>; -+ cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; -+ max-frequency = <150000000>; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; -+ vqmmc-supply = <&vcc_sdio>; ++ vqmmc-supply = <&vcc_io_sdio>; + status = "okay"; +}; + @@ -391,16 +440,25 @@ Signed-off-by: David Bauer + status = "okay"; +}; + ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ +&uart2 { + status = "okay"; +}; + -+&u2phy { ++&usb20_otg { + status = "okay"; -+ -+ u2phy_host: host-port { -+ status = "okay"; -+ }; ++ dr_mode = "host"; +}; + +&usb_host0_ehci { @@ -410,6 +468,7 @@ Signed-off-by: David Bauer +&usb_host0_ohci { + status = "okay"; +}; ++ --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c index fa42c1a76..a7c57e72c 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c @@ -19,7 +19,7 @@ U_BOOT_DEVICE(syscon_at_ff100000) = { static const struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { .reg = {0xff440000, 0x1000}, - .rockchip_grf = 0x3a, + .rockchip_grf = 0x3b, }; U_BOOT_DEVICE(clock_controller_at_ff440000) = { .name = "rockchip_rk3328_cru", @@ -49,7 +49,6 @@ U_BOOT_DEVICE(serial_at_ff130000) = { static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = { .bus_width = 0x4, - .cap_mmc_highspeed = true, .cap_sd_highspeed = true, .clocks = { {&dtv_clock_controller_at_ff440000, {317}}, @@ -60,11 +59,15 @@ static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = { .fifo_depth = 0x100, .interrupts = {0x0, 0xc, 0x4}, .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, + .pinctrl_0 = {0x48, 0x49, 0x4a, 0x4b}, .pinctrl_names = "default", .reg = {0xff500000, 0x4000}, + .sd_uhs_sdr104 = true, + .sd_uhs_sdr12 = true, + .sd_uhs_sdr25 = true, + .sd_uhs_sdr50 = true, .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, + .vmmc_supply = 0x4c, .vqmmc_supply = 0x1e, }; U_BOOT_DEVICE(mmc_at_ff500000) = { @@ -75,7 +78,7 @@ U_BOOT_DEVICE(mmc_at_ff500000) = { static const struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = { .ranges = true, - .rockchip_grf = 0x3a, + .rockchip_grf = 0x3b, }; U_BOOT_DEVICE(pinctrl) = { .name = "rockchip_rk3328_pinctrl", @@ -98,9 +101,10 @@ U_BOOT_DEVICE(gpio0_at_ff210000) = { }; static const struct dtd_regulator_fixed dtv_sdmmc_regulator = { - .gpio = {0x60, 0x1e, 0x1}, - .pinctrl_0 = 0x61, + .gpio = {0x61, 0x1e, 0x1}, + .pinctrl_0 = 0x68, .pinctrl_names = "default", + .regulator_boot_on = true, .regulator_max_microvolt = 0x325aa0, .regulator_min_microvolt = 0x325aa0, .regulator_name = "vcc_sd", diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h index 88291627b..499ddb78a 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h @@ -10,6 +10,7 @@ struct dtd_regulator_fixed { fdt32_t gpio[3]; fdt32_t pinctrl_0; const char * pinctrl_names; + bool regulator_boot_on; fdt32_t regulator_max_microvolt; fdt32_t regulator_min_microvolt; const char * regulator_name; @@ -32,7 +33,6 @@ struct dtd_rockchip_rk3328_dmc { }; struct dtd_rockchip_rk3328_dw_mshc { fdt32_t bus_width; - bool cap_mmc_highspeed; bool cap_sd_highspeed; struct phandle_1_arg clocks[4]; bool disable_wp; @@ -42,6 +42,10 @@ struct dtd_rockchip_rk3328_dw_mshc { fdt32_t pinctrl_0[4]; const char * pinctrl_names; fdt64_t reg[2]; + bool sd_uhs_sdr104; + bool sd_uhs_sdr12; + bool sd_uhs_sdr25; + bool sd_uhs_sdr50; bool u_boot_spl_fifo_mode; fdt32_t vmmc_supply; fdt32_t vqmmc_supply; diff --git a/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch index 904a2f31b..69ee8a7c3 100644 --- a/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -1,4 +1,4 @@ -From 749cbb7b1a4bc2244b6af8cd7d8b471d4e33c80f Mon Sep 17 00:00:00 2001 +From 0720be5371c806c1b89936984a321248fa739bea Mon Sep 17 00:00:00 2001 From: David Bauer Date: Fri, 10 Jul 2020 15:57:46 +0200 Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S @@ -17,8 +17,8 @@ WAN - LAN - SYS LED Signed-off-by: David Bauer --- arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 334 ++++++++++++++++++ - 2 files changed, 335 insertions(+) + .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 368 ++++++++++++++++++ + 2 files changed, 369 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts --- a/arch/arm64/boot/dts/rockchip/Makefile @@ -33,7 +33,7 @@ Signed-off-by: David Bauer dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -0,0 +1,334 @@ +@@ -0,0 +1,368 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 David Bauer @@ -46,92 +46,91 @@ Signed-off-by: David Bauer +#include "rk3328.dtsi" + +/ { -+ model = "FriendlyARM NanoPi R2S"; ++ model = "FriendlyElec NanoPi R2S"; + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + -+ gmac_clkin: external-gmac-clock { ++ gmac_clk: gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; -+ clock-output-names = "gmac_clkin"; ++ clock-output-names = "gmac_clk"; + #clock-cells = <0>; + }; + -+ vcc_sd: sdmmc-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&reset_button_pin>; + pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0m1_gpio>; -+ regulator-name = "vcc_sd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_io>; -+ }; + -+ vcc_sdio: sdmmcio-regulator { -+ compatible = "regulator-gpio"; -+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio_vcc_pin>; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_sdio"; -+ regulator-settling-time-us = <5000>; -+ regulator-type = "voltage"; -+ vin-supply = <&vcc_io>; -+ }; -+ -+ vcc_sys: vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; ++ reset { ++ label = "reset"; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <50>; ++ }; + }; + + leds { + compatible = "gpio-leds"; -+ ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; -+ pinctrl-0 = <&led_pins>; + -+ sys { -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "nanopi-r2s:red:sys"; -+ }; -+ -+ lan { ++ lan_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:lan"; + }; + -+ wan { ++ sys_led: led-1 { ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-r2s:red:sys"; ++ }; ++ ++ wan_led: led-2 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:wan"; + }; + }; + -+ gpio_keys { -+ compatible = "gpio-keys-polled"; -+ poll-interval = <100>; -+ ++ vcc_io_sdio: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&sdio_vcc_pin>; + pinctrl-names = "default"; -+ pinctrl-0 = <&button_pins>; ++ regulator-name = "vcc_io_sdio"; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-settling-time-us = <5000>; ++ regulator-type = "voltage"; ++ startup-delay-us = <2000>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ vin-supply = <&vcc_io_33>; ++ }; + -+ reset { -+ label = "Reset Button"; -+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <50>; -+ }; ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_gpio>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_sd"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io_33>; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; + }; +}; + @@ -153,19 +152,16 @@ Signed-off-by: David Bauer + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; -+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; + clock_in_out = "input"; -+ phy-supply = <&vcc_io>; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; -+ pinctrl-names = "default"; ++ phy-supply = <&vcc_io_33>; + pinctrl-0 = <&rgmiim1_pins>; -+ snps,aal; -+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ tx_delay = <0x24>; ++ pinctrl-names = "default"; + rx_delay = <0x18>; ++ snps,aal; ++ tx_delay = <0x24>; + status = "okay"; + + mdio { @@ -173,8 +169,13 @@ Signed-off-by: David Bauer + #address-cells = <1>; + #size-cells = <0>; + -+ rtl8211e: ethernet-phy@0 { -+ reg = <0>; ++ rtl8211e: ethernet-phy@1 { ++ reg = <1>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; @@ -182,35 +183,36 @@ Signed-off-by: David Bauer +&i2c1 { + status = "okay"; + -+ rk805: rk805@18 { ++ rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; -+ interrupt-parent = <&gpio2>; -+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; -+ pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; ++ pinctrl-names = "default"; + rockchip,system-power-controller; + wakeup-source; + -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_io>; -+ vcc6-supply = <&vcc_sys>; ++ vcc1-supply = <&vdd_5v>; ++ vcc2-supply = <&vdd_5v>; ++ vcc3-supply = <&vdd_5v>; ++ vcc4-supply = <&vdd_5v>; ++ vcc5-supply = <&vcc_io_33>; ++ vcc6-supply = <&vdd_5v>; + + regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; ++ vdd_log: DCDC_REG1 { ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; -+ regulator-always-on; -+ regulator-boot-on; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; @@ -219,11 +221,12 @@ Signed-off-by: David Bauer + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; ++ regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; -+ regulator-always-on; -+ regulator-boot-on; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; @@ -234,17 +237,19 @@ Signed-off-by: David Bauer + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; ++ + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + -+ vcc_io: DCDC_REG4 { -+ regulator-name = "vcc_io"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; ++ vcc_io_33: DCDC_REG4 { ++ regulator-name = "vcc_io_33"; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; @@ -253,10 +258,11 @@ Signed-off-by: David Bauer + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; @@ -265,10 +271,11 @@ Signed-off-by: David Bauer + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; @@ -277,10 +284,11 @@ Signed-off-by: David Bauer + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; @@ -291,35 +299,46 @@ Signed-off-by: David Bauer +}; + +&io_domains { -+ status = "okay"; -+ -+ vccio1-supply = <&vcc_io>; ++ pmuio-supply = <&vcc_io_33>; ++ vccio1-supply = <&vcc_io_33>; + vccio2-supply = <&vcc18_emmc>; -+ vccio3-supply = <&vcc_sdio>; ++ vccio3-supply = <&vcc_io_sdio>; + vccio4-supply = <&vcc_18>; -+ vccio5-supply = <&vcc_io>; -+ vccio6-supply = <&vcc_io>; -+ pmuio-supply = <&vcc_io>; ++ vccio5-supply = <&vcc_io_33>; ++ vccio6-supply = <&vcc_io_33>; ++ status = "okay"; +}; + +&pinctrl { -+ leds { -+ led_pins: led-pins { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, -+ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, -+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ button { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + -+ button { -+ button_pins: button-pins { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ ethernet-phy { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { -+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + @@ -330,16 +349,22 @@ Signed-off-by: David Bauer + }; +}; + ++&pwm2 { ++ status = "okay"; ++}; ++ +&sdmmc { + bus-width = <4>; -+ cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; -+ max-frequency = <150000000>; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; -+ vqmmc-supply = <&vcc_sdio>; ++ vqmmc-supply = <&vcc_io_sdio>; + status = "okay"; +}; + @@ -349,16 +374,25 @@ Signed-off-by: David Bauer + status = "okay"; +}; + ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ +&uart2 { + status = "okay"; +}; + -+&u2phy { ++&usb20_otg { + status = "okay"; -+ -+ u2phy_host: host-port { -+ status = "okay"; -+ }; ++ dr_mode = "host"; +}; + +&usb_host0_ehci { diff --git a/target/linux/rockchip/patches-5.4/104-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch b/target/linux/rockchip/patches-5.4/002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/104-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch rename to target/linux/rockchip/patches-5.4/002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch diff --git a/target/linux/rockchip/patches-5.4/002-rockchip-rk3328-Enable-i2c0-on-FriendlyARM-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/002-rockchip-rk3328-Enable-i2c0-on-FriendlyARM-NanoPi-R2S.patch deleted file mode 100644 index 2477e7da2..000000000 --- a/target/linux/rockchip/patches-5.4/002-rockchip-rk3328-Enable-i2c0-on-FriendlyARM-NanoPi-R2S.patch +++ /dev/null @@ -1,15 +0,0 @@ -From: QiuSimons -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -226,6 +226,10 @@ - }; - }; - -+&i2c0 { -+ status = "okay"; -+}; -+ - &io_domains { - status = "okay"; - diff --git a/target/linux/rockchip/patches-5.4/003-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-5.4/003-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch new file mode 100644 index 000000000..ead32d360 --- /dev/null +++ b/target/linux/rockchip/patches-5.4/003-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch @@ -0,0 +1,44 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Leonidas P. Papadakos +Date: Fri, 1 Mar 2019 21:55:53 +0200 +Subject: [PATCH v2] arm64: dts: rockchip: add more cpu operating points for + RK3328 + +This allows for greater max frequency on rk3328 boards, +increasing performance. + +It has been included in Armbian (a linux distibution for ARM boards) +for a while now without any reported issues + +https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1392mhz-opp.patch +https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1512mhz-opp.patch + +Signed-off-by: Leonidas P. Papadakos +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 15 +++++++++++++++ + 1 files changed, 15 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -123,6 +123,21 @@ + opp-microvolt = <1300000>; + clock-latency-ns = <40000>; + }; ++ opp-1392000000 { ++ opp-hz = /bits/ 64 <1392000000>; ++ opp-microvolt = <1350000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1512000000 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <1400000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1450000>; ++ clock-latency-ns = <40000>; ++ }; + }; + + amba { diff --git a/target/linux/rockchip/patches-5.4/003-rockchip-rk3328-allow-higher-frequency.patch b/target/linux/rockchip/patches-5.4/003-rockchip-rk3328-allow-higher-frequency.patch deleted file mode 100644 index 576e46215..000000000 --- a/target/linux/rockchip/patches-5.4/003-rockchip-rk3328-allow-higher-frequency.patch +++ /dev/null @@ -1,20 +0,0 @@ -From: QiuSimons ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -123,6 +123,16 @@ - opp-microvolt = <1300000>; - clock-latency-ns = <40000>; - }; -+ opp-1512000000 { -+ opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <1400000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <1450000>; -+ clock-latency-ns = <40000>; -+ }; - }; - - amba { diff --git a/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch b/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch index 8931d5c5a..cc90bad69 100644 --- a/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch +++ b/target/linux/rockchip/patches-5.4/004-arm64-dts-rockchip-Add-txpbl-node-for-RK3399-RK3328.patch @@ -26,7 +26,7 @@ Signed-off-by: Heiko Stuebner --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -857,6 +857,7 @@ +@@ -872,6 +872,7 @@ resets = <&cru SRST_GMAC2IO_A>; reset-names = "stmmaceth"; rockchip,grf = <&grf>; @@ -34,7 +34,7 @@ Signed-off-by: Heiko Stuebner status = "disabled"; }; -@@ -878,6 +879,7 @@ +@@ -893,6 +894,7 @@ reset-names = "stmmaceth", "mac-phy"; phy-mode = "rmii"; phy-handle = <&phy>; diff --git a/target/linux/rockchip/patches-5.4/005-arm64-dts-rockchip-Add-RK3328-idle-state.patch b/target/linux/rockchip/patches-5.4/005-arm64-dts-rockchip-Add-RK3328-idle-state.patch new file mode 100644 index 000000000..a65f04011 --- /dev/null +++ b/target/linux/rockchip/patches-5.4/005-arm64-dts-rockchip-Add-RK3328-idle-state.patch @@ -0,0 +1,74 @@ +From 4f279f9fbca54464173240f7e73b145a136dfa1e Mon Sep 17 00:00:00 2001 +From: Robin Murphy +Date: Sun, 29 Dec 2019 20:16:17 +0000 +Subject: arm64: dts: rockchip: Add RK3328 idle state + +Downstream RK3328 DTBs describe a CPU idle state matching that present +on other SoCs like RK3399. This works with upstream Trusted Firmware-A +too, so let's add it here. + +Signed-off-by: Robin Murphy +Link: https://lore.kernel.org/r/a8c83e705d387446ea8121516d410e38b2d9c57b.1577640736.git.robin.murphy@arm.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 91306ebed4da2..c9ff1188bd7b1 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -41,6 +41,7 @@ + reg = <0x0 0x0>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; +@@ -53,6 +54,7 @@ + reg = <0x0 0x1>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; +@@ -65,6 +67,7 @@ + reg = <0x0 0x2>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; +@@ -77,12 +80,26 @@ + reg = <0x0 0x3>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; + }; + ++ idle-states { ++ entry-method = "psci"; ++ ++ CPU_SLEEP: cpu-sleep { ++ compatible = "arm,idle-state"; ++ local-timer-stop; ++ arm,psci-suspend-param = <0x0010000>; ++ entry-latency-us = <120>; ++ exit-latency-us = <250>; ++ min-residency-us = <900>; ++ }; ++ }; ++ + l2: l2-cache0 { + compatible = "cache"; + }; +-- +cgit 1.2.3-1.el7 + diff --git a/target/linux/rockchip/patches-5.4/006-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch b/target/linux/rockchip/patches-5.4/006-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch new file mode 100644 index 000000000..897a42fea --- /dev/null +++ b/target/linux/rockchip/patches-5.4/006-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch @@ -0,0 +1,25 @@ +From bc6c96d850419e71dbc9b0094ccc9b668ba9be43 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Mon, 28 Sep 2020 22:54:52 +0200 +Subject: [PATCH] rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY + +This adds the compatible property to the NanoPi R2S ethernet PHY node. +Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff +when it is still in reset. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -134,6 +134,8 @@ + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { ++ compatible = "ethernet-phy-id001c.c915", ++ "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; diff --git a/target/linux/rockchip/patches-5.4/005-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-5.4/007-net-usb-r8152-add-LED-configuration-from-OF.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/005-net-usb-r8152-add-LED-configuration-from-OF.patch rename to target/linux/rockchip/patches-5.4/007-net-usb-r8152-add-LED-configuration-from-OF.patch diff --git a/target/linux/rockchip/patches-5.4/006-dt-bindings-net-add-RTL8152-binding-documentation.patch b/target/linux/rockchip/patches-5.4/008-dt-bindings-net-add-RTL8152-binding-documentation.patch similarity index 100% rename from target/linux/rockchip/patches-5.4/006-dt-bindings-net-add-RTL8152-binding-documentation.patch rename to target/linux/rockchip/patches-5.4/008-dt-bindings-net-add-RTL8152-binding-documentation.patch diff --git a/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch index 1250dbcd9..7f9af85b1 100644 --- a/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch +++ b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch @@ -15,26 +15,17 @@ Signed-off-by: David Bauer --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -17,6 +17,13 @@ - stdout-path = "serial2:1500000n8"; - }; +@@ -13,6 +13,13 @@ + model = "FriendlyElec NanoPi R2S"; + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; + aliases { -+ led-boot = &led_sys; -+ led-failsafe = &led_sys; -+ led-running = &led_sys; -+ led-upgrade = &led_sys; ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; + }; + - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; -@@ -67,7 +74,7 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - -- sys { -+ led_sys: sys { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "nanopi-r2s:red:sys"; - }; + chosen { + stdout-path = "serial2:1500000n8"; + }; diff --git a/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch index 2635c7a67..f6d5f518e 100644 --- a/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch +++ b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch @@ -26,7 +26,7 @@ use-case. You've been warned. --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -938,6 +938,33 @@ +@@ -970,6 +970,33 @@ status = "disabled"; }; diff --git a/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch index e2aa2d67e..aa8f72e84 100644 --- a/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch +++ b/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch @@ -1,4 +1,4 @@ -From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001 +From 7cde8541d04e0ade5d126bdada3cf0c0429eaa99 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Fri, 10 Jul 2020 21:12:16 +0200 Subject: [PATCH] rockchip: enabled LAN port on NanoPi R2S @@ -13,10 +13,11 @@ Signed-off-by: David Bauer --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -68,6 +68,18 @@ +@@ -103,6 +103,18 @@ + regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; - ++ + vcc_rtl8153: vcc-rtl8153-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; @@ -28,11 +29,10 @@ Signed-off-by: David Bauer + regulator-max-microvolt = <5000000>; + enable-active-high; + }; -+ - leds { - compatible = "gpio-leds"; + }; -@@ -299,6 +311,12 @@ + &cpu0 { +@@ -318,6 +330,12 @@ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; @@ -44,8 +44,8 @@ Signed-off-by: David Bauer + }; }; - &sdmmc { -@@ -339,3 +357,12 @@ + &pwm2 { +@@ -373,3 +391,12 @@ &usb_host0_ohci { status = "okay"; }; diff --git a/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch index 3b97ecde9..473c26501 100644 --- a/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch +++ b/target/linux/rockchip/patches-5.4/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch @@ -14,7 +14,7 @@ Signed-off-by: David Bauer --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -365,4 +365,11 @@ +@@ -399,4 +399,11 @@ &usbdrd_dwc3 { dr_mode = "host"; status = "okay"; diff --git a/target/linux/rockchip/patches-5.4/104-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch b/target/linux/rockchip/patches-5.4/104-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch new file mode 100644 index 000000000..30dbcc17a --- /dev/null +++ b/target/linux/rockchip/patches-5.4/104-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch @@ -0,0 +1,22 @@ +From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001 +From: QiuSimons <45143996+QiuSimons@users.noreply.github.com> +Date: Tue, 4 Aug 2020 20:17:53 +0800 +Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s + +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++ + 1 files changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -163,6 +163,10 @@ + }; + }; + ++&i2c0 { ++ status = "okay"; ++}; ++ + &i2c1 { + status = "okay"; + diff --git a/target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch b/target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch new file mode 100644 index 000000000..196cc00ae --- /dev/null +++ b/target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch @@ -0,0 +1,388 @@ +From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001 +From: wevsty +Date: Mon, 24 Aug 2020 02:27:11 +0800 +Subject: [PATCH] char: add support for rockchip hardware random number + generator + +This patch provides hardware random number generator support for all rockchip SOC. + +rockchip-rng.c from https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/char/hw_random/rockchip-rng.c + +Signed-off-by: wevsty +--- + +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -345,6 +345,19 @@ config HW_RANDOM_STM32 + + If unsure, say N. + ++config HW_RANDOM_ROCKCHIP ++ tristate "Rockchip Random Number Generator support" ++ depends on ARCH_ROCKCHIP ++ default HW_RANDOM ++ help ++ This driver provides kernel-side support for the Random Number ++ Generator hardware found on Rockchip cpus. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called rockchip-rng. ++ ++ If unsure, say Y. ++ + config HW_RANDOM_PIC32 + tristate "Microchip PIC32 Random Number Generator support" + depends on HW_RANDOM && MACH_PIC32 +--- /dev/null ++++ b/drivers/char/hw_random/rockchip-rng.c +@@ -0,0 +1,340 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * rockchip-rng.c Random Number Generator driver for the Rockchip ++ * ++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. ++ * Author: Lin Jinhan ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define _SBF(s, v) ((v) << (s)) ++#define HIWORD_UPDATE(val, mask, shift) \ ++ ((val) << (shift) | (mask) << ((shift) + 16)) ++ ++#define ROCKCHIP_AUTOSUSPEND_DELAY 100 ++#define ROCKCHIP_POLL_PERIOD_US 100 ++#define ROCKCHIP_POLL_TIMEOUT_US 10000 ++#define RK_MAX_RNG_BYTE (32) ++ ++/* start of CRYPTO V1 register define */ ++#define CRYPTO_V1_CTRL 0x0008 ++#define CRYPTO_V1_RNG_START BIT(8) ++#define CRYPTO_V1_RNG_FLUSH BIT(9) ++ ++#define CRYPTO_V1_TRNG_CTRL 0x0200 ++#define CRYPTO_V1_OSC_ENABLE BIT(16) ++#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) ++ ++#define CRYPTO_V1_TRNG_DOUT_0 0x0204 ++/* end of CRYPTO V1 register define */ ++ ++/* start of CRYPTO V2 register define */ ++#define CRYPTO_V2_RNG_CTL 0x0400 ++#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) ++#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) ++#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) ++#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) ++#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) ++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) ++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) ++#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) ++#define CRYPTO_V2_RNG_ENABLE BIT(1) ++#define CRYPTO_V2_RNG_START BIT(0) ++#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404 ++#define CRYPTO_V2_RNG_DOUT_0 0x0410 ++/* end of CRYPTO V2 register define */ ++ ++struct rk_rng_soc_data { ++ const char * const *clks; ++ int clks_num; ++ int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait); ++}; ++ ++struct rk_rng { ++ struct device *dev; ++ struct hwrng rng; ++ void __iomem *mem; ++ struct rk_rng_soc_data *soc_data; ++ u32 clk_num; ++ struct clk_bulk_data *clk_bulks; ++}; ++ ++static const char * const rk_rng_v1_clks[] = { ++ "hclk_crypto", ++ "clk_crypto", ++}; ++ ++static const char * const rk_rng_v2_clks[] = { ++ "hclk_crypto", ++ "aclk_crypto", ++ "clk_crypto", ++ "clk_crypto_apk", ++}; ++ ++static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset) ++{ ++ __raw_writel(val, rng->mem + offset); ++} ++ ++static u32 rk_rng_readl(struct rk_rng *rng, u32 offset) ++{ ++ return __raw_readl(rng->mem + offset); ++} ++ ++static int rk_rng_init(struct hwrng *rng) ++{ ++ int ret; ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n"); ++ ++ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); ++ if (ret < 0) { ++ dev_err(rk_rng->dev, "failed to enable clks %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void rk_rng_cleanup(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n"); ++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); ++} ++ ++static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf, ++ size_t size) ++{ ++ u32 i; ++ ++ for (i = 0; i < size; i += 4) ++ *(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i)); ++} ++ ++static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ int ret = 0; ++ u32 reg_ctrl = 0; ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ ret = pm_runtime_get_sync(rk_rng->dev); ++ if (ret < 0) { ++ pm_runtime_put_noidle(rk_rng->dev); ++ return ret; ++ } ++ ++ /* enable osc_ring to get entropy, sample period is set as 100 */ ++ reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100); ++ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL); ++ ++ reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0); ++ ++ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL); ++ ++ ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl, ++ !(reg_ctrl & CRYPTO_V1_RNG_START), ++ ROCKCHIP_POLL_PERIOD_US, ++ ROCKCHIP_POLL_TIMEOUT_US); ++ if (ret < 0) ++ goto out; ++ ++ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); ++ ++ rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret); ++ ++out: ++ /* close TRNG */ ++ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0), ++ CRYPTO_V1_CTRL); ++ ++ pm_runtime_mark_last_busy(rk_rng->dev); ++ pm_runtime_put_sync_autosuspend(rk_rng->dev); ++ ++ return ret; ++} ++ ++static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ int ret = 0; ++ u32 reg_ctrl = 0; ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ ++ ret = pm_runtime_get_sync(rk_rng->dev); ++ if (ret < 0) { ++ pm_runtime_put_noidle(rk_rng->dev); ++ return ret; ++ } ++ ++ /* enable osc_ring to get entropy, sample period is set as 100 */ ++ rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT); ++ ++ reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN; ++ reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; ++ reg_ctrl |= CRYPTO_V2_RNG_ENABLE; ++ reg_ctrl |= CRYPTO_V2_RNG_START; ++ ++ rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), ++ CRYPTO_V2_RNG_CTL); ++ ++ ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl, ++ !(reg_ctrl & CRYPTO_V2_RNG_START), ++ ROCKCHIP_POLL_PERIOD_US, ++ ROCKCHIP_POLL_TIMEOUT_US); ++ if (ret < 0) ++ goto out; ++ ++ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); ++ ++ rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret); ++ ++out: ++ /* close TRNG */ ++ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL); ++ ++ pm_runtime_mark_last_busy(rk_rng->dev); ++ pm_runtime_put_sync_autosuspend(rk_rng->dev); ++ ++ return ret; ++} ++ ++static const struct rk_rng_soc_data rk_rng_v1_soc_data = { ++ .clks_num = ARRAY_SIZE(rk_rng_v1_clks), ++ .clks = rk_rng_v1_clks, ++ .rk_rng_read = rk_rng_v1_read, ++}; ++ ++static const struct rk_rng_soc_data rk_rng_v2_soc_data = { ++ .clks_num = ARRAY_SIZE(rk_rng_v2_clks), ++ .clks = rk_rng_v2_clks, ++ .rk_rng_read = rk_rng_v2_read, ++}; ++ ++static const struct of_device_id rk_rng_dt_match[] = { ++ { ++ .compatible = "rockchip,cryptov1-rng", ++ .data = (void *)&rk_rng_v1_soc_data, ++ }, ++ { ++ .compatible = "rockchip,cryptov2-rng", ++ .data = (void *)&rk_rng_v2_soc_data, ++ }, ++ { }, ++}; ++ ++MODULE_DEVICE_TABLE(of, rk_rng_dt_match); ++ ++static int rk_rng_probe(struct platform_device *pdev) ++{ ++ int i; ++ int ret; ++ struct rk_rng *rk_rng; ++ struct device_node *np = pdev->dev.of_node; ++ const struct of_device_id *match; ++ ++ dev_dbg(&pdev->dev, "probing...\n"); ++ rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL); ++ if (!rk_rng) ++ return -ENOMEM; ++ ++ match = of_match_node(rk_rng_dt_match, np); ++ rk_rng->soc_data = (struct rk_rng_soc_data *)match->data; ++ ++ rk_rng->dev = &pdev->dev; ++ rk_rng->rng.name = "rockchip"; ++#ifndef CONFIG_PM ++ rk_rng->rng.init = rk_rng_init; ++ rk_rng->rng.cleanup = rk_rng_cleanup, ++#endif ++ rk_rng->rng.read = rk_rng->soc_data->rk_rng_read; ++ rk_rng->rng.quality = 999; ++ ++ rk_rng->clk_bulks = ++ devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) * ++ rk_rng->soc_data->clks_num, GFP_KERNEL); ++ ++ rk_rng->clk_num = rk_rng->soc_data->clks_num; ++ ++ for (i = 0; i < rk_rng->soc_data->clks_num; i++) ++ rk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i]; ++ ++ rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); ++ if (IS_ERR(rk_rng->mem)) ++ return PTR_ERR(rk_rng->mem); ++ ++ ret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num, ++ rk_rng->clk_bulks); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to get clks property\n"); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, rk_rng); ++ ++ pm_runtime_set_autosuspend_delay(&pdev->dev, ++ ROCKCHIP_AUTOSUSPEND_DELAY); ++ pm_runtime_use_autosuspend(&pdev->dev); ++ pm_runtime_enable(&pdev->dev); ++ ++ ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng); ++ if (ret) { ++ pm_runtime_dont_use_autosuspend(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ } ++ ++ return ret; ++} ++ ++#ifdef CONFIG_PM ++static int rk_rng_runtime_suspend(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ rk_rng_cleanup(&rk_rng->rng); ++ ++ return 0; ++} ++ ++static int rk_rng_runtime_resume(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ return rk_rng_init(&rk_rng->rng); ++} ++ ++static const struct dev_pm_ops rk_rng_pm_ops = { ++ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, ++ rk_rng_runtime_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++}; ++ ++#endif ++ ++static struct platform_driver rk_rng_driver = { ++ .driver = { ++ .name = "rockchip-rng", ++#ifdef CONFIG_PM ++ .pm = &rk_rng_pm_ops, ++#endif ++ .of_match_table = rk_rng_dt_match, ++ }, ++ .probe = rk_rng_probe, ++}; ++ ++module_platform_driver(rk_rng_driver); ++ ++MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver"); ++MODULE_AUTHOR("Lin Jinhan "); ++MODULE_LICENSE("GPL v2"); ++ +--- a/drivers/char/hw_random/Makefile ++++ b/drivers/char/hw_random/Makefile +@@ -32,6 +32,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += + obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o + obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o + obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o ++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o + obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o + obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o + obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o diff --git a/target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch new file mode 100644 index 000000000..aa7c5c39d --- /dev/null +++ b/target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -0,0 +1,50 @@ +From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001 +From: wevsty +Date: Mon, 24 Aug 2020 02:27:11 +0800 +Subject: [PATCH] arm64: dts: rockchip: add hardware random number generator + for RK3328 and RK3399 + +Adding Hardware Random Number Generator Resources to the RK3328 and RK3399. + +Signed-off-by: wevsty +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -279,6 +279,17 @@ + status = "disabled"; + }; + ++ rng: rng@ff060000 { ++ compatible = "rockchip,cryptov1-rng"; ++ reg = <0x0 0xff060000 0x0 0x4000>; ++ ++ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; ++ clock-names = "clk_crypto", "hclk_crypto"; ++ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; ++ assigned-clock-rates = <150000000>, <100000000>; ++ status = "disabled"; ++ }; ++ + grf: syscon@ff100000 { + compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff100000 0x0 0x1000>; +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1879,6 +1879,16 @@ + }; + }; + ++ rng: rng@ff8b8000 { ++ compatible = "rockchip,cryptov1-rng"; ++ reg = <0x0 0xff8b8000 0x0 0x1000>; ++ clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; ++ clock-names = "clk_crypto", "hclk_crypto"; ++ assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; ++ assigned-clock-rates = <150000000>, <100000000>; ++ status = "disabled"; ++ }; ++ + gpu: gpu@ff9a0000 { + compatible = "rockchip,rk3399-mali", "arm,mali-t860"; + reg = <0x0 0xff9a0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-5.4/107-rockchip-enable-hardware-rng-for-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/107-rockchip-enable-hardware-rng-for-NanoPi-R2S.patch new file mode 100644 index 000000000..cab0abedd --- /dev/null +++ b/target/linux/rockchip/patches-5.4/107-rockchip-enable-hardware-rng-for-NanoPi-R2S.patch @@ -0,0 +1,19 @@ +From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001 +From: wevsty +Date: Mon, 24 Aug 2020 02:27:11 +0800 +Subject: [PATCH] rockchip: rk3328: enable hardware rng for NanoPi R2S + + +Signed-off-by: wevsty +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -411,3 +411,7 @@ + realtek,led-data = <0x87>; + }; + }; ++ ++&rng { ++ status = "okay"; ++};