From b5b402cd07a1a580345cef828bf82cb0cb31a873 Mon Sep 17 00:00:00 2001 From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> Date: Sun, 31 Jul 2022 23:15:16 +0800 Subject: [PATCH] Revert "rockchip: backport rk3568 support to kernel 5.10" This reverts commit cb3ea4bf5562ba0eccd0403573648f76bff3a464. --- package/boot/uboot-rockchip/Makefile | 12 - .../src/configs/opc-h68k-rk3568_defconfig | 59 - .../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 47 - .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 70 - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 39 - .../arch/arm64/boot/dts/rockchip/rk3566.dtsi | 35 - .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 3111 ----------------- .../arch/arm64/boot/dts/rockchip/rk3568.dtsi | 143 - .../arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1706 --------- .../boot/dts/rockchip/rockchip-pinconf.dtsi | 344 -- .../drivers/clk/rockchip/clk-rk3568.c | 1725 --------- .../gpu/drm/rockchip/rockchip_drm_vop2.c | 2706 -------------- .../gpu/drm/rockchip/rockchip_drm_vop2.h | 477 --- .../gpu/drm/rockchip/rockchip_vop2_reg.c | 281 -- .../pci/controller/dwc/pcie-dw-rockchip.c | 279 -- .../rockchip/phy-rockchip-naneng-combphy.c | 581 --- .../staging/media/hantro/rockchip_vpu_hw.c | 569 --- .../include/dt-bindings/clock/rk3568-cru.h | 926 ----- .../include/dt-bindings/power/rk3568-power.h | 32 - .../include/dt-bindings/soc/rockchip,vop2.h | 14 - ...-r8152-add-LED-configuration-from-OF.patch | 74 + ...et-add-RTL8152-binding-documentation.patch | 54 + ...kchip-add-EEPROM-node-for-NanoPi-R4S.patch | 2 +- ...-rockchip-Add-support-for-rv1126-pdm.patch | 155 - ...kchip-pdm-Add-support-for-rk3568-pdm.patch | 26 - ...ockchip-pdm-Add-support-for-path-map.patch | 95 - ...-dts-rockchip-add-rk3568-tsadc-nodes.patch | 32 - ...hip_thermal-Allow-more-resets-for-ts.patch | 28 - ...8-Add-support-for-power-off-on-RK817.patch | 27 - ...ip-inno-usb2-support-address_cells-2.patch | 45 - ...p-inno-usb2-support-muxed-interrupts.patch | 237 -- ...no-usb2-support-standalone-phy-nodes.patch | 44 - ...ockchip-inno-usb2-add-rk3568-support.patch | 104 - ...ckchip-Add-more-PLL-rates-for-rk3568.patch | 44 - ...SET_RATE_PARENT-to-the-HDMI-referenc.patch | 52 - ...chip-add-naneng-combo-phy-for-RK3568.patch | 49 - ...port-setting-f_min-from-host-drivers.patch | 54 - ...hip-Fix-handling-invalid-clock-rates.patch | 79 - ...-rk808-Add-reboot-support-to-rk808.c.patch | 110 - ...c-rockchip-set-dwc3-clock-for-rk3566.patch | 51 - ...-Add-support-for-Hantro-G1-on-RK356x.patch | 71 - ...nno-usb2-Fix-muxed-interrupt-support.patch | 42 - ...-inno-usb2-Do-not-check-bvalid-twice.patch | 37 - ...b2-Do-not-lock-in-bvalid-IRQ-handler.patch | 31 - ...b2-Support-multi-bit-mask-properties.patch | 29 - ...chip-inno-usb2-Handle-bvalid-falling.patch | 45 - ...phy-rockchip-inno-usb2-Handle-ID-IRQ.patch | 214 -- ...p-Mark-hclk_vo-as-critical-on-rk3568.patch | 66 - ...ed-drm_encoder-into-rockchip_decoder.patch | 601 ---- ...crtc_endpoint_id-to-rockchip_encoder.patch | 88 - ...rename-vpll-clock-to-reference-clock.patch | 93 - ...-rockchip-dw_hdmi-add-rk3568-support.patch | 84 - ...ckchip-dw_hdmi-add-regulator-support.patch | 109 - ...rm-rockchip-Make-VOP-driver-optional.patch | 65 - ...2-v5.19-drm-rockchip-Add-VOP2-driver.patch | 149 - ...kchip-dwc-Reset-core-at-driver-probe.patch | 72 - ...hip-dwc-Add-legacy-interrupt-support.patch | 163 - ...ockchip-vop2-unlock-on-error-path-in.patch | 27 - ...antro-Add-support-for-RK356x-encoder.patch | 96 - ...no-usb2-Ignore-OTG-IRQs-in-host-mode.patch | 36 - ...-Fix-RK3399-H.264-format-advertising.patch | 126 - ...sb2-Prevent-incorrect-error-on-probe.patch | 27 - ...hip-inno-usb2-Sync-initial-otg-state.patch | 33 - ...v6.0-arm64-enable-THP_SWAP-for-arm64.patch | 123 - .../patches-5.10/105-rockchip-rock-pi-4.patch | 2 +- ...d-OF-node-for-pcie-eth-on-NanoPi-R4S.patch | 2 +- ...-initial-signal-voltage-on-power-off.patch | 2 +- .../108-phy-rockchip-Support-PCIe-v3.patch | 106 - ...ts-rockchip-rk3568-Add-PCIe-v3-nodes.patch | 174 - ...328-Add-support-for-OrangePi-R1-Plus.patch | 42 + ...8-Add-support-for-EmbedFire-DoorNet1.patch | 2 + ...Add-support-for-FriendlyARM-NanoPi-R.patch | 50 + ...9-Add-support-for-EmbedFire-DoorNet2.patch | 2 +- ...Add-support-for-OrangePi-R1-Plus-LTS.patch | 82 +- ...-support-for-FriendlyARM-NanoPi-Neo3.patch | 14 +- ...Add-driver-for-Motorcomm-YT85xx-PHYs.patch | 4 +- ...Add-driver-for-Motorcomm-YT8531-PHYs.patch | 28 +- ...-add-driver-for-Rockchip-USB-3.0-PHY.patch | 10 +- ...-doornet1-add-rk3328-dmc-relate-node.patch | 13 +- .../900-arm64-boot-add-dts-files.patch | 10 - ...3-rockchip-rk3568-remove-rng-node-for-r66s | 13 - 81 files changed, 353 insertions(+), 17148 deletions(-) delete mode 100644 package/boot/uboot-rockchip/src/configs/opc-h68k-rk3568_defconfig delete mode 100644 target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts delete mode 100644 target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts delete mode 100644 target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts delete mode 100644 target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3566.dtsi delete mode 100644 target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi delete mode 100644 target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568.dtsi delete mode 100644 target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk356x.dtsi delete mode 100644 target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi delete mode 100644 target/linux/rockchip/files-5.10/drivers/clk/rockchip/clk-rk3568.c delete mode 100644 target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c delete mode 100644 target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h delete mode 100644 target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c delete mode 100644 target/linux/rockchip/files-5.10/drivers/pci/controller/dwc/pcie-dw-rockchip.c delete mode 100644 target/linux/rockchip/files-5.10/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c delete mode 100644 target/linux/rockchip/files-5.10/drivers/staging/media/hantro/rockchip_vpu_hw.c delete mode 100644 target/linux/rockchip/files-5.10/include/dt-bindings/clock/rk3568-cru.h delete mode 100644 target/linux/rockchip/files-5.10/include/dt-bindings/power/rk3568-power.h delete mode 100644 target/linux/rockchip/files-5.10/include/dt-bindings/soc/rockchip,vop2.h create mode 100644 target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch create mode 100644 target/linux/rockchip/patches-5.10/003-dt-bindings-net-add-RTL8152-binding-documentation.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0001-v5.16-ASoC-rockchip-Add-support-for-rv1126-pdm.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0002-v5.16-ASoC-rockchip-pdm-Add-support-for-rk3568-pdm.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0003-v5.16-ASoC-rockchip-pdm-Add-support-for-path-map.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0004-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0005-v5.16-thermal-drivers-rockchip_thermal-Allow-more-resets-for-ts.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0006-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0007-v5.17-phy-phy-rockchip-inno-usb2-support-address_cells-2.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0008-v5.17-phy-phy-rockchip-inno-usb2-support-muxed-interrupts.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0009-v5.17-phy-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0010-v5.17-phy-phy-rockchip-inno-usb2-add-rk3568-support.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0011-v5.18-clk-rockchip-Add-more-PLL-rates-for-rk3568.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0012-v5.18-clk-rockchip-Add-CLK_SET_RATE_PARENT-to-the-HDMI-referenc.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0013-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0014-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0015-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0016-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0017-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0018-v5.19-media-hantro-Add-support-for-Hantro-G1-on-RK356x.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0019-v5.19-phy-rockchip-inno-usb2-Fix-muxed-interrupt-support.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0020-v5.19-phy-rockchip-inno-usb2-Do-not-check-bvalid-twice.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0021-v5.19-phy-rockchip-inno-usb2-Do-not-lock-in-bvalid-IRQ-handler.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0022-v5.19-phy-rockchip-inno-usb2-Support-multi-bit-mask-properties.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0023-v5.19-phy-rockchip-inno-usb2-Handle-bvalid-falling.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0024-v5.19-phy-rockchip-inno-usb2-Handle-ID-IRQ.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0025-v5.19-clk-rockchip-Mark-hclk_vo-as-critical-on-rk3568.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0026-v5.19-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0027-v5.19-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0028-v5.19-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0029-v5.19-drm-rockchip-dw_hdmi-add-rk3568-support.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0030-v5.19-drm-rockchip-dw_hdmi-add-regulator-support.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0031-v5.19-drm-rockchip-Make-VOP-driver-optional.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0032-v5.19-drm-rockchip-Add-VOP2-driver.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0033-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0034-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0035-v6.0-drm-rockchip-vop2-unlock-on-error-path-in.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0036-v6.0-media-hantro-Add-support-for-RK356x-encoder.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0037-v6.0-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0038-v6.0-media-hantro-Fix-RK3399-H.264-format-advertising.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0039-v6.0-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-probe.patch delete mode 100644 target/linux/rockchip/patches-5.10/008-0040-v6.0-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch delete mode 100644 target/linux/rockchip/patches-5.10/009-v6.0-arm64-enable-THP_SWAP-for-arm64.patch delete mode 100644 target/linux/rockchip/patches-5.10/108-phy-rockchip-Support-PCIe-v3.patch delete mode 100644 target/linux/rockchip/patches-5.10/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch delete mode 100644 target/linux/rockchip/patches-5.10/900-arm64-boot-add-dts-files.patch delete mode 100644 target/linux/rockchip/patches-5.10/993-rockchip-rk3568-remove-rng-node-for-r66s diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index ac5b0aaaf..ab922002b 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -126,17 +126,6 @@ define U-Boot/nanopi-r4se-rk3399 USE_RKBIN:=1 endef -define U-Boot/opc-h68k-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=HINLINK OPC-H68K - BUILD_DEVICES:= \ - hinlink_opc-h68k-d - DEPENDS:=+PACKAGE_u-boot-opc-h68k-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - define U-Boot/fastrhino-r66s-rk3568 BUILD_SUBTARGET:=armv8 NAME:=FastRhin-R66S @@ -216,7 +205,6 @@ UBOOT_TARGETS := \ nanopi-r2s-rk3328 \ orangepi-r1-plus-rk3328 \ orangepi-r1-plus-lts-rk3328 \ - opc-h68k-rk3568 \ station-p2-rk3568 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/boot/uboot-rockchip/src/configs/opc-h68k-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/opc-h68k-rk3568_defconfig deleted file mode 100644 index 435be99ed..000000000 --- a/package/boot/uboot-rockchip/src/configs/opc-h68k-rk3568_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00a00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" -CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 -CONFIG_TARGET_EVB_RK3568=y -CONFIG_DEBUG_UART_BASE=0xFE660000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_SYS_LOAD_ADDR=0xc00800 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_ATF=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_SPL_DOS_PARTITION is not set -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_REGMAP=y -CONFIG_SPL_SYSCON=y -CONFIG_SPL_CLK=y -CONFIG_ROCKCHIP_GPIO=y -CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y -CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y -CONFIG_REGULATOR_PWM=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_SPL_RAM=y -CONFIG_DM_RESET=y -CONFIG_BAUDRATE=1500000 -CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYSRESET=y -CONFIG_ERRNO_STR=y diff --git a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts b/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts deleted file mode 100644 index c58b88f9d..000000000 --- a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2021 Tianling Shen - */ - -/dts-v1/; - -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "FriendlyElec NanoPi R2C"; - compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -}; - -&gmac2io { - phy-handle = <&yt8521s>; - - mdio { - /delete-node/ ethernet-phy@1; - - yt8521s: ethernet-phy@3 { - compatible = "ethernet-phy-id0000.011a", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&lan_led { - label = "nanopi-r2c:green:lan"; -}; - -&sys_led { - label = "nanopi-r2c:red:sys"; -}; - -&wan_led { - label = "nanopi-r2c:green:wan"; -}; \ No newline at end of file diff --git a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts deleted file mode 100644 index a0b3dd68c..000000000 --- a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -#include "rk3328-orangepi-r1-plus.dts" - -/ { - model = "Xunlong Orange Pi R1 Plus LTS"; - compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -}; - -/delete-node/ &rtl8211e; -&gmac2io { - phy-handle = <ðphy3>; - snps,reset-delays-us = <0 15000 50000>; - tx_delay = <0x19>; - rx_delay = <0x05>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy3: ethernet-phy@0 { - reg = <0x0>; - keep-clkout-on; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - pinctrl-names = "default"; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_io_sdio>; - status = "okay"; -}; - -&dmc_opp_table { - opp-1056000000 { - status = "disabled"; - }; - opp-924000000 { - status = "disabled"; - }; - opp-840000000 { - status = "disabled"; - }; - opp-798000000 { - status = "disabled"; - }; -}; - -&sys_led { - label = "orangepi-r1-plus-lts:red:sys"; -}; - -&wan_led { - label = "orangepi-r1-plus-lts:green:wan"; -}; - -&lan_led { - label = "orangepi-r1-plus-lts:green:lan"; -}; \ No newline at end of file diff --git a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts b/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts deleted file mode 100644 index cc9ebb7b0..000000000 --- a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "Xunlong Orange Pi R1 Plus"; - compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; -}; - -&lan_led { - label = "orangepi-r1-plus:green:lan"; -}; - -&spi0 { - max-freq = <48000000>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&sys_led { - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - label = "orangepi-r1-plus:red:sys"; -}; - -&sys_led_pin { - rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -}; - -&uart1 { - status = "okay"; -}; - -&wan_led { - label = "orangepi-r1-plus:green:wan"; -}; \ No newline at end of file diff --git a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3566.dtsi deleted file mode 100644 index 6c4b17d27..000000000 --- a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3566.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include "rk356x.dtsi" - -/ { - compatible = "rockchip,rk3566"; -}; - -&pipegrf { - compatible = "rockchip,rk3566-pipe-grf", "syscon"; -}; - -&power { - power-domain@RK3568_PD_PIPE { - reg = ; - clocks = <&cru PCLK_PIPE>; - pm_qos = <&qos_pcie2x1>, - <&qos_sata1>, - <&qos_sata2>, - <&qos_usb3_0>, - <&qos_usb3_1>; - #power-domain-cells = <0>; - }; -}; - -&usb_host0_xhci { - phys = <&usb2phy0_otg>; - phy-names = "usb2-phy"; - extcon = <&usb2phy0>; - maximum-speed = "high-speed"; -}; - -&vop { - compatible = "rockchip,rk3566-vop"; -}; diff --git a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi deleted file mode 100644 index a588ca95a..000000000 --- a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +++ /dev/null @@ -1,3111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include "rockchip-pinconf.dtsi" - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - acodec { - /omit-if-no-ref/ - acodec_pins: acodec-pins { - rockchip,pins = - /* acodec_adc_sync */ - <1 RK_PB1 5 &pcfg_pull_none>, - /* acodec_adcclk */ - <1 RK_PA1 5 &pcfg_pull_none>, - /* acodec_adcdata */ - <1 RK_PA0 5 &pcfg_pull_none>, - /* acodec_dac_datal */ - <1 RK_PA7 5 &pcfg_pull_none>, - /* acodec_dac_datar */ - <1 RK_PB0 5 &pcfg_pull_none>, - /* acodec_dacclk */ - <1 RK_PA3 5 &pcfg_pull_none>, - /* acodec_dacsync */ - <1 RK_PA5 5 &pcfg_pull_none>; - }; - }; - - audiopwm { - /omit-if-no-ref/ - audiopwm_lout: audiopwm-lout { - rockchip,pins = - /* audiopwm_lout */ - <1 RK_PA0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_loutn: audiopwm-loutn { - rockchip,pins = - /* audiopwm_loutn */ - <1 RK_PA1 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_loutp: audiopwm-loutp { - rockchip,pins = - /* audiopwm_loutp */ - <1 RK_PA0 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_rout: audiopwm-rout { - rockchip,pins = - /* audiopwm_rout */ - <1 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_routn: audiopwm-routn { - rockchip,pins = - /* audiopwm_routn */ - <1 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_routp: audiopwm-routp { - rockchip,pins = - /* audiopwm_routp */ - <1 RK_PA6 4 &pcfg_pull_none>; - }; - }; - - bt656 { - /omit-if-no-ref/ - bt656m0_pins: bt656m0-pins { - rockchip,pins = - /* bt656_clkm0 */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* bt656_d0m0 */ - <2 RK_PD0 2 &pcfg_pull_none>, - /* bt656_d1m0 */ - <2 RK_PD1 2 &pcfg_pull_none>, - /* bt656_d2m0 */ - <2 RK_PD2 2 &pcfg_pull_none>, - /* bt656_d3m0 */ - <2 RK_PD3 2 &pcfg_pull_none>, - /* bt656_d4m0 */ - <2 RK_PD4 2 &pcfg_pull_none>, - /* bt656_d5m0 */ - <2 RK_PD5 2 &pcfg_pull_none>, - /* bt656_d6m0 */ - <2 RK_PD6 2 &pcfg_pull_none>, - /* bt656_d7m0 */ - <2 RK_PD7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - bt656m1_pins: bt656m1-pins { - rockchip,pins = - /* bt656_clkm1 */ - <4 RK_PB4 5 &pcfg_pull_none>, - /* bt656_d0m1 */ - <3 RK_PC6 5 &pcfg_pull_none>, - /* bt656_d1m1 */ - <3 RK_PC7 5 &pcfg_pull_none>, - /* bt656_d2m1 */ - <3 RK_PD0 5 &pcfg_pull_none>, - /* bt656_d3m1 */ - <3 RK_PD1 5 &pcfg_pull_none>, - /* bt656_d4m1 */ - <3 RK_PD2 5 &pcfg_pull_none>, - /* bt656_d5m1 */ - <3 RK_PD3 5 &pcfg_pull_none>, - /* bt656_d6m1 */ - <3 RK_PD4 5 &pcfg_pull_none>, - /* bt656_d7m1 */ - <3 RK_PD5 5 &pcfg_pull_none>; - }; - }; - - bt1120 { - /omit-if-no-ref/ - bt1120_pins: bt1120-pins { - rockchip,pins = - /* bt1120_clk */ - <3 RK_PA6 2 &pcfg_pull_none>, - /* bt1120_d0 */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* bt1120_d1 */ - <3 RK_PA2 2 &pcfg_pull_none>, - /* bt1120_d2 */ - <3 RK_PA3 2 &pcfg_pull_none>, - /* bt1120_d3 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* bt1120_d4 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* bt1120_d5 */ - <3 RK_PA7 2 &pcfg_pull_none>, - /* bt1120_d6 */ - <3 RK_PB0 2 &pcfg_pull_none>, - /* bt1120_d7 */ - <3 RK_PB1 2 &pcfg_pull_none>, - /* bt1120_d8 */ - <3 RK_PB2 2 &pcfg_pull_none>, - /* bt1120_d9 */ - <3 RK_PB3 2 &pcfg_pull_none>, - /* bt1120_d10 */ - <3 RK_PB4 2 &pcfg_pull_none>, - /* bt1120_d11 */ - <3 RK_PB5 2 &pcfg_pull_none>, - /* bt1120_d12 */ - <3 RK_PB6 2 &pcfg_pull_none>, - /* bt1120_d13 */ - <3 RK_PC1 2 &pcfg_pull_none>, - /* bt1120_d14 */ - <3 RK_PC2 2 &pcfg_pull_none>, - /* bt1120_d15 */ - <3 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - cam { - /omit-if-no-ref/ - cam_clkout0: cam-clkout0 { - rockchip,pins = - /* cam_clkout0 */ - <4 RK_PA7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cam_clkout1: cam-clkout1 { - rockchip,pins = - /* cam_clkout1 */ - <4 RK_PB0 1 &pcfg_pull_none>; - }; - }; - - can0 { - /omit-if-no-ref/ - can0m0_pins: can0m0-pins { - rockchip,pins = - /* can0_rxm0 */ - <0 RK_PB4 2 &pcfg_pull_none>, - /* can0_txm0 */ - <0 RK_PB3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can0m1_pins: can0m1-pins { - rockchip,pins = - /* can0_rxm1 */ - <2 RK_PA2 4 &pcfg_pull_none>, - /* can0_txm1 */ - <2 RK_PA1 4 &pcfg_pull_none>; - }; - }; - - can1 { - /omit-if-no-ref/ - can1m0_pins: can1m0-pins { - rockchip,pins = - /* can1_rxm0 */ - <1 RK_PA0 3 &pcfg_pull_none>, - /* can1_txm0 */ - <1 RK_PA1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can1m1_pins: can1m1-pins { - rockchip,pins = - /* can1_rxm1 */ - <4 RK_PC2 3 &pcfg_pull_none>, - /* can1_txm1 */ - <4 RK_PC3 3 &pcfg_pull_none>; - }; - }; - - can2 { - /omit-if-no-ref/ - can2m0_pins: can2m0-pins { - rockchip,pins = - /* can2_rxm0 */ - <4 RK_PB4 3 &pcfg_pull_none>, - /* can2_txm0 */ - <4 RK_PB5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can2m1_pins: can2m1-pins { - rockchip,pins = - /* can2_rxm1 */ - <2 RK_PB1 4 &pcfg_pull_none>, - /* can2_txm1 */ - <2 RK_PB2 4 &pcfg_pull_none>; - }; - }; - - cif { - /omit-if-no-ref/ - cif_clk: cif-clk { - rockchip,pins = - /* cif_clkout */ - <4 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_clk: cif-dvp-clk { - rockchip,pins = - /* cif_clkin */ - <4 RK_PC1 1 &pcfg_pull_none>, - /* cif_href */ - <4 RK_PB6 1 &pcfg_pull_none>, - /* cif_vsync */ - <4 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus16: cif-dvp-bus16 { - rockchip,pins = - /* cif_d8 */ - <3 RK_PD6 1 &pcfg_pull_none>, - /* cif_d9 */ - <3 RK_PD7 1 &pcfg_pull_none>, - /* cif_d10 */ - <4 RK_PA0 1 &pcfg_pull_none>, - /* cif_d11 */ - <4 RK_PA1 1 &pcfg_pull_none>, - /* cif_d12 */ - <4 RK_PA2 1 &pcfg_pull_none>, - /* cif_d13 */ - <4 RK_PA3 1 &pcfg_pull_none>, - /* cif_d14 */ - <4 RK_PA4 1 &pcfg_pull_none>, - /* cif_d15 */ - <4 RK_PA5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus8: cif-dvp-bus8 { - rockchip,pins = - /* cif_d0 */ - <3 RK_PC6 1 &pcfg_pull_none>, - /* cif_d1 */ - <3 RK_PC7 1 &pcfg_pull_none>, - /* cif_d2 */ - <3 RK_PD0 1 &pcfg_pull_none>, - /* cif_d3 */ - <3 RK_PD1 1 &pcfg_pull_none>, - /* cif_d4 */ - <3 RK_PD2 1 &pcfg_pull_none>, - /* cif_d5 */ - <3 RK_PD3 1 &pcfg_pull_none>, - /* cif_d6 */ - <3 RK_PD4 1 &pcfg_pull_none>, - /* cif_d7 */ - <3 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - clk32k { - /omit-if-no-ref/ - clk32k_in: clk32k-in { - rockchip,pins = - /* clk32k_in */ - <0 RK_PB0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - clk32k_out0: clk32k-out0 { - rockchip,pins = - /* clk32k_out0 */ - <0 RK_PB0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - clk32k_out1: clk32k-out1 { - rockchip,pins = - /* clk32k_out1 */ - <2 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - cpu { - /omit-if-no-ref/ - cpu_pins: cpu-pins { - rockchip,pins = - /* cpu_avs */ - <0 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - ebc { - /omit-if-no-ref/ - ebc_extern: ebc-extern { - rockchip,pins = - /* ebc_sdce1 */ - <4 RK_PA7 2 &pcfg_pull_none>, - /* ebc_sdce2 */ - <4 RK_PB0 2 &pcfg_pull_none>, - /* ebc_sdce3 */ - <4 RK_PB1 2 &pcfg_pull_none>, - /* ebc_sdshr */ - <4 RK_PB5 2 &pcfg_pull_none>, - /* ebc_vcom */ - <4 RK_PB2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - ebc_pins: ebc-pins { - rockchip,pins = - /* ebc_gdclk */ - <4 RK_PC0 2 &pcfg_pull_none>, - /* ebc_gdoe */ - <4 RK_PB3 2 &pcfg_pull_none>, - /* ebc_gdsp */ - <4 RK_PB4 2 &pcfg_pull_none>, - /* ebc_sdce0 */ - <4 RK_PA6 2 &pcfg_pull_none>, - /* ebc_sdclk */ - <4 RK_PC1 2 &pcfg_pull_none>, - /* ebc_sddo0 */ - <3 RK_PC6 2 &pcfg_pull_none>, - /* ebc_sddo1 */ - <3 RK_PC7 2 &pcfg_pull_none>, - /* ebc_sddo2 */ - <3 RK_PD0 2 &pcfg_pull_none>, - /* ebc_sddo3 */ - <3 RK_PD1 2 &pcfg_pull_none>, - /* ebc_sddo4 */ - <3 RK_PD2 2 &pcfg_pull_none>, - /* ebc_sddo5 */ - <3 RK_PD3 2 &pcfg_pull_none>, - /* ebc_sddo6 */ - <3 RK_PD4 2 &pcfg_pull_none>, - /* ebc_sddo7 */ - <3 RK_PD5 2 &pcfg_pull_none>, - /* ebc_sddo8 */ - <3 RK_PD6 2 &pcfg_pull_none>, - /* ebc_sddo9 */ - <3 RK_PD7 2 &pcfg_pull_none>, - /* ebc_sddo10 */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* ebc_sddo11 */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* ebc_sddo12 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* ebc_sddo13 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* ebc_sddo14 */ - <4 RK_PA4 2 &pcfg_pull_none>, - /* ebc_sddo15 */ - <4 RK_PA5 2 &pcfg_pull_none>, - /* ebc_sdle */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* ebc_sdoe */ - <4 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - edpdp { - /omit-if-no-ref/ - edpdpm0_pins: edpdpm0-pins { - rockchip,pins = - /* edpdp_hpdinm0 */ - <4 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - edpdpm1_pins: edpdpm1-pins { - rockchip,pins = - /* edpdp_hpdinm1 */ - <0 RK_PC2 2 &pcfg_pull_none>; - }; - }; - - emmc { - /omit-if-no-ref/ - emmc_rstnout: emmc-rstnout { - rockchip,pins = - /* emmc_rstn */ - <1 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - emmc_bus8: emmc-bus8 { - rockchip,pins = - /* emmc_d0 */ - <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d1 */ - <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d2 */ - <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d3 */ - <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d4 */ - <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d5 */ - <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d6 */ - <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d7 */ - <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_clk: emmc-clk { - rockchip,pins = - /* emmc_clkout */ - <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_cmd: emmc-cmd { - rockchip,pins = - /* emmc_cmd */ - <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_datastrobe: emmc-datastrobe { - rockchip,pins = - /* emmc_datastrobe */ - <1 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - eth0 { - /omit-if-no-ref/ - eth0_pins: eth0-pins { - rockchip,pins = - /* eth0_refclko25m */ - <2 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - eth1 { - /omit-if-no-ref/ - eth1m0_pins: eth1m0-pins { - rockchip,pins = - /* eth1_refclko25mm0 */ - <3 RK_PB0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - eth1m1_pins: eth1m1-pins { - rockchip,pins = - /* eth1_refclko25mm1 */ - <4 RK_PB3 3 &pcfg_pull_none>; - }; - }; - - flash { - /omit-if-no-ref/ - flash_pins: flash-pins { - rockchip,pins = - /* flash_ale */ - <1 RK_PD0 2 &pcfg_pull_none>, - /* flash_cle */ - <1 RK_PC6 3 &pcfg_pull_none>, - /* flash_cs0n */ - <1 RK_PD3 2 &pcfg_pull_none>, - /* flash_cs1n */ - <1 RK_PD4 2 &pcfg_pull_none>, - /* flash_d0 */ - <1 RK_PB4 2 &pcfg_pull_none>, - /* flash_d1 */ - <1 RK_PB5 2 &pcfg_pull_none>, - /* flash_d2 */ - <1 RK_PB6 2 &pcfg_pull_none>, - /* flash_d3 */ - <1 RK_PB7 2 &pcfg_pull_none>, - /* flash_d4 */ - <1 RK_PC0 2 &pcfg_pull_none>, - /* flash_d5 */ - <1 RK_PC1 2 &pcfg_pull_none>, - /* flash_d6 */ - <1 RK_PC2 2 &pcfg_pull_none>, - /* flash_d7 */ - <1 RK_PC3 2 &pcfg_pull_none>, - /* flash_dqs */ - <1 RK_PC5 2 &pcfg_pull_none>, - /* flash_rdn */ - <1 RK_PD2 2 &pcfg_pull_none>, - /* flash_rdy */ - <1 RK_PD1 2 &pcfg_pull_none>, - /* flash_volsel */ - <0 RK_PA7 1 &pcfg_pull_none>, - /* flash_wpn */ - <1 RK_PC7 3 &pcfg_pull_none>, - /* flash_wrn */ - <1 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - fspi { - /omit-if-no-ref/ - fspi_pins: fspi-pins { - rockchip,pins = - /* fspi_clk */ - <1 RK_PD0 1 &pcfg_pull_none>, - /* fspi_cs0n */ - <1 RK_PD3 1 &pcfg_pull_none>, - /* fspi_d0 */ - <1 RK_PD1 1 &pcfg_pull_none>, - /* fspi_d1 */ - <1 RK_PD2 1 &pcfg_pull_none>, - /* fspi_d2 */ - <1 RK_PC7 2 &pcfg_pull_none>, - /* fspi_d3 */ - <1 RK_PD4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - fspi_cs1: fspi-cs1 { - rockchip,pins = - /* fspi_cs1n */ - <1 RK_PC6 2 &pcfg_pull_up>; - }; - }; - - gmac0 { - /omit-if-no-ref/ - gmac0_miim: gmac0-miim { - rockchip,pins = - /* gmac0_mdc */ - <2 RK_PC3 2 &pcfg_pull_none>, - /* gmac0_mdio */ - <2 RK_PC4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_clkinout: gmac0-clkinout { - rockchip,pins = - /* gmac0_mclkinout */ - <2 RK_PC2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rx_er: gmac0-rx-er { - rockchip,pins = - /* gmac0_rxer */ - <2 RK_PC5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rx_bus2: gmac0-rx-bus2 { - rockchip,pins = - /* gmac0_rxd0 */ - <2 RK_PB6 1 &pcfg_pull_none>, - /* gmac0_rxd1 */ - <2 RK_PB7 2 &pcfg_pull_none>, - /* gmac0_rxdvcrs */ - <2 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_tx_bus2: gmac0-tx-bus2 { - rockchip,pins = - /* gmac0_txd0 */ - <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, - /* gmac0_txd1 */ - <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, - /* gmac0_txen */ - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_clk: gmac0-rgmii-clk { - rockchip,pins = - /* gmac0_rxclk */ - <2 RK_PA5 2 &pcfg_pull_none>, - /* gmac0_txclk */ - <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_bus: gmac0-rgmii-bus { - rockchip,pins = - /* gmac0_rxd2 */ - <2 RK_PA3 2 &pcfg_pull_none>, - /* gmac0_rxd3 */ - <2 RK_PA4 2 &pcfg_pull_none>, - /* gmac0_txd2 */ - <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, - /* gmac0_txd3 */ - <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; - }; - }; - - gmac1 { - /omit-if-no-ref/ - gmac1m0_miim: gmac1m0-miim { - rockchip,pins = - /* gmac1_mdcm0 */ - <3 RK_PC4 3 &pcfg_pull_none>, - /* gmac1_mdiom0 */ - <3 RK_PC5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_clkinout: gmac1m0-clkinout { - rockchip,pins = - /* gmac1_mclkinoutm0 */ - <3 RK_PC0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rx_er: gmac1m0-rx-er { - rockchip,pins = - /* gmac1_rxerm0 */ - <3 RK_PB4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rx_bus2: gmac1m0-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0m0 */ - <3 RK_PB1 3 &pcfg_pull_none>, - /* gmac1_rxd1m0 */ - <3 RK_PB2 3 &pcfg_pull_none>, - /* gmac1_rxdvcrsm0 */ - <3 RK_PB3 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_tx_bus2: gmac1m0-tx-bus2 { - rockchip,pins = - /* gmac1_txd0m0 */ - <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd1m0 */ - <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txenm0 */ - <3 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { - rockchip,pins = - /* gmac1_rxclkm0 */ - <3 RK_PA7 3 &pcfg_pull_none>, - /* gmac1_txclkm0 */ - <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2m0 */ - <3 RK_PA4 3 &pcfg_pull_none>, - /* gmac1_rxd3m0 */ - <3 RK_PA5 3 &pcfg_pull_none>, - /* gmac1_txd2m0 */ - <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd3m0 */ - <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; - }; - - /omit-if-no-ref/ - gmac1m1_miim: gmac1m1-miim { - rockchip,pins = - /* gmac1_mdcm1 */ - <4 RK_PB6 3 &pcfg_pull_none>, - /* gmac1_mdiom1 */ - <4 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_clkinout: gmac1m1-clkinout { - rockchip,pins = - /* gmac1_mclkinoutm1 */ - <4 RK_PC1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rx_er: gmac1m1-rx-er { - rockchip,pins = - /* gmac1_rxerm1 */ - <4 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rx_bus2: gmac1m1-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0m1 */ - <4 RK_PA7 3 &pcfg_pull_none>, - /* gmac1_rxd1m1 */ - <4 RK_PB0 3 &pcfg_pull_none>, - /* gmac1_rxdvcrsm1 */ - <4 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_tx_bus2: gmac1m1-tx-bus2 { - rockchip,pins = - /* gmac1_txd0m1 */ - <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd1m1 */ - <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txenm1 */ - <4 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { - rockchip,pins = - /* gmac1_rxclkm1 */ - <4 RK_PA3 3 &pcfg_pull_none>, - /* gmac1_txclkm1 */ - <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2m1 */ - <4 RK_PA1 3 &pcfg_pull_none>, - /* gmac1_rxd3m1 */ - <4 RK_PA2 3 &pcfg_pull_none>, - /* gmac1_txd2m1 */ - <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd3m1 */ - <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; - }; - }; - - gpu { - /omit-if-no-ref/ - gpu_pins: gpu-pins { - rockchip,pins = - /* gpu_avs */ - <0 RK_PC0 2 &pcfg_pull_none>, - /* gpu_pwren */ - <0 RK_PA6 4 &pcfg_pull_none>; - }; - }; - - hdmitx { - /omit-if-no-ref/ - hdmitxm0_cec: hdmitxm0-cec { - rockchip,pins = - /* hdmitxm0_cec */ - <4 RK_PD1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmitxm1_cec: hdmitxm1-cec { - rockchip,pins = - /* hdmitxm1_cec */ - <0 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmitx_scl: hdmitx-scl { - rockchip,pins = - /* hdmitx_scl */ - <4 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmitx_sda: hdmitx-sda { - rockchip,pins = - /* hdmitx_sda */ - <4 RK_PD0 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - /omit-if-no-ref/ - i2c0_xfer: i2c0-xfer { - rockchip,pins = - /* i2c0_scl */ - <0 RK_PB1 1 &pcfg_pull_none_smt>, - /* i2c0_sda */ - <0 RK_PB2 1 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - /omit-if-no-ref/ - i2c1_xfer: i2c1-xfer { - rockchip,pins = - /* i2c1_scl */ - <0 RK_PB3 1 &pcfg_pull_none_smt>, - /* i2c1_sda */ - <0 RK_PB4 1 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - /omit-if-no-ref/ - i2c2m0_xfer: i2c2m0-xfer { - rockchip,pins = - /* i2c2_sclm0 */ - <0 RK_PB5 1 &pcfg_pull_none_smt>, - /* i2c2_sdam0 */ - <0 RK_PB6 1 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = - /* i2c2_sclm1 */ - <4 RK_PB5 1 &pcfg_pull_none_smt>, - /* i2c2_sdam1 */ - <4 RK_PB4 1 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - /omit-if-no-ref/ - i2c3m0_xfer: i2c3m0-xfer { - rockchip,pins = - /* i2c3_sclm0 */ - <1 RK_PA1 1 &pcfg_pull_none_smt>, - /* i2c3_sdam0 */ - <1 RK_PA0 1 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m1_xfer: i2c3m1-xfer { - rockchip,pins = - /* i2c3_sclm1 */ - <3 RK_PB5 4 &pcfg_pull_none_smt>, - /* i2c3_sdam1 */ - <3 RK_PB6 4 &pcfg_pull_none_smt>; - }; - }; - - i2c4 { - /omit-if-no-ref/ - i2c4m0_xfer: i2c4m0-xfer { - rockchip,pins = - /* i2c4_sclm0 */ - <4 RK_PB3 1 &pcfg_pull_none_smt>, - /* i2c4_sdam0 */ - <4 RK_PB2 1 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m1_xfer: i2c4m1-xfer { - rockchip,pins = - /* i2c4_sclm1 */ - <2 RK_PB2 2 &pcfg_pull_none_smt>, - /* i2c4_sdam1 */ - <2 RK_PB1 2 &pcfg_pull_none_smt>; - }; - }; - - i2c5 { - /omit-if-no-ref/ - i2c5m0_xfer: i2c5m0-xfer { - rockchip,pins = - /* i2c5_sclm0 */ - <3 RK_PB3 4 &pcfg_pull_none_smt>, - /* i2c5_sdam0 */ - <3 RK_PB4 4 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m1_xfer: i2c5m1-xfer { - rockchip,pins = - /* i2c5_sclm1 */ - <4 RK_PC7 2 &pcfg_pull_none_smt>, - /* i2c5_sdam1 */ - <4 RK_PD0 2 &pcfg_pull_none_smt>; - }; - }; - - i2s1 { - /omit-if-no-ref/ - i2s1m0_lrckrx: i2s1m0-lrckrx { - rockchip,pins = - /* i2s1m0_lrckrx */ - <1 RK_PA6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_lrcktx: i2s1m0-lrcktx { - rockchip,pins = - /* i2s1m0_lrcktx */ - <1 RK_PA5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_mclk: i2s1m0-mclk { - rockchip,pins = - /* i2s1m0_mclk */ - <1 RK_PA2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sclkrx: i2s1m0-sclkrx { - rockchip,pins = - /* i2s1m0_sclkrx */ - <1 RK_PA4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sclktx: i2s1m0-sclktx { - rockchip,pins = - /* i2s1m0_sclktx */ - <1 RK_PA3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi0: i2s1m0-sdi0 { - rockchip,pins = - /* i2s1m0_sdi0 */ - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi1: i2s1m0-sdi1 { - rockchip,pins = - /* i2s1m0_sdi1 */ - <1 RK_PB2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi2: i2s1m0-sdi2 { - rockchip,pins = - /* i2s1m0_sdi2 */ - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi3: i2s1m0-sdi3 { - rockchip,pins = - /* i2s1m0_sdi3 */ - <1 RK_PB0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo0: i2s1m0-sdo0 { - rockchip,pins = - /* i2s1m0_sdo0 */ - <1 RK_PA7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo1: i2s1m0-sdo1 { - rockchip,pins = - /* i2s1m0_sdo1 */ - <1 RK_PB0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo2: i2s1m0-sdo2 { - rockchip,pins = - /* i2s1m0_sdo2 */ - <1 RK_PB1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo3: i2s1m0-sdo3 { - rockchip,pins = - /* i2s1m0_sdo3 */ - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_lrckrx: i2s1m1-lrckrx { - rockchip,pins = - /* i2s1m1_lrckrx */ - <4 RK_PA7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_lrcktx: i2s1m1-lrcktx { - rockchip,pins = - /* i2s1m1_lrcktx */ - <3 RK_PD0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_mclk: i2s1m1-mclk { - rockchip,pins = - /* i2s1m1_mclk */ - <3 RK_PC6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sclkrx: i2s1m1-sclkrx { - rockchip,pins = - /* i2s1m1_sclkrx */ - <4 RK_PA6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sclktx: i2s1m1-sclktx { - rockchip,pins = - /* i2s1m1_sclktx */ - <3 RK_PC7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi0: i2s1m1-sdi0 { - rockchip,pins = - /* i2s1m1_sdi0 */ - <3 RK_PD2 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi1: i2s1m1-sdi1 { - rockchip,pins = - /* i2s1m1_sdi1 */ - <3 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi2: i2s1m1-sdi2 { - rockchip,pins = - /* i2s1m1_sdi2 */ - <3 RK_PD4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi3: i2s1m1-sdi3 { - rockchip,pins = - /* i2s1m1_sdi3 */ - <3 RK_PD5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo0: i2s1m1-sdo0 { - rockchip,pins = - /* i2s1m1_sdo0 */ - <3 RK_PD1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo1: i2s1m1-sdo1 { - rockchip,pins = - /* i2s1m1_sdo1 */ - <4 RK_PB0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo2: i2s1m1-sdo2 { - rockchip,pins = - /* i2s1m1_sdo2 */ - <4 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo3: i2s1m1-sdo3 { - rockchip,pins = - /* i2s1m1_sdo3 */ - <4 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_lrckrx: i2s1m2-lrckrx { - rockchip,pins = - /* i2s1m2_lrckrx */ - <3 RK_PC5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_lrcktx: i2s1m2-lrcktx { - rockchip,pins = - /* i2s1m2_lrcktx */ - <2 RK_PD2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_mclk: i2s1m2-mclk { - rockchip,pins = - /* i2s1m2_mclk */ - <2 RK_PD0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sclkrx: i2s1m2-sclkrx { - rockchip,pins = - /* i2s1m2_sclkrx */ - <3 RK_PC3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sclktx: i2s1m2-sclktx { - rockchip,pins = - /* i2s1m2_sclktx */ - <2 RK_PD1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi0: i2s1m2-sdi0 { - rockchip,pins = - /* i2s1m2_sdi0 */ - <2 RK_PD3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi1: i2s1m2-sdi1 { - rockchip,pins = - /* i2s1m2_sdi1 */ - <2 RK_PD4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi2: i2s1m2-sdi2 { - rockchip,pins = - /* i2s1m2_sdi2 */ - <2 RK_PD5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi3: i2s1m2-sdi3 { - rockchip,pins = - /* i2s1m2_sdi3 */ - <2 RK_PD6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo0: i2s1m2-sdo0 { - rockchip,pins = - /* i2s1m2_sdo0 */ - <2 RK_PD7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo1: i2s1m2-sdo1 { - rockchip,pins = - /* i2s1m2_sdo1 */ - <3 RK_PA0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo2: i2s1m2-sdo2 { - rockchip,pins = - /* i2s1m2_sdo2 */ - <3 RK_PC1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo3: i2s1m2-sdo3 { - rockchip,pins = - /* i2s1m2_sdo3 */ - <3 RK_PC2 5 &pcfg_pull_none>; - }; - }; - - i2s2 { - /omit-if-no-ref/ - i2s2m0_lrckrx: i2s2m0-lrckrx { - rockchip,pins = - /* i2s2m0_lrckrx */ - <2 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_lrcktx: i2s2m0-lrcktx { - rockchip,pins = - /* i2s2m0_lrcktx */ - <2 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - /* i2s2m0_mclk */ - <2 RK_PC1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclkrx: i2s2m0-sclkrx { - rockchip,pins = - /* i2s2m0_sclkrx */ - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclktx: i2s2m0-sclktx { - rockchip,pins = - /* i2s2m0_sclktx */ - <2 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - /* i2s2m0_sdi */ - <2 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - /* i2s2m0_sdo */ - <2 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_lrckrx: i2s2m1-lrckrx { - rockchip,pins = - /* i2s2m1_lrckrx */ - <4 RK_PA5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_lrcktx: i2s2m1-lrcktx { - rockchip,pins = - /* i2s2m1_lrcktx */ - <4 RK_PA4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = - /* i2s2m1_mclk */ - <4 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sclkrx: i2s2m1-sclkrx { - rockchip,pins = - /* i2s2m1_sclkrx */ - <4 RK_PC1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sclktx: i2s2m1-sclktx { - rockchip,pins = - /* i2s2m1_sclktx */ - <4 RK_PB7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = - /* i2s2m1_sdi */ - <4 RK_PB2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = - /* i2s2m1_sdo */ - <4 RK_PB3 5 &pcfg_pull_none>; - }; - }; - - i2s3 { - /omit-if-no-ref/ - i2s3m0_lrck: i2s3m0-lrck { - rockchip,pins = - /* i2s3m0_lrck */ - <3 RK_PA4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_mclk: i2s3m0-mclk { - rockchip,pins = - /* i2s3m0_mclk */ - <3 RK_PA2 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_sclk: i2s3m0-sclk { - rockchip,pins = - /* i2s3m0_sclk */ - <3 RK_PA3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_sdi: i2s3m0-sdi { - rockchip,pins = - /* i2s3m0_sdi */ - <3 RK_PA6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_sdo: i2s3m0-sdo { - rockchip,pins = - /* i2s3m0_sdo */ - <3 RK_PA5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_lrck: i2s3m1-lrck { - rockchip,pins = - /* i2s3m1_lrck */ - <4 RK_PC4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_mclk: i2s3m1-mclk { - rockchip,pins = - /* i2s3m1_mclk */ - <4 RK_PC2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_sclk: i2s3m1-sclk { - rockchip,pins = - /* i2s3m1_sclk */ - <4 RK_PC3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_sdi: i2s3m1-sdi { - rockchip,pins = - /* i2s3m1_sdi */ - <4 RK_PC6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_sdo: i2s3m1-sdo { - rockchip,pins = - /* i2s3m1_sdo */ - <4 RK_PC5 5 &pcfg_pull_none>; - }; - }; - - isp { - /omit-if-no-ref/ - isp_pins: isp-pins { - rockchip,pins = - /* isp_flashtrigin */ - <4 RK_PB4 4 &pcfg_pull_none>, - /* isp_flashtrigout */ - <4 RK_PA6 1 &pcfg_pull_none>, - /* isp_prelighttrig */ - <4 RK_PB1 1 &pcfg_pull_none>; - }; - }; - - jtag { - /omit-if-no-ref/ - jtag_pins: jtag-pins { - rockchip,pins = - /* jtag_tck */ - <1 RK_PD7 2 &pcfg_pull_none>, - /* jtag_tms */ - <2 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - lcdc { - /omit-if-no-ref/ - lcdc_ctl: lcdc-ctl { - rockchip,pins = - /* lcdc_clk */ - <3 RK_PA0 1 &pcfg_pull_none>, - /* lcdc_d0 */ - <2 RK_PD0 1 &pcfg_pull_none>, - /* lcdc_d1 */ - <2 RK_PD1 1 &pcfg_pull_none>, - /* lcdc_d2 */ - <2 RK_PD2 1 &pcfg_pull_none>, - /* lcdc_d3 */ - <2 RK_PD3 1 &pcfg_pull_none>, - /* lcdc_d4 */ - <2 RK_PD4 1 &pcfg_pull_none>, - /* lcdc_d5 */ - <2 RK_PD5 1 &pcfg_pull_none>, - /* lcdc_d6 */ - <2 RK_PD6 1 &pcfg_pull_none>, - /* lcdc_d7 */ - <2 RK_PD7 1 &pcfg_pull_none>, - /* lcdc_d8 */ - <3 RK_PA1 1 &pcfg_pull_none>, - /* lcdc_d9 */ - <3 RK_PA2 1 &pcfg_pull_none>, - /* lcdc_d10 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* lcdc_d11 */ - <3 RK_PA4 1 &pcfg_pull_none>, - /* lcdc_d12 */ - <3 RK_PA5 1 &pcfg_pull_none>, - /* lcdc_d13 */ - <3 RK_PA6 1 &pcfg_pull_none>, - /* lcdc_d14 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* lcdc_d15 */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* lcdc_d16 */ - <3 RK_PB1 1 &pcfg_pull_none>, - /* lcdc_d17 */ - <3 RK_PB2 1 &pcfg_pull_none>, - /* lcdc_d18 */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* lcdc_d19 */ - <3 RK_PB4 1 &pcfg_pull_none>, - /* lcdc_d20 */ - <3 RK_PB5 1 &pcfg_pull_none>, - /* lcdc_d21 */ - <3 RK_PB6 1 &pcfg_pull_none>, - /* lcdc_d22 */ - <3 RK_PB7 1 &pcfg_pull_none>, - /* lcdc_d23 */ - <3 RK_PC0 1 &pcfg_pull_none>, - /* lcdc_den */ - <3 RK_PC3 1 &pcfg_pull_none>, - /* lcdc_hsync */ - <3 RK_PC1 1 &pcfg_pull_none>, - /* lcdc_vsync */ - <3 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - mcu { - /omit-if-no-ref/ - mcu_pins: mcu-pins { - rockchip,pins = - /* mcu_jtagtck */ - <0 RK_PB4 4 &pcfg_pull_none>, - /* mcu_jtagtdi */ - <0 RK_PC1 4 &pcfg_pull_none>, - /* mcu_jtagtdo */ - <0 RK_PB3 4 &pcfg_pull_none>, - /* mcu_jtagtms */ - <0 RK_PC2 4 &pcfg_pull_none>, - /* mcu_jtagtrstn */ - <0 RK_PC3 4 &pcfg_pull_none>; - }; - }; - - npu { - /omit-if-no-ref/ - npu_pins: npu-pins { - rockchip,pins = - /* npu_avs */ - <0 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - pcie20 { - /omit-if-no-ref/ - pcie20m0_pins: pcie20m0-pins { - rockchip,pins = - /* pcie20_clkreqnm0 */ - <0 RK_PA5 3 &pcfg_pull_none>, - /* pcie20_perstnm0 */ - <0 RK_PB6 3 &pcfg_pull_none>, - /* pcie20_wakenm0 */ - <0 RK_PB5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20m1_pins: pcie20m1-pins { - rockchip,pins = - /* pcie20_clkreqnm1 */ - <2 RK_PD0 4 &pcfg_pull_none>, - /* pcie20_perstnm1 */ - <3 RK_PC1 4 &pcfg_pull_none>, - /* pcie20_wakenm1 */ - <2 RK_PD1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20m2_pins: pcie20m2-pins { - rockchip,pins = - /* pcie20_clkreqnm2 */ - <1 RK_PB0 4 &pcfg_pull_none>, - /* pcie20_perstnm2 */ - <1 RK_PB2 4 &pcfg_pull_none>, - /* pcie20_wakenm2 */ - <1 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20_buttonrstn: pcie20-buttonrstn { - rockchip,pins = - /* pcie20_buttonrstn */ - <0 RK_PB4 3 &pcfg_pull_none>; - }; - }; - - pcie30x1 { - /omit-if-no-ref/ - pcie30x1m0_pins: pcie30x1m0-pins { - rockchip,pins = - /* pcie30x1_clkreqnm0 */ - <0 RK_PA4 3 &pcfg_pull_none>, - /* pcie30x1_perstnm0 */ - <0 RK_PC3 3 &pcfg_pull_none>, - /* pcie30x1_wakenm0 */ - <0 RK_PC2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m1_pins: pcie30x1m1-pins { - rockchip,pins = - /* pcie30x1_clkreqnm1 */ - <2 RK_PD2 4 &pcfg_pull_none>, - /* pcie30x1_perstnm1 */ - <3 RK_PA1 4 &pcfg_pull_none>, - /* pcie30x1_wakenm1 */ - <2 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m2_pins: pcie30x1m2-pins { - rockchip,pins = - /* pcie30x1_clkreqnm2 */ - <1 RK_PA5 4 &pcfg_pull_none>, - /* pcie30x1_perstnm2 */ - <1 RK_PA2 4 &pcfg_pull_none>, - /* pcie30x1_wakenm2 */ - <1 RK_PA3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1_buttonrstn: pcie30x1-buttonrstn { - rockchip,pins = - /* pcie30x1_buttonrstn */ - <0 RK_PB3 3 &pcfg_pull_none>; - }; - }; - - pcie30x2 { - /omit-if-no-ref/ - pcie30x2m0_pins: pcie30x2m0-pins { - rockchip,pins = - /* pcie30x2_clkreqnm0 */ - <0 RK_PA6 2 &pcfg_pull_none>, - /* pcie30x2_perstnm0 */ - <0 RK_PC6 3 &pcfg_pull_none>, - /* pcie30x2_wakenm0 */ - <0 RK_PC5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m1_pins: pcie30x2m1-pins { - rockchip,pins = - /* pcie30x2_clkreqnm1 */ - <2 RK_PD4 4 &pcfg_pull_none>, - /* pcie30x2_perstnm1 */ - <2 RK_PD6 4 &pcfg_pull_none>, - /* pcie30x2_wakenm1 */ - <2 RK_PD5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m2_pins: pcie30x2m2-pins { - rockchip,pins = - /* pcie30x2_clkreqnm2 */ - <4 RK_PC2 4 &pcfg_pull_none>, - /* pcie30x2_perstnm2 */ - <4 RK_PC4 4 &pcfg_pull_none>, - /* pcie30x2_wakenm2 */ - <4 RK_PC3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2_buttonrstn: pcie30x2-buttonrstn { - rockchip,pins = - /* pcie30x2_buttonrstn */ - <0 RK_PB0 3 &pcfg_pull_none>; - }; - }; - - pdm { - /omit-if-no-ref/ - pdmm0_clk: pdmm0-clk { - rockchip,pins = - /* pdm_clk0m0 */ - <1 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_clk1: pdmm0-clk1 { - rockchip,pins = - /* pdmm0_clk1 */ - <1 RK_PA4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi0: pdmm0-sdi0 { - rockchip,pins = - /* pdmm0_sdi0 */ - <1 RK_PB3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi1: pdmm0-sdi1 { - rockchip,pins = - /* pdmm0_sdi1 */ - <1 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi2: pdmm0-sdi2 { - rockchip,pins = - /* pdmm0_sdi2 */ - <1 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi3: pdmm0-sdi3 { - rockchip,pins = - /* pdmm0_sdi3 */ - <1 RK_PB0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_clk: pdmm1-clk { - rockchip,pins = - /* pdm_clk0m1 */ - <3 RK_PD6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_clk1: pdmm1-clk1 { - rockchip,pins = - /* pdmm1_clk1 */ - <4 RK_PA0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi0: pdmm1-sdi0 { - rockchip,pins = - /* pdmm1_sdi0 */ - <3 RK_PD7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi1: pdmm1-sdi1 { - rockchip,pins = - /* pdmm1_sdi1 */ - <4 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi2: pdmm1-sdi2 { - rockchip,pins = - /* pdmm1_sdi2 */ - <4 RK_PA2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi3: pdmm1-sdi3 { - rockchip,pins = - /* pdmm1_sdi3 */ - <4 RK_PA3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_clk1: pdmm2-clk1 { - rockchip,pins = - /* pdmm2_clk1 */ - <3 RK_PC4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi0: pdmm2-sdi0 { - rockchip,pins = - /* pdmm2_sdi0 */ - <3 RK_PB3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi1: pdmm2-sdi1 { - rockchip,pins = - /* pdmm2_sdi1 */ - <3 RK_PB4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi2: pdmm2-sdi2 { - rockchip,pins = - /* pdmm2_sdi2 */ - <3 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi3: pdmm2-sdi3 { - rockchip,pins = - /* pdmm2_sdi3 */ - <3 RK_PC0 5 &pcfg_pull_none>; - }; - }; - - pmic { - /omit-if-no-ref/ - pmic_pins: pmic-pins { - rockchip,pins = - /* pmic_sleep */ - <0 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - pmu { - /omit-if-no-ref/ - pmu_pins: pmu-pins { - rockchip,pins = - /* pmu_debug0 */ - <0 RK_PA5 4 &pcfg_pull_none>, - /* pmu_debug1 */ - <0 RK_PA6 3 &pcfg_pull_none>, - /* pmu_debug2 */ - <0 RK_PC4 4 &pcfg_pull_none>, - /* pmu_debug3 */ - <0 RK_PC5 4 &pcfg_pull_none>, - /* pmu_debug4 */ - <0 RK_PC6 4 &pcfg_pull_none>, - /* pmu_debug5 */ - <0 RK_PC7 4 &pcfg_pull_none>; - }; - }; - - pwm0 { - /omit-if-no-ref/ - pwm0m0_pins: pwm0m0-pins { - rockchip,pins = - /* pwm0_m0 */ - <0 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm0m1_pins: pwm0m1-pins { - rockchip,pins = - /* pwm0_m1 */ - <0 RK_PC7 2 &pcfg_pull_none>; - }; - }; - - pwm1 { - /omit-if-no-ref/ - pwm1m0_pins: pwm1m0-pins { - rockchip,pins = - /* pwm1_m0 */ - <0 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm1m1_pins: pwm1m1-pins { - rockchip,pins = - /* pwm1_m1 */ - <0 RK_PB5 4 &pcfg_pull_none>; - }; - }; - - pwm2 { - /omit-if-no-ref/ - pwm2m0_pins: pwm2m0-pins { - rockchip,pins = - /* pwm2_m0 */ - <0 RK_PC1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm2m1_pins: pwm2m1-pins { - rockchip,pins = - /* pwm2_m1 */ - <0 RK_PB6 4 &pcfg_pull_none>; - }; - }; - - pwm3 { - /omit-if-no-ref/ - pwm3_pins: pwm3-pins { - rockchip,pins = - /* pwm3_ir */ - <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - pwm4 { - /omit-if-no-ref/ - pwm4_pins: pwm4-pins { - rockchip,pins = - /* pwm4 */ - <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - pwm5 { - /omit-if-no-ref/ - pwm5_pins: pwm5-pins { - rockchip,pins = - /* pwm5 */ - <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - pwm6 { - /omit-if-no-ref/ - pwm6_pins: pwm6-pins { - rockchip,pins = - /* pwm6 */ - <0 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm7 { - /omit-if-no-ref/ - pwm7_pins: pwm7-pins { - rockchip,pins = - /* pwm7_ir */ - <0 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - pwm8 { - /omit-if-no-ref/ - pwm8m0_pins: pwm8m0-pins { - rockchip,pins = - /* pwm8_m0 */ - <3 RK_PB1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm8m1_pins: pwm8m1-pins { - rockchip,pins = - /* pwm8_m1 */ - <1 RK_PD5 4 &pcfg_pull_none>; - }; - }; - - pwm9 { - /omit-if-no-ref/ - pwm9m0_pins: pwm9m0-pins { - rockchip,pins = - /* pwm9_m0 */ - <3 RK_PB2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm9m1_pins: pwm9m1-pins { - rockchip,pins = - /* pwm9_m1 */ - <1 RK_PD6 4 &pcfg_pull_none>; - }; - }; - - pwm10 { - /omit-if-no-ref/ - pwm10m0_pins: pwm10m0-pins { - rockchip,pins = - /* pwm10_m0 */ - <3 RK_PB5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm10m1_pins: pwm10m1-pins { - rockchip,pins = - /* pwm10_m1 */ - <2 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm11 { - /omit-if-no-ref/ - pwm11m0_pins: pwm11m0-pins { - rockchip,pins = - /* pwm11_irm0 */ - <3 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m1_pins: pwm11m1-pins { - rockchip,pins = - /* pwm11_irm1 */ - <4 RK_PC0 3 &pcfg_pull_none>; - }; - }; - - pwm12 { - /omit-if-no-ref/ - pwm12m0_pins: pwm12m0-pins { - rockchip,pins = - /* pwm12_m0 */ - <3 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm12m1_pins: pwm12m1-pins { - rockchip,pins = - /* pwm12_m1 */ - <4 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm13 { - /omit-if-no-ref/ - pwm13m0_pins: pwm13m0-pins { - rockchip,pins = - /* pwm13_m0 */ - <3 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm13m1_pins: pwm13m1-pins { - rockchip,pins = - /* pwm13_m1 */ - <4 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - pwm14 { - /omit-if-no-ref/ - pwm14m0_pins: pwm14m0-pins { - rockchip,pins = - /* pwm14_m0 */ - <3 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm14m1_pins: pwm14m1-pins { - rockchip,pins = - /* pwm14_m1 */ - <4 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - pwm15 { - /omit-if-no-ref/ - pwm15m0_pins: pwm15m0-pins { - rockchip,pins = - /* pwm15_irm0 */ - <3 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m1_pins: pwm15m1-pins { - rockchip,pins = - /* pwm15_irm1 */ - <4 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - refclk { - /omit-if-no-ref/ - refclk_pins: refclk-pins { - rockchip,pins = - /* refclk_ou */ - <0 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - sata { - /omit-if-no-ref/ - sata_pins: sata-pins { - rockchip,pins = - /* sata_cpdet */ - <0 RK_PA4 2 &pcfg_pull_none>, - /* sata_cppod */ - <0 RK_PA6 1 &pcfg_pull_none>, - /* sata_mpswitch */ - <0 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - sata0 { - /omit-if-no-ref/ - sata0_pins: sata0-pins { - rockchip,pins = - /* sata0_actled */ - <4 RK_PC6 3 &pcfg_pull_none>; - }; - }; - - sata1 { - /omit-if-no-ref/ - sata1_pins: sata1-pins { - rockchip,pins = - /* sata1_actled */ - <4 RK_PC5 3 &pcfg_pull_none>; - }; - }; - - sata2 { - /omit-if-no-ref/ - sata2_pins: sata2-pins { - rockchip,pins = - /* sata2_actled */ - <4 RK_PC4 3 &pcfg_pull_none>; - }; - }; - - scr { - /omit-if-no-ref/ - scr_pins: scr-pins { - rockchip,pins = - /* scr_clk */ - <1 RK_PA2 3 &pcfg_pull_none>, - /* scr_det */ - <1 RK_PA7 3 &pcfg_pull_up>, - /* scr_io */ - <1 RK_PA3 3 &pcfg_pull_up>, - /* scr_rst */ - <1 RK_PA5 3 &pcfg_pull_none>; - }; - }; - - sdmmc0 { - /omit-if-no-ref/ - sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = - /* sdmmc0_d0 */ - <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d1 */ - <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d2 */ - <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d3 */ - <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc0_clk: sdmmc0-clk { - rockchip,pins = - /* sdmmc0_clk */ - <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = - /* sdmmc0_cmd */ - <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc0_det: sdmmc0-det { - rockchip,pins = - /* sdmmc0_det */ - <0 RK_PA4 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc0_pwren: sdmmc0-pwren { - rockchip,pins = - /* sdmmc0_pwren */ - <0 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - sdmmc1 { - /omit-if-no-ref/ - sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = - /* sdmmc1_d0 */ - <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d1 */ - <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d2 */ - <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d3 */ - <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc1_clk: sdmmc1-clk { - rockchip,pins = - /* sdmmc1_clk */ - <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = - /* sdmmc1_cmd */ - <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc1_det: sdmmc1-det { - rockchip,pins = - /* sdmmc1_det */ - <2 RK_PB2 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc1_pwren: sdmmc1-pwren { - rockchip,pins = - /* sdmmc1_pwren */ - <2 RK_PB1 1 &pcfg_pull_none>; - }; - }; - - sdmmc2 { - /omit-if-no-ref/ - sdmmc2m0_bus4: sdmmc2m0-bus4 { - rockchip,pins = - /* sdmmc2_d0m0 */ - <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d1m0 */ - <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d2m0 */ - <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d3m0 */ - <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m0_clk: sdmmc2m0-clk { - rockchip,pins = - /* sdmmc2_clkm0 */ - <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m0_cmd: sdmmc2m0-cmd { - rockchip,pins = - /* sdmmc2_cmdm0 */ - <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m0_det: sdmmc2m0-det { - rockchip,pins = - /* sdmmc2_detm0 */ - <3 RK_PD4 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc2m0_pwren: sdmmc2m0-pwren { - rockchip,pins = - /* sdmmc2m0_pwren */ - <3 RK_PD5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sdmmc2m1_bus4: sdmmc2m1-bus4 { - rockchip,pins = - /* sdmmc2_d0m1 */ - <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d1m1 */ - <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d2m1 */ - <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d3m1 */ - <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m1_clk: sdmmc2m1-clk { - rockchip,pins = - /* sdmmc2_clkm1 */ - <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m1_cmd: sdmmc2m1-cmd { - rockchip,pins = - /* sdmmc2_cmdm1 */ - <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m1_det: sdmmc2m1-det { - rockchip,pins = - /* sdmmc2_detm1 */ - <3 RK_PA7 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc2m1_pwren: sdmmc2m1-pwren { - rockchip,pins = - /* sdmmc2m1_pwren */ - <3 RK_PB0 4 &pcfg_pull_none>; - }; - }; - - spdif { - /omit-if-no-ref/ - spdifm0_tx: spdifm0-tx { - rockchip,pins = - /* spdifm0_tx */ - <1 RK_PA4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdifm1_tx: spdifm1-tx { - rockchip,pins = - /* spdifm1_tx */ - <3 RK_PC5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdifm2_tx: spdifm2-tx { - rockchip,pins = - /* spdifm2_tx */ - <4 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - spi0 { - /omit-if-no-ref/ - spi0m0_pins: spi0m0-pins { - rockchip,pins = - /* spi0_clkm0 */ - <0 RK_PB5 2 &pcfg_pull_none>, - /* spi0_misom0 */ - <0 RK_PC5 2 &pcfg_pull_none>, - /* spi0_mosim0 */ - <0 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = - /* spi0_cs0m0 */ - <0 RK_PC6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = - /* spi0_cs1m0 */ - <0 RK_PC4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m1_pins: spi0m1-pins { - rockchip,pins = - /* spi0_clkm1 */ - <2 RK_PD3 3 &pcfg_pull_none>, - /* spi0_misom1 */ - <2 RK_PD0 3 &pcfg_pull_none>, - /* spi0_mosim1 */ - <2 RK_PD1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = - /* spi0_cs0m1 */ - <2 RK_PD2 3 &pcfg_pull_none>; - }; - }; - - spi1 { - /omit-if-no-ref/ - spi1m0_pins: spi1m0-pins { - rockchip,pins = - /* spi1_clkm0 */ - <2 RK_PB5 3 &pcfg_pull_none>, - /* spi1_misom0 */ - <2 RK_PB6 3 &pcfg_pull_none>, - /* spi1_mosim0 */ - <2 RK_PB7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m0_cs0: spi1m0-cs0 { - rockchip,pins = - /* spi1_cs0m0 */ - <2 RK_PC0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m0_cs1: spi1m0-cs1 { - rockchip,pins = - /* spi1_cs1m0 */ - <2 RK_PC6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m1_pins: spi1m1-pins { - rockchip,pins = - /* spi1_clkm1 */ - <3 RK_PC3 3 &pcfg_pull_none>, - /* spi1_misom1 */ - <3 RK_PC2 3 &pcfg_pull_none>, - /* spi1_mosim1 */ - <3 RK_PC1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m1_cs0: spi1m1-cs0 { - rockchip,pins = - /* spi1_cs0m1 */ - <3 RK_PA1 3 &pcfg_pull_none>; - }; - }; - - spi2 { - /omit-if-no-ref/ - spi2m0_pins: spi2m0-pins { - rockchip,pins = - /* spi2_clkm0 */ - <2 RK_PC1 4 &pcfg_pull_none>, - /* spi2_misom0 */ - <2 RK_PC2 4 &pcfg_pull_none>, - /* spi2_mosim0 */ - <2 RK_PC3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m0_cs0: spi2m0-cs0 { - rockchip,pins = - /* spi2_cs0m0 */ - <2 RK_PC4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m0_cs1: spi2m0-cs1 { - rockchip,pins = - /* spi2_cs1m0 */ - <2 RK_PC5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m1_pins: spi2m1-pins { - rockchip,pins = - /* spi2_clkm1 */ - <3 RK_PA0 3 &pcfg_pull_none>, - /* spi2_misom1 */ - <2 RK_PD7 3 &pcfg_pull_none>, - /* spi2_mosim1 */ - <2 RK_PD6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m1_cs0: spi2m1-cs0 { - rockchip,pins = - /* spi2_cs0m1 */ - <2 RK_PD5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m1_cs1: spi2m1-cs1 { - rockchip,pins = - /* spi2_cs1m1 */ - <2 RK_PD4 3 &pcfg_pull_none>; - }; - }; - - spi3 { - /omit-if-no-ref/ - spi3m0_pins: spi3m0-pins { - rockchip,pins = - /* spi3_clkm0 */ - <4 RK_PB3 4 &pcfg_pull_none>, - /* spi3_misom0 */ - <4 RK_PB0 4 &pcfg_pull_none>, - /* spi3_mosim0 */ - <4 RK_PB2 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m0_cs0: spi3m0-cs0 { - rockchip,pins = - /* spi3_cs0m0 */ - <4 RK_PA6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m0_cs1: spi3m0-cs1 { - rockchip,pins = - /* spi3_cs1m0 */ - <4 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m1_pins: spi3m1-pins { - rockchip,pins = - /* spi3_clkm1 */ - <4 RK_PC2 2 &pcfg_pull_none>, - /* spi3_misom1 */ - <4 RK_PC5 2 &pcfg_pull_none>, - /* spi3_mosim1 */ - <4 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m1_cs0: spi3m1-cs0 { - rockchip,pins = - /* spi3_cs0m1 */ - <4 RK_PC6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m1_cs1: spi3m1-cs1 { - rockchip,pins = - /* spi3_cs1m1 */ - <4 RK_PD1 2 &pcfg_pull_none>; - }; - }; - - tsadc { - /omit-if-no-ref/ - tsadcm0_shut: tsadcm0-shut { - rockchip,pins = - /* tsadcm0_shut */ - <0 RK_PA1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadcm1_shut: tsadcm1-shut { - rockchip,pins = - /* tsadcm1_shut */ - <0 RK_PA2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadc_shutorg: tsadc-shutorg { - rockchip,pins = - /* tsadc_shutorg */ - <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - uart0 { - /omit-if-no-ref/ - uart0_xfer: uart0-xfer { - rockchip,pins = - /* uart0_rx */ - <0 RK_PC0 3 &pcfg_pull_up>, - /* uart0_tx */ - <0 RK_PC1 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0_ctsn: uart0-ctsn { - rockchip,pins = - /* uart0_ctsn */ - <0 RK_PC7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart0_rtsn: uart0-rtsn { - rockchip,pins = - /* uart0_rtsn */ - <0 RK_PC4 3 &pcfg_pull_none>; - }; - }; - - uart1 { - /omit-if-no-ref/ - uart1m0_xfer: uart1m0-xfer { - rockchip,pins = - /* uart1_rxm0 */ - <2 RK_PB3 2 &pcfg_pull_up>, - /* uart1_txm0 */ - <2 RK_PB4 2 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m0_ctsn: uart1m0-ctsn { - rockchip,pins = - /* uart1m0_ctsn */ - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m0_rtsn: uart1m0-rtsn { - rockchip,pins = - /* uart1m0_rtsn */ - <2 RK_PB5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m1_xfer: uart1m1-xfer { - rockchip,pins = - /* uart1_rxm1 */ - <3 RK_PD7 4 &pcfg_pull_up>, - /* uart1_txm1 */ - <3 RK_PD6 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m1_ctsn: uart1m1-ctsn { - rockchip,pins = - /* uart1m1_ctsn */ - <4 RK_PC1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m1_rtsn: uart1m1-rtsn { - rockchip,pins = - /* uart1m1_rtsn */ - <4 RK_PB6 4 &pcfg_pull_none>; - }; - }; - - uart2 { - /omit-if-no-ref/ - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - /* uart2_rxm0 */ - <0 RK_PD0 1 &pcfg_pull_up>, - /* uart2_txm0 */ - <0 RK_PD1 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - /* uart2_rxm1 */ - <1 RK_PD6 2 &pcfg_pull_up>, - /* uart2_txm1 */ - <1 RK_PD5 2 &pcfg_pull_up>; - }; - }; - - uart3 { - /omit-if-no-ref/ - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - /* uart3_rxm0 */ - <1 RK_PA0 2 &pcfg_pull_up>, - /* uart3_txm0 */ - <1 RK_PA1 2 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3m0_ctsn: uart3m0-ctsn { - rockchip,pins = - /* uart3m0_ctsn */ - <1 RK_PA3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart3m0_rtsn: uart3m0-rtsn { - rockchip,pins = - /* uart3m0_rtsn */ - <1 RK_PA2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - /* uart3_rxm1 */ - <3 RK_PC0 4 &pcfg_pull_up>, - /* uart3_txm1 */ - <3 RK_PB7 4 &pcfg_pull_up>; - }; - }; - - uart4 { - /omit-if-no-ref/ - uart4m0_xfer: uart4m0-xfer { - rockchip,pins = - /* uart4_rxm0 */ - <1 RK_PA4 2 &pcfg_pull_up>, - /* uart4_txm0 */ - <1 RK_PA6 2 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4m0_ctsn: uart4m0-ctsn { - rockchip,pins = - /* uart4m0_ctsn */ - <1 RK_PA7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart4m0_rtsn: uart4m0-rtsn { - rockchip,pins = - /* uart4m0_rtsn */ - <1 RK_PA5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart4m1_xfer: uart4m1-xfer { - rockchip,pins = - /* uart4_rxm1 */ - <3 RK_PB1 4 &pcfg_pull_up>, - /* uart4_txm1 */ - <3 RK_PB2 4 &pcfg_pull_up>; - }; - }; - - uart5 { - /omit-if-no-ref/ - uart5m0_xfer: uart5m0-xfer { - rockchip,pins = - /* uart5_rxm0 */ - <2 RK_PA1 3 &pcfg_pull_up>, - /* uart5_txm0 */ - <2 RK_PA2 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart5m0_ctsn: uart5m0-ctsn { - rockchip,pins = - /* uart5m0_ctsn */ - <1 RK_PD7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m0_rtsn: uart5m0-rtsn { - rockchip,pins = - /* uart5m0_rtsn */ - <2 RK_PA0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m1_xfer: uart5m1-xfer { - rockchip,pins = - /* uart5_rxm1 */ - <3 RK_PC3 4 &pcfg_pull_up>, - /* uart5_txm1 */ - <3 RK_PC2 4 &pcfg_pull_up>; - }; - }; - - uart6 { - /omit-if-no-ref/ - uart6m0_xfer: uart6m0-xfer { - rockchip,pins = - /* uart6_rxm0 */ - <2 RK_PA3 3 &pcfg_pull_up>, - /* uart6_txm0 */ - <2 RK_PA4 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart6m0_ctsn: uart6m0-ctsn { - rockchip,pins = - /* uart6m0_ctsn */ - <2 RK_PC0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m0_rtsn: uart6m0-rtsn { - rockchip,pins = - /* uart6m0_rtsn */ - <2 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m1_xfer: uart6m1-xfer { - rockchip,pins = - /* uart6_rxm1 */ - <1 RK_PD6 3 &pcfg_pull_up>, - /* uart6_txm1 */ - <1 RK_PD5 3 &pcfg_pull_up>; - }; - }; - - uart7 { - /omit-if-no-ref/ - uart7m0_xfer: uart7m0-xfer { - rockchip,pins = - /* uart7_rxm0 */ - <2 RK_PA5 3 &pcfg_pull_up>, - /* uart7_txm0 */ - <2 RK_PA6 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m0_ctsn: uart7m0-ctsn { - rockchip,pins = - /* uart7m0_ctsn */ - <2 RK_PC2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m0_rtsn: uart7m0-rtsn { - rockchip,pins = - /* uart7m0_rtsn */ - <2 RK_PC1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m1_xfer: uart7m1-xfer { - rockchip,pins = - /* uart7_rxm1 */ - <3 RK_PC5 4 &pcfg_pull_up>, - /* uart7_txm1 */ - <3 RK_PC4 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m2_xfer: uart7m2-xfer { - rockchip,pins = - /* uart7_rxm2 */ - <4 RK_PA3 4 &pcfg_pull_up>, - /* uart7_txm2 */ - <4 RK_PA2 4 &pcfg_pull_up>; - }; - }; - - uart8 { - /omit-if-no-ref/ - uart8m0_xfer: uart8m0-xfer { - rockchip,pins = - /* uart8_rxm0 */ - <2 RK_PC6 2 &pcfg_pull_up>, - /* uart8_txm0 */ - <2 RK_PC5 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart8m0_ctsn: uart8m0-ctsn { - rockchip,pins = - /* uart8m0_ctsn */ - <2 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m0_rtsn: uart8m0-rtsn { - rockchip,pins = - /* uart8m0_rtsn */ - <2 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m1_xfer: uart8m1-xfer { - rockchip,pins = - /* uart8_rxm1 */ - <3 RK_PA0 4 &pcfg_pull_up>, - /* uart8_txm1 */ - <2 RK_PD7 4 &pcfg_pull_up>; - }; - }; - - uart9 { - /omit-if-no-ref/ - uart9m0_xfer: uart9m0-xfer { - rockchip,pins = - /* uart9_rxm0 */ - <2 RK_PA7 3 &pcfg_pull_up>, - /* uart9_txm0 */ - <2 RK_PB0 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m0_ctsn: uart9m0-ctsn { - rockchip,pins = - /* uart9m0_ctsn */ - <2 RK_PC4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m0_rtsn: uart9m0-rtsn { - rockchip,pins = - /* uart9m0_rtsn */ - <2 RK_PC3 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m1_xfer: uart9m1-xfer { - rockchip,pins = - /* uart9_rxm1 */ - <4 RK_PC6 4 &pcfg_pull_up>, - /* uart9_txm1 */ - <4 RK_PC5 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m2_xfer: uart9m2-xfer { - rockchip,pins = - /* uart9_rxm2 */ - <4 RK_PA5 4 &pcfg_pull_up>, - /* uart9_txm2 */ - <4 RK_PA4 4 &pcfg_pull_up>; - }; - }; - - vop { - /omit-if-no-ref/ - vopm0_pins: vopm0-pins { - rockchip,pins = - /* vop_pwmm0 */ - <0 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - vopm1_pins: vopm1-pins { - rockchip,pins = - /* vop_pwmm1 */ - <3 RK_PC4 2 &pcfg_pull_none>; - }; - }; -}; - -/* - * This part is edited handly. - */ -&pinctrl { - spi0-hs { - /omit-if-no-ref/ - spi0m0_pins_hs: spi0m0-pins { - rockchip,pins = - /* spi0_clkm0 */ - <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, - /* spi0_misom0 */ - <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, - /* spi0_mosim0 */ - <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs0_hs: spi0m0-cs0 { - rockchip,pins = - /* spi0_cs0m0 */ - <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs1_hs: spi0m0-cs1 { - rockchip,pins = - /* spi0_cs1m0 */ - <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_pins_hs: spi0m1-pins { - rockchip,pins = - /* spi0_clkm1 */ - <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, - /* spi0_misom1 */ - <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, - /* spi0_mosim1 */ - <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_cs0_hs: spi0m1-cs0 { - rockchip,pins = - /* spi0_cs0m1 */ - <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi1-hs { - /omit-if-no-ref/ - spi1m0_pins_hs: spi1m0-pins { - rockchip,pins = - /* spi1_clkm0 */ - <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, - /* spi1_misom0 */ - <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, - /* spi1_mosim0 */ - <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs0_hs: spi1m0-cs0 { - rockchip,pins = - /* spi1_cs0m0 */ - <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs1_hs: spi1m0-cs1 { - rockchip,pins = - /* spi1_cs1m0 */ - <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_pins_hs: spi1m1-pins { - rockchip,pins = - /* spi1_clkm1 */ - <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, - /* spi1_misom1 */ - <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, - /* spi1_mosim1 */ - <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_cs0_hs: spi1m1-cs0 { - rockchip,pins = - /* spi1_cs0m1 */ - <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi2-hs { - /omit-if-no-ref/ - spi2m0_pins_hs: spi2m0-pins { - rockchip,pins = - /* spi2_clkm0 */ - <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, - /* spi2_misom0 */ - <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, - /* spi2_mosim0 */ - <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs0_hs: spi2m0-cs0 { - rockchip,pins = - /* spi2_cs0m0 */ - <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs1_hs: spi2m0-cs1 { - rockchip,pins = - /* spi2_cs1m0 */ - <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_pins_hs: spi2m1-pins { - rockchip,pins = - /* spi2_clkm1 */ - <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, - /* spi2_misom1 */ - <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, - /* spi2_mosim1 */ - <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs0_hs: spi2m1-cs0 { - rockchip,pins = - /* spi2_cs0m1 */ - <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs1_hs: spi2m1-cs1 { - rockchip,pins = - /* spi2_cs1m1 */ - <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi3-hs { - /omit-if-no-ref/ - spi3m0_pins_hs: spi3m0-pins { - rockchip,pins = - /* spi3_clkm0 */ - <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, - /* spi3_misom0 */ - <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, - /* spi3_mosim0 */ - <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs0_hs: spi3m0-cs0 { - rockchip,pins = - /* spi3_cs0m0 */ - <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs1_hs: spi3m0-cs1 { - rockchip,pins = - /* spi3_cs1m0 */ - <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_pins_hs: spi3m1-pins { - rockchip,pins = - /* spi3_clkm1 */ - <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, - /* spi3_misom1 */ - <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, - /* spi3_mosim1 */ - <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs0_hs: spi3m1-cs0 { - rockchip,pins = - /* spi3_cs0m1 */ - <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs1_hs: spi3m1-cs1 { - rockchip,pins = - /* spi3_cs1m1 */ - <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; - }; - }; - - gmac-txd-level3 { - /omit-if-no-ref/ - gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { - rockchip,pins = - /* gmac0_txd0 */ - <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, - /* gmac0_txd1 */ - <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, - /* gmac0_txen */ - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { - rockchip,pins = - /* gmac0_rxd2 */ - <2 RK_PA3 2 &pcfg_pull_none>, - /* gmac0_rxd3 */ - <2 RK_PA4 2 &pcfg_pull_none>, - /* gmac0_txd2 */ - <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, - /* gmac0_txd3 */ - <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; - }; - - /omit-if-no-ref/ - gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { - rockchip,pins = - /* gmac1_txd0m0 */ - <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd1m0 */ - <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txenm0 */ - <3 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { - rockchip,pins = - /* gmac1_rxd2m0 */ - <3 RK_PA4 3 &pcfg_pull_none>, - /* gmac1_rxd3m0 */ - <3 RK_PA5 3 &pcfg_pull_none>, - /* gmac1_txd2m0 */ - <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd3m0 */ - <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; - }; - - /omit-if-no-ref/ - gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { - rockchip,pins = - /* gmac1_txd0m1 */ - <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd1m1 */ - <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txenm1 */ - <4 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { - rockchip,pins = - /* gmac1_rxd2m1 */ - <4 RK_PA1 3 &pcfg_pull_none>, - /* gmac1_rxd3m1 */ - <4 RK_PA2 3 &pcfg_pull_none>, - /* gmac1_txd2m1 */ - <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd3m1 */ - <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; - }; - }; - - gmac-txc-level2 { - /omit-if-no-ref/ - gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { - rockchip,pins = - /* gmac0_rxclk */ - <2 RK_PA5 2 &pcfg_pull_none>, - /* gmac0_txclk */ - <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { - rockchip,pins = - /* gmac1_rxclkm0 */ - <3 RK_PA7 3 &pcfg_pull_none>, - /* gmac1_txclkm0 */ - <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { - rockchip,pins = - /* gmac1_rxclkm1 */ - <4 RK_PA3 3 &pcfg_pull_none>, - /* gmac1_txclkm1 */ - <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; - }; - }; -}; diff --git a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568.dtsi deleted file mode 100644 index 2bdf8c7e9..000000000 --- a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include "rk356x.dtsi" - -/ { - compatible = "rockchip,rk3568"; - - sata0: sata@fc000000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc000000 0 0x1000>; - clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, - <&cru CLK_SATA0_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - phys = <&combphy0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - pipe_phy_grf0: syscon@fdc70000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc70000 0x0 0x1000>; - }; - - qos_pcie3x1: qos@fe190080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190080 0x0 0x20>; - }; - - qos_pcie3x2: qos@fe190100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190100 0x0 0x20>; - }; - - qos_sata0: qos@fe190200 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190200 0x0 0x20>; - }; - - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, - <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref"; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,rd_osr_lmt = <8>; - snps,wr_osr_lmt = <4>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - combphy0: phy@fe820000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe820000 0x0 0x100>; - clocks = <&pmucru CLK_PCIEPHY0_REF>, - <&cru PCLK_PIPEPHY0>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY0>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf0>; - #phy-cells = <1>; - status = "disabled"; - }; -}; - -&cpu0_opp_table { - opp-1992000000 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1150000 1150000 1150000>; - }; -}; - -&pipegrf { - compatible = "rockchip,rk3568-pipe-grf", "syscon"; -}; - -&power { - power-domain@RK3568_PD_PIPE { - reg = ; - clocks = <&cru PCLK_PIPE>; - pm_qos = <&qos_pcie2x1>, - <&qos_pcie3x1>, - <&qos_pcie3x2>, - <&qos_sata0>, - <&qos_sata1>, - <&qos_sata2>, - <&qos_usb3_0>, - <&qos_usb3_1>; - #power-domain-cells = <0>; - }; -}; - -&usb_host0_xhci { - phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; -}; - -&vop { - compatible = "rockchip,rk3568-vop"; -}; diff --git a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk356x.dtsi deleted file mode 100644 index 319981c3e..000000000 --- a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ /dev/null @@ -1,1706 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - clocks = <&scmi_clk 0>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000 900000 1150000>; - clock-latency-ns = <40000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <900000 900000 1150000>; - opp-suspend; - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <975000 975000 1150000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1050000 1050000 1150000>; - }; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - }; - }; - - gpu_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <825000>; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <825000>; - }; - - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <900000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - }; - }; - - hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "HDMI"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - status = "disabled"; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - pinctrl-0 = <&clk32k_out0>; - pinctrl-names = "default"; - #clock-cells = <0>; - }; - - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - sata1: sata@fc400000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc400000 0 0x1000>; - clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, - <&cru CLK_SATA1_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - phys = <&combphy1 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - sata2: sata@fc800000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc800000 0 0x1000>; - clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, - <&cru CLK_SATA2_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - phys = <&combphy2 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - usb_host0_xhci: usb@fcc00000 { - compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfcc00000 0x0 0x400000>; - interrupts = ; - clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "otg"; - phy_type = "utmi_wide"; - power-domains = <&power RK3568_PD_PIPE>; - resets = <&cru SRST_USB3OTG0>; - snps,dis_u2_susphy_quirk; - status = "disabled"; - }; - - usb_host1_xhci: usb@fd000000 { - compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfd000000 0x0 0x400000>; - interrupts = ; - clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "host"; - phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3568_PD_PIPE>; - resets = <&cru SRST_USB3OTG1>; - snps,dis_u2_susphy_quirk; - status = "disabled"; - }; - - gic: interrupt-controller@fd400000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ - <0x0 0xfd460000 0 0x80000>; /* GICR */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - mbi-alias = <0x0 0xfd410000>; - mbi-ranges = <296 24>; - msi-controller; - }; - - usb_host0_ehci: usb@fd800000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd800000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@fd840000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd840000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@fd880000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd880000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@fd8c0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd8c0000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - pmugrf: syscon@fdc20000 { - compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc20000 0x0 0x10000>; - - pmu_io_domains: io-domains { - compatible = "rockchip,rk3568-pmu-io-voltage-domain"; - status = "disabled"; - }; - }; - - pipegrf: syscon@fdc50000 { - reg = <0x0 0xfdc50000 0x0 0x1000>; - }; - - grf: syscon@fdc60000 { - compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc60000 0x0 0x10000>; - }; - - pipe_phy_grf1: syscon@fdc80000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc80000 0x0 0x1000>; - }; - - pipe_phy_grf2: syscon@fdc90000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc90000 0x0 0x1000>; - }; - - usb2phy0_grf: syscon@fdca0000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca0000 0x0 0x8000>; - }; - - usb2phy1_grf: syscon@fdca8000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca8000 0x0 0x8000>; - }; - - pmucru: clock-controller@fdd00000 { - compatible = "rockchip,rk3568-pmucru"; - reg = <0x0 0xfdd00000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@fdd20000 { - compatible = "rockchip,rk3568-cru"; - reg = <0x0 0xfdd20000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; - assigned-clock-rates = <1200000000>, <200000000>; - rockchip,grf = <&grf>; - }; - - i2c0: i2c@fdd40000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfdd40000 0x0 0x1000>; - interrupts = ; - clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fdd50000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfdd50000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 0>, <&dmac0 1>; - pinctrl-0 = <&uart0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm0: pwm@fdd70000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70000 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fdd70010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70010 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fdd70020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70020 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fdd70030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70030 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu: power-management@fdd90000 { - compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xfdd90000 0x0 0x1000>; - - power: power-controller { - compatible = "rockchip,rk3568-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* These power domains are grouped by VD_GPU */ - power-domain@RK3568_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU_PRE>, - <&cru PCLK_GPU_PRE>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - - /* These power domains are grouped by VD_LOGIC */ - power-domain@RK3568_PD_VI { - reg = ; - clocks = <&cru HCLK_VI>, - <&cru PCLK_VI>; - pm_qos = <&qos_isp>, - <&qos_vicap0>, - <&qos_vicap1>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_VO { - reg = ; - clocks = <&cru HCLK_VO>, - <&cru PCLK_VO>, - <&cru ACLK_VOP_PRE>; - pm_qos = <&qos_hdcp>, - <&qos_vop_m0>, - <&qos_vop_m1>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_RGA { - reg = ; - clocks = <&cru HCLK_RGA_PRE>, - <&cru PCLK_RGA_PRE>; - pm_qos = <&qos_ebc>, - <&qos_iep>, - <&qos_jpeg_dec>, - <&qos_jpeg_enc>, - <&qos_rga_rd>, - <&qos_rga_wr>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_VPU { - reg = ; - clocks = <&cru HCLK_VPU_PRE>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_RKVDEC { - clocks = <&cru HCLK_RKVDEC_PRE>; - reg = ; - pm_qos = <&qos_rkvdec>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_RKVENC { - reg = ; - clocks = <&cru HCLK_RKVENC_PRE>; - pm_qos = <&qos_rkvenc_rd_m0>, - <&qos_rkvenc_rd_m1>, - <&qos_rkvenc_wr_m0>; - #power-domain-cells = <0>; - }; - }; - }; - - gpu: gpu@fde60000 { - compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; - reg = <0x0 0xfde60000 0x0 0x4000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&scmi_clk 1>, <&cru CLK_GPU>; - clock-names = "gpu", "bus"; - #cooling-cells = <2>; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3568_PD_GPU>; - status = "disabled"; - }; - - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, - <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC2>; - reset-names = "reset"; - status = "disabled"; - }; - - gmac1: ethernet@fe010000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe010000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, - <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref"; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,rd_osr_lmt = <8>; - snps,wr_osr_lmt = <4>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - vop: vop@fe040000 { - reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; - clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; - iommus = <&vop_mmu>; - power-domains = <&power RK3568_PD_VO>; - rockchip,grf = <&grf>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - vp1: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - vp2: port@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - vop_mmu: iommu@fe043e00 { - compatible = "rockchip,rk3568-iommu"; - reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@fe0a0000 { - compatible = "rockchip,rk3568-dw-hdmi"; - reg = <0x0 0xfe0a0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru PCLK_HDMI_HOST>, - <&cru CLK_HDMI_SFR>, - <&cru CLK_HDMI_CEC>, - <&pmucru CLK_HDMI_REF>, - <&cru HCLK_VO>; - clock-names = "iahb", "isfr", "cec", "ref"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; - power-domains = <&power RK3568_PD_VO>; - reg-io-width = <4>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; - }; - - qos_rkvenc_rd_m0: qos@fe138080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe138080 0x0 0x20>; - }; - - qos_rkvenc_rd_m1: qos@fe138100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe138100 0x0 0x20>; - }; - - qos_rkvenc_wr_m0: qos@fe138180 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe138180 0x0 0x20>; - }; - - qos_isp: qos@fe148000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe148000 0x0 0x20>; - }; - - qos_vicap0: qos@fe148080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe148080 0x0 0x20>; - }; - - qos_vicap1: qos@fe148100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe148100 0x0 0x20>; - }; - - qos_vpu: qos@fe150000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe150000 0x0 0x20>; - }; - - qos_ebc: qos@fe158000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158000 0x0 0x20>; - }; - - qos_iep: qos@fe158100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158100 0x0 0x20>; - }; - - qos_jpeg_dec: qos@fe158180 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158180 0x0 0x20>; - }; - - qos_jpeg_enc: qos@fe158200 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158200 0x0 0x20>; - }; - - qos_rga_rd: qos@fe158280 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158280 0x0 0x20>; - }; - - qos_rga_wr: qos@fe158300 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158300 0x0 0x20>; - }; - - qos_npu: qos@fe180000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe180000 0x0 0x20>; - }; - - qos_pcie2x1: qos@fe190000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190000 0x0 0x20>; - }; - - qos_sata1: qos@fe190280 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190280 0x0 0x20>; - }; - - qos_sata2: qos@fe190300 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190300 0x0 0x20>; - }; - - qos_usb3_0: qos@fe190380 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190380 0x0 0x20>; - }; - - qos_usb3_1: qos@fe190400 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190400 0x0 0x20>; - }; - - qos_rkvdec: qos@fe198000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe198000 0x0 0x20>; - }; - - qos_hdcp: qos@fe1a8000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8000 0x0 0x20>; - }; - - qos_vop_m0: qos@fe1a8080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8080 0x0 0x20>; - }; - - qos_vop_m1: qos@fe1a8100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8100 0x0 0x20>; - }; - - pcie2x1: pcie@fe260000 { - compatible = "rockchip,rk3568-pcie"; - reg = <0x3 0xc0000000 0x0 0x00400000>, - <0x0 0xfe260000 0x0 0x00010000>, - <0x3 0x3f000000 0x0 0x01000000>; - reg-names = "dbi", "apb", "config"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msi", "legacy", "err"; - bus-range = <0x0 0xf>; - clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, - <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX_NDFT>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type = "pci"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - linux,pci-domain = <0>; - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; - num-lanes = <1>; - phys = <&combphy2 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 - 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; - resets = <&cru SRST_PCIE20_POWERUP>; - reset-names = "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc: legacy-interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - sdmmc0: mmc@fe2b0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, - <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdmmc1: mmc@fe2c0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, - <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC1>; - reset-names = "reset"; - status = "disabled"; - }; - - sfc: spi@fe300000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe300000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&fspi_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sdhci: mmc@fe310000 { - compatible = "rockchip,rk3568-dwcmshc"; - reg = <0x0 0xfe310000 0x0 0x10000>; - interrupts = ; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - spdif: spdif@fe460000 { - compatible = "rockchip,rk3568-spdif"; - reg = <0x0 0xfe460000 0x0 0x1000>; - interrupts = ; - clock-names = "mclk", "hclk"; - clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; - dmas = <&dmac1 1>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdifm0_tx>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s0_8ch: i2s@fe400000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe400000 0x0 0x1000>; - interrupts = ; - assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; - assigned-clock-rates = <1188000000>, <1188000000>; - clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 0>; - dma-names = "tx"; - resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_8ch: i2s@fe410000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe410000 0x0 0x1000>; - interrupts = ; - assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; - assigned-clock-rates = <1188000000>, <1188000000>; - clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, - <&cru HCLK_I2S1_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 3>, <&dmac1 2>; - dma-names = "rx", "tx"; - resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx - &i2s1m0_lrcktx &i2s1m0_lrckrx - &i2s1m0_sdi0 &i2s1m0_sdi1 - &i2s1m0_sdi2 &i2s1m0_sdi3 - &i2s1m0_sdo0 &i2s1m0_sdo1 - &i2s1m0_sdo2 &i2s1m0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s3_2ch: i2s@fe430000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe430000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, - <&cru HCLK_I2S3_2CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 6>, <&dmac1 7>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pdm: pdm@fe440000 { - compatible = "rockchip,rk3568-pdm"; - reg = <0x0 0xfe440000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&dmac1 9>; - dma-names = "rx"; - pinctrl-0 = <&pdmm0_clk - &pdmm0_clk1 - &pdmm0_sdi0 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - pinctrl-names = "default"; - resets = <&cru SRST_M_PDM>; - reset-names = "pdm-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@fe530000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe530000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@fe550000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe550000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fe5a0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5a0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c1_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@fe5b0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5b0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@fe5c0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5c0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@fe5d0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5d0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fe5e0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5e0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@fe600000 { - compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; - reg = <0x0 0xfe600000 0x0 0x100>; - interrupts = ; - clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; - clock-names = "tclk", "pclk"; - }; - - spi0: spi@fe610000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe610000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 20>, <&dmac0 21>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@fe620000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe620000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 22>, <&dmac0 23>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@fe630000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe630000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 24>, <&dmac0 25>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@fe640000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe640000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 26>, <&dmac0 27>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@fe650000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe650000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - pinctrl-0 = <&uart1m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@fe660000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe660000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 4>, <&dmac0 5>; - pinctrl-0 = <&uart2m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@fe670000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe670000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - pinctrl-0 = <&uart3m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@fe680000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe680000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - pinctrl-0 = <&uart4m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@fe690000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe690000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - pinctrl-0 = <&uart5m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@fe6a0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - pinctrl-0 = <&uart6m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@fe6b0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - pinctrl-0 = <&uart7m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@fe6c0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - pinctrl-0 = <&uart8m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@fe6d0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6d0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 18>, <&dmac0 19>; - pinctrl-0 = <&uart9m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - thermal_zones: thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <20>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - gpu_threshold: gpu-threshold { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_target: gpu-target { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_crit: gpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_target>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@fe710000 { - compatible = "rockchip,rk3568-tsadc"; - reg = <0x0 0xfe710000 0x0 0x100>; - interrupts = ; - assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; - assigned-clock-rates = <17000000>, <700000>; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, - <&cru SRST_TSADCPHY>; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <95000>; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&tsadc_pin>; - pinctrl-1 = <&tsadc_shutorg>; - pinctrl-2 = <&tsadc_pin>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: saradc@fe720000 { - compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xfe720000 0x0 0x100>; - interrupts = ; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - pwm4: pwm@fe6e0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@fe6e0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@fe6e0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@fe6e0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@fe6f0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@fe6f0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@fe6f0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@fe6f0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@fe700000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@fe700010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@fe700020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@fe700030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - combphy1: phy@fe830000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe830000 0x0 0x100>; - clocks = <&pmucru CLK_PCIEPHY1_REF>, - <&cru PCLK_PIPEPHY1>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY1>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf1>; - #phy-cells = <1>; - status = "disabled"; - }; - - combphy2: phy@fe840000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe840000 0x0 0x100>; - clocks = <&pmucru CLK_PCIEPHY2_REF>, - <&cru PCLK_PIPEPHY2>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY2>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf2>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2phy0: usb2phy@fe8a0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8a0000 0x0 0x10000>; - clocks = <&pmucru CLK_USBPHY0_REF>; - clock-names = "phyclk"; - clock-output-names = "clk_usbphy0_480m"; - interrupts = ; - rockchip,usbgrf = <&usb2phy0_grf>; - #clock-cells = <0>; - status = "disabled"; - - usb2phy0_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - usb2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - usb2phy1: usb2phy@fe8b0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8b0000 0x0 0x10000>; - clocks = <&pmucru CLK_USBPHY1_REF>; - clock-names = "phyclk"; - clock-output-names = "clk_usbphy1_480m"; - interrupts = ; - rockchip,usbgrf = <&usb2phy1_grf>; - #clock-cells = <0>; - status = "disabled"; - - usb2phy1_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - usb2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@fdd60000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfdd60000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@fe740000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe740000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@fe750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe750000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@fe760000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe760000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@fe770000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe770000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3568-pinctrl.dtsi" diff --git a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi b/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi deleted file mode 100644 index 5c645437b..000000000 --- a/target/linux/rockchip/files-5.10/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -&pinctrl { - /omit-if-no-ref/ - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - /omit-if-no-ref/ - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - /omit-if-no-ref/ - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { - bias-disable; - drive-strength = <0>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { - bias-disable; - drive-strength = <1>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { - bias-disable; - drive-strength = <2>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { - bias-disable; - drive-strength = <3>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { - bias-disable; - drive-strength = <4>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { - bias-disable; - drive-strength = <5>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { - bias-disable; - drive-strength = <6>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { - bias-disable; - drive-strength = <7>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { - bias-disable; - drive-strength = <8>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { - bias-disable; - drive-strength = <9>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { - bias-disable; - drive-strength = <10>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { - bias-disable; - drive-strength = <11>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { - bias-disable; - drive-strength = <12>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { - bias-disable; - drive-strength = <13>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { - bias-disable; - drive-strength = <14>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { - bias-disable; - drive-strength = <15>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { - bias-pull-up; - drive-strength = <0>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { - bias-pull-up; - drive-strength = <1>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { - bias-pull-up; - drive-strength = <2>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { - bias-pull-up; - drive-strength = <3>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { - bias-pull-up; - drive-strength = <4>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { - bias-pull-up; - drive-strength = <5>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { - bias-pull-up; - drive-strength = <6>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { - bias-pull-up; - drive-strength = <7>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { - bias-pull-up; - drive-strength = <8>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { - bias-pull-up; - drive-strength = <9>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { - bias-pull-up; - drive-strength = <10>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { - bias-pull-up; - drive-strength = <11>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { - bias-pull-up; - drive-strength = <12>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { - bias-pull-up; - drive-strength = <13>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { - bias-pull-up; - drive-strength = <14>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { - bias-pull-up; - drive-strength = <15>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { - bias-pull-down; - drive-strength = <0>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { - bias-pull-down; - drive-strength = <1>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { - bias-pull-down; - drive-strength = <2>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { - bias-pull-down; - drive-strength = <3>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { - bias-pull-down; - drive-strength = <4>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { - bias-pull-down; - drive-strength = <5>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { - bias-pull-down; - drive-strength = <6>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { - bias-pull-down; - drive-strength = <7>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { - bias-pull-down; - drive-strength = <8>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { - bias-pull-down; - drive-strength = <9>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { - bias-pull-down; - drive-strength = <10>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { - bias-pull-down; - drive-strength = <11>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { - bias-pull-down; - drive-strength = <12>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { - bias-pull-down; - drive-strength = <13>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { - bias-pull-down; - drive-strength = <14>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { - bias-pull-down; - drive-strength = <15>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_smt: pcfg-pull-up-smt { - bias-pull-up; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_pull_down_smt: pcfg-pull-down-smt { - bias-pull-down; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { - bias-disable; - drive-strength = <0>; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_output_high: pcfg-output-high { - output-high; - }; - - /omit-if-no-ref/ - pcfg_output_low: pcfg-output-low { - output-low; - }; -}; diff --git a/target/linux/rockchip/files-5.10/drivers/clk/rockchip/clk-rk3568.c b/target/linux/rockchip/files-5.10/drivers/clk/rockchip/clk-rk3568.c deleted file mode 100644 index 6e5440841..000000000 --- a/target/linux/rockchip/files-5.10/drivers/clk/rockchip/clk-rk3568.c +++ /dev/null @@ -1,1725 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Author: Elaine Zhang - */ - -#include -#include -#include -#include -#include -#include -#include -#include "clk.h" - -#define RK3568_GRF_SOC_STATUS0 0x580 - -enum rk3568_pmu_plls { - ppll, hpll, -}; - -enum rk3568_plls { - apll, dpll, gpll, cpll, npll, vpll, -}; - -static struct rockchip_pll_rate_table rk3568_pll_rates[] = { - /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ - RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), - RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), - RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), - RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), - RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), - RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), - RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), - RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), - RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), - RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), - RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), - RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), - RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), - RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), - RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), - RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), - RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), - RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), - RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), - RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), - RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), - RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), - RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), - RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), - RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), - RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), - RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), - RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), - RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), - RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), - RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), - RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), - RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), - RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), - RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), - RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), - RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), - RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), - RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), - RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), - RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), - RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), - RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), - RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), - RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), - RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), - RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), - RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), - RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), - RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), - RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), - RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), - { /* sentinel */ }, -}; - -#define RK3568_DIV_ATCLK_CORE_MASK 0x1f -#define RK3568_DIV_ATCLK_CORE_SHIFT 0 -#define RK3568_DIV_GICCLK_CORE_MASK 0x1f -#define RK3568_DIV_GICCLK_CORE_SHIFT 8 -#define RK3568_DIV_PCLK_CORE_MASK 0x1f -#define RK3568_DIV_PCLK_CORE_SHIFT 0 -#define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f -#define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8 -#define RK3568_DIV_ACLK_CORE_MASK 0x1f -#define RK3568_DIV_ACLK_CORE_SHIFT 8 - -#define RK3568_DIV_SCLK_CORE_MASK 0xf -#define RK3568_DIV_SCLK_CORE_SHIFT 0 -#define RK3568_MUX_SCLK_CORE_MASK 0x3 -#define RK3568_MUX_SCLK_CORE_SHIFT 8 -#define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1 -#define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15 -#define RK3568_MUX_CLK_CORE_APLL_MASK 0x1 -#define RK3568_MUX_CLK_CORE_APLL_SHIFT 7 -#define RK3568_MUX_CLK_PVTPLL_MASK 0x1 -#define RK3568_MUX_CLK_PVTPLL_SHIFT 15 - -#define RK3568_CLKSEL1(_sclk_core) \ -{ \ - .reg = RK3568_CLKSEL_CON(2), \ - .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \ - RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \ - HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \ - RK3568_MUX_SCLK_CORE_SHIFT) | \ - HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \ - RK3568_DIV_SCLK_CORE_SHIFT), \ -} - -#define RK3568_CLKSEL2(_aclk_core) \ -{ \ - .reg = RK3568_CLKSEL_CON(5), \ - .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \ - RK3568_DIV_ACLK_CORE_SHIFT), \ -} - -#define RK3568_CLKSEL3(_atclk_core, _gic_core) \ -{ \ - .reg = RK3568_CLKSEL_CON(3), \ - .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \ - RK3568_DIV_ATCLK_CORE_SHIFT) | \ - HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \ - RK3568_DIV_GICCLK_CORE_SHIFT), \ -} - -#define RK3568_CLKSEL4(_pclk_core, _periph_core) \ -{ \ - .reg = RK3568_CLKSEL_CON(4), \ - .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \ - RK3568_DIV_PCLK_CORE_SHIFT) | \ - HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \ - RK3568_DIV_PERIPHCLK_CORE_SHIFT), \ -} - -#define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \ -{ \ - .prate = _prate##U, \ - .divs = { \ - RK3568_CLKSEL1(_sclk), \ - RK3568_CLKSEL2(_acore), \ - RK3568_CLKSEL3(_atcore, _gicclk), \ - RK3568_CLKSEL4(_pclk, _periph), \ - }, \ -} - -static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { - RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), - RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), - RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5), - RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3), - RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3), -}; - -static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = { - .core_reg[0] = RK3568_CLKSEL_CON(0), - .div_core_shift[0] = 0, - .div_core_mask[0] = 0x1f, - .core_reg[1] = RK3568_CLKSEL_CON(0), - .div_core_shift[1] = 8, - .div_core_mask[1] = 0x1f, - .core_reg[2] = RK3568_CLKSEL_CON(1), - .div_core_shift[2] = 0, - .div_core_mask[2] = 0x1f, - .core_reg[3] = RK3568_CLKSEL_CON(1), - .div_core_shift[3] = 8, - .div_core_mask[3] = 0x1f, - .num_cores = 4, - .mux_core_alt = 1, - .mux_core_main = 0, - .mux_core_shift = 6, - .mux_core_mask = 0x1, -}; - -PNAME(mux_pll_p) = { "xin24m" }; -PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; -PNAME(mux_armclk_p) = { "apll", "gpll" }; -PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "}; -PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" }; -PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; -PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; -PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; -PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; -PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; -PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; -PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; -PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; -PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; -PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; -PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; -PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; -PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" }; -PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; -PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; -PNAME(npll_gpll_p) = { "npll", "gpll" }; -PNAME(cpll_gpll_p) = { "cpll", "gpll" }; -PNAME(gpll_cpll_p) = { "gpll", "cpll" }; -PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; -PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; -PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" }; -PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" }; -PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; -PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"}; -PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; -PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; -PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; -PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" }; -PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; -PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; -PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; -PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; -PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; -PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; -PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; -PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; -PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; -PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; -PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; -PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" }; -PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" }; -PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" }; -PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" }; -PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" }; -PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; -PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" }; -PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" }; -PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" }; -PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" }; -PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" }; -PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" }; -PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; -PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; -PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" }; -PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; -PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; -PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" }; -PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" }; -PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; -PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; -PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; -PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; -PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; -PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" }; -PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; -PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" }; -PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"}; -PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" }; -PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" }; -PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" }; -PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" }; -PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" }; -PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" }; -PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" }; -PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" }; -PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; -PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; -PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; -PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" }; -PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; -PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; -PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; -PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" }; -PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" }; -PNAME(clk_pdpmu_p) = { "ppll", "gpll" }; -PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; -PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; -PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; -PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" }; - -static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = { - [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, - 0, RK3568_PMU_PLL_CON(0), - RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates), - [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, - 0, RK3568_PMU_PLL_CON(16), - RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates), -}; - -static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = { - [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, - 0, RK3568_PLL_CON(0), - RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates), - [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, - 0, RK3568_PLL_CON(8), - RK3568_MODE_CON0, 2, 1, 0, NULL), - [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, - 0, RK3568_PLL_CON(24), - RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates), - [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, - 0, RK3568_PLL_CON(16), - RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates), - [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, - 0, RK3568_PLL_CON(32), - RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates), - [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, - 0, RK3568_PLL_CON(40), - RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates), -}; - -#define MFLAGS CLK_MUX_HIWORD_MASK -#define DFLAGS CLK_DIVIDER_HIWORD_MASK -#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) - -static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata = - MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(11), 10, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata = - MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(13), 10, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata = - MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(15), 10, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata = - MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(17), 10, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata = - MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(19), 10, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata = - MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(21), 10, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata = - MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(83), 10, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata = - MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(23), 15, 1, MFLAGS); - -static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata = - MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(25), 15, 1, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata = - MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(52), 12, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata = - MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(54), 12, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata = - MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(56), 12, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata = - MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(58), 12, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata = - MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(60), 12, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata = - MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(62), 12, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata = - MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(64), 12, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata = - MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(66), 12, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata = - MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(68), 12, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata = - MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT, - RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata = - MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS); - -static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { - /* - * Clock-Architecture Diagram 1 - */ - /* SRC_CLK */ - COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(75), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 0, GFLAGS), - COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(75), 8, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 1, GFLAGS), - COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(76), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 2, GFLAGS), - COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(76), 8, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 3, GFLAGS), - COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(77), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 4, GFLAGS), - COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(77), 8, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 5, GFLAGS), - COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(78), 0, 6, DFLAGS, - RK3568_CLKGATE_CON(35), 6, GFLAGS), - COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(78), 8, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 7, GFLAGS), - COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(79), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 8, GFLAGS), - COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(79), 8, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 9, GFLAGS), - COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 10, GFLAGS), - COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 11, GFLAGS), - COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 12, GFLAGS), - COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 13, GFLAGS), - COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, - RK3568_CLKGATE_CON(35), 14, GFLAGS), - COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(82), 8, 6, DFLAGS, - RK3568_CLKGATE_CON(35), 15, GFLAGS), - FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2), - FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), - MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, - RK3568_MODE_CON0, 14, 2, MFLAGS), - - /* PD_CORE */ - COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK3568_CLKGATE_CON(0), 5, GFLAGS), - COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(2), 15, 1, MFLAGS, - RK3568_CLKGATE_CON(0), 7, GFLAGS), - - COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK3568_CLKGATE_CON(0), 8, GFLAGS), - COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK3568_CLKGATE_CON(0), 9, GFLAGS), - COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK3568_CLKGATE_CON(0), 10, GFLAGS), - COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK3568_CLKGATE_CON(0), 11, GFLAGS), - COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK3568_CLKGATE_CON(0), 14, GFLAGS), - COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK3568_CLKGATE_CON(0), 15, GFLAGS), - COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK3568_CLKGATE_CON(1), 0, GFLAGS), - - COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(5), 14, 2, MFLAGS, - RK3568_CLKGATE_CON(1), 2, GFLAGS), - - GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0, - RK3568_CLKGATE_CON(1), 10, GFLAGS), - GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0, - RK3568_CLKGATE_CON(1), 11, GFLAGS), - GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(1), 12, GFLAGS), - GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0, - RK3568_CLKGATE_CON(1), 9, GFLAGS), - - /* PD_GPU */ - COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK3568_CLKGATE_CON(2), 0, GFLAGS), - MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY), - DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0, - RK3568_CLKSEL_CON(6), 8, 2, DFLAGS), - DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0, - RK3568_CLKSEL_CON(6), 12, 4, DFLAGS), - GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0, - RK3568_CLKGATE_CON(2), 3, GFLAGS), - - GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0, - RK3568_CLKGATE_CON(2), 6, GFLAGS), - GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, - RK3568_CLKGATE_CON(2), 7, GFLAGS), - GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0, - RK3568_CLKGATE_CON(2), 8, GFLAGS), - GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(2), 9, GFLAGS), - - /* PD_NPU */ - COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0, - RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS, - RK3568_CLKGATE_CON(3), 0, GFLAGS), - MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, - RK3568_CLKSEL_CON(7), 8, 1, MFLAGS), - MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(7), 15, 1, MFLAGS), - COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0, - RK3568_CLKSEL_CON(8), 0, 4, DFLAGS, - RK3568_CLKGATE_CON(3), 2, GFLAGS), - COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0, - RK3568_CLKSEL_CON(8), 4, 4, DFLAGS, - RK3568_CLKGATE_CON(3), 3, GFLAGS), - GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0, - RK3568_CLKGATE_CON(3), 4, GFLAGS), - GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0, - RK3568_CLKGATE_CON(3), 7, GFLAGS), - GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0, - RK3568_CLKGATE_CON(3), 8, GFLAGS), - - GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0, - RK3568_CLKGATE_CON(3), 9, GFLAGS), - GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, - RK3568_CLKGATE_CON(3), 10, GFLAGS), - GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0, - RK3568_CLKGATE_CON(3), 11, GFLAGS), - GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(3), 12, GFLAGS), - - /* PD_DDR */ - COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(4), 0, GFLAGS), - MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(9), 15, 1, MFLAGS), - - COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(10), 0, 2, DFLAGS, - RK3568_CLKGATE_CON(4), 2, GFLAGS), - GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(4), 15, GFLAGS), - - /* PD_GIC_AUDIO */ - COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(10), 8, 2, MFLAGS, - RK3568_CLKGATE_CON(5), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(10), 10, 2, MFLAGS, - RK3568_CLKGATE_CON(5), 1, GFLAGS), - GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(5), 8, GFLAGS), - COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0, - RK3568_CLKSEL_CON(10), 12, 2, MFLAGS, - RK3568_CLKGATE_CON(5), 9, GFLAGS), - GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(5), 4, GFLAGS), - GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(5), 7, GFLAGS), - GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(5), 10, GFLAGS), - GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(5), 11, GFLAGS), - GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(5), 12, GFLAGS), - GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(5), 13, GFLAGS), - - COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(6), 0, GFLAGS), - COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(12), 0, - RK3568_CLKGATE_CON(6), 1, GFLAGS, - &rk3568_i2s0_8ch_tx_fracmux), - GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, - RK3568_CLKGATE_CON(6), 2, GFLAGS), - COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(11), 15, 1, MFLAGS, - RK3568_CLKGATE_CON(6), 3, GFLAGS), - - COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(6), 4, GFLAGS), - COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(14), 0, - RK3568_CLKGATE_CON(6), 5, GFLAGS, - &rk3568_i2s0_8ch_rx_fracmux), - GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, - RK3568_CLKGATE_CON(6), 6, GFLAGS), - COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(13), 15, 1, MFLAGS, - RK3568_CLKGATE_CON(6), 7, GFLAGS), - - COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(6), 8, GFLAGS), - COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(16), 0, - RK3568_CLKGATE_CON(6), 9, GFLAGS, - &rk3568_i2s1_8ch_tx_fracmux), - GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, - RK3568_CLKGATE_CON(6), 10, GFLAGS), - COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(15), 15, 1, MFLAGS, - RK3568_CLKGATE_CON(6), 11, GFLAGS), - - COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(6), 12, GFLAGS), - COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(18), 0, - RK3568_CLKGATE_CON(6), 13, GFLAGS, - &rk3568_i2s1_8ch_rx_fracmux), - GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, - RK3568_CLKGATE_CON(6), 14, GFLAGS), - COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(17), 15, 1, MFLAGS, - RK3568_CLKGATE_CON(6), 15, GFLAGS), - - COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(7), 0, GFLAGS), - COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(20), 0, - RK3568_CLKGATE_CON(7), 1, GFLAGS, - &rk3568_i2s2_2ch_fracmux), - GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, - RK3568_CLKGATE_CON(7), 2, GFLAGS), - COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(19), 15, 1, MFLAGS, - RK3568_CLKGATE_CON(7), 3, GFLAGS), - - COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(7), 4, GFLAGS), - COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(22), 0, - RK3568_CLKGATE_CON(7), 5, GFLAGS, - &rk3568_i2s3_2ch_tx_fracmux), - GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0, - RK3568_CLKGATE_CON(7), 6, GFLAGS), - COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(21), 15, 1, MFLAGS, - RK3568_CLKGATE_CON(7), 7, GFLAGS), - - COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(7), 8, GFLAGS), - COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(84), 0, - RK3568_CLKGATE_CON(7), 9, GFLAGS, - &rk3568_i2s3_2ch_rx_fracmux), - GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0, - RK3568_CLKGATE_CON(7), 10, GFLAGS), - COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(83), 15, 1, MFLAGS, - RK3568_CLKGATE_CON(7), 11, GFLAGS), - - GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(5), 14, GFLAGS), - COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, - RK3568_CLKSEL_CON(23), 8, 2, MFLAGS, - RK3568_CLKGATE_CON(5), 15, GFLAGS), - GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(7), 12, GFLAGS), - GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(7), 13, GFLAGS), - - COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0, - RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(7), 14, GFLAGS), - COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(24), 0, - RK3568_CLKGATE_CON(7), 15, GFLAGS, - &rk3568_spdif_8ch_fracmux), - - GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(8), 0, GFLAGS), - COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0, - RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS, - RK3568_CLKGATE_CON(8), 1, GFLAGS), - COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(26), 0, - RK3568_CLKGATE_CON(8), 2, GFLAGS, - &rk3568_audpwm_fracmux), - - GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0, - RK3568_CLKGATE_CON(8), 3, GFLAGS), - COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0, - RK3568_CLKSEL_CON(23), 10, 2, MFLAGS, - RK3568_CLKGATE_CON(8), 4, GFLAGS), - GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0, - RK3568_CLKGATE_CON(8), 5, GFLAGS), - GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0, - RK3568_CLKGATE_CON(8), 6, GFLAGS), - - /* PD_SECURE_FLASH */ - COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0, - RK3568_CLKSEL_CON(27), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(8), 7, GFLAGS), - COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0, - RK3568_CLKSEL_CON(27), 2, 2, MFLAGS, - RK3568_CLKGATE_CON(8), 8, GFLAGS), - GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0, - RK3568_CLKGATE_CON(8), 11, GFLAGS), - GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0, - RK3568_CLKGATE_CON(8), 12, GFLAGS), - COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0, - RK3568_CLKSEL_CON(27), 4, 2, MFLAGS, - RK3568_CLKGATE_CON(8), 13, GFLAGS), - COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0, - RK3568_CLKSEL_CON(27), 6, 2, MFLAGS, - RK3568_CLKGATE_CON(8), 14, GFLAGS), - GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0, - RK3568_CLKGATE_CON(8), 15, GFLAGS), - GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(9), 10, GFLAGS), - GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(9), 11, GFLAGS), - GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0, - RK3568_CLKGATE_CON(26), 9, GFLAGS), - GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0, - RK3568_CLKGATE_CON(26), 10, GFLAGS), - GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0, - RK3568_CLKGATE_CON(26), 11, GFLAGS), - GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0, - RK3568_CLKGATE_CON(9), 0, GFLAGS), - COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0, - RK3568_CLKSEL_CON(28), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(9), 1, GFLAGS), - GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0, - RK3568_CLKGATE_CON(9), 2, GFLAGS), - GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0, - RK3568_CLKGATE_CON(9), 3, GFLAGS), - COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0, - RK3568_CLKSEL_CON(28), 4, 3, MFLAGS, - RK3568_CLKGATE_CON(9), 4, GFLAGS), - GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0, - RK3568_CLKGATE_CON(9), 5, GFLAGS), - GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0, - RK3568_CLKGATE_CON(9), 6, GFLAGS), - COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0, - RK3568_CLKSEL_CON(28), 8, 2, MFLAGS, - RK3568_CLKGATE_CON(9), 7, GFLAGS), - COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0, - RK3568_CLKSEL_CON(28), 12, 3, MFLAGS, - RK3568_CLKGATE_CON(9), 8, GFLAGS), - GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, - RK3568_CLKGATE_CON(9), 9, GFLAGS), - MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1), - MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1), - - /* PD_PIPE */ - COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0, - RK3568_CLKSEL_CON(29), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(10), 0, GFLAGS), - COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0, - RK3568_CLKSEL_CON(29), 4, 4, DFLAGS, - RK3568_CLKGATE_CON(10), 1, GFLAGS), - GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0, - RK3568_CLKGATE_CON(12), 0, GFLAGS), - GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0, - RK3568_CLKGATE_CON(12), 1, GFLAGS), - GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0, - RK3568_CLKGATE_CON(12), 2, GFLAGS), - GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0, - RK3568_CLKGATE_CON(12), 3, GFLAGS), - GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0, - RK3568_CLKGATE_CON(12), 4, GFLAGS), - GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0, - RK3568_CLKGATE_CON(12), 8, GFLAGS), - GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0, - RK3568_CLKGATE_CON(12), 9, GFLAGS), - GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0, - RK3568_CLKGATE_CON(12), 10, GFLAGS), - GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0, - RK3568_CLKGATE_CON(12), 11, GFLAGS), - GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0, - RK3568_CLKGATE_CON(12), 12, GFLAGS), - GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0, - RK3568_CLKGATE_CON(13), 0, GFLAGS), - GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0, - RK3568_CLKGATE_CON(13), 1, GFLAGS), - GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0, - RK3568_CLKGATE_CON(13), 2, GFLAGS), - GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0, - RK3568_CLKGATE_CON(13), 3, GFLAGS), - GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0, - RK3568_CLKGATE_CON(13), 4, GFLAGS), - GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0, - RK3568_CLKGATE_CON(11), 0, GFLAGS), - GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0, - RK3568_CLKGATE_CON(11), 1, GFLAGS), - GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0, - RK3568_CLKGATE_CON(11), 2, GFLAGS), - GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0, - RK3568_CLKGATE_CON(11), 4, GFLAGS), - GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0, - RK3568_CLKGATE_CON(11), 5, GFLAGS), - GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0, - RK3568_CLKGATE_CON(11), 6, GFLAGS), - GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0, - RK3568_CLKGATE_CON(11), 8, GFLAGS), - GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0, - RK3568_CLKGATE_CON(11), 9, GFLAGS), - GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0, - RK3568_CLKGATE_CON(11), 10, GFLAGS), - GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0, - RK3568_CLKGATE_CON(10), 8, GFLAGS), - GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, - RK3568_CLKGATE_CON(10), 9, GFLAGS), - COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0, - RK3568_CLKSEL_CON(29), 8, 1, MFLAGS, - RK3568_CLKGATE_CON(10), 10, GFLAGS), - GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0, - RK3568_CLKGATE_CON(10), 12, GFLAGS), - GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, - RK3568_CLKGATE_CON(10), 13, GFLAGS), - COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0, - RK3568_CLKSEL_CON(29), 9, 1, MFLAGS, - RK3568_CLKGATE_CON(10), 14, GFLAGS), - COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0, - RK3568_CLKSEL_CON(29), 13, 1, MFLAGS, - RK3568_CLKGATE_CON(10), 4, GFLAGS), - GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0, - RK3568_CLKGATE_CON(13), 6, GFLAGS), - - /* PD_PHP */ - COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0, - RK3568_CLKSEL_CON(30), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(14), 8, GFLAGS), - COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0, - RK3568_CLKSEL_CON(30), 2, 2, MFLAGS, - RK3568_CLKGATE_CON(14), 9, GFLAGS), - COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, - RK3568_CLKSEL_CON(30), 4, 4, DFLAGS, - RK3568_CLKGATE_CON(14), 10, GFLAGS), - GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0, - RK3568_CLKGATE_CON(15), 0, GFLAGS), - COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0, - RK3568_CLKSEL_CON(30), 8, 3, MFLAGS, - RK3568_CLKGATE_CON(15), 1, GFLAGS), - MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1), - MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1), - - GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0, - RK3568_CLKGATE_CON(15), 2, GFLAGS), - COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0, - RK3568_CLKSEL_CON(30), 12, 3, MFLAGS, - RK3568_CLKGATE_CON(15), 3, GFLAGS), - MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1), - MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1), - - GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0, - RK3568_CLKGATE_CON(15), 5, GFLAGS), - GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0, - RK3568_CLKGATE_CON(15), 6, GFLAGS), - COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0, - RK3568_CLKSEL_CON(31), 8, 2, MFLAGS, - RK3568_CLKGATE_CON(15), 7, GFLAGS), - COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0, - RK3568_CLKSEL_CON(31), 14, 2, MFLAGS, - RK3568_CLKGATE_CON(15), 8, GFLAGS), - GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0, - RK3568_CLKGATE_CON(15), 12, GFLAGS), - COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0, - RK3568_CLKSEL_CON(31), 12, 2, MFLAGS, - RK3568_CLKGATE_CON(15), 4, GFLAGS), - MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(31), 2, 1, MFLAGS), - FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5), - FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50), - FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2), - FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20), - MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0, - RK3568_CLKSEL_CON(31), 4, 2, MFLAGS), - MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0, - RK3568_CLKSEL_CON(31), 3, 1, MFLAGS), - MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(31), 0, 2, MFLAGS), - - /* PD_USB */ - COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0, - RK3568_CLKSEL_CON(32), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(16), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0, - RK3568_CLKSEL_CON(32), 2, 2, MFLAGS, - RK3568_CLKGATE_CON(16), 1, GFLAGS), - COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0, - RK3568_CLKSEL_CON(32), 4, 4, DFLAGS, - RK3568_CLKGATE_CON(16), 2, GFLAGS), - GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0, - RK3568_CLKGATE_CON(16), 12, GFLAGS), - GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0, - RK3568_CLKGATE_CON(16), 13, GFLAGS), - GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0, - RK3568_CLKGATE_CON(16), 14, GFLAGS), - GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0, - RK3568_CLKGATE_CON(16), 15, GFLAGS), - GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0, - RK3568_CLKGATE_CON(17), 0, GFLAGS), - COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0, - RK3568_CLKSEL_CON(32), 8, 3, MFLAGS, - RK3568_CLKGATE_CON(17), 1, GFLAGS), - MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1), - MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1), - - GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0, - RK3568_CLKGATE_CON(17), 3, GFLAGS), - GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0, - RK3568_CLKGATE_CON(17), 4, GFLAGS), - COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0, - RK3568_CLKSEL_CON(33), 8, 2, MFLAGS, - RK3568_CLKGATE_CON(17), 5, GFLAGS), - COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0, - RK3568_CLKSEL_CON(33), 14, 2, MFLAGS, - RK3568_CLKGATE_CON(17), 6, GFLAGS), - GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0, - RK3568_CLKGATE_CON(17), 10, GFLAGS), - COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0, - RK3568_CLKSEL_CON(33), 12, 2, MFLAGS, - RK3568_CLKGATE_CON(17), 2, GFLAGS), - MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(33), 2, 1, MFLAGS), - FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5), - FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50), - FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2), - FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20), - MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0, - RK3568_CLKSEL_CON(33), 4, 2, MFLAGS), - MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0, - RK3568_CLKSEL_CON(33), 3, 1, MFLAGS), - MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(33), 0, 2, MFLAGS), - - /* PD_PERI */ - COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(10), 4, 2, MFLAGS, - RK3568_CLKGATE_CON(14), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(10), 6, 2, MFLAGS, - RK3568_CLKGATE_CON(14), 1, GFLAGS), - - /* PD_VI */ - COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0, - RK3568_CLKSEL_CON(34), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(18), 0, GFLAGS), - COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0, - RK3568_CLKSEL_CON(34), 4, 4, DFLAGS, - RK3568_CLKGATE_CON(18), 1, GFLAGS), - COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0, - RK3568_CLKSEL_CON(34), 8, 4, DFLAGS, - RK3568_CLKGATE_CON(18), 2, GFLAGS), - GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0, - RK3568_CLKGATE_CON(18), 9, GFLAGS), - GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, - RK3568_CLKGATE_CON(18), 10, GFLAGS), - COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0, - RK3568_CLKSEL_CON(34), 14, 2, MFLAGS, - RK3568_CLKGATE_CON(18), 11, GFLAGS), - GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0, - RK3568_CLKGATE_CON(18), 13, GFLAGS), - GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0, - RK3568_CLKGATE_CON(19), 0, GFLAGS), - GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, - RK3568_CLKGATE_CON(19), 1, GFLAGS), - COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0, - RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(19), 2, GFLAGS), - GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0, - RK3568_CLKGATE_CON(19), 4, GFLAGS), - COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0, - RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS, - RK3568_CLKGATE_CON(19), 8, GFLAGS), - COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0, - RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS, - RK3568_CLKGATE_CON(19), 9, GFLAGS), - COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0, - RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS, - RK3568_CLKGATE_CON(19), 10, GFLAGS), - - /* PD_VO */ - COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0, - RK3568_CLKSEL_CON(37), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(20), 0, GFLAGS), - COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0, - RK3568_CLKSEL_CON(37), 8, 4, DFLAGS, - RK3568_CLKGATE_CON(20), 1, GFLAGS), - COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0, - RK3568_CLKSEL_CON(37), 12, 4, DFLAGS, - RK3568_CLKGATE_CON(20), 2, GFLAGS), - COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0, - RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(20), 6, GFLAGS), - GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, - RK3568_CLKGATE_CON(20), 8, GFLAGS), - GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, - RK3568_CLKGATE_CON(20), 9, GFLAGS), - COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 10, GFLAGS), - COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 11, GFLAGS), - COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 12, GFLAGS), - GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, - RK3568_CLKGATE_CON(20), 13, GFLAGS), - GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0, - RK3568_CLKGATE_CON(21), 0, GFLAGS), - GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0, - RK3568_CLKGATE_CON(21), 1, GFLAGS), - GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0, - RK3568_CLKGATE_CON(21), 2, GFLAGS), - GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0, - RK3568_CLKGATE_CON(21), 3, GFLAGS), - GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, - RK3568_CLKGATE_CON(21), 4, GFLAGS), - GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0, - RK3568_CLKGATE_CON(21), 5, GFLAGS), - GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0, - RK3568_CLKGATE_CON(21), 6, GFLAGS), - GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0, - RK3568_CLKGATE_CON(21), 7, GFLAGS), - GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0, - RK3568_CLKGATE_CON(21), 8, GFLAGS), - COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0, - RK3568_CLKSEL_CON(38), 8, 2, MFLAGS, - RK3568_CLKGATE_CON(21), 9, GFLAGS), - - /* PD_VPU */ - COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0, - RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(22), 0, GFLAGS), - COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, - RK3568_CLKSEL_CON(42), 8, 4, DFLAGS, - RK3568_CLKGATE_CON(22), 1, GFLAGS), - GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, - RK3568_CLKGATE_CON(22), 4, GFLAGS), - GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, - RK3568_CLKGATE_CON(22), 5, GFLAGS), - - /* PD_RGA */ - COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0, - RK3568_CLKSEL_CON(43), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(23), 0, GFLAGS), - COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0, - RK3568_CLKSEL_CON(43), 8, 4, DFLAGS, - RK3568_CLKGATE_CON(23), 1, GFLAGS), - COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0, - RK3568_CLKSEL_CON(43), 12, 4, DFLAGS, - RK3568_CLKGATE_CON(22), 12, GFLAGS), - GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, - RK3568_CLKGATE_CON(23), 4, GFLAGS), - GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, - RK3568_CLKGATE_CON(23), 5, GFLAGS), - COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0, - RK3568_CLKSEL_CON(43), 2, 2, MFLAGS, - RK3568_CLKGATE_CON(23), 6, GFLAGS), - GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0, - RK3568_CLKGATE_CON(23), 7, GFLAGS), - GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0, - RK3568_CLKGATE_CON(23), 8, GFLAGS), - COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0, - RK3568_CLKSEL_CON(43), 4, 2, MFLAGS, - RK3568_CLKGATE_CON(23), 9, GFLAGS), - GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS), - COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0, - RK3568_CLKSEL_CON(43), 6, 2, MFLAGS, - RK3568_CLKGATE_CON(23), 11, GFLAGS), - GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0, - RK3568_CLKGATE_CON(23), 12, GFLAGS), - GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, - RK3568_CLKGATE_CON(23), 13, GFLAGS), - GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0, - RK3568_CLKGATE_CON(23), 14, GFLAGS), - GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0, - RK3568_CLKGATE_CON(23), 15, GFLAGS), - GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0, - RK3568_CLKGATE_CON(22), 14, GFLAGS), - GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0, - RK3568_CLKGATE_CON(22), 15, GFLAGS), - - /* PD_RKVENC */ - COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0, - RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(24), 0, GFLAGS), - COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, - RK3568_CLKSEL_CON(44), 8, 4, DFLAGS, - RK3568_CLKGATE_CON(24), 1, GFLAGS), - GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, - RK3568_CLKGATE_CON(24), 6, GFLAGS), - GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, - RK3568_CLKGATE_CON(24), 7, GFLAGS), - COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0, - RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(24), 8, GFLAGS), - COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(25), 0, GFLAGS), - COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, - RK3568_CLKSEL_CON(47), 8, 4, DFLAGS, - RK3568_CLKGATE_CON(25), 1, GFLAGS), - GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, - RK3568_CLKGATE_CON(25), 4, GFLAGS), - GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, - RK3568_CLKGATE_CON(25), 5, GFLAGS), - COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0, - RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(25), 6, GFLAGS), - COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT, - RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK3568_CLKGATE_CON(25), 7, GFLAGS), - COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0, - RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(25), 8, GFLAGS), - - /* PD_BUS */ - COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0, - RK3568_CLKSEL_CON(50), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(26), 0, GFLAGS), - COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0, - RK3568_CLKSEL_CON(50), 4, 2, MFLAGS, - RK3568_CLKGATE_CON(26), 1, GFLAGS), - GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, - RK3568_CLKGATE_CON(26), 4, GFLAGS), - COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0, - RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS, - RK3568_CLKGATE_CON(26), 5, GFLAGS), - COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0, - RK3568_CLKSEL_CON(51), 8, 7, DFLAGS, - RK3568_CLKGATE_CON(26), 6, GFLAGS), - GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, - RK3568_CLKGATE_CON(26), 7, GFLAGS), - GATE(CLK_SARADC, "clk_saradc", "xin24m", 0, - RK3568_CLKGATE_CON(26), 8, GFLAGS), - GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(26), 12, GFLAGS), - GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0, - RK3568_CLKGATE_CON(26), 13, GFLAGS), - GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, - RK3568_CLKGATE_CON(26), 14, GFLAGS), - GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(32), 13, GFLAGS), - GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED, - RK3568_CLKGATE_CON(32), 14, GFLAGS), - GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, - RK3568_CLKGATE_CON(32), 15, GFLAGS), - - GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, - RK3568_CLKGATE_CON(27), 12, GFLAGS), - COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0, - RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(27), 13, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(53), 0, - RK3568_CLKGATE_CON(27), 14, GFLAGS, - &rk3568_uart1_fracmux), - GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0, - RK3568_CLKGATE_CON(27), 15, GFLAGS), - - GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, - RK3568_CLKGATE_CON(28), 0, GFLAGS), - COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0, - RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(28), 1, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(55), 0, - RK3568_CLKGATE_CON(28), 2, GFLAGS, - &rk3568_uart2_fracmux), - GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0, - RK3568_CLKGATE_CON(28), 3, GFLAGS), - - GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, - RK3568_CLKGATE_CON(28), 4, GFLAGS), - COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0, - RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(28), 5, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(57), 0, - RK3568_CLKGATE_CON(28), 6, GFLAGS, - &rk3568_uart3_fracmux), - GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0, - RK3568_CLKGATE_CON(28), 7, GFLAGS), - - GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, - RK3568_CLKGATE_CON(28), 8, GFLAGS), - COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0, - RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(28), 9, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(59), 0, - RK3568_CLKGATE_CON(28), 10, GFLAGS, - &rk3568_uart4_fracmux), - GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0, - RK3568_CLKGATE_CON(28), 11, GFLAGS), - - GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0, - RK3568_CLKGATE_CON(28), 12, GFLAGS), - COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0, - RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(28), 13, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(61), 0, - RK3568_CLKGATE_CON(28), 14, GFLAGS, - &rk3568_uart5_fracmux), - GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0, - RK3568_CLKGATE_CON(28), 15, GFLAGS), - - GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0, - RK3568_CLKGATE_CON(29), 0, GFLAGS), - COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0, - RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(29), 1, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(63), 0, - RK3568_CLKGATE_CON(29), 2, GFLAGS, - &rk3568_uart6_fracmux), - GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0, - RK3568_CLKGATE_CON(29), 3, GFLAGS), - - GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0, - RK3568_CLKGATE_CON(29), 4, GFLAGS), - COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0, - RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(29), 5, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(65), 0, - RK3568_CLKGATE_CON(29), 6, GFLAGS, - &rk3568_uart7_fracmux), - GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0, - RK3568_CLKGATE_CON(29), 7, GFLAGS), - - GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0, - RK3568_CLKGATE_CON(29), 8, GFLAGS), - COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0, - RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(29), 9, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(67), 0, - RK3568_CLKGATE_CON(29), 10, GFLAGS, - &rk3568_uart8_fracmux), - GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0, - RK3568_CLKGATE_CON(29), 11, GFLAGS), - - GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0, - RK3568_CLKGATE_CON(29), 12, GFLAGS), - COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0, - RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_CLKGATE_CON(29), 13, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, - RK3568_CLKSEL_CON(69), 0, - RK3568_CLKGATE_CON(29), 14, GFLAGS, - &rk3568_uart9_fracmux), - GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0, - RK3568_CLKGATE_CON(29), 15, GFLAGS), - - GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0, - RK3568_CLKGATE_CON(27), 5, GFLAGS), - COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, - RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(27), 6, GFLAGS), - GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0, - RK3568_CLKGATE_CON(27), 7, GFLAGS), - COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, - RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS, - RK3568_CLKGATE_CON(27), 8, GFLAGS), - GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0, - RK3568_CLKGATE_CON(27), 9, GFLAGS), - COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, - RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3568_CLKGATE_CON(27), 10, GFLAGS), - COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0, - RK3568_CLKSEL_CON(71), 8, 2, MFLAGS, - RK3568_CLKGATE_CON(32), 10, GFLAGS), - GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, - RK3568_CLKGATE_CON(30), 0, GFLAGS), - GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, - RK3568_CLKGATE_CON(30), 1, GFLAGS), - GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, - RK3568_CLKGATE_CON(30), 2, GFLAGS), - GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, - RK3568_CLKGATE_CON(30), 3, GFLAGS), - GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, - RK3568_CLKGATE_CON(30), 4, GFLAGS), - GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, - RK3568_CLKGATE_CON(30), 5, GFLAGS), - GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, - RK3568_CLKGATE_CON(30), 6, GFLAGS), - GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, - RK3568_CLKGATE_CON(30), 7, GFLAGS), - GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, - RK3568_CLKGATE_CON(30), 8, GFLAGS), - GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, - RK3568_CLKGATE_CON(30), 9, GFLAGS), - GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, - RK3568_CLKGATE_CON(30), 10, GFLAGS), - COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 0, 1, MFLAGS, - RK3568_CLKGATE_CON(30), 11, GFLAGS), - GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, - RK3568_CLKGATE_CON(30), 12, GFLAGS), - COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 2, 1, MFLAGS, - RK3568_CLKGATE_CON(30), 13, GFLAGS), - GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, - RK3568_CLKGATE_CON(30), 14, GFLAGS), - COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 4, 1, MFLAGS, - RK3568_CLKGATE_CON(30), 15, GFLAGS), - GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0, - RK3568_CLKGATE_CON(31), 0, GFLAGS), - COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS), - GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS), - COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 8, 1, MFLAGS, - RK3568_CLKGATE_CON(31), 11, GFLAGS), - GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, - RK3568_CLKGATE_CON(31), 12, GFLAGS), - GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, - RK3568_CLKGATE_CON(31), 13, GFLAGS), - COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 10, 1, MFLAGS, - RK3568_CLKGATE_CON(31), 14, GFLAGS), - GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, - RK3568_CLKGATE_CON(31), 15, GFLAGS), - GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, - RK3568_CLKGATE_CON(32), 0, GFLAGS), - COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(72), 12, 1, MFLAGS, - RK3568_CLKGATE_CON(32), 1, GFLAGS), - GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, - RK3568_CLKGATE_CON(32), 2, GFLAGS), - COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0, - RK3568_CLKSEL_CON(72), 14, 1, MFLAGS, - RK3568_CLKGATE_CON(32), 11, GFLAGS), - GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, - RK3568_CLKGATE_CON(31), 2, GFLAGS), - GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0, - RK3568_CLKGATE_CON(31), 3, GFLAGS), - GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, - RK3568_CLKGATE_CON(31), 4, GFLAGS), - GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0, - RK3568_CLKGATE_CON(31), 5, GFLAGS), - GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, - RK3568_CLKGATE_CON(31), 6, GFLAGS), - GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0, - RK3568_CLKGATE_CON(31), 7, GFLAGS), - GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, - RK3568_CLKGATE_CON(31), 8, GFLAGS), - GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0, - RK3568_CLKGATE_CON(31), 9, GFLAGS), - GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, - RK3568_CLKGATE_CON(32), 3, GFLAGS), - GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, - RK3568_CLKGATE_CON(32), 4, GFLAGS), - GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, - RK3568_CLKGATE_CON(32), 5, GFLAGS), - GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, - RK3568_CLKGATE_CON(32), 6, GFLAGS), - GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, - RK3568_CLKGATE_CON(32), 7, GFLAGS), - GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, - RK3568_CLKGATE_CON(32), 8, GFLAGS), - GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, - RK3568_CLKGATE_CON(32), 9, GFLAGS), - - /* PD_TOP */ - COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0, - RK3568_CLKSEL_CON(73), 0, 2, MFLAGS, - RK3568_CLKGATE_CON(33), 0, GFLAGS), - COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0, - RK3568_CLKSEL_CON(73), 4, 2, MFLAGS, - RK3568_CLKGATE_CON(33), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0, - RK3568_CLKSEL_CON(73), 8, 2, MFLAGS, - RK3568_CLKGATE_CON(33), 2, GFLAGS), - COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0, - RK3568_CLKSEL_CON(73), 12, 2, MFLAGS, - RK3568_CLKGATE_CON(33), 3, GFLAGS), - GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0, - RK3568_CLKGATE_CON(33), 8, GFLAGS), - COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0, - RK3568_CLKSEL_CON(73), 15, 1, MFLAGS, - RK3568_CLKGATE_CON(33), 9, GFLAGS), - GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0, - RK3568_CLKGATE_CON(33), 13, GFLAGS), - GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0, - RK3568_CLKGATE_CON(33), 14, GFLAGS), - GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0, - RK3568_CLKGATE_CON(33), 15, GFLAGS), - GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0, - RK3568_CLKGATE_CON(34), 4, GFLAGS), - GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0, - RK3568_CLKGATE_CON(34), 5, GFLAGS), - GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0, - RK3568_CLKGATE_CON(34), 6, GFLAGS), - GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0, - RK3568_CLKGATE_CON(34), 11, GFLAGS), - GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0, - RK3568_CLKGATE_CON(34), 12, GFLAGS), - GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0, - RK3568_CLKGATE_CON(34), 13, GFLAGS), - GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0, - RK3568_CLKGATE_CON(34), 14, GFLAGS), -}; - -static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { - /* PD_PMU */ - FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2), - FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2), - FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2), - - MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, - RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS), - COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0, - RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS, - RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS), - GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, - RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS), - GATE(CLK_PMU, "clk_pmu", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS), - GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0, - RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS), - COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0, - RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, - RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS), - GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0, - RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS), - - COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, - RK3568_PMU_CLKSEL_CON(1), 0, - RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS, - &rk3568_rtc32k_pmu_fracmux), - - COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED, - RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, - RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS), - - COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0, - RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS), - COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT, - RK3568_PMU_CLKSEL_CON(5), 0, - RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS, - &rk3568_uart0_fracmux), - GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0, - RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS), - - GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0, - RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS), - COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0, - RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, - RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS), - GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0, - RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS), - COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0, - RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS, - RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS), - GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS), - GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0, - RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS), - GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS), - GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS), - COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0, - RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS, - RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS), - GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS), - MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, - RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS), - GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS), - MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, - RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS), - GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS), - MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, - RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS), - GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS), - MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, - RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS), - COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0, - RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS, - RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS), - GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS), - MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, - RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS), - COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, - RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS, - RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS), - GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS), - MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT, - RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS), - COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0, - RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS, - RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS), - GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS), - MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT, - RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS), - COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0, - RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS, - RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS), - GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS), - MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT, - RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS), - GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0, - RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS), - GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0, - RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), - GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), - MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, - RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), -}; - -static const char *const rk3568_cru_critical_clocks[] __initconst = { - "armclk", - "pclk_core_pre", - "aclk_bus", - "pclk_bus", - "aclk_top_high", - "aclk_top_low", - "hclk_top", - "pclk_top", - "aclk_perimid", - "hclk_perimid", - "aclk_secure_flash", - "hclk_secure_flash", - "aclk_core_niu2bus", - "npll", - "clk_optc_arb", - "hclk_php", - "pclk_php", - "hclk_usb", -}; - -static const char *const rk3568_pmucru_critical_clocks[] __initconst = { - "pclk_pdpmu", - "pclk_pmu", - "clk_pmu", -}; - -static void __init rk3568_pmu_clk_init(struct device_node *np) -{ - struct rockchip_clk_provider *ctx; - void __iomem *reg_base; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: could not map cru pmu region\n", __func__); - return; - } - - ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); - if (IS_ERR(ctx)) { - pr_err("%s: rockchip pmu clk init failed\n", __func__); - return; - } - - rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks, - ARRAY_SIZE(rk3568_pmu_pll_clks), - RK3568_GRF_SOC_STATUS0); - - rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches, - ARRAY_SIZE(rk3568_clk_pmu_branches)); - - rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0), - ROCKCHIP_SOFTRST_HIWORD_MASK); - - rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks, - ARRAY_SIZE(rk3568_pmucru_critical_clocks)); - - rockchip_clk_of_add_provider(np, ctx); -} - -CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init); - -static void __init rk3568_clk_init(struct device_node *np) -{ - struct rockchip_clk_provider *ctx; - void __iomem *reg_base; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: could not map cru region\n", __func__); - return; - } - - ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); - if (IS_ERR(ctx)) { - pr_err("%s: rockchip clk init failed\n", __func__); - iounmap(reg_base); - return; - } - - rockchip_clk_register_plls(ctx, rk3568_pll_clks, - ARRAY_SIZE(rk3568_pll_clks), - RK3568_GRF_SOC_STATUS0); - - rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), - &rk3568_cpuclk_data, rk3568_cpuclk_rates, - ARRAY_SIZE(rk3568_cpuclk_rates)); - - rockchip_clk_register_branches(ctx, rk3568_clk_branches, - ARRAY_SIZE(rk3568_clk_branches)); - - rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0), - ROCKCHIP_SOFTRST_HIWORD_MASK); - - rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL); - - rockchip_clk_protect_critical(rk3568_cru_critical_clocks, - ARRAY_SIZE(rk3568_cru_critical_clocks)); - - rockchip_clk_of_add_provider(np, ctx); -} - -CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init); - -struct clk_rk3568_inits { - void (*inits)(struct device_node *np); -}; - -static const struct clk_rk3568_inits clk_rk3568_pmucru_init = { - .inits = rk3568_pmu_clk_init, -}; - -static const struct clk_rk3568_inits clk_3568_cru_init = { - .inits = rk3568_clk_init, -}; - -static const struct of_device_id clk_rk3568_match_table[] = { - { - .compatible = "rockchip,rk3568-cru", - .data = &clk_3568_cru_init, - }, { - .compatible = "rockchip,rk3568-pmucru", - .data = &clk_rk3568_pmucru_init, - }, - { } -}; -MODULE_DEVICE_TABLE(of, clk_rk3568_match_table); - -static int __init clk_rk3568_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - const struct of_device_id *match; - const struct clk_rk3568_inits *init_data; - - match = of_match_device(clk_rk3568_match_table, &pdev->dev); - if (!match || !match->data) - return -EINVAL; - - init_data = match->data; - if (init_data->inits) - init_data->inits(np); - - return 0; -} - -static struct platform_driver clk_rk3568_driver = { - .driver = { - .name = "clk-rk3568", - .of_match_table = clk_rk3568_match_table, - .suppress_bind_attrs = true, - }, -}; -builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe); - -MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c deleted file mode 100644 index 0b49fed16..000000000 --- a/target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ /dev/null @@ -1,2706 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * Author: Andy Yan - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "rockchip_drm_drv.h" -#include "rockchip_drm_gem.h" -#include "rockchip_drm_fb.h" -#include "rockchip_drm_vop2.h" - -/* - * VOP2 architecture - * - +----------+ +-------------+ +-----------+ - | Cluster | | Sel 1 from 6| | 1 from 3 | - | window0 | | Layer0 | | RGB | - +----------+ +-------------+ +---------------+ +-------------+ +-----------+ - +----------+ +-------------+ |N from 6 layers| | | - | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+ - | window1 | | Layer1 | | | | | | 1 from 3 | - +----------+ +-------------+ +---------------+ +-------------+ | LVDS | - +----------+ +-------------+ +-----------+ - | Esmart | | Sel 1 from 6| - | window0 | | Layer2 | +---------------+ +-------------+ +-----------+ - +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 | - +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI | - | Esmart | | Sel 1 from 6| --------> | | | | +-----------+ - | Window1 | | Layer3 | +---------------+ +-------------+ - +----------+ +-------------+ +-----------+ - +----------+ +-------------+ | 1 from 3 | - | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI | - | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+ - +----------+ +-------------+ | Overlay2 +--->| Video Port2 | - +----------+ +-------------+ | | | | +-----------+ - | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 | - | Window1 | | Layer5 | | eDP | - +----------+ +-------------+ +-----------+ - * - */ - -enum vop2_data_format { - VOP2_FMT_ARGB8888 = 0, - VOP2_FMT_RGB888, - VOP2_FMT_RGB565, - VOP2_FMT_XRGB101010, - VOP2_FMT_YUV420SP, - VOP2_FMT_YUV422SP, - VOP2_FMT_YUV444SP, - VOP2_FMT_YUYV422 = 8, - VOP2_FMT_YUYV420, - VOP2_FMT_VYUY422, - VOP2_FMT_VYUY420, - VOP2_FMT_YUV420SP_TILE_8x4 = 0x10, - VOP2_FMT_YUV420SP_TILE_16x2, - VOP2_FMT_YUV422SP_TILE_8x4, - VOP2_FMT_YUV422SP_TILE_16x2, - VOP2_FMT_YUV420SP_10, - VOP2_FMT_YUV422SP_10, - VOP2_FMT_YUV444SP_10, -}; - -enum vop2_afbc_format { - VOP2_AFBC_FMT_RGB565, - VOP2_AFBC_FMT_ARGB2101010 = 2, - VOP2_AFBC_FMT_YUV420_10BIT, - VOP2_AFBC_FMT_RGB888, - VOP2_AFBC_FMT_ARGB8888, - VOP2_AFBC_FMT_YUV420 = 9, - VOP2_AFBC_FMT_YUV422 = 0xb, - VOP2_AFBC_FMT_YUV422_10BIT = 0xe, - VOP2_AFBC_FMT_INVALID = -1, -}; - -union vop2_alpha_ctrl { - u32 val; - struct { - /* [0:1] */ - u32 color_mode:1; - u32 alpha_mode:1; - /* [2:3] */ - u32 blend_mode:2; - u32 alpha_cal_mode:1; - /* [5:7] */ - u32 factor_mode:3; - /* [8:9] */ - u32 alpha_en:1; - u32 src_dst_swap:1; - u32 reserved:6; - /* [16:23] */ - u32 glb_alpha:8; - } bits; -}; - -struct vop2_alpha { - union vop2_alpha_ctrl src_color_ctrl; - union vop2_alpha_ctrl dst_color_ctrl; - union vop2_alpha_ctrl src_alpha_ctrl; - union vop2_alpha_ctrl dst_alpha_ctrl; -}; - -struct vop2_alpha_config { - bool src_premulti_en; - bool dst_premulti_en; - bool src_pixel_alpha_en; - bool dst_pixel_alpha_en; - u16 src_glb_alpha_value; - u16 dst_glb_alpha_value; -}; - -struct vop2_win { - struct vop2 *vop2; - struct drm_plane base; - const struct vop2_win_data *data; - struct regmap_field *reg[VOP2_WIN_MAX_REG]; - - /** - * @win_id: graphic window id, a cluster may be split into two - * graphics windows. - */ - u8 win_id; - u8 delay; - u32 offset; - - enum drm_plane_type type; -}; - -struct vop2_video_port { - struct drm_crtc crtc; - struct vop2 *vop2; - struct clk *dclk; - unsigned int id; - const struct vop2_video_port_regs *regs; - const struct vop2_video_port_data *data; - - struct completion dsp_hold_completion; - - /** - * @win_mask: Bitmask of windows attached to the video port; - */ - u32 win_mask; - - struct vop2_win *primary_plane; - struct drm_pending_vblank_event *event; - - unsigned int nlayers; -}; - -struct vop2 { - struct device *dev; - struct drm_device *drm; - struct vop2_video_port vps[ROCKCHIP_MAX_CRTC]; - - const struct vop2_data *data; - /* - * Number of windows that are registered as plane, may be less than the - * total number of hardware windows. - */ - u32 registered_num_wins; - - void __iomem *regs; - struct regmap *map; - - struct regmap *grf; - - /* physical map length of vop2 register */ - u32 len; - - void __iomem *lut_regs; - - /* protects crtc enable/disable */ - struct mutex vop2_lock; - - int irq; - - /* - * Some global resources are shared between all video ports(crtcs), so - * we need a ref counter here. - */ - unsigned int enable_count; - struct clk *hclk; - struct clk *aclk; - - /* must be put at the end of the struct */ - struct vop2_win win[]; -}; - -static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) -{ - return container_of(crtc, struct vop2_video_port, crtc); -} - -static struct vop2_win *to_vop2_win(struct drm_plane *p) -{ - return container_of(p, struct vop2_win, base); -} - -static void vop2_lock(struct vop2 *vop2) -{ - mutex_lock(&vop2->vop2_lock); -} - -static void vop2_unlock(struct vop2 *vop2) -{ - mutex_unlock(&vop2->vop2_lock); -} - -static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) -{ - regmap_write(vop2->map, offset, v); -} - -static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v) -{ - regmap_write(vp->vop2->map, vp->data->offset + offset, v); -} - -static u32 vop2_readl(struct vop2 *vop2, u32 offset) -{ - u32 val; - - regmap_read(vop2->map, offset, &val); - - return val; -} - -static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v) -{ - regmap_field_write(win->reg[reg], v); -} - -static bool vop2_cluster_window(const struct vop2_win *win) -{ - return win->data->feature & WIN_FEATURE_CLUSTER; -} - -static void vop2_cfg_done(struct vop2_video_port *vp) -{ - struct vop2 *vop2 = vp->vop2; - - regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, - BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); -} - -static void vop2_win_disable(struct vop2_win *win) -{ - vop2_win_write(win, VOP2_WIN_ENABLE, 0); - - if (vop2_cluster_window(win)) - vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0); -} - -static enum vop2_data_format vop2_convert_format(u32 format) -{ - switch (format) { - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - return VOP2_FMT_ARGB8888; - case DRM_FORMAT_RGB888: - case DRM_FORMAT_BGR888: - return VOP2_FMT_RGB888; - case DRM_FORMAT_RGB565: - case DRM_FORMAT_BGR565: - return VOP2_FMT_RGB565; - case DRM_FORMAT_NV12: - return VOP2_FMT_YUV420SP; - case DRM_FORMAT_NV16: - return VOP2_FMT_YUV422SP; - case DRM_FORMAT_NV24: - return VOP2_FMT_YUV444SP; - case DRM_FORMAT_YUYV: - case DRM_FORMAT_YVYU: - return VOP2_FMT_VYUY422; - case DRM_FORMAT_VYUY: - case DRM_FORMAT_UYVY: - return VOP2_FMT_YUYV422; - default: - DRM_ERROR("unsupported format[%08x]\n", format); - return -EINVAL; - } -} - -static enum vop2_afbc_format vop2_convert_afbc_format(u32 format) -{ - switch (format) { - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - return VOP2_AFBC_FMT_ARGB8888; - case DRM_FORMAT_RGB888: - case DRM_FORMAT_BGR888: - return VOP2_AFBC_FMT_RGB888; - case DRM_FORMAT_RGB565: - case DRM_FORMAT_BGR565: - return VOP2_AFBC_FMT_RGB565; - case DRM_FORMAT_NV12: - return VOP2_AFBC_FMT_YUV420; - case DRM_FORMAT_NV16: - return VOP2_AFBC_FMT_YUV422; - default: - return VOP2_AFBC_FMT_INVALID; - } - - return VOP2_AFBC_FMT_INVALID; -} - -static bool vop2_win_rb_swap(u32 format) -{ - switch (format) { - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - case DRM_FORMAT_BGR888: - case DRM_FORMAT_BGR565: - return true; - default: - return false; - } -} - -static bool vop2_afbc_rb_swap(u32 format) -{ - switch (format) { - case DRM_FORMAT_NV24: - return true; - default: - return false; - } -} - -static bool vop2_afbc_uv_swap(u32 format) -{ - switch (format) { - case DRM_FORMAT_NV12: - case DRM_FORMAT_NV16: - return true; - default: - return false; - } -} - -static bool vop2_win_uv_swap(u32 format) -{ - switch (format) { - case DRM_FORMAT_NV12: - case DRM_FORMAT_NV16: - case DRM_FORMAT_NV24: - return true; - default: - return false; - } -} - -static bool vop2_win_dither_up(u32 format) -{ - switch (format) { - case DRM_FORMAT_BGR565: - case DRM_FORMAT_RGB565: - return true; - default: - return false; - } -} - -static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode) -{ - /* - * FIXME: - * - * There is no media type for YUV444 output, - * so when out_mode is AAAA or P888, assume output is YUV444 on - * yuv format. - * - * From H/W testing, YUV444 mode need a rb swap. - */ - if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || - bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || - bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || - bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || - ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || - bus_format == MEDIA_BUS_FMT_YUV10_1X30) && - (output_mode == ROCKCHIP_OUT_MODE_AAAA || - output_mode == ROCKCHIP_OUT_MODE_P888))) - return true; - else - return false; -} - -static bool is_yuv_output(u32 bus_format) -{ - switch (bus_format) { - case MEDIA_BUS_FMT_YUV8_1X24: - case MEDIA_BUS_FMT_YUV10_1X30: - case MEDIA_BUS_FMT_UYYVYY8_0_5X24: - case MEDIA_BUS_FMT_UYYVYY10_0_5X30: - case MEDIA_BUS_FMT_YUYV8_2X8: - case MEDIA_BUS_FMT_YVYU8_2X8: - case MEDIA_BUS_FMT_UYVY8_2X8: - case MEDIA_BUS_FMT_VYUY8_2X8: - case MEDIA_BUS_FMT_YUYV8_1X16: - case MEDIA_BUS_FMT_YVYU8_1X16: - case MEDIA_BUS_FMT_UYVY8_1X16: - case MEDIA_BUS_FMT_VYUY8_1X16: - return true; - default: - return false; - } -} - -static bool rockchip_afbc(struct drm_plane *plane, u64 modifier) -{ - int i; - - if (modifier == DRM_FORMAT_MOD_LINEAR) - return false; - - for (i = 0 ; i < plane->modifier_count; i++) - if (plane->modifiers[i] == modifier) - return true; - - return false; -} - -static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, - u64 modifier) -{ - struct vop2_win *win = to_vop2_win(plane); - struct vop2 *vop2 = win->vop2; - - if (modifier == DRM_FORMAT_MOD_INVALID) - return false; - - if (modifier == DRM_FORMAT_MOD_LINEAR) - return true; - - if (!rockchip_afbc(plane, modifier)) { - drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n", - modifier); - - return false; - } - - return vop2_convert_afbc_format(format) >= 0; -} - -static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate, - bool afbc_half_block_en) -{ - struct drm_rect *src = &pstate->src; - struct drm_framebuffer *fb = pstate->fb; - u32 bpp = fb->format->cpp[0] * 8; - u32 vir_width = (fb->pitches[0] << 3) / bpp; - u32 width = drm_rect_width(src) >> 16; - u32 height = drm_rect_height(src) >> 16; - u32 act_xoffset = src->x1 >> 16; - u32 act_yoffset = src->y1 >> 16; - u32 align16_crop = 0; - u32 align64_crop = 0; - u32 height_tmp; - u8 tx, ty; - u8 bottom_crop_line_num = 0; - - /* 16 pixel align */ - if (height & 0xf) - align16_crop = 16 - (height & 0xf); - - height_tmp = height + align16_crop; - - /* 64 pixel align */ - if (height_tmp & 0x3f) - align64_crop = 64 - (height_tmp & 0x3f); - - bottom_crop_line_num = align16_crop + align64_crop; - - switch (pstate->rotation & - (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | - DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) { - case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y: - tx = 16 - ((act_xoffset + width) & 0xf); - ty = bottom_crop_line_num - act_yoffset; - break; - case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90: - tx = bottom_crop_line_num - act_yoffset; - ty = vir_width - width - act_xoffset; - break; - case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270: - tx = act_yoffset; - ty = act_xoffset; - break; - case DRM_MODE_REFLECT_X: - tx = 16 - ((act_xoffset + width) & 0xf); - ty = act_yoffset; - break; - case DRM_MODE_REFLECT_Y: - tx = act_xoffset; - ty = bottom_crop_line_num - act_yoffset; - break; - case DRM_MODE_ROTATE_90: - tx = bottom_crop_line_num - act_yoffset; - ty = act_xoffset; - break; - case DRM_MODE_ROTATE_270: - tx = act_yoffset; - ty = vir_width - width - act_xoffset; - break; - case 0: - tx = act_xoffset; - ty = act_yoffset; - break; - } - - if (afbc_half_block_en) - ty &= 0x7f; - -#define TRANSFORM_XOFFSET GENMASK(7, 0) -#define TRANSFORM_YOFFSET GENMASK(23, 16) - return FIELD_PREP(TRANSFORM_XOFFSET, tx) | - FIELD_PREP(TRANSFORM_YOFFSET, ty); -} - -/* - * A Cluster window has 2048 x 16 line buffer, which can - * works at 2048 x 16(Full) or 4096 x 8 (Half) mode. - * for Cluster_lb_mode register: - * 0: half mode, for plane input width range 2048 ~ 4096 - * 1: half mode, for cluster work at 2 * 2048 plane mode - * 2: half mode, for rotate_90/270 mode - * - */ -static int vop2_get_cluster_lb_mode(struct vop2_win *win, - struct drm_plane_state *pstate) -{ - if ((pstate->rotation & DRM_MODE_ROTATE_270) || - (pstate->rotation & DRM_MODE_ROTATE_90)) - return 2; - else - return 0; -} - -static u16 vop2_scale_factor(u32 src, u32 dst) -{ - u32 fac; - int shift; - - if (src == dst) - return 0; - - if (dst < 2) - return U16_MAX; - - if (src < 2) - return 0; - - if (src > dst) - shift = 12; - else - shift = 16; - - src--; - dst--; - - fac = DIV_ROUND_UP(src << shift, dst) - 1; - - if (fac > U16_MAX) - return U16_MAX; - - return fac; -} - -static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, - u32 src_w, u32 src_h, u32 dst_w, - u32 dst_h, u32 pixel_format) -{ - const struct drm_format_info *info; - u16 hor_scl_mode, ver_scl_mode; - u16 hscl_filter_mode, vscl_filter_mode; - u8 gt2 = 0; - u8 gt4 = 0; - u32 val; - - info = drm_format_info(pixel_format); - - if (src_h >= (4 * dst_h)) { - gt4 = 1; - src_h >>= 2; - } else if (src_h >= (2 * dst_h)) { - gt2 = 1; - src_h >>= 1; - } - - hor_scl_mode = scl_get_scl_mode(src_w, dst_w); - ver_scl_mode = scl_get_scl_mode(src_h, dst_h); - - if (hor_scl_mode == SCALE_UP) - hscl_filter_mode = VOP2_SCALE_UP_BIC; - else - hscl_filter_mode = VOP2_SCALE_DOWN_BIL; - - if (ver_scl_mode == SCALE_UP) - vscl_filter_mode = VOP2_SCALE_UP_BIL; - else - vscl_filter_mode = VOP2_SCALE_DOWN_BIL; - - /* - * RK3568 VOP Esmart/Smart dsp_w should be even pixel - * at scale down mode - */ - if (!(win->data->feature & WIN_FEATURE_AFBDC)) { - if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { - drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n", - win->data->name, dst_w); - dst_w++; - } - } - - val = vop2_scale_factor(src_w, dst_w); - vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val); - val = vop2_scale_factor(src_h, dst_h); - vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val); - - vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4); - vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2); - - vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode); - vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode); - - if (vop2_cluster_window(win)) - return; - - vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode); - vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); - - if (info->is_yuv) { - src_w /= info->hsub; - src_h /= info->vsub; - - gt4 = 0; - gt2 = 0; - - if (src_h >= (4 * dst_h)) { - gt4 = 1; - src_h >>= 2; - } else if (src_h >= (2 * dst_h)) { - gt2 = 1; - src_h >>= 1; - } - - hor_scl_mode = scl_get_scl_mode(src_w, dst_w); - ver_scl_mode = scl_get_scl_mode(src_h, dst_h); - - val = vop2_scale_factor(src_w, dst_w); - vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); - - val = vop2_scale_factor(src_h, dst_h); - vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); - - vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4); - vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2); - vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode); - vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode); - vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode); - vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode); - } -} - -static int vop2_convert_csc_mode(int csc_mode) -{ - switch (csc_mode) { - case V4L2_COLORSPACE_SMPTE170M: - case V4L2_COLORSPACE_470_SYSTEM_M: - case V4L2_COLORSPACE_470_SYSTEM_BG: - return CSC_BT601L; - case V4L2_COLORSPACE_REC709: - case V4L2_COLORSPACE_SMPTE240M: - case V4L2_COLORSPACE_DEFAULT: - return CSC_BT709L; - case V4L2_COLORSPACE_JPEG: - return CSC_BT601F; - case V4L2_COLORSPACE_BT2020: - return CSC_BT2020; - default: - return CSC_BT709L; - } -} - -/* - * colorspace path: - * Input Win csc Output - * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709) - * RGB --> R2Y __/ - * - * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020) - * RGB --> 709To2020->R2Y __/ - * - * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709) - * RGB --> R2Y __/ - * - * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020) - * RGB --> 709To2020->R2Y __/ - * - * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709) - * RGB --> R2Y __/ - * - * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601) - * RGB --> R2Y(601) __/ - * - * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709) - * RGB --> bypass __/ - * - * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020) - * - * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709) - * - * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601) - * - * 11. RGB --> bypass --> RGB_OUTPUT(709) - */ - -static void vop2_setup_csc_mode(struct vop2_video_port *vp, - struct vop2_win *win, - struct drm_plane_state *pstate) -{ - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); - int is_input_yuv = pstate->fb->format->is_yuv; - int is_output_yuv = is_yuv_output(vcstate->bus_format); - int input_csc = V4L2_COLORSPACE_DEFAULT; - int output_csc = vcstate->color_space; - bool r2y_en, y2r_en; - int csc_mode; - - if (is_input_yuv && !is_output_yuv) { - y2r_en = true; - r2y_en = false; - csc_mode = vop2_convert_csc_mode(input_csc); - } else if (!is_input_yuv && is_output_yuv) { - y2r_en = false; - r2y_en = true; - csc_mode = vop2_convert_csc_mode(output_csc); - } else { - y2r_en = false; - r2y_en = false; - csc_mode = false; - } - - vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en); - vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en); - vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode); -} - -static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) -{ - struct vop2 *vop2 = vp->vop2; - - vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); - vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); -} - -static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) -{ - struct vop2 *vop2 = vp->vop2; - - vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); -} - -static int vop2_core_clks_prepare_enable(struct vop2 *vop2) -{ - int ret; - - ret = clk_prepare_enable(vop2->hclk); - if (ret < 0) { - drm_err(vop2->drm, "failed to enable hclk - %d\n", ret); - return ret; - } - - ret = clk_prepare_enable(vop2->aclk); - if (ret < 0) { - drm_err(vop2->drm, "failed to enable aclk - %d\n", ret); - goto err; - } - - return 0; -err: - clk_disable_unprepare(vop2->hclk); - - return ret; -} - -static void vop2_enable(struct vop2 *vop2) -{ - int ret; - - ret = pm_runtime_get_sync(vop2->dev); - if (ret < 0) { - drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret); - return; - } - - ret = vop2_core_clks_prepare_enable(vop2); - if (ret) { - pm_runtime_put_sync(vop2->dev); - return; - } - - ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev); - if (ret) { - drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret); - return; - } - - if (vop2->data->soc_id == 3566) - vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); - - vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); - - /* - * Disable auto gating, this is a workaround to - * avoid display image shift when a window enabled. - */ - regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL, - RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN); - - vop2_writel(vop2, RK3568_SYS0_INT_CLR, - VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); - vop2_writel(vop2, RK3568_SYS0_INT_EN, - VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); - vop2_writel(vop2, RK3568_SYS1_INT_CLR, - VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); - vop2_writel(vop2, RK3568_SYS1_INT_EN, - VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); -} - -static void vop2_disable(struct vop2 *vop2) -{ - rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); - - pm_runtime_put_sync(vop2->dev); - - clk_disable_unprepare(vop2->aclk); - clk_disable_unprepare(vop2->hclk); -} - -static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct vop2 *vop2 = vp->vop2; - int ret; - - vop2_lock(vop2); - - drm_crtc_vblank_off(crtc); - - /* - * Vop standby will take effect at end of current frame, - * if dsp hold valid irq happen, it means standby complete. - * - * we must wait standby complete when we want to disable aclk, - * if not, memory bus maybe dead. - */ - reinit_completion(&vp->dsp_hold_completion); - - vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); - - vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); - - ret = wait_for_completion_timeout(&vp->dsp_hold_completion, - msecs_to_jiffies(50)); - if (!ret) - drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); - - vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); - - clk_disable_unprepare(vp->dclk); - - vop2->enable_count--; - - if (!vop2->enable_count) - vop2_disable(vop2); - - vop2_unlock(vop2); - - if (crtc->state->event && !crtc->state->active) { - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, crtc->state->event); - spin_unlock_irq(&crtc->dev->event_lock); - - crtc->state->event = NULL; - } -} - -static int vop2_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *astate) -{ - struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane); - struct drm_framebuffer *fb = pstate->fb; - struct drm_crtc *crtc = pstate->crtc; - struct drm_crtc_state *cstate; - struct vop2_video_port *vp; - struct vop2 *vop2; - const struct vop2_data *vop2_data; - struct drm_rect *dest = &pstate->dst; - struct drm_rect *src = &pstate->src; - int min_scale = FRAC_16_16(1, 8); - int max_scale = FRAC_16_16(8, 1); - int format; - int ret; - - if (!crtc) - return 0; - - vp = to_vop2_video_port(crtc); - vop2 = vp->vop2; - vop2_data = vop2->data; - - cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc); - if (WARN_ON(!cstate)) - return -EINVAL; - - ret = drm_atomic_helper_check_plane_state(pstate, cstate, - min_scale, max_scale, - true, true); - if (ret) - return ret; - - if (!pstate->visible) - return 0; - - format = vop2_convert_format(fb->format->format); - if (format < 0) - return format; - - if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 || - drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) { - drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n", - drm_rect_width(src) >> 16, drm_rect_height(src) >> 16, - drm_rect_width(dest), drm_rect_height(dest)); - pstate->visible = false; - return 0; - } - - if (drm_rect_width(src) >> 16 > vop2_data->max_input.width || - drm_rect_height(src) >> 16 > vop2_data->max_input.height) { - drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n", - drm_rect_width(src) >> 16, - drm_rect_height(src) >> 16, - vop2_data->max_input.width, - vop2_data->max_input.height); - return -EINVAL; - } - - /* - * Src.x1 can be odd when do clip, but yuv plane start point - * need align with 2 pixel. - */ - if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) { - drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n"); - return -EINVAL; - } - - return 0; -} - -static void vop2_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) -{ - struct drm_plane_state *old_pstate = drm_atomic_get_old_plane_state(state, plane); - struct vop2_win *win = to_vop2_win(plane); - struct vop2 *vop2 = win->vop2; - - drm_dbg(vop2->drm, "%s disable\n", win->data->name); - - if (!old_pstate->crtc) - return; - - vop2_win_disable(win); - vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0); -} - -/* - * The color key is 10 bit, so all format should - * convert to 10 bit here. - */ -static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key) -{ - struct drm_plane_state *pstate = plane->state; - struct drm_framebuffer *fb = pstate->fb; - struct vop2_win *win = to_vop2_win(plane); - u32 color_key_en = 0; - u32 r = 0; - u32 g = 0; - u32 b = 0; - - if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) { - vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0); - return; - } - - switch (fb->format->format) { - case DRM_FORMAT_RGB565: - case DRM_FORMAT_BGR565: - r = (color_key & 0xf800) >> 11; - g = (color_key & 0x7e0) >> 5; - b = (color_key & 0x1f); - r <<= 5; - g <<= 4; - b <<= 5; - color_key_en = 1; - break; - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - case DRM_FORMAT_RGB888: - case DRM_FORMAT_BGR888: - r = (color_key & 0xff0000) >> 16; - g = (color_key & 0xff00) >> 8; - b = (color_key & 0xff); - r <<= 2; - g <<= 2; - b <<= 2; - color_key_en = 1; - break; - } - - vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en); - vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b); -} - -static void vop2_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) -{ - struct drm_plane_state *pstate = plane->state; - struct drm_crtc *crtc = pstate->crtc; - struct vop2_win *win = to_vop2_win(plane); - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; - struct vop2 *vop2 = win->vop2; - struct drm_framebuffer *fb = pstate->fb; - u32 bpp = fb->format->cpp[0] * 8; - u32 actual_w, actual_h, dsp_w, dsp_h; - u32 act_info, dsp_info; - u32 format; - u32 afbc_format; - u32 rb_swap; - u32 uv_swap; - struct drm_rect *src = &pstate->src; - struct drm_rect *dest = &pstate->dst; - u32 afbc_tile_num; - u32 transform_offset; - bool dither_up; - bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; - bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; - bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; - bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; - struct rockchip_gem_object *rk_obj; - unsigned long offset; - bool afbc_en; - dma_addr_t yrgb_mst; - dma_addr_t uv_mst; - - /* - * can't update plane when vop2 is disabled. - */ - if (WARN_ON(!crtc)) - return; - - if (!pstate->visible) { - vop2_plane_atomic_disable(plane, state); - return; - } - - afbc_en = rockchip_afbc(plane, fb->modifier); - - offset = (src->x1 >> 16) * fb->format->cpp[0]; - - /* - * AFBC HDR_PTR must set to the zero offset of the framebuffer. - */ - if (afbc_en) - offset = 0; - else if (pstate->rotation & DRM_MODE_REFLECT_Y) - offset += ((src->y2 >> 16) - 1) * fb->pitches[0]; - else - offset += (src->y1 >> 16) * fb->pitches[0]; - - rk_obj = to_rockchip_obj(fb->obj[0]); - - yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; - if (fb->format->is_yuv) { - int hsub = fb->format->hsub; - int vsub = fb->format->vsub; - - offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub; - offset += (src->y1 >> 16) * fb->pitches[1] / vsub; - - if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en) - offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub; - - rk_obj = to_rockchip_obj(fb->obj[0]); - uv_mst = rk_obj->dma_addr + offset + fb->offsets[1]; - } - - actual_w = drm_rect_width(src) >> 16; - actual_h = drm_rect_height(src) >> 16; - dsp_w = drm_rect_width(dest); - - if (dest->x1 + dsp_w > adjusted_mode->hdisplay) { - drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n", - vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay); - dsp_w = adjusted_mode->hdisplay - dest->x1; - if (dsp_w < 4) - dsp_w = 4; - actual_w = dsp_w * actual_w / drm_rect_width(dest); - } - - dsp_h = drm_rect_height(dest); - - if (dest->y1 + dsp_h > adjusted_mode->vdisplay) { - drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n", - vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay); - dsp_h = adjusted_mode->vdisplay - dest->y1; - if (dsp_h < 4) - dsp_h = 4; - actual_h = dsp_h * actual_h / drm_rect_height(dest); - } - - /* - * This is workaround solution for IC design: - * esmart can't support scale down when actual_w % 16 == 1. - */ - if (!(win->data->feature & WIN_FEATURE_AFBDC)) { - if (actual_w > dsp_w && (actual_w & 0xf) == 1) { - drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", - vp->id, win->data->name, actual_w); - actual_w -= 1; - } - } - - if (afbc_en && actual_w % 4) { - drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n", - vp->id, win->data->name, actual_w); - actual_w = ALIGN_DOWN(actual_w, 4); - } - - act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); - dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff); - - format = vop2_convert_format(fb->format->format); - - drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", - vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, - dest->x1, dest->y1, - &fb->format->format, - afbc_en ? "AFBC" : "", &yrgb_mst); - - if (afbc_en) { - u32 stride; - - /* the afbc superblock is 16 x 16 */ - afbc_format = vop2_convert_afbc_format(fb->format->format); - - /* Enable color transform for YTR */ - if (fb->modifier & AFBC_FORMAT_MOD_YTR) - afbc_format |= (1 << 4); - - afbc_tile_num = ALIGN(actual_w, 16) >> 4; - - /* - * AFBC pic_vir_width is count by pixel, this is different - * with WIN_VIR_STRIDE. - */ - stride = (fb->pitches[0] << 3) / bpp; - if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270)) - drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligened\n", - vp->id, win->data->name, stride); - - rb_swap = vop2_afbc_rb_swap(fb->format->format); - uv_swap = vop2_afbc_uv_swap(fb->format->format); - /* - * This is a workaround for crazy IC design, Cluster - * and Esmart/Smart use different format configuration map: - * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart. - * - * This is one thing we can make the convert simple: - * AFBCD decode all the YUV data to YUV444. So we just - * set all the yuv 10 bit to YUV444_10. - */ - if (fb->format->is_yuv && bpp == 10) - format = VOP2_CLUSTER_YUV444_10; - - if (vop2_cluster_window(win)) - vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); - vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); - vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap); - vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); - vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); - vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); - if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) { - vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0); - transform_offset = vop2_afbc_transform_offset(pstate, false); - } else { - vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1); - transform_offset = vop2_afbc_transform_offset(pstate, true); - } - vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); - vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); - vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset); - vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1)); - vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16))); - vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride); - vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num); - vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror); - vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270); - vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90); - } else { - vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); - } - - vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror); - - if (rotate_90 || rotate_270) { - act_info = swahw32(act_info); - actual_w = drm_rect_height(src) >> 16; - actual_h = drm_rect_width(src) >> 16; - } - - vop2_win_write(win, VOP2_WIN_FORMAT, format); - vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst); - - rb_swap = vop2_win_rb_swap(fb->format->format); - vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap); - if (!vop2_cluster_window(win)) { - uv_swap = vop2_win_uv_swap(fb->format->format); - vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap); - } - - if (fb->format->is_yuv) { - vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4)); - vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst); - } - - vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format); - if (!vop2_cluster_window(win)) - vop2_plane_setup_color_key(plane, 0); - vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info); - vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info); - vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff)); - - vop2_setup_csc_mode(vp, win, pstate); - - dither_up = vop2_win_dither_up(fb->format->format); - vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up); - - vop2_win_write(win, VOP2_WIN_ENABLE, 1); - - if (vop2_cluster_window(win)) { - int lb_mode = vop2_get_cluster_lb_mode(win, pstate); - - vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode); - vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1); - } -} - -static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = { - .atomic_check = vop2_plane_atomic_check, - .atomic_update = vop2_plane_atomic_update, - .atomic_disable = vop2_plane_atomic_disable, -}; - -static const struct drm_plane_funcs vop2_plane_funcs = { - .update_plane = drm_atomic_helper_update_plane, - .disable_plane = drm_atomic_helper_disable_plane, - .destroy = drm_plane_cleanup, - .reset = drm_atomic_helper_plane_reset, - .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, - .format_mod_supported = rockchip_vop2_mod_supported, -}; - -static int vop2_crtc_enable_vblank(struct drm_crtc *crtc) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - - vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD); - - return 0; -} - -static void vop2_crtc_disable_vblank(struct drm_crtc *crtc) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - - vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD); -} - -static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) -{ - drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | - CRTC_STEREO_DOUBLE); - - return true; -} - -static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl) -{ - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); - - switch (vcstate->bus_format) { - case MEDIA_BUS_FMT_RGB565_1X16: - *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; - break; - case MEDIA_BUS_FMT_RGB666_1X18: - case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: - case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: - *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; - *dsp_ctrl |= RGB888_TO_RGB666; - break; - case MEDIA_BUS_FMT_YUV8_1X24: - case MEDIA_BUS_FMT_UYYVYY8_0_5X24: - *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; - break; - default: - break; - } - - if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA) - *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; - - *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL, - DITHER_DOWN_ALLEGRO); -} - -static void vop2_post_config(struct drm_crtc *crtc) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct drm_display_mode *mode = &crtc->state->adjusted_mode; - u16 vtotal = mode->crtc_vtotal; - u16 hdisplay = mode->crtc_hdisplay; - u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; - u16 vdisplay = mode->crtc_vdisplay; - u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; - u32 left_margin = 100, right_margin = 100; - u32 top_margin = 100, bottom_margin = 100; - u16 hsize = hdisplay * (left_margin + right_margin) / 200; - u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; - u16 hact_end, vact_end; - u32 val; - - vsize = rounddown(vsize, 2); - hsize = rounddown(hsize, 2); - hact_st += hdisplay * (100 - left_margin) / 200; - hact_end = hact_st + hsize; - val = hact_st << 16; - val |= hact_end; - vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val); - vact_st += vdisplay * (100 - top_margin) / 200; - vact_end = vact_st + vsize; - val = vact_st << 16; - val |= vact_end; - vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val); - val = scl_cal_scale2(vdisplay, vsize) << 16; - val |= scl_cal_scale2(hdisplay, hsize); - vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val); - - val = 0; - if (hdisplay != hsize) - val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN; - if (vdisplay != vsize) - val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN; - vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); - - if (mode->flags & DRM_MODE_FLAG_INTERLACE) { - u16 vact_st_f1 = vtotal + vact_st + 1; - u16 vact_end_f1 = vact_st_f1 + vsize; - - val = vact_st_f1 << 16 | vact_end_f1; - vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); - } - - vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); -} - -static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, - u32 polflags) -{ - struct vop2 *vop2 = vp->vop2; - u32 die, dip; - - die = vop2_readl(vop2, RK3568_DSP_IF_EN); - dip = vop2_readl(vop2, RK3568_DSP_IF_POL); - - switch (id) { - case ROCKCHIP_VOP2_EP_RGB0: - die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_RGB | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id); - if (polflags & POLFLAG_DCLK_INV) - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); - else - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); - break; - case ROCKCHIP_VOP2_EP_HDMI0: - die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_HDMI | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id); - break; - case ROCKCHIP_VOP2_EP_EDP0: - die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_EDP | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id); - break; - case ROCKCHIP_VOP2_EP_MIPI0: - die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id); - dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; - dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); - break; - case ROCKCHIP_VOP2_EP_MIPI1: - die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); - dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; - dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); - break; - case ROCKCHIP_VOP2_EP_LVDS0: - die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id); - dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; - dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); - break; - case ROCKCHIP_VOP2_EP_LVDS1: - die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX; - die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 | - FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id); - dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; - dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); - break; - default: - drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); - return; - }; - - dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; - - vop2_writel(vop2, RK3568_DSP_IF_EN, die); - vop2_writel(vop2, RK3568_DSP_IF_POL, dip); -} - -static int us_to_vertical_line(struct drm_display_mode *mode, int us) -{ - return us * mode->clock / mode->htotal / 1000; -} - -static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct vop2 *vop2 = vp->vop2; - const struct vop2_data *vop2_data = vop2->data; - const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; - struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); - struct drm_display_mode *mode = &crtc->state->adjusted_mode; - unsigned long clock = mode->crtc_clock * 1000; - u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; - u16 hdisplay = mode->crtc_hdisplay; - u16 htotal = mode->crtc_htotal; - u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; - u16 hact_end = hact_st + hdisplay; - u16 vdisplay = mode->crtc_vdisplay; - u16 vtotal = mode->crtc_vtotal; - u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; - u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; - u16 vact_end = vact_st + vdisplay; - u8 out_mode; - u32 dsp_ctrl = 0; - int act_end; - u32 val, polflags; - int ret; - struct drm_encoder *encoder; - - drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", - hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", - drm_mode_vrefresh(mode), vcstate->output_type, vp->id); - - vop2_lock(vop2); - - ret = clk_prepare_enable(vp->dclk); - if (ret < 0) { - drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", - vp->id, ret); - return; - } - - if (!vop2->enable_count) - vop2_enable(vop2); - - vop2->enable_count++; - - vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); - - polflags = 0; - if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) - polflags |= POLFLAG_DCLK_INV; - if (mode->flags & DRM_MODE_FLAG_PHSYNC) - polflags |= BIT(HSYNC_POSITIVE); - if (mode->flags & DRM_MODE_FLAG_PVSYNC) - polflags |= BIT(VSYNC_POSITIVE); - - drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { - struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); - - rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); - } - - if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && - !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) - out_mode = ROCKCHIP_OUT_MODE_P888; - else - out_mode = vcstate->output_mode; - - dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode); - - if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) - dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; - - if (is_yuv_output(vcstate->bus_format)) - dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; - - vop2_dither_setup(crtc, &dsp_ctrl); - - vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len); - val = hact_st << 16; - val |= hact_end; - vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val); - - val = vact_st << 16; - val |= vact_end; - vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); - - if (mode->flags & DRM_MODE_FLAG_INTERLACE) { - u16 vact_st_f1 = vtotal + vact_st + 1; - u16 vact_end_f1 = vact_st_f1 + vdisplay; - - val = vact_st_f1 << 16 | vact_end_f1; - vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); - - val = vtotal << 16 | (vtotal + vsync_len); - vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val); - dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE; - dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL; - dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN; - vtotal += vtotal + 1; - act_end = vact_end_f1; - } else { - act_end = vact_end; - } - - vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), - (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end); - - vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len); - - if (mode->flags & DRM_MODE_FLAG_DBLCLK) { - dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; - clock *= 2; - } - - vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); - - clk_set_rate(vp->dclk, clock); - - vop2_post_config(crtc); - - vop2_cfg_done(vp); - - vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); - - drm_crtc_vblank_on(crtc); - - vop2_unlock(vop2); -} - -static int vop2_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct drm_plane *plane; - int nplanes = 0; - struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); - - drm_atomic_crtc_state_for_each_plane(plane, crtc_state) - nplanes++; - - if (nplanes > vp->nlayers) - return -EINVAL; - - return 0; -} - -static bool is_opaque(u16 alpha) -{ - return (alpha >> 8) == 0xff; -} - -static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config, - struct vop2_alpha *alpha) -{ - int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1; - int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1; - int src_color_mode = alpha_config->src_premulti_en ? - ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; - int dst_color_mode = alpha_config->dst_premulti_en ? - ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; - - alpha->src_color_ctrl.val = 0; - alpha->dst_color_ctrl.val = 0; - alpha->src_alpha_ctrl.val = 0; - alpha->dst_alpha_ctrl.val = 0; - - if (!alpha_config->src_pixel_alpha_en) - alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; - else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en) - alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX; - else - alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; - - alpha->src_color_ctrl.bits.alpha_en = 1; - - if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) { - alpha->src_color_ctrl.bits.color_mode = src_color_mode; - alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; - } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) { - alpha->src_color_ctrl.bits.color_mode = src_color_mode; - alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE; - } else { - alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL; - alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; - } - alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8; - alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; - alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; - - alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; - alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; - alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; - alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8; - alpha->dst_color_ctrl.bits.color_mode = dst_color_mode; - alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; - - alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; - alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode; - alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; - alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE; - - alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; - if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en) - alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX; - else - alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; - alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION; - alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; -} - -static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id) -{ - struct vop2_video_port *vp; - int used_layer = 0; - int i; - - for (i = 0; i < port_id; i++) { - vp = &vop2->vps[i]; - used_layer += hweight32(vp->win_mask); - } - - return used_layer; -} - -static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win) -{ - u32 offset = (main_win->data->phys_id * 0x10); - struct vop2_alpha_config alpha_config; - struct vop2_alpha alpha; - struct drm_plane_state *bottom_win_pstate; - bool src_pixel_alpha_en = false; - u16 src_glb_alpha_val, dst_glb_alpha_val; - bool premulti_en = false; - bool swap = false; - - /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */ - bottom_win_pstate = main_win->base.state; - src_glb_alpha_val = 0; - dst_glb_alpha_val = main_win->base.state->alpha; - - if (!bottom_win_pstate->fb) - return; - - alpha_config.src_premulti_en = premulti_en; - alpha_config.dst_premulti_en = false; - alpha_config.src_pixel_alpha_en = src_pixel_alpha_en; - alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ - alpha_config.src_glb_alpha_value = src_glb_alpha_val; - alpha_config.dst_glb_alpha_value = dst_glb_alpha_val; - vop2_parse_alpha(&alpha_config, &alpha); - - alpha.src_color_ctrl.bits.src_dst_swap = swap; - vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset, - alpha.src_color_ctrl.val); - vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset, - alpha.dst_color_ctrl.val); - vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset, - alpha.src_alpha_ctrl.val); - vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset, - alpha.dst_alpha_ctrl.val); -} - -static void vop2_setup_alpha(struct vop2_video_port *vp) -{ - struct vop2 *vop2 = vp->vop2; - struct drm_framebuffer *fb; - struct vop2_alpha_config alpha_config; - struct vop2_alpha alpha; - struct drm_plane *plane; - int pixel_alpha_en; - int premulti_en, gpremulti_en = 0; - int mixer_id; - u32 offset; - bool bottom_layer_alpha_en = false; - u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE; - - mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id); - alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ - - drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { - struct vop2_win *win = to_vop2_win(plane); - - if (plane->state->normalized_zpos == 0 && - !is_opaque(plane->state->alpha) && - !vop2_cluster_window(win)) { - /* - * If bottom layer have global alpha effect [except cluster layer, - * because cluster have deal with bottom layer global alpha value - * at cluster mix], bottom layer mix need deal with global alpha. - */ - bottom_layer_alpha_en = true; - dst_global_alpha = plane->state->alpha; - } - } - - drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { - struct vop2_win *win = to_vop2_win(plane); - int zpos = plane->state->normalized_zpos; - - if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) - premulti_en = 1; - else - premulti_en = 0; - - plane = &win->base; - fb = plane->state->fb; - - pixel_alpha_en = fb->format->has_alpha; - - alpha_config.src_premulti_en = premulti_en; - - if (bottom_layer_alpha_en && zpos == 1) { - gpremulti_en = premulti_en; - /* Cd = Cs + (1 - As) * Cd * Agd */ - alpha_config.dst_premulti_en = false; - alpha_config.src_pixel_alpha_en = pixel_alpha_en; - alpha_config.src_glb_alpha_value = plane->state->alpha; - alpha_config.dst_glb_alpha_value = dst_global_alpha; - } else if (vop2_cluster_window(win)) { - /* Mix output data only have pixel alpha */ - alpha_config.dst_premulti_en = true; - alpha_config.src_pixel_alpha_en = true; - alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - } else { - /* Cd = Cs + (1 - As) * Cd */ - alpha_config.dst_premulti_en = true; - alpha_config.src_pixel_alpha_en = pixel_alpha_en; - alpha_config.src_glb_alpha_value = plane->state->alpha; - alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - } - - vop2_parse_alpha(&alpha_config, &alpha); - - offset = (mixer_id + zpos - 1) * 0x10; - vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset, - alpha.src_color_ctrl.val); - vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset, - alpha.dst_color_ctrl.val); - vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset, - alpha.src_alpha_ctrl.val); - vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset, - alpha.dst_alpha_ctrl.val); - } - - if (vp->id == 0) { - if (bottom_layer_alpha_en) { - /* Transfer pixel alpha to hdr mix */ - alpha_config.src_premulti_en = gpremulti_en; - alpha_config.dst_premulti_en = true; - alpha_config.src_pixel_alpha_en = true; - alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; - vop2_parse_alpha(&alpha_config, &alpha); - - vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, - alpha.src_color_ctrl.val); - vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL, - alpha.dst_color_ctrl.val); - vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL, - alpha.src_alpha_ctrl.val); - vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL, - alpha.dst_alpha_ctrl.val); - } else { - vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0); - } - } -} - -static void vop2_setup_layer_mixer(struct vop2_video_port *vp) -{ - struct vop2 *vop2 = vp->vop2; - struct drm_plane *plane; - u32 layer_sel = 0; - u32 port_sel; - unsigned int nlayer, ofs; - struct drm_display_mode *adjusted_mode; - u16 hsync_len; - u16 hdisplay; - u32 bg_dly; - u32 pre_scan_dly; - int i; - struct vop2_video_port *vp0 = &vop2->vps[0]; - struct vop2_video_port *vp1 = &vop2->vps[1]; - struct vop2_video_port *vp2 = &vop2->vps[2]; - - adjusted_mode = &vp->crtc.state->adjusted_mode; - hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; - hdisplay = adjusted_mode->crtc_hdisplay; - - bg_dly = vp->data->pre_scan_max_dly[3]; - vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id), - FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly)); - - pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; - vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); - - vop2_writel(vop2, RK3568_OVL_CTRL, 0); - port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); - port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT; - - if (vp0->nlayers) - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, - vp0->nlayers - 1); - else - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8); - - if (vp1->nlayers) - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, - (vp0->nlayers + vp1->nlayers - 1)); - else - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); - - if (vp2->nlayers) - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, - (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1)); - else - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); - - layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); - - ofs = 0; - for (i = 0; i < vp->id; i++) - ofs += vop2->vps[i].nlayers; - - nlayer = 0; - drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { - struct vop2_win *win = to_vop2_win(plane); - - switch (win->data->phys_id) { - case ROCKCHIP_VOP2_CLUSTER0: - port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id); - break; - case ROCKCHIP_VOP2_CLUSTER1: - port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id); - break; - case ROCKCHIP_VOP2_ESMART0: - port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id); - break; - case ROCKCHIP_VOP2_ESMART1: - port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id); - break; - case ROCKCHIP_VOP2_SMART0: - port_sel &= ~RK3568_OVL_PORT_SEL__SMART0; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id); - break; - case ROCKCHIP_VOP2_SMART1: - port_sel &= ~RK3568_OVL_PORT_SEL__SMART1; - port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id); - break; - } - - layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, - 0x7); - layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, - win->data->layer_sel_id); - nlayer++; - } - - /* configure unused layers to 0x5 (reserved) */ - for (; nlayer < vp->nlayers; nlayer++) { - layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7); - layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5); - } - - vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); - vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); - vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD); -} - -static void vop2_setup_dly_for_windows(struct vop2 *vop2) -{ - struct vop2_win *win; - int i = 0; - u32 cdly = 0, sdly = 0; - - for (i = 0; i < vop2->data->win_size; i++) { - u32 dly; - - win = &vop2->win[i]; - dly = win->delay; - - switch (win->data->phys_id) { - case ROCKCHIP_VOP2_CLUSTER0: - cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly); - cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly); - break; - case ROCKCHIP_VOP2_CLUSTER1: - cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly); - cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly); - break; - case ROCKCHIP_VOP2_ESMART0: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly); - break; - case ROCKCHIP_VOP2_ESMART1: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly); - break; - case ROCKCHIP_VOP2_SMART0: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly); - break; - case ROCKCHIP_VOP2_SMART1: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly); - break; - } - } - - vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly); - vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly); -} - -static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - struct vop2 *vop2 = vp->vop2; - struct drm_plane *plane; - - vp->win_mask = 0; - - drm_atomic_crtc_for_each_plane(plane, crtc) { - struct vop2_win *win = to_vop2_win(plane); - - win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT]; - - vp->win_mask |= BIT(win->data->phys_id); - - if (vop2_cluster_window(win)) - vop2_setup_cluster_alpha(vop2, win); - } - - if (!vp->win_mask) - return; - - vop2_setup_layer_mixer(vp); - vop2_setup_alpha(vp); - vop2_setup_dly_for_windows(vop2); -} - -static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - struct vop2_video_port *vp = to_vop2_video_port(crtc); - - vop2_post_config(crtc); - - vop2_cfg_done(vp); - - spin_lock_irq(&crtc->dev->event_lock); - - if (crtc->state->event) { - WARN_ON(drm_crtc_vblank_get(crtc)); - vp->event = crtc->state->event; - crtc->state->event = NULL; - } - - spin_unlock_irq(&crtc->dev->event_lock); -} - -static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { - .mode_fixup = vop2_crtc_mode_fixup, - .atomic_check = vop2_crtc_atomic_check, - .atomic_begin = vop2_crtc_atomic_begin, - .atomic_flush = vop2_crtc_atomic_flush, - .atomic_enable = vop2_crtc_atomic_enable, - .atomic_disable = vop2_crtc_atomic_disable, -}; - -static void vop2_crtc_reset(struct drm_crtc *crtc) -{ - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); - - if (crtc->state) { - __drm_atomic_helper_crtc_destroy_state(crtc->state); - kfree(vcstate); - } - - vcstate = kzalloc(sizeof(*vcstate), GFP_KERNEL); - if (!vcstate) - return; - - crtc->state = &vcstate->base; - crtc->state->crtc = crtc; -} - -static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc) -{ - struct rockchip_crtc_state *vcstate, *old_vcstate; - - old_vcstate = to_rockchip_crtc_state(crtc->state); - - vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL); - if (!vcstate) - return NULL; - - __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base); - - return &vcstate->base; -} - -static void vop2_crtc_destroy_state(struct drm_crtc *crtc, - struct drm_crtc_state *state) -{ - struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state); - - __drm_atomic_helper_crtc_destroy_state(&vcstate->base); - kfree(vcstate); -} - -static const struct drm_crtc_funcs vop2_crtc_funcs = { - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, - .destroy = drm_crtc_cleanup, - .reset = vop2_crtc_reset, - .atomic_duplicate_state = vop2_crtc_duplicate_state, - .atomic_destroy_state = vop2_crtc_destroy_state, - .enable_vblank = vop2_crtc_enable_vblank, - .disable_vblank = vop2_crtc_disable_vblank, -}; - -static irqreturn_t vop2_isr(int irq, void *data) -{ - struct vop2 *vop2 = data; - const struct vop2_data *vop2_data = vop2->data; - u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM]; - int ret = IRQ_NONE; - int i; - - /* - * The irq is shared with the iommu. If the runtime-pm state of the - * vop2-device is disabled the irq has to be targeted at the iommu. - */ - if (!pm_runtime_get_if_in_use(vop2->dev)) - return IRQ_NONE; - - for (i = 0; i < vop2_data->nr_vps; i++) { - struct vop2_video_port *vp = &vop2->vps[i]; - struct drm_crtc *crtc = &vp->crtc; - u32 irqs; - - irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); - vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); - - if (irqs & VP_INT_DSP_HOLD_VALID) { - complete(&vp->dsp_hold_completion); - ret = IRQ_HANDLED; - } - - if (irqs & VP_INT_FS_FIELD) { - drm_crtc_handle_vblank(crtc); - spin_lock(&crtc->dev->event_lock); - if (vp->event) { - u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); - - if (!(val & BIT(vp->id))) { - drm_crtc_send_vblank_event(crtc, vp->event); - vp->event = NULL; - drm_crtc_vblank_put(crtc); - } - } - spin_unlock(&crtc->dev->event_lock); - - ret = IRQ_HANDLED; - } - - if (irqs & VP_INT_POST_BUF_EMPTY) { - drm_err_ratelimited(vop2->drm, - "POST_BUF_EMPTY irq err at vp%d\n", - vp->id); - ret = IRQ_HANDLED; - } - } - - axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS); - vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]); - axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS); - vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]); - - for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) { - if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) { - drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n"); - ret = IRQ_HANDLED; - } - } - - pm_runtime_put(vop2->dev); - - return ret; -} - -static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, - unsigned long possible_crtcs) -{ - const struct vop2_win_data *win_data = win->data; - unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | - BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE); - int ret; - - ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs, - &vop2_plane_funcs, win_data->formats, - win_data->nformats, - win_data->format_modifiers, - win->type, win_data->name); - if (ret) { - drm_err(vop2->drm, "failed to initialize plane %d\n", ret); - return ret; - } - - drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs); - - if (win->data->supported_rotations) - drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0, - DRM_MODE_ROTATE_0 | - win->data->supported_rotations); - drm_plane_create_alpha_property(&win->base); - drm_plane_create_blend_mode_property(&win->base, blend_caps); - drm_plane_create_zpos_property(&win->base, win->win_id, 0, - vop2->registered_num_wins - 1); - - return 0; -} - -static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2) -{ - int i; - - for (i = 0; i < vop2->data->nr_vps; i++) { - struct vop2_video_port *vp = &vop2->vps[i]; - - if (!vp->crtc.port) - continue; - if (vp->primary_plane) - continue; - - return vp; - } - - return NULL; -} - -#define NR_LAYERS 6 - -static int vop2_create_crtc(struct vop2 *vop2) -{ - const struct vop2_data *vop2_data = vop2->data; - struct drm_device *drm = vop2->drm; - struct device *dev = vop2->dev; - struct drm_plane *plane; - struct device_node *port; - struct vop2_video_port *vp; - int i, nvp, nvps = 0; - int ret; - - for (i = 0; i < vop2_data->nr_vps; i++) { - const struct vop2_video_port_data *vp_data; - struct device_node *np; - char dclk_name[9]; - - vp_data = &vop2_data->vp[i]; - vp = &vop2->vps[i]; - vp->vop2 = vop2; - vp->id = vp_data->id; - vp->regs = vp_data->regs; - vp->data = vp_data; - - snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); - vp->dclk = devm_clk_get(vop2->dev, dclk_name); - if (IS_ERR(vp->dclk)) { - drm_err(vop2->drm, "failed to get %s\n", dclk_name); - return PTR_ERR(vp->dclk); - } - - np = of_graph_get_remote_node(dev->of_node, i, -1); - if (!np) { - drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); - continue; - } - of_node_put(np); - - port = of_graph_get_port_by_id(dev->of_node, i); - if (!port) { - drm_err(vop2->drm, "no port node found for video_port%d\n", i); - return -ENOENT; - } - - vp->crtc.port = port; - nvps++; - } - - nvp = 0; - for (i = 0; i < vop2->registered_num_wins; i++) { - struct vop2_win *win = &vop2->win[i]; - u32 possible_crtcs; - - if (vop2->data->soc_id == 3566) { - /* - * On RK3566 these windows don't have an independent - * framebuffer. They share the framebuffer with smart0, - * esmart0 and cluster0 respectively. - */ - switch (win->data->phys_id) { - case ROCKCHIP_VOP2_SMART1: - case ROCKCHIP_VOP2_ESMART1: - case ROCKCHIP_VOP2_CLUSTER1: - continue; - } - } - - if (win->type == DRM_PLANE_TYPE_PRIMARY) { - vp = find_vp_without_primary(vop2); - if (vp) { - possible_crtcs = BIT(nvp); - vp->primary_plane = win; - nvp++; - } else { - /* change the unused primary window to overlay window */ - win->type = DRM_PLANE_TYPE_OVERLAY; - } - } - - if (win->type == DRM_PLANE_TYPE_OVERLAY) - possible_crtcs = (1 << nvps) - 1; - - ret = vop2_plane_init(vop2, win, possible_crtcs); - if (ret) { - drm_err(vop2->drm, "failed to init plane %s: %d\n", - win->data->name, ret); - return ret; - } - } - - for (i = 0; i < vop2_data->nr_vps; i++) { - vp = &vop2->vps[i]; - - if (!vp->crtc.port) - continue; - - plane = &vp->primary_plane->base; - - ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, - &vop2_crtc_funcs, - "video_port%d", vp->id); - if (ret) { - drm_err(vop2->drm, "crtc init for video_port%d failed\n", i); - return ret; - } - - drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); - - init_completion(&vp->dsp_hold_completion); - } - - /* - * On the VOP2 it's very hard to change the number of layers on a VP - * during runtime, so we distribute the layers equally over the used - * VPs - */ - for (i = 0; i < vop2->data->nr_vps; i++) { - struct vop2_video_port *vp = &vop2->vps[i]; - - if (vp->crtc.port) - vp->nlayers = NR_LAYERS / nvps; - } - - return 0; -} - -static void vop2_destroy_crtc(struct drm_crtc *crtc) -{ - of_node_put(crtc->port); - - /* - * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane() - * references the CRTC. - */ - drm_crtc_cleanup(crtc); -} - -static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { - [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), - [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), - [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14), - [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18), - [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31), - [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31), - [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31), - [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31), - [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31), - [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19), - [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15), - [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31), - [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8), - [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9), - [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11), - - /* Scale */ - [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15), - [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31), - [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15), - [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13), - [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3), - [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28), - [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29), - - /* cluster regs */ - [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1), - [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0), - [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7), - - /* afbc regs */ - [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6), - [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9), - [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10), - [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4), - [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7), - [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8), - [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31), - [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31), - [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15), - [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31), - [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31), - [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31), - [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31), - [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0), - [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1), - [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2), - [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3), - [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff }, - [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff }, - [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff }, - [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff }, - [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff }, - [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff }, - [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff }, -}; - -static int vop2_cluster_init(struct vop2_win *win) -{ - struct vop2 *vop2 = win->vop2; - struct reg_field *cluster_regs; - int ret, i; - - cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs), - GFP_KERNEL); - if (!cluster_regs) - return -ENOMEM; - - for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++) - if (cluster_regs[i].reg != 0xffffffff) - cluster_regs[i].reg += win->offset; - - ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, - cluster_regs, - ARRAY_SIZE(vop2_cluster_regs)); - - kfree(cluster_regs); - - return ret; -}; - -static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = { - [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0), - [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5), - [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12), - [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14), - [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16), - [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31), - [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31), - [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28), - [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31), - [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31), - [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17), - [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15), - [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31), - [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0), - [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1), - [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3), - [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31), - [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29), - [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31), - - /* Scale */ - [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15), - [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31), - [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15), - [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31), - [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1), - [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3), - [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5), - [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7), - [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9), - [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11), - [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13), - [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15), - [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17), - [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8), - [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9), - [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10), - [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11), - [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff }, - [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff }, - [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff }, - [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff }, -}; - -static int vop2_esmart_init(struct vop2_win *win) -{ - struct vop2 *vop2 = win->vop2; - struct reg_field *esmart_regs; - int ret, i; - - esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs), - GFP_KERNEL); - if (!esmart_regs) - return -ENOMEM; - - for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++) - if (esmart_regs[i].reg != 0xffffffff) - esmart_regs[i].reg += win->offset; - - ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, - esmart_regs, - ARRAY_SIZE(vop2_esmart_regs)); - - kfree(esmart_regs); - - return ret; -}; - -static int vop2_win_init(struct vop2 *vop2) -{ - const struct vop2_data *vop2_data = vop2->data; - struct vop2_win *win; - int i, ret; - - for (i = 0; i < vop2_data->win_size; i++) { - const struct vop2_win_data *win_data = &vop2_data->win[i]; - - win = &vop2->win[i]; - win->data = win_data; - win->type = win_data->type; - win->offset = win_data->base; - win->win_id = i; - win->vop2 = vop2; - if (vop2_cluster_window(win)) - ret = vop2_cluster_init(win); - else - ret = vop2_esmart_init(win); - if (ret) - return ret; - } - - vop2->registered_num_wins = vop2_data->win_size; - - return 0; -} - -/* - * The window registers are only updated when config done is written. - * Until that they read back the old value. As we read-modify-write - * these registers mark them as non-volatile. This makes sure we read - * the new values from the regmap register cache. - */ -static const struct regmap_range vop2_nonvolatile_range[] = { - regmap_reg_range(0x1000, 0x23ff), -}; - -static const struct regmap_access_table vop2_volatile_table = { - .no_ranges = vop2_nonvolatile_range, - .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range), -}; - -static const struct regmap_config vop2_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = 0x3000, - .name = "vop2", - .volatile_table = &vop2_volatile_table, - .cache_type = REGCACHE_RBTREE, -}; - -static int vop2_bind(struct device *dev, struct device *master, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - const struct vop2_data *vop2_data; - struct drm_device *drm = data; - struct vop2 *vop2; - struct resource *res; - size_t alloc_size; - int ret; - - vop2_data = of_device_get_match_data(dev); - if (!vop2_data) - return -ENODEV; - - /* Allocate vop2 struct and its vop2_win array */ - alloc_size = sizeof(*vop2) + sizeof(*vop2->win) * vop2_data->win_size; - vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL); - if (!vop2) - return -ENOMEM; - - vop2->dev = dev; - vop2->data = vop2_data; - vop2->drm = drm; - - dev_set_drvdata(dev, vop2); - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); - if (!res) { - drm_err(vop2->drm, "failed to get vop2 register byname\n"); - return -EINVAL; - } - - vop2->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(vop2->regs)) - return PTR_ERR(vop2->regs); - vop2->len = resource_size(res); - - vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config); - - ret = vop2_win_init(vop2); - if (ret) - return ret; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut"); - if (res) { - vop2->lut_regs = devm_ioremap_resource(dev, res); - if (IS_ERR(vop2->lut_regs)) - return PTR_ERR(vop2->lut_regs); - } - - vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); - - vop2->hclk = devm_clk_get(vop2->dev, "hclk"); - if (IS_ERR(vop2->hclk)) { - drm_err(vop2->drm, "failed to get hclk source\n"); - return PTR_ERR(vop2->hclk); - } - - vop2->aclk = devm_clk_get(vop2->dev, "aclk"); - if (IS_ERR(vop2->aclk)) { - drm_err(vop2->drm, "failed to get aclk source\n"); - return PTR_ERR(vop2->aclk); - } - - vop2->irq = platform_get_irq(pdev, 0); - if (vop2->irq < 0) { - drm_err(vop2->drm, "cannot find irq for vop2\n"); - return vop2->irq; - } - - mutex_init(&vop2->vop2_lock); - - ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2); - if (ret) - return ret; - - ret = vop2_create_crtc(vop2); - if (ret) - return ret; - - rockchip_drm_dma_init_device(vop2->drm, vop2->dev); - - pm_runtime_enable(&pdev->dev); - - return 0; -} - -static void vop2_unbind(struct device *dev, struct device *master, void *data) -{ - struct vop2 *vop2 = dev_get_drvdata(dev); - struct drm_device *drm = vop2->drm; - struct list_head *plane_list = &drm->mode_config.plane_list; - struct list_head *crtc_list = &drm->mode_config.crtc_list; - struct drm_crtc *crtc, *tmpc; - struct drm_plane *plane, *tmpp; - - pm_runtime_disable(dev); - - list_for_each_entry_safe(plane, tmpp, plane_list, head) - drm_plane_cleanup(plane); - - list_for_each_entry_safe(crtc, tmpc, crtc_list, head) - vop2_destroy_crtc(crtc); -} - -const struct component_ops vop2_component_ops = { - .bind = vop2_bind, - .unbind = vop2_unbind, -}; -EXPORT_SYMBOL_GPL(vop2_component_ops); diff --git a/target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h deleted file mode 100644 index c727093a0..000000000 --- a/target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ /dev/null @@ -1,477 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd - * Author:Mark Yao - */ - -#ifndef _ROCKCHIP_DRM_VOP2_H -#define _ROCKCHIP_DRM_VOP2_H - -#include "rockchip_drm_vop.h" - -#include -#include - -#define VOP_FEATURE_OUTPUT_10BIT BIT(0) - -#define WIN_FEATURE_AFBDC BIT(0) -#define WIN_FEATURE_CLUSTER BIT(1) - -/* - * the delay number of a window in different mode. - */ -enum win_dly_mode { - VOP2_DLY_MODE_DEFAULT, /**< default mode */ - VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */ - VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */ - VOP2_DLY_MODE_MAX, -}; - -struct vop_rect { - int width; - int height; -}; - -enum vop2_scale_up_mode { - VOP2_SCALE_UP_NRST_NBOR, - VOP2_SCALE_UP_BIL, - VOP2_SCALE_UP_BIC, -}; - -enum vop2_scale_down_mode { - VOP2_SCALE_DOWN_NRST_NBOR, - VOP2_SCALE_DOWN_BIL, - VOP2_SCALE_DOWN_AVG, -}; - -enum vop2_win_regs { - VOP2_WIN_ENABLE, - VOP2_WIN_FORMAT, - VOP2_WIN_CSC_MODE, - VOP2_WIN_XMIRROR, - VOP2_WIN_YMIRROR, - VOP2_WIN_RB_SWAP, - VOP2_WIN_UV_SWAP, - VOP2_WIN_ACT_INFO, - VOP2_WIN_DSP_INFO, - VOP2_WIN_DSP_ST, - VOP2_WIN_YRGB_MST, - VOP2_WIN_UV_MST, - VOP2_WIN_YRGB_VIR, - VOP2_WIN_UV_VIR, - VOP2_WIN_YUV_CLIP, - VOP2_WIN_Y2R_EN, - VOP2_WIN_R2Y_EN, - VOP2_WIN_COLOR_KEY, - VOP2_WIN_COLOR_KEY_EN, - VOP2_WIN_DITHER_UP, - - /* scale regs */ - VOP2_WIN_SCALE_YRGB_X, - VOP2_WIN_SCALE_YRGB_Y, - VOP2_WIN_SCALE_CBCR_X, - VOP2_WIN_SCALE_CBCR_Y, - VOP2_WIN_YRGB_HOR_SCL_MODE, - VOP2_WIN_YRGB_HSCL_FILTER_MODE, - VOP2_WIN_YRGB_VER_SCL_MODE, - VOP2_WIN_YRGB_VSCL_FILTER_MODE, - VOP2_WIN_CBCR_VER_SCL_MODE, - VOP2_WIN_CBCR_HSCL_FILTER_MODE, - VOP2_WIN_CBCR_HOR_SCL_MODE, - VOP2_WIN_CBCR_VSCL_FILTER_MODE, - VOP2_WIN_VSD_CBCR_GT2, - VOP2_WIN_VSD_CBCR_GT4, - VOP2_WIN_VSD_YRGB_GT2, - VOP2_WIN_VSD_YRGB_GT4, - VOP2_WIN_BIC_COE_SEL, - - /* cluster regs */ - VOP2_WIN_CLUSTER_ENABLE, - VOP2_WIN_AFBC_ENABLE, - VOP2_WIN_CLUSTER_LB_MODE, - - /* afbc regs */ - VOP2_WIN_AFBC_FORMAT, - VOP2_WIN_AFBC_RB_SWAP, - VOP2_WIN_AFBC_UV_SWAP, - VOP2_WIN_AFBC_AUTO_GATING_EN, - VOP2_WIN_AFBC_BLOCK_SPLIT_EN, - VOP2_WIN_AFBC_PIC_VIR_WIDTH, - VOP2_WIN_AFBC_TILE_NUM, - VOP2_WIN_AFBC_PIC_OFFSET, - VOP2_WIN_AFBC_PIC_SIZE, - VOP2_WIN_AFBC_DSP_OFFSET, - VOP2_WIN_AFBC_TRANSFORM_OFFSET, - VOP2_WIN_AFBC_HDR_PTR, - VOP2_WIN_AFBC_HALF_BLOCK_EN, - VOP2_WIN_AFBC_ROTATE_270, - VOP2_WIN_AFBC_ROTATE_90, - VOP2_WIN_MAX_REG, -}; - -struct vop2_win_data { - const char *name; - unsigned int phys_id; - - u32 base; - enum drm_plane_type type; - - u32 nformats; - const u32 *formats; - const uint64_t *format_modifiers; - const unsigned int supported_rotations; - - /** - * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 - */ - unsigned int layer_sel_id; - uint64_t feature; - - unsigned int max_upscale_factor; - unsigned int max_downscale_factor; - const u8 dly[VOP2_DLY_MODE_MAX]; -}; - -struct vop2_video_port_data { - unsigned int id; - u32 feature; - u16 gamma_lut_len; - u16 cubic_lut_len; - struct vop_rect max_output; - const u8 pre_scan_max_dly[4]; - const struct vop2_video_port_regs *regs; - unsigned int offset; -}; - -struct vop2_data { - u8 nr_vps; - const struct vop2_ctrl *ctrl; - const struct vop2_win_data *win; - const struct vop2_video_port_data *vp; - const struct vop_csc_table *csc_table; - struct vop_rect max_input; - struct vop_rect max_output; - - unsigned int win_size; - unsigned int soc_id; -}; - -/* interrupt define */ -#define FS_NEW_INTR BIT(4) -#define ADDR_SAME_INTR BIT(5) -#define LINE_FLAG1_INTR BIT(6) -#define WIN0_EMPTY_INTR BIT(7) -#define WIN1_EMPTY_INTR BIT(8) -#define WIN2_EMPTY_INTR BIT(9) -#define WIN3_EMPTY_INTR BIT(10) -#define HWC_EMPTY_INTR BIT(11) -#define POST_BUF_EMPTY_INTR BIT(12) -#define PWM_GEN_INTR BIT(13) -#define DMA_FINISH_INTR BIT(14) -#define FS_FIELD_INTR BIT(15) -#define FE_INTR BIT(16) -#define WB_UV_FIFO_FULL_INTR BIT(17) -#define WB_YRGB_FIFO_FULL_INTR BIT(18) -#define WB_COMPLETE_INTR BIT(19) - -/* - * display output interface supported by rockchip lcdc - */ -#define ROCKCHIP_OUT_MODE_P888 0 -#define ROCKCHIP_OUT_MODE_BT1120 0 -#define ROCKCHIP_OUT_MODE_P666 1 -#define ROCKCHIP_OUT_MODE_P565 2 -#define ROCKCHIP_OUT_MODE_BT656 5 -#define ROCKCHIP_OUT_MODE_S888 8 -#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 -#define ROCKCHIP_OUT_MODE_YUV420 14 -/* for use special outface */ -#define ROCKCHIP_OUT_MODE_AAAA 15 - -enum vop_csc_format { - CSC_BT601L, - CSC_BT709L, - CSC_BT601F, - CSC_BT2020, -}; - -enum src_factor_mode { - SRC_FAC_ALPHA_ZERO, - SRC_FAC_ALPHA_ONE, - SRC_FAC_ALPHA_DST, - SRC_FAC_ALPHA_DST_INVERSE, - SRC_FAC_ALPHA_SRC, - SRC_FAC_ALPHA_SRC_GLOBAL, -}; - -enum dst_factor_mode { - DST_FAC_ALPHA_ZERO, - DST_FAC_ALPHA_ONE, - DST_FAC_ALPHA_SRC, - DST_FAC_ALPHA_SRC_INVERSE, - DST_FAC_ALPHA_DST, - DST_FAC_ALPHA_DST_GLOBAL, -}; - -#define RK3568_GRF_VO_CON1 0x0364 -/* System registers definition */ -#define RK3568_REG_CFG_DONE 0x000 -#define RK3568_VERSION_INFO 0x004 -#define RK3568_SYS_AUTO_GATING_CTRL 0x008 -#define RK3568_SYS_AXI_LUT_CTRL 0x024 -#define RK3568_DSP_IF_EN 0x028 -#define RK3568_DSP_IF_CTRL 0x02c -#define RK3568_DSP_IF_POL 0x030 -#define RK3568_WB_CTRL 0x40 -#define RK3568_WB_XSCAL_FACTOR 0x44 -#define RK3568_WB_YRGB_MST 0x48 -#define RK3568_WB_CBR_MST 0x4C -#define RK3568_OTP_WIN_EN 0x050 -#define RK3568_LUT_PORT_SEL 0x058 -#define RK3568_SYS_STATUS0 0x060 -#define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4) -#define RK3568_SYS0_INT_EN 0x80 -#define RK3568_SYS0_INT_CLR 0x84 -#define RK3568_SYS0_INT_STATUS 0x88 -#define RK3568_SYS1_INT_EN 0x90 -#define RK3568_SYS1_INT_CLR 0x94 -#define RK3568_SYS1_INT_STATUS 0x98 -#define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10) -#define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10) -#define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10) -#define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) - -/* Video Port registers definition */ -#define RK3568_VP_DSP_CTRL 0x00 -#define RK3568_VP_MIPI_CTRL 0x04 -#define RK3568_VP_COLOR_BAR_CTRL 0x08 -#define RK3568_VP_3D_LUT_CTRL 0x10 -#define RK3568_VP_3D_LUT_MST 0x20 -#define RK3568_VP_DSP_BG 0x2C -#define RK3568_VP_PRE_SCAN_HTIMING 0x30 -#define RK3568_VP_POST_DSP_HACT_INFO 0x34 -#define RK3568_VP_POST_DSP_VACT_INFO 0x38 -#define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C -#define RK3568_VP_POST_SCL_CTRL 0x40 -#define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44 -#define RK3568_VP_DSP_HTOTAL_HS_END 0x48 -#define RK3568_VP_DSP_HACT_ST_END 0x4C -#define RK3568_VP_DSP_VTOTAL_VS_END 0x50 -#define RK3568_VP_DSP_VACT_ST_END 0x54 -#define RK3568_VP_DSP_VS_ST_END_F1 0x58 -#define RK3568_VP_DSP_VACT_ST_END_F1 0x5C -#define RK3568_VP_BCSH_CTRL 0x60 -#define RK3568_VP_BCSH_BCS 0x64 -#define RK3568_VP_BCSH_H 0x68 -#define RK3568_VP_BCSH_COLOR_BAR 0x6C - -/* Overlay registers definition */ -#define RK3568_OVL_CTRL 0x600 -#define RK3568_OVL_LAYER_SEL 0x604 -#define RK3568_OVL_PORT_SEL 0x608 -#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 -#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 -#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 -#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C -#define RK3568_MIX0_SRC_COLOR_CTRL 0x650 -#define RK3568_MIX0_DST_COLOR_CTRL 0x654 -#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 -#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C -#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 -#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 -#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 -#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC -#define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4) -#define RK3568_CLUSTER_DLY_NUM 0x6F0 -#define RK3568_SMART_DLY_NUM 0x6F8 - -/* Cluster register definition, offset relative to window base */ -#define RK3568_CLUSTER_WIN_CTRL0 0x00 -#define RK3568_CLUSTER_WIN_CTRL1 0x04 -#define RK3568_CLUSTER_WIN_YRGB_MST 0x10 -#define RK3568_CLUSTER_WIN_CBR_MST 0x14 -#define RK3568_CLUSTER_WIN_VIR 0x18 -#define RK3568_CLUSTER_WIN_ACT_INFO 0x20 -#define RK3568_CLUSTER_WIN_DSP_INFO 0x24 -#define RK3568_CLUSTER_WIN_DSP_ST 0x28 -#define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30 -#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C -#define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50 -#define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54 -#define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58 -#define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C -#define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60 -#define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64 -#define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68 -#define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C - -#define RK3568_CLUSTER_CTRL 0x100 - -/* (E)smart register definition, offset relative to window base */ -#define RK3568_SMART_CTRL0 0x00 -#define RK3568_SMART_CTRL1 0x04 -#define RK3568_SMART_REGION0_CTRL 0x10 -#define RK3568_SMART_REGION0_YRGB_MST 0x14 -#define RK3568_SMART_REGION0_CBR_MST 0x18 -#define RK3568_SMART_REGION0_VIR 0x1C -#define RK3568_SMART_REGION0_ACT_INFO 0x20 -#define RK3568_SMART_REGION0_DSP_INFO 0x24 -#define RK3568_SMART_REGION0_DSP_ST 0x28 -#define RK3568_SMART_REGION0_SCL_CTRL 0x30 -#define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34 -#define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38 -#define RK3568_SMART_REGION0_SCL_OFFSET 0x3C -#define RK3568_SMART_REGION1_CTRL 0x40 -#define RK3568_SMART_REGION1_YRGB_MST 0x44 -#define RK3568_SMART_REGION1_CBR_MST 0x48 -#define RK3568_SMART_REGION1_VIR 0x4C -#define RK3568_SMART_REGION1_ACT_INFO 0x50 -#define RK3568_SMART_REGION1_DSP_INFO 0x54 -#define RK3568_SMART_REGION1_DSP_ST 0x58 -#define RK3568_SMART_REGION1_SCL_CTRL 0x60 -#define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64 -#define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68 -#define RK3568_SMART_REGION1_SCL_OFFSET 0x6C -#define RK3568_SMART_REGION2_CTRL 0x70 -#define RK3568_SMART_REGION2_YRGB_MST 0x74 -#define RK3568_SMART_REGION2_CBR_MST 0x78 -#define RK3568_SMART_REGION2_VIR 0x7C -#define RK3568_SMART_REGION2_ACT_INFO 0x80 -#define RK3568_SMART_REGION2_DSP_INFO 0x84 -#define RK3568_SMART_REGION2_DSP_ST 0x88 -#define RK3568_SMART_REGION2_SCL_CTRL 0x90 -#define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94 -#define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98 -#define RK3568_SMART_REGION2_SCL_OFFSET 0x9C -#define RK3568_SMART_REGION3_CTRL 0xA0 -#define RK3568_SMART_REGION3_YRGB_MST 0xA4 -#define RK3568_SMART_REGION3_CBR_MST 0xA8 -#define RK3568_SMART_REGION3_VIR 0xAC -#define RK3568_SMART_REGION3_ACT_INFO 0xB0 -#define RK3568_SMART_REGION3_DSP_INFO 0xB4 -#define RK3568_SMART_REGION3_DSP_ST 0xB8 -#define RK3568_SMART_REGION3_SCL_CTRL 0xC0 -#define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4 -#define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8 -#define RK3568_SMART_REGION3_SCL_OFFSET 0xCC -#define RK3568_SMART_COLOR_KEY_CTRL 0xD0 - -/* HDR register definition */ -#define RK3568_HDR_LUT_CTRL 0x2000 -#define RK3568_HDR_LUT_MST 0x2004 -#define RK3568_SDR2HDR_CTRL 0x2010 -#define RK3568_HDR2SDR_CTRL 0x2020 -#define RK3568_HDR2SDR_SRC_RANGE 0x2024 -#define RK3568_HDR2SDR_NORMFACEETF 0x2028 -#define RK3568_HDR2SDR_DST_RANGE 0x202C -#define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030 -#define RK3568_HDR_EETF_OETF_Y0 0x203C -#define RK3568_HDR_SAT_Y0 0x20C0 -#define RK3568_HDR_EOTF_OETF_Y0 0x20F0 -#define RK3568_HDR_OETF_DX_POW1 0x2200 -#define RK3568_HDR_OETF_XN1 0x2300 - -#define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15) - -#define RK3568_VP_DSP_CTRL__STANDBY BIT(31) -#define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20) -#define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18) -#define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17) -#define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16) -#define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15) -#define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9) -#define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7) -#define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6) -#define RK3568_VP_DSP_CTRL__P2I_EN BIT(5) -#define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4) -#define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0) - -#define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) -#define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) - -#define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25) -#define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24) -#define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) -#define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20) -#define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18) -#define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16) -#define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14) -#define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10) -#define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8) -#define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5) -#define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4) -#define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3) -#define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1) -#define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0) - -#define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16) -#define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12) -#define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4) -#define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0) - -#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5) -#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4) - -#define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31) - -#define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28) - -#define VOP2_SYS_AXI_BUS_NUM 2 - -#define VOP2_CLUSTER_YUV444_10 0x12 - -#define VOP2_COLOR_KEY_MASK BIT(31) - -#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28) - -#define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) - -#define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16) -#define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30) -#define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28) -#define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26) -#define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24) -#define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18) -#define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16) -#define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8) -#define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4) -#define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0) -#define RK3568_OVL_LAYER_SEL__LAYER(layer, x) ((x) << ((layer) * 4)) - -#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24) -#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16) -#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8) -#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0) - -#define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24) -#define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16) -#define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8) -#define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0) - -#define VP_INT_DSP_HOLD_VALID BIT(6) -#define VP_INT_FS_FIELD BIT(5) -#define VP_INT_POST_BUF_EMPTY BIT(4) -#define VP_INT_LINE_FLAG1 BIT(3) -#define VP_INT_LINE_FLAG0 BIT(2) -#define VOP2_INT_BUS_ERRPR BIT(1) -#define VP_INT_FS BIT(0) - -#define POLFLAG_DCLK_INV BIT(3) - -enum vop2_layer_phy_id { - ROCKCHIP_VOP2_CLUSTER0 = 0, - ROCKCHIP_VOP2_CLUSTER1, - ROCKCHIP_VOP2_ESMART0, - ROCKCHIP_VOP2_ESMART1, - ROCKCHIP_VOP2_SMART0, - ROCKCHIP_VOP2_SMART1, - ROCKCHIP_VOP2_CLUSTER2, - ROCKCHIP_VOP2_CLUSTER3, - ROCKCHIP_VOP2_ESMART2, - ROCKCHIP_VOP2_ESMART3, - ROCKCHIP_VOP2_PHY_ID_INVALID = -1, -}; - -extern const struct component_ops vop2_component_ops; - -#endif /* _ROCKCHIP_DRM_VOP2_H */ diff --git a/target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c deleted file mode 100644 index 9bf0637bf..000000000 --- a/target/linux/rockchip/files-5.10/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ /dev/null @@ -1,281 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) Rockchip Electronics Co.Ltd - * Author: Andy Yan - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rockchip_drm_vop2.h" - -static const uint32_t formats_win_full_10bit[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_XBGR8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_BGR888, - DRM_FORMAT_RGB565, - DRM_FORMAT_BGR565, - DRM_FORMAT_NV12, - DRM_FORMAT_NV16, - DRM_FORMAT_NV24, -}; - -static const uint32_t formats_win_full_10bit_yuyv[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_XBGR8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_BGR888, - DRM_FORMAT_RGB565, - DRM_FORMAT_BGR565, - DRM_FORMAT_NV12, - DRM_FORMAT_NV16, - DRM_FORMAT_NV24, - DRM_FORMAT_YVYU, - DRM_FORMAT_VYUY, -}; - -static const uint32_t formats_win_lite[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_XBGR8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_BGR888, - DRM_FORMAT_RGB565, - DRM_FORMAT_BGR565, -}; - -static const uint64_t format_modifiers[] = { - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID, -}; - -static const uint64_t format_modifiers_afbc[] = { - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_SPARSE), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_CBR), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR | - AFBC_FORMAT_MOD_SPARSE), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_CBR | - AFBC_FORMAT_MOD_SPARSE), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR | - AFBC_FORMAT_MOD_CBR), - - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR | - AFBC_FORMAT_MOD_CBR | - AFBC_FORMAT_MOD_SPARSE), - - /* SPLIT mandates SPARSE, RGB modes mandates YTR */ - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | - AFBC_FORMAT_MOD_YTR | - AFBC_FORMAT_MOD_SPARSE | - AFBC_FORMAT_MOD_SPLIT), - DRM_FORMAT_MOD_INVALID, -}; - -static const struct vop2_video_port_data rk3568_vop_video_ports[] = { - { - .id = 0, - .feature = VOP_FEATURE_OUTPUT_10BIT, - .gamma_lut_len = 1024, - .cubic_lut_len = 9 * 9 * 9, - .max_output = { 4096, 2304 }, - .pre_scan_max_dly = { 69, 53, 53, 42 }, - .offset = 0xc00, - }, { - .id = 1, - .gamma_lut_len = 1024, - .max_output = { 2048, 1536 }, - .pre_scan_max_dly = { 40, 40, 40, 40 }, - .offset = 0xd00, - }, { - .id = 2, - .gamma_lut_len = 1024, - .max_output = { 1920, 1080 }, - .pre_scan_max_dly = { 40, 40, 40, 40 }, - .offset = 0xe00, - }, -}; - -/* - * rk3568 vop with 2 cluster, 2 esmart win, 2 smart win. - * Every cluster can work as 4K win or split into two win. - * All win in cluster support AFBCD. - * - * Every esmart win and smart win support 4 Multi-region. - * - * Scale filter mode: - * - * * Cluster: bicubic for horizontal scale up, others use bilinear - * * ESmart: - * * nearest-neighbor/bilinear/bicubic for scale up - * * nearest-neighbor/bilinear/average for scale down - * - * - * @TODO describe the wind like cpu-map dt nodes; - */ -static const struct vop2_win_data rk3568_vop_win_data[] = { - { - .name = "Smart0-win0", - .phys_id = ROCKCHIP_VOP2_SMART0, - .base = 0x1c00, - .formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .format_modifiers = format_modifiers, - .layer_sel_id = 3, - .supported_rotations = DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_PRIMARY, - .max_upscale_factor = 8, - .max_downscale_factor = 8, - .dly = { 20, 47, 41 }, - }, { - .name = "Smart1-win0", - .phys_id = ROCKCHIP_VOP2_SMART1, - .formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .format_modifiers = format_modifiers, - .base = 0x1e00, - .layer_sel_id = 7, - .supported_rotations = DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_PRIMARY, - .max_upscale_factor = 8, - .max_downscale_factor = 8, - .dly = { 20, 47, 41 }, - }, { - .name = "Esmart1-win0", - .phys_id = ROCKCHIP_VOP2_ESMART1, - .formats = formats_win_full_10bit_yuyv, - .nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv), - .format_modifiers = format_modifiers, - .base = 0x1a00, - .layer_sel_id = 6, - .supported_rotations = DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_PRIMARY, - .max_upscale_factor = 8, - .max_downscale_factor = 8, - .dly = { 20, 47, 41 }, - }, { - .name = "Esmart0-win0", - .phys_id = ROCKCHIP_VOP2_ESMART0, - .formats = formats_win_full_10bit_yuyv, - .nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv), - .format_modifiers = format_modifiers, - .base = 0x1800, - .layer_sel_id = 2, - .supported_rotations = DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_OVERLAY, - .max_upscale_factor = 8, - .max_downscale_factor = 8, - .dly = { 20, 47, 41 }, - }, { - .name = "Cluster0-win0", - .phys_id = ROCKCHIP_VOP2_CLUSTER0, - .base = 0x1000, - .formats = formats_win_full_10bit, - .nformats = ARRAY_SIZE(formats_win_full_10bit), - .format_modifiers = format_modifiers_afbc, - .layer_sel_id = 0, - .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | - DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, - .max_upscale_factor = 4, - .max_downscale_factor = 4, - .dly = { 0, 27, 21 }, - .type = DRM_PLANE_TYPE_OVERLAY, - .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, - }, { - .name = "Cluster1-win0", - .phys_id = ROCKCHIP_VOP2_CLUSTER1, - .base = 0x1200, - .formats = formats_win_full_10bit, - .nformats = ARRAY_SIZE(formats_win_full_10bit), - .format_modifiers = format_modifiers_afbc, - .layer_sel_id = 1, - .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | - DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, - .type = DRM_PLANE_TYPE_OVERLAY, - .max_upscale_factor = 4, - .max_downscale_factor = 4, - .dly = { 0, 27, 21 }, - .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, - }, -}; - -static const struct vop2_data rk3566_vop = { - .nr_vps = 3, - .max_input = { 4096, 2304 }, - .max_output = { 4096, 2304 }, - .vp = rk3568_vop_video_ports, - .win = rk3568_vop_win_data, - .win_size = ARRAY_SIZE(rk3568_vop_win_data), - .soc_id = 3566, -}; - -static const struct vop2_data rk3568_vop = { - .nr_vps = 3, - .max_input = { 4096, 2304 }, - .max_output = { 4096, 2304 }, - .vp = rk3568_vop_video_ports, - .win = rk3568_vop_win_data, - .win_size = ARRAY_SIZE(rk3568_vop_win_data), - .soc_id = 3568, -}; - -static const struct of_device_id vop2_dt_match[] = { - { - .compatible = "rockchip,rk3566-vop", - .data = &rk3566_vop, - }, { - .compatible = "rockchip,rk3568-vop", - .data = &rk3568_vop, - }, { - }, -}; -MODULE_DEVICE_TABLE(of, vop2_dt_match); - -static int vop2_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - - return component_add(dev, &vop2_component_ops); -} - -static int vop2_remove(struct platform_device *pdev) -{ - component_del(&pdev->dev, &vop2_component_ops); - - return 0; -} - -struct platform_driver vop2_platform_driver = { - .probe = vop2_probe, - .remove = vop2_remove, - .driver = { - .name = "rockchip-vop2", - .of_match_table = of_match_ptr(vop2_dt_match), - }, -}; diff --git a/target/linux/rockchip/files-5.10/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/target/linux/rockchip/files-5.10/drivers/pci/controller/dwc/pcie-dw-rockchip.c deleted file mode 100644 index c9b341e55..000000000 --- a/target/linux/rockchip/files-5.10/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ /dev/null @@ -1,279 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * PCIe host controller driver for Rockchip SoCs. - * - * Copyright (C) 2021 Rockchip Electronics Co., Ltd. - * http://www.rock-chips.com - * - * Author: Simon Xue - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pcie-designware.h" - -/* - * The upper 16 bits of PCIE_CLIENT_CONFIG are a write - * mask for the lower 16 bits. - */ -#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) -#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) - -#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) - -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) -#define PCIE_SMLH_LINKUP BIT(16) -#define PCIE_RDLH_LINKUP BIT(17) -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) -#define PCIE_L0S_ENTRY 0x11 -#define PCIE_CLIENT_GENERAL_CONTROL 0x0 -#define PCIE_CLIENT_GENERAL_DEBUG 0x104 -#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 -#define PCIE_CLIENT_LTSSM_STATUS 0x300 -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) -#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) - -struct rockchip_pcie { - struct dw_pcie pci; - void __iomem *apb_base; - struct phy *phy; - struct clk_bulk_data *clks; - unsigned int clk_cnt; - struct reset_control *rst; - struct gpio_desc *rst_gpio; - struct regulator *vpcie3v3; -}; - -static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, - u32 reg) -{ - return readl_relaxed(rockchip->apb_base + reg); -} - -static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, - u32 val, u32 reg) -{ - writel_relaxed(val, rockchip->apb_base + reg); -} - -static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) -{ - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, - PCIE_CLIENT_GENERAL_CONTROL); -} - -static int rockchip_pcie_link_up(struct dw_pcie *pci) -{ - struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); - u32 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS); - - if ((val & PCIE_LINKUP) == PCIE_LINKUP && - (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY) - return 1; - - return 0; -} - -static int rockchip_pcie_start_link(struct dw_pcie *pci) -{ - struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); - - /* Reset device */ - gpiod_set_value_cansleep(rockchip->rst_gpio, 0); - - rockchip_pcie_enable_ltssm(rockchip); - - /* - * PCIe requires the refclk to be stable for 100µs prior to releasing - * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI - * Express Card Electromechanical Specification, 1.1. However, we don't - * know if the refclk is coming from RC's PHY or external OSC. If it's - * from RC, so enabling LTSSM is the just right place to release #PERST. - * We need more extra time as before, rather than setting just - * 100us as we don't know how long should the device need to reset. - */ - msleep(100); - gpiod_set_value_cansleep(rockchip->rst_gpio, 1); - - return 0; -} - -static int rockchip_pcie_host_init(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); - u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); - - /* LTSSM enable control mode */ - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); - - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, - PCIE_CLIENT_GENERAL_CONTROL); - - return 0; -} - -static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { - .host_init = rockchip_pcie_host_init, -}; - -static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip) -{ - struct device *dev = rockchip->pci.dev; - int ret; - - ret = devm_clk_bulk_get_all(dev, &rockchip->clks); - if (ret < 0) - return ret; - - rockchip->clk_cnt = ret; - - return clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks); -} - -static int rockchip_pcie_resource_get(struct platform_device *pdev, - struct rockchip_pcie *rockchip) -{ - rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); - if (IS_ERR(rockchip->apb_base)) - return PTR_ERR(rockchip->apb_base); - - rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", - GPIOD_OUT_HIGH); - if (IS_ERR(rockchip->rst_gpio)) - return PTR_ERR(rockchip->rst_gpio); - - return 0; -} - -static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip) -{ - struct device *dev = rockchip->pci.dev; - int ret; - - rockchip->phy = devm_phy_get(dev, "pcie-phy"); - if (IS_ERR(rockchip->phy)) - return dev_err_probe(dev, PTR_ERR(rockchip->phy), - "missing PHY\n"); - - ret = phy_init(rockchip->phy); - if (ret < 0) - return ret; - - ret = phy_power_on(rockchip->phy); - if (ret) - phy_exit(rockchip->phy); - - return ret; -} - -static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip) -{ - phy_exit(rockchip->phy); - phy_power_off(rockchip->phy); -} - -static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip) -{ - struct device *dev = rockchip->pci.dev; - - rockchip->rst = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(rockchip->rst)) - return dev_err_probe(dev, PTR_ERR(rockchip->rst), - "failed to get reset lines\n"); - - return reset_control_deassert(rockchip->rst); -} - -static const struct dw_pcie_ops dw_pcie_ops = { - .link_up = rockchip_pcie_link_up, - .start_link = rockchip_pcie_start_link, -}; - -static int rockchip_pcie_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct rockchip_pcie *rockchip; - struct pcie_port *pp; - int ret; - - rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL); - if (!rockchip) - return -ENOMEM; - - platform_set_drvdata(pdev, rockchip); - - rockchip->pci.dev = dev; - rockchip->pci.ops = &dw_pcie_ops; - - pp = &rockchip->pci.pp; - pp->ops = &rockchip_pcie_host_ops; - - ret = rockchip_pcie_resource_get(pdev, rockchip); - if (ret) - return ret; - - /* DON'T MOVE ME: must be enable before PHY init */ - rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); - if (IS_ERR(rockchip->vpcie3v3)) { - if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV) - return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3), - "failed to get vpcie3v3 regulator\n"); - rockchip->vpcie3v3 = NULL; - } else { - ret = regulator_enable(rockchip->vpcie3v3); - if (ret) { - dev_err(dev, "failed to enable vpcie3v3 regulator\n"); - return ret; - } - } - - ret = rockchip_pcie_phy_init(rockchip); - if (ret) - goto disable_regulator; - - ret = rockchip_pcie_reset_control_release(rockchip); - if (ret) - goto deinit_phy; - - ret = rockchip_pcie_clk_init(rockchip); - if (ret) - goto deinit_phy; - - ret = dw_pcie_host_init(pp); - if (!ret) - return 0; - - clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); -deinit_phy: - rockchip_pcie_phy_deinit(rockchip); -disable_regulator: - if (rockchip->vpcie3v3) - regulator_disable(rockchip->vpcie3v3); - - return ret; -} - -static const struct of_device_id rockchip_pcie_of_match[] = { - { .compatible = "rockchip,rk3568-pcie", }, - {}, -}; - -static struct platform_driver rockchip_pcie_driver = { - .driver = { - .name = "rockchip-dw-pcie", - .of_match_table = rockchip_pcie_of_match, - .suppress_bind_attrs = true, - }, - .probe = rockchip_pcie_probe, -}; -builtin_platform_driver(rockchip_pcie_driver); diff --git a/target/linux/rockchip/files-5.10/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/target/linux/rockchip/files-5.10/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c deleted file mode 100644 index 7b213825f..000000000 --- a/target/linux/rockchip/files-5.10/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ /dev/null @@ -1,581 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver - * - * Copyright (C) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define BIT_WRITEABLE_SHIFT 16 -#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) -#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) -#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) - -/* COMBO PHY REG */ -#define PHYREG6 0x14 -#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6) -#define PHYREG6_PLL_DIV_SHIFT 6 -#define PHYREG6_PLL_DIV_2 1 - -#define PHYREG7 0x18 -#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4) -#define PHYREG7_TX_RTERM_SHIFT 4 -#define PHYREG7_TX_RTERM_50OHM 8 -#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0) -#define PHYREG7_RX_RTERM_SHIFT 0 -#define PHYREG7_RX_RTERM_44OHM 15 - -#define PHYREG8 0x1C -#define PHYREG8_SSC_EN BIT(4) - -#define PHYREG11 0x28 -#define PHYREG11_SU_TRIM_0_7 0xF0 - -#define PHYREG12 0x2C -#define PHYREG12_PLL_LPF_ADJ_VALUE 4 - -#define PHYREG13 0x30 -#define PHYREG13_RESISTER_MASK GENMASK(5, 4) -#define PHYREG13_RESISTER_SHIFT 0x4 -#define PHYREG13_RESISTER_HIGH_Z 3 -#define PHYREG13_CKRCV_AMP0 BIT(7) - -#define PHYREG14 0x34 -#define PHYREG14_CKRCV_AMP1 BIT(0) - -#define PHYREG15 0x38 -#define PHYREG15_CTLE_EN BIT(0) -#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6) -#define PHYREG15_SSC_CNT_SHIFT 6 -#define PHYREG15_SSC_CNT_VALUE 1 - -#define PHYREG16 0x3C -#define PHYREG16_SSC_CNT_VALUE 0x5f - -#define PHYREG18 0x44 -#define PHYREG18_PLL_LOOP 0x32 - -#define PHYREG32 0x7C -#define PHYREG32_SSC_MASK GENMASK(7, 4) -#define PHYREG32_SSC_DIR_SHIFT 4 -#define PHYREG32_SSC_UPWARD 0 -#define PHYREG32_SSC_DOWNWARD 1 -#define PHYREG32_SSC_OFFSET_SHIFT 6 -#define PHYREG32_SSC_OFFSET_500PPM 1 - -#define PHYREG33 0x80 -#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) -#define PHYREG33_PLL_KVCO_SHIFT 2 -#define PHYREG33_PLL_KVCO_VALUE 2 - -struct rockchip_combphy_priv; - -struct combphy_reg { - u16 offset; - u16 bitend; - u16 bitstart; - u16 disable; - u16 enable; -}; - -struct rockchip_combphy_grfcfg { - struct combphy_reg pcie_mode_set; - struct combphy_reg usb_mode_set; - struct combphy_reg sgmii_mode_set; - struct combphy_reg qsgmii_mode_set; - struct combphy_reg pipe_rxterm_set; - struct combphy_reg pipe_txelec_set; - struct combphy_reg pipe_txcomp_set; - struct combphy_reg pipe_clk_25m; - struct combphy_reg pipe_clk_100m; - struct combphy_reg pipe_phymode_sel; - struct combphy_reg pipe_rate_sel; - struct combphy_reg pipe_rxterm_sel; - struct combphy_reg pipe_txelec_sel; - struct combphy_reg pipe_txcomp_sel; - struct combphy_reg pipe_clk_ext; - struct combphy_reg pipe_sel_usb; - struct combphy_reg pipe_sel_qsgmii; - struct combphy_reg pipe_phy_status; - struct combphy_reg con0_for_pcie; - struct combphy_reg con1_for_pcie; - struct combphy_reg con2_for_pcie; - struct combphy_reg con3_for_pcie; - struct combphy_reg con0_for_sata; - struct combphy_reg con1_for_sata; - struct combphy_reg con2_for_sata; - struct combphy_reg con3_for_sata; - struct combphy_reg pipe_con0_for_sata; - struct combphy_reg pipe_xpcs_phy_ready; -}; - -struct rockchip_combphy_cfg { - const struct rockchip_combphy_grfcfg *grfcfg; - int (*combphy_cfg)(struct rockchip_combphy_priv *priv); -}; - -struct rockchip_combphy_priv { - u8 type; - void __iomem *mmio; - int num_clks; - struct clk_bulk_data *clks; - struct device *dev; - struct regmap *pipe_grf; - struct regmap *phy_grf; - struct phy *phy; - struct reset_control *phy_rst; - const struct rockchip_combphy_cfg *cfg; - bool enable_ssc; - bool ext_refclk; - struct clk *refclk; -}; - -static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, - int mask, int val, int reg) -{ - unsigned int temp; - - temp = readl(priv->mmio + reg); - temp = (temp & ~(mask)) | val; - writel(temp, priv->mmio + reg); -} - -static int rockchip_combphy_param_write(struct regmap *base, - const struct combphy_reg *reg, bool en) -{ - u32 val, mask, tmp; - - tmp = en ? reg->enable : reg->disable; - mask = GENMASK(reg->bitend, reg->bitstart); - val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); - - return regmap_write(base, reg->offset, val); -} - -static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) -{ - const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; - u32 mask, val; - - mask = GENMASK(cfg->pipe_phy_status.bitend, - cfg->pipe_phy_status.bitstart); - - regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); - val = (val & mask) >> cfg->pipe_phy_status.bitstart; - - return val; -} - -static int rockchip_combphy_init(struct phy *phy) -{ - struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); - const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; - u32 val; - int ret; - - ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); - if (ret) { - dev_err(priv->dev, "failed to enable clks\n"); - return ret; - } - - switch (priv->type) { - case PHY_TYPE_PCIE: - case PHY_TYPE_USB3: - case PHY_TYPE_SATA: - case PHY_TYPE_SGMII: - case PHY_TYPE_QSGMII: - if (priv->cfg->combphy_cfg) - ret = priv->cfg->combphy_cfg(priv); - break; - default: - dev_err(priv->dev, "incompatible PHY type\n"); - ret = -EINVAL; - break; - } - - if (ret) { - dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); - goto err_clk; - } - - ret = reset_control_deassert(priv->phy_rst); - if (ret) - goto err_clk; - - if (priv->type == PHY_TYPE_USB3) { - ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, - priv, val, - val == cfg->pipe_phy_status.enable, - 10, 1000); - if (ret) - dev_warn(priv->dev, "wait phy status ready timeout\n"); - } - - return 0; - -err_clk: - clk_bulk_disable_unprepare(priv->num_clks, priv->clks); - - return ret; -} - -static int rockchip_combphy_exit(struct phy *phy) -{ - struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); - - clk_bulk_disable_unprepare(priv->num_clks, priv->clks); - reset_control_assert(priv->phy_rst); - - return 0; -} - -static const struct phy_ops rochchip_combphy_ops = { - .init = rockchip_combphy_init, - .exit = rockchip_combphy_exit, - .owner = THIS_MODULE, -}; - -static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args) -{ - struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); - - if (args->args_count != 1) { - dev_err(dev, "invalid number of arguments\n"); - return ERR_PTR(-EINVAL); - } - - if (priv->type != PHY_NONE && priv->type != args->args[0]) - dev_warn(dev, "phy type select %d overwriting type %d\n", - args->args[0], priv->type); - - priv->type = args->args[0]; - - return priv->phy; -} - -static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) -{ - int i; - - priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); - if (priv->num_clks < 1) - return -EINVAL; - - priv->refclk = NULL; - for (i = 0; i < priv->num_clks; i++) { - if (!strncmp(priv->clks[i].id, "ref", 3)) { - priv->refclk = priv->clks[i].clk; - break; - } - } - - if (!priv->refclk) { - dev_err(dev, "no refclk found\n"); - return -EINVAL; - } - - priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); - if (IS_ERR(priv->pipe_grf)) { - dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); - return PTR_ERR(priv->pipe_grf); - } - - priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); - if (IS_ERR(priv->phy_grf)) { - dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); - return PTR_ERR(priv->phy_grf); - } - - priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); - - priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); - - priv->phy_rst = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(priv->phy_rst)) - return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); - - return 0; -} - -static int rockchip_combphy_probe(struct platform_device *pdev) -{ - struct phy_provider *phy_provider; - struct device *dev = &pdev->dev; - struct rockchip_combphy_priv *priv; - const struct rockchip_combphy_cfg *phy_cfg; - struct resource *res; - int ret; - - phy_cfg = of_device_get_match_data(dev); - if (!phy_cfg) { - dev_err(dev, "no OF match data provided\n"); - return -EINVAL; - } - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(priv->mmio)) { - ret = PTR_ERR(priv->mmio); - return ret; - } - - priv->dev = dev; - priv->type = PHY_NONE; - priv->cfg = phy_cfg; - - ret = rockchip_combphy_parse_dt(dev, priv); - if (ret) - return ret; - - ret = reset_control_assert(priv->phy_rst); - if (ret) { - dev_err(dev, "failed to reset phy\n"); - return ret; - } - - priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); - if (IS_ERR(priv->phy)) { - dev_err(dev, "failed to create combphy\n"); - return PTR_ERR(priv->phy); - } - - dev_set_drvdata(dev, priv); - phy_set_drvdata(priv->phy, priv); - - phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); - - return PTR_ERR_OR_ZERO(phy_provider); -} - -static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) -{ - const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; - unsigned long rate; - u32 val; - - switch (priv->type) { - case PHY_TYPE_PCIE: - /* Set SSC downward spread spectrum. */ - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, - PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, - PHYREG32); - - rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); - break; - - case PHY_TYPE_USB3: - /* Set SSC downward spread spectrum. */ - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, - PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, - PHYREG32); - - /* Enable adaptive CTLE for USB3.0 Rx. */ - val = readl(priv->mmio + PHYREG15); - val |= PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); - - /* Set PLL KVCO fine tuning signals. */ - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, - PHYREG33); - - /* Enable controlling random jitter. */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); - - /* Set PLL input clock divider 1/2. */ - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, - PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, - PHYREG6); - - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); - - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); - rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); - break; - - case PHY_TYPE_SATA: - /* Enable adaptive CTLE for SATA Rx. */ - val = readl(priv->mmio + PHYREG15); - val |= PHYREG15_CTLE_EN; - writel(val, priv->mmio + PHYREG15); - /* - * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. - * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) - */ - val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; - val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; - writel(val, priv->mmio + PHYREG7); - - rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); - rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); - break; - - case PHY_TYPE_SGMII: - rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); - break; - - case PHY_TYPE_QSGMII: - rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); - rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); - break; - - default: - dev_err(priv->dev, "incompatible PHY type\n"); - return -EINVAL; - } - - rate = clk_get_rate(priv->refclk); - - switch (rate) { - case REF_CLOCK_24MHz: - if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { - /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ - val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; - rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, - val, PHYREG15); - - writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); - } - break; - - case REF_CLOCK_25MHz: - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); - break; - - case REF_CLOCK_100MHz: - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); - if (priv->type == PHY_TYPE_PCIE) { - /* PLL KVCO fine tuning. */ - val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT; - rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, - val, PHYREG33); - - /* Enable controlling random jitter. */ - writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); - - val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; - rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, - val, PHYREG6); - - writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); - writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); - } else if (priv->type == PHY_TYPE_SATA) { - /* downward spread spectrum +500ppm */ - val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; - val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; - rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); - } - break; - - default: - dev_err(priv->dev, "unsupported rate: %lu\n", rate); - return -EINVAL; - } - - if (priv->ext_refclk) { - rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); - if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { - val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; - val |= PHYREG13_CKRCV_AMP0; - rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); - - val = readl(priv->mmio + PHYREG14); - val |= PHYREG14_CKRCV_AMP1; - writel(val, priv->mmio + PHYREG14); - } - } - - if (priv->enable_ssc) { - val = readl(priv->mmio + PHYREG8); - val |= PHYREG8_SSC_EN; - writel(val, priv->mmio + PHYREG8); - } - - return 0; -} - -static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { - /* pipe-phy-grf */ - .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, - .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, - .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, - .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, - .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, - .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, - .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, - .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, - .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, - .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, - .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, - .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, - .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, - .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, - .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, - .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, - .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, - .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, - .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, - .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, - .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, - .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, - .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, - .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, - .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, - .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, - /* pipe-grf */ - .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, - .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, -}; - -static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { - .grfcfg = &rk3568_combphy_grfcfgs, - .combphy_cfg = rk3568_combphy_cfg, -}; - -static const struct of_device_id rockchip_combphy_of_match[] = { - { - .compatible = "rockchip,rk3568-naneng-combphy", - .data = &rk3568_combphy_cfgs, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); - -static struct platform_driver rockchip_combphy_driver = { - .probe = rockchip_combphy_probe, - .driver = { - .name = "rockchip-naneng-combphy", - .of_match_table = rockchip_combphy_of_match, - }, -}; -module_platform_driver(rockchip_combphy_driver); - -MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/files-5.10/drivers/staging/media/hantro/rockchip_vpu_hw.c b/target/linux/rockchip/files-5.10/drivers/staging/media/hantro/rockchip_vpu_hw.c deleted file mode 100644 index 543dc4a54..000000000 --- a/target/linux/rockchip/files-5.10/drivers/staging/media/hantro/rockchip_vpu_hw.c +++ /dev/null @@ -1,569 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hantro VPU codec driver - * - * Copyright (C) 2018 Rockchip Electronics Co., Ltd. - * Jeffy Chen - */ - -#include - -#include "hantro.h" -#include "hantro_jpeg.h" -#include "hantro_g1_regs.h" -#include "hantro_h1_regs.h" -#include "rockchip_vpu2_regs.h" - -#define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) -#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) - -/* - * Supported formats. - */ - -static const struct hantro_fmt rockchip_vpu_enc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUV420M, - .codec_mode = HANTRO_MODE_NONE, - .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P, - }, - { - .fourcc = V4L2_PIX_FMT_NV12M, - .codec_mode = HANTRO_MODE_NONE, - .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP, - }, - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, - .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422, - }, - { - .fourcc = V4L2_PIX_FMT_UYVY, - .codec_mode = HANTRO_MODE_NONE, - .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422, - }, - { - .fourcc = V4L2_PIX_FMT_JPEG, - .codec_mode = HANTRO_MODE_JPEG_ENC, - .max_depth = 2, - .header_size = JPEG_HEADER_SIZE, - .frmsize = { - .min_width = 96, - .max_width = 8192, - .step_width = MB_DIM, - .min_height = 32, - .max_height = 8192, - .step_height = MB_DIM, - }, - }, -}; - -static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, - .postprocessed = true, - }, -}; - -static const struct hantro_fmt rk3066_vpu_dec_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12, - .codec_mode = HANTRO_MODE_NONE, - }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .codec_mode = HANTRO_MODE_H264_DEC, - .max_depth = 2, - .frmsize = { - .min_width = 48, - .max_width = 1920, - .step_width = MB_DIM, - .min_height = 48, - .max_height = 1088, - .step_height = MB_DIM, - }, - }, - { - .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, - .codec_mode = HANTRO_MODE_MPEG2_DEC, - .max_depth = 2, - .frmsize = { - .min_width = 48, - .max_width = 1920, - .step_width = MB_DIM, - .min_height = 48, - .max_height = 1088, - .step_height = MB_DIM, - }, - }, - { - .fourcc = V4L2_PIX_FMT_VP8_FRAME, - .codec_mode = HANTRO_MODE_VP8_DEC, - .max_depth = 2, - .frmsize = { - .min_width = 48, - .max_width = 1920, - .step_width = MB_DIM, - .min_height = 48, - .max_height = 1088, - .step_height = MB_DIM, - }, - }, -}; - -static const struct hantro_fmt rk3288_vpu_dec_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12, - .codec_mode = HANTRO_MODE_NONE, - }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .codec_mode = HANTRO_MODE_H264_DEC, - .max_depth = 2, - .frmsize = { - .min_width = 48, - .max_width = 4096, - .step_width = MB_DIM, - .min_height = 48, - .max_height = 2304, - .step_height = MB_DIM, - }, - }, - { - .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, - .codec_mode = HANTRO_MODE_MPEG2_DEC, - .max_depth = 2, - .frmsize = { - .min_width = 48, - .max_width = 1920, - .step_width = MB_DIM, - .min_height = 48, - .max_height = 1088, - .step_height = MB_DIM, - }, - }, - { - .fourcc = V4L2_PIX_FMT_VP8_FRAME, - .codec_mode = HANTRO_MODE_VP8_DEC, - .max_depth = 2, - .frmsize = { - .min_width = 48, - .max_width = 3840, - .step_width = MB_DIM, - .min_height = 48, - .max_height = 2160, - .step_height = MB_DIM, - }, - }, -}; - -static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12, - .codec_mode = HANTRO_MODE_NONE, - }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .codec_mode = HANTRO_MODE_H264_DEC, - .max_depth = 2, - .frmsize = { - .min_width = 48, - .max_width = 1920, - .step_width = MB_DIM, - .min_height = 48, - .max_height = 1088, - .step_height = MB_DIM, - }, - }, - { - .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, - .codec_mode = HANTRO_MODE_MPEG2_DEC, - .max_depth = 2, - .frmsize = { - .min_width = 48, - .max_width = 1920, - .step_width = MB_DIM, - .min_height = 48, - .max_height = 1088, - .step_height = MB_DIM, - }, - }, - { - .fourcc = V4L2_PIX_FMT_VP8_FRAME, - .codec_mode = HANTRO_MODE_VP8_DEC, - .max_depth = 2, - .frmsize = { - .min_width = 48, - .max_width = 3840, - .step_width = MB_DIM, - .min_height = 48, - .max_height = 2160, - .step_height = MB_DIM, - }, - }, -}; - -static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id) -{ - struct hantro_dev *vpu = dev_id; - enum vb2_buffer_state state; - u32 status; - - status = vepu_read(vpu, H1_REG_INTERRUPT); - state = (status & H1_REG_INTERRUPT_FRAME_RDY) ? - VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; - - vepu_write(vpu, 0, H1_REG_INTERRUPT); - vepu_write(vpu, 0, H1_REG_AXI_CTRL); - - hantro_irq_done(vpu, state); - - return IRQ_HANDLED; -} - -static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id) -{ - struct hantro_dev *vpu = dev_id; - enum vb2_buffer_state state; - u32 status; - - status = vdpu_read(vpu, VDPU_REG_INTERRUPT); - state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ? - VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; - - vdpu_write(vpu, 0, VDPU_REG_INTERRUPT); - vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL); - - hantro_irq_done(vpu, state); - - return IRQ_HANDLED; -} - -static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id) -{ - struct hantro_dev *vpu = dev_id; - enum vb2_buffer_state state; - u32 status; - - status = vepu_read(vpu, VEPU_REG_INTERRUPT); - state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ? - VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; - - vepu_write(vpu, 0, VEPU_REG_INTERRUPT); - vepu_write(vpu, 0, VEPU_REG_AXI_CTRL); - - hantro_irq_done(vpu, state); - - return IRQ_HANDLED; -} - -static int rk3036_vpu_hw_init(struct hantro_dev *vpu) -{ - /* Bump ACLK to max. possible freq. to improve performance. */ - clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ); - return 0; -} - -static int rk3066_vpu_hw_init(struct hantro_dev *vpu) -{ - /* Bump ACLKs to max. possible freq. to improve performance. */ - clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ); - clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ); - return 0; -} - -static int rockchip_vpu_hw_init(struct hantro_dev *vpu) -{ - /* Bump ACLK to max. possible freq. to improve performance. */ - clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); - return 0; -} - -static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); - vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); -} - -static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT); - vepu_write(vpu, 0, H1_REG_ENC_CTRL); - vepu_write(vpu, 0, H1_REG_AXI_CTRL); -} - -static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT); - vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS); - vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET); -} - -static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT); - vepu_write(vpu, 0, VEPU_REG_ENCODE_START); - vepu_write(vpu, 0, VEPU_REG_AXI_CTRL); -} - -/* - * Supported codec ops. - */ -static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = { - [HANTRO_MODE_H264_DEC] = { - .run = hantro_g1_h264_dec_run, - .reset = hantro_g1_reset, - .init = hantro_h264_dec_init, - .exit = hantro_h264_dec_exit, - }, - [HANTRO_MODE_MPEG2_DEC] = { - .run = hantro_g1_mpeg2_dec_run, - .reset = hantro_g1_reset, - .init = hantro_mpeg2_dec_init, - .exit = hantro_mpeg2_dec_exit, - }, - [HANTRO_MODE_VP8_DEC] = { - .run = hantro_g1_vp8_dec_run, - .reset = hantro_g1_reset, - .init = hantro_vp8_dec_init, - .exit = hantro_vp8_dec_exit, - }, -}; - -static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = { - [HANTRO_MODE_JPEG_ENC] = { - .run = hantro_h1_jpeg_enc_run, - .reset = rockchip_vpu1_enc_reset, - .init = hantro_jpeg_enc_init, - .done = hantro_h1_jpeg_enc_done, - .exit = hantro_jpeg_enc_exit, - }, - [HANTRO_MODE_H264_DEC] = { - .run = hantro_g1_h264_dec_run, - .reset = rk3066_vpu_dec_reset, - .init = hantro_h264_dec_init, - .exit = hantro_h264_dec_exit, - }, - [HANTRO_MODE_MPEG2_DEC] = { - .run = hantro_g1_mpeg2_dec_run, - .reset = rk3066_vpu_dec_reset, - .init = hantro_mpeg2_dec_init, - .exit = hantro_mpeg2_dec_exit, - }, - [HANTRO_MODE_VP8_DEC] = { - .run = hantro_g1_vp8_dec_run, - .reset = rk3066_vpu_dec_reset, - .init = hantro_vp8_dec_init, - .exit = hantro_vp8_dec_exit, - }, -}; - -static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = { - [HANTRO_MODE_JPEG_ENC] = { - .run = hantro_h1_jpeg_enc_run, - .reset = rockchip_vpu1_enc_reset, - .init = hantro_jpeg_enc_init, - .done = hantro_h1_jpeg_enc_done, - .exit = hantro_jpeg_enc_exit, - }, - [HANTRO_MODE_H264_DEC] = { - .run = hantro_g1_h264_dec_run, - .reset = hantro_g1_reset, - .init = hantro_h264_dec_init, - .exit = hantro_h264_dec_exit, - }, - [HANTRO_MODE_MPEG2_DEC] = { - .run = hantro_g1_mpeg2_dec_run, - .reset = hantro_g1_reset, - .init = hantro_mpeg2_dec_init, - .exit = hantro_mpeg2_dec_exit, - }, - [HANTRO_MODE_VP8_DEC] = { - .run = hantro_g1_vp8_dec_run, - .reset = hantro_g1_reset, - .init = hantro_vp8_dec_init, - .exit = hantro_vp8_dec_exit, - }, -}; - -static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { - [HANTRO_MODE_JPEG_ENC] = { - .run = rockchip_vpu2_jpeg_enc_run, - .reset = rockchip_vpu2_enc_reset, - .init = hantro_jpeg_enc_init, - .done = rockchip_vpu2_jpeg_enc_done, - .exit = hantro_jpeg_enc_exit, - }, - [HANTRO_MODE_H264_DEC] = { - .run = rockchip_vpu2_h264_dec_run, - .reset = rockchip_vpu2_dec_reset, - .init = hantro_h264_dec_init, - .exit = hantro_h264_dec_exit, - }, - [HANTRO_MODE_MPEG2_DEC] = { - .run = rockchip_vpu2_mpeg2_dec_run, - .reset = rockchip_vpu2_dec_reset, - .init = hantro_mpeg2_dec_init, - .exit = hantro_mpeg2_dec_exit, - }, - [HANTRO_MODE_VP8_DEC] = { - .run = rockchip_vpu2_vp8_dec_run, - .reset = rockchip_vpu2_dec_reset, - .init = hantro_vp8_dec_init, - .exit = hantro_vp8_dec_exit, - }, -}; - -/* - * VPU variant. - */ - -static const struct hantro_irq rockchip_vdpu1_irqs[] = { - { "vdpu", hantro_g1_irq }, -}; - -static const struct hantro_irq rockchip_vpu1_irqs[] = { - { "vepu", rockchip_vpu1_vepu_irq }, - { "vdpu", hantro_g1_irq }, -}; - -static const struct hantro_irq rockchip_vdpu2_irqs[] = { - { "vdpu", rockchip_vpu2_vdpu_irq }, -}; - -static const struct hantro_irq rockchip_vpu2_irqs[] = { - { "vepu", rockchip_vpu2_vepu_irq }, - { "vdpu", rockchip_vpu2_vdpu_irq }, -}; - -static const char * const rk3066_vpu_clk_names[] = { - "aclk_vdpu", "hclk_vdpu", - "aclk_vepu", "hclk_vepu" -}; - -static const char * const rockchip_vpu_clk_names[] = { - "aclk", "hclk" -}; - -/* VDPU1/VEPU1 */ - -const struct hantro_variant rk3036_vpu_variant = { - .dec_offset = 0x400, - .dec_fmts = rk3066_vpu_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), - .postproc_regs = &hantro_g1_postproc_regs, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = rk3036_vpu_codec_ops, - .irqs = rockchip_vdpu1_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs), - .init = rk3036_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) -}; - -/* - * Despite this variant has separate clocks for decoder and encoder, - * it's still required to enable all four of them for either decoding - * or encoding and we can't split it in separate g1/h1 variants. - */ -const struct hantro_variant rk3066_vpu_variant = { - .enc_offset = 0x0, - .enc_fmts = rockchip_vpu_enc_fmts, - .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), - .dec_offset = 0x400, - .dec_fmts = rk3066_vpu_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), - .postproc_regs = &hantro_g1_postproc_regs, - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3066_vpu_codec_ops, - .irqs = rockchip_vpu1_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), - .init = rk3066_vpu_hw_init, - .clk_names = rk3066_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names) -}; - -const struct hantro_variant rk3288_vpu_variant = { - .enc_offset = 0x0, - .enc_fmts = rockchip_vpu_enc_fmts, - .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), - .dec_offset = 0x400, - .dec_fmts = rk3288_vpu_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), - .postproc_regs = &hantro_g1_postproc_regs, - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3288_vpu_codec_ops, - .irqs = rockchip_vpu1_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), - .init = rockchip_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) -}; - -/* VDPU2/VEPU2 */ - -const struct hantro_variant rk3328_vpu_variant = { - .dec_offset = 0x400, - .dec_fmts = rk3399_vpu_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, - .irqs = rockchip_vdpu2_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), - .init = rockchip_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names), -}; - -const struct hantro_variant rk3399_vpu_variant = { - .enc_offset = 0x0, - .enc_fmts = rockchip_vpu_enc_fmts, - .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), - .dec_offset = 0x400, - .dec_fmts = rk3399_vpu_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER, - .codec_ops = rk3399_vpu_codec_ops, - .irqs = rockchip_vpu2_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs), - .init = rockchip_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) -}; - -const struct hantro_variant px30_vpu_variant = { - .enc_offset = 0x0, - .enc_fmts = rockchip_vpu_enc_fmts, - .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), - .dec_offset = 0x400, - .dec_fmts = rk3399_vpu_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, - .irqs = rockchip_vpu2_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs), - .init = rk3036_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) -}; diff --git a/target/linux/rockchip/files-5.10/include/dt-bindings/clock/rk3568-cru.h b/target/linux/rockchip/files-5.10/include/dt-bindings/clock/rk3568-cru.h deleted file mode 100644 index d29890865..000000000 --- a/target/linux/rockchip/files-5.10/include/dt-bindings/clock/rk3568-cru.h +++ /dev/null @@ -1,926 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Author: Elaine Zhang - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H - -/* pmucru-clocks indices */ - -/* pmucru plls */ -#define PLL_PPLL 1 -#define PLL_HPLL 2 - -/* pmucru clocks */ -#define XIN_OSC0_DIV 4 -#define CLK_RTC_32K 5 -#define CLK_PMU 6 -#define CLK_I2C0 7 -#define CLK_RTC32K_FRAC 8 -#define CLK_UART0_DIV 9 -#define CLK_UART0_FRAC 10 -#define SCLK_UART0 11 -#define DBCLK_GPIO0 12 -#define CLK_PWM0 13 -#define CLK_CAPTURE_PWM0_NDFT 14 -#define CLK_PMUPVTM 15 -#define CLK_CORE_PMUPVTM 16 -#define CLK_REF24M 17 -#define XIN_OSC0_USBPHY0_G 18 -#define CLK_USBPHY0_REF 19 -#define XIN_OSC0_USBPHY1_G 20 -#define CLK_USBPHY1_REF 21 -#define XIN_OSC0_MIPIDSIPHY0_G 22 -#define CLK_MIPIDSIPHY0_REF 23 -#define XIN_OSC0_MIPIDSIPHY1_G 24 -#define CLK_MIPIDSIPHY1_REF 25 -#define CLK_WIFI_DIV 26 -#define CLK_WIFI_OSC0 27 -#define CLK_WIFI 28 -#define CLK_PCIEPHY0_DIV 29 -#define CLK_PCIEPHY0_OSC0 30 -#define CLK_PCIEPHY0_REF 31 -#define CLK_PCIEPHY1_DIV 32 -#define CLK_PCIEPHY1_OSC0 33 -#define CLK_PCIEPHY1_REF 34 -#define CLK_PCIEPHY2_DIV 35 -#define CLK_PCIEPHY2_OSC0 36 -#define CLK_PCIEPHY2_REF 37 -#define CLK_PCIE30PHY_REF_M 38 -#define CLK_PCIE30PHY_REF_N 39 -#define CLK_HDMI_REF 40 -#define XIN_OSC0_EDPPHY_G 41 -#define PCLK_PDPMU 42 -#define PCLK_PMU 43 -#define PCLK_UART0 44 -#define PCLK_I2C0 45 -#define PCLK_GPIO0 46 -#define PCLK_PMUPVTM 47 -#define PCLK_PWM0 48 -#define CLK_PDPMU 49 -#define SCLK_32K_IOE 50 - -#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) - -/* cru-clocks indices */ - -/* cru plls */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_VPLL 5 -#define PLL_NPLL 6 - -/* cru clocks */ -#define CPLL_333M 9 -#define ARMCLK 10 -#define USB480M 11 -#define ACLK_CORE_NIU2BUS 18 -#define CLK_CORE_PVTM 19 -#define CLK_CORE_PVTM_CORE 20 -#define CLK_CORE_PVTPLL 21 -#define CLK_GPU_SRC 22 -#define CLK_GPU_PRE_NDFT 23 -#define CLK_GPU_PRE_MUX 24 -#define ACLK_GPU_PRE 25 -#define PCLK_GPU_PRE 26 -#define CLK_GPU 27 -#define CLK_GPU_NP5 28 -#define PCLK_GPU_PVTM 29 -#define CLK_GPU_PVTM 30 -#define CLK_GPU_PVTM_CORE 31 -#define CLK_GPU_PVTPLL 32 -#define CLK_NPU_SRC 33 -#define CLK_NPU_PRE_NDFT 34 -#define CLK_NPU 35 -#define CLK_NPU_NP5 36 -#define HCLK_NPU_PRE 37 -#define PCLK_NPU_PRE 38 -#define ACLK_NPU_PRE 39 -#define ACLK_NPU 40 -#define HCLK_NPU 41 -#define PCLK_NPU_PVTM 42 -#define CLK_NPU_PVTM 43 -#define CLK_NPU_PVTM_CORE 44 -#define CLK_NPU_PVTPLL 45 -#define CLK_DDRPHY1X_SRC 46 -#define CLK_DDRPHY1X_HWFFC_SRC 47 -#define CLK_DDR1X 48 -#define CLK_MSCH 49 -#define CLK24_DDRMON 50 -#define ACLK_GIC_AUDIO 51 -#define HCLK_GIC_AUDIO 52 -#define HCLK_SDMMC_BUFFER 53 -#define DCLK_SDMMC_BUFFER 54 -#define ACLK_GIC600 55 -#define ACLK_SPINLOCK 56 -#define HCLK_I2S0_8CH 57 -#define HCLK_I2S1_8CH 58 -#define HCLK_I2S2_2CH 59 -#define HCLK_I2S3_2CH 60 -#define CLK_I2S0_8CH_TX_SRC 61 -#define CLK_I2S0_8CH_TX_FRAC 62 -#define MCLK_I2S0_8CH_TX 63 -#define I2S0_MCLKOUT_TX 64 -#define CLK_I2S0_8CH_RX_SRC 65 -#define CLK_I2S0_8CH_RX_FRAC 66 -#define MCLK_I2S0_8CH_RX 67 -#define I2S0_MCLKOUT_RX 68 -#define CLK_I2S1_8CH_TX_SRC 69 -#define CLK_I2S1_8CH_TX_FRAC 70 -#define MCLK_I2S1_8CH_TX 71 -#define I2S1_MCLKOUT_TX 72 -#define CLK_I2S1_8CH_RX_SRC 73 -#define CLK_I2S1_8CH_RX_FRAC 74 -#define MCLK_I2S1_8CH_RX 75 -#define I2S1_MCLKOUT_RX 76 -#define CLK_I2S2_2CH_SRC 77 -#define CLK_I2S2_2CH_FRAC 78 -#define MCLK_I2S2_2CH 79 -#define I2S2_MCLKOUT 80 -#define CLK_I2S3_2CH_TX_SRC 81 -#define CLK_I2S3_2CH_TX_FRAC 82 -#define MCLK_I2S3_2CH_TX 83 -#define I2S3_MCLKOUT_TX 84 -#define CLK_I2S3_2CH_RX_SRC 85 -#define CLK_I2S3_2CH_RX_FRAC 86 -#define MCLK_I2S3_2CH_RX 87 -#define I2S3_MCLKOUT_RX 88 -#define HCLK_PDM 89 -#define MCLK_PDM 90 -#define HCLK_VAD 91 -#define HCLK_SPDIF_8CH 92 -#define MCLK_SPDIF_8CH_SRC 93 -#define MCLK_SPDIF_8CH_FRAC 94 -#define MCLK_SPDIF_8CH 95 -#define HCLK_AUDPWM 96 -#define SCLK_AUDPWM_SRC 97 -#define SCLK_AUDPWM_FRAC 98 -#define SCLK_AUDPWM 99 -#define HCLK_ACDCDIG 100 -#define CLK_ACDCDIG_I2C 101 -#define CLK_ACDCDIG_DAC 102 -#define CLK_ACDCDIG_ADC 103 -#define ACLK_SECURE_FLASH 104 -#define HCLK_SECURE_FLASH 105 -#define ACLK_CRYPTO_NS 106 -#define HCLK_CRYPTO_NS 107 -#define CLK_CRYPTO_NS_CORE 108 -#define CLK_CRYPTO_NS_PKA 109 -#define CLK_CRYPTO_NS_RNG 110 -#define HCLK_TRNG_NS 111 -#define CLK_TRNG_NS 112 -#define PCLK_OTPC_NS 113 -#define CLK_OTPC_NS_SBPI 114 -#define CLK_OTPC_NS_USR 115 -#define HCLK_NANDC 116 -#define NCLK_NANDC 117 -#define HCLK_SFC 118 -#define HCLK_SFC_XIP 119 -#define SCLK_SFC 120 -#define ACLK_EMMC 121 -#define HCLK_EMMC 122 -#define BCLK_EMMC 123 -#define CCLK_EMMC 124 -#define TCLK_EMMC 125 -#define ACLK_PIPE 126 -#define PCLK_PIPE 127 -#define PCLK_PIPE_GRF 128 -#define ACLK_PCIE20_MST 129 -#define ACLK_PCIE20_SLV 130 -#define ACLK_PCIE20_DBI 131 -#define PCLK_PCIE20 132 -#define CLK_PCIE20_AUX_NDFT 133 -#define CLK_PCIE20_AUX_DFT 134 -#define CLK_PCIE20_PIPE_DFT 135 -#define ACLK_PCIE30X1_MST 136 -#define ACLK_PCIE30X1_SLV 137 -#define ACLK_PCIE30X1_DBI 138 -#define PCLK_PCIE30X1 139 -#define CLK_PCIE30X1_AUX_NDFT 140 -#define CLK_PCIE30X1_AUX_DFT 141 -#define CLK_PCIE30X1_PIPE_DFT 142 -#define ACLK_PCIE30X2_MST 143 -#define ACLK_PCIE30X2_SLV 144 -#define ACLK_PCIE30X2_DBI 145 -#define PCLK_PCIE30X2 146 -#define CLK_PCIE30X2_AUX_NDFT 147 -#define CLK_PCIE30X2_AUX_DFT 148 -#define CLK_PCIE30X2_PIPE_DFT 149 -#define ACLK_SATA0 150 -#define CLK_SATA0_PMALIVE 151 -#define CLK_SATA0_RXOOB 152 -#define CLK_SATA0_PIPE_NDFT 153 -#define CLK_SATA0_PIPE_DFT 154 -#define ACLK_SATA1 155 -#define CLK_SATA1_PMALIVE 156 -#define CLK_SATA1_RXOOB 157 -#define CLK_SATA1_PIPE_NDFT 158 -#define CLK_SATA1_PIPE_DFT 159 -#define ACLK_SATA2 160 -#define CLK_SATA2_PMALIVE 161 -#define CLK_SATA2_RXOOB 162 -#define CLK_SATA2_PIPE_NDFT 163 -#define CLK_SATA2_PIPE_DFT 164 -#define ACLK_USB3OTG0 165 -#define CLK_USB3OTG0_REF 166 -#define CLK_USB3OTG0_SUSPEND 167 -#define ACLK_USB3OTG1 168 -#define CLK_USB3OTG1_REF 169 -#define CLK_USB3OTG1_SUSPEND 170 -#define CLK_XPCS_EEE 171 -#define PCLK_XPCS 172 -#define ACLK_PHP 173 -#define HCLK_PHP 174 -#define PCLK_PHP 175 -#define HCLK_SDMMC0 176 -#define CLK_SDMMC0 177 -#define HCLK_SDMMC1 178 -#define CLK_SDMMC1 179 -#define ACLK_GMAC0 180 -#define PCLK_GMAC0 181 -#define CLK_MAC0_2TOP 182 -#define CLK_MAC0_OUT 183 -#define CLK_MAC0_REFOUT 184 -#define CLK_GMAC0_PTP_REF 185 -#define ACLK_USB 186 -#define HCLK_USB 187 -#define PCLK_USB 188 -#define HCLK_USB2HOST0 189 -#define HCLK_USB2HOST0_ARB 190 -#define HCLK_USB2HOST1 191 -#define HCLK_USB2HOST1_ARB 192 -#define HCLK_SDMMC2 193 -#define CLK_SDMMC2 194 -#define ACLK_GMAC1 195 -#define PCLK_GMAC1 196 -#define CLK_MAC1_2TOP 197 -#define CLK_MAC1_OUT 198 -#define CLK_MAC1_REFOUT 199 -#define CLK_GMAC1_PTP_REF 200 -#define ACLK_PERIMID 201 -#define HCLK_PERIMID 202 -#define ACLK_VI 203 -#define HCLK_VI 204 -#define PCLK_VI 205 -#define ACLK_VICAP 206 -#define HCLK_VICAP 207 -#define DCLK_VICAP 208 -#define ICLK_VICAP_G 209 -#define ACLK_ISP 210 -#define HCLK_ISP 211 -#define CLK_ISP 212 -#define PCLK_CSI2HOST1 213 -#define CLK_CIF_OUT 214 -#define CLK_CAM0_OUT 215 -#define CLK_CAM1_OUT 216 -#define ACLK_VO 217 -#define HCLK_VO 218 -#define PCLK_VO 219 -#define ACLK_VOP_PRE 220 -#define ACLK_VOP 221 -#define HCLK_VOP 222 -#define DCLK_VOP0 223 -#define DCLK_VOP1 224 -#define DCLK_VOP2 225 -#define CLK_VOP_PWM 226 -#define ACLK_HDCP 227 -#define HCLK_HDCP 228 -#define PCLK_HDCP 229 -#define PCLK_HDMI_HOST 230 -#define CLK_HDMI_SFR 231 -#define PCLK_DSITX_0 232 -#define PCLK_DSITX_1 233 -#define PCLK_EDP_CTRL 234 -#define CLK_EDP_200M 235 -#define ACLK_VPU_PRE 236 -#define HCLK_VPU_PRE 237 -#define ACLK_VPU 238 -#define HCLK_VPU 239 -#define ACLK_RGA_PRE 240 -#define HCLK_RGA_PRE 241 -#define PCLK_RGA_PRE 242 -#define ACLK_RGA 243 -#define HCLK_RGA 244 -#define CLK_RGA_CORE 245 -#define ACLK_IEP 246 -#define HCLK_IEP 247 -#define CLK_IEP_CORE 248 -#define HCLK_EBC 249 -#define DCLK_EBC 250 -#define ACLK_JDEC 251 -#define HCLK_JDEC 252 -#define ACLK_JENC 253 -#define HCLK_JENC 254 -#define PCLK_EINK 255 -#define HCLK_EINK 256 -#define ACLK_RKVENC_PRE 257 -#define HCLK_RKVENC_PRE 258 -#define ACLK_RKVENC 259 -#define HCLK_RKVENC 260 -#define CLK_RKVENC_CORE 261 -#define ACLK_RKVDEC_PRE 262 -#define HCLK_RKVDEC_PRE 263 -#define ACLK_RKVDEC 264 -#define HCLK_RKVDEC 265 -#define CLK_RKVDEC_CA 266 -#define CLK_RKVDEC_CORE 267 -#define CLK_RKVDEC_HEVC_CA 268 -#define ACLK_BUS 269 -#define PCLK_BUS 270 -#define PCLK_TSADC 271 -#define CLK_TSADC_TSEN 272 -#define CLK_TSADC 273 -#define PCLK_SARADC 274 -#define CLK_SARADC 275 -#define PCLK_SCR 276 -#define PCLK_WDT_NS 277 -#define TCLK_WDT_NS 278 -#define ACLK_DMAC0 279 -#define ACLK_DMAC1 280 -#define ACLK_MCU 281 -#define PCLK_INTMUX 282 -#define PCLK_MAILBOX 283 -#define PCLK_UART1 284 -#define CLK_UART1_SRC 285 -#define CLK_UART1_FRAC 286 -#define SCLK_UART1 287 -#define PCLK_UART2 288 -#define CLK_UART2_SRC 289 -#define CLK_UART2_FRAC 290 -#define SCLK_UART2 291 -#define PCLK_UART3 292 -#define CLK_UART3_SRC 293 -#define CLK_UART3_FRAC 294 -#define SCLK_UART3 295 -#define PCLK_UART4 296 -#define CLK_UART4_SRC 297 -#define CLK_UART4_FRAC 298 -#define SCLK_UART4 299 -#define PCLK_UART5 300 -#define CLK_UART5_SRC 301 -#define CLK_UART5_FRAC 302 -#define SCLK_UART5 303 -#define PCLK_UART6 304 -#define CLK_UART6_SRC 305 -#define CLK_UART6_FRAC 306 -#define SCLK_UART6 307 -#define PCLK_UART7 308 -#define CLK_UART7_SRC 309 -#define CLK_UART7_FRAC 310 -#define SCLK_UART7 311 -#define PCLK_UART8 312 -#define CLK_UART8_SRC 313 -#define CLK_UART8_FRAC 314 -#define SCLK_UART8 315 -#define PCLK_UART9 316 -#define CLK_UART9_SRC 317 -#define CLK_UART9_FRAC 318 -#define SCLK_UART9 319 -#define PCLK_CAN0 320 -#define CLK_CAN0 321 -#define PCLK_CAN1 322 -#define CLK_CAN1 323 -#define PCLK_CAN2 324 -#define CLK_CAN2 325 -#define CLK_I2C 326 -#define PCLK_I2C1 327 -#define CLK_I2C1 328 -#define PCLK_I2C2 329 -#define CLK_I2C2 330 -#define PCLK_I2C3 331 -#define CLK_I2C3 332 -#define PCLK_I2C4 333 -#define CLK_I2C4 334 -#define PCLK_I2C5 335 -#define CLK_I2C5 336 -#define PCLK_SPI0 337 -#define CLK_SPI0 338 -#define PCLK_SPI1 339 -#define CLK_SPI1 340 -#define PCLK_SPI2 341 -#define CLK_SPI2 342 -#define PCLK_SPI3 343 -#define CLK_SPI3 344 -#define PCLK_PWM1 345 -#define CLK_PWM1 346 -#define CLK_PWM1_CAPTURE 347 -#define PCLK_PWM2 348 -#define CLK_PWM2 349 -#define CLK_PWM2_CAPTURE 350 -#define PCLK_PWM3 351 -#define CLK_PWM3 352 -#define CLK_PWM3_CAPTURE 353 -#define DBCLK_GPIO 354 -#define PCLK_GPIO1 355 -#define DBCLK_GPIO1 356 -#define PCLK_GPIO2 357 -#define DBCLK_GPIO2 358 -#define PCLK_GPIO3 359 -#define DBCLK_GPIO3 360 -#define PCLK_GPIO4 361 -#define DBCLK_GPIO4 362 -#define OCC_SCAN_CLK_GPIO 363 -#define PCLK_TIMER 364 -#define CLK_TIMER0 365 -#define CLK_TIMER1 366 -#define CLK_TIMER2 367 -#define CLK_TIMER3 368 -#define CLK_TIMER4 369 -#define CLK_TIMER5 370 -#define ACLK_TOP_HIGH 371 -#define ACLK_TOP_LOW 372 -#define HCLK_TOP 373 -#define PCLK_TOP 374 -#define PCLK_PCIE30PHY 375 -#define CLK_OPTC_ARB 376 -#define PCLK_MIPICSIPHY 377 -#define PCLK_MIPIDSIPHY0 378 -#define PCLK_MIPIDSIPHY1 379 -#define PCLK_PIPEPHY0 380 -#define PCLK_PIPEPHY1 381 -#define PCLK_PIPEPHY2 382 -#define PCLK_CPU_BOOST 383 -#define CLK_CPU_BOOST 384 -#define PCLK_OTPPHY 385 -#define SCLK_GMAC0 386 -#define SCLK_GMAC0_RGMII_SPEED 387 -#define SCLK_GMAC0_RMII_SPEED 388 -#define SCLK_GMAC0_RX_TX 389 -#define SCLK_GMAC1 390 -#define SCLK_GMAC1_RGMII_SPEED 391 -#define SCLK_GMAC1_RMII_SPEED 392 -#define SCLK_GMAC1_RX_TX 393 -#define SCLK_SDMMC0_DRV 394 -#define SCLK_SDMMC0_SAMPLE 395 -#define SCLK_SDMMC1_DRV 396 -#define SCLK_SDMMC1_SAMPLE 397 -#define SCLK_SDMMC2_DRV 398 -#define SCLK_SDMMC2_SAMPLE 399 -#define SCLK_EMMC_DRV 400 -#define SCLK_EMMC_SAMPLE 401 -#define PCLK_EDPPHY_GRF 402 -#define CLK_HDMI_CEC 403 -#define CLK_I2S0_8CH_TX 404 -#define CLK_I2S0_8CH_RX 405 -#define CLK_I2S1_8CH_TX 406 -#define CLK_I2S1_8CH_RX 407 -#define CLK_I2S2_2CH 408 -#define CLK_I2S3_2CH_TX 409 -#define CLK_I2S3_2CH_RX 410 -#define CPLL_500M 411 -#define CPLL_250M 412 -#define CPLL_125M 413 -#define CPLL_62P5M 414 -#define CPLL_50M 415 -#define CPLL_25M 416 -#define CPLL_100M 417 -#define SCLK_DDRCLK 418 - -#define PCLK_CORE_PVTM 450 - -#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) - -/* pmu soft-reset indices */ -/* pmucru_softrst_con0 */ -#define SRST_P_PDPMU_NIU 0 -#define SRST_P_PMUCRU 1 -#define SRST_P_PMUGRF 2 -#define SRST_P_I2C0 3 -#define SRST_I2C0 4 -#define SRST_P_UART0 5 -#define SRST_S_UART0 6 -#define SRST_P_PWM0 7 -#define SRST_PWM0 8 -#define SRST_P_GPIO0 9 -#define SRST_GPIO0 10 -#define SRST_P_PMUPVTM 11 -#define SRST_PMUPVTM 12 - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_NCORERESET0 0 -#define SRST_NCORERESET1 1 -#define SRST_NCORERESET2 2 -#define SRST_NCORERESET3 3 -#define SRST_NCPUPORESET0 4 -#define SRST_NCPUPORESET1 5 -#define SRST_NCPUPORESET2 6 -#define SRST_NCPUPORESET3 7 -#define SRST_NSRESET 8 -#define SRST_NSPORESET 9 -#define SRST_NATRESET 10 -#define SRST_NGICRESET 11 -#define SRST_NPRESET 12 -#define SRST_NPERIPHRESET 13 - -/* cru_softrst_con1 */ -#define SRST_A_CORE_NIU2DDR 16 -#define SRST_A_CORE_NIU2BUS 17 -#define SRST_P_DBG_NIU 18 -#define SRST_P_DBG 19 -#define SRST_P_DBG_DAPLITE 20 -#define SRST_DAP 21 -#define SRST_A_ADB400_CORE2GIC 22 -#define SRST_A_ADB400_GIC2CORE 23 -#define SRST_P_CORE_GRF 24 -#define SRST_P_CORE_PVTM 25 -#define SRST_CORE_PVTM 26 -#define SRST_CORE_PVTPLL 27 - -/* cru_softrst_con2 */ -#define SRST_GPU 32 -#define SRST_A_GPU_NIU 33 -#define SRST_P_GPU_NIU 34 -#define SRST_P_GPU_PVTM 35 -#define SRST_GPU_PVTM 36 -#define SRST_GPU_PVTPLL 37 -#define SRST_A_NPU_NIU 40 -#define SRST_H_NPU_NIU 41 -#define SRST_P_NPU_NIU 42 -#define SRST_A_NPU 43 -#define SRST_H_NPU 44 -#define SRST_P_NPU_PVTM 45 -#define SRST_NPU_PVTM 46 -#define SRST_NPU_PVTPLL 47 - -/* cru_softrst_con3 */ -#define SRST_A_MSCH 51 -#define SRST_HWFFC_CTRL 52 -#define SRST_DDR_ALWAYSON 53 -#define SRST_A_DDRSPLIT 54 -#define SRST_DDRDFI_CTL 55 -#define SRST_A_DMA2DDR 57 - -/* cru_softrst_con4 */ -#define SRST_A_PERIMID_NIU 64 -#define SRST_H_PERIMID_NIU 65 -#define SRST_A_GIC_AUDIO_NIU 66 -#define SRST_H_GIC_AUDIO_NIU 67 -#define SRST_A_GIC600 68 -#define SRST_A_GIC600_DEBUG 69 -#define SRST_A_GICADB_CORE2GIC 70 -#define SRST_A_GICADB_GIC2CORE 71 -#define SRST_A_SPINLOCK 72 -#define SRST_H_SDMMC_BUFFER 73 -#define SRST_D_SDMMC_BUFFER 74 -#define SRST_H_I2S0_8CH 75 -#define SRST_H_I2S1_8CH 76 -#define SRST_H_I2S2_2CH 77 -#define SRST_H_I2S3_2CH 78 - -/* cru_softrst_con5 */ -#define SRST_M_I2S0_8CH_TX 80 -#define SRST_M_I2S0_8CH_RX 81 -#define SRST_M_I2S1_8CH_TX 82 -#define SRST_M_I2S1_8CH_RX 83 -#define SRST_M_I2S2_2CH 84 -#define SRST_M_I2S3_2CH_TX 85 -#define SRST_M_I2S3_2CH_RX 86 -#define SRST_H_PDM 87 -#define SRST_M_PDM 88 -#define SRST_H_VAD 89 -#define SRST_H_SPDIF_8CH 90 -#define SRST_M_SPDIF_8CH 91 -#define SRST_H_AUDPWM 92 -#define SRST_S_AUDPWM 93 -#define SRST_H_ACDCDIG 94 -#define SRST_ACDCDIG 95 - -/* cru_softrst_con6 */ -#define SRST_A_SECURE_FLASH_NIU 96 -#define SRST_H_SECURE_FLASH_NIU 97 -#define SRST_A_CRYPTO_NS 103 -#define SRST_H_CRYPTO_NS 104 -#define SRST_CRYPTO_NS_CORE 105 -#define SRST_CRYPTO_NS_PKA 106 -#define SRST_CRYPTO_NS_RNG 107 -#define SRST_H_TRNG_NS 108 -#define SRST_TRNG_NS 109 - -/* cru_softrst_con7 */ -#define SRST_H_NANDC 112 -#define SRST_N_NANDC 113 -#define SRST_H_SFC 114 -#define SRST_H_SFC_XIP 115 -#define SRST_S_SFC 116 -#define SRST_A_EMMC 117 -#define SRST_H_EMMC 118 -#define SRST_B_EMMC 119 -#define SRST_C_EMMC 120 -#define SRST_T_EMMC 121 - -/* cru_softrst_con8 */ -#define SRST_A_PIPE_NIU 128 -#define SRST_P_PIPE_NIU 130 -#define SRST_P_PIPE_GRF 133 -#define SRST_A_SATA0 134 -#define SRST_SATA0_PIPE 135 -#define SRST_SATA0_PMALIVE 136 -#define SRST_SATA0_RXOOB 137 -#define SRST_A_SATA1 138 -#define SRST_SATA1_PIPE 139 -#define SRST_SATA1_PMALIVE 140 -#define SRST_SATA1_RXOOB 141 - -/* cru_softrst_con9 */ -#define SRST_A_SATA2 144 -#define SRST_SATA2_PIPE 145 -#define SRST_SATA2_PMALIVE 146 -#define SRST_SATA2_RXOOB 147 -#define SRST_USB3OTG0 148 -#define SRST_USB3OTG1 149 -#define SRST_XPCS 150 -#define SRST_XPCS_TX_DIV10 151 -#define SRST_XPCS_RX_DIV10 152 -#define SRST_XPCS_XGXS_RX 153 - -/* cru_softrst_con10 */ -#define SRST_P_PCIE20 160 -#define SRST_PCIE20_POWERUP 161 -#define SRST_MSTR_ARESET_PCIE20 162 -#define SRST_SLV_ARESET_PCIE20 163 -#define SRST_DBI_ARESET_PCIE20 164 -#define SRST_BRESET_PCIE20 165 -#define SRST_PERST_PCIE20 166 -#define SRST_CORE_RST_PCIE20 167 -#define SRST_NSTICKY_RST_PCIE20 168 -#define SRST_STICKY_RST_PCIE20 169 -#define SRST_PWR_RST_PCIE20 170 - -/* cru_softrst_con11 */ -#define SRST_P_PCIE30X1 176 -#define SRST_PCIE30X1_POWERUP 177 -#define SRST_M_ARESET_PCIE30X1 178 -#define SRST_S_ARESET_PCIE30X1 179 -#define SRST_D_ARESET_PCIE30X1 180 -#define SRST_BRESET_PCIE30X1 181 -#define SRST_PERST_PCIE30X1 182 -#define SRST_CORE_RST_PCIE30X1 183 -#define SRST_NSTC_RST_PCIE30X1 184 -#define SRST_STC_RST_PCIE30X1 185 -#define SRST_PWR_RST_PCIE30X1 186 - -/* cru_softrst_con12 */ -#define SRST_P_PCIE30X2 192 -#define SRST_PCIE30X2_POWERUP 193 -#define SRST_M_ARESET_PCIE30X2 194 -#define SRST_S_ARESET_PCIE30X2 195 -#define SRST_D_ARESET_PCIE30X2 196 -#define SRST_BRESET_PCIE30X2 197 -#define SRST_PERST_PCIE30X2 198 -#define SRST_CORE_RST_PCIE30X2 199 -#define SRST_NSTC_RST_PCIE30X2 200 -#define SRST_STC_RST_PCIE30X2 201 -#define SRST_PWR_RST_PCIE30X2 202 - -/* cru_softrst_con13 */ -#define SRST_A_PHP_NIU 208 -#define SRST_H_PHP_NIU 209 -#define SRST_P_PHP_NIU 210 -#define SRST_H_SDMMC0 211 -#define SRST_SDMMC0 212 -#define SRST_H_SDMMC1 213 -#define SRST_SDMMC1 214 -#define SRST_A_GMAC0 215 -#define SRST_GMAC0_TIMESTAMP 216 - -/* cru_softrst_con14 */ -#define SRST_A_USB_NIU 224 -#define SRST_H_USB_NIU 225 -#define SRST_P_USB_NIU 226 -#define SRST_P_USB_GRF 227 -#define SRST_H_USB2HOST0 228 -#define SRST_H_USB2HOST0_ARB 229 -#define SRST_USB2HOST0_UTMI 230 -#define SRST_H_USB2HOST1 231 -#define SRST_H_USB2HOST1_ARB 232 -#define SRST_USB2HOST1_UTMI 233 -#define SRST_H_SDMMC2 234 -#define SRST_SDMMC2 235 -#define SRST_A_GMAC1 236 -#define SRST_GMAC1_TIMESTAMP 237 - -/* cru_softrst_con15 */ -#define SRST_A_VI_NIU 240 -#define SRST_H_VI_NIU 241 -#define SRST_P_VI_NIU 242 -#define SRST_A_VICAP 247 -#define SRST_H_VICAP 248 -#define SRST_D_VICAP 249 -#define SRST_I_VICAP 250 -#define SRST_P_VICAP 251 -#define SRST_H_ISP 252 -#define SRST_ISP 253 -#define SRST_P_CSI2HOST1 255 - -/* cru_softrst_con16 */ -#define SRST_A_VO_NIU 256 -#define SRST_H_VO_NIU 257 -#define SRST_P_VO_NIU 258 -#define SRST_A_VOP_NIU 259 -#define SRST_A_VOP 260 -#define SRST_H_VOP 261 -#define SRST_VOP0 262 -#define SRST_VOP1 263 -#define SRST_VOP2 264 -#define SRST_VOP_PWM 265 -#define SRST_A_HDCP 266 -#define SRST_H_HDCP 267 -#define SRST_P_HDCP 268 -#define SRST_P_HDMI_HOST 270 -#define SRST_HDMI_HOST 271 - -/* cru_softrst_con17 */ -#define SRST_P_DSITX_0 272 -#define SRST_P_DSITX_1 273 -#define SRST_P_EDP_CTRL 274 -#define SRST_EDP_24M 275 -#define SRST_A_VPU_NIU 280 -#define SRST_H_VPU_NIU 281 -#define SRST_A_VPU 282 -#define SRST_H_VPU 283 -#define SRST_H_EINK 286 -#define SRST_P_EINK 287 - -/* cru_softrst_con18 */ -#define SRST_A_RGA_NIU 288 -#define SRST_H_RGA_NIU 289 -#define SRST_P_RGA_NIU 290 -#define SRST_A_RGA 292 -#define SRST_H_RGA 293 -#define SRST_RGA_CORE 294 -#define SRST_A_IEP 295 -#define SRST_H_IEP 296 -#define SRST_IEP_CORE 297 -#define SRST_H_EBC 298 -#define SRST_D_EBC 299 -#define SRST_A_JDEC 300 -#define SRST_H_JDEC 301 -#define SRST_A_JENC 302 -#define SRST_H_JENC 303 - -/* cru_softrst_con19 */ -#define SRST_A_VENC_NIU 304 -#define SRST_H_VENC_NIU 305 -#define SRST_A_RKVENC 307 -#define SRST_H_RKVENC 308 -#define SRST_RKVENC_CORE 309 - -/* cru_softrst_con20 */ -#define SRST_A_RKVDEC_NIU 320 -#define SRST_H_RKVDEC_NIU 321 -#define SRST_A_RKVDEC 322 -#define SRST_H_RKVDEC 323 -#define SRST_RKVDEC_CA 324 -#define SRST_RKVDEC_CORE 325 -#define SRST_RKVDEC_HEVC_CA 326 - -/* cru_softrst_con21 */ -#define SRST_A_BUS_NIU 336 -#define SRST_P_BUS_NIU 338 -#define SRST_P_CAN0 340 -#define SRST_CAN0 341 -#define SRST_P_CAN1 342 -#define SRST_CAN1 343 -#define SRST_P_CAN2 344 -#define SRST_CAN2 345 -#define SRST_P_GPIO1 346 -#define SRST_GPIO1 347 -#define SRST_P_GPIO2 348 -#define SRST_GPIO2 349 -#define SRST_P_GPIO3 350 -#define SRST_GPIO3 351 - -/* cru_softrst_con22 */ -#define SRST_P_GPIO4 352 -#define SRST_GPIO4 353 -#define SRST_P_I2C1 354 -#define SRST_I2C1 355 -#define SRST_P_I2C2 356 -#define SRST_I2C2 357 -#define SRST_P_I2C3 358 -#define SRST_I2C3 359 -#define SRST_P_I2C4 360 -#define SRST_I2C4 361 -#define SRST_P_I2C5 362 -#define SRST_I2C5 363 -#define SRST_P_OTPC_NS 364 -#define SRST_OTPC_NS_SBPI 365 -#define SRST_OTPC_NS_USR 366 - -/* cru_softrst_con23 */ -#define SRST_P_PWM1 368 -#define SRST_PWM1 369 -#define SRST_P_PWM2 370 -#define SRST_PWM2 371 -#define SRST_P_PWM3 372 -#define SRST_PWM3 373 -#define SRST_P_SPI0 374 -#define SRST_SPI0 375 -#define SRST_P_SPI1 376 -#define SRST_SPI1 377 -#define SRST_P_SPI2 378 -#define SRST_SPI2 379 -#define SRST_P_SPI3 380 -#define SRST_SPI3 381 - -/* cru_softrst_con24 */ -#define SRST_P_SARADC 384 -#define SRST_P_TSADC 385 -#define SRST_TSADC 386 -#define SRST_P_TIMER 387 -#define SRST_TIMER0 388 -#define SRST_TIMER1 389 -#define SRST_TIMER2 390 -#define SRST_TIMER3 391 -#define SRST_TIMER4 392 -#define SRST_TIMER5 393 -#define SRST_P_UART1 394 -#define SRST_S_UART1 395 - -/* cru_softrst_con25 */ -#define SRST_P_UART2 400 -#define SRST_S_UART2 401 -#define SRST_P_UART3 402 -#define SRST_S_UART3 403 -#define SRST_P_UART4 404 -#define SRST_S_UART4 405 -#define SRST_P_UART5 406 -#define SRST_S_UART5 407 -#define SRST_P_UART6 408 -#define SRST_S_UART6 409 -#define SRST_P_UART7 410 -#define SRST_S_UART7 411 -#define SRST_P_UART8 412 -#define SRST_S_UART8 413 -#define SRST_P_UART9 414 -#define SRST_S_UART9 415 - -/* cru_softrst_con26 */ -#define SRST_P_GRF 416 -#define SRST_P_GRF_VCCIO12 417 -#define SRST_P_GRF_VCCIO34 418 -#define SRST_P_GRF_VCCIO567 419 -#define SRST_P_SCR 420 -#define SRST_P_WDT_NS 421 -#define SRST_T_WDT_NS 422 -#define SRST_P_DFT2APB 423 -#define SRST_A_MCU 426 -#define SRST_P_INTMUX 427 -#define SRST_P_MAILBOX 428 - -/* cru_softrst_con27 */ -#define SRST_A_TOP_HIGH_NIU 432 -#define SRST_A_TOP_LOW_NIU 433 -#define SRST_H_TOP_NIU 434 -#define SRST_P_TOP_NIU 435 -#define SRST_P_TOP_CRU 438 -#define SRST_P_DDRPHY 439 -#define SRST_DDRPHY 440 -#define SRST_P_MIPICSIPHY 442 -#define SRST_P_MIPIDSIPHY0 443 -#define SRST_P_MIPIDSIPHY1 444 -#define SRST_P_PCIE30PHY 445 -#define SRST_PCIE30PHY 446 -#define SRST_P_PCIE30PHY_GRF 447 - -/* cru_softrst_con28 */ -#define SRST_P_APB2ASB_LEFT 448 -#define SRST_P_APB2ASB_BOTTOM 449 -#define SRST_P_ASB2APB_LEFT 450 -#define SRST_P_ASB2APB_BOTTOM 451 -#define SRST_P_PIPEPHY0 452 -#define SRST_PIPEPHY0 453 -#define SRST_P_PIPEPHY1 454 -#define SRST_PIPEPHY1 455 -#define SRST_P_PIPEPHY2 456 -#define SRST_PIPEPHY2 457 -#define SRST_P_USB2PHY0_GRF 458 -#define SRST_P_USB2PHY1_GRF 459 -#define SRST_P_CPU_BOOST 460 -#define SRST_CPU_BOOST 461 -#define SRST_P_OTPPHY 462 -#define SRST_OTPPHY 463 - -/* cru_softrst_con29 */ -#define SRST_USB2PHY0_POR 464 -#define SRST_USB2PHY0_USB3OTG0 465 -#define SRST_USB2PHY0_USB3OTG1 466 -#define SRST_USB2PHY1_POR 467 -#define SRST_USB2PHY1_USB2HOST0 468 -#define SRST_USB2PHY1_USB2HOST1 469 -#define SRST_P_EDPPHY_GRF 470 -#define SRST_TSADCPHY 471 -#define SRST_GMAC0_DELAYLINE 472 -#define SRST_GMAC1_DELAYLINE 473 -#define SRST_OTPC_ARB 474 -#define SRST_P_PIPEPHY0_GRF 475 -#define SRST_P_PIPEPHY1_GRF 476 -#define SRST_P_PIPEPHY2_GRF 477 - -#endif diff --git a/target/linux/rockchip/files-5.10/include/dt-bindings/power/rk3568-power.h b/target/linux/rockchip/files-5.10/include/dt-bindings/power/rk3568-power.h deleted file mode 100644 index 6cc1af1a9..000000000 --- a/target/linux/rockchip/files-5.10/include/dt-bindings/power/rk3568-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ -#define __DT_BINDINGS_POWER_RK3568_POWER_H__ - -/* VD_CORE */ -#define RK3568_PD_CPU_0 0 -#define RK3568_PD_CPU_1 1 -#define RK3568_PD_CPU_2 2 -#define RK3568_PD_CPU_3 3 -#define RK3568_PD_CORE_ALIVE 4 - -/* VD_PMU */ -#define RK3568_PD_PMU 5 - -/* VD_NPU */ -#define RK3568_PD_NPU 6 - -/* VD_GPU */ -#define RK3568_PD_GPU 7 - -/* VD_LOGIC */ -#define RK3568_PD_VI 8 -#define RK3568_PD_VO 9 -#define RK3568_PD_RGA 10 -#define RK3568_PD_VPU 11 -#define RK3568_PD_CENTER 12 -#define RK3568_PD_RKVDEC 13 -#define RK3568_PD_RKVENC 14 -#define RK3568_PD_PIPE 15 -#define RK3568_PD_LOGIC_ALIVE 16 - -#endif diff --git a/target/linux/rockchip/files-5.10/include/dt-bindings/soc/rockchip,vop2.h b/target/linux/rockchip/files-5.10/include/dt-bindings/soc/rockchip,vop2.h deleted file mode 100644 index 6e66a802b..000000000 --- a/target/linux/rockchip/files-5.10/include/dt-bindings/soc/rockchip,vop2.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ - -#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H -#define __DT_BINDINGS_ROCKCHIP_VOP2_H - -#define ROCKCHIP_VOP2_EP_RGB0 1 -#define ROCKCHIP_VOP2_EP_HDMI0 2 -#define ROCKCHIP_VOP2_EP_EDP0 3 -#define ROCKCHIP_VOP2_EP_MIPI0 4 -#define ROCKCHIP_VOP2_EP_LVDS0 5 -#define ROCKCHIP_VOP2_EP_MIPI1 6 -#define ROCKCHIP_VOP2_EP_LVDS1 7 - -#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ diff --git a/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch new file mode 100644 index 000000000..40d484dad --- /dev/null +++ b/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch @@ -0,0 +1,74 @@ +From 82985725e071f2a5735052f18e109a32aeac3a0b Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Sun, 26 Jul 2020 02:38:31 +0200 +Subject: [PATCH] net: usb: r8152: add LED configuration from OF + +This adds the ability to configure the LED configuration register using +OF. This way, the correct value for board specific LED configuration can +be determined. + +Signed-off-by: David Bauer +--- + drivers/net/usb/r8152.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -5301,6 +5302,22 @@ static void rtl_tally_reset(struct r8152 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); + } + ++static int r8152_led_configuration(struct r8152 *tp) ++{ ++ u32 led_data; ++ int ret; ++ ++ ret = of_property_read_u32(tp->udev->dev.of_node, "realtek,led-data", ++ &led_data); ++ ++ if (ret) ++ return ret; ++ ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data); ++ ++ return 0; ++} ++ + static void r8152b_init(struct r8152 *tp) + { + u32 ocp_data; +@@ -5342,6 +5359,8 @@ static void r8152b_init(struct r8152 *tp + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); ++ ++ r8152_led_configuration(tp); + } + + static void r8153_init(struct r8152 *tp) +@@ -5487,6 +5506,8 @@ static void r8153_init(struct r8152 *tp) + tp->coalesce = COALESCE_SLOW; + break; + } ++ ++ r8152_led_configuration(tp); + } + + static void r8153b_init(struct r8152 *tp) +@@ -5573,6 +5594,8 @@ static void r8153b_init(struct r8152 *tp + rtl_tally_reset(tp); + + tp->coalesce = 15000; /* 15 us */ ++ ++ r8152_led_configuration(tp); + } + + static int rtl8152_pre_reset(struct usb_interface *intf) diff --git a/target/linux/rockchip/patches-5.10/003-dt-bindings-net-add-RTL8152-binding-documentation.patch b/target/linux/rockchip/patches-5.10/003-dt-bindings-net-add-RTL8152-binding-documentation.patch new file mode 100644 index 000000000..be262b993 --- /dev/null +++ b/target/linux/rockchip/patches-5.10/003-dt-bindings-net-add-RTL8152-binding-documentation.patch @@ -0,0 +1,54 @@ +From 3ee05f4aa64fc86af3be5bc176ba5808de9260a7 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Sun, 26 Jul 2020 15:30:33 +0200 +Subject: [PATCH] dt-bindings: net: add RTL8152 binding documentation + +Add binding documentation for the Realtek RTL8152 / RTL8153 USB ethernet +adapters. + +Signed-off-by: David Bauer +--- + .../bindings/net/realtek,rtl8152.yaml | 36 +++++++++++++++++++ + 1 file changed, 36 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl8152.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/realtek,rtl8152.yaml +@@ -0,0 +1,36 @@ ++# SPDX-License-Identifier: GPL-2.0 ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/realtek,rtl8152.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Realtek RTL8152/RTL8153 series USB ethernet ++ ++maintainers: ++ - David Bauer ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - realtek,rtl8152 ++ - realtek,rtl8153 ++ ++ reg: ++ description: The device number on the USB bus ++ ++ realtek,led-data: ++ description: Value to be written to the LED configuration register. ++ ++required: ++ - compatible ++ - reg ++ ++examples: ++ - | ++ usb-eth@2 { ++ compatible = "realtek,rtl8153"; ++ reg = <2>; ++ realtek,led-data = <0x87>; ++ }; +\ No newline at end of file diff --git a/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch index 74e3f17f3..a5631b632 100644 --- a/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch +++ b/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch @@ -13,7 +13,7 @@ Signed-off-by: Tianling Shen --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -68,6 +68,19 @@ +@@ -75,6 +75,19 @@ &emmc_phy { status = "disabled"; }; diff --git a/target/linux/rockchip/patches-5.10/008-0001-v5.16-ASoC-rockchip-Add-support-for-rv1126-pdm.patch b/target/linux/rockchip/patches-5.10/008-0001-v5.16-ASoC-rockchip-Add-support-for-rv1126-pdm.patch deleted file mode 100644 index 58d4b15cf..000000000 --- a/target/linux/rockchip/patches-5.10/008-0001-v5.16-ASoC-rockchip-Add-support-for-rv1126-pdm.patch +++ /dev/null @@ -1,155 +0,0 @@ -From d269aa2ab975807764dc2509e4156bb9b6bd0d34 Mon Sep 17 00:00:00 2001 -From: Sugar Zhang -Date: Fri, 3 Sep 2021 21:23:24 +0800 -Subject: [PATCH] ASoC: rockchip: Add support for rv1126 pdm - -This patch adds support for rv1126 pdm controller which -redesign cic filiter for better performance. - -Signed-off-by: Sugar Zhang -Link: https://lore.kernel.org/r/1630675410-3354-1-git-send-email-sugar.zhang@rock-chips.com -Signed-off-by: Mark Brown ---- - sound/soc/rockchip/rockchip_pdm.c | 76 ++++++++++++++++++++++++++++--- - sound/soc/rockchip/rockchip_pdm.h | 3 ++ - 2 files changed, 73 insertions(+), 6 deletions(-) - ---- a/sound/soc/rockchip/rockchip_pdm.c -+++ b/sound/soc/rockchip/rockchip_pdm.c -@@ -24,6 +24,7 @@ - enum rk_pdm_version { - RK_PDM_RK3229, - RK_PDM_RK3308, -+ RK_PDM_RV1126, - }; - - struct rk_pdm_dev { -@@ -121,6 +122,55 @@ static unsigned int get_pdm_ds_ratio(uns - return ratio; - } - -+static unsigned int get_pdm_cic_ratio(unsigned int clk) -+{ -+ switch (clk) { -+ case 4096000: -+ case 5644800: -+ case 6144000: -+ return 0; -+ case 2048000: -+ case 2822400: -+ case 3072000: -+ return 1; -+ case 1024000: -+ case 1411200: -+ case 1536000: -+ return 2; -+ default: -+ return 1; -+ } -+} -+ -+static unsigned int samplerate_to_bit(unsigned int samplerate) -+{ -+ switch (samplerate) { -+ case 8000: -+ case 11025: -+ case 12000: -+ return 0; -+ case 16000: -+ case 22050: -+ case 24000: -+ return 1; -+ case 32000: -+ return 2; -+ case 44100: -+ case 48000: -+ return 3; -+ case 64000: -+ case 88200: -+ case 96000: -+ return 4; -+ case 128000: -+ case 176400: -+ case 192000: -+ return 5; -+ default: -+ return 1; -+ } -+} -+ - static inline struct rk_pdm_dev *to_info(struct snd_soc_dai *dai) - { - return snd_soc_dai_get_drvdata(dai); -@@ -166,7 +216,8 @@ static int rockchip_pdm_hw_params(struct - if (ret) - return -EINVAL; - -- if (pdm->version == RK_PDM_RK3308) { -+ if (pdm->version == RK_PDM_RK3308 || -+ pdm->version == RK_PDM_RV1126) { - rational_best_approximation(clk_out, clk_src, - GENMASK(16 - 1, 0), - GENMASK(16 - 1, 0), -@@ -194,8 +245,18 @@ static int rockchip_pdm_hw_params(struct - PDM_CLK_FD_RATIO_MSK, - val); - } -- val = get_pdm_ds_ratio(samplerate); -- regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val); -+ -+ if (pdm->version == RK_PDM_RV1126) { -+ val = get_pdm_cic_ratio(clk_out); -+ regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CIC_RATIO_MSK, val); -+ val = samplerate_to_bit(samplerate); -+ regmap_update_bits(pdm->regmap, PDM_CTRL0, -+ PDM_SAMPLERATE_MSK, PDM_SAMPLERATE(val)); -+ } else { -+ val = get_pdm_ds_ratio(samplerate); -+ regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val); -+ } -+ - regmap_update_bits(pdm->regmap, PDM_HPF_CTRL, - PDM_HPF_CF_MSK, PDM_HPF_60HZ); - regmap_update_bits(pdm->regmap, PDM_HPF_CTRL, -@@ -441,9 +502,10 @@ static bool rockchip_pdm_precious_reg(st - } - - static const struct reg_default rockchip_pdm_reg_defaults[] = { -- {0x04, 0x78000017}, -- {0x08, 0x0bb8ea60}, -- {0x18, 0x0000001f}, -+ { PDM_CTRL0, 0x78000017 }, -+ { PDM_CTRL1, 0x0bb8ea60 }, -+ { PDM_CLK_CTRL, 0x0000e401 }, -+ { PDM_DMA_CTRL, 0x0000001f }, - }; - - static const struct regmap_config rockchip_pdm_regmap_config = { -@@ -469,6 +531,8 @@ static const struct of_device_id rockchi - .data = (void *)RK_PDM_RK3308 }, - { .compatible = "rockchip,rk3308-pdm", - .data = (void *)RK_PDM_RK3308 }, -+ { .compatible = "rockchip,rv1126-pdm", -+ .data = (void *)RK_PDM_RV1126 }, - {}, - }; - MODULE_DEVICE_TABLE(of, rockchip_pdm_match); ---- a/sound/soc/rockchip/rockchip_pdm.h -+++ b/sound/soc/rockchip/rockchip_pdm.h -@@ -41,6 +41,8 @@ - #define PDM_PATH1_EN BIT(28) - #define PDM_PATH0_EN BIT(27) - #define PDM_HWT_EN BIT(26) -+#define PDM_SAMPLERATE_MSK GENMASK(7, 5) -+#define PDM_SAMPLERATE(x) ((x) << 5) - #define PDM_VDW_MSK (0x1f << 0) - #define PDM_VDW(X) ((X - 1) << 0) - -@@ -66,6 +68,7 @@ - #define PDM_CLK_1280FS (0x2 << 0) - #define PDM_CLK_2560FS (0x3 << 0) - #define PDM_CLK_5120FS (0x4 << 0) -+#define PDM_CIC_RATIO_MSK (0x3 << 0) - - /* PDM HPF CTRL */ - #define PDM_HPF_LE BIT(3) diff --git a/target/linux/rockchip/patches-5.10/008-0002-v5.16-ASoC-rockchip-pdm-Add-support-for-rk3568-pdm.patch b/target/linux/rockchip/patches-5.10/008-0002-v5.16-ASoC-rockchip-pdm-Add-support-for-rk3568-pdm.patch deleted file mode 100644 index 7eef2b8a7..000000000 --- a/target/linux/rockchip/patches-5.10/008-0002-v5.16-ASoC-rockchip-pdm-Add-support-for-rk3568-pdm.patch +++ /dev/null @@ -1,26 +0,0 @@ -From d00d1cd4ab42f92d4d871deb9cdea1d7c262a213 Mon Sep 17 00:00:00 2001 -From: Sugar Zhang -Date: Fri, 3 Sep 2021 21:23:26 +0800 -Subject: [PATCH] ASoC: rockchip: pdm: Add support for rk3568 pdm - -This patch adds compatible for rk3568 which is the same -with rv1126. - -Signed-off-by: Sugar Zhang -Link: https://lore.kernel.org/r/1630675410-3354-3-git-send-email-sugar.zhang@rock-chips.com -Signed-off-by: Mark Brown ---- - sound/soc/rockchip/rockchip_pdm.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/sound/soc/rockchip/rockchip_pdm.c -+++ b/sound/soc/rockchip/rockchip_pdm.c -@@ -531,6 +531,8 @@ static const struct of_device_id rockchi - .data = (void *)RK_PDM_RK3308 }, - { .compatible = "rockchip,rk3308-pdm", - .data = (void *)RK_PDM_RK3308 }, -+ { .compatible = "rockchip,rk3568-pdm", -+ .data = (void *)RK_PDM_RV1126 }, - { .compatible = "rockchip,rv1126-pdm", - .data = (void *)RK_PDM_RV1126 }, - {}, diff --git a/target/linux/rockchip/patches-5.10/008-0003-v5.16-ASoC-rockchip-pdm-Add-support-for-path-map.patch b/target/linux/rockchip/patches-5.10/008-0003-v5.16-ASoC-rockchip-pdm-Add-support-for-path-map.patch deleted file mode 100644 index 0aeb92efb..000000000 --- a/target/linux/rockchip/patches-5.10/008-0003-v5.16-ASoC-rockchip-pdm-Add-support-for-path-map.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 13e6e042a6f9c2be676f421935e026308de3303c Mon Sep 17 00:00:00 2001 -From: Sugar Zhang -Date: Fri, 3 Sep 2021 21:23:28 +0800 -Subject: [PATCH] ASoC: rockchip: pdm: Add support for path map - -This patch adds property 'rockchip,path-map' for path mapping. - -e.g. - -"rockchip,path-map = <3 2 1 0>" means the mapping as follows: - - path0 <-- sdi3 - path1 <-- sdi2 - path2 <-- sdi1 - path3 <-- sdi0 - -Signed-off-by: Sugar Zhang -Link: https://lore.kernel.org/r/1630675410-3354-5-git-send-email-sugar.zhang@rock-chips.com -Signed-off-by: Mark Brown ---- - sound/soc/rockchip/rockchip_pdm.c | 34 +++++++++++++++++++++++++++++++ - sound/soc/rockchip/rockchip_pdm.h | 3 +++ - 2 files changed, 37 insertions(+) - ---- a/sound/soc/rockchip/rockchip_pdm.c -+++ b/sound/soc/rockchip/rockchip_pdm.c -@@ -20,6 +20,7 @@ - - #define PDM_DMA_BURST_SIZE (8) /* size * width: 8*4 = 32 bytes */ - #define PDM_SIGNOFF_CLK_RATE (100000000) -+#define PDM_PATH_MAX (4) - - enum rk_pdm_version { - RK_PDM_RK3229, -@@ -539,8 +540,36 @@ static const struct of_device_id rockchi - }; - MODULE_DEVICE_TABLE(of, rockchip_pdm_match); - -+static int rockchip_pdm_path_parse(struct rk_pdm_dev *pdm, struct device_node *node) -+{ -+ unsigned int path[PDM_PATH_MAX]; -+ int cnt = 0, ret = 0, i = 0, val = 0, msk = 0; -+ -+ cnt = of_count_phandle_with_args(node, "rockchip,path-map", -+ NULL); -+ if (cnt != PDM_PATH_MAX) -+ return cnt; -+ -+ ret = of_property_read_u32_array(node, "rockchip,path-map", -+ path, cnt); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < cnt; i++) { -+ if (path[i] >= PDM_PATH_MAX) -+ return -EINVAL; -+ msk |= PDM_PATH_MASK(i); -+ val |= PDM_PATH(i, path[i]); -+ } -+ -+ regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, msk, val); -+ -+ return 0; -+} -+ - static int rockchip_pdm_probe(struct platform_device *pdev) - { -+ struct device_node *node = pdev->dev.of_node; - const struct of_device_id *match; - struct rk_pdm_dev *pdm; - struct resource *res; -@@ -607,6 +636,11 @@ static int rockchip_pdm_probe(struct pla - } - - rockchip_pdm_rxctrl(pdm, 0); -+ -+ ret = rockchip_pdm_path_parse(pdm, node); -+ if (ret != 0 && ret != -ENOENT) -+ goto err_suspend; -+ - ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); - if (ret) { - dev_err(&pdev->dev, "could not register pcm: %d\n", ret); ---- a/sound/soc/rockchip/rockchip_pdm.h -+++ b/sound/soc/rockchip/rockchip_pdm.h -@@ -53,6 +53,9 @@ - #define PDM_FD_DENOMINATOR_MSK GENMASK(15, 0) - - /* PDM CLK CTRL */ -+#define PDM_PATH_SHIFT(x) (8 + (x) * 2) -+#define PDM_PATH_MASK(x) (0x3 << PDM_PATH_SHIFT(x)) -+#define PDM_PATH(x, v) ((v) << PDM_PATH_SHIFT(x)) - #define PDM_CLK_FD_RATIO_MSK BIT(6) - #define PDM_CLK_FD_RATIO_40 (0X0 << 6) - #define PDM_CLK_FD_RATIO_35 BIT(6) diff --git a/target/linux/rockchip/patches-5.10/008-0004-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch b/target/linux/rockchip/patches-5.10/008-0004-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch deleted file mode 100644 index fdf559c5a..000000000 --- a/target/linux/rockchip/patches-5.10/008-0004-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 1330875dc2a3742fd41127e78d5036f2d8f261da Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 28 Jul 2021 14:00:31 -0400 -Subject: [PATCH] arm64: dts: rockchip: add rk3568 tsadc nodes - -Add the thermal and tsadc nodes to the rk3568 device tree. -There are two sensors, one for the cpu, one for the gpu. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 9 +++ - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++ - 2 files changed, 79 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi -@@ -3108,4 +3108,13 @@ - <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; - }; - }; -+ -+ tsadc { -+ /omit-if-no-ref/ -+ tsadc_pin: tsadc-pin { -+ rockchip,pins = -+ /* tsadc_pin */ -+ <0 RK_PA1 0 &pcfg_pull_none>; -+ }; -+ }; - }; diff --git a/target/linux/rockchip/patches-5.10/008-0005-v5.16-thermal-drivers-rockchip_thermal-Allow-more-resets-for-ts.patch b/target/linux/rockchip/patches-5.10/008-0005-v5.16-thermal-drivers-rockchip_thermal-Allow-more-resets-for-ts.patch deleted file mode 100644 index 74c0ad07a..000000000 --- a/target/linux/rockchip/patches-5.10/008-0005-v5.16-thermal-drivers-rockchip_thermal-Allow-more-resets-for-ts.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 02832ed8ae2c8b130efea4e43d3ecac50b4b7933 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Thu, 30 Sep 2021 13:05:16 +0200 -Subject: [PATCH] thermal/drivers/rockchip_thermal: Allow more resets for tsadc - node - -The tsadc node in rk356x.dtsi has more resets then currently supported -by the rockchip_thermal.c driver, so use -devm_reset_control_array_get() to reset them all. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20210930110517.14323-3-jbx6244@gmail.com -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/rockchip_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/rockchip_thermal.c -+++ b/drivers/thermal/rockchip_thermal.c -@@ -1262,7 +1262,7 @@ static int rockchip_thermal_probe(struct - if (IS_ERR(thermal->regs)) - return PTR_ERR(thermal->regs); - -- thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); -+ thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false); - if (IS_ERR(thermal->reset)) { - error = PTR_ERR(thermal->reset); - dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); diff --git a/target/linux/rockchip/patches-5.10/008-0006-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch b/target/linux/rockchip/patches-5.10/008-0006-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch deleted file mode 100644 index 456237fa4..000000000 --- a/target/linux/rockchip/patches-5.10/008-0006-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 4d94b98f2e2407e3f053b2546f86c76179fea644 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sun, 29 Aug 2021 04:51:53 +0200 -Subject: [PATCH] mfd: rk808: Add support for power off on RK817 - -RK817 has a power-off bit in SYS_CFG3. Add support for powering -off the PMIC. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Lee Jones ---- - drivers/mfd/rk808.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mfd/rk808.c -+++ b/drivers/mfd/rk808.c -@@ -462,6 +462,10 @@ static void rk808_pm_power_off(void) - reg = RK808_DEVCTRL_REG, - bit = DEV_OFF_RST; - break; -+ case RK817_ID: -+ reg = RK817_SYS_CFG(3); -+ bit = DEV_OFF; -+ break; - case RK818_ID: - reg = RK818_DEVCTRL_REG; - bit = DEV_OFF; diff --git a/target/linux/rockchip/patches-5.10/008-0007-v5.17-phy-phy-rockchip-inno-usb2-support-address_cells-2.patch b/target/linux/rockchip/patches-5.10/008-0007-v5.17-phy-phy-rockchip-inno-usb2-support-address_cells-2.patch deleted file mode 100644 index 8ee043d5d..000000000 --- a/target/linux/rockchip/patches-5.10/008-0007-v5.17-phy-phy-rockchip-inno-usb2-support-address_cells-2.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 9c19c531dc98d7ba49b44802a607042e763ebe21 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 15 Dec 2021 16:02:47 -0500 -Subject: [PATCH] phy: phy-rockchip-inno-usb2: support #address_cells = 2 - -New Rockchip devices have the usb phy nodes as standalone devices. -These nodes have register nodes with #address_cells = 2, but only use 32 -bit addresses. - -Adjust the driver to check if the returned address is "0", and adjust -the index in that case. - -Signed-off-by: Peter Geis -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++- - 1 file changed, 10 insertions(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1098,12 +1098,21 @@ static int rockchip_usb2phy_probe(struct - rphy->usbgrf = NULL; - } - -- if (of_property_read_u32(np, "reg", ®)) { -+ if (of_property_read_u32_index(np, "reg", 0, ®)) { - dev_err(dev, "the reg property is not assigned in %pOFn node\n", - np); - return -EINVAL; - } - -+ /* support address_cells=2 */ -+ if (reg == 0) { -+ if (of_property_read_u32_index(np, "reg", 1, ®)) { -+ dev_err(dev, "the reg property is not assigned in %pOFn node\n", -+ np); -+ return -EINVAL; -+ } -+ } -+ - rphy->dev = dev; - phy_cfgs = match->data; - rphy->chg_state = USB_CHG_STATE_UNDEFINED; diff --git a/target/linux/rockchip/patches-5.10/008-0008-v5.17-phy-phy-rockchip-inno-usb2-support-muxed-interrupts.patch b/target/linux/rockchip/patches-5.10/008-0008-v5.17-phy-phy-rockchip-inno-usb2-support-muxed-interrupts.patch deleted file mode 100644 index e1bfabdf7..000000000 --- a/target/linux/rockchip/patches-5.10/008-0008-v5.17-phy-phy-rockchip-inno-usb2-support-muxed-interrupts.patch +++ /dev/null @@ -1,237 +0,0 @@ -From ed2b5a8e6b98d042b323afbe177a5dc618921b31 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 15 Dec 2021 16:02:49 -0500 -Subject: [PATCH] phy: phy-rockchip-inno-usb2: support muxed interrupts - -The rk3568 usb2phy has a single muxed interrupt that handles all -interrupts. -Allow the driver to plug in only a single interrupt as necessary. - -Signed-off-by: Peter Geis -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 168 +++++++++++++----- - 1 file changed, 119 insertions(+), 49 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -204,6 +204,7 @@ struct rockchip_usb2phy_port { - * @dcd_retries: The retry count used to track Data contact - * detection process. - * @edev: extcon device for notification registration -+ * @irq: muxed interrupt for single irq configuration - * @phy_cfg: phy register configuration, assigned by driver data. - * @ports: phy port instance. - */ -@@ -218,6 +219,7 @@ struct rockchip_usb2phy { - enum power_supply_type chg_type; - u8 dcd_retries; - struct extcon_dev *edev; -+ int irq; - const struct rockchip_usb2phy_cfg *phy_cfg; - struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS]; - }; -@@ -934,6 +936,102 @@ static irqreturn_t rockchip_usb2phy_otg_ - return IRQ_NONE; - } - -+static irqreturn_t rockchip_usb2phy_irq(int irq, void *data) -+{ -+ struct rockchip_usb2phy *rphy = data; -+ struct rockchip_usb2phy_port *rport; -+ irqreturn_t ret = IRQ_NONE; -+ unsigned int index; -+ -+ for (index = 0; index < rphy->phy_cfg->num_ports; index++) { -+ rport = &rphy->ports[index]; -+ if (!rport->phy) -+ continue; -+ -+ /* Handle linestate irq for both otg port and host port */ -+ ret = rockchip_usb2phy_linestate_irq(irq, rport); -+ } -+ -+ return ret; -+} -+ -+static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy, -+ struct rockchip_usb2phy_port *rport, -+ struct device_node *child_np) -+{ -+ int ret; -+ -+ /* -+ * If the usb2 phy used combined irq for otg and host port, -+ * don't need to init otg and host port irq separately. -+ */ -+ if (rphy->irq > 0) -+ return 0; -+ -+ switch (rport->port_id) { -+ case USB2PHY_PORT_HOST: -+ rport->ls_irq = of_irq_get_byname(child_np, "linestate"); -+ if (rport->ls_irq < 0) { -+ dev_err(rphy->dev, "no linestate irq provided\n"); -+ return rport->ls_irq; -+ } -+ -+ ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, -+ rockchip_usb2phy_linestate_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy", rport); -+ if (ret) { -+ dev_err(rphy->dev, "failed to request linestate irq handle\n"); -+ return ret; -+ } -+ break; -+ case USB2PHY_PORT_OTG: -+ /* -+ * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate -+ * interrupts muxed together, so probe the otg-mux interrupt first, -+ * if not found, then look for the regular interrupts one by one. -+ */ -+ rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); -+ if (rport->otg_mux_irq > 0) { -+ ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, -+ NULL, -+ rockchip_usb2phy_otg_mux_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy_otg", -+ rport); -+ if (ret) { -+ dev_err(rphy->dev, -+ "failed to request otg-mux irq handle\n"); -+ return ret; -+ } -+ } else { -+ rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); -+ if (rport->bvalid_irq < 0) { -+ dev_err(rphy->dev, "no vbus valid irq provided\n"); -+ ret = rport->bvalid_irq; -+ return ret; -+ } -+ -+ ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, -+ NULL, -+ rockchip_usb2phy_bvalid_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy_bvalid", -+ rport); -+ if (ret) { -+ dev_err(rphy->dev, -+ "failed to request otg-bvalid irq handle\n"); -+ return ret; -+ } -+ } -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ - static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, - struct rockchip_usb2phy_port *rport, - struct device_node *child_np) -@@ -947,18 +1045,9 @@ static int rockchip_usb2phy_host_port_in - mutex_init(&rport->mutex); - INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work); - -- rport->ls_irq = of_irq_get_byname(child_np, "linestate"); -- if (rport->ls_irq < 0) { -- dev_err(rphy->dev, "no linestate irq provided\n"); -- return rport->ls_irq; -- } -- -- ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, -- rockchip_usb2phy_linestate_irq, -- IRQF_ONESHOT, -- "rockchip_usb2phy", rport); -+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np); - if (ret) { -- dev_err(rphy->dev, "failed to request linestate irq handle\n"); -+ dev_err(rphy->dev, "failed to setup host irq\n"); - return ret; - } - -@@ -1007,44 +1096,10 @@ static int rockchip_usb2phy_otg_port_ini - INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work); - INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work); - -- /* -- * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate -- * interrupts muxed together, so probe the otg-mux interrupt first, -- * if not found, then look for the regular interrupts one by one. -- */ -- rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); -- if (rport->otg_mux_irq > 0) { -- ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, -- NULL, -- rockchip_usb2phy_otg_mux_irq, -- IRQF_ONESHOT, -- "rockchip_usb2phy_otg", -- rport); -- if (ret) { -- dev_err(rphy->dev, -- "failed to request otg-mux irq handle\n"); -- goto out; -- } -- } else { -- rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); -- if (rport->bvalid_irq < 0) { -- dev_err(rphy->dev, "no vbus valid irq provided\n"); -- ret = rport->bvalid_irq; -- goto out; -- } -- -- ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, -- NULL, -- rockchip_usb2phy_bvalid_irq, -- IRQF_ONESHOT, -- "rockchip_usb2phy_bvalid", -- rport); -- if (ret) { -- dev_err(rphy->dev, -- "failed to request otg-bvalid irq handle\n"); -- goto out; -- } -- } -+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np); -+ if (ret) { -+ dev_err(rphy->dev, "failed to init irq for host port\n"); -+ goto out; - - if (!IS_ERR(rphy->edev)) { - rport->event_nb.notifier_call = rockchip_otg_event; -@@ -1117,6 +1172,7 @@ static int rockchip_usb2phy_probe(struct - phy_cfgs = match->data; - rphy->chg_state = USB_CHG_STATE_UNDEFINED; - rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; -+ rphy->irq = platform_get_irq_optional(pdev, 0); - platform_set_drvdata(pdev, rphy); - - ret = rockchip_usb2phy_extcon_register(rphy); -@@ -1194,6 +1250,20 @@ next_child: - } - - provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ if (rphy->irq > 0) { -+ ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL, -+ rockchip_usb2phy_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy", -+ rphy); -+ if (ret) { -+ dev_err(rphy->dev, -+ "failed to request usb2phy irq handle\n"); -+ goto put_child; -+ } -+ } -+ - return PTR_ERR_OR_ZERO(provider); - - put_child: diff --git a/target/linux/rockchip/patches-5.10/008-0009-v5.17-phy-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch b/target/linux/rockchip/patches-5.10/008-0009-v5.17-phy-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch deleted file mode 100644 index 4a6f282c6..000000000 --- a/target/linux/rockchip/patches-5.10/008-0009-v5.17-phy-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch +++ /dev/null @@ -1,44 +0,0 @@ -From e6915e1acca57bc4fdb61dccd5cc2e49f72ef743 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 15 Dec 2021 16:02:48 -0500 -Subject: [PATCH] phy: phy-rockchip-inno-usb2: support standalone phy nodes - -New Rockchip devices have the usb2 phy devices as standalone nodes -instead of children of the grf node. -Allow the driver to find the grf node from a phandle. - -Signed-off-by: Peter Geis -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 17 ++++++++++++----- - 1 file changed, 12 insertions(+), 5 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1136,12 +1136,19 @@ static int rockchip_usb2phy_probe(struct - return -EINVAL; - } - -- if (!dev->parent || !dev->parent->of_node) -- return -EINVAL; -+ if (!dev->parent || !dev->parent->of_node) { -+ rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf"); -+ if (IS_ERR(rphy->grf)) { -+ dev_err(dev, "failed to locate usbgrf\n"); -+ return PTR_ERR(rphy->grf); -+ } -+ } - -- rphy->grf = syscon_node_to_regmap(dev->parent->of_node); -- if (IS_ERR(rphy->grf)) -- return PTR_ERR(rphy->grf); -+ else { -+ rphy->grf = syscon_node_to_regmap(dev->parent->of_node); -+ if (IS_ERR(rphy->grf)) -+ return PTR_ERR(rphy->grf); -+ } - - if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) { - rphy->usbgrf = diff --git a/target/linux/rockchip/patches-5.10/008-0010-v5.17-phy-phy-rockchip-inno-usb2-add-rk3568-support.patch b/target/linux/rockchip/patches-5.10/008-0010-v5.17-phy-phy-rockchip-inno-usb2-add-rk3568-support.patch deleted file mode 100644 index 0ef6d4293..000000000 --- a/target/linux/rockchip/patches-5.10/008-0010-v5.17-phy-phy-rockchip-inno-usb2-add-rk3568-support.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 42b559727a45d79c811f493515eb9b7e56016421 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 15 Dec 2021 16:02:50 -0500 -Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3568 support - -The rk3568 usb2phy is a standalone device with a single muxed interrupt. -Add support for the registers to the usb2phy driver. - -Signed-off-by: Peter Geis -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 65 +++++++++++++++++++ - 1 file changed, 65 insertions(+) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1100,6 +1100,7 @@ static int rockchip_usb2phy_otg_port_ini - if (ret) { - dev_err(rphy->dev, "failed to init irq for host port\n"); - goto out; -+ } - - if (!IS_ERR(rphy->edev)) { - rport->event_nb.notifier_call = rockchip_otg_event; -@@ -1466,6 +1467,69 @@ static const struct rockchip_usb2phy_cfg - { /* sentinel */ } - }; - -+static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { -+ { -+ .reg = 0xfe8a0000, -+ .num_ports = 2, -+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_OTG] = { -+ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, -+ .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, -+ .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, -+ .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, -+ .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, -+ .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, -+ }, -+ [USB2PHY_PORT_HOST] = { -+ /* Select suspend control from controller */ -+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 }, -+ .ls_det_en = { 0x0080, 1, 1, 0, 1 }, -+ .ls_det_st = { 0x0084, 1, 1, 0, 1 }, -+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, -+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, -+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } -+ } -+ }, -+ .chg_det = { -+ .opmode = { 0x0000, 3, 0, 5, 1 }, -+ .cp_det = { 0x00c0, 24, 24, 0, 1 }, -+ .dcp_det = { 0x00c0, 23, 23, 0, 1 }, -+ .dp_det = { 0x00c0, 25, 25, 0, 1 }, -+ .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, -+ .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, -+ .idp_src_en = { 0x0008, 9, 9, 0, 1 }, -+ .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, -+ .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, -+ .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, -+ }, -+ }, -+ { -+ .reg = 0xfe8b0000, -+ .num_ports = 2, -+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_OTG] = { -+ .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, -+ .ls_det_en = { 0x0080, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x0084, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, -+ .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, -+ .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } -+ }, -+ [USB2PHY_PORT_HOST] = { -+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, -+ .ls_det_en = { 0x0080, 1, 1, 0, 1 }, -+ .ls_det_st = { 0x0084, 1, 1, 0, 1 }, -+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, -+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, -+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } -+ } -+ }, -+ }, -+ { /* sentinel */ } -+}; -+ - static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { - { - .reg = 0x100, -@@ -1514,6 +1578,7 @@ static const struct of_device_id rockchi - { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, - { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, - { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, -+ { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, - { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, - {} - }; diff --git a/target/linux/rockchip/patches-5.10/008-0011-v5.18-clk-rockchip-Add-more-PLL-rates-for-rk3568.patch b/target/linux/rockchip/patches-5.10/008-0011-v5.18-clk-rockchip-Add-more-PLL-rates-for-rk3568.patch deleted file mode 100644 index 93323ff6b..000000000 --- a/target/linux/rockchip/patches-5.10/008-0011-v5.18-clk-rockchip-Add-more-PLL-rates-for-rk3568.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 842f4cb7263953020f4e2f2f0005fc3e6fc56144 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Wed, 26 Jan 2022 15:55:33 +0100 -Subject: [PATCH] clk: rockchip: Add more PLL rates for rk3568 - -This adds a few more PLL settings needed for some standard resolutions: - -297MHz 3840x2160-30.00 -241.5MHz 2560x1440-59.95 -135MHz 1280x1024-75.02 -119MHz 1680x1050-59.88 -108MHz 1280x1024-60.02 - 78.75MHz 1024x768-75.03 - -Changes since v3: -- new patch - -Signed-off-by: Sascha Hauer -Link: https://lore.kernel.org/r/20220126145549.617165-12-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3568.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -71,11 +71,17 @@ static struct rockchip_pll_rate_table rk - RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), - RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), - RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), -+ RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0), -+ RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0), - RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), - RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), - RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), -+ RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), -+ RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), -+ RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), - RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), - RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), -+ RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0), - RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), - { /* sentinel */ }, - }; diff --git a/target/linux/rockchip/patches-5.10/008-0012-v5.18-clk-rockchip-Add-CLK_SET_RATE_PARENT-to-the-HDMI-referenc.patch b/target/linux/rockchip/patches-5.10/008-0012-v5.18-clk-rockchip-Add-CLK_SET_RATE_PARENT-to-the-HDMI-referenc.patch deleted file mode 100644 index 890fe0897..000000000 --- a/target/linux/rockchip/patches-5.10/008-0012-v5.18-clk-rockchip-Add-CLK_SET_RATE_PARENT-to-the-HDMI-referenc.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 6e69052f01d9131388cfcfaee929120118a267f4 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Wed, 26 Jan 2022 15:55:47 +0100 -Subject: [PATCH] clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference - clock on rk3568 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -On the rk3568 we have this (simplified) situation: - - .--------. .-----. .---------. --| hpll |--.--| /n |----|dclk_vop0|- - `--------´ | `-----´ `---------´ - | .-----. .---------. - `--| /m |----|dclk_vop1|- - | `-----´ `---------´ - | .---------. - `-------------|hdmi_ref |- - `---------´ - -For the HDMI to work the HDMI reference clock needs to be the same as the -pixel clock which means the dividers have be set to one. The last patch removed -the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not -changed on pixel clock changes. In order to allow the HDMI controller to -set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the -HDMI reference clock. With this the flow becomes: - -1) HDMI controller driver sets the rate to its pixel clock which means - hpll is set to the pixel clock -2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change - the hpll clock anymore this means only the divider is adjusted to the - desired value of dividing by one. - -Signed-off-by: Sascha Hauer -Link: https://lore.kernel.org/r/20220126145549.617165-26-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3568.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -1568,7 +1568,7 @@ static struct rockchip_clk_branch rk3568 - RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), - GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, - RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), -- MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, -+ MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, - RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), - }; - diff --git a/target/linux/rockchip/patches-5.10/008-0013-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch b/target/linux/rockchip/patches-5.10/008-0013-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch deleted file mode 100644 index 117f08b32..000000000 --- a/target/linux/rockchip/patches-5.10/008-0013-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 7160820d742a16313f7802e33c2956c19548e488 Mon Sep 17 00:00:00 2001 -From: Yifeng Zhao -Date: Tue, 8 Feb 2022 17:13:25 +0800 -Subject: [PATCH] phy: rockchip: add naneng combo phy for RK3568 - -This patch implements a combo phy driver for Rockchip SoCs -with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, -sata-phy or sgmii-phy. - -Signed-off-by: Yifeng Zhao -Signed-off-by: Johan Jonker -Tested-by: Peter Geis -Tested-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/Kconfig | 8 + - drivers/phy/rockchip/Makefile | 1 + - .../rockchip/phy-rockchip-naneng-combphy.c | 581 ++++++++++++++++++ - 3 files changed, 590 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c - ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -56,6 +56,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY - Enable this to support the Rockchip MIPI/LVDS/TTL PHY with - Innosilicon IP block. - -+config PHY_ROCKCHIP_NANENG_COMBO_PHY -+ tristate "Rockchip NANENG COMBO PHY Driver" -+ depends on ARCH_ROCKCHIP && OF -+ select GENERIC_PHY -+ help -+ Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII -+ combo PHY with NaNeng IP block. -+ - config PHY_ROCKCHIP_PCIE - tristate "Rockchip PCIe PHY Driver" - depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy- - obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o -+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/target/linux/rockchip/patches-5.10/008-0014-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch b/target/linux/rockchip/patches-5.10/008-0014-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch deleted file mode 100644 index 608330f15..000000000 --- a/target/linux/rockchip/patches-5.10/008-0014-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch +++ /dev/null @@ -1,54 +0,0 @@ -From c4313e75001492f8a288d3ffd595544cbc880821 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sat, 5 Mar 2022 16:58:34 -0500 -Subject: [PATCH] mmc: dw_mmc: Support setting f_min from host drivers - -Host drivers may not be able to support frequencies as low as dw-mmc -supports. Unfortunately f_min isn't available when the drv_data->init -function is called, as the mmc_host struct hasn't been set up yet. - -Support the host drivers saving the requested minimum frequency, so we -can later set f_min when it is available. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220305215835.2210388-2-pgwipeout@gmail.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/dw_mmc.c | 7 ++++++- - drivers/mmc/host/dw_mmc.h | 2 ++ - 2 files changed, 8 insertions(+), 1 deletion(-) - ---- a/drivers/mmc/host/dw_mmc.c -+++ b/drivers/mmc/host/dw_mmc.c -@@ -2776,7 +2776,12 @@ static int dw_mci_init_slot_caps(struct - if (host->pdata->caps2) - mmc->caps2 = host->pdata->caps2; - -- mmc->f_min = DW_MCI_FREQ_MIN; -+ /* if host has set a minimum_freq, we should respect it */ -+ if (host->minimum_speed) -+ mmc->f_min = host->minimum_speed; -+ else -+ mmc->f_min = DW_MCI_FREQ_MIN; -+ - if (!mmc->f_max) - mmc->f_max = DW_MCI_FREQ_MAX; - ---- a/drivers/mmc/host/dw_mmc.h -+++ b/drivers/mmc/host/dw_mmc.h -@@ -97,6 +97,7 @@ struct dw_mci_dma_slave { - * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus - * rate and timeout calculations. - * @current_speed: Configured rate of the controller. -+ * @minimum_speed: Stored minimum rate of the controller. - * @fifoth_val: The value of FIFOTH register. - * @verid: Denote Version ID. - * @dev: Device associated with the MMC controller. -@@ -198,6 +199,7 @@ struct dw_mci { - - u32 bus_hz; - u32 current_speed; -+ u32 minimum_speed; - u32 fifoth_val; - u16 verid; - struct device *dev; diff --git a/target/linux/rockchip/patches-5.10/008-0015-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch b/target/linux/rockchip/patches-5.10/008-0015-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch deleted file mode 100644 index f86a6cdf0..000000000 --- a/target/linux/rockchip/patches-5.10/008-0015-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 52c92286b71e28d88642a4a416f40fbdb6cbb46f Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sat, 5 Mar 2022 16:58:35 -0500 -Subject: [PATCH] mmc: dw-mmc-rockchip: Fix handling invalid clock rates - -The Rockchip rk356x ciu clock cannot be set as low as the dw-mmc -hardware supports. This leads to a situation during card initialization -where the clock is set lower than the clock driver can support. The -dw-mmc-rockchip driver spews errors when this happens. -For normal operation this only happens a few times during boot, but when -cd-broken is enabled (in cases such as the SoQuartz module) this fires -multiple times each poll cycle. - -Fix this by testing the lowest possible frequency that the clock driver -can support which is within the mmc specification. Divide that rate by -the internal divider and set f_min to this. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220305215835.2210388-3-pgwipeout@gmail.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++---- - 1 file changed, 23 insertions(+), 4 deletions(-) - ---- a/drivers/mmc/host/dw_mmc-rockchip.c -+++ b/drivers/mmc/host/dw_mmc-rockchip.c -@@ -15,7 +15,9 @@ - #include "dw_mmc.h" - #include "dw_mmc-pltfm.h" - --#define RK3288_CLKGEN_DIV 2 -+#define RK3288_CLKGEN_DIV 2 -+ -+static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 }; - - struct dw_mci_rockchip_priv_data { - struct clk *drv_clk; -@@ -51,7 +53,7 @@ static void dw_mci_rk3288_set_ios(struct - - ret = clk_set_rate(host->ciu_clk, cclkin); - if (ret) -- dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); -+ dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret); - - bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; - if (bus_hz != host->bus_hz) { -@@ -290,13 +292,30 @@ static int dw_mci_rk3288_parse_dt(struct - - static int dw_mci_rockchip_init(struct dw_mci *host) - { -+ int ret, i; -+ - /* It is slot 8 on Rockchip SoCs */ - host->sdio_id0 = 8; - -- if (of_device_is_compatible(host->dev->of_node, -- "rockchip,rk3288-dw-mshc")) -+ if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) { - host->bus_hz /= RK3288_CLKGEN_DIV; - -+ /* clock driver will fail if the clock is less than the lowest source clock -+ * divided by the internal clock divider. Test for the lowest available -+ * clock and set the minimum freq to clock / clock divider. -+ */ -+ -+ for (i = 0; i < ARRAY_SIZE(freqs); i++) { -+ ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV); -+ if (ret > 0) { -+ host->minimum_speed = ret / RK3288_CLKGEN_DIV; -+ break; -+ } -+ } -+ if (ret < 0) -+ dev_warn(host->dev, "no valid minimum freq: %d\n", ret); -+ } -+ - return 0; - } - diff --git a/target/linux/rockchip/patches-5.10/008-0016-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch b/target/linux/rockchip/patches-5.10/008-0016-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch deleted file mode 100644 index 7b4c28a26..000000000 --- a/target/linux/rockchip/patches-5.10/008-0016-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 56f216d8efbc1212bf5ff8a6ff5e29927965e8db Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 8 Feb 2022 14:40:23 -0500 -Subject: [PATCH] mfd: rk808: Add reboot support to rk808.c - -This adds reboot support to the rk808 pmic driver and enables it for -the rk809 and rk817 devices. -This only enables if the rockchip,system-power-controller flag is set. - -Signed-off-by: Peter Geis -Signed-off-by: Frank Wunderlich -Reviewed-by: Dmitry Osipenko -Signed-off-by: Lee Jones -Link: https://lore.kernel.org/r/20220208194023.929720-1-pgwipeout@gmail.com ---- - drivers/mfd/rk808.c | 44 +++++++++++++++++++++++++++++++++++++++ - include/linux/mfd/rk808.h | 1 + - 2 files changed, 45 insertions(+) - ---- a/drivers/mfd/rk808.c -+++ b/drivers/mfd/rk808.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - struct rk808_reg_data { - int addr; -@@ -462,6 +463,7 @@ static void rk808_pm_power_off(void) - reg = RK808_DEVCTRL_REG, - bit = DEV_OFF_RST; - break; -+ case RK809_ID: - case RK817_ID: - reg = RK817_SYS_CFG(3); - bit = DEV_OFF; -@@ -478,6 +480,34 @@ static void rk808_pm_power_off(void) - dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n"); - } - -+static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd) -+{ -+ struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); -+ unsigned int reg, bit; -+ int ret; -+ -+ switch (rk808->variant) { -+ case RK809_ID: -+ case RK817_ID: -+ reg = RK817_SYS_CFG(3); -+ bit = DEV_RST; -+ break; -+ -+ default: -+ return NOTIFY_DONE; -+ } -+ ret = regmap_update_bits(rk808->regmap, reg, bit, bit); -+ if (ret) -+ dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n"); -+ -+ return NOTIFY_DONE; -+} -+ -+static struct notifier_block rk808_restart_handler = { -+ .notifier_call = rk808_restart_notify, -+ .priority = 192, -+}; -+ - static void rk8xx_shutdown(struct i2c_client *client) - { - struct rk808 *rk808 = i2c_get_clientdata(client); -@@ -646,6 +676,18 @@ static int rk808_probe(struct i2c_client - if (of_property_read_bool(np, "rockchip,system-power-controller")) { - rk808_i2c_client = client; - pm_power_off = rk808_pm_power_off; -+ -+ switch (rk808->variant) { -+ case RK809_ID: -+ case RK817_ID: -+ ret = register_restart_handler(&rk808_restart_handler); -+ if (ret) -+ dev_warn(&client->dev, "failed to register rst handler, %d\n", ret); -+ break; -+ default: -+ dev_dbg(&client->dev, "pmic controlled board reset not supported\n"); -+ break; -+ } - } - - return 0; -@@ -668,6 +710,8 @@ static int rk808_remove(struct i2c_clien - if (pm_power_off == rk808_pm_power_off) - pm_power_off = NULL; - -+ unregister_restart_handler(&rk808_restart_handler); -+ - return 0; - } - ---- a/include/linux/mfd/rk808.h -+++ b/include/linux/mfd/rk808.h -@@ -373,6 +373,7 @@ enum rk805_reg { - #define SWITCH2_EN BIT(6) - #define SWITCH1_EN BIT(5) - #define DEV_OFF_RST BIT(3) -+#define DEV_RST BIT(2) - #define DEV_OFF BIT(0) - #define RTC_STOP BIT(0) - diff --git a/target/linux/rockchip/patches-5.10/008-0017-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch b/target/linux/rockchip/patches-5.10/008-0017-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch deleted file mode 100644 index f2288c752..000000000 --- a/target/linux/rockchip/patches-5.10/008-0017-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 5c0bb71138770d85ea840acd379edc6471b867ee Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Fri, 8 Apr 2022 11:12:34 -0400 -Subject: [PATCH] soc: rockchip: set dwc3 clock for rk3566 - -The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to -the combophy as the clock source. As combophy0 doesn't exist on rk3566, -we need to set the clock source to the usb2 phy instead. - -Add handling to the grf driver to handle this on boot. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - drivers/soc/rockchip/grf.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/soc/rockchip/grf.c -+++ b/drivers/soc/rockchip/grf.c -@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk - .num_values = ARRAY_SIZE(rk3399_defaults), - }; - -+#define RK3566_GRF_USB3OTG0_CON1 0x0104 -+ -+static const struct rockchip_grf_value rk3566_defaults[] __initconst = { -+ { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) }, -+ { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) }, -+ { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) }, -+}; -+ -+static const struct rockchip_grf_info rk3566_pipegrf __initconst = { -+ .values = rk3566_defaults, -+ .num_values = ARRAY_SIZE(rk3566_defaults), -+}; -+ -+ - static const struct of_device_id rockchip_grf_dt_match[] __initconst = { - { - .compatible = "rockchip,rk3036-grf", -@@ -130,6 +144,9 @@ static const struct of_device_id rockchi - }, { - .compatible = "rockchip,rk3399-grf", - .data = (void *)&rk3399_grf, -+ }, { -+ .compatible = "rockchip,rk3566-pipe-grf", -+ .data = (void *)&rk3566_pipegrf, - }, - { /* sentinel */ }, - }; diff --git a/target/linux/rockchip/patches-5.10/008-0018-v5.19-media-hantro-Add-support-for-Hantro-G1-on-RK356x.patch b/target/linux/rockchip/patches-5.10/008-0018-v5.19-media-hantro-Add-support-for-Hantro-G1-on-RK356x.patch deleted file mode 100644 index f6377dce7..000000000 --- a/target/linux/rockchip/patches-5.10/008-0018-v5.19-media-hantro-Add-support-for-Hantro-G1-on-RK356x.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 5f6bfab6da6531238e899fdf29efd6d0185adc3e Mon Sep 17 00:00:00 2001 -From: Piotr Oniszczuk -Date: Mon, 14 Feb 2022 21:29:53 +0000 -Subject: [PATCH] media: hantro: Add support for Hantro G1 on RK356x - -RK356x has Hantro G1 video decoder capable to decode MPEG2/H.264/VP8 -video formats. - -This patch adds support for RK356x family in existing Hantro -video decoder kernel driver. - -Tested on [1] with FFmpeg v4l2_request code taken from [2] -with MPEG2, H.642 and VP8 samples with results [3]. - -[1] https://github.com/warpme/minimyth2 -[2] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch -[3] https://github.com/warpme/minimyth2/blob/master/video-test-summary.txt - -Signed-off-by: Piotr Oniszczuk -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/hantro/hantro_drv.c | 1 + - drivers/staging/media/hantro/hantro_hw.h | 1 + - drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 ++++++++++++++ - 3 files changed, 16 insertions(+) - ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -486,6 +486,7 @@ static const struct of_device_id of_hant - { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, - { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, }, - { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, -+ { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, - #endif - #ifdef CONFIG_VIDEO_HANTRO_IMX8M - { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -153,6 +153,7 @@ enum hantro_enc_fmt { - extern const struct hantro_variant rk3399_vpu_variant; - extern const struct hantro_variant rk3328_vpu_variant; - extern const struct hantro_variant rk3288_vpu_variant; -+extern const struct hantro_variant rk3568_vpu_variant; - extern const struct hantro_variant imx8mq_vpu_variant; - - extern const struct hantro_postproc_regs hantro_g1_postproc_regs; ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -551,6 +551,20 @@ const struct hantro_variant rk3399_vpu_v - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; - -+const struct hantro_variant rk3568_vpu_variant = { -+ .dec_offset = 0x400, -+ .dec_fmts = rk3399_vpu_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -+ .codec = HANTRO_MPEG2_DECODER | -+ HANTRO_VP8_DECODER | HANTRO_H264_DECODER, -+ .codec_ops = rk3399_vpu_codec_ops, -+ .irqs = rockchip_vdpu2_irqs, -+ .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), -+ .init = rockchip_vpu_hw_init, -+ .clk_names = rockchip_vpu_clk_names, -+ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) -+}; -+ - const struct hantro_variant px30_vpu_variant = { - .enc_offset = 0x0, - .enc_fmts = rockchip_vpu_enc_fmts, diff --git a/target/linux/rockchip/patches-5.10/008-0019-v5.19-phy-rockchip-inno-usb2-Fix-muxed-interrupt-support.patch b/target/linux/rockchip/patches-5.10/008-0019-v5.19-phy-rockchip-inno-usb2-Fix-muxed-interrupt-support.patch deleted file mode 100644 index ba6b6c5ea..000000000 --- a/target/linux/rockchip/patches-5.10/008-0019-v5.19-phy-rockchip-inno-usb2-Fix-muxed-interrupt-support.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 6a98df08ccd55e87947d253b19925691763e755c Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:52 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Fix muxed interrupt support - -This commit fixes two issues with the muxed interrupt handler. First, -the OTG port has the "bvalid" interrupt enabled, not "linestate". Since -only the linestate interrupt was handled, and not the bvalid interrupt, -plugging in a cable to the OTG port caused an interrupt storm. - -Second, the return values from the individual port IRQ handlers need to -be OR-ed together. Otherwise, the lack of an interrupt from the last -port would cause the handler to erroneously return IRQ_NONE. - -Fixes: ed2b5a8e6b98 ("phy: phy-rockchip-inno-usb2: support muxed interrupts") -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-2-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -948,8 +948,14 @@ static irqreturn_t rockchip_usb2phy_irq( - if (!rport->phy) - continue; - -- /* Handle linestate irq for both otg port and host port */ -- ret = rockchip_usb2phy_linestate_irq(irq, rport); -+ switch (rport->port_id) { -+ case USB2PHY_PORT_OTG: -+ ret |= rockchip_usb2phy_otg_mux_irq(irq, rport); -+ break; -+ case USB2PHY_PORT_HOST: -+ ret |= rockchip_usb2phy_linestate_irq(irq, rport); -+ break; -+ } - } - - return ret; diff --git a/target/linux/rockchip/patches-5.10/008-0020-v5.19-phy-rockchip-inno-usb2-Do-not-check-bvalid-twice.patch b/target/linux/rockchip/patches-5.10/008-0020-v5.19-phy-rockchip-inno-usb2-Do-not-check-bvalid-twice.patch deleted file mode 100644 index 8ee9bccde..000000000 --- a/target/linux/rockchip/patches-5.10/008-0020-v5.19-phy-rockchip-inno-usb2-Do-not-check-bvalid-twice.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 656f7fcb1272df590e10cb82e07cd2b79bbf60d1 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:53 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Do not check bvalid twice - -The bvalid interrupt handler already checks bvalid status. The muxed IRQ -handler just needs to call the other handler (plus any other handlers -that will be added). - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-3-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++------ - 1 file changed, 4 insertions(+), 6 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -927,13 +927,11 @@ static irqreturn_t rockchip_usb2phy_bval - - static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) - { -- struct rockchip_usb2phy_port *rport = data; -- struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); -+ irqreturn_t ret = IRQ_NONE; - -- if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) -- return rockchip_usb2phy_bvalid_irq(irq, data); -- else -- return IRQ_NONE; -+ ret |= rockchip_usb2phy_bvalid_irq(irq, data); -+ -+ return ret; - } - - static irqreturn_t rockchip_usb2phy_irq(int irq, void *data) diff --git a/target/linux/rockchip/patches-5.10/008-0021-v5.19-phy-rockchip-inno-usb2-Do-not-lock-in-bvalid-IRQ-handler.patch b/target/linux/rockchip/patches-5.10/008-0021-v5.19-phy-rockchip-inno-usb2-Do-not-lock-in-bvalid-IRQ-handler.patch deleted file mode 100644 index b6652143c..000000000 --- a/target/linux/rockchip/patches-5.10/008-0021-v5.19-phy-rockchip-inno-usb2-Do-not-lock-in-bvalid-IRQ-handler.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 5a709a46e4270a6130877c052260d9a6d14ac685 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:54 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Do not lock in bvalid IRQ handler - -Clearing the IRQ is atomic, so there is no need to hold the mutex. - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-4-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 ---- - 1 file changed, 4 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -913,13 +913,9 @@ static irqreturn_t rockchip_usb2phy_bval - if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) - return IRQ_NONE; - -- mutex_lock(&rport->mutex); -- - /* clear bvalid detect irq pending status */ - property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true); - -- mutex_unlock(&rport->mutex); -- - rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); - - return IRQ_HANDLED; diff --git a/target/linux/rockchip/patches-5.10/008-0022-v5.19-phy-rockchip-inno-usb2-Support-multi-bit-mask-properties.patch b/target/linux/rockchip/patches-5.10/008-0022-v5.19-phy-rockchip-inno-usb2-Support-multi-bit-mask-properties.patch deleted file mode 100644 index 03538c5b8..000000000 --- a/target/linux/rockchip/patches-5.10/008-0022-v5.19-phy-rockchip-inno-usb2-Support-multi-bit-mask-properties.patch +++ /dev/null @@ -1,29 +0,0 @@ -From ffe597d04db2b75d9c547a2d2e07c268c2a33117 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:55 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Support multi-bit mask properties - -The "bvalid" and "id" interrupts can trigger on either the rising edge -or the falling edge, so each interrupt has two enable bits and two -status bits. This change allows using a single property for both bits, -checking whether either bit is set. - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-5-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -253,7 +253,7 @@ static inline bool property_enabled(stru - return false; - - tmp = (orig & mask) >> reg->bitstart; -- return tmp == reg->enable; -+ return tmp != reg->disable; - } - - static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) diff --git a/target/linux/rockchip/patches-5.10/008-0023-v5.19-phy-rockchip-inno-usb2-Handle-bvalid-falling.patch b/target/linux/rockchip/patches-5.10/008-0023-v5.19-phy-rockchip-inno-usb2-Handle-bvalid-falling.patch deleted file mode 100644 index b8d234e86..000000000 --- a/target/linux/rockchip/patches-5.10/008-0023-v5.19-phy-rockchip-inno-usb2-Handle-bvalid-falling.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 21a470606ed5e8b14980f34cd360595d1cba737f Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:56 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Handle bvalid falling - -Some SoCs have a bvalid falling interrupt, in addition to bvalid rising. -This interrupt can detect OTG cable plugout immediately, so it can avoid -the delay until the next scheduled work. - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-6-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 18 +++++++++--------- - 1 file changed, 9 insertions(+), 9 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1351,9 +1351,9 @@ static const struct rockchip_usb2phy_cfg - .port_cfgs = { - [USB2PHY_PORT_OTG] = { - .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, -- .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, -- .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, -- .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, -+ .bvalid_det_en = { 0x0110, 3, 2, 0, 3 }, -+ .bvalid_det_st = { 0x0114, 3, 2, 0, 3 }, -+ .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 }, - .ls_det_en = { 0x0110, 0, 0, 0, 1 }, - .ls_det_st = { 0x0114, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, -@@ -1475,9 +1475,9 @@ static const struct rockchip_usb2phy_cfg - .port_cfgs = { - [USB2PHY_PORT_OTG] = { - .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, -- .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, -- .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, -- .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, -+ .bvalid_det_en = { 0x0080, 3, 2, 0, 3 }, -+ .bvalid_det_st = { 0x0084, 3, 2, 0, 3 }, -+ .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 }, - .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, - .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, - }, diff --git a/target/linux/rockchip/patches-5.10/008-0024-v5.19-phy-rockchip-inno-usb2-Handle-ID-IRQ.patch b/target/linux/rockchip/patches-5.10/008-0024-v5.19-phy-rockchip-inno-usb2-Handle-ID-IRQ.patch deleted file mode 100644 index 344276848..000000000 --- a/target/linux/rockchip/patches-5.10/008-0024-v5.19-phy-rockchip-inno-usb2-Handle-ID-IRQ.patch +++ /dev/null @@ -1,214 +0,0 @@ -From 51a9b2c03dd3fddc56c2f68740fade2e38a066d0 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 13 Apr 2022 22:22:57 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Handle ID IRQ - -This supports detecting host mode for the OTG port without an extcon. - -The rv1108 properties are not updated due to lack of documentation. - -Signed-off-by: Samuel Holland -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220414032258.40984-7-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 85 +++++++++++++++++++ - 1 file changed, 85 insertions(+) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -116,11 +116,15 @@ struct rockchip_chg_det_reg { - * @bvalid_det_en: vbus valid rise detection enable register. - * @bvalid_det_st: vbus valid rise detection status register. - * @bvalid_det_clr: vbus valid rise detection clear register. -+ * @id_det_en: id detection enable register. -+ * @id_det_st: id detection state register. -+ * @id_det_clr: id detection clear register. - * @ls_det_en: linestate detection enable register. - * @ls_det_st: linestate detection state register. - * @ls_det_clr: linestate detection clear register. - * @utmi_avalid: utmi vbus avalid status register. - * @utmi_bvalid: utmi vbus bvalid status register. -+ * @utmi_id: utmi id state register. - * @utmi_ls: utmi linestate state register. - * @utmi_hstdet: utmi host disconnect register. - */ -@@ -129,11 +133,15 @@ struct rockchip_usb2phy_port_cfg { - struct usb2phy_reg bvalid_det_en; - struct usb2phy_reg bvalid_det_st; - struct usb2phy_reg bvalid_det_clr; -+ struct usb2phy_reg id_det_en; -+ struct usb2phy_reg id_det_st; -+ struct usb2phy_reg id_det_clr; - struct usb2phy_reg ls_det_en; - struct usb2phy_reg ls_det_st; - struct usb2phy_reg ls_det_clr; - struct usb2phy_reg utmi_avalid; - struct usb2phy_reg utmi_bvalid; -+ struct usb2phy_reg utmi_id; - struct usb2phy_reg utmi_ls; - struct usb2phy_reg utmi_hstdet; - }; -@@ -161,6 +169,7 @@ struct rockchip_usb2phy_cfg { - * @suspended: phy suspended flag. - * @vbus_attached: otg device vbus status. - * @bvalid_irq: IRQ number assigned for vbus valid rise detection. -+ * @id_irq: IRQ number assigned for ID pin detection. - * @ls_irq: IRQ number assigned for linestate detection. - * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate - * irqs to one irq in otg-port. -@@ -179,6 +188,7 @@ struct rockchip_usb2phy_port { - bool suspended; - bool vbus_attached; - int bvalid_irq; -+ int id_irq; - int ls_irq; - int otg_mux_irq; - struct mutex mutex; -@@ -426,6 +436,19 @@ static int rockchip_usb2phy_init(struct - if (ret) - goto out; - -+ /* clear id status and enable id detect irq */ -+ ret = property_enable(rphy->grf, -+ &rport->port_cfg->id_det_clr, -+ true); -+ if (ret) -+ goto out; -+ -+ ret = property_enable(rphy->grf, -+ &rport->port_cfg->id_det_en, -+ true); -+ if (ret) -+ goto out; -+ - schedule_delayed_work(&rport->otg_sm_work, - OTG_SCHEDULE_DELAY * 3); - } else { -@@ -921,11 +944,30 @@ static irqreturn_t rockchip_usb2phy_bval - return IRQ_HANDLED; - } - -+static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data) -+{ -+ struct rockchip_usb2phy_port *rport = data; -+ struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); -+ bool id; -+ -+ if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st)) -+ return IRQ_NONE; -+ -+ /* clear id detect irq pending status */ -+ property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true); -+ -+ id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); -+ extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); -+ -+ return IRQ_HANDLED; -+} -+ - static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) - { - irqreturn_t ret = IRQ_NONE; - - ret |= rockchip_usb2phy_bvalid_irq(irq, data); -+ ret |= rockchip_usb2phy_id_irq(irq, data); - - return ret; - } -@@ -1023,6 +1065,25 @@ static int rockchip_usb2phy_port_irq_ini - "failed to request otg-bvalid irq handle\n"); - return ret; - } -+ -+ rport->id_irq = of_irq_get_byname(child_np, "otg-id"); -+ if (rport->id_irq < 0) { -+ dev_err(rphy->dev, "no otg-id irq provided\n"); -+ ret = rport->id_irq; -+ return ret; -+ } -+ -+ ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, -+ NULL, -+ rockchip_usb2phy_id_irq, -+ IRQF_ONESHOT, -+ "rockchip_usb2phy_id", -+ rport); -+ if (ret) { -+ dev_err(rphy->dev, -+ "failed to request otg-id irq handle\n"); -+ return ret; -+ } - } - break; - default: -@@ -1295,10 +1356,14 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, - .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, - .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, -+ .id_det_en = { 0x0680, 6, 5, 0, 3 }, -+ .id_det_st = { 0x0690, 6, 5, 0, 3 }, -+ .id_det_clr = { 0x06a0, 6, 5, 0, 3 }, - .ls_det_en = { 0x0680, 2, 2, 0, 1 }, - .ls_det_st = { 0x0690, 2, 2, 0, 1 }, - .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, - .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, -+ .utmi_id = { 0x0480, 1, 1, 0, 1 }, - .utmi_ls = { 0x0480, 3, 2, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { -@@ -1354,11 +1419,15 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0x0110, 3, 2, 0, 3 }, - .bvalid_det_st = { 0x0114, 3, 2, 0, 3 }, - .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 }, -+ .id_det_en = { 0x0110, 5, 4, 0, 3 }, -+ .id_det_st = { 0x0114, 5, 4, 0, 3 }, -+ .id_det_clr = { 0x0118, 5, 4, 0, 3 }, - .ls_det_en = { 0x0110, 0, 0, 0, 1 }, - .ls_det_st = { 0x0114, 0, 0, 0, 1 }, - .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, - .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, - .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, -+ .utmi_id = { 0x0120, 6, 6, 0, 1 }, - .utmi_ls = { 0x0120, 5, 4, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { -@@ -1416,8 +1485,12 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, - .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, - .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, -+ .id_det_en = { 0xe3c0, 5, 4, 0, 3 }, -+ .id_det_st = { 0xe3e0, 5, 4, 0, 3 }, -+ .id_det_clr = { 0xe3d0, 5, 4, 0, 3 }, - .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, - .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, -+ .utmi_id = { 0xe2ac, 8, 8, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { - .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, -@@ -1451,8 +1524,12 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, - .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, - .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, -+ .id_det_en = { 0xe3c0, 10, 9, 0, 3 }, -+ .id_det_st = { 0xe3e0, 10, 9, 0, 3 }, -+ .id_det_clr = { 0xe3d0, 10, 9, 0, 3 }, - .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, - .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, -+ .utmi_id = { 0xe2ac, 11, 11, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { - .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, -@@ -1478,8 +1555,12 @@ static const struct rockchip_usb2phy_cfg - .bvalid_det_en = { 0x0080, 3, 2, 0, 3 }, - .bvalid_det_st = { 0x0084, 3, 2, 0, 3 }, - .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 }, -+ .id_det_en = { 0x0080, 5, 4, 0, 3 }, -+ .id_det_st = { 0x0084, 5, 4, 0, 3 }, -+ .id_det_clr = { 0x0088, 5, 4, 0, 3 }, - .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, - .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, -+ .utmi_id = { 0x00c0, 6, 6, 0, 1 }, - }, - [USB2PHY_PORT_HOST] = { - /* Select suspend control from controller */ diff --git a/target/linux/rockchip/patches-5.10/008-0025-v5.19-clk-rockchip-Mark-hclk_vo-as-critical-on-rk3568.patch b/target/linux/rockchip/patches-5.10/008-0025-v5.19-clk-rockchip-Mark-hclk_vo-as-critical-on-rk3568.patch deleted file mode 100644 index c49bac1b5..000000000 --- a/target/linux/rockchip/patches-5.10/008-0025-v5.19-clk-rockchip-Mark-hclk_vo-as-critical-on-rk3568.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 6931f85c29d5a0261219cf8a73773d3165806d84 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:18 +0200 -Subject: [PATCH] clk: rockchip: Mark hclk_vo as critical on rk3568 - -Whenever pclk_vo is enabled hclk_vo must be enabled as well. This is -described in the Reference Manual as: - -| 2.8.6 NIU Clock gating reliance -| -| A part of niu clocks have a dependence on another niu clock in order to -| sharing the internal bus. When these clocks are in use, another niu -| clock must be opened, and cannot be gated. These clocks and the special -| clock on which they are relied are as following: -| -| Clocks which have dependency The clock which can not be gated -| ----------------------------------------------------------------- -| ... -| pclk_vo_niu, hclk_vo_s_niu hclk_vo_niu -| ... - -The clock framework doesn't offer a way to enable clock B whenever clock A is -enabled, at least not when B is not an ancestor of A. Workaround this by -marking hclk_vo as critical so it is never disabled. This is suboptimal in -terms of power consumption, but a stop gap solution until the clock framework -has a way to deal with this. - -We have this clock tree: - -| aclk_vo 2 2 0 300000000 0 0 50000 Y -| aclk_hdcp 0 0 0 300000000 0 0 50000 N -| pclk_vo 2 3 0 75000000 0 0 50000 Y -| pclk_edp_ctrl 0 0 0 75000000 0 0 50000 N -| pclk_dsitx_1 0 0 0 75000000 0 0 50000 N -| pclk_dsitx_0 1 2 0 75000000 0 0 50000 Y -| pclk_hdmi_host 1 2 0 75000000 0 0 50000 Y -| pclk_hdcp 0 0 0 75000000 0 0 50000 N -| hclk_vo 2 5 0 150000000 0 0 50000 Y -| hclk_hdcp 0 0 0 150000000 0 0 50000 N -| hclk_vop 0 2 0 150000000 0 0 50000 N - -Without this patch the edp, dsitx, hdmi and hdcp driver would enable their -clocks which then enables pclk_vo, but hclk_vo stays disabled and register -accesses just hang. hclk_vo is enabled by the VOP2 driver, so reproducibility -of this issue depends on the probe order. - -Signed-off-by: Sascha Hauer -Reviewed-by: Dmitry Osipenko -Reviewed-by: Robin Murphy -Tested-by: Michael Riesch -Link: https://lore.kernel.org/r/20220422072841.2206452-2-s.hauer@pengutronix.de -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3568.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -1591,6 +1591,7 @@ static const char *const rk3568_cru_crit - "hclk_php", - "pclk_php", - "hclk_usb", -+ "hclk_vo", - }; - - static const char *const rk3568_pmucru_critical_clocks[] __initconst = { diff --git a/target/linux/rockchip/patches-5.10/008-0026-v5.19-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch b/target/linux/rockchip/patches-5.10/008-0026-v5.19-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch deleted file mode 100644 index a02a405b9..000000000 --- a/target/linux/rockchip/patches-5.10/008-0026-v5.19-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch +++ /dev/null @@ -1,601 +0,0 @@ -From 540b8f271e53362a308f6bf288d38b630cf3fbd2 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:19 +0200 -Subject: [PATCH] drm/rockchip: Embed drm_encoder into rockchip_decoder - -The VOP2 driver needs rockchip specific information for a drm_encoder. - -This patch creates a struct rockchip_encoder with a struct drm_encoder -embedded in it. This is used throughout the rockchip driver instead of -struct drm_encoder directly. - -The information the VOP2 drivers needs is the of_graph endpoint node -of the encoder. To ease bisectability this is added here. - -While at it convert the different encoder-to-driverdata macros to -static inline functions in order to gain type safety and readability. - -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-3-s.hauer@pengutronix.de ---- - .../gpu/drm/rockchip/analogix_dp-rockchip.c | 32 +++++++++++------ - drivers/gpu/drm/rockchip/cdn-dp-core.c | 18 ++++++---- - drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +- - .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 17 ++++++---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 11 ++++-- - drivers/gpu/drm/rockchip/inno_hdmi.c | 32 +++++++++++------ - drivers/gpu/drm/rockchip/rk3066_hdmi.c | 34 ++++++++++++------- - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 10 ++++++ - drivers/gpu/drm/rockchip/rockchip_lvds.c | 26 ++++++++------ - 9 files changed, 122 insertions(+), 60 deletions(-) - ---- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c -+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c -@@ -40,8 +40,6 @@ - - #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 - --#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm) -- - /** - * struct rockchip_dp_chip_data - splite the grf setting of kind of chips - * @lcdsel_grf_reg: grf register offset of lcdc select -@@ -59,7 +57,7 @@ struct rockchip_dp_chip_data { - struct rockchip_dp_device { - struct drm_device *drm_dev; - struct device *dev; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - struct drm_display_mode mode; - - struct clk *pclk; -@@ -73,6 +71,18 @@ struct rockchip_dp_device { - struct analogix_dp_plat_data plat_data; - }; - -+static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_dp_device, encoder); -+} -+ -+static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data) -+{ -+ return container_of(plat_data, struct rockchip_dp_device, plat_data); -+} -+ - static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) - { - reset_control_assert(dp->rst); -@@ -84,7 +94,7 @@ static int rockchip_dp_pre_init(struct r - - static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data) - { -- struct rockchip_dp_device *dp = to_dp(plat_data); -+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); - int ret; - - ret = clk_prepare_enable(dp->pclk); -@@ -105,7 +115,7 @@ static int rockchip_dp_poweron_start(str - - static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) - { -- struct rockchip_dp_device *dp = to_dp(plat_data); -+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); - - clk_disable_unprepare(dp->pclk); - -@@ -166,7 +176,7 @@ struct drm_crtc *rockchip_dp_drm_get_new - static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) - { -- struct rockchip_dp_device *dp = to_dp(encoder); -+ struct rockchip_dp_device *dp = encoder_to_dp(encoder); - struct drm_crtc *crtc; - struct drm_crtc_state *old_crtc_state; - int ret; -@@ -208,7 +218,7 @@ static void rockchip_dp_drm_encoder_enab - static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) - { -- struct rockchip_dp_device *dp = to_dp(encoder); -+ struct rockchip_dp_device *dp = encoder_to_dp(encoder); - struct drm_crtc *crtc; - struct drm_crtc_state *new_crtc_state = NULL; - int ret; -@@ -297,7 +307,7 @@ static int rockchip_dp_of_probe(struct r - - static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp) - { -- struct drm_encoder *encoder = &dp->encoder; -+ struct drm_encoder *encoder = &dp->encoder.encoder; - struct drm_device *drm_dev = dp->drm_dev; - struct device *dev = dp->dev; - int ret; -@@ -333,7 +343,7 @@ static int rockchip_dp_bind(struct devic - return ret; - } - -- dp->plat_data.encoder = &dp->encoder; -+ dp->plat_data.encoder = &dp->encoder.encoder; - - ret = analogix_dp_bind(dp->adp, drm_dev); - if (ret) -@@ -341,7 +351,7 @@ static int rockchip_dp_bind(struct devic - - return 0; - err_cleanup_encoder: -- dp->encoder.funcs->destroy(&dp->encoder); -+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); - return ret; - } - -@@ -351,7 +361,7 @@ static void rockchip_dp_unbind(struct de - struct rockchip_dp_device *dp = dev_get_drvdata(dev); - - analogix_dp_unbind(dp->adp); -- dp->encoder.funcs->destroy(&dp->encoder); -+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); - } - - static const struct component_ops rockchip_dp_component_ops = { ---- a/drivers/gpu/drm/rockchip/cdn-dp-core.c -+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c -@@ -26,11 +26,17 @@ - #include "cdn-dp-reg.h" - #include "rockchip_drm_vop.h" - --#define connector_to_dp(c) \ -- container_of(c, struct cdn_dp_device, connector) -+static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector) -+{ -+ return container_of(connector, struct cdn_dp_device, connector); -+} - --#define encoder_to_dp(c) \ -- container_of(c, struct cdn_dp_device, encoder) -+static inline struct cdn_dp_device *encoder_to_dp(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct cdn_dp_device, encoder); -+} - - #define GRF_SOC_CON9 0x6224 - #define DP_SEL_VOP_LIT BIT(12) -@@ -1023,7 +1029,7 @@ static int cdn_dp_bind(struct device *de - - INIT_WORK(&dp->event_work, cdn_dp_pd_event_work); - -- encoder = &dp->encoder; -+ encoder = &dp->encoder.encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, - dev->of_node); -@@ -1088,7 +1094,7 @@ err_free_encoder: - static void cdn_dp_unbind(struct device *dev, struct device *master, void *data) - { - struct cdn_dp_device *dp = dev_get_drvdata(dev); -- struct drm_encoder *encoder = &dp->encoder; -+ struct drm_encoder *encoder = &dp->encoder.encoder; - struct drm_connector *connector = &dp->connector; - - cancel_work_sync(&dp->event_work); ---- a/drivers/gpu/drm/rockchip/cdn-dp-core.h -+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h -@@ -65,7 +65,7 @@ struct cdn_dp_device { - struct device *dev; - struct drm_device *drm_dev; - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - struct drm_display_mode mode; - struct platform_device *audio_pdev; - struct work_struct event_work; ---- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -@@ -174,8 +174,6 @@ - - #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) - --#define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm) -- - enum { - BANDGAP_97_07, - BANDGAP_98_05, -@@ -219,7 +217,7 @@ struct rockchip_dw_dsi_chip_data { - - struct dw_mipi_dsi_rockchip { - struct device *dev; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - void __iomem *base; - - struct regmap *grf_regmap; -@@ -247,6 +245,13 @@ struct dw_mipi_dsi_rockchip { - bool dsi_bound; - }; - -+static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); -+} -+ - struct dphy_pll_parameter_map { - unsigned int max_mbps; - u8 hsfreqrange; -@@ -751,7 +756,7 @@ static void dw_mipi_dsi_encoder_enable(s - int ret, mux; - - mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, -- &dsi->encoder); -+ &dsi->encoder.encoder); - if (mux < 0) - return; - -@@ -782,7 +787,7 @@ dw_mipi_dsi_encoder_helper_funcs = { - static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, - struct drm_device *drm_dev) - { -- struct drm_encoder *encoder = &dsi->encoder; -+ struct drm_encoder *encoder = &dsi->encoder.encoder; - int ret; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, -@@ -940,7 +945,7 @@ static int dw_mipi_dsi_rockchip_bind(str - goto out_pll_clk; - } - -- ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); -+ ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); - if (ret) { - DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); - goto out_pll_clk; ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -67,7 +67,7 @@ struct rockchip_hdmi_chip_data { - struct rockchip_hdmi { - struct device *dev; - struct regmap *regmap; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; - struct clk *vpll_clk; - struct clk *grf_clk; -@@ -75,7 +75,12 @@ struct rockchip_hdmi { - struct phy *phy; - }; - --#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) -+static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_hdmi, encoder); -+} - - static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - { -@@ -511,7 +516,7 @@ static int dw_hdmi_rockchip_bind(struct - hdmi->dev = &pdev->dev; - hdmi->chip_data = plat_data->phy_data; - plat_data->phy_data = hdmi; -- encoder = &hdmi->encoder; -+ encoder = &hdmi->encoder.encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); - /* ---- a/drivers/gpu/drm/rockchip/inno_hdmi.c -+++ b/drivers/gpu/drm/rockchip/inno_hdmi.c -@@ -26,8 +26,6 @@ - - #include "inno_hdmi.h" - --#define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x) -- - struct hdmi_data_info { - int vic; - bool sink_is_hdmi; -@@ -56,7 +54,7 @@ struct inno_hdmi { - void __iomem *regs; - - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - - struct inno_hdmi_i2c *i2c; - struct i2c_adapter *ddc; -@@ -67,6 +65,18 @@ struct inno_hdmi { - struct drm_display_mode previous_mode; - }; - -+static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct inno_hdmi, encoder); -+} -+ -+static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector) -+{ -+ return container_of(connector, struct inno_hdmi, connector); -+} -+ - enum { - CSC_ITU601_16_235_TO_RGB_0_255_8BIT, - CSC_ITU601_0_255_TO_RGB_0_255_8BIT, -@@ -483,7 +493,7 @@ static void inno_hdmi_encoder_mode_set(s - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); -+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_setup(hdmi, adj_mode); - -@@ -493,14 +503,14 @@ static void inno_hdmi_encoder_mode_set(s - - static void inno_hdmi_encoder_enable(struct drm_encoder *encoder) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); -+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_set_pwr_mode(hdmi, NORMAL); - } - - static void inno_hdmi_encoder_disable(struct drm_encoder *encoder) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); -+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR); - } -@@ -536,7 +546,7 @@ static struct drm_encoder_helper_funcs i - static enum drm_connector_status - inno_hdmi_connector_detect(struct drm_connector *connector, bool force) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(connector); -+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); - - return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? - connector_status_connected : connector_status_disconnected; -@@ -544,7 +554,7 @@ inno_hdmi_connector_detect(struct drm_co - - static int inno_hdmi_connector_get_modes(struct drm_connector *connector) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(connector); -+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); - struct edid *edid; - int ret = 0; - -@@ -599,7 +609,7 @@ static struct drm_connector_helper_funcs - - static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) - { -- struct drm_encoder *encoder = &hdmi->encoder; -+ struct drm_encoder *encoder = &hdmi->encoder.encoder; - struct device *dev = hdmi->dev; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -@@ -881,7 +891,7 @@ static int inno_hdmi_bind(struct device - return 0; - err_cleanup_hdmi: - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - err_put_adapter: - i2c_put_adapter(hdmi->ddc); - err_disable_clk: -@@ -895,7 +905,7 @@ static void inno_hdmi_unbind(struct devi - struct inno_hdmi *hdmi = dev_get_drvdata(dev); - - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - - i2c_put_adapter(hdmi->ddc); - clk_disable_unprepare(hdmi->pclk); ---- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c -+++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c -@@ -47,7 +47,7 @@ struct rk3066_hdmi { - void __iomem *regs; - - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - - struct rk3066_hdmi_i2c *i2c; - struct i2c_adapter *ddc; -@@ -58,7 +58,17 @@ struct rk3066_hdmi { - struct drm_display_mode previous_mode; - }; - --#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x) -+static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rk3066_hdmi, encoder); -+} -+ -+static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector) -+{ -+ return container_of(connector, struct rk3066_hdmi, connector); -+} - - static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) - { -@@ -380,7 +390,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_ - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); -+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); - - /* Store the display mode for plugin/DPMS poweron events. */ - memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode)); -@@ -388,7 +398,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_ - - static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); -+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); - int mux, val; - - mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); -@@ -407,7 +417,7 @@ static void rk3066_hdmi_encoder_enable(s - - static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); -+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); - - DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); - -@@ -455,7 +465,7 @@ struct drm_encoder_helper_funcs rk3066_h - static enum drm_connector_status - rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); -+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); - - return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? - connector_status_connected : connector_status_disconnected; -@@ -463,7 +473,7 @@ rk3066_hdmi_connector_detect(struct drm_ - - static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); -+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); - struct edid *edid; - int ret = 0; - -@@ -496,9 +506,9 @@ rk3066_hdmi_connector_mode_valid(struct - static struct drm_encoder * - rk3066_hdmi_connector_best_encoder(struct drm_connector *connector) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); -+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); - -- return &hdmi->encoder; -+ return &hdmi->encoder.encoder; - } - - static int -@@ -538,7 +548,7 @@ struct drm_connector_helper_funcs rk3066 - static int - rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) - { -- struct drm_encoder *encoder = &hdmi->encoder; -+ struct drm_encoder *encoder = &hdmi->encoder.encoder; - struct device *dev = hdmi->dev; - - encoder->possible_crtcs = -@@ -816,7 +826,7 @@ static int rk3066_hdmi_bind(struct devic - - err_cleanup_hdmi: - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - err_disable_i2c: - i2c_put_adapter(hdmi->ddc); - err_disable_hclk: -@@ -831,7 +841,7 @@ static void rk3066_hdmi_unbind(struct de - struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); - - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - - i2c_put_adapter(hdmi->ddc); - clk_disable_unprepare(hdmi->hclk); ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -52,6 +52,10 @@ struct rockchip_drm_private { - struct mutex psr_list_lock; - }; - -+struct rockchip_encoder { -+ struct drm_encoder encoder; -+}; -+ - int rockchip_drm_dma_attach_device(struct drm_device *drm_dev, - struct device *dev); - void rockchip_drm_dma_detach_device(struct drm_device *drm_dev, -@@ -67,4 +71,10 @@ extern struct platform_driver rockchip_d - extern struct platform_driver rockchip_lvds_driver; - extern struct platform_driver vop_platform_driver; - extern struct platform_driver rk3066_hdmi_driver; -+ -+static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder) -+{ -+ return container_of(encoder, struct rockchip_encoder, encoder); -+} -+ - #endif /* _ROCKCHIP_DRM_DRV_H_ */ ---- a/drivers/gpu/drm/rockchip/rockchip_lvds.c -+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c -@@ -35,12 +35,6 @@ - - struct rockchip_lvds; - --#define connector_to_lvds(c) \ -- container_of(c, struct rockchip_lvds, connector) -- --#define encoder_to_lvds(c) \ -- container_of(c, struct rockchip_lvds, encoder) -- - /** - * rockchip_lvds_soc_data - rockchip lvds Soc private data - * @probe: LVDS platform probe function -@@ -64,10 +58,22 @@ struct rockchip_lvds { - struct drm_panel *panel; - struct drm_bridge *bridge; - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - struct dev_pin_info *pins; - }; - -+static inline struct rockchip_lvds *connector_to_lvds(struct drm_connector *connector) -+{ -+ return container_of(connector, struct rockchip_lvds, connector); -+} -+ -+static inline struct rockchip_lvds *encoder_to_lvds(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_lvds, encoder); -+} -+ - static inline void rk3288_writel(struct rockchip_lvds *lvds, u32 offset, - u32 val) - { -@@ -600,7 +606,7 @@ static int rockchip_lvds_bind(struct dev - goto err_put_remote; - } - -- encoder = &lvds->encoder; -+ encoder = &lvds->encoder.encoder; - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, - dev->of_node); - -@@ -668,10 +674,10 @@ static void rockchip_lvds_unbind(struct - const struct drm_encoder_helper_funcs *encoder_funcs; - - encoder_funcs = lvds->soc_data->helper_funcs; -- encoder_funcs->disable(&lvds->encoder); -+ encoder_funcs->disable(&lvds->encoder.encoder); - pm_runtime_disable(dev); - drm_connector_cleanup(&lvds->connector); -- drm_encoder_cleanup(&lvds->encoder); -+ drm_encoder_cleanup(&lvds->encoder.encoder); - } - - static const struct component_ops rockchip_lvds_component_ops = { diff --git a/target/linux/rockchip/patches-5.10/008-0027-v5.19-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch b/target/linux/rockchip/patches-5.10/008-0027-v5.19-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch deleted file mode 100644 index 91db25c67..000000000 --- a/target/linux/rockchip/patches-5.10/008-0027-v5.19-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch +++ /dev/null @@ -1,88 +0,0 @@ -From cf544c6a885c52d79e4d8bf139fb8cb63a878512 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:20 +0200 -Subject: [PATCH] drm/rockchip: Add crtc_endpoint_id to rockchip_encoder - -The VOP2 has an interface mux which decides to which encoder(s) a CRTC -is routed to. The encoders and CRTCs are connected via of_graphs in the -device tree. When given an encoder the VOP2 driver needs to know to -which internal register setting this encoder matches. For this the VOP2 -binding offers different endpoints, one for each possible encoder. The -endpoint ids of these endpoints are used as a key from an encoders -device tree description to the internal register setting. - -This patch adds the key aka endpoint id to struct rockchip_encoder plus -a function to read the endpoint id starting from the encoders device -node. - -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-4-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 33 +++++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 4 ++- - 2 files changed, 36 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -256,6 +256,39 @@ static struct platform_driver *rockchip_ - static int num_rockchip_sub_drivers; - - /* -+ * Get the endpoint id of the remote endpoint of the given encoder. This -+ * information is used by the VOP2 driver to identify the encoder. -+ * -+ * @rkencoder: The encoder to get the remote endpoint id from -+ * @np: The encoder device node -+ * @port: The number of the port leading to the VOP2 -+ * @reg: The endpoint number leading to the VOP2 -+ */ -+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rkencoder, -+ struct device_node *np, int port, int reg) -+{ -+ struct of_endpoint ep; -+ struct device_node *en, *ren; -+ int ret; -+ -+ en = of_graph_get_endpoint_by_regs(np, port, reg); -+ if (!en) -+ return -ENOENT; -+ -+ ren = of_graph_get_remote_endpoint(en); -+ if (!ren) -+ return -ENOENT; -+ -+ ret = of_graph_parse_endpoint(ren, &ep); -+ if (ret) -+ return ret; -+ -+ rkencoder->crtc_endpoint_id = ep.id; -+ -+ return 0; -+} -+ -+/* - * Check if a vop endpoint is leading to a rockchip subdriver or bridge. - * Should be called from the component bind stage of the drivers - * to ensure that all subdrivers are probed. ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -53,6 +53,7 @@ struct rockchip_drm_private { - }; - - struct rockchip_encoder { -+ int crtc_endpoint_id; - struct drm_encoder encoder; - }; - -@@ -61,7 +62,8 @@ int rockchip_drm_dma_attach_device(struc - void rockchip_drm_dma_detach_device(struct drm_device *drm_dev, - struct device *dev); - int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout); -- -+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder, -+ struct device_node *np, int port, int reg); - int rockchip_drm_endpoint_is_subdriver(struct device_node *ep); - extern struct platform_driver cdn_dp_driver; - extern struct platform_driver dw_hdmi_rockchip_pltfm_driver; diff --git a/target/linux/rockchip/patches-5.10/008-0028-v5.19-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch b/target/linux/rockchip/patches-5.10/008-0028-v5.19-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch deleted file mode 100644 index 82b98d05b..000000000 --- a/target/linux/rockchip/patches-5.10/008-0028-v5.19-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch +++ /dev/null @@ -1,93 +0,0 @@ -From a9d37e684492ab5db1cce28b655e20c01191873f Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:21 +0200 -Subject: [PATCH] drm/rockchip: dw_hdmi: rename vpll clock to reference clock - -"vpll" is a misnomer. A clock input to a device should be named after -the usage in the device, not after the clock that drives it. On the -rk3568 the same clock is driven by the HPLL. -To fix that, this patch renames the vpll clock to ref clock. The clock -name "vpll" is left for compatibility to old device trees. - -Signed-off-by: Sascha Hauer -Reviewed-by: Dmitry Osipenko -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-5-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 27 +++++++++++---------- - 1 file changed, 14 insertions(+), 13 deletions(-) - ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -69,7 +69,7 @@ struct rockchip_hdmi { - struct regmap *regmap; - struct rockchip_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; -- struct clk *vpll_clk; -+ struct clk *ref_clk; - struct clk *grf_clk; - struct dw_hdmi *hdmi; - struct phy *phy; -@@ -201,14 +201,15 @@ static int rockchip_hdmi_parse_dt(struct - return PTR_ERR(hdmi->regmap); - } - -- hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll"); -- if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) { -- hdmi->vpll_clk = NULL; -- } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) { -+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref"); -+ if (!hdmi->ref_clk) -+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll"); -+ -+ if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) { - return -EPROBE_DEFER; -- } else if (IS_ERR(hdmi->vpll_clk)) { -- DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n"); -- return PTR_ERR(hdmi->vpll_clk); -+ } else if (IS_ERR(hdmi->ref_clk)) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n"); -+ return PTR_ERR(hdmi->ref_clk); - } - - hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); -@@ -262,7 +263,7 @@ static void dw_hdmi_rockchip_encoder_mod - { - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); - -- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000); -+ clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); - } - - static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) -@@ -542,9 +543,9 @@ static int dw_hdmi_rockchip_bind(struct - return ret; - } - -- ret = clk_prepare_enable(hdmi->vpll_clk); -+ ret = clk_prepare_enable(hdmi->ref_clk); - if (ret) { -- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", -+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", - ret); - return ret; - } -@@ -563,7 +564,7 @@ static int dw_hdmi_rockchip_bind(struct - if (IS_ERR(hdmi->hdmi)) { - ret = PTR_ERR(hdmi->hdmi); - drm_encoder_cleanup(encoder); -- clk_disable_unprepare(hdmi->vpll_clk); -+ clk_disable_unprepare(hdmi->ref_clk); - } - - return ret; -@@ -575,7 +576,7 @@ static void dw_hdmi_rockchip_unbind(stru - struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); - - dw_hdmi_unbind(hdmi->hdmi); -- clk_disable_unprepare(hdmi->vpll_clk); -+ clk_disable_unprepare(hdmi->ref_clk); - } - - static const struct component_ops dw_hdmi_rockchip_ops = { diff --git a/target/linux/rockchip/patches-5.10/008-0029-v5.19-drm-rockchip-dw_hdmi-add-rk3568-support.patch b/target/linux/rockchip/patches-5.10/008-0029-v5.19-drm-rockchip-dw_hdmi-add-rk3568-support.patch deleted file mode 100644 index 799f159ca..000000000 --- a/target/linux/rockchip/patches-5.10/008-0029-v5.19-drm-rockchip-dw_hdmi-add-rk3568-support.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 28bbb5ffbe32741e65d798070986d212cc11e1bb Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:24 +0200 -Subject: [PATCH] drm/rockchip: dw_hdmi: add rk3568 support - -Add a new dw_hdmi_plat_data struct and new compatible for rk3568. - -Signed-off-by: Benjamin Gaignard -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-8-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 31 +++++++++++++++++++++ - 1 file changed, 31 insertions(+) - ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -50,6 +50,10 @@ - #define RK3399_GRF_SOC_CON20 0x6250 - #define RK3399_HDMI_LCDC_SEL BIT(6) - -+#define RK3568_GRF_VO_CON1 0x0364 -+#define RK3568_HDMI_SDAIN_MSK BIT(15) -+#define RK3568_HDMI_SCLIN_MSK BIT(14) -+ - #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) - - /** -@@ -473,6 +477,19 @@ static const struct dw_hdmi_plat_data rk - .use_drm_infoframe = true, - }; - -+static struct rockchip_hdmi_chip_data rk3568_chip_data = { -+ .lcdsel_grf_reg = -1, -+}; -+ -+static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { -+ .mode_valid = dw_hdmi_rockchip_mode_valid, -+ .mpll_cfg = rockchip_mpll_cfg, -+ .cur_ctr = rockchip_cur_ctr, -+ .phy_config = rockchip_phy_config, -+ .phy_data = &rk3568_chip_data, -+ .use_drm_infoframe = true, -+}; -+ - static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { - { .compatible = "rockchip,rk3228-dw-hdmi", - .data = &rk3228_hdmi_drv_data -@@ -486,6 +503,9 @@ static const struct of_device_id dw_hdmi - { .compatible = "rockchip,rk3399-dw-hdmi", - .data = &rk3399_hdmi_drv_data - }, -+ { .compatible = "rockchip,rk3568-dw-hdmi", -+ .data = &rk3568_hdmi_drv_data -+ }, - {}, - }; - MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); -@@ -520,6 +540,9 @@ static int dw_hdmi_rockchip_bind(struct - encoder = &hdmi->encoder.encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -+ rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, -+ dev->of_node, 0, 0); -+ - /* - * If we failed to find the CRTC(s) which this encoder is - * supposed to be connected to, it's because the CRTC has -@@ -550,6 +573,14 @@ static int dw_hdmi_rockchip_bind(struct - return ret; - } - -+ if (hdmi->chip_data == &rk3568_chip_data) { -+ regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, -+ HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | -+ RK3568_HDMI_SCLIN_MSK, -+ RK3568_HDMI_SDAIN_MSK | -+ RK3568_HDMI_SCLIN_MSK)); -+ } -+ - drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - diff --git a/target/linux/rockchip/patches-5.10/008-0030-v5.19-drm-rockchip-dw_hdmi-add-regulator-support.patch b/target/linux/rockchip/patches-5.10/008-0030-v5.19-drm-rockchip-dw_hdmi-add-regulator-support.patch deleted file mode 100644 index 4a67db21d..000000000 --- a/target/linux/rockchip/patches-5.10/008-0030-v5.19-drm-rockchip-dw_hdmi-add-regulator-support.patch +++ /dev/null @@ -1,109 +0,0 @@ -From ca80c4eb4b01a7f1c2f333d0a329937ef9c7f03a Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:26 +0200 -Subject: [PATCH] drm/rockchip: dw_hdmi: add regulator support - -The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed -for the HDMI port. add support for these to the driver for boards which -have them supplied by switchable regulators. - -Signed-off-by: Sascha Hauer -Reviewed-by: Dmitry Osipenko -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-10-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++-- - 1 file changed, 38 insertions(+), 3 deletions(-) - ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -76,6 +77,8 @@ struct rockchip_hdmi { - struct clk *ref_clk; - struct clk *grf_clk; - struct dw_hdmi *hdmi; -+ struct regulator *avdd_0v9; -+ struct regulator *avdd_1v8; - struct phy *phy; - }; - -@@ -226,6 +229,14 @@ static int rockchip_hdmi_parse_dt(struct - return PTR_ERR(hdmi->grf_clk); - } - -+ hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); -+ if (IS_ERR(hdmi->avdd_0v9)) -+ return PTR_ERR(hdmi->avdd_0v9); -+ -+ hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8"); -+ if (IS_ERR(hdmi->avdd_1v8)) -+ return PTR_ERR(hdmi->avdd_1v8); -+ - return 0; - } - -@@ -566,11 +577,23 @@ static int dw_hdmi_rockchip_bind(struct - return ret; - } - -+ ret = regulator_enable(hdmi->avdd_0v9); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); -+ goto err_avdd_0v9; -+ } -+ -+ ret = regulator_enable(hdmi->avdd_1v8); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); -+ goto err_avdd_1v8; -+ } -+ - ret = clk_prepare_enable(hdmi->ref_clk); - if (ret) { - DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", - ret); -- return ret; -+ goto err_clk; - } - - if (hdmi->chip_data == &rk3568_chip_data) { -@@ -594,10 +617,19 @@ static int dw_hdmi_rockchip_bind(struct - */ - if (IS_ERR(hdmi->hdmi)) { - ret = PTR_ERR(hdmi->hdmi); -- drm_encoder_cleanup(encoder); -- clk_disable_unprepare(hdmi->ref_clk); -+ goto err_bind; - } - -+ return 0; -+ -+err_bind: -+ drm_encoder_cleanup(encoder); -+ clk_disable_unprepare(hdmi->ref_clk); -+err_clk: -+ regulator_disable(hdmi->avdd_1v8); -+err_avdd_1v8: -+ regulator_disable(hdmi->avdd_0v9); -+err_avdd_0v9: - return ret; - } - -@@ -608,6 +640,9 @@ static void dw_hdmi_rockchip_unbind(stru - - dw_hdmi_unbind(hdmi->hdmi); - clk_disable_unprepare(hdmi->ref_clk); -+ -+ regulator_disable(hdmi->avdd_1v8); -+ regulator_disable(hdmi->avdd_0v9); - } - - static const struct component_ops dw_hdmi_rockchip_ops = { diff --git a/target/linux/rockchip/patches-5.10/008-0031-v5.19-drm-rockchip-Make-VOP-driver-optional.patch b/target/linux/rockchip/patches-5.10/008-0031-v5.19-drm-rockchip-Make-VOP-driver-optional.patch deleted file mode 100644 index b0ac8ff3e..000000000 --- a/target/linux/rockchip/patches-5.10/008-0031-v5.19-drm-rockchip-Make-VOP-driver-optional.patch +++ /dev/null @@ -1,65 +0,0 @@ -From b382406a2cf4afaa7320a7ad4b298ed6e2675437 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer -Date: Fri, 22 Apr 2022 09:28:38 +0200 -Subject: [PATCH] drm/rockchip: Make VOP driver optional - -With upcoming VOP2 support VOP won't be the only choice anymore, so make -the VOP driver optional. - -This also adds a dependency from ROCKCHIP_ANALOGIX_DP to ROCKCHIP_VOP, -because that driver currently only links and works with the VOP driver. - -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-22-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/Kconfig | 8 ++++++++ - drivers/gpu/drm/rockchip/Makefile | 3 ++- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +- - 3 files changed, 11 insertions(+), 2 deletions(-) - ---- a/drivers/gpu/drm/rockchip/Kconfig -+++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -20,8 +20,16 @@ config DRM_ROCKCHIP - - if DRM_ROCKCHIP - -+config ROCKCHIP_VOP -+ bool "Rockchip VOP driver" -+ default y -+ help -+ This selects support for the VOP driver. You should enable it -+ on older SoCs. -+ - config ROCKCHIP_ANALOGIX_DP - bool "Rockchip specific extensions for Analogix DP driver" -+ depends on ROCKCHIP_VOP - help - This selects support for Rockchip SoC specific extensions - for the Analogix Core DP driver. If you want to enable DP ---- a/drivers/gpu/drm/rockchip/Makefile -+++ b/drivers/gpu/drm/rockchip/Makefile -@@ -4,9 +4,10 @@ - # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. - - rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ -- rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o -+ rockchip_drm_gem.o - rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o - -+rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -503,7 +503,7 @@ static int __init rockchip_drm_init(void - int ret; - - num_rockchip_sub_drivers = 0; -- ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP); -+ ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver, - CONFIG_ROCKCHIP_LVDS); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver, diff --git a/target/linux/rockchip/patches-5.10/008-0032-v5.19-drm-rockchip-Add-VOP2-driver.patch b/target/linux/rockchip/patches-5.10/008-0032-v5.19-drm-rockchip-Add-VOP2-driver.patch deleted file mode 100644 index 8e0fb859c..000000000 --- a/target/linux/rockchip/patches-5.10/008-0032-v5.19-drm-rockchip-Add-VOP2-driver.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 604be85547ce4d61b89292d2f9a78c721b778c16 Mon Sep 17 00:00:00 2001 -From: Andy Yan -Date: Fri, 22 Apr 2022 09:28:39 +0200 -Subject: [PATCH] drm/rockchip: Add VOP2 driver - -The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568. -It replaces the VOP unit found in the older Rockchip SoCs. - -This driver has been derived from the downstream Rockchip Kernel and -heavily modified: - -- All nonstandard DRM properties have been removed -- dropped struct vop2_plane_state and pass around less data between - functions -- Dropped all DRM_FORMAT_* not known on upstream -- rework register access to get rid of excessively used macros -- Drop all waiting for framesyncs - -The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB -board. Overlay support is tested with the modetest utility. AFBC support -on the cluster windows is tested with weston-simple-dmabuf-egl on -weston using the (yet to be upstreamed) panfrost driver support. - -Signed-off-by: Andy Yan -Co-Developed-by: Sascha Hauer -Signed-off-by: Sascha Hauer -Tested-by: Michael Riesch -[dt-binding-header:] -Acked-by: Rob Herring -[moved dt-binding header from dt-nodes patch to here - and made checkpatch --strict happier] -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-23-s.hauer@pengutronix.de ---- - drivers/gpu/drm/rockchip/Kconfig | 6 + - drivers/gpu/drm/rockchip/Makefile | 1 + - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 + - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 6 +- - drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 + - drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 14 + - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2706 ++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 477 +++ - drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 281 ++ - include/dt-bindings/soc/rockchip,vop2.h | 14 + - 10 files changed, 3507 insertions(+), 1 deletion(-) - create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c - create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h - create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c - create mode 100644 include/dt-bindings/soc/rockchip,vop2.h - ---- a/drivers/gpu/drm/rockchip/Kconfig -+++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -27,6 +27,12 @@ config ROCKCHIP_VOP - This selects support for the VOP driver. You should enable it - on older SoCs. - -+config ROCKCHIP_VOP2 -+ bool "Rockchip VOP2 driver" -+ help -+ This selects support for the VOP2 driver. The VOP2 hardware is -+ first found on the RK3568. -+ - config ROCKCHIP_ANALOGIX_DP - bool "Rockchip specific extensions for Analogix DP driver" - depends on ROCKCHIP_VOP ---- a/drivers/gpu/drm/rockchip/Makefile -+++ b/drivers/gpu/drm/rockchip/Makefile -@@ -7,6 +7,7 @@ rockchipdrm-y := rockchip_drm_drv.o rock - rockchip_drm_gem.o - rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o - -+rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -504,6 +504,7 @@ static int __init rockchip_drm_init(void - - num_rockchip_sub_drivers = 0; - ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP); -+ ADD_ROCKCHIP_SUB_DRIVER(vop2_platform_driver, CONFIG_ROCKCHIP_VOP2); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver, - CONFIG_ROCKCHIP_LVDS); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver, ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -18,7 +18,7 @@ - - #define ROCKCHIP_MAX_FB_BUFFER 3 - #define ROCKCHIP_MAX_CONNECTOR 2 --#define ROCKCHIP_MAX_CRTC 2 -+#define ROCKCHIP_MAX_CRTC 4 - - struct drm_device; - struct drm_connector; -@@ -31,6 +31,9 @@ struct rockchip_crtc_state { - int output_bpc; - int output_flags; - bool enable_afbc; -+ u32 bus_format; -+ u32 bus_flags; -+ int color_space; - }; - #define to_rockchip_crtc_state(s) \ - container_of(s, struct rockchip_crtc_state, base) -@@ -73,6 +76,7 @@ extern struct platform_driver rockchip_d - extern struct platform_driver rockchip_lvds_driver; - extern struct platform_driver vop_platform_driver; - extern struct platform_driver rk3066_hdmi_driver; -+extern struct platform_driver vop2_platform_driver; - - static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder) - { ---- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -@@ -134,4 +134,6 @@ void rockchip_drm_mode_config_init(struc - - dev->mode_config.funcs = &rockchip_drm_mode_config_funcs; - dev->mode_config.helper_private = &rockchip_mode_config_helpers; -+ -+ dev->mode_config.normalize_zpos = true; - } ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -54,9 +54,23 @@ struct vop_afbc { - struct vop_reg enable; - struct vop_reg win_sel; - struct vop_reg format; -+ struct vop_reg rb_swap; -+ struct vop_reg uv_swap; -+ struct vop_reg auto_gating_en; -+ struct vop_reg block_split_en; -+ struct vop_reg pic_vir_width; -+ struct vop_reg tile_num; - struct vop_reg hreg_block_split; -+ struct vop_reg pic_offset; - struct vop_reg pic_size; -+ struct vop_reg dsp_offset; -+ struct vop_reg transform_offset; - struct vop_reg hdr_ptr; -+ struct vop_reg half_block_en; -+ struct vop_reg xmirror; -+ struct vop_reg ymirror; -+ struct vop_reg rotate_270; -+ struct vop_reg rotate_90; - struct vop_reg rstn; - }; - diff --git a/target/linux/rockchip/patches-5.10/008-0033-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch b/target/linux/rockchip/patches-5.10/008-0033-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch deleted file mode 100644 index fd380befd..000000000 --- a/target/linux/rockchip/patches-5.10/008-0033-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 431e7d2eece5b906578926d15ee22a70504c364d Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Fri, 29 Apr 2022 08:38:28 -0400 -Subject: [PATCH] PCI: rockchip-dwc: Reset core at driver probe - -The PCIe controller is in an unknown state at driver probe. This can -lead to undesireable effects when the driver attempts to configure the -controller. - -Prevent issues in the future by resetting the core during probe. - -Link: https://lore.kernel.org/r/20220429123832.2376381-3-pgwipeout@gmail.com -Tested-by: Nicolas Frattaroli -Signed-off-by: Peter Geis -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/dwc/pcie-dw-rockchip.c | 23 ++++++++----------- - 1 file changed, 10 insertions(+), 13 deletions(-) - ---- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c -+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c -@@ -152,6 +152,11 @@ static int rockchip_pcie_resource_get(st - if (IS_ERR(rockchip->rst_gpio)) - return PTR_ERR(rockchip->rst_gpio); - -+ rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev); -+ if (IS_ERR(rockchip->rst)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst), -+ "failed to get reset lines\n"); -+ - return 0; - } - -@@ -182,18 +187,6 @@ static void rockchip_pcie_phy_deinit(str - phy_power_off(rockchip->phy); - } - --static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip) --{ -- struct device *dev = rockchip->pci.dev; -- -- rockchip->rst = devm_reset_control_array_get_exclusive(dev); -- if (IS_ERR(rockchip->rst)) -- return dev_err_probe(dev, PTR_ERR(rockchip->rst), -- "failed to get reset lines\n"); -- -- return reset_control_deassert(rockchip->rst); --} -- - static const struct dw_pcie_ops dw_pcie_ops = { - .link_up = rockchip_pcie_link_up, - .start_link = rockchip_pcie_start_link, -@@ -222,6 +215,10 @@ static int rockchip_pcie_probe(struct pl - if (ret) - return ret; - -+ ret = reset_control_assert(rockchip->rst); -+ if (ret) -+ return ret; -+ - /* DON'T MOVE ME: must be enable before PHY init */ - rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); - if (IS_ERR(rockchip->vpcie3v3)) { -@@ -241,7 +238,7 @@ static int rockchip_pcie_probe(struct pl - if (ret) - goto disable_regulator; - -- ret = rockchip_pcie_reset_control_release(rockchip); -+ ret = reset_control_deassert(rockchip->rst); - if (ret) - goto deinit_phy; - diff --git a/target/linux/rockchip/patches-5.10/008-0034-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch b/target/linux/rockchip/patches-5.10/008-0034-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch deleted file mode 100644 index 05b762ff5..000000000 --- a/target/linux/rockchip/patches-5.10/008-0034-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch +++ /dev/null @@ -1,163 +0,0 @@ -From e8aae154df6121167e5b4f156cfc2402e651d2b1 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Fri, 29 Apr 2022 08:38:29 -0400 -Subject: [PATCH] PCI: rockchip-dwc: Add legacy interrupt support - -The legacy interrupts on the rk356x PCIe controller are handled by a -single muxed interrupt. Add IRQ domain support to the pcie-dw-rockchip -driver to support the virtual domain. - -Link: https://lore.kernel.org/r/20220429123832.2376381-4-pgwipeout@gmail.com -Signed-off-by: Peter Geis -Signed-off-by: Lorenzo Pieralisi -Reviewed-by: Marc Zyngier ---- - drivers/pci/controller/dwc/pcie-dw-rockchip.c | 96 ++++++++++++++++++- - 1 file changed, 94 insertions(+), 2 deletions(-) - ---- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c -+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c -@@ -10,9 +10,12 @@ - - #include - #include -+#include -+#include - #include - #include - #include -+#include - #include - #include - #include -@@ -26,6 +29,7 @@ - */ - #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) - #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) -+#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val) - - #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) - -@@ -36,10 +40,12 @@ - #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) - #define PCIE_L0S_ENTRY 0x11 - #define PCIE_CLIENT_GENERAL_CONTROL 0x0 -+#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 -+#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c - #define PCIE_CLIENT_GENERAL_DEBUG 0x104 --#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 -+#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 - #define PCIE_CLIENT_LTSSM_STATUS 0x300 --#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) -+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) - #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) - - struct rockchip_pcie { -@@ -51,6 +57,7 @@ struct rockchip_pcie { - struct reset_control *rst; - struct gpio_desc *rst_gpio; - struct regulator *vpcie3v3; -+ struct irq_domain *irq_domain; - }; - - static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, -@@ -65,6 +72,78 @@ static void rockchip_pcie_writel_apb(str - writel_relaxed(val, rockchip->apb_base + reg); - } - -+static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) -+{ -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); -+ unsigned long reg, hwirq; -+ -+ chained_irq_enter(chip, desc); -+ -+ reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY); -+ -+ for_each_set_bit(hwirq, ®, 4) -+ generic_handle_domain_irq(rockchip->irq_domain, hwirq); -+ -+ chained_irq_exit(chip, desc); -+} -+ -+static void rockchip_intx_mask(struct irq_data *data) -+{ -+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data), -+ HIWORD_UPDATE_BIT(BIT(data->hwirq)), -+ PCIE_CLIENT_INTR_MASK_LEGACY); -+}; -+ -+static void rockchip_intx_unmask(struct irq_data *data) -+{ -+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data), -+ HIWORD_DISABLE_BIT(BIT(data->hwirq)), -+ PCIE_CLIENT_INTR_MASK_LEGACY); -+}; -+ -+static struct irq_chip rockchip_intx_irq_chip = { -+ .name = "INTx", -+ .irq_mask = rockchip_intx_mask, -+ .irq_unmask = rockchip_intx_unmask, -+ .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, -+}; -+ -+static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, -+ irq_hw_number_t hwirq) -+{ -+ irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq); -+ irq_set_chip_data(irq, domain->host_data); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops intx_domain_ops = { -+ .map = rockchip_pcie_intx_map, -+}; -+ -+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) -+{ -+ struct device *dev = rockchip->pci.dev; -+ struct device_node *intc; -+ -+ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"); -+ if (!intc) { -+ dev_err(dev, "missing child interrupt-controller node\n"); -+ return -EINVAL; -+ } -+ -+ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, -+ &intx_domain_ops, rockchip); -+ of_node_put(intc); -+ if (!rockchip->irq_domain) { -+ dev_err(dev, "failed to get a INTx IRQ domain\n"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ - static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) - { - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, -@@ -111,7 +190,20 @@ static int rockchip_pcie_host_init(struc - { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); -+ struct device *dev = rockchip->pci.dev; - u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); -+ int irq, ret; -+ -+ irq = of_irq_get_byname(dev->of_node, "legacy"); -+ if (irq < 0) -+ return irq; -+ -+ ret = rockchip_pcie_init_irq_domain(rockchip); -+ if (ret < 0) -+ dev_err(dev, "failed to init irq domain\n"); -+ -+ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, -+ rockchip); - - /* LTSSM enable control mode */ - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); diff --git a/target/linux/rockchip/patches-5.10/008-0035-v6.0-drm-rockchip-vop2-unlock-on-error-path-in.patch b/target/linux/rockchip/patches-5.10/008-0035-v6.0-drm-rockchip-vop2-unlock-on-error-path-in.patch deleted file mode 100644 index bf17aa7ff..000000000 --- a/target/linux/rockchip/patches-5.10/008-0035-v6.0-drm-rockchip-vop2-unlock-on-error-path-in.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 98526c5bbe3267d447ddd076b685439e3e1396c6 Mon Sep 17 00:00:00 2001 -From: Dan Carpenter -Date: Mon, 9 May 2022 12:05:05 +0300 -Subject: [PATCH] drm/rockchip: vop2: unlock on error path in - vop2_crtc_atomic_enable() - -This error path needs an unlock before returning. - -Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver") -Signed-off-by: Dan Carpenter -Acked-by: Sascha Hauer -Signed-off-by: Heiko Stuebner -Link: https://patchwork.freedesktop.org/patch/msgid/YnjZQRV9lpub2ET8@kili ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -1524,6 +1524,7 @@ static void vop2_crtc_atomic_enable(stru - if (ret < 0) { - drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", - vp->id, ret); -+ vop2_unlock(vop2); - return; - } - diff --git a/target/linux/rockchip/patches-5.10/008-0036-v6.0-media-hantro-Add-support-for-RK356x-encoder.patch b/target/linux/rockchip/patches-5.10/008-0036-v6.0-media-hantro-Add-support-for-RK356x-encoder.patch deleted file mode 100644 index 5a5a595d6..000000000 --- a/target/linux/rockchip/patches-5.10/008-0036-v6.0-media-hantro-Add-support-for-RK356x-encoder.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 6f1ae821a6c4aa9d5b8f437b27ec86fb569219fd Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Sun, 12 Jun 2022 16:53:45 +0100 -Subject: [PATCH] media: hantro: Add support for RK356x encoder - -The RK3566 and RK3568 SoCs come with a small Hantro instance which is -solely dedicated to encoding. This patch adds the necessary structs to -the Hantro driver to allow the JPEG encoder of it to function. - -Through some sleuthing through the vendor's MPP source code and after -closer inspection of the TRM, it was determined that the hardware likely -supports VP8 and H.264 as well. - -Tested with the following GStreamer command: - -gst-launch-1.0 videotestsrc ! v4l2jpegenc ! matroskamux ! \ - filesink location=foo.mkv - -Signed-off-by: Nicolas Frattaroli -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/hantro/hantro_drv.c | 1 + - drivers/staging/media/hantro/hantro_hw.h | 1 + - .../staging/media/hantro/rockchip_vpu_hw.c | 25 +++++++++++++++++++ - 3 files changed, 27 insertions(+) - ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -486,6 +486,7 @@ static const struct of_device_id of_hant - { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, - { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, }, - { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, -+ { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, }, - { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, - #endif - #ifdef CONFIG_VIDEO_HANTRO_IMX8M ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -153,6 +153,7 @@ enum hantro_enc_fmt { - extern const struct hantro_variant rk3399_vpu_variant; - extern const struct hantro_variant rk3328_vpu_variant; - extern const struct hantro_variant rk3288_vpu_variant; -+extern const struct hantro_variant rk3568_vepu_variant; - extern const struct hantro_variant rk3568_vpu_variant; - extern const struct hantro_variant imx8mq_vpu_variant; - ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -423,6 +423,14 @@ static const struct hantro_codec_ops rk3 - }, - }; - -+static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = { -+ [HANTRO_MODE_JPEG_ENC] = { -+ .run = rockchip_vpu2_jpeg_enc_run, -+ .reset = rockchip_vpu2_enc_reset, -+ .done = rockchip_vpu2_jpeg_enc_done, -+ }, -+}; -+ - /* - * VPU variant. - */ -@@ -445,6 +453,10 @@ static const struct hantro_irq rockchip_ - { "vdpu", rockchip_vpu2_vdpu_irq }, - }; - -+static const struct hantro_irq rk3568_vepu_irqs[] = { -+ { "vepu", rockchip_vpu2_vepu_irq }, -+}; -+ - static const char * const rk3066_vpu_clk_names[] = { - "aclk_vdpu", "hclk_vdpu", - "aclk_vepu", "hclk_vepu" -@@ -549,6 +561,19 @@ const struct hantro_variant rk3399_vpu_v - .init = rockchip_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) -+}; -+ -+const struct hantro_variant rk3568_vepu_variant = { -+ .enc_offset = 0x0, -+ .enc_fmts = rockchip_vpu_enc_fmts, -+ .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), -+ .codec = HANTRO_JPEG_ENCODER, -+ .codec_ops = rk3568_vepu_codec_ops, -+ .irqs = rk3568_vepu_irqs, -+ .num_irqs = ARRAY_SIZE(rk3568_vepu_irqs), -+ .init = rockchip_vpu_hw_init, -+ .clk_names = rockchip_vpu_clk_names, -+ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; - - const struct hantro_variant rk3568_vpu_variant = { diff --git a/target/linux/rockchip/patches-5.10/008-0037-v6.0-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch b/target/linux/rockchip/patches-5.10/008-0037-v6.0-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch deleted file mode 100644 index b850bbcf5..000000000 --- a/target/linux/rockchip/patches-5.10/008-0037-v6.0-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch +++ /dev/null @@ -1,36 +0,0 @@ -From fd7d47484125c7d04578de9294faa7fec6e5df0a Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 8 Jul 2022 01:14:34 -0500 -Subject: [PATCH] phy: rockchip-inno-usb2: Ignore OTG IRQs in host mode - -When the OTG port is fixed to host mode, the driver does not request its -IRQs, nor does it enable those IRQs in hardware. Similarly, the driver -should ignore the OTG port IRQs when handling the shared interrupt. - -Otherwise, it would update the extcon based on an ID pin which may be in -an undefined state, or try to queue a uninitialized work item. - -Fixes: 6a98df08ccd5 ("phy: rockchip-inno-usb2: Fix muxed interrupt support") -Reported-by: Frank Wunderlich -Signed-off-by: Samuel Holland -Tested-by: Peter Geis -Tested-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20220708061434.38115-1-samuel@sholland.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -986,7 +986,9 @@ static irqreturn_t rockchip_usb2phy_irq( - - switch (rport->port_id) { - case USB2PHY_PORT_OTG: -- ret |= rockchip_usb2phy_otg_mux_irq(irq, rport); -+ if (rport->mode != USB_DR_MODE_HOST && -+ rport->mode != USB_DR_MODE_UNKNOWN) -+ ret |= rockchip_usb2phy_otg_mux_irq(irq, rport); - break; - case USB2PHY_PORT_HOST: - ret |= rockchip_usb2phy_linestate_irq(irq, rport); diff --git a/target/linux/rockchip/patches-5.10/008-0038-v6.0-media-hantro-Fix-RK3399-H.264-format-advertising.patch b/target/linux/rockchip/patches-5.10/008-0038-v6.0-media-hantro-Fix-RK3399-H.264-format-advertising.patch deleted file mode 100644 index 22e33fca3..000000000 --- a/target/linux/rockchip/patches-5.10/008-0038-v6.0-media-hantro-Fix-RK3399-H.264-format-advertising.patch +++ /dev/null @@ -1,126 +0,0 @@ -From 177d841fa19542eb35aa5ec9579c4abb989c9255 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Wed, 29 Jun 2022 20:56:23 +0100 -Subject: [PATCH] media: hantro: Fix RK3399 H.264 format advertising - -Commit 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2") -enabled H.264 on some SoCs with VDPU2 cores. This had the side-effect -of exposing H.264 coded format as supported on RK3399. - -Fix this and clarify how the codec is explicitly disabled on RK3399 on -this driver. - -Fixes: 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2") -Signed-off-by: Ezequiel Garcia -Tested-by: Nicolas Dufresne -Reviewed-by: Nicolas Dufresne -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/hantro/rockchip_vpu_hw.c | 60 ++++++++++++++++--- - 1 file changed, 53 insertions(+), 7 deletions(-) - ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -158,7 +158,7 @@ static const struct hantro_fmt rk3288_vp - }, - }; - --static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { -+static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12, - .codec_mode = HANTRO_MODE_NONE, -@@ -204,6 +204,47 @@ static const struct hantro_fmt rk3399_vp - }, - }; - -+static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .codec_mode = HANTRO_MODE_NONE, -+ .frmsize = { -+ .min_width = FMT_MIN_WIDTH, -+ .max_width = FMT_FHD_WIDTH, -+ .step_width = MB_DIM, -+ .min_height = FMT_MIN_HEIGHT, -+ .max_height = FMT_FHD_HEIGHT, -+ .step_height = MB_DIM, -+ }, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, -+ .codec_mode = HANTRO_MODE_MPEG2_DEC, -+ .max_depth = 2, -+ .frmsize = { -+ .min_width = FMT_MIN_WIDTH, -+ .max_width = FMT_FHD_WIDTH, -+ .step_width = MB_DIM, -+ .min_height = FMT_MIN_HEIGHT, -+ .max_height = FMT_FHD_HEIGHT, -+ .step_height = MB_DIM, -+ }, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_VP8_FRAME, -+ .codec_mode = HANTRO_MODE_VP8_DEC, -+ .max_depth = 2, -+ .frmsize = { -+ .min_width = FMT_MIN_WIDTH, -+ .max_width = FMT_UHD_WIDTH, -+ .step_width = MB_DIM, -+ .min_height = FMT_MIN_HEIGHT, -+ .max_height = FMT_UHD_HEIGHT, -+ .step_height = MB_DIM, -+ }, -+ }, -+}; -+ - static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id) - { - struct hantro_dev *vpu = dev_id; -@@ -534,8 +575,8 @@ const struct hantro_variant rk3288_vpu_v - - const struct hantro_variant rk3328_vpu_variant = { - .dec_offset = 0x400, -- .dec_fmts = rk3399_vpu_dec_fmts, -- .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -+ .dec_fmts = rockchip_vdpu2_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts), - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, -@@ -546,6 +587,11 @@ const struct hantro_variant rk3328_vpu_v - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names), - }; - -+/* -+ * H.264 decoding explicitly disabled in RK3399. -+ * This ensures userspace applications use the Rockchip VDEC core, -+ * which has better performance. -+ */ - const struct hantro_variant rk3399_vpu_variant = { - .enc_offset = 0x0, - .enc_fmts = rockchip_vpu_enc_fmts, -@@ -578,8 +624,8 @@ const struct hantro_variant rk3568_vepu_ - - const struct hantro_variant rk3568_vpu_variant = { - .dec_offset = 0x400, -- .dec_fmts = rk3399_vpu_dec_fmts, -- .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -+ .dec_fmts = rockchip_vdpu2_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts), - .codec = HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, -@@ -595,8 +641,8 @@ const struct hantro_variant px30_vpu_var - .enc_fmts = rockchip_vpu_enc_fmts, - .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), - .dec_offset = 0x400, -- .dec_fmts = rk3399_vpu_dec_fmts, -- .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), -+ .dec_fmts = rockchip_vdpu2_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts), - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, diff --git a/target/linux/rockchip/patches-5.10/008-0039-v6.0-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-probe.patch b/target/linux/rockchip/patches-5.10/008-0039-v6.0-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-probe.patch deleted file mode 100644 index f65056fe2..000000000 --- a/target/linux/rockchip/patches-5.10/008-0039-v6.0-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-probe.patch +++ /dev/null @@ -1,27 +0,0 @@ -From b113e55913e7f7f031d6cbf9d7b585c6b112f55a Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sat, 25 Jun 2022 17:27:11 -0400 -Subject: [PATCH] phy: rockchip-inno-usb2: Prevent incorrect error on probe - -If a phy supply is designated but isn't available at probe time, an -EPROBE_DEFER is returned. Use dev_err_probe to prevent this from -incorrectly printing during boot. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20220625212711.558495-1-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1293,7 +1293,7 @@ static int rockchip_usb2phy_probe(struct - - phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops); - if (IS_ERR(phy)) { -- dev_err(dev, "failed to create phy\n"); -+ dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n"); - ret = PTR_ERR(phy); - goto put_child; - } diff --git a/target/linux/rockchip/patches-5.10/008-0040-v6.0-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch b/target/linux/rockchip/patches-5.10/008-0040-v6.0-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch deleted file mode 100644 index 666c31539..000000000 --- a/target/linux/rockchip/patches-5.10/008-0040-v6.0-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8dc60f8da22fdbaa1fafcfb5ff6d24bc9eff56aa Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 21 Jun 2022 20:31:40 -0400 -Subject: [PATCH] phy: rockchip-inno-usb2: Sync initial otg state - -The initial otg state for the phy defaults to device mode. The actual -state isn't detected until an ID IRQ fires. Fix this by syncing the ID -state during initialization. - -Fixes: 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") -Signed-off-by: Peter Geis -Reviewed-by: Samuel Holland -Link: https://lore.kernel.org/r/20220622003140.30365-1-pgwipeout@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1172,6 +1172,12 @@ static int rockchip_usb2phy_otg_port_ini - EXTCON_USB_HOST, &rport->event_nb); - if (ret) - dev_err(rphy->dev, "register USB HOST notifier failed\n"); -+ -+ if (!of_property_read_bool(rphy->dev->of_node, "extcon")) { -+ /* do initial sync of usb state */ -+ ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); -+ extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret); -+ } - } - - out: diff --git a/target/linux/rockchip/patches-5.10/009-v6.0-arm64-enable-THP_SWAP-for-arm64.patch b/target/linux/rockchip/patches-5.10/009-v6.0-arm64-enable-THP_SWAP-for-arm64.patch deleted file mode 100644 index f7ddd498c..000000000 --- a/target/linux/rockchip/patches-5.10/009-v6.0-arm64-enable-THP_SWAP-for-arm64.patch +++ /dev/null @@ -1,123 +0,0 @@ -From d0637c505f8a1d8c4088642f1f3e9e3b22da14f6 Mon Sep 17 00:00:00 2001 -From: Barry Song -Date: Wed, 20 Jul 2022 21:37:37 +1200 -Subject: [PATCH] arm64: enable THP_SWAP for arm64 - -THP_SWAP has been proven to improve the swap throughput significantly -on x86_64 according to commit bd4c82c22c367e ("mm, THP, swap: delay -splitting THP after swapped out"). -As long as arm64 uses 4K page size, it is quite similar with x86_64 -by having 2MB PMD THP. THP_SWAP is architecture-independent, thus, -enabling it on arm64 will benefit arm64 as well. -A corner case is that MTE has an assumption that only base pages -can be swapped. We won't enable THP_SWAP for ARM64 hardware with -MTE support until MTE is reworked to coexist with THP_SWAP. - -A micro-benchmark is written to measure thp swapout throughput as -below, - - unsigned long long tv_to_ms(struct timeval tv) - { - return tv.tv_sec * 1000 + tv.tv_usec / 1000; - } - - main() - { - struct timeval tv_b, tv_e;; - #define SIZE 400*1024*1024 - volatile void *p = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, - MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); - if (!p) { - perror("fail to get memory"); - exit(-1); - } - - madvise(p, SIZE, MADV_HUGEPAGE); - memset(p, 0x11, SIZE); /* write to get mem */ - - gettimeofday(&tv_b, NULL); - madvise(p, SIZE, MADV_PAGEOUT); - gettimeofday(&tv_e, NULL); - - printf("swp out bandwidth: %ld bytes/ms\n", - SIZE/(tv_to_ms(tv_e) - tv_to_ms(tv_b))); - } - -Testing is done on rk3568 64bit Quad Core Cortex-A55 platform - -ROCK 3A. -thp swp throughput w/o patch: 2734bytes/ms (mean of 10 tests) -thp swp throughput w/ patch: 3331bytes/ms (mean of 10 tests) - -Cc: "Huang, Ying" -Cc: Minchan Kim -Cc: Johannes Weiner -Cc: Hugh Dickins -Cc: Andrea Arcangeli -Cc: Steven Price -Cc: Yang Shi -Reviewed-by: Anshuman Khandual -Signed-off-by: Barry Song -Link: https://lore.kernel.org/r/20220720093737.133375-1-21cnbao@gmail.com -Signed-off-by: Will Deacon ---- - arch/arm64/Kconfig | 1 + - arch/arm64/include/asm/pgtable.h | 6 ++++++ - include/linux/huge_mm.h | 12 ++++++++++++ - mm/swap_slots.c | 2 +- - 4 files changed, 20 insertions(+), 1 deletion(-) - ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -82,6 +82,7 @@ config ARM64 - select ARCH_WANT_FRAME_POINTERS - select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) - select ARCH_WANT_LD_ORPHAN_WARN -+ select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES - select ARCH_HAS_UBSAN_SANITIZE_ALL - select ARM_AMBA - select ARM_ARCH_TIMER ---- a/arch/arm64/include/asm/pgtable.h -+++ b/arch/arm64/include/asm/pgtable.h -@@ -46,6 +46,12 @@ - __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) - #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ - -+static inline bool arch_thp_swp_supported(void) -+{ -+ return !system_supports_mte(); -+} -+#define arch_thp_swp_supported arch_thp_swp_supported -+ - /* - * Outside of a few very special situations (e.g. hibernation), we always - * use broadcast TLB invalidation instructions, therefore a spurious page ---- a/include/linux/huge_mm.h -+++ b/include/linux/huge_mm.h -@@ -499,4 +499,16 @@ static inline unsigned long thp_size(str - return PAGE_SIZE << thp_order(page); - } - -+/* -+ * archs that select ARCH_WANTS_THP_SWAP but don't support THP_SWP due to -+ * limitations in the implementation like arm64 MTE can override this to -+ * false -+ */ -+#ifndef arch_thp_swp_supported -+static inline bool arch_thp_swp_supported(void) -+{ -+ return true; -+} -+#endif -+ - #endif /* _LINUX_HUGE_MM_H */ ---- a/mm/swap_slots.c -+++ b/mm/swap_slots.c -@@ -311,7 +311,7 @@ swp_entry_t get_swap_page(struct page *p - entry.val = 0; - - if (PageTransHuge(page)) { -- if (IS_ENABLED(CONFIG_THP_SWAP)) -+ if (IS_ENABLED(CONFIG_THP_SWAP) && arch_thp_swp_supported()) - get_swap_pages(1, &entry, HPAGE_PMD_NR); - goto out; - } diff --git a/target/linux/rockchip/patches-5.10/105-rockchip-rock-pi-4.patch b/target/linux/rockchip/patches-5.10/105-rockchip-rock-pi-4.patch index 23d461fad..404f64ab9 100644 --- a/target/linux/rockchip/patches-5.10/105-rockchip-rock-pi-4.patch +++ b/target/linux/rockchip/patches-5.10/105-rockchip-rock-pi-4.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pi +@@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pi dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb diff --git a/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch index 624b993de..563a7f6df 100644 --- a/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch +++ b/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -96,6 +96,19 @@ +@@ -101,6 +101,19 @@ max-link-speed = <1>; num-lanes = <1>; vpcie3v3-supply = <&vcc3v3_sys>; diff --git a/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch index ef3011585..acc3e2c14 100644 --- a/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch +++ b/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch @@ -32,4 +32,4 @@ Signed-off-by: Jonas Karlman + host->ios.clock = 0; host->ios.vdd = 0; - + \ No newline at end of file diff --git a/target/linux/rockchip/patches-5.10/108-phy-rockchip-Support-PCIe-v3.patch b/target/linux/rockchip/patches-5.10/108-phy-rockchip-Support-PCIe-v3.patch deleted file mode 100644 index 691816906..000000000 --- a/target/linux/rockchip/patches-5.10/108-phy-rockchip-Support-PCIe-v3.patch +++ /dev/null @@ -1,106 +0,0 @@ -From: Frank Wunderlich -To: linux-rockchip@lists.infradead.org -Cc: Frank Wunderlich , - Kishon Vijay Abraham I , - Vinod Koul , Rob Herring , - Krzysztof Kozlowski , - Heiko Stuebner , - Philipp Zabel , - Johan Jonker , - Yifeng Zhao , - Peter Geis , - Michael Riesch , - Liang Chen , Simon Xue , - Shawn Lin , - linux-phy@lists.infradead.org, devicetree@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, - linux-kernel@vger.kernel.org -Subject: [PATCH v4 3/5] phy: rockchip: Support PCIe v3 -Date: Sun, 19 Jun 2022 10:26:03 +0200 [thread overview] -Message-ID: <20220619082605.7935-4-linux@fw-web.de> (raw) -In-Reply-To: <20220619082605.7935-1-linux@fw-web.de> - -From: Shawn Lin - -RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. -It use a dedicated PCIe-phy. Add support for this. - -Initial support by Shawn Lin, modifications by Peter Geis and Frank -Wunderlich. - -Add data-lanes property for splitting pcie-lanes across controllers. - -The data-lanes is an array where x=0 means lane is disabled and x > 0 -means controller x is assigned to phy lane. - -Signed-off-by: Shawn Lin -Suggested-by: Peter Geis -Signed-off-by: Frank Wunderlich ---- -v4: -- change u8 lane-map to u32 data-lanes - -v3: -- change dt-binding include -- change reset to devm_reset_control_get_optional_exclusive - exit on error and lower severity of message if unset -- fix from peter: disable reg-write for phy-mode in rockchip_p3phy_probe -- move bifurcation/lane-map support from PCIe to phy driver - -v2: -- move dt-bindings header into separate patch -- use BIT-macro -- make constants better readable -- use dev_err instead of pr_* -- change dt-binding include due to renaming (phy-snps-pcie3.h => phy-rockchip-pcie3.h) -- use exclusive variant of devm_reset_control_get{,_exclusive} -- fix semicolon.cocci warnings reported by kernel test robot - ---- -driver was taken from linux 5.10 based on in -https://github.com/JeffyCN/mirrors -which now has disappeared - -Update phy-rockchip-snps-pcie3.c - -Fix messages for data-lanes - -Update phy-rockchip-snps-pcie3.c - -Fix comment for data-lanes ---- - drivers/phy/rockchip/Kconfig | 9 + - drivers/phy/rockchip/Makefile | 1 + - .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ - include/linux/phy/pcie.h | 12 + - 4 files changed, 339 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c - create mode 100644 include/linux/phy/pcie.h - ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -73,6 +73,15 @@ config PHY_ROCKCHIP_PCIE - help - Enable this to support the Rockchip PCIe PHY. - -+config PHY_ROCKCHIP_SNPS_PCIE3 -+ tristate "Rockchip Snps PCIe3 PHY Driver" -+ depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST -+ depends on HAS_IOMEM -+ select GENERIC_PHY -+ select MFD_SYSCON -+ help -+ Enable this to support the Rockchip snps PCIe3 PHY. -+ - config PHY_ROCKCHIP_TYPEC - tristate "Rockchip TYPEC PHY Driver" - depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -7,5 +7,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o - obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o -+obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/target/linux/rockchip/patches-5.10/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch b/target/linux/rockchip/patches-5.10/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch deleted file mode 100644 index 6513c17c3..000000000 --- a/target/linux/rockchip/patches-5.10/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch +++ /dev/null @@ -1,174 +0,0 @@ -From: Frank Wunderlich -To: linux-rockchip@lists.infradead.org -Cc: Frank Wunderlich , - Kishon Vijay Abraham I , - Vinod Koul , Rob Herring , - Krzysztof Kozlowski , - Heiko Stuebner , - Philipp Zabel , - Johan Jonker , - Yifeng Zhao , - Peter Geis , - Michael Riesch , - Liang Chen , Simon Xue , - Shawn Lin , - linux-phy@lists.infradead.org, devicetree@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, - linux-kernel@vger.kernel.org -Subject: [PATCH v4 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes -Date: Sun, 19 Jun 2022 10:26:04 +0200 [thread overview] -Message-ID: <20220619082605.7935-5-linux@fw-web.de> (raw) -In-Reply-To: <20220619082605.7935-1-linux@fw-web.de> - -From: Frank Wunderlich - -Add nodes to rk356x devicetree to support PCIe v3. - -Co-developed-by: Peter Geis -Signed-off-by: Frank Wunderlich ---- -v4: -- update pcie3 reg/ranges - -v3: -- fix from Peter: change bus-range and msi-map, msi-map needs - to start from 0x0 - -v2: -- change to compatible with soc-part -- change rockchip,bifurcation to vendor unspecific bifurcation ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ - 1 file changed, 122 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -42,6 +42,128 @@ - reg = <0x0 0xfe190200 0x0 0x20>; - }; - -+ pcie30_phy_grf: syscon@fdcb8000 { -+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; -+ reg = <0x0 0xfdcb8000 0x0 0x10000>; -+ }; -+ -+ pcie30phy: phy@fe8c0000 { -+ compatible = "rockchip,rk3568-pcie3-phy"; -+ reg = <0x0 0xfe8c0000 0x0 0x20000>; -+ #phy-cells = <0>; -+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, -+ <&cru PCLK_PCIE30PHY>; -+ clock-names = "refclk_m", "refclk_n", "pclk"; -+ resets = <&cru SRST_PCIE30PHY>; -+ reset-names = "phy"; -+ rockchip,phy-grf = <&pcie30_phy_grf>; -+ status = "disabled"; -+ }; -+ -+ pcie3x1: pcie@fe270000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, -+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, -+ <&cru CLK_PCIE30X1_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, -+ <0 0 0 2 &pcie3x1_intc 1>, -+ <0 0 0 3 &pcie3x1_intc 2>, -+ <0 0 0 4 &pcie3x1_intc 3>; -+ linux,pci-domain = <1>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x1000 0x1000>; -+ num-lanes = <1>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0400000 0x0 0x00400000>, -+ <0x0 0xfe270000 0x0 0x00010000>, -+ <0x3 0x7f000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X1_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane1 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x1_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie3x2: pcie@fe280000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, -+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, -+ <&cru CLK_PCIE30X2_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, -+ <0 0 0 2 &pcie3x2_intc 1>, -+ <0 0 0 3 &pcie3x2_intc 2>, -+ <0 0 0 4 &pcie3x2_intc 3>; -+ linux,pci-domain = <2>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x2000 0x1000>; -+ num-lanes = <2>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0800000 0x0 0x00400000>, -+ <0x0 0xfe280000 0x0 0x00010000>, -+ <0x3 0xbf000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X2_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane0 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x2_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-5.10/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch b/target/linux/rockchip/patches-5.10/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch index ea6d70e22..216667683 100644 --- a/target/linux/rockchip/patches-5.10/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch +++ b/target/linux/rockchip/patches-5.10/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch @@ -8,3 +8,45 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++#include "rk3328-nanopi-r2s.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus"; ++ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; ++}; ++ ++&lan_led { ++ label = "orangepi-r1-plus:green:lan"; ++}; ++ ++&spi0 { ++ max-freq = <48000000>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ }; ++}; ++ ++&sys_led { ++ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; ++ label = "orangepi-r1-plus:red:sys"; ++}; ++ ++&sys_led_pin { ++ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&wan_led { ++ label = "orangepi-r1-plus:green:wan"; ++}; diff --git a/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch b/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch index 0a70299ab..efd3cd233 100644 --- a/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch +++ b/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-EmbedFire-DoorNet1.patch @@ -430,3 +430,5 @@ + realtek,led-data = <0x87>; + }; +}; +-- +2.25.1 diff --git a/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch index 0afb4fff7..f7e84c4ee 100644 --- a/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -8,3 +8,53 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2021 Tianling Shen ++ */ ++ ++/dts-v1/; ++ ++#include "rk3328-nanopi-r2s.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R2C"; ++ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; ++}; ++ ++&gmac2io { ++ phy-handle = <&yt8521s>; ++ ++ mdio { ++ /delete-node/ ethernet-phy@1; ++ ++ yt8521s: ethernet-phy@3 { ++ compatible = "ethernet-phy-id0000.011a", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <3>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&lan_led { ++ label = "nanopi-r2c:green:lan"; ++}; ++ ++&sys_led { ++ label = "nanopi-r2c:red:sys"; ++}; ++ ++&wan_led { ++ label = "nanopi-r2c:green:wan"; ++}; diff --git a/target/linux/rockchip/patches-5.10/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch b/target/linux/rockchip/patches-5.10/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch index a744fcfe0..154f5e655 100644 --- a/target/linux/rockchip/patches-5.10/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch +++ b/target/linux/rockchip/patches-5.10/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-li +@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-li dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb diff --git a/target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch index ca65bd263..eabd5bb3b 100644 --- a/target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch +++ b/target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch @@ -9,9 +9,11 @@ Subject: [PATCH] Add support for OrangePi R1 Plus LTS 2 files changed, 45 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 23373c752..552d97555 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev +@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb @@ -19,3 +21,81 @@ Subject: [PATCH] Add support for OrangePi R1 Plus LTS dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +new file mode 100644 +index 000000000..c65f7c417 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +@@ -0,0 +1,70 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++#include "rk3328-orangepi-r1-plus.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus LTS"; ++ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; ++}; ++ ++/delete-node/ &rtl8211e; ++&gmac2io { ++ phy-handle = <ðphy3>; ++ snps,reset-delays-us = <0 15000 50000>; ++ tx_delay = <0x19>; ++ rx_delay = <0x05>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethphy3: ethernet-phy@0 { ++ reg = <0x0>; ++ keep-clkout-on; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; ++ pinctrl-names = "default"; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_sd>; ++ vqmmc-supply = <&vcc_io_sdio>; ++ status = "okay"; ++}; ++ ++&dmc_opp_table { ++ opp-1056000000 { ++ status = "disabled"; ++ }; ++ opp-924000000 { ++ status = "disabled"; ++ }; ++ opp-840000000 { ++ status = "disabled"; ++ }; ++ opp-798000000 { ++ status = "disabled"; ++ }; ++}; ++ ++&sys_led { ++ label = "orangepi-r1-plus-lts:red:sys"; ++}; ++ ++&wan_led { ++ label = "orangepi-r1-plus-lts:green:wan"; ++}; ++ ++&lan_led { ++ label = "orangepi-r1-plus-lts:green:lan"; ++}; +-- +2.25.1 diff --git a/target/linux/rockchip/patches-5.10/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch b/target/linux/rockchip/patches-5.10/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch index 234c150b9..44ed7d9cd 100644 --- a/target/linux/rockchip/patches-5.10/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch +++ b/target/linux/rockchip/patches-5.10/207-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch @@ -33,11 +33,13 @@ to status_led in accordance with the board schematics. 2 files changed, 397 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 479906f3a..5f6ffb496 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -9,6 +9,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-do +@@ -3,6 +3,11 @@ + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4se.dtb @@ -45,8 +47,11 @@ to status_led in accordance with the board schematics. +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-station-p2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts +new file mode 100644 +index 000000000..1eb7fd5f7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts @@ -0,0 +1,396 @@ @@ -446,3 +451,6 @@ to status_led in accordance with the board schematics. + realtek,led-data = <0x87>; + }; +}; +-- +2.34.1 + diff --git a/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch b/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch index d406b8d13..e478541c0 100644 --- a/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch +++ b/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch @@ -15,7 +15,7 @@ Signed-off-by: hmz007 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -302,6 +302,11 @@ config MICROSEMI_PHY +@@ -297,6 +297,11 @@ config MICROSEMI_PHY help Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs @@ -29,7 +29,7 @@ Signed-off-by: hmz007 help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -83,6 +83,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o +@@ -82,6 +82,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o obj-$(CONFIG_MICROCHIP_PHY) += microchip.o obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o obj-$(CONFIG_MICROSEMI_PHY) += mscc/ diff --git a/target/linux/rockchip/patches-5.10/601-net-phy-Add-driver-for-Motorcomm-YT8531-PHYs.patch b/target/linux/rockchip/patches-5.10/601-net-phy-Add-driver-for-Motorcomm-YT8531-PHYs.patch index cef0019af..9b9c46dfb 100644 --- a/target/linux/rockchip/patches-5.10/601-net-phy-Add-driver-for-Motorcomm-YT8531-PHYs.patch +++ b/target/linux/rockchip/patches-5.10/601-net-phy-Add-driver-for-Motorcomm-YT8531-PHYs.patch @@ -10,9 +10,11 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs include/linux/motorcomm_phy.h | 5 + 4 files changed, 350 insertions(+), 1 deletion(-) +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +index 8dc4def..bcd46ca 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -121,6 +121,10 @@ static void stmmac_exit_fs(struct net_de +@@ -121,6 +121,10 @@ static void stmmac_exit_fs(struct net_device *dev); #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) @@ -23,7 +25,7 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) { int ret = 0; -@@ -4947,6 +4951,74 @@ int stmmac_reinit_ringparam(struct net_d +@@ -4950,6 +4954,74 @@ int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) return ret; } @@ -98,7 +100,7 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs /** * stmmac_dvr_probe * @device: device pointer -@@ -5170,6 +5242,16 @@ int stmmac_dvr_probe(struct device *devi +@@ -5173,6 +5245,16 @@ int stmmac_dvr_probe(struct device *device, netdev_err(ndev, "failed to setup phy (%d)\n", ret); goto error_phy_setup; } @@ -115,6 +117,8 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs ret = register_netdev(ndev); if (ret) { +diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c +index 17a4f6c..e37dfb9 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -26,6 +26,13 @@ @@ -131,7 +135,7 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) { int ret; -@@ -263,6 +270,38 @@ static int yt8521_config_intr(struct phy +@@ -263,6 +270,38 @@ static int yt8521_config_intr(struct phy_device *phydev) return phy_write(phydev, REG_INT_MASK, val); } @@ -170,7 +174,7 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs static int yt8521_ack_interrupt(struct phy_device *phydev) { int val; -@@ -273,6 +312,121 @@ static int yt8521_ack_interrupt(struct p +@@ -273,6 +312,121 @@ static int yt8521_ack_interrupt(struct phy_device *phydev) return (val < 0) ? val : 0; } @@ -292,7 +296,7 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs static struct phy_driver ytphy_drvs[] = { { .phy_id = PHY_ID_YT8010, -@@ -323,7 +477,30 @@ static struct phy_driver ytphy_drvs[] = +@@ -323,7 +477,30 @@ static struct phy_driver ytphy_drvs[] = { .config_intr = yt8521_config_intr, .suspend = genphy_suspend, .resume = genphy_resume, @@ -324,7 +328,7 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs }; module_phy_driver(ytphy_drvs); -@@ -339,6 +516,8 @@ static struct mdio_device_id __maybe_unu +@@ -339,6 +516,8 @@ static struct mdio_device_id __maybe_unused motorcomm_tbl[] = { { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK }, { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK }, { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK }, @@ -333,6 +337,8 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs { } }; +diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c +index 950277e..3a35040 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -32,6 +32,7 @@ @@ -343,7 +349,7 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs MODULE_DESCRIPTION("PHY library"); MODULE_AUTHOR("Andy Fleming"); -@@ -409,6 +410,33 @@ int phy_unregister_fixup_for_id(const ch +@@ -409,6 +410,33 @@ int phy_unregister_fixup_for_id(const char *bus_id) } EXPORT_SYMBOL(phy_unregister_fixup_for_id); @@ -377,7 +383,7 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs /* Returns 1 if fixup matches phydev in bus_id and phy_uid. * Fixups can be set to match any in one or more fields. */ -@@ -816,6 +844,50 @@ static int get_phy_c22_id(struct mii_bus +@@ -816,6 +844,50 @@ static int get_phy_c22_id(struct mii_bus *bus, int addr, u32 *phy_id) return 0; } @@ -428,7 +434,7 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs /** * get_phy_device - reads the specified PHY device and returns its @phy_device * struct -@@ -853,6 +925,15 @@ struct phy_device *get_phy_device(struct +@@ -853,6 +925,15 @@ struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45) if (r) return ERR_PTR(r); @@ -444,6 +450,8 @@ Subject: [PATCH] net: phy: Add driver for Motorcomm YT8531(S) PHYs return phy_device_create(bus, addr, phy_id, is_c45, &c45_ids); } EXPORT_SYMBOL(get_phy_device); +diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h +index facce6d..23cccca 100644 --- a/include/linux/motorcomm_phy.h +++ b/include/linux/motorcomm_phy.h @@ -14,6 +14,8 @@ diff --git a/target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch b/target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch index 11c6c71e8..f369f2bcd 100644 --- a/target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch +++ b/target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch @@ -13,9 +13,9 @@ Signed-off-by: hmz007 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig -@@ -64,6 +64,15 @@ config PHY_ROCKCHIP_NANENG_COMBO_PHY - Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII - combo PHY with NaNeng IP block. +@@ -56,6 +56,15 @@ config PHY_ROCKCHIP_INNO_DSIDPHY + Enable this to support the Rockchip MIPI/LVDS/TTL PHY with + Innosilicon IP block. +config PHY_ROCKCHIP_INNO_USB3 + tristate "Rockchip INNO USB 3.0 PHY Driver" @@ -36,9 +36,9 @@ Signed-off-by: hmz007 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o +obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o - obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o - obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o + obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o + obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt @@ -45,6 +45,8 @@ Required Properties: diff --git a/target/linux/rockchip/patches-5.10/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch b/target/linux/rockchip/patches-5.10/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch index a1c09a1bf..54cd42051 100644 --- a/target/linux/rockchip/patches-5.10/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch +++ b/target/linux/rockchip/patches-5.10/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch @@ -7,6 +7,8 @@ Subject: [PATCH] arm64-dts-doornet1-add-rk3328-dmc-relate-node .../boot/dts/rockchip/rk3328-doornet1.dts | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts +index 8333351..d984163 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts @@ -7,6 +7,7 @@ @@ -17,7 +19,7 @@ Subject: [PATCH] arm64-dts-doornet1-add-rk3328-dmc-relate-node #include "rk3328.dtsi" / { -@@ -58,6 +59,72 @@ +@@ -56,6 +57,72 @@ enable-active-high; }; @@ -90,7 +92,7 @@ Subject: [PATCH] arm64-dts-doornet1-add-rk3328-dmc-relate-node leds { compatible = "gpio-leds"; pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -@@ -140,6 +207,10 @@ +@@ -138,6 +205,10 @@ cpu-supply = <&vdd_arm>; }; @@ -101,7 +103,7 @@ Subject: [PATCH] arm64-dts-doornet1-add-rk3328-dmc-relate-node &gmac2io { assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; -@@ -185,6 +256,7 @@ +@@ -201,6 +272,7 @@ regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; @@ -109,7 +111,7 @@ Subject: [PATCH] arm64-dts-doornet1-add-rk3328-dmc-relate-node regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; regulator-ramp-delay = <12500>; -@@ -199,6 +271,7 @@ +@@ -215,6 +287,7 @@ regulator-name = "vdd_arm"; regulator-always-on; regulator-boot-on; @@ -117,3 +119,6 @@ Subject: [PATCH] arm64-dts-doornet1-add-rk3328-dmc-relate-node regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; regulator-ramp-delay = <12500>; +-- +2.25.1 + diff --git a/target/linux/rockchip/patches-5.10/900-arm64-boot-add-dts-files.patch b/target/linux/rockchip/patches-5.10/900-arm64-boot-add-dts-files.patch deleted file mode 100644 index 3c5011b4a..000000000 --- a/target/linux/rockchip/patches-5.10/900-arm64-boot-add-dts-files.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -57,3 +57,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-station-p2.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb diff --git a/target/linux/rockchip/patches-5.10/993-rockchip-rk3568-remove-rng-node-for-r66s b/target/linux/rockchip/patches-5.10/993-rockchip-rk3568-remove-rng-node-for-r66s deleted file mode 100644 index a237162a6..000000000 --- a/target/linux/rockchip/patches-5.10/993-rockchip-rk3568-remove-rng-node-for-r66s +++ /dev/null @@ -1,13 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts -@@ -456,10 +456,6 @@ - status = "okay"; - }; - --&rng { -- status = "okay"; --}; -- - &saradc { - vref-supply = <&vcca_1v8>; - status = "okay";