mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
rockchip: add yt85xx eth support for R2C
This commit is contained in:
lean
parent
56c4a5e91c
commit
b1b36c86af
@ -17,8 +17,7 @@ endef
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include $(INCLUDE_DIR)/target.mk
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DEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug \
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automount autocore-arm autosamba fdisk cfdisk e2fsprogs ethtool haveged htop \
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luci-app-zerotier luci-app-ipsec-vpnd
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automount autocore-arm fdisk e2fsprogs
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KERNELNAME:=Image dtbs
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@ -4,8 +4,14 @@
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get_device_irq() {
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local device="$1"
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local line
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local seconds
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local line=$(grep -m 1 "${device}\$" /proc/interrupts)
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# wait up to 10 seconds for the irq/device to appear
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for seconds in $(seq 0 9); do
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line=$(grep -m 1 "${device}\$" /proc/interrupts) && break
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sleep 1
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done
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echo ${line} | sed 's/:.*//'
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}
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@ -22,6 +28,7 @@ set_interface_core() {
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}
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case "$(board_name)" in
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friendlyarm,nanopi-r2c|\
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friendlyarm,nanopi-r2s|\
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xunlong,orangepi-r1-plus|\
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embedfire,doornet1)
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@ -5,8 +5,8 @@ move_config() {
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if export_bootdevice && export_partdevice partdev 1; then
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if mount -o rw,noatime "/dev/$partdev" /mnt; then
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if [ -f "/mnt/$BACKUP_FILE" ]; then
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mv -f "/mnt/$BACKUP_FILE" /
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if [ -f "/mnt/sysupgrade.tgz" ]; then
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mv -f "/mnt/sysupgrade.tgz" /
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fi
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umount /mnt
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fi
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@ -30,7 +30,7 @@ platform_copy_config() {
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if export_partdevice partdev 1; then
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mount -o rw,noatime "/dev/$partdev" /mnt
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cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE"
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cp -af "$CONF_TAR" "/mnt/sysupgrade.tgz"
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umount /mnt
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fi
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}
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@ -45,7 +45,7 @@ platform_do_upgrade() {
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sync
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if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
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if [ "$SAVE_PARTITIONS" = "1" ]; then
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get_partitions "/dev/$diskdev" bootdisk
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#extract the boot sector from the image
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@ -18,9 +18,6 @@ CONFIG_ARC_EMAC_CORE=y
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CONFIG_ARM64=y
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CONFIG_ARM64_4K_PAGES=y
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CONFIG_ARM64_CNP=y
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# CONFIG_ARM64_ERRATUM_1165522 is not set
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# CONFIG_ARM64_ERRATUM_1286807 is not set
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# CONFIG_ARM64_ERRATUM_1418040 is not set
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CONFIG_ARM64_ERRATUM_819472=y
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CONFIG_ARM64_ERRATUM_824069=y
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CONFIG_ARM64_ERRATUM_826319=y
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@ -92,7 +89,6 @@ CONFIG_BLOCK_COMPAT=y
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CONFIG_BRCMSTB_GISB_ARB=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
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# CONFIG_CHARGER_BQ25980 is not set
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CONFIG_CHARGER_GPIO=y
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CONFIG_CLKDEV_LOOKUP=y
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@ -223,7 +219,6 @@ CONFIG_FRAME_WARN=2048
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FS_POSIX_ACL=y
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# CONFIG_FUJITSU_ERRATUM_010001 is not set
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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@ -375,6 +370,7 @@ CONFIG_MMC_SDHCI_OF_DWCMSHC=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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CONFIG_MODULES_USE_ELF_RELA=y
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CONFIG_MOTORCOMM_PHY=y
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CONFIG_MQ_IOSCHED_DEADLINE=y
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# CONFIG_MTD_CFI is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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@ -492,10 +488,6 @@ CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
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CONFIG_RAS=y
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CONFIG_RATIONAL=y
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# CONFIG_RAVE_SP_CORE is not set
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CONFIG_RCU_CPU_STALL_TIMEOUT=21
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# CONFIG_RCU_EXPERT is not set
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CONFIG_RCU_NEED_SEGCBLIST=y
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CONFIG_RCU_STALL_COMMON=y
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CONFIG_RCU_TRACE=y
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CONFIG_REALTEK_PHY=y
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CONFIG_REGMAP=y
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@ -590,7 +582,6 @@ CONFIG_SRAM=y
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CONFIG_SRCU=y
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CONFIG_STACKPROTECTOR=y
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CONFIG_STACKPROTECTOR_STRONG=y
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# CONFIG_STAGING is not set
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CONFIG_STMMAC_ETH=y
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CONFIG_STMMAC_PLATFORM=y
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# CONFIG_STMMAC_SELFTESTS is not set
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@ -19,9 +19,6 @@ CONFIG_ARM64=y
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CONFIG_ARM64_4K_PAGES=y
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CONFIG_ARM64_CNP=y
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CONFIG_ARM64_CONT_SHIFT=4
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# CONFIG_ARM64_ERRATUM_1165522 is not set
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# CONFIG_ARM64_ERRATUM_1286807 is not set
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# CONFIG_ARM64_ERRATUM_1418040 is not set
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CONFIG_ARM64_ERRATUM_819472=y
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CONFIG_ARM64_ERRATUM_824069=y
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CONFIG_ARM64_ERRATUM_826319=y
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@ -91,7 +88,6 @@ CONFIG_BLOCK_COMPAT=y
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CONFIG_BRCMSTB_GISB_ARB=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
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CONFIG_CHARGER_GPIO=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKSRC_MMIO=y
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@ -183,6 +179,7 @@ CONFIG_DMA_REMAP=y
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CONFIG_DMA_SHARED_BUFFER=y
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CONFIG_DNOTIFY=y
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CONFIG_DRM_RCAR_WRITEBACK=y
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# CONFIG_DRM_ROCKCHIP is not set
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CONFIG_DTC=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DUMMY_CONSOLE=y
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@ -209,7 +206,6 @@ CONFIG_FRAME_WARN=2048
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FS_POSIX_ACL=y
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# CONFIG_FUJITSU_ERRATUM_010001 is not set
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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@ -280,6 +276,7 @@ CONFIG_INPUT_KEYBOARD=y
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CONFIG_INPUT_LEDS=y
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CONFIG_INPUT_MATRIXKMAP=y
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# CONFIG_INPUT_MISC is not set
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# CONFIG_INPUT_RK805_PWRKEY is not set
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CONFIG_IOMMU_API=y
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# CONFIG_IOMMU_DEBUGFS is not set
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# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
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@ -355,6 +352,7 @@ CONFIG_MMC_SDHCI_OF_DWCMSHC=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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CONFIG_MODULES_USE_ELF_RELA=y
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CONFIG_MOTORCOMM_PHY=y
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CONFIG_MQ_IOSCHED_DEADLINE=y
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# CONFIG_MTD_CFI is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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@ -470,10 +468,6 @@ CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
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CONFIG_RAS=y
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CONFIG_RATIONAL=y
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# CONFIG_RAVE_SP_CORE is not set
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CONFIG_RCU_CPU_STALL_TIMEOUT=21
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# CONFIG_RCU_EXPERT is not set
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CONFIG_RCU_NEED_SEGCBLIST=y
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CONFIG_RCU_STALL_COMMON=y
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CONFIG_RCU_TRACE=y
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CONFIG_REALTEK_PHY=y
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CONFIG_REFCOUNT_FULL=y
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@ -490,6 +484,8 @@ CONFIG_REGULATOR_RK808=y
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CONFIG_RELOCATABLE=y
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CONFIG_RESET_CONTROLLER=y
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CONFIG_RFS_ACCEL=y
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# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
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# CONFIG_ROCKCHIP_CDN_DP is not set
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CONFIG_ROCKCHIP_EFUSE=y
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CONFIG_ROCKCHIP_GRF=y
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CONFIG_ROCKCHIP_IODOMAIN=y
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@ -497,6 +493,9 @@ CONFIG_ROCKCHIP_IOMMU=y
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CONFIG_ROCKCHIP_MBOX=y
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CONFIG_ROCKCHIP_PHY=y
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CONFIG_ROCKCHIP_PM_DOMAINS=y
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# CONFIG_ROCKCHIP_RGB is not set
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# CONFIG_ROCKCHIP_RK3066_HDMI is not set
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# CONFIG_ROCKCHIP_SARADC is not set
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CONFIG_ROCKCHIP_THERMAL=y
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CONFIG_ROCKCHIP_TIMER=y
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CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
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@ -540,6 +539,7 @@ CONFIG_SG_POOL=y
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CONFIG_SIMPLE_PM_BUS=y
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CONFIG_SLUB_DEBUG=y
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CONFIG_SMP=y
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# CONFIG_SND_SOC_ROCKCHIP is not set
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CONFIG_SPARSEMEM=y
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CONFIG_SPARSEMEM_EXTREME=y
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CONFIG_SPARSEMEM_MANUAL=y
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@ -562,7 +562,6 @@ CONFIG_SRAM=y
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CONFIG_SRCU=y
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CONFIG_STACKPROTECTOR=y
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CONFIG_STACKPROTECTOR_STRONG=y
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# CONFIG_STAGING is not set
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CONFIG_STMMAC_ETH=y
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CONFIG_STMMAC_PLATFORM=y
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# CONFIG_STMMAC_SELFTESTS is not set
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@ -75,4 +75,4 @@ endef
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include $(SUBTARGET).mk
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$(eval $(call BuildImage))
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$(eval $(call BuildImage))
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@ -71,4 +71,5 @@ define Device/embedfire_doornet1
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IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
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DEVICE_PACKAGES := kmod-usb-net-rtl8152
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endef
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TARGET_DEVICES += embedfire_doornet1
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TARGET_DEVICES += embedfire_doornet1
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@ -19,7 +19,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
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+&gmac {
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+ nvmem-cells = <&mac_address>;
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+ nvmem-cells-names = "mac-address";
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+ nvmem-cell-names = "mac-address";
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+};
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+
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+&i2c2 {
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@ -1,6 +1,6 @@
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--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
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@@ -83,6 +83,19 @@
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@@ -101,6 +101,19 @@
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max-link-speed = <1>;
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num-lanes = <1>;
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vpcie3v3-supply = <&vcc3v3_sys>;
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@ -24,7 +24,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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--- a/drivers/mmc/core/core.c
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+++ b/drivers/mmc/core/core.c
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@@ -1351,6 +1351,8 @@ void mmc_power_off(struct mmc_host *host
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@@ -1354,6 +1354,8 @@ void mmc_power_off(struct mmc_host *host
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mmc_pwrseq_power_off(host);
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@ -1,6 +1,6 @@
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -7,6 +7,7 @@
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@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
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@ -0,0 +1,457 @@
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From 5d6862cc5eac1679d7a4ef388f7c9bbc70e76770 Mon Sep 17 00:00:00 2001
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From: hmz007 <hmz007@gmail.com>
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Date: Mon, 5 Jul 2021 17:03:00 +0800
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Subject: [PATCH] net: phy: Add driver for Motorcomm YT85xx PHYs
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Signed-off-by: hmz007 <hmz007@gmail.com>
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---
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drivers/net/phy/Kconfig | 5 +
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drivers/net/phy/Makefile | 1 +
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drivers/net/phy/motorcomm.c | 346 ++++++++++++++++++++++++++++++++++
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include/linux/motorcomm_phy.h | 68 +++++++
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4 files changed, 420 insertions(+)
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create mode 100644 drivers/net/phy/motorcomm.c
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create mode 100644 include/linux/motorcomm_phy.h
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -297,6 +297,11 @@ config MICROSEMI_PHY
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help
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Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
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+config MOTORCOMM_PHY
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+ tristate "Motorcomm PHYs"
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+ help
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+ Supports the YT8010, YT8510, YT8511, YT8512 PHYs.
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+
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config NATIONAL_PHY
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tristate "National Semiconductor PHYs"
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help
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -82,6 +82,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o
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obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
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obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o
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obj-$(CONFIG_MICROSEMI_PHY) += mscc/
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+obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm.o
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obj-$(CONFIG_NATIONAL_PHY) += national.o
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obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
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obj-$(CONFIG_QSEMI_PHY) += qsemi.o
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--- /dev/null
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+++ b/drivers/net/phy/motorcomm.c
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@@ -0,0 +1,345 @@
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+/*
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+ * drivers/net/phy/motorcomm.c
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+ *
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+ * Driver for Motorcomm PHYs
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+ *
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+ * Author: Leilei Zhao <leilei.zhao@motorcomm.com>
|
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+ *
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+ * Copyright (c) 2019 Motorcomm, Inc.
|
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
|
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+ * under the terms of the GNU General Public License as published by the
|
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+ * Free Software Foundation; either version 2 of the License, or (at your
|
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+ * option) any later version.
|
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+ *
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+ * Support : Motorcomm Phys:
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+ * Giga phys: yt8511, yt8521
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+ * 100/10 Phys : yt8512, yt8512b, yt8510
|
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+ * Automotive 100Mb Phys : yt8010
|
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+ * Automotive 100/10 hyper range Phys: yt8510
|
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+ */
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+
|
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+#include <linux/kernel.h>
|
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+#include <linux/module.h>
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+#include <linux/phy.h>
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+#include <linux/motorcomm_phy.h>
|
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+#include <linux/of.h>
|
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+#include <linux/clk.h>
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+
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+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
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+{
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+ int ret;
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+ int val;
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+
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+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
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+ if (ret < 0)
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+ return ret;
|
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+
|
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+ val = phy_read(phydev, REG_DEBUG_DATA);
|
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+
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+ return val;
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+}
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+
|
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+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
|
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+{
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+ int ret;
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+
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+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
|
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+ if (ret < 0)
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+ return ret;
|
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+
|
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+ ret = phy_write(phydev, REG_DEBUG_DATA, val);
|
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+
|
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+ return ret;
|
||||
+}
|
||||
+
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||||
+static int yt8010_config_aneg(struct phy_device *phydev)
|
||||
+{
|
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+ phydev->speed = SPEED_100;
|
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+ return 0;
|
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+}
|
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+
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+static int yt8512_clk_init(struct phy_device *phydev)
|
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+{
|
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+ int ret;
|
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+ int val;
|
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+
|
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+ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
|
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+ if (val < 0)
|
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+ return val;
|
||||
+
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+ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
|
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+
|
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+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
|
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+ if (ret < 0)
|
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+ return ret;
|
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+
|
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+ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
|
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+ if (val < 0)
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+ return val;
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+
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+ val |= YT8512_CONTROL1_RMII_EN;
|
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+
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+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
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+ if (ret < 0)
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+ return ret;
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+
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+ val = phy_read(phydev, MII_BMCR);
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+ if (val < 0)
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+ return val;
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+
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+ val |= YT_SOFTWARE_RESET;
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+ ret = phy_write(phydev, MII_BMCR, val);
|
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+
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+ return ret;
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+}
|
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+
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+static int yt8512_led_init(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
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+ int val;
|
||||
+ int mask;
|
||||
+
|
||||
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val |= YT8512_LED0_ACT_BLK_IND;
|
||||
+
|
||||
+ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
|
||||
+ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
|
||||
+ YT8512_LED0_BT_ON_EN;
|
||||
+ val &= ~mask;
|
||||
+
|
||||
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val |= YT8512_LED1_BT_ON_EN;
|
||||
+
|
||||
+ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
|
||||
+ val &= ~mask;
|
||||
+
|
||||
+ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int yt8512_config_init(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int val;
|
||||
+
|
||||
+ ret = yt8512_clk_init(phydev);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = yt8512_led_init(phydev);
|
||||
+
|
||||
+ /* disable auto sleep */
|
||||
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
|
||||
+
|
||||
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int yt8512_read_status(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int val;
|
||||
+ int speed, speed_mode, duplex;
|
||||
+
|
||||
+ ret = genphy_update_link(phydev);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
|
||||
+ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
|
||||
+ switch (speed_mode) {
|
||||
+ case 0:
|
||||
+ speed = SPEED_10;
|
||||
+ break;
|
||||
+ case 1:
|
||||
+ speed = SPEED_100;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ case 3:
|
||||
+ default:
|
||||
+ speed = SPEED_UNKNOWN;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ phydev->speed = speed;
|
||||
+ phydev->duplex = duplex;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int yt8521_config_init(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int val;
|
||||
+
|
||||
+ /* disable auto sleep */
|
||||
+ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
|
||||
+ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* switch to access UTP */
|
||||
+ ret = ytphy_write_ext(phydev, 0xa000, 0);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* enable RXC clock when no wire plug */
|
||||
+ val = ytphy_read_ext(phydev, 0xc);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val &= ~(1 << 12);
|
||||
+ ret = ytphy_write_ext(phydev, 0xc, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* output SyncE clock (125mhz) even link is down */
|
||||
+ ret = ytphy_write_ext(phydev, 0xa012, 0x38);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* disable rgmii clk 2ns delay */
|
||||
+ val = ytphy_read_ext(phydev, 0xa001);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val &= ~(1 << 8);
|
||||
+ ret = ytphy_write_ext(phydev, 0xa001, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* setup delay */
|
||||
+ val = (1 << 10) | (0xf << 4) | 5;
|
||||
+ ret = ytphy_write_ext(phydev, 0xa003, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
|
||||
+ ytphy_write_ext(phydev, 0xa00b, 0xe004);
|
||||
+ ytphy_write_ext(phydev, 0xa00c, 0);
|
||||
+ ytphy_write_ext(phydev, 0xa00d, 0x2600);
|
||||
+ ytphy_write_ext(phydev, 0xa00e, 0x0070);
|
||||
+ ytphy_write_ext(phydev, 0xa00f, 0x000a);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int yt8521_config_intr(struct phy_device *phydev)
|
||||
+{
|
||||
+ int val;
|
||||
+
|
||||
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
||||
+ val = BIT(14) | BIT(13) | BIT(11) | BIT(10);
|
||||
+ else
|
||||
+ val = 0;
|
||||
+
|
||||
+ return phy_write(phydev, REG_INT_MASK, val);
|
||||
+}
|
||||
+
|
||||
+static int yt8521_ack_interrupt(struct phy_device *phydev)
|
||||
+{
|
||||
+ int val;
|
||||
+
|
||||
+ val = phy_read(phydev, REG_INT_STATUS);
|
||||
+ phydev_dbg(phydev, "intr status 0x04%x\n", val);
|
||||
+
|
||||
+ return (val < 0) ? val : 0;
|
||||
+}
|
||||
+
|
||||
+static struct phy_driver ytphy_drvs[] = {
|
||||
+ {
|
||||
+ .phy_id = PHY_ID_YT8010,
|
||||
+ .name = "YT8010 Automotive Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_BASIC_FEATURES,
|
||||
+ .config_aneg = yt8010_config_aneg,
|
||||
+ .read_status = genphy_read_status,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8510,
|
||||
+ .name = "YT8510 100/10Mb Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_BASIC_FEATURES,
|
||||
+ .read_status = genphy_read_status,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8511,
|
||||
+ .name = "YT8511 Gigabit Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_GBIT_FEATURES,
|
||||
+ .read_status = genphy_read_status,
|
||||
+ .suspend = genphy_suspend,
|
||||
+ .resume = genphy_resume,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8512,
|
||||
+ .name = "YT8512 Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_BASIC_FEATURES,
|
||||
+ .config_init = yt8512_config_init,
|
||||
+ .read_status = yt8512_read_status,
|
||||
+ .suspend = genphy_suspend,
|
||||
+ .resume = genphy_resume,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8512B,
|
||||
+ .name = "YT8512B Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_BASIC_FEATURES,
|
||||
+ .config_init = yt8512_config_init,
|
||||
+ .read_status = yt8512_read_status,
|
||||
+ .suspend = genphy_suspend,
|
||||
+ .resume = genphy_resume,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8521,
|
||||
+ .name = "YT8521 Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ /* PHY_GBIT_FEATURES */
|
||||
+ .config_init = yt8521_config_init,
|
||||
+ .ack_interrupt = yt8521_ack_interrupt,
|
||||
+ .config_intr = yt8521_config_intr,
|
||||
+ .suspend = genphy_suspend,
|
||||
+ .resume = genphy_resume,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_phy_driver(ytphy_drvs);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Motorcomm PHY driver");
|
||||
+MODULE_AUTHOR("Leilei Zhao");
|
||||
+MODULE_LICENSE("GPL");
|
||||
+
|
||||
+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
|
||||
+ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { }
|
||||
+};
|
||||
+
|
||||
+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
|
||||
--- /dev/null
|
||||
+++ b/include/linux/motorcomm_phy.h
|
||||
@@ -0,0 +1,67 @@
|
||||
+/*
|
||||
+ * include/linux/motorcomm_phy.h
|
||||
+ *
|
||||
+ * Motorcomm PHY IDs
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License as published by the
|
||||
+ * Free Software Foundation; either version 2 of the License, or (at your
|
||||
+ * option) any later version.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#ifndef _MOTORCOMM_PHY_H
|
||||
+#define _MOTORCOMM_PHY_H
|
||||
+
|
||||
+#define MOTORCOMM_PHY_ID_MASK 0x00000fff
|
||||
+
|
||||
+#define PHY_ID_YT8010 0x00000309
|
||||
+#define PHY_ID_YT8510 0x00000109
|
||||
+#define PHY_ID_YT8511 0x0000010a
|
||||
+#define PHY_ID_YT8512 0x00000118
|
||||
+#define PHY_ID_YT8512B 0x00000128
|
||||
+#define PHY_ID_YT8521 0x0000011a
|
||||
+
|
||||
+#define REG_PHY_SPEC_STATUS 0x11
|
||||
+#define REG_INT_MASK 0x12
|
||||
+#define REG_INT_STATUS 0x13
|
||||
+#define REG_DEBUG_ADDR_OFFSET 0x1e
|
||||
+#define REG_DEBUG_DATA 0x1f
|
||||
+
|
||||
+#define YT8512_EXTREG_AFE_PLL 0x50
|
||||
+#define YT8512_EXTREG_EXTEND_COMBO 0x4000
|
||||
+#define YT8512_EXTREG_LED0 0x40c0
|
||||
+#define YT8512_EXTREG_LED1 0x40c3
|
||||
+
|
||||
+#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
|
||||
+
|
||||
+#define YT_SOFTWARE_RESET 0x8000
|
||||
+
|
||||
+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040
|
||||
+#define YT8512_CONTROL1_RMII_EN 0x0001
|
||||
+#define YT8512_LED0_ACT_BLK_IND 0x1000
|
||||
+#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
|
||||
+#define YT8512_LED0_BT_BLK_EN 0x0002
|
||||
+#define YT8512_LED0_HT_BLK_EN 0x0004
|
||||
+#define YT8512_LED0_COL_BLK_EN 0x0008
|
||||
+#define YT8512_LED0_BT_ON_EN 0x0010
|
||||
+#define YT8512_LED1_BT_ON_EN 0x0010
|
||||
+#define YT8512_LED1_TXACT_BLK_EN 0x0100
|
||||
+#define YT8512_LED1_RXACT_BLK_EN 0x0200
|
||||
+#define YT8512_SPEED_MODE 0xc000
|
||||
+#define YT8512_DUPLEX 0x2000
|
||||
+
|
||||
+#define YT8512_SPEED_MODE_BIT 14
|
||||
+#define YT8512_DUPLEX_BIT 13
|
||||
+#define YT8512_EN_SLEEP_SW_BIT 15
|
||||
+
|
||||
+#define YT8521_EXTREG_SLEEP_CONTROL1 0x27
|
||||
+#define YT8521_EN_SLEEP_SW_BIT 15
|
||||
+
|
||||
+#define YT8521_SPEED_MODE 0xc000
|
||||
+#define YT8521_DUPLEX 0x2000
|
||||
+#define YT8521_SPEED_MODE_BIT 14
|
||||
+#define YT8521_DUPLEX_BIT 13
|
||||
+#define YT8521_LINK_STATUS_BIT 10
|
||||
+
|
||||
+#endif /* _MOTORCOMM_PHY_H */
|
||||
@ -19,7 +19,7 @@ Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
|
||||
+&gmac {
|
||||
+ nvmem-cells = <&mac_address>;
|
||||
+ nvmem-cells-names = "mac-address";
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
+&i2c2 {
|
||||
|
||||
@ -24,7 +24,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
|
||||
--- a/drivers/mmc/core/core.c
|
||||
+++ b/drivers/mmc/core/core.c
|
||||
@@ -1368,6 +1368,8 @@ void mmc_power_off(struct mmc_host *host
|
||||
@@ -1371,6 +1371,8 @@ void mmc_power_off(struct mmc_host *host
|
||||
|
||||
mmc_pwrseq_power_off(host);
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -83,6 +83,19 @@
|
||||
@@ -101,6 +101,19 @@
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
|
||||
@ -0,0 +1,457 @@
|
||||
From 5d6862cc5eac1679d7a4ef388f7c9bbc70e76770 Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Mon, 5 Jul 2021 17:03:00 +0800
|
||||
Subject: [PATCH] net: phy: Add driver for Motorcomm YT85xx PHYs
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/net/phy/Kconfig | 5 +
|
||||
drivers/net/phy/Makefile | 1 +
|
||||
drivers/net/phy/motorcomm.c | 346 ++++++++++++++++++++++++++++++++++
|
||||
include/linux/motorcomm_phy.h | 68 +++++++
|
||||
4 files changed, 420 insertions(+)
|
||||
create mode 100644 drivers/net/phy/motorcomm.c
|
||||
create mode 100644 include/linux/motorcomm_phy.h
|
||||
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -519,6 +519,11 @@ config MICROSEMI_PHY
|
||||
---help---
|
||||
Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
|
||||
|
||||
+config MOTORCOMM_PHY
|
||||
+ tristate "Motorcomm PHYs"
|
||||
+ ---help---
|
||||
+ Supports the YT8010, YT8510, YT8511, YT8512 PHYs.
|
||||
+
|
||||
config NATIONAL_PHY
|
||||
tristate "National Semiconductor PHYs"
|
||||
---help---
|
||||
--- a/drivers/net/phy/Makefile
|
||||
+++ b/drivers/net/phy/Makefile
|
||||
@@ -98,6 +98,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o
|
||||
obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
|
||||
obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o
|
||||
obj-$(CONFIG_MICROSEMI_PHY) += mscc.o
|
||||
+obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm.o
|
||||
obj-$(CONFIG_NATIONAL_PHY) += national.o
|
||||
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
|
||||
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/phy/motorcomm.c
|
||||
@@ -0,0 +1,345 @@
|
||||
+/*
|
||||
+ * drivers/net/phy/motorcomm.c
|
||||
+ *
|
||||
+ * Driver for Motorcomm PHYs
|
||||
+ *
|
||||
+ * Author: Leilei Zhao <leilei.zhao@motorcomm.com>
|
||||
+ *
|
||||
+ * Copyright (c) 2019 Motorcomm, Inc.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License as published by the
|
||||
+ * Free Software Foundation; either version 2 of the License, or (at your
|
||||
+ * option) any later version.
|
||||
+ *
|
||||
+ * Support : Motorcomm Phys:
|
||||
+ * Giga phys: yt8511, yt8521
|
||||
+ * 100/10 Phys : yt8512, yt8512b, yt8510
|
||||
+ * Automotive 100Mb Phys : yt8010
|
||||
+ * Automotive 100/10 hyper range Phys: yt8510
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/phy.h>
|
||||
+#include <linux/motorcomm_phy.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/clk.h>
|
||||
+
|
||||
+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int val;
|
||||
+
|
||||
+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ val = phy_read(phydev, REG_DEBUG_DATA);
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = phy_write(phydev, REG_DEBUG_DATA, val);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int yt8010_config_aneg(struct phy_device *phydev)
|
||||
+{
|
||||
+ phydev->speed = SPEED_100;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int yt8512_clk_init(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int val;
|
||||
+
|
||||
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
|
||||
+
|
||||
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val |= YT8512_CONTROL1_RMII_EN;
|
||||
+
|
||||
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ val = phy_read(phydev, MII_BMCR);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val |= YT_SOFTWARE_RESET;
|
||||
+ ret = phy_write(phydev, MII_BMCR, val);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int yt8512_led_init(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int val;
|
||||
+ int mask;
|
||||
+
|
||||
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val |= YT8512_LED0_ACT_BLK_IND;
|
||||
+
|
||||
+ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
|
||||
+ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
|
||||
+ YT8512_LED0_BT_ON_EN;
|
||||
+ val &= ~mask;
|
||||
+
|
||||
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val |= YT8512_LED1_BT_ON_EN;
|
||||
+
|
||||
+ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
|
||||
+ val &= ~mask;
|
||||
+
|
||||
+ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int yt8512_config_init(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int val;
|
||||
+
|
||||
+ ret = yt8512_clk_init(phydev);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = yt8512_led_init(phydev);
|
||||
+
|
||||
+ /* disable auto sleep */
|
||||
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
|
||||
+
|
||||
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int yt8512_read_status(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int val;
|
||||
+ int speed, speed_mode, duplex;
|
||||
+
|
||||
+ ret = genphy_update_link(phydev);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
|
||||
+ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
|
||||
+ switch (speed_mode) {
|
||||
+ case 0:
|
||||
+ speed = SPEED_10;
|
||||
+ break;
|
||||
+ case 1:
|
||||
+ speed = SPEED_100;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ case 3:
|
||||
+ default:
|
||||
+ speed = SPEED_UNKNOWN;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ phydev->speed = speed;
|
||||
+ phydev->duplex = duplex;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int yt8521_config_init(struct phy_device *phydev)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int val;
|
||||
+
|
||||
+ /* disable auto sleep */
|
||||
+ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
|
||||
+ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* switch to access UTP */
|
||||
+ ret = ytphy_write_ext(phydev, 0xa000, 0);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* enable RXC clock when no wire plug */
|
||||
+ val = ytphy_read_ext(phydev, 0xc);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val &= ~(1 << 12);
|
||||
+ ret = ytphy_write_ext(phydev, 0xc, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* output SyncE clock (125mhz) even link is down */
|
||||
+ ret = ytphy_write_ext(phydev, 0xa012, 0x38);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* disable rgmii clk 2ns delay */
|
||||
+ val = ytphy_read_ext(phydev, 0xa001);
|
||||
+ if (val < 0)
|
||||
+ return val;
|
||||
+
|
||||
+ val &= ~(1 << 8);
|
||||
+ ret = ytphy_write_ext(phydev, 0xa001, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* setup delay */
|
||||
+ val = (1 << 10) | (0xf << 4) | 5;
|
||||
+ ret = ytphy_write_ext(phydev, 0xa003, val);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
|
||||
+ ytphy_write_ext(phydev, 0xa00b, 0xe004);
|
||||
+ ytphy_write_ext(phydev, 0xa00c, 0);
|
||||
+ ytphy_write_ext(phydev, 0xa00d, 0x2600);
|
||||
+ ytphy_write_ext(phydev, 0xa00e, 0x0070);
|
||||
+ ytphy_write_ext(phydev, 0xa00f, 0x000a);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int yt8521_config_intr(struct phy_device *phydev)
|
||||
+{
|
||||
+ int val;
|
||||
+
|
||||
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
||||
+ val = BIT(14) | BIT(13) | BIT(11) | BIT(10);
|
||||
+ else
|
||||
+ val = 0;
|
||||
+
|
||||
+ return phy_write(phydev, REG_INT_MASK, val);
|
||||
+}
|
||||
+
|
||||
+static int yt8521_ack_interrupt(struct phy_device *phydev)
|
||||
+{
|
||||
+ int val;
|
||||
+
|
||||
+ val = phy_read(phydev, REG_INT_STATUS);
|
||||
+ phydev_dbg(phydev, "intr status 0x04%x\n", val);
|
||||
+
|
||||
+ return (val < 0) ? val : 0;
|
||||
+}
|
||||
+
|
||||
+static struct phy_driver ytphy_drvs[] = {
|
||||
+ {
|
||||
+ .phy_id = PHY_ID_YT8010,
|
||||
+ .name = "YT8010 Automotive Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_BASIC_FEATURES,
|
||||
+ .config_aneg = yt8010_config_aneg,
|
||||
+ .read_status = genphy_read_status,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8510,
|
||||
+ .name = "YT8510 100/10Mb Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_BASIC_FEATURES,
|
||||
+ .read_status = genphy_read_status,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8511,
|
||||
+ .name = "YT8511 Gigabit Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_GBIT_FEATURES,
|
||||
+ .read_status = genphy_read_status,
|
||||
+ .suspend = genphy_suspend,
|
||||
+ .resume = genphy_resume,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8512,
|
||||
+ .name = "YT8512 Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_BASIC_FEATURES,
|
||||
+ .config_init = yt8512_config_init,
|
||||
+ .read_status = yt8512_read_status,
|
||||
+ .suspend = genphy_suspend,
|
||||
+ .resume = genphy_resume,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8512B,
|
||||
+ .name = "YT8512B Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ .features = PHY_BASIC_FEATURES,
|
||||
+ .config_init = yt8512_config_init,
|
||||
+ .read_status = yt8512_read_status,
|
||||
+ .suspend = genphy_suspend,
|
||||
+ .resume = genphy_resume,
|
||||
+ }, {
|
||||
+ .phy_id = PHY_ID_YT8521,
|
||||
+ .name = "YT8521 Ethernet",
|
||||
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
|
||||
+ /* PHY_GBIT_FEATURES */
|
||||
+ .config_init = yt8521_config_init,
|
||||
+ .ack_interrupt = yt8521_ack_interrupt,
|
||||
+ .config_intr = yt8521_config_intr,
|
||||
+ .suspend = genphy_suspend,
|
||||
+ .resume = genphy_resume,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_phy_driver(ytphy_drvs);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Motorcomm PHY driver");
|
||||
+MODULE_AUTHOR("Leilei Zhao");
|
||||
+MODULE_LICENSE("GPL");
|
||||
+
|
||||
+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
|
||||
+ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
|
||||
+ { }
|
||||
+};
|
||||
+
|
||||
+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
|
||||
--- /dev/null
|
||||
+++ b/include/linux/motorcomm_phy.h
|
||||
@@ -0,0 +1,67 @@
|
||||
+/*
|
||||
+ * include/linux/motorcomm_phy.h
|
||||
+ *
|
||||
+ * Motorcomm PHY IDs
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License as published by the
|
||||
+ * Free Software Foundation; either version 2 of the License, or (at your
|
||||
+ * option) any later version.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#ifndef _MOTORCOMM_PHY_H
|
||||
+#define _MOTORCOMM_PHY_H
|
||||
+
|
||||
+#define MOTORCOMM_PHY_ID_MASK 0x00000fff
|
||||
+
|
||||
+#define PHY_ID_YT8010 0x00000309
|
||||
+#define PHY_ID_YT8510 0x00000109
|
||||
+#define PHY_ID_YT8511 0x0000010a
|
||||
+#define PHY_ID_YT8512 0x00000118
|
||||
+#define PHY_ID_YT8512B 0x00000128
|
||||
+#define PHY_ID_YT8521 0x0000011a
|
||||
+
|
||||
+#define REG_PHY_SPEC_STATUS 0x11
|
||||
+#define REG_INT_MASK 0x12
|
||||
+#define REG_INT_STATUS 0x13
|
||||
+#define REG_DEBUG_ADDR_OFFSET 0x1e
|
||||
+#define REG_DEBUG_DATA 0x1f
|
||||
+
|
||||
+#define YT8512_EXTREG_AFE_PLL 0x50
|
||||
+#define YT8512_EXTREG_EXTEND_COMBO 0x4000
|
||||
+#define YT8512_EXTREG_LED0 0x40c0
|
||||
+#define YT8512_EXTREG_LED1 0x40c3
|
||||
+
|
||||
+#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
|
||||
+
|
||||
+#define YT_SOFTWARE_RESET 0x8000
|
||||
+
|
||||
+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040
|
||||
+#define YT8512_CONTROL1_RMII_EN 0x0001
|
||||
+#define YT8512_LED0_ACT_BLK_IND 0x1000
|
||||
+#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
|
||||
+#define YT8512_LED0_BT_BLK_EN 0x0002
|
||||
+#define YT8512_LED0_HT_BLK_EN 0x0004
|
||||
+#define YT8512_LED0_COL_BLK_EN 0x0008
|
||||
+#define YT8512_LED0_BT_ON_EN 0x0010
|
||||
+#define YT8512_LED1_BT_ON_EN 0x0010
|
||||
+#define YT8512_LED1_TXACT_BLK_EN 0x0100
|
||||
+#define YT8512_LED1_RXACT_BLK_EN 0x0200
|
||||
+#define YT8512_SPEED_MODE 0xc000
|
||||
+#define YT8512_DUPLEX 0x2000
|
||||
+
|
||||
+#define YT8512_SPEED_MODE_BIT 14
|
||||
+#define YT8512_DUPLEX_BIT 13
|
||||
+#define YT8512_EN_SLEEP_SW_BIT 15
|
||||
+
|
||||
+#define YT8521_EXTREG_SLEEP_CONTROL1 0x27
|
||||
+#define YT8521_EN_SLEEP_SW_BIT 15
|
||||
+
|
||||
+#define YT8521_SPEED_MODE 0xc000
|
||||
+#define YT8521_DUPLEX 0x2000
|
||||
+#define YT8521_SPEED_MODE_BIT 14
|
||||
+#define YT8521_DUPLEX_BIT 13
|
||||
+#define YT8521_LINK_STATUS_BIT 10
|
||||
+
|
||||
+#endif /* _MOTORCOMM_PHY_H */
|
||||
Loading…
Reference in New Issue
Block a user