mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
rockchip: add kernel 6.6 support
This commit is contained in:
aiamadeus
parent
38ed25d038
commit
af6fdbd097
@ -7,8 +7,8 @@ BOARDNAME:=Rockchip
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FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
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FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
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SUBTARGETS:=armv8
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SUBTARGETS:=armv8
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KERNEL_PATCHVER:=5.15
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KERNEL_PATCHVER:=6.1
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KERNEL_TESTING_PATCHVER:=6.1
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KERNEL_TESTING_PATCHVER:=6.6
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define Target/Description
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define Target/Description
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Build firmware image for Rockchip SoC devices.
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Build firmware image for Rockchip SoC devices.
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726
target/linux/rockchip/armv8/config-6.6
Normal file
726
target/linux/rockchip/armv8/config-6.6
Normal file
@ -0,0 +1,726 @@
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CONFIG_64BIT=y
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CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
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CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
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CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_FORCE_MAX_ORDER=10
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
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CONFIG_ARCH_MMAP_RND_BITS=18
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CONFIG_ARCH_MMAP_RND_BITS_MAX=33
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CONFIG_ARCH_MMAP_RND_BITS_MIN=18
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
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CONFIG_ARCH_PROC_KCORE_TEXT=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_SELECTS_KEXEC_FILE=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_STACKWALK=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_WANTS_NO_INSTR=y
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CONFIG_ARCH_WANTS_THP_SWAP=y
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CONFIG_ARC_EMAC_CORE=y
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CONFIG_ARM64=y
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CONFIG_ARM64_4K_PAGES=y
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CONFIG_ARM64_CNP=y
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CONFIG_ARM64_EPAN=y
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CONFIG_ARM64_ERRATUM_1742098=y
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CONFIG_ARM64_ERRATUM_819472=y
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CONFIG_ARM64_ERRATUM_824069=y
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CONFIG_ARM64_ERRATUM_826319=y
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CONFIG_ARM64_ERRATUM_827319=y
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CONFIG_ARM64_ERRATUM_832075=y
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CONFIG_ARM64_ERRATUM_843419=y
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CONFIG_ARM64_ERRATUM_845719=y
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CONFIG_ARM64_ERRATUM_858921=y
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CONFIG_ARM64_HW_AFDBM=y
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CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
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CONFIG_ARM64_PAGE_SHIFT=12
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CONFIG_ARM64_PAN=y
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CONFIG_ARM64_PA_BITS=48
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CONFIG_ARM64_PA_BITS_48=y
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CONFIG_ARM64_PTR_AUTH=y
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CONFIG_ARM64_PTR_AUTH_KERNEL=y
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CONFIG_ARM64_RAS_EXTN=y
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CONFIG_ARM64_SVE=y
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# CONFIG_ARM64_SW_TTBR0_PAN is not set
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CONFIG_ARM64_TAGGED_ADDR_ABI=y
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CONFIG_ARM64_VA_BITS=48
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# CONFIG_ARM64_VA_BITS_39 is not set
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CONFIG_ARM64_VA_BITS_48=y
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CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
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# CONFIG_ARMV8_DEPRECATED is not set
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CONFIG_ARM_AMBA=y
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CONFIG_ARM_ARCH_TIMER=y
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CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
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CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_GIC_V2M=y
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CONFIG_ARM_GIC_V3=y
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CONFIG_ARM_GIC_V3_ITS=y
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CONFIG_ARM_GIC_V3_ITS_PCI=y
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CONFIG_ARM_MHU=y
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# CONFIG_ARM_MHU_V2 is not set
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CONFIG_ARM_PSCI_CPUIDLE=y
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CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
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CONFIG_ARM_PSCI_FW=y
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CONFIG_ARM_RK3328_DMC_DEVFREQ=y
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# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
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# CONFIG_ARM_SCMI_CPUFREQ is not set
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CONFIG_ARM_SCMI_HAVE_SHMEM=y
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CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
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CONFIG_ARM_SCMI_POWER_CONTROL=y
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CONFIG_ARM_SCMI_POWER_DOMAIN=y
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CONFIG_ARM_SCMI_PROTOCOL=y
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# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
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CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
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CONFIG_ARM_SCMI_TRANSPORT_SMC=y
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# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
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CONFIG_ARM_SCPI_CPUFREQ=y
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CONFIG_ARM_SCPI_POWER_DOMAIN=y
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CONFIG_ARM_SCPI_PROTOCOL=y
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CONFIG_ARM_SMMU=y
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CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
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# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
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CONFIG_ARM_SMMU_V3=y
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# CONFIG_ARM_SMMU_V3_SVA is not set
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CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_GPIO=y
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CONFIG_BACKLIGHT_PWM=y
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CONFIG_BLK_DEV_BSG=y
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CONFIG_BLK_DEV_BSGLIB=y
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CONFIG_BLK_DEV_BSG_COMMON=y
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# CONFIG_BLK_DEV_INITRD is not set
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CONFIG_BLK_DEV_INTEGRITY=y
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CONFIG_BLK_DEV_INTEGRITY_T10=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_NVME=y
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CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_PM=y
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CONFIG_BRCMSTB_GISB_ARB=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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CONFIG_BUFFER_HEAD=y
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CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
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CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
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CONFIG_CC_NO_ARRAY_BOUNDS=y
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CONFIG_CHARGER_GPIO=y
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# CONFIG_CHARGER_RK817 is not set
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLK_PX30=y
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CONFIG_CLK_RK3308=y
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CONFIG_CLK_RK3328=y
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CONFIG_CLK_RK3368=y
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CONFIG_CLK_RK3399=y
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CONFIG_CLK_RK3568=y
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CONFIG_CLK_RK3588=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMA=y
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CONFIG_CMA_ALIGNMENT=8
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CONFIG_CMA_AREAS=7
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# CONFIG_CMA_DEBUG is not set
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# CONFIG_CMA_DEBUGFS is not set
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CONFIG_CMA_SIZE_MBYTES=64
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# CONFIG_CMA_SIZE_SEL_MAX is not set
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CONFIG_CMA_SIZE_SEL_MBYTES=y
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# CONFIG_CMA_SIZE_SEL_MIN is not set
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# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
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# CONFIG_CMA_SYSFS is not set
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_RK808=y
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CONFIG_COMMON_CLK_ROCKCHIP=y
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CONFIG_COMMON_CLK_SCMI=y
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CONFIG_COMMON_CLK_SCPI=y
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CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
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CONFIG_COMPAT=y
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CONFIG_COMPAT_32BIT_TIME=y
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# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
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CONFIG_COMPAT_BINFMT_ELF=y
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CONFIG_COMPAT_OLD_SIGACTION=y
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CONFIG_CONFIGFS_FS=y
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CONFIG_CONSOLE_TRANSLATIONS=y
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CONFIG_CONTEXT_TRACKING=y
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CONFIG_CONTEXT_TRACKING_IDLE=y
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CONFIG_CONTIG_ALLOC=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_CPUFREQ_DT_PLATDEV=y
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CONFIG_CPU_FREQ=y
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# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
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CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
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CONFIG_CPU_FREQ_GOV_ATTR_SET=y
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# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
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# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
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# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_IDLE=y
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CONFIG_CPU_IDLE_GOV_MENU=y
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CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
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CONFIG_CPU_ISOLATION=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_THERMAL=y
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CONFIG_CRASH_CORE=y
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CONFIG_CRASH_DUMP=y
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CONFIG_CRC16=y
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# CONFIG_CRC32_SARWATE is not set
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CONFIG_CRC32_SLICEBY8=y
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CONFIG_CRC64=y
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CONFIG_CRC64_ROCKSOFT=y
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CONFIG_CRC_T10DIF=y
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CONFIG_CROSS_MEMORY_ATTACH=y
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CONFIG_CRYPTO_AES_ARM64=y
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CONFIG_CRYPTO_AES_ARM64_CE=y
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CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
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CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
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CONFIG_CRYPTO_CRC32=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_CRC64_ROCKSOFT=y
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CONFIG_CRYPTO_CRCT10DIF=y
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CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
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CONFIG_CRYPTO_CRYPTD=y
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CONFIG_CRYPTO_GHASH_ARM64_CE=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_LIB_GF128MUL=y
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CONFIG_CRYPTO_LIB_SHA1=y
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CONFIG_CRYPTO_LIB_SHA256=y
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CONFIG_CRYPTO_LIB_UTILS=y
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CONFIG_CRYPTO_SHA256=y
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CONFIG_CRYPTO_SM4=y
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CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
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CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
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CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
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# CONFIG_DEVFREQ_GOV_PASSIVE is not set
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CONFIG_DEVFREQ_GOV_PERFORMANCE=y
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CONFIG_DEVFREQ_GOV_POWERSAVE=y
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CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
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CONFIG_DEVFREQ_GOV_USERSPACE=y
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# CONFIG_DEVFREQ_THERMAL is not set
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CONFIG_DEVMEM=y
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# CONFIG_DEVPORT is not set
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_DMADEVICES=y
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CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
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CONFIG_DMA_CMA=y
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CONFIG_DMA_DIRECT_REMAP=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_OF=y
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CONFIG_DMA_OPS=y
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CONFIG_DMA_SHARED_BUFFER=y
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CONFIG_DNOTIFY=y
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CONFIG_DTC=y
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CONFIG_DT_IDLE_GENPD=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DUMMY_CONSOLE=y
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CONFIG_DWMAC_DWC_QOS_ETH=y
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CONFIG_DWMAC_GENERIC=y
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CONFIG_DWMAC_ROCKCHIP=y
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CONFIG_DW_WATCHDOG=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EEPROM_AT24=y
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CONFIG_EMAC_ROCKCHIP=y
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CONFIG_ENERGY_MODEL=y
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CONFIG_EXCLUSIVE_SYSTEM_RAM=y
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CONFIG_EXT4_FS=y
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CONFIG_EXT4_FS_POSIX_ACL=y
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CONFIG_EXTCON=y
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CONFIG_F2FS_FS=y
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CONFIG_FANOTIFY=y
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CONFIG_FHANDLE=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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# CONFIG_FORTIFY_SOURCE is not set
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CONFIG_FRAME_POINTER=y
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FS_POSIX_ACL=y
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CONFIG_FUNCTION_ALIGNMENT=4
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CONFIG_FUNCTION_ALIGNMENT_4B=y
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CONFIG_FWNODE_MDIO=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_FW_LOADER_SYSFS=y
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CONFIG_GCC11_NO_ARRAY_BOUNDS=y
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||||||
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CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
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||||||
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CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
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||||||
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CONFIG_GENERIC_ALLOCATOR=y
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||||||
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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CONFIG_GENERIC_BUG=y
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||||||
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CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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||||||
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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||||||
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_CPU_VULNERABILITIES=y
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CONFIG_GENERIC_CSUM=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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||||||
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||||
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CONFIG_GENERIC_IOREMAP=y
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||||||
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CONFIG_GENERIC_IRQ_CHIP=y
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||||||
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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||||||
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CONFIG_GENERIC_IRQ_MIGRATION=y
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||||||
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CONFIG_GENERIC_IRQ_SHOW=y
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||||||
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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||||||
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CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
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||||||
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CONFIG_GENERIC_MSI_IRQ=y
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||||||
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CONFIG_GENERIC_PCI_IOMAP=y
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||||||
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CONFIG_GENERIC_PHY=y
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||||||
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CONFIG_GENERIC_PINCONF=y
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||||||
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CONFIG_GENERIC_SCHED_CLOCK=y
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||||||
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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||||||
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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||||||
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CONFIG_GENERIC_STRNLEN_USER=y
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||||||
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CONFIG_GENERIC_TIME_VSYSCALL=y
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||||||
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CONFIG_GPIOLIB_IRQCHIP=y
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||||||
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CONFIG_GPIO_CDEV=y
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||||||
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CONFIG_GPIO_DWAPB=y
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||||||
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CONFIG_GPIO_GENERIC=y
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||||||
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CONFIG_GPIO_GENERIC_PLATFORM=y
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||||||
|
CONFIG_GPIO_ROCKCHIP=y
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||||||
|
# CONFIG_HARDENED_USERCOPY is not set
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||||||
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CONFIG_HARDIRQS_SW_RESEND=y
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||||||
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CONFIG_HAS_DMA=y
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||||||
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CONFIG_HAS_IOMEM=y
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||||||
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CONFIG_HAS_IOPORT=y
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||||||
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CONFIG_HAS_IOPORT_MAP=y
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||||||
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CONFIG_HID=y
|
||||||
|
CONFIG_HID_SUPPORT=y
|
||||||
|
CONFIG_HOTPLUG_CORE_SYNC=y
|
||||||
|
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
|
||||||
|
CONFIG_HOTPLUG_CPU=y
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||||||
|
CONFIG_HOTPLUG_PCI=y
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||||||
|
# CONFIG_HOTPLUG_PCI_CPCI is not set
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||||||
|
# CONFIG_HOTPLUG_PCI_PCIE is not set
|
||||||
|
# CONFIG_HOTPLUG_PCI_SHPC is not set
|
||||||
|
CONFIG_HUGETLBFS=y
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||||||
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CONFIG_HUGETLB_PAGE=y
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||||||
|
CONFIG_HWMON=y
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||||||
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CONFIG_HWSPINLOCK=y
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||||||
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CONFIG_HW_CONSOLE=y
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||||||
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CONFIG_HW_RANDOM=y
|
||||||
|
CONFIG_HW_RANDOM_ROCKCHIP=y
|
||||||
|
CONFIG_HZ=250
|
||||||
|
# CONFIG_HZ_100 is not set
|
||||||
|
CONFIG_HZ_250=y
|
||||||
|
CONFIG_I2C=y
|
||||||
|
CONFIG_I2C_BOARDINFO=y
|
||||||
|
CONFIG_I2C_CHARDEV=y
|
||||||
|
CONFIG_I2C_COMPAT=y
|
||||||
|
CONFIG_I2C_HELPER_AUTO=y
|
||||||
|
CONFIG_I2C_RK3X=y
|
||||||
|
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||||
|
CONFIG_INDIRECT_PIO=y
|
||||||
|
CONFIG_INPUT=y
|
||||||
|
CONFIG_INPUT_EVDEV=y
|
||||||
|
CONFIG_INPUT_FF_MEMLESS=y
|
||||||
|
CONFIG_INPUT_KEYBOARD=y
|
||||||
|
CONFIG_INPUT_LEDS=y
|
||||||
|
CONFIG_INPUT_MATRIXKMAP=y
|
||||||
|
# CONFIG_INPUT_MISC is not set
|
||||||
|
# CONFIG_IOMMUFD is not set
|
||||||
|
CONFIG_IOMMU_API=y
|
||||||
|
# CONFIG_IOMMU_DEBUGFS is not set
|
||||||
|
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
|
||||||
|
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
|
||||||
|
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
|
||||||
|
CONFIG_IOMMU_DMA=y
|
||||||
|
CONFIG_IOMMU_IOVA=y
|
||||||
|
CONFIG_IOMMU_IO_PGTABLE=y
|
||||||
|
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||||
|
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
|
||||||
|
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
|
||||||
|
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
|
||||||
|
CONFIG_IOMMU_SUPPORT=y
|
||||||
|
# CONFIG_IO_STRICT_DEVMEM is not set
|
||||||
|
CONFIG_IO_URING=y
|
||||||
|
CONFIG_IRQCHIP=y
|
||||||
|
CONFIG_IRQ_DOMAIN=y
|
||||||
|
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||||
|
CONFIG_IRQ_FORCED_THREADING=y
|
||||||
|
CONFIG_IRQ_MSI_IOMMU=y
|
||||||
|
CONFIG_IRQ_TIME_ACCOUNTING=y
|
||||||
|
CONFIG_IRQ_WORK=y
|
||||||
|
CONFIG_JBD2=y
|
||||||
|
CONFIG_JFFS2_ZLIB=y
|
||||||
|
CONFIG_JUMP_LABEL=y
|
||||||
|
CONFIG_KALLSYMS=y
|
||||||
|
CONFIG_KEXEC_CORE=y
|
||||||
|
CONFIG_KEXEC_FILE=y
|
||||||
|
CONFIG_KSM=y
|
||||||
|
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
|
||||||
|
CONFIG_LEDS_GPIO=y
|
||||||
|
CONFIG_LEDS_PWM=y
|
||||||
|
CONFIG_LEDS_SYSCON=y
|
||||||
|
CONFIG_LEDS_TRIGGER_CPU=y
|
||||||
|
CONFIG_LEDS_TRIGGER_PANIC=y
|
||||||
|
CONFIG_LEGACY_PTYS=y
|
||||||
|
CONFIG_LEGACY_PTY_COUNT=16
|
||||||
|
CONFIG_LIBCRC32C=y
|
||||||
|
CONFIG_LIBFDT=y
|
||||||
|
CONFIG_LOCALVERSION_AUTO=y
|
||||||
|
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||||
|
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||||
|
CONFIG_LOG_BUF_SHIFT=19
|
||||||
|
CONFIG_MAGIC_SYSRQ=y
|
||||||
|
CONFIG_MAGIC_SYSRQ_SERIAL=y
|
||||||
|
CONFIG_MAILBOX=y
|
||||||
|
# CONFIG_MAILBOX_TEST is not set
|
||||||
|
CONFIG_MDIO_BUS=y
|
||||||
|
CONFIG_MDIO_BUS_MUX=y
|
||||||
|
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||||
|
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||||
|
CONFIG_MDIO_DEVICE=y
|
||||||
|
CONFIG_MDIO_DEVRES=y
|
||||||
|
CONFIG_MEMORY_ISOLATION=y
|
||||||
|
CONFIG_MFD_CORE=y
|
||||||
|
# CONFIG_MFD_KHADAS_MCU is not set
|
||||||
|
CONFIG_MFD_RK8XX=y
|
||||||
|
CONFIG_MFD_RK8XX_I2C=y
|
||||||
|
CONFIG_MFD_RK8XX_SPI=y
|
||||||
|
CONFIG_MFD_SYSCON=y
|
||||||
|
CONFIG_MIGRATION=y
|
||||||
|
CONFIG_MMC=y
|
||||||
|
CONFIG_MMC_BLOCK=y
|
||||||
|
CONFIG_MMC_BLOCK_MINORS=32
|
||||||
|
CONFIG_MMC_CQHCI=y
|
||||||
|
CONFIG_MMC_DW=y
|
||||||
|
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||||
|
# CONFIG_MMC_DW_EXYNOS is not set
|
||||||
|
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||||
|
# CONFIG_MMC_DW_K3 is not set
|
||||||
|
# CONFIG_MMC_DW_PCI is not set
|
||||||
|
CONFIG_MMC_DW_PLTFM=y
|
||||||
|
CONFIG_MMC_DW_ROCKCHIP=y
|
||||||
|
CONFIG_MMC_SDHCI=y
|
||||||
|
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||||
|
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||||
|
# CONFIG_MMC_SDHCI_PCI is not set
|
||||||
|
CONFIG_MMC_SDHCI_PLTFM=y
|
||||||
|
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
|
||||||
|
CONFIG_MODULES_USE_ELF_RELA=y
|
||||||
|
CONFIG_MOTORCOMM_PHY=y
|
||||||
|
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||||
|
# CONFIG_MTD_CFI is not set
|
||||||
|
CONFIG_MTD_CMDLINE_PARTS=y
|
||||||
|
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||||
|
CONFIG_MTD_SPI_NOR=y
|
||||||
|
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||||
|
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||||
|
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||||
|
CONFIG_NEED_DMA_MAP_STATE=y
|
||||||
|
CONFIG_NEED_SG_DMA_FLAGS=y
|
||||||
|
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||||
|
CONFIG_NET_EGRESS=y
|
||||||
|
CONFIG_NET_FLOW_LIMIT=y
|
||||||
|
CONFIG_NET_INGRESS=y
|
||||||
|
CONFIG_NET_SELFTESTS=y
|
||||||
|
CONFIG_NET_XGRESS=y
|
||||||
|
CONFIG_NLS=y
|
||||||
|
CONFIG_NLS_ISO8859_1=y
|
||||||
|
CONFIG_NOP_USB_XCEIV=y
|
||||||
|
CONFIG_NO_HZ_COMMON=y
|
||||||
|
CONFIG_NO_HZ_IDLE=y
|
||||||
|
CONFIG_NR_CPUS=256
|
||||||
|
CONFIG_NVMEM=y
|
||||||
|
CONFIG_NVMEM_LAYOUTS=y
|
||||||
|
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
|
||||||
|
CONFIG_NVMEM_ROCKCHIP_OTP=y
|
||||||
|
CONFIG_NVMEM_SYSFS=y
|
||||||
|
CONFIG_NVME_CORE=y
|
||||||
|
# CONFIG_NVME_HWMON is not set
|
||||||
|
# CONFIG_NVME_MULTIPATH is not set
|
||||||
|
CONFIG_OF=y
|
||||||
|
CONFIG_OF_ADDRESS=y
|
||||||
|
CONFIG_OF_DYNAMIC=y
|
||||||
|
CONFIG_OF_EARLY_FLATTREE=y
|
||||||
|
CONFIG_OF_FLATTREE=y
|
||||||
|
CONFIG_OF_GPIO=y
|
||||||
|
CONFIG_OF_IOMMU=y
|
||||||
|
CONFIG_OF_IRQ=y
|
||||||
|
CONFIG_OF_KOBJ=y
|
||||||
|
CONFIG_OF_MDIO=y
|
||||||
|
CONFIG_OF_OVERLAY=y
|
||||||
|
CONFIG_OF_RESOLVE=y
|
||||||
|
CONFIG_OLD_SIGSUSPEND3=y
|
||||||
|
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||||
|
CONFIG_PADATA=y
|
||||||
|
CONFIG_PAGE_POOL=y
|
||||||
|
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
|
||||||
|
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||||
|
# CONFIG_PANIC_ON_OOPS is not set
|
||||||
|
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||||
|
CONFIG_PANIC_TIMEOUT=0
|
||||||
|
# CONFIG_PARTITION_ADVANCED is not set
|
||||||
|
CONFIG_PARTITION_PERCPU=y
|
||||||
|
CONFIG_PCI=y
|
||||||
|
CONFIG_PCIEAER=y
|
||||||
|
CONFIG_PCIEASPM=y
|
||||||
|
CONFIG_PCIEASPM_DEFAULT=y
|
||||||
|
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||||
|
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||||
|
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||||
|
CONFIG_PCIEPORTBUS=y
|
||||||
|
CONFIG_PCIE_DW=y
|
||||||
|
CONFIG_PCIE_DW_HOST=y
|
||||||
|
CONFIG_PCIE_PME=y
|
||||||
|
CONFIG_PCIE_ROCKCHIP=y
|
||||||
|
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
|
||||||
|
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||||
|
CONFIG_PCI_DOMAINS=y
|
||||||
|
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||||
|
CONFIG_PCI_MSI=y
|
||||||
|
CONFIG_PCI_STUB=y
|
||||||
|
CONFIG_PCS_XPCS=y
|
||||||
|
CONFIG_PER_VMA_LOCK=y
|
||||||
|
CONFIG_PGTABLE_LEVELS=4
|
||||||
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHYLIB_LEDS=y
|
||||||
|
CONFIG_PHYLINK=y
|
||||||
|
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||||
|
CONFIG_PHY_ROCKCHIP_DP=y
|
||||||
|
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
|
||||||
|
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||||
|
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
|
||||||
|
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
|
||||||
|
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||||
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||||
|
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
|
||||||
|
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||||
|
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||||
|
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||||
|
CONFIG_PHY_ROCKCHIP_USB=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
CONFIG_PINCTRL_RK805=y
|
||||||
|
CONFIG_PINCTRL_ROCKCHIP=y
|
||||||
|
# CONFIG_PINCTRL_SINGLE is not set
|
||||||
|
CONFIG_PL330_DMA=y
|
||||||
|
CONFIG_PLATFORM_MHU=y
|
||||||
|
CONFIG_PM=y
|
||||||
|
CONFIG_PM_CLK=y
|
||||||
|
CONFIG_PM_DEVFREQ=y
|
||||||
|
CONFIG_PM_DEVFREQ_EVENT=y
|
||||||
|
CONFIG_PM_GENERIC_DOMAINS=y
|
||||||
|
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||||
|
CONFIG_PM_OPP=y
|
||||||
|
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
|
||||||
|
CONFIG_POWER_RESET=y
|
||||||
|
CONFIG_POWER_SUPPLY=y
|
||||||
|
CONFIG_POWER_SUPPLY_HWMON=y
|
||||||
|
CONFIG_PREEMPT=y
|
||||||
|
CONFIG_PREEMPTION=y
|
||||||
|
CONFIG_PREEMPT_BUILD=y
|
||||||
|
CONFIG_PREEMPT_COUNT=y
|
||||||
|
# CONFIG_PREEMPT_NONE is not set
|
||||||
|
CONFIG_PREEMPT_RCU=y
|
||||||
|
CONFIG_PRINTK_TIME=y
|
||||||
|
CONFIG_PROC_PAGE_MONITOR=y
|
||||||
|
CONFIG_PROC_VMCORE=y
|
||||||
|
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||||
|
CONFIG_PWM=y
|
||||||
|
CONFIG_PWM_ROCKCHIP=y
|
||||||
|
CONFIG_PWM_SYSFS=y
|
||||||
|
# CONFIG_QFMT_V2 is not set
|
||||||
|
CONFIG_QUEUED_RWLOCKS=y
|
||||||
|
CONFIG_QUEUED_SPINLOCKS=y
|
||||||
|
CONFIG_QUOTA=y
|
||||||
|
CONFIG_QUOTACTL=y
|
||||||
|
CONFIG_RAID_ATTRS=y
|
||||||
|
CONFIG_RANDOMIZE_BASE=y
|
||||||
|
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
|
||||||
|
CONFIG_RANDSTRUCT_NONE=y
|
||||||
|
CONFIG_RAS=y
|
||||||
|
CONFIG_RATIONAL=y
|
||||||
|
# CONFIG_RAVE_SP_CORE is not set
|
||||||
|
CONFIG_RCU_TRACE=y
|
||||||
|
CONFIG_REALTEK_PHY=y
|
||||||
|
CONFIG_REGMAP=y
|
||||||
|
CONFIG_REGMAP_I2C=y
|
||||||
|
CONFIG_REGMAP_IRQ=y
|
||||||
|
CONFIG_REGMAP_MMIO=y
|
||||||
|
CONFIG_REGMAP_SPI=y
|
||||||
|
CONFIG_REGULATOR=y
|
||||||
|
# CONFIG_REGULATOR_ARM_SCMI is not set
|
||||||
|
CONFIG_REGULATOR_FAN53555=y
|
||||||
|
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||||
|
CONFIG_REGULATOR_GPIO=y
|
||||||
|
CONFIG_REGULATOR_PWM=y
|
||||||
|
CONFIG_REGULATOR_RK808=y
|
||||||
|
CONFIG_RELOCATABLE=y
|
||||||
|
CONFIG_RESET_CONTROLLER=y
|
||||||
|
CONFIG_RESET_SCMI=y
|
||||||
|
CONFIG_RFS_ACCEL=y
|
||||||
|
CONFIG_ROCKCHIP_ERRATUM_3588001=y
|
||||||
|
CONFIG_ROCKCHIP_GRF=y
|
||||||
|
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||||
|
CONFIG_ROCKCHIP_IOMMU=y
|
||||||
|
CONFIG_ROCKCHIP_MBOX=y
|
||||||
|
CONFIG_ROCKCHIP_PHY=y
|
||||||
|
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||||
|
CONFIG_ROCKCHIP_THERMAL=y
|
||||||
|
CONFIG_ROCKCHIP_TIMER=y
|
||||||
|
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||||
|
CONFIG_RPS=y
|
||||||
|
CONFIG_RSEQ=y
|
||||||
|
CONFIG_RTC_CLASS=y
|
||||||
|
CONFIG_RTC_DRV_RK808=y
|
||||||
|
CONFIG_RTC_I2C_AND_SPI=y
|
||||||
|
CONFIG_RTC_NVMEM=y
|
||||||
|
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||||
|
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||||
|
CONFIG_SCHED_MC=y
|
||||||
|
CONFIG_SCSI=y
|
||||||
|
CONFIG_SCSI_COMMON=y
|
||||||
|
# CONFIG_SCSI_LOWLEVEL is not set
|
||||||
|
# CONFIG_SCSI_PROC_FS is not set
|
||||||
|
CONFIG_SCSI_SAS_ATTRS=y
|
||||||
|
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||||
|
CONFIG_SCSI_SAS_LIBSAS=y
|
||||||
|
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||||
|
# CONFIG_SENSORS_ARM_SCMI is not set
|
||||||
|
CONFIG_SENSORS_ARM_SCPI=y
|
||||||
|
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||||
|
CONFIG_SERIAL_8250_DW=y
|
||||||
|
CONFIG_SERIAL_8250_DWLIB=y
|
||||||
|
CONFIG_SERIAL_8250_EXAR=y
|
||||||
|
CONFIG_SERIAL_8250_EXTENDED=y
|
||||||
|
CONFIG_SERIAL_8250_FSL=y
|
||||||
|
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||||
|
CONFIG_SERIAL_8250_PCI=y
|
||||||
|
CONFIG_SERIAL_8250_PCILIB=y
|
||||||
|
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||||
|
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||||
|
CONFIG_SERIAL_AMBA_PL011=y
|
||||||
|
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||||
|
CONFIG_SERIAL_DEV_BUS=y
|
||||||
|
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||||
|
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||||
|
CONFIG_SERIAL_OF_PLATFORM=y
|
||||||
|
CONFIG_SERIO=y
|
||||||
|
CONFIG_SERIO_AMBAKMI=y
|
||||||
|
CONFIG_SERIO_LIBPS2=y
|
||||||
|
CONFIG_SG_POOL=y
|
||||||
|
CONFIG_SLUB_DEBUG=y
|
||||||
|
CONFIG_SMP=y
|
||||||
|
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||||
|
CONFIG_SOFTIRQ_ON_OWN_STACK=y
|
||||||
|
CONFIG_SPARSEMEM=y
|
||||||
|
CONFIG_SPARSEMEM_EXTREME=y
|
||||||
|
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||||
|
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||||
|
CONFIG_SPARSE_IRQ=y
|
||||||
|
CONFIG_SPI=y
|
||||||
|
CONFIG_SPI_BITBANG=y
|
||||||
|
CONFIG_SPI_DYNAMIC=y
|
||||||
|
CONFIG_SPI_MASTER=y
|
||||||
|
CONFIG_SPI_MEM=y
|
||||||
|
CONFIG_SPI_ROCKCHIP=y
|
||||||
|
CONFIG_SPI_ROCKCHIP_SFC=y
|
||||||
|
CONFIG_SPI_SPIDEV=y
|
||||||
|
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
|
||||||
|
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||||
|
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||||
|
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||||
|
CONFIG_SRAM=y
|
||||||
|
CONFIG_STACKDEPOT=y
|
||||||
|
CONFIG_STACKPROTECTOR=y
|
||||||
|
CONFIG_STACKPROTECTOR_PER_TASK=y
|
||||||
|
CONFIG_STACKPROTECTOR_STRONG=y
|
||||||
|
CONFIG_STACKTRACE=y
|
||||||
|
# CONFIG_STAGING is not set
|
||||||
|
CONFIG_STMMAC_ETH=y
|
||||||
|
CONFIG_STMMAC_PLATFORM=y
|
||||||
|
CONFIG_STRICT_DEVMEM=y
|
||||||
|
# CONFIG_STRIP_ASM_SYMS is not set
|
||||||
|
# CONFIG_SWAP is not set
|
||||||
|
CONFIG_SWIOTLB=y
|
||||||
|
CONFIG_SWPHY=y
|
||||||
|
CONFIG_SYNC_FILE=y
|
||||||
|
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||||
|
CONFIG_SYSFS_SYSCALL=y
|
||||||
|
CONFIG_SYSVIPC_COMPAT=y
|
||||||
|
# CONFIG_TEXTSEARCH is not set
|
||||||
|
CONFIG_THERMAL=y
|
||||||
|
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||||
|
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||||
|
CONFIG_THERMAL_EMULATION=y
|
||||||
|
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||||
|
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||||
|
CONFIG_THERMAL_HWMON=y
|
||||||
|
CONFIG_THERMAL_OF=y
|
||||||
|
CONFIG_THREAD_INFO_IN_TASK=y
|
||||||
|
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||||
|
CONFIG_TIMER_OF=y
|
||||||
|
CONFIG_TIMER_PROBE=y
|
||||||
|
CONFIG_TRACE_CLOCK=y
|
||||||
|
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
|
||||||
|
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||||
|
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||||
|
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||||
|
CONFIG_TRANS_TABLE=y
|
||||||
|
CONFIG_TREE_RCU=y
|
||||||
|
CONFIG_TREE_SRCU=y
|
||||||
|
CONFIG_TYPEC=y
|
||||||
|
# CONFIG_TYPEC_ANX7411 is not set
|
||||||
|
CONFIG_TYPEC_FUSB302=y
|
||||||
|
# CONFIG_TYPEC_HD3SS3220 is not set
|
||||||
|
# CONFIG_TYPEC_MUX_FSA4480 is not set
|
||||||
|
# CONFIG_TYPEC_MUX_GPIO_SBU is not set
|
||||||
|
# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
|
||||||
|
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||||
|
# CONFIG_TYPEC_RT1719 is not set
|
||||||
|
# CONFIG_TYPEC_STUSB160X is not set
|
||||||
|
# CONFIG_TYPEC_TCPCI is not set
|
||||||
|
CONFIG_TYPEC_TCPM=y
|
||||||
|
# CONFIG_TYPEC_TPS6598X is not set
|
||||||
|
# CONFIG_TYPEC_WUSB3801 is not set
|
||||||
|
# CONFIG_UACCE is not set
|
||||||
|
# CONFIG_UCLAMP_TASK is not set
|
||||||
|
# CONFIG_UEVENT_HELPER is not set
|
||||||
|
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||||
|
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_USB_COMMON=y
|
||||||
|
CONFIG_USB_DWC3=y
|
||||||
|
CONFIG_USB_DWC3_HOST=y
|
||||||
|
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||||
|
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||||
|
CONFIG_USB_HID=y
|
||||||
|
CONFIG_USB_OHCI_HCD=y
|
||||||
|
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||||
|
CONFIG_USB_PHY=y
|
||||||
|
CONFIG_USB_ROLE_SWITCH=y
|
||||||
|
CONFIG_USB_STORAGE=y
|
||||||
|
CONFIG_USB_SUPPORT=y
|
||||||
|
CONFIG_USB_ULPI=y
|
||||||
|
CONFIG_USB_ULPI_BUS=y
|
||||||
|
CONFIG_USB_ULPI_VIEWPORT=y
|
||||||
|
CONFIG_USB_XHCI_HCD=y
|
||||||
|
CONFIG_USB_XHCI_PLATFORM=y
|
||||||
|
# CONFIG_VIRTIO_MENU is not set
|
||||||
|
CONFIG_VMAP_STACK=y
|
||||||
|
CONFIG_VM_EVENT_COUNTERS=y
|
||||||
|
CONFIG_VT=y
|
||||||
|
CONFIG_VT_CONSOLE=y
|
||||||
|
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||||
|
CONFIG_WATCHDOG_CORE=y
|
||||||
|
CONFIG_XARRAY_MULTI=y
|
||||||
|
CONFIG_XPS=y
|
||||||
|
CONFIG_XXHASH=y
|
||||||
|
CONFIG_XZ_DEC_ARM=y
|
||||||
|
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||||
|
CONFIG_XZ_DEC_BCJ=y
|
||||||
|
CONFIG_ZLIB_DEFLATE=y
|
||||||
|
CONFIG_ZLIB_INFLATE=y
|
||||||
|
CONFIG_ZONE_DMA32=y
|
||||||
@ -73,7 +73,7 @@ define Device/Default
|
|||||||
DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))
|
DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))
|
||||||
endef
|
endef
|
||||||
|
|
||||||
ifdef CONFIG_LINUX_6_1
|
ifndef CONFIG_LINUX_5_15
|
||||||
DTS_CPPFLAGS += -DDTS_NO_LEGACY
|
DTS_CPPFLAGS += -DDTS_NO_LEGACY
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
|||||||
@ -0,0 +1,31 @@
|
|||||||
|
From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001
|
||||||
|
From: Tianling Shen <cnsztl@gmail.com>
|
||||||
|
Date: Mon, 7 Jun 2021 15:45:37 +0800
|
||||||
|
Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
|
||||||
|
|
||||||
|
NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
|
||||||
|
stores the MAC address.
|
||||||
|
|
||||||
|
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++
|
||||||
|
1 file changed, 9 insertions(+)
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||||
|
@@ -68,6 +68,15 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+&i2c2 {
|
||||||
|
+ eeprom@51 {
|
||||||
|
+ compatible = "microchip,24c02", "atmel,24c02";
|
||||||
|
+ reg = <0x51>;
|
||||||
|
+ pagesize = <16>;
|
||||||
|
+ read-only; /* This holds our MAC */
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&i2c4 {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
@ -0,0 +1,58 @@
|
|||||||
|
From edcc2833819f6750bf003b95a6ac856aced26274 Mon Sep 17 00:00:00 2001
|
||||||
|
From: AnYun <amadeus@jmu.edu.cn>
|
||||||
|
Date: Sat, 18 Mar 2023 23:05:16 +0800
|
||||||
|
Subject: [PATCH] r8169: add LED configuration from OF
|
||||||
|
|
||||||
|
---
|
||||||
|
drivers/net/ethernet/realtek/r8169_main.c | 19 +++++++++++++++++++
|
||||||
|
1 file changed, 19 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/net/ethernet/realtek/r8169_main.c
|
||||||
|
+++ b/drivers/net/ethernet/realtek/r8169_main.c
|
||||||
|
@@ -17,6 +17,7 @@
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <linux/ethtool.h>
|
||||||
|
#include <linux/phy.h>
|
||||||
|
+#include <linux/of.h>
|
||||||
|
#include <linux/if_vlan.h>
|
||||||
|
#include <linux/in.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
@@ -174,6 +175,7 @@ enum rtl_registers {
|
||||||
|
MAR0 = 8, /* Multicast filter. */
|
||||||
|
CounterAddrLow = 0x10,
|
||||||
|
CounterAddrHigh = 0x14,
|
||||||
|
+ CustomLED = 0x18,
|
||||||
|
TxDescStartAddrLow = 0x20,
|
||||||
|
TxDescStartAddrHigh = 0x24,
|
||||||
|
TxHDescStartAddrLow = 0x28,
|
||||||
|
@@ -5202,6 +5204,22 @@ static bool rtl_aspm_is_safe(struct rtl8
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int rtl_led_configuration(struct rtl8169_private *tp)
|
||||||
|
+{
|
||||||
|
+ u32 led_data;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ ret = of_property_read_u32(tp->pci_dev->dev.of_node,
|
||||||
|
+ "realtek,led-data", &led_data);
|
||||||
|
+
|
||||||
|
+ if (ret)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ RTL_W16(tp, CustomLED, led_data);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||||
|
{
|
||||||
|
struct rtl8169_private *tp;
|
||||||
|
@@ -5373,6 +5391,7 @@ static int rtl_init_one(struct pci_dev *
|
||||||
|
if (!tp->counters)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
+ rtl_led_configuration(tp);
|
||||||
|
pci_set_drvdata(pdev, tp);
|
||||||
|
|
||||||
|
rc = r8169_mdio_register(tp);
|
||||||
@ -0,0 +1,44 @@
|
|||||||
|
From edcc2833819f6750bf003b95a6ac856aced26276 Mon Sep 17 00:00:00 2001
|
||||||
|
From: AnYun <amadeus@jmu.edu.cn>
|
||||||
|
Date: Mon, 3 Apr 2023 23:26:04 +0800
|
||||||
|
Subject: [PATCH] net: phy: realtek: add LED configuration from OF for 8211f
|
||||||
|
|
||||||
|
---
|
||||||
|
drivers/net/phy/realtek.c | 9 +++++++++
|
||||||
|
1 file changed, 9 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/net/phy/realtek.c
|
||||||
|
+++ b/drivers/net/phy/realtek.c
|
||||||
|
@@ -28,6 +28,8 @@
|
||||||
|
#define RTL821x_EXT_PAGE_SELECT 0x1e
|
||||||
|
#define RTL821x_PAGE_SELECT 0x1f
|
||||||
|
|
||||||
|
+#define RTL8211F_LCR 0x10
|
||||||
|
+#define RTL8211F_EEELCR 0x11
|
||||||
|
#define RTL8211F_PHYCR1 0x18
|
||||||
|
#define RTL8211F_PHYCR2 0x19
|
||||||
|
#define RTL8211F_INSR 0x1d
|
||||||
|
@@ -357,6 +359,7 @@ static int rtl8211f_config_init(struct p
|
||||||
|
struct rtl821x_priv *priv = phydev->priv;
|
||||||
|
struct device *dev = &phydev->mdio.dev;
|
||||||
|
u16 val_txdly, val_rxdly;
|
||||||
|
+ u32 led_data;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
|
||||||
|
@@ -423,6 +426,15 @@ static int rtl8211f_config_init(struct p
|
||||||
|
val_rxdly ? "enabled" : "disabled");
|
||||||
|
}
|
||||||
|
|
||||||
|
+ ret = of_property_read_u32(dev->of_node,
|
||||||
|
+ "realtek,led-data", &led_data);
|
||||||
|
+ if (!ret) {
|
||||||
|
+ phy_write(phydev, RTL821x_PAGE_SELECT, 0xd04);
|
||||||
|
+ phy_write(phydev, RTL8211F_LCR, led_data);
|
||||||
|
+ phy_write(phydev, RTL8211F_EEELCR, 0x0);
|
||||||
|
+ phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (priv->has_phycr2) {
|
||||||
|
ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
|
||||||
|
RTL8211F_CLKOUT_EN, priv->phycr2);
|
||||||
@ -0,0 +1,24 @@
|
|||||||
|
From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
|
||||||
|
From: David Bauer <mail@david-bauer.net>
|
||||||
|
Date: Sun, 26 Jul 2020 13:32:59 +0200
|
||||||
|
Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
|
||||||
|
|
||||||
|
This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
|
||||||
|
NanoPi R2S. Add the correct value for the RTL8153 LED configuration
|
||||||
|
register to match the blink behavior of the other port on the device.
|
||||||
|
|
||||||
|
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
|
||||||
|
1 file changed, 1 insertions(+)
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||||
|
@@ -397,6 +397,7 @@
|
||||||
|
rtl8153: device@2 {
|
||||||
|
compatible = "usbbda,8153";
|
||||||
|
reg = <2>;
|
||||||
|
+ realtek,led-data = <0x87>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
@ -0,0 +1,26 @@
|
|||||||
|
From: David Bauer <mail@david-bauer.net>
|
||||||
|
Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S
|
||||||
|
|
||||||
|
The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting
|
||||||
|
while U-Boot requires the card to be in 3.3V mode.
|
||||||
|
|
||||||
|
Remove UHS support from the SD controller so the card remains in 3.3V
|
||||||
|
mode. This reduces transfer speeds but ensures a reboot whether from
|
||||||
|
userspace or following a kernel panic is always working.
|
||||||
|
|
||||||
|
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||||
|
@@ -121,6 +121,11 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+&sdmmc {
|
||||||
|
+ /delete-property/ sd-uhs-sdr104;
|
||||||
|
+ cap-sd-highspeed;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&u2phy0_host {
|
||||||
|
phy-supply = <&vdd_5v>;
|
||||||
|
};
|
||||||
@ -0,0 +1,35 @@
|
|||||||
|
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||||
|
@@ -38,6 +38,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gr
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-dumo.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-guangmiao-g4c.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4se.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb
|
||||||
|
@@ -59,6 +61,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4c-plus.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4se.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
|
||||||
|
@@ -0,0 +1,13 @@
|
||||||
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||||
|
+/*
|
||||||
|
+ * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
|
||||||
|
+ * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+/dts-v1/;
|
||||||
|
+#include "rk3399-rock-pi-4.dtsi"
|
||||||
|
+
|
||||||
|
+/ {
|
||||||
|
+ model = "Radxa ROCK Pi 4";
|
||||||
|
+ compatible = "radxa,rockpi4", "rockchip,rk3399";
|
||||||
|
+};
|
||||||
@ -0,0 +1,35 @@
|
|||||||
|
From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jonas Karlman <jonas@kwiboo.se>
|
||||||
|
Date: Wed, 20 Feb 2019 07:38:34 +0000
|
||||||
|
Subject: [PATCH] mmc: core: set initial signal voltage on power off
|
||||||
|
|
||||||
|
Some boards have SD card connectors where the power rail cannot be switched
|
||||||
|
off by the driver. If the card has not been power cycled, it may still be
|
||||||
|
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
|
||||||
|
will fail to boot from a UHS card that continue to use 1.8V signaling.
|
||||||
|
|
||||||
|
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
|
||||||
|
|
||||||
|
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
|
||||||
|
same issue have been seen on some Rockchip RK3399 boards.
|
||||||
|
|
||||||
|
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
|
||||||
|
this change fix a re-boot issue on my boards and does not break emmc/sdio.
|
||||||
|
Is this an acceptable workaround? Any advice is appreciated.
|
||||||
|
|
||||||
|
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||||
|
---
|
||||||
|
drivers/mmc/core/core.c | 2 ++
|
||||||
|
1 file changed, 2 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/mmc/core/core.c
|
||||||
|
+++ b/drivers/mmc/core/core.c
|
||||||
|
@@ -1370,6 +1370,8 @@ void mmc_power_off(struct mmc_host *host
|
||||||
|
|
||||||
|
mmc_pwrseq_power_off(host);
|
||||||
|
|
||||||
|
+ mmc_set_initial_signal_voltage(host);
|
||||||
|
+
|
||||||
|
host->ios.clock = 0;
|
||||||
|
host->ios.vdd = 0;
|
||||||
|
|
||||||
@ -0,0 +1,77 @@
|
|||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||||
|
@@ -64,7 +64,7 @@
|
||||||
|
compatible = "rockchip,rk3568-pcie";
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
- bus-range = <0x0 0xf>;
|
||||||
|
+ bus-range = <0x10 0x1f>;
|
||||||
|
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
||||||
|
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
||||||
|
<&cru CLK_PCIE30X1_AUX_NDFT>;
|
||||||
|
@@ -87,7 +87,7 @@
|
||||||
|
num-ib-windows = <6>;
|
||||||
|
num-ob-windows = <2>;
|
||||||
|
max-link-speed = <3>;
|
||||||
|
- msi-map = <0x0 &gic 0x1000 0x1000>;
|
||||||
|
+ msi-map = <0x1000 &its 0x1000 0x1000>;
|
||||||
|
num-lanes = <1>;
|
||||||
|
phys = <&pcie30phy>;
|
||||||
|
phy-names = "pcie-phy";
|
||||||
|
@@ -117,7 +117,7 @@
|
||||||
|
compatible = "rockchip,rk3568-pcie";
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
- bus-range = <0x0 0xf>;
|
||||||
|
+ bus-range = <0x20 0x2f>;
|
||||||
|
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
||||||
|
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
||||||
|
<&cru CLK_PCIE30X2_AUX_NDFT>;
|
||||||
|
@@ -140,7 +140,7 @@
|
||||||
|
num-ib-windows = <6>;
|
||||||
|
num-ob-windows = <2>;
|
||||||
|
max-link-speed = <3>;
|
||||||
|
- msi-map = <0x0 &gic 0x2000 0x1000>;
|
||||||
|
+ msi-map = <0x2000 &its 0x2000 0x1000>;
|
||||||
|
num-lanes = <2>;
|
||||||
|
phys = <&pcie30phy>;
|
||||||
|
phy-names = "pcie-phy";
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||||
|
@@ -315,14 +315,21 @@
|
||||||
|
|
||||||
|
gic: interrupt-controller@fd400000 {
|
||||||
|
compatible = "arm,gic-v3";
|
||||||
|
+ #interrupt-cells = <3>;
|
||||||
|
+ #address-cells = <2>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ ranges;
|
||||||
|
+ interrupt-controller;
|
||||||
|
+
|
||||||
|
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
||||||
|
- <0x0 0xfd460000 0 0x80000>; /* GICR */
|
||||||
|
+ <0x0 0xfd460000 0 0xc0000>; /* GICR */
|
||||||
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
- interrupt-controller;
|
||||||
|
- #interrupt-cells = <3>;
|
||||||
|
- mbi-alias = <0x0 0xfd410000>;
|
||||||
|
- mbi-ranges = <296 24>;
|
||||||
|
- msi-controller;
|
||||||
|
+ its: interrupt-controller@fd440000 {
|
||||||
|
+ compatible = "arm,gic-v3-its";
|
||||||
|
+ msi-controller;
|
||||||
|
+ #msi-cells = <1>;
|
||||||
|
+ reg = <0x0 0xfd440000 0x0 0x20000>;
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
usb_host0_ehci: usb@fd800000 {
|
||||||
|
@@ -988,7 +995,7 @@
|
||||||
|
num-ib-windows = <6>;
|
||||||
|
num-ob-windows = <2>;
|
||||||
|
max-link-speed = <2>;
|
||||||
|
- msi-map = <0x0 &gic 0x0 0x1000>;
|
||||||
|
+ msi-map = <0x0 &its 0x0 0x1000>;
|
||||||
|
num-lanes = <1>;
|
||||||
|
phys = <&combphy2 PHY_TYPE_PCIE>;
|
||||||
|
phy-names = "pcie-phy";
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
--- a/drivers/irqchip/irq-gic-v3-its.c
|
||||||
|
+++ b/drivers/irqchip/irq-gic-v3-its.c
|
||||||
|
@@ -4757,11 +4757,13 @@ static bool __maybe_unused its_enable_qu
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static bool __maybe_unused its_enable_rk3588001(void *data)
|
||||||
|
+static bool __maybe_unused its_enable_rk35xx(void *data)
|
||||||
|
{
|
||||||
|
struct its_node *its = data;
|
||||||
|
|
||||||
|
- if (!of_machine_is_compatible("rockchip,rk3588") &&
|
||||||
|
+ if (!of_machine_is_compatible("rockchip,rk3566") &&
|
||||||
|
+ !of_machine_is_compatible("rockchip,rk3568") &&
|
||||||
|
+ !of_machine_is_compatible("rockchip,rk3588") &&
|
||||||
|
!of_machine_is_compatible("rockchip,rk3588s"))
|
||||||
|
return false;
|
||||||
|
|
||||||
|
@@ -4827,10 +4829,10 @@ static const struct gic_quirk its_quirks
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_ROCKCHIP_ERRATUM_3588001
|
||||||
|
{
|
||||||
|
- .desc = "ITS: Rockchip erratum RK3588001",
|
||||||
|
+ .desc = "ITS: Rockchip erratum RK35XX",
|
||||||
|
.iidr = 0x0201743b,
|
||||||
|
.mask = 0xffffffff,
|
||||||
|
- .init = its_enable_rk3588001,
|
||||||
|
+ .init = its_enable_rk35xx,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
{
|
||||||
@ -0,0 +1,33 @@
|
|||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||||
|
@@ -175,11 +175,13 @@
|
||||||
|
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||||
|
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||||
|
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||||
|
- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
|
||||||
|
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
||||||
|
+ <&cru PCLK_XPCS>;
|
||||||
|
clock-names = "stmmaceth", "mac_clk_rx",
|
||||||
|
"mac_clk_tx", "clk_mac_refout",
|
||||||
|
"aclk_mac", "pclk_mac",
|
||||||
|
- "clk_mac_speed", "ptp_ref";
|
||||||
|
+ "clk_mac_speed", "ptp_ref",
|
||||||
|
+ "pclk_xpcs";
|
||||||
|
resets = <&cru SRST_A_GMAC0>;
|
||||||
|
reset-names = "stmmaceth";
|
||||||
|
rockchip,grf = <&grf>;
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||||
|
@@ -376,6 +376,12 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+ xpcs: syscon@fda00000 {
|
||||||
|
+ compatible = "rockchip,rk3568-xpcs", "syscon";
|
||||||
|
+ reg = <0x0 0xfda00000 0x0 0x200000>;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
pmugrf: syscon@fdc20000 {
|
||||||
|
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
||||||
|
reg = <0x0 0xfdc20000 0x0 0x10000>;
|
||||||
@ -0,0 +1,320 @@
|
|||||||
|
From ca89ea7e0760c096c6fd807d321ecb8416f8cd9d Mon Sep 17 00:00:00 2001
|
||||||
|
From: David Wu <david.wu@rock-chips.com>
|
||||||
|
Date: Thu, 31 Dec 2020 18:32:03 +0800
|
||||||
|
Subject: [PATCH] ethernet: stmicro: stmmac: Add SGMII/QSGMII support for
|
||||||
|
RK3568
|
||||||
|
|
||||||
|
After the completion of Clause 37 auto-negotiation, xpcs automatically
|
||||||
|
switches to the negotiated speed for 10/100/1000M.
|
||||||
|
|
||||||
|
Change-Id: Iab9dd6ee61a35bf89fd3a0721f5d398de501a7ec
|
||||||
|
Signed-off-by: David Wu <david.wu@rock-chips.com>
|
||||||
|
---
|
||||||
|
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 228 +++++++++++++++++-
|
||||||
|
1 file changed, 217 insertions(+), 11 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
|
||||||
|
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
|
||||||
|
@@ -11,6 +11,7 @@
|
||||||
|
#include <linux/bitops.h>
|
||||||
|
#include <linux/clk.h>
|
||||||
|
#include <linux/phy.h>
|
||||||
|
+#include <linux/phy/phy.h>
|
||||||
|
#include <linux/of_net.h>
|
||||||
|
#include <linux/gpio.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
@@ -30,6 +31,8 @@ struct rk_gmac_ops {
|
||||||
|
void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
|
||||||
|
int tx_delay, int rx_delay);
|
||||||
|
void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
|
||||||
|
+ void (*set_to_sgmii)(struct rk_priv_data *bsp_priv);
|
||||||
|
+ void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv);
|
||||||
|
void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
|
||||||
|
void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
|
||||||
|
void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
|
||||||
|
@@ -40,7 +43,7 @@ struct rk_gmac_ops {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const rk_clocks[] = {
|
||||||
|
- "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
|
||||||
|
+ "aclk_mac", "pclk_mac", "pclk_xpcs", "mac_clk_tx", "clk_mac_speed",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const rk_rmii_clocks[] = {
|
||||||
|
@@ -50,6 +53,7 @@ static const char * const rk_rmii_clocks
|
||||||
|
enum rk_clocks_index {
|
||||||
|
RK_ACLK_MAC = 0,
|
||||||
|
RK_PCLK_MAC,
|
||||||
|
+ RK_PCLK_XPCS,
|
||||||
|
RK_MAC_CLK_TX,
|
||||||
|
RK_CLK_MAC_SPEED,
|
||||||
|
RK_MAC_CLK_RX,
|
||||||
|
@@ -81,6 +85,7 @@ struct rk_priv_data {
|
||||||
|
|
||||||
|
struct regmap *grf;
|
||||||
|
struct regmap *php_grf;
|
||||||
|
+ struct regmap *xpcs;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define HIWORD_UPDATE(val, mask, shift) \
|
||||||
|
@@ -93,6 +98,128 @@ struct rk_priv_data {
|
||||||
|
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
|
||||||
|
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
|
||||||
|
|
||||||
|
+/* XPCS */
|
||||||
|
+#define XPCS_APB_INCREMENT (0x4)
|
||||||
|
+#define XPCS_APB_MASK GENMASK_ULL(20, 0)
|
||||||
|
+
|
||||||
|
+#define SR_MII_BASE (0x1F0000)
|
||||||
|
+#define SR_MII1_BASE (0x1A0000)
|
||||||
|
+
|
||||||
|
+#define VR_MII_DIG_CTRL1 (0x8000)
|
||||||
|
+#define VR_MII_AN_CTRL (0x8001)
|
||||||
|
+#define VR_MII_AN_INTR_STS (0x8002)
|
||||||
|
+#define VR_MII_LINK_TIMER_CTRL (0x800A)
|
||||||
|
+
|
||||||
|
+#define SR_MII_CTRL_AN_ENABLE \
|
||||||
|
+ (BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000)
|
||||||
|
+#define MII_MAC_AUTO_SW (0x0200)
|
||||||
|
+#define PCS_MODE_OFFSET (0x1)
|
||||||
|
+#define MII_AN_INTR_EN (0x1)
|
||||||
|
+#define PCS_SGMII_MODE (0x2 << PCS_MODE_OFFSET)
|
||||||
|
+#define PCS_QSGMII_MODE (0X3 << PCS_MODE_OFFSET)
|
||||||
|
+#define VR_MII_CTRL_SGMII_AN_EN (PCS_SGMII_MODE | MII_AN_INTR_EN)
|
||||||
|
+#define VR_MII_CTRL_QSGMII_AN_EN (PCS_QSGMII_MODE | MII_AN_INTR_EN)
|
||||||
|
+
|
||||||
|
+#define SR_MII_OFFSET(_x) ({ \
|
||||||
|
+ typeof(_x) (x) = (_x); \
|
||||||
|
+ (((x) == 0) ? SR_MII_BASE : (SR_MII1_BASE + ((x) - 1) * 0x10000)); \
|
||||||
|
+}) \
|
||||||
|
+
|
||||||
|
+static int xpcs_read(void *priv, int reg)
|
||||||
|
+{
|
||||||
|
+ struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv;
|
||||||
|
+ int ret, val;
|
||||||
|
+
|
||||||
|
+ ret = regmap_read(bsp_priv->xpcs,
|
||||||
|
+ (u32)(reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK,
|
||||||
|
+ &val);
|
||||||
|
+ if (ret)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ return val;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int xpcs_write(void *priv, int reg, u16 value)
|
||||||
|
+{
|
||||||
|
+ struct rk_priv_data *bsp_priv = (struct rk_priv_data *)priv;
|
||||||
|
+
|
||||||
|
+ return regmap_write(bsp_priv->xpcs,
|
||||||
|
+ (reg * XPCS_APB_INCREMENT) & XPCS_APB_MASK, value);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int xpcs_poll_reset(struct rk_priv_data *bsp_priv, int dev)
|
||||||
|
+{
|
||||||
|
+ /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
|
||||||
|
+ unsigned int retries = 12;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ do {
|
||||||
|
+ msleep(50);
|
||||||
|
+ ret = xpcs_read(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+ } while (ret & MDIO_CTRL1_RESET && --retries);
|
||||||
|
+
|
||||||
|
+ return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int xpcs_soft_reset(struct rk_priv_data *bsp_priv, int dev)
|
||||||
|
+{
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ ret = xpcs_write(bsp_priv, SR_MII_OFFSET(dev) + MDIO_CTRL1,
|
||||||
|
+ MDIO_CTRL1_RESET);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ return xpcs_poll_reset(bsp_priv, dev);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int xpcs_setup(struct rk_priv_data *bsp_priv, int mode)
|
||||||
|
+{
|
||||||
|
+ int ret, i, idx = bsp_priv->id;
|
||||||
|
+ u32 val;
|
||||||
|
+
|
||||||
|
+ if (mode == PHY_INTERFACE_MODE_QSGMII && idx > 0)
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+ ret = xpcs_soft_reset(bsp_priv, idx);
|
||||||
|
+ if (ret) {
|
||||||
|
+ dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret);
|
||||||
|
+ return ret;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_INTR_STS, 0x0);
|
||||||
|
+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_LINK_TIMER_CTRL, 0x1);
|
||||||
|
+
|
||||||
|
+ if (mode == PHY_INTERFACE_MODE_SGMII)
|
||||||
|
+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL,
|
||||||
|
+ VR_MII_CTRL_SGMII_AN_EN);
|
||||||
|
+ else
|
||||||
|
+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL,
|
||||||
|
+ VR_MII_CTRL_QSGMII_AN_EN);
|
||||||
|
+
|
||||||
|
+ if (mode == PHY_INTERFACE_MODE_QSGMII) {
|
||||||
|
+ for (i = 0; i < 4; i++) {
|
||||||
|
+ val = xpcs_read(bsp_priv,
|
||||||
|
+ SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1);
|
||||||
|
+ xpcs_write(bsp_priv,
|
||||||
|
+ SR_MII_OFFSET(i) + VR_MII_DIG_CTRL1,
|
||||||
|
+ val | MII_MAC_AUTO_SW);
|
||||||
|
+ xpcs_write(bsp_priv, SR_MII_OFFSET(i) + MII_BMCR,
|
||||||
|
+ SR_MII_CTRL_AN_ENABLE);
|
||||||
|
+ }
|
||||||
|
+ } else {
|
||||||
|
+ val = xpcs_read(bsp_priv, SR_MII_OFFSET(idx) + VR_MII_DIG_CTRL1);
|
||||||
|
+ xpcs_write(bsp_priv, SR_MII_OFFSET(idx) + VR_MII_DIG_CTRL1,
|
||||||
|
+ val | MII_MAC_AUTO_SW);
|
||||||
|
+ xpcs_write(bsp_priv, SR_MII_OFFSET(idx) + MII_BMCR,
|
||||||
|
+ SR_MII_CTRL_AN_ENABLE);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
#define PX30_GRF_GMAC_CON1 0x0904
|
||||||
|
|
||||||
|
/* PX30_GRF_GMAC_CON1 */
|
||||||
|
@@ -1021,6 +1148,7 @@ static const struct rk_gmac_ops rk3399_o
|
||||||
|
#define RK3568_GRF_GMAC1_CON1 0x038c
|
||||||
|
|
||||||
|
/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
|
||||||
|
+#define RK3568_GMAC_GMII_MODE GRF_BIT(7)
|
||||||
|
#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
|
||||||
|
(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
|
||||||
|
#define RK3568_GMAC_PHY_INTF_SEL_RMII \
|
||||||
|
@@ -1036,6 +1164,46 @@ static const struct rk_gmac_ops rk3399_o
|
||||||
|
#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
|
||||||
|
#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
|
||||||
|
|
||||||
|
+#define RK3568_PIPE_GRF_XPCS_CON0 0X0040
|
||||||
|
+
|
||||||
|
+#define RK3568_PIPE_GRF_XPCS_QGMII_MAC_SEL GRF_BIT(0)
|
||||||
|
+#define RK3568_PIPE_GRF_XPCS_SGMII_MAC_SEL GRF_BIT(1)
|
||||||
|
+#define RK3568_PIPE_GRF_XPCS_PHY_READY GRF_BIT(2)
|
||||||
|
+
|
||||||
|
+static void rk3568_set_to_sgmii(struct rk_priv_data *bsp_priv)
|
||||||
|
+{
|
||||||
|
+ struct device *dev = &bsp_priv->pdev->dev;
|
||||||
|
+ u32 con1;
|
||||||
|
+
|
||||||
|
+ if (IS_ERR(bsp_priv->grf)) {
|
||||||
|
+ dev_err(dev, "Missing rockchip,grf property\n");
|
||||||
|
+ return;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
|
||||||
|
+ RK3568_GRF_GMAC0_CON1;
|
||||||
|
+ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_GMII_MODE);
|
||||||
|
+
|
||||||
|
+ xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_SGMII);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void rk3568_set_to_qsgmii(struct rk_priv_data *bsp_priv)
|
||||||
|
+{
|
||||||
|
+ struct device *dev = &bsp_priv->pdev->dev;
|
||||||
|
+ u32 con1;
|
||||||
|
+
|
||||||
|
+ if (IS_ERR(bsp_priv->grf)) {
|
||||||
|
+ dev_err(dev, "Missing rockchip,grf property\n");
|
||||||
|
+ return;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
|
||||||
|
+ RK3568_GRF_GMAC0_CON1;
|
||||||
|
+ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_GMII_MODE);
|
||||||
|
+
|
||||||
|
+ xpcs_setup(bsp_priv, PHY_INTERFACE_MODE_QSGMII);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
|
||||||
|
int tx_delay, int rx_delay)
|
||||||
|
{
|
||||||
|
@@ -1108,6 +1276,8 @@ static void rk3568_set_gmac_speed(struct
|
||||||
|
static const struct rk_gmac_ops rk3568_ops = {
|
||||||
|
.set_to_rgmii = rk3568_set_to_rgmii,
|
||||||
|
.set_to_rmii = rk3568_set_to_rmii,
|
||||||
|
+ .set_to_sgmii = rk3568_set_to_sgmii,
|
||||||
|
+ .set_to_qsgmii = rk3568_set_to_qsgmii,
|
||||||
|
.set_rgmii_speed = rk3568_set_gmac_speed,
|
||||||
|
.set_rmii_speed = rk3568_set_gmac_speed,
|
||||||
|
.regs_valid = true,
|
||||||
|
@@ -1580,7 +1750,7 @@ static int gmac_clk_enable(struct rk_pri
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
|
||||||
|
+static int rk_gmac_phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
|
||||||
|
{
|
||||||
|
struct regulator *ldo = bsp_priv->regulator;
|
||||||
|
int ret;
|
||||||
|
@@ -1679,6 +1849,18 @@ static struct rk_priv_data *rk_gmac_setu
|
||||||
|
"rockchip,grf");
|
||||||
|
bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||||
|
"rockchip,php-grf");
|
||||||
|
+ bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||||
|
+ "rockchip,xpcs");
|
||||||
|
+ if (!IS_ERR(bsp_priv->xpcs)) {
|
||||||
|
+ struct phy *comphy;
|
||||||
|
+
|
||||||
|
+ comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
|
||||||
|
+ if (IS_ERR(comphy))
|
||||||
|
+ dev_err(dev, "devm_of_phy_get error\n");
|
||||||
|
+ ret = phy_init(comphy);
|
||||||
|
+ if (ret)
|
||||||
|
+ dev_err(dev, "phy_init error\n");
|
||||||
|
+ }
|
||||||
|
|
||||||
|
if (plat->phy_node) {
|
||||||
|
bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
|
||||||
|
@@ -1756,11 +1938,19 @@ static int rk_gmac_powerup(struct rk_pri
|
||||||
|
dev_info(dev, "init for RMII\n");
|
||||||
|
bsp_priv->ops->set_to_rmii(bsp_priv);
|
||||||
|
break;
|
||||||
|
+ case PHY_INTERFACE_MODE_SGMII:
|
||||||
|
+ dev_info(dev, "init for SGMII\n");
|
||||||
|
+ bsp_priv->ops->set_to_sgmii(bsp_priv);
|
||||||
|
+ break;
|
||||||
|
+ case PHY_INTERFACE_MODE_QSGMII:
|
||||||
|
+ dev_info(dev, "init for QSGMII\n");
|
||||||
|
+ bsp_priv->ops->set_to_qsgmii(bsp_priv);
|
||||||
|
+ break;
|
||||||
|
default:
|
||||||
|
dev_err(dev, "NO interface defined!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
- ret = phy_power_on(bsp_priv, true);
|
||||||
|
+ ret = rk_gmac_phy_power_on(bsp_priv, true);
|
||||||
|
if (ret) {
|
||||||
|
gmac_clk_enable(bsp_priv, false);
|
||||||
|
return ret;
|
||||||
|
@@ -1781,7 +1971,7 @@ static void rk_gmac_powerdown(struct rk_
|
||||||
|
|
||||||
|
pm_runtime_put_sync(&gmac->pdev->dev);
|
||||||
|
|
||||||
|
- phy_power_on(gmac, false);
|
||||||
|
+ rk_gmac_phy_power_on(gmac, false);
|
||||||
|
gmac_clk_enable(gmac, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -1802,6 +1992,9 @@ static void rk_fix_speed(void *priv, uns
|
||||||
|
if (bsp_priv->ops->set_rmii_speed)
|
||||||
|
bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
|
||||||
|
break;
|
||||||
|
+ case PHY_INTERFACE_MODE_SGMII:
|
||||||
|
+ case PHY_INTERFACE_MODE_QSGMII:
|
||||||
|
+ break;
|
||||||
|
default:
|
||||||
|
dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
|
||||||
|
}
|
||||||
@ -0,0 +1,22 @@
|
|||||||
|
From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001
|
||||||
|
From: QiuSimons <45143996+QiuSimons@users.noreply.github.com>
|
||||||
|
Date: Tue, 4 Aug 2020 20:17:53 +0800
|
||||||
|
Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s
|
||||||
|
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++
|
||||||
|
1 files changed, 4 insertions(+)
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||||
|
@@ -166,6 +166,10 @@
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
+&i2c0 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&i2c1 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
@ -0,0 +1,442 @@
|
|||||||
|
From 0f989817a4c1d2c3d196d550ff05cda98bc91324 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Julian Pidancet <julian@pidancet.net>
|
||||||
|
Date: Sun, 23 Jan 2022 16:34:08 +0100
|
||||||
|
Subject: [PATCH v2] rockchip: rk3328: add support for FriendlyARM NanoPi NEO3
|
||||||
|
|
||||||
|
This patch adds support for FriendlyARM NanoPi NEO3
|
||||||
|
|
||||||
|
Soc: RockChip RK3328
|
||||||
|
RAM: 1GB/2GB DDR4
|
||||||
|
LAN: 10/100/1000M Ethernet with unique MAC
|
||||||
|
USB Host: 1x USB3.0 Type A and 2x USB2.0 on 2.54mm pin header
|
||||||
|
MicroSD: x 1 for system boot and storage
|
||||||
|
LED: Power LED x 1, System LED x 1
|
||||||
|
Key: User Button x 1
|
||||||
|
Fan: 2 Pin JST ZH 1.5mm Connector for 5V Fan
|
||||||
|
GPIO: 26 pin-header, include I2C, UART, SPI, I2S, GPIO
|
||||||
|
Power: 5V/1A, via Type-C or GPIO
|
||||||
|
|
||||||
|
Signed-off-by: Julian Pidancet <julian@pidancet.net>
|
||||||
|
---
|
||||||
|
|
||||||
|
This is another shot at previous work submitted by Marty Jones
|
||||||
|
<mj8263788@gmail.com> (https://lore.kernel.org/linux-arm-kernel/20201228152836.02795e09.mj8263788@gmail.com/),
|
||||||
|
which is now a year old.
|
||||||
|
|
||||||
|
v2: Following up on Robin Murphy's comments, the NEO3 DTS is now
|
||||||
|
standalone and no longer includes the nanopi R2S one. The lan_led and
|
||||||
|
wan_len nodes have been removed, and the sys_led node has been renamed
|
||||||
|
to status_led in accordance with the board schematics.
|
||||||
|
|
||||||
|
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||||
|
.../boot/dts/rockchip/rk3328-nanopi-neo3.dts | 396 ++++++++++++++++++
|
||||||
|
2 files changed, 397 insertions(+)
|
||||||
|
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||||
|
@@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
|
||||||
|
@@ -0,0 +1,394 @@
|
||||||
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||||
|
+/*
|
||||||
|
+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
|
||||||
|
+ * Copyright (c) 2022 Julian Pidancet <julian@pidancet.net>
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+/dts-v1/;
|
||||||
|
+
|
||||||
|
+#include <dt-bindings/input/input.h>
|
||||||
|
+#include <dt-bindings/gpio/gpio.h>
|
||||||
|
+#include "rk3328.dtsi"
|
||||||
|
+
|
||||||
|
+/ {
|
||||||
|
+ model = "FriendlyElec NanoPi NEO3";
|
||||||
|
+ compatible = "friendlyarm,nanopi-neo3", "rockchip,rk3328";
|
||||||
|
+
|
||||||
|
+ aliases {
|
||||||
|
+ led-boot = &status_led;
|
||||||
|
+ led-failsafe = &status_led;
|
||||||
|
+ led-running = &status_led;
|
||||||
|
+ led-upgrade = &status_led;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ chosen {
|
||||||
|
+ stdout-path = "serial2:1500000n8";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gmac_clk: gmac-clock {
|
||||||
|
+ compatible = "fixed-clock";
|
||||||
|
+ clock-frequency = <125000000>;
|
||||||
|
+ clock-output-names = "gmac_clkin";
|
||||||
|
+ #clock-cells = <0>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ keys {
|
||||||
|
+ compatible = "gpio-keys";
|
||||||
|
+ pinctrl-0 = <&reset_button_pin>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+
|
||||||
|
+ reset {
|
||||||
|
+ label = "reset";
|
||||||
|
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||||
|
+ linux,code = <KEY_RESTART>;
|
||||||
|
+ debounce-interval = <50>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ leds {
|
||||||
|
+ compatible = "gpio-leds";
|
||||||
|
+ pinctrl-0 = <&status_led_pin>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+
|
||||||
|
+ status_led: led-0 {
|
||||||
|
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ label = "nanopi-neo3:green:status";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vcc_io_sdio: sdmmcio-regulator {
|
||||||
|
+ compatible = "regulator-gpio";
|
||||||
|
+ enable-active-high;
|
||||||
|
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ pinctrl-0 = <&sdio_vcc_pin>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ regulator-name = "vcc_io_sdio";
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-min-microvolt = <1800000>;
|
||||||
|
+ regulator-max-microvolt = <3300000>;
|
||||||
|
+ regulator-settling-time-us = <5000>;
|
||||||
|
+ regulator-type = "voltage";
|
||||||
|
+ startup-delay-us = <2000>;
|
||||||
|
+ states = <1800000 0x1>,
|
||||||
|
+ <3300000 0x0>;
|
||||||
|
+ vin-supply = <&vcc_io_33>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vcc_sd: sdmmc-regulator {
|
||||||
|
+ compatible = "regulator-fixed";
|
||||||
|
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||||
|
+ pinctrl-0 = <&sdmmc0m1_pin>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ regulator-name = "vcc_sd";
|
||||||
|
+ regulator-boot-on;
|
||||||
|
+ regulator-min-microvolt = <3300000>;
|
||||||
|
+ regulator-max-microvolt = <3300000>;
|
||||||
|
+ vin-supply = <&vcc_io_33>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vdd_5v: vdd-5v {
|
||||||
|
+ compatible = "regulator-fixed";
|
||||||
|
+ regulator-name = "vdd_5v";
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-boot-on;
|
||||||
|
+ regulator-min-microvolt = <5000000>;
|
||||||
|
+ regulator-max-microvolt = <5000000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vcc_rtl8153: vcc-rtl8153-regulator {
|
||||||
|
+ compatible = "regulator-fixed";
|
||||||
|
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ pinctrl-0 = <&rtl8153_en_drv>;
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-name = "vcc_rtl8153";
|
||||||
|
+ regulator-min-microvolt = <5000000>;
|
||||||
|
+ regulator-max-microvolt = <5000000>;
|
||||||
|
+ enable-active-high;
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&cpu0 {
|
||||||
|
+ cpu-supply = <&vdd_arm>;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&cpu1 {
|
||||||
|
+ cpu-supply = <&vdd_arm>;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&cpu2 {
|
||||||
|
+ cpu-supply = <&vdd_arm>;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&cpu3 {
|
||||||
|
+ cpu-supply = <&vdd_arm>;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&display_subsystem {
|
||||||
|
+ status = "disabled";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&gmac2io {
|
||||||
|
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
|
||||||
|
+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
|
||||||
|
+ clock_in_out = "input";
|
||||||
|
+ phy-handle = <&rtl8211e>;
|
||||||
|
+ phy-mode = "rgmii";
|
||||||
|
+ phy-supply = <&vcc_io_33>;
|
||||||
|
+ pinctrl-0 = <&rgmiim1_pins>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ rx_delay = <0x18>;
|
||||||
|
+ snps,aal;
|
||||||
|
+ tx_delay = <0x24>;
|
||||||
|
+ status = "okay";
|
||||||
|
+
|
||||||
|
+ mdio {
|
||||||
|
+ compatible = "snps,dwmac-mdio";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+
|
||||||
|
+ rtl8211e: ethernet-phy@1 {
|
||||||
|
+ reg = <1>;
|
||||||
|
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ reset-assert-us = <10000>;
|
||||||
|
+ reset-deassert-us = <50000>;
|
||||||
|
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&i2c1 {
|
||||||
|
+ status = "okay";
|
||||||
|
+
|
||||||
|
+ rk805: pmic@18 {
|
||||||
|
+ compatible = "rockchip,rk805";
|
||||||
|
+ reg = <0x18>;
|
||||||
|
+ interrupt-parent = <&gpio1>;
|
||||||
|
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
+ #clock-cells = <1>;
|
||||||
|
+ clock-output-names = "xin32k", "rk805-clkout2";
|
||||||
|
+ gpio-controller;
|
||||||
|
+ #gpio-cells = <2>;
|
||||||
|
+ pinctrl-0 = <&pmic_int_l>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ rockchip,system-power-controller;
|
||||||
|
+ wakeup-source;
|
||||||
|
+
|
||||||
|
+ vcc1-supply = <&vdd_5v>;
|
||||||
|
+ vcc2-supply = <&vdd_5v>;
|
||||||
|
+ vcc3-supply = <&vdd_5v>;
|
||||||
|
+ vcc4-supply = <&vdd_5v>;
|
||||||
|
+ vcc5-supply = <&vcc_io_33>;
|
||||||
|
+ vcc6-supply = <&vdd_5v>;
|
||||||
|
+
|
||||||
|
+ regulators {
|
||||||
|
+ vdd_log: DCDC_REG1 {
|
||||||
|
+ regulator-name = "vdd_log";
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-boot-on;
|
||||||
|
+ regulator-min-microvolt = <712500>;
|
||||||
|
+ regulator-max-microvolt = <1450000>;
|
||||||
|
+ regulator-ramp-delay = <12500>;
|
||||||
|
+
|
||||||
|
+ regulator-state-mem {
|
||||||
|
+ regulator-on-in-suspend;
|
||||||
|
+ regulator-suspend-microvolt = <1000000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vdd_arm: DCDC_REG2 {
|
||||||
|
+ regulator-name = "vdd_arm";
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-boot-on;
|
||||||
|
+ regulator-min-microvolt = <712500>;
|
||||||
|
+ regulator-max-microvolt = <1450000>;
|
||||||
|
+ regulator-ramp-delay = <12500>;
|
||||||
|
+
|
||||||
|
+ regulator-state-mem {
|
||||||
|
+ regulator-on-in-suspend;
|
||||||
|
+ regulator-suspend-microvolt = <950000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vcc_ddr: DCDC_REG3 {
|
||||||
|
+ regulator-name = "vcc_ddr";
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-boot-on;
|
||||||
|
+
|
||||||
|
+ regulator-state-mem {
|
||||||
|
+ regulator-on-in-suspend;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vcc_io_33: DCDC_REG4 {
|
||||||
|
+ regulator-name = "vcc_io_33";
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-boot-on;
|
||||||
|
+ regulator-min-microvolt = <3300000>;
|
||||||
|
+ regulator-max-microvolt = <3300000>;
|
||||||
|
+
|
||||||
|
+ regulator-state-mem {
|
||||||
|
+ regulator-on-in-suspend;
|
||||||
|
+ regulator-suspend-microvolt = <3300000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vcc_18: LDO_REG1 {
|
||||||
|
+ regulator-name = "vcc_18";
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-boot-on;
|
||||||
|
+ regulator-min-microvolt = <1800000>;
|
||||||
|
+ regulator-max-microvolt = <1800000>;
|
||||||
|
+
|
||||||
|
+ regulator-state-mem {
|
||||||
|
+ regulator-on-in-suspend;
|
||||||
|
+ regulator-suspend-microvolt = <1800000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vcc18_emmc: LDO_REG2 {
|
||||||
|
+ regulator-name = "vcc18_emmc";
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-boot-on;
|
||||||
|
+ regulator-min-microvolt = <1800000>;
|
||||||
|
+ regulator-max-microvolt = <1800000>;
|
||||||
|
+
|
||||||
|
+ regulator-state-mem {
|
||||||
|
+ regulator-on-in-suspend;
|
||||||
|
+ regulator-suspend-microvolt = <1800000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vdd_10: LDO_REG3 {
|
||||||
|
+ regulator-name = "vdd_10";
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ regulator-boot-on;
|
||||||
|
+ regulator-min-microvolt = <1000000>;
|
||||||
|
+ regulator-max-microvolt = <1000000>;
|
||||||
|
+
|
||||||
|
+ regulator-state-mem {
|
||||||
|
+ regulator-on-in-suspend;
|
||||||
|
+ regulator-suspend-microvolt = <1000000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&io_domains {
|
||||||
|
+ pmuio-supply = <&vcc_io_33>;
|
||||||
|
+ vccio1-supply = <&vcc_io_33>;
|
||||||
|
+ vccio2-supply = <&vcc18_emmc>;
|
||||||
|
+ vccio3-supply = <&vcc_io_sdio>;
|
||||||
|
+ vccio4-supply = <&vcc_18>;
|
||||||
|
+ vccio5-supply = <&vcc_io_33>;
|
||||||
|
+ vccio6-supply = <&vcc_io_33>;
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&pinctrl {
|
||||||
|
+ button {
|
||||||
|
+ reset_button_pin: reset-button-pin {
|
||||||
|
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ethernet-phy {
|
||||||
|
+ eth_phy_reset_pin: eth-phy-reset-pin {
|
||||||
|
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ leds {
|
||||||
|
+ status_led_pin: status-led-pin {
|
||||||
|
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ pmic {
|
||||||
|
+ pmic_int_l: pmic-int-l {
|
||||||
|
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sd {
|
||||||
|
+ sdio_vcc_pin: sdio-vcc-pin {
|
||||||
|
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ usb {
|
||||||
|
+ rtl8153_en_drv: rtl8153-en-drv {
|
||||||
|
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&pwm2 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&sdmmc {
|
||||||
|
+ bus-width = <4>;
|
||||||
|
+ cap-sd-highspeed;
|
||||||
|
+ disable-wp;
|
||||||
|
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ sd-uhs-sdr12;
|
||||||
|
+ sd-uhs-sdr25;
|
||||||
|
+ sd-uhs-sdr50;
|
||||||
|
+ sd-uhs-sdr104;
|
||||||
|
+ vmmc-supply = <&vcc_sd>;
|
||||||
|
+ vqmmc-supply = <&vcc_io_sdio>;
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&tsadc {
|
||||||
|
+ rockchip,hw-tshut-mode = <0>;
|
||||||
|
+ rockchip,hw-tshut-polarity = <0>;
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&u2phy {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&u2phy_host {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&u2phy_otg {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&uart2 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&usb20_otg {
|
||||||
|
+ status = "okay";
|
||||||
|
+ dr_mode = "host";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&usb_host0_ehci {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&usb_host0_ohci {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&usbdrd3 {
|
||||||
|
+ dr_mode = "host";
|
||||||
|
+ status = "okay";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+
|
||||||
|
+ usb-eth@2 {
|
||||||
|
+ compatible = "realtek,rtl8153";
|
||||||
|
+ reg = <2>;
|
||||||
|
+
|
||||||
|
+ realtek,led-data = <0x87>;
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
@ -0,0 +1,30 @@
|
|||||||
|
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||||
|
@@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-an
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-panther-x2.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
|
||||||
|
@@ -98,9 +99,19 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lu
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-opc-h66k.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-opc-h68k.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-opc-h69k.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r68s.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-t68m.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-seewo-sv21.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s-plus.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||||
|
@@ -68,6 +68,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b-plus.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-king3399.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-h3399pc.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-dlfr100.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mpc1903.dtb
|
||||||
|
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-xiaobao-nas-v1.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
|
||||||
@ -0,0 +1,45 @@
|
|||||||
|
From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
|
||||||
|
From: wevsty <ty@wevs.org>
|
||||||
|
Date: Mon, 24 Aug 2020 02:27:11 +0800
|
||||||
|
Subject: [PATCH] char: add support for rockchip hardware random number
|
||||||
|
generator
|
||||||
|
|
||||||
|
This patch provides hardware random number generator support for all rockchip SOC.
|
||||||
|
|
||||||
|
rockchip-rng.c from https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/char/hw_random/rockchip-rng.c
|
||||||
|
|
||||||
|
Signed-off-by: wevsty <ty@wevs.org>
|
||||||
|
---
|
||||||
|
|
||||||
|
--- a/drivers/char/hw_random/Kconfig
|
||||||
|
+++ b/drivers/char/hw_random/Kconfig
|
||||||
|
@@ -383,6 +383,19 @@ config HW_RANDOM_STM32
|
||||||
|
|
||||||
|
If unsure, say N.
|
||||||
|
|
||||||
|
+config HW_RANDOM_ROCKCHIP
|
||||||
|
+ tristate "Rockchip Random Number Generator support"
|
||||||
|
+ depends on ARCH_ROCKCHIP
|
||||||
|
+ default HW_RANDOM
|
||||||
|
+ help
|
||||||
|
+ This driver provides kernel-side support for the Random Number
|
||||||
|
+ Generator hardware found on Rockchip cpus.
|
||||||
|
+
|
||||||
|
+ To compile this driver as a module, choose M here: the
|
||||||
|
+ module will be called rockchip-rng.
|
||||||
|
+
|
||||||
|
+ If unsure, say Y.
|
||||||
|
+
|
||||||
|
config HW_RANDOM_PIC32
|
||||||
|
tristate "Microchip PIC32 Random Number Generator support"
|
||||||
|
depends on MACH_PIC32 || COMPILE_TEST
|
||||||
|
--- a/drivers/char/hw_random/Makefile
|
||||||
|
+++ b/drivers/char/hw_random/Makefile
|
||||||
|
@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
|
||||||
|
obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
|
||||||
|
obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
|
||||||
|
obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
|
||||||
|
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
|
||||||
|
obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
|
||||||
|
obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
|
||||||
|
obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
|
||||||
@ -0,0 +1,69 @@
|
|||||||
|
From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
|
||||||
|
From: wevsty <ty@wevs.org>
|
||||||
|
Date: Mon, 24 Aug 2020 02:27:11 +0800
|
||||||
|
Subject: [PATCH] arm64: dts: rockchip: add hardware random number generator
|
||||||
|
for RK3328 and RK3399
|
||||||
|
|
||||||
|
Adding Hardware Random Number Generator Resources to the RK3328 and RK3399.
|
||||||
|
|
||||||
|
Signed-off-by: wevsty <ty@wevs.org>
|
||||||
|
---
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||||
|
@@ -281,6 +281,17 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+ rng: rng@ff060000 {
|
||||||
|
+ compatible = "rockchip,cryptov1-rng";
|
||||||
|
+ reg = <0x0 0xff060000 0x0 0x4000>;
|
||||||
|
+
|
||||||
|
+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
|
||||||
|
+ clock-names = "clk_crypto", "hclk_crypto";
|
||||||
|
+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
|
||||||
|
+ assigned-clock-rates = <150000000>, <100000000>;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
grf: syscon@ff100000 {
|
||||||
|
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
|
||||||
|
reg = <0x0 0xff100000 0x0 0x1000>;
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||||
|
@@ -2106,6 +2106,16 @@
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
+ rng: rng@ff8b8000 {
|
||||||
|
+ compatible = "rockchip,cryptov1-rng";
|
||||||
|
+ reg = <0x0 0xff8b8000 0x0 0x1000>;
|
||||||
|
+ clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
|
||||||
|
+ clock-names = "clk_crypto", "hclk_crypto";
|
||||||
|
+ assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
|
||||||
|
+ assigned-clock-rates = <150000000>, <100000000>;
|
||||||
|
+ status = "okay";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
gpu: gpu@ff9a0000 {
|
||||||
|
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
|
||||||
|
reg = <0x0 0xff9a0000 0x0 0x10000>;
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||||
|
@@ -215,6 +215,16 @@
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
+ rng: rng@fe388000 {
|
||||||
|
+ compatible = "rockchip,cryptov2-rng";
|
||||||
|
+ reg = <0x0 0xfe388000 0x0 0x2000>;
|
||||||
|
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
|
||||||
|
+ clock-names = "clk_trng", "hclk_trng";
|
||||||
|
+ resets = <&cru SRST_TRNG_NS>;
|
||||||
|
+ reset-names = "reset";
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
combphy0: phy@fe820000 {
|
||||||
|
compatible = "rockchip,rk3568-naneng-combphy";
|
||||||
|
reg = <0x0 0xfe820000 0x0 0x100>;
|
||||||
@ -0,0 +1,44 @@
|
|||||||
|
From fcd9629c05f373771e85920e1c1d0ab252617878 Mon Sep 17 00:00:00 2001
|
||||||
|
From: hmz007 <hmz007@gmail.com>
|
||||||
|
Date: Tue, 19 Nov 2019 13:53:25 +0800
|
||||||
|
Subject: [PATCH] PM / devfreq: rockchip: add devfreq driver for rk3328 dmc
|
||||||
|
|
||||||
|
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/devfreq/Kconfig | 18 +-
|
||||||
|
drivers/devfreq/Makefile | 1 +
|
||||||
|
drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++++++++++++++++++
|
||||||
|
3 files changed, 862 insertions(+), 3 deletions(-)
|
||||||
|
create mode 100644 drivers/devfreq/rk3328_dmc.c
|
||||||
|
|
||||||
|
--- a/drivers/devfreq/Kconfig
|
||||||
|
+++ b/drivers/devfreq/Kconfig
|
||||||
|
@@ -129,6 +129,18 @@ config ARM_MEDIATEK_CCI_DEVFREQ
|
||||||
|
buck voltages and update a proper CCI frequency. Use the notification
|
||||||
|
to get the regulator status.
|
||||||
|
|
||||||
|
+config ARM_RK3328_DMC_DEVFREQ
|
||||||
|
+ tristate "ARM RK3328 DMC DEVFREQ Driver"
|
||||||
|
+ depends on ARCH_ROCKCHIP
|
||||||
|
+ select DEVFREQ_EVENT_ROCKCHIP_DFI
|
||||||
|
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
|
||||||
|
+ select PM_DEVFREQ_EVENT
|
||||||
|
+ select PM_OPP
|
||||||
|
+ help
|
||||||
|
+ This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller).
|
||||||
|
+ It sets the frequency for the memory controller and reads the usage counts
|
||||||
|
+ from hardware.
|
||||||
|
+
|
||||||
|
config ARM_RK3399_DMC_DEVFREQ
|
||||||
|
tristate "ARM RK3399 DMC DEVFREQ Driver"
|
||||||
|
depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
|
||||||
|
--- a/drivers/devfreq/Makefile
|
||||||
|
+++ b/drivers/devfreq/Makefile
|
||||||
|
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) +=
|
||||||
|
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
|
||||||
|
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
|
||||||
|
obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
|
||||||
|
+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o
|
||||||
|
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
|
||||||
|
obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
|
||||||
|
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
|
||||||
@ -0,0 +1,210 @@
|
|||||||
|
From ce6d3614888e6358466f0e84e248177a6bca5258 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Tang Yun ping <typ@rock-chips.com>
|
||||||
|
Date: Thu, 4 May 2017 20:49:58 +0800
|
||||||
|
Subject: [PATCH] clk: rockchip: support setting ddr clock via SIP Version 2
|
||||||
|
APIs
|
||||||
|
|
||||||
|
commit 764e893ee82321938fc6f4349e9e7caf06a04410 rockchip.
|
||||||
|
|
||||||
|
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
|
||||||
|
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/clk/rockchip/clk-ddr.c | 130 ++++++++++++++++++++++++++++
|
||||||
|
drivers/clk/rockchip/clk-rk3328.c | 7 +-
|
||||||
|
drivers/clk/rockchip/clk.h | 3 +-
|
||||||
|
include/soc/rockchip/rockchip_sip.h | 11 +++
|
||||||
|
4 files changed, 147 insertions(+), 4 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/clk/rockchip/clk-ddr.c
|
||||||
|
+++ b/drivers/clk/rockchip/clk-ddr.c
|
||||||
|
@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddr
|
||||||
|
.get_parent = rockchip_ddrclk_get_parent,
|
||||||
|
};
|
||||||
|
|
||||||
|
+/* See v4.4/include/dt-bindings/display/rk_fb.h */
|
||||||
|
+#define SCREEN_NULL 0
|
||||||
|
+#define SCREEN_HDMI 6
|
||||||
|
+
|
||||||
|
+static inline int rk_drm_get_lcdc_type(void)
|
||||||
|
+{
|
||||||
|
+ return SCREEN_NULL;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+struct share_params {
|
||||||
|
+ u32 hz;
|
||||||
|
+ u32 lcdc_type;
|
||||||
|
+ u32 vop;
|
||||||
|
+ u32 vop_dclk_mode;
|
||||||
|
+ u32 sr_idle_en;
|
||||||
|
+ u32 addr_mcu_el3;
|
||||||
|
+ /*
|
||||||
|
+ * 1: need to wait flag1
|
||||||
|
+ * 0: never wait flag1
|
||||||
|
+ */
|
||||||
|
+ u32 wait_flag1;
|
||||||
|
+ /*
|
||||||
|
+ * 1: need to wait flag1
|
||||||
|
+ * 0: never wait flag1
|
||||||
|
+ */
|
||||||
|
+ u32 wait_flag0;
|
||||||
|
+ u32 complt_hwirq;
|
||||||
|
+ /* if need, add parameter after */
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+struct rockchip_ddrclk_data {
|
||||||
|
+ u32 inited_flag;
|
||||||
|
+ void __iomem *share_memory;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct rockchip_ddrclk_data ddr_data;
|
||||||
|
+
|
||||||
|
+static void rockchip_ddrclk_data_init(void)
|
||||||
|
+{
|
||||||
|
+ struct arm_smccc_res res;
|
||||||
|
+
|
||||||
|
+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
|
||||||
|
+ 1, SHARE_PAGE_TYPE_DDR, 0,
|
||||||
|
+ 0, 0, 0, 0, &res);
|
||||||
|
+
|
||||||
|
+ if (!res.a0) {
|
||||||
|
+ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
|
||||||
|
+ ddr_data.inited_flag = 1;
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
|
||||||
|
+ unsigned long drate,
|
||||||
|
+ unsigned long prate)
|
||||||
|
+{
|
||||||
|
+ struct share_params *p;
|
||||||
|
+ struct arm_smccc_res res;
|
||||||
|
+
|
||||||
|
+ if (!ddr_data.inited_flag)
|
||||||
|
+ rockchip_ddrclk_data_init();
|
||||||
|
+
|
||||||
|
+ p = (struct share_params *)ddr_data.share_memory;
|
||||||
|
+
|
||||||
|
+ p->hz = drate;
|
||||||
|
+ p->lcdc_type = rk_drm_get_lcdc_type();
|
||||||
|
+ p->wait_flag1 = 1;
|
||||||
|
+ p->wait_flag0 = 1;
|
||||||
|
+
|
||||||
|
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||||
|
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||||
|
+ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
|
||||||
|
+ 0, 0, 0, 0, &res);
|
||||||
|
+
|
||||||
|
+ if ((int)res.a1 == -6) {
|
||||||
|
+ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
|
||||||
|
+ /* TODO: rockchip_dmcfreq_wait_complete(); */
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return res.a0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
|
||||||
|
+ (struct clk_hw *hw, unsigned long parent_rate)
|
||||||
|
+{
|
||||||
|
+ struct arm_smccc_res res;
|
||||||
|
+
|
||||||
|
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||||
|
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||||
|
+ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
|
||||||
|
+ 0, 0, 0, 0, &res);
|
||||||
|
+ if (!res.a0)
|
||||||
|
+ return res.a1;
|
||||||
|
+ else
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
|
||||||
|
+ unsigned long rate,
|
||||||
|
+ unsigned long *prate)
|
||||||
|
+{
|
||||||
|
+ struct share_params *p;
|
||||||
|
+ struct arm_smccc_res res;
|
||||||
|
+
|
||||||
|
+ if (!ddr_data.inited_flag)
|
||||||
|
+ rockchip_ddrclk_data_init();
|
||||||
|
+
|
||||||
|
+ p = (struct share_params *)ddr_data.share_memory;
|
||||||
|
+
|
||||||
|
+ p->hz = rate;
|
||||||
|
+
|
||||||
|
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||||
|
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||||
|
+ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
|
||||||
|
+ 0, 0, 0, 0, &res);
|
||||||
|
+ if (!res.a0)
|
||||||
|
+ return res.a1;
|
||||||
|
+ else
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
|
||||||
|
+ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
|
||||||
|
+ .set_rate = rockchip_ddrclk_sip_set_rate_v2,
|
||||||
|
+ .round_rate = rockchip_ddrclk_sip_round_rate_v2,
|
||||||
|
+ .get_parent = rockchip_ddrclk_get_parent,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||||
|
const char *const *parent_names,
|
||||||
|
u8 num_parents, int mux_offset,
|
||||||
|
@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk
|
||||||
|
case ROCKCHIP_DDRCLK_SIP:
|
||||||
|
init.ops = &rockchip_ddrclk_sip_ops;
|
||||||
|
break;
|
||||||
|
+ case ROCKCHIP_DDRCLK_SIP_V2:
|
||||||
|
+ init.ops = &rockchip_ddrclk_sip_ops_v2;
|
||||||
|
+ break;
|
||||||
|
default:
|
||||||
|
pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
|
||||||
|
kfree(ddrclk);
|
||||||
|
--- a/drivers/clk/rockchip/clk-rk3328.c
|
||||||
|
+++ b/drivers/clk/rockchip/clk-rk3328.c
|
||||||
|
@@ -315,9 +315,10 @@ static struct rockchip_clk_branch rk3328
|
||||||
|
RK3328_CLKGATE_CON(14), 1, GFLAGS),
|
||||||
|
|
||||||
|
/* PD_DDR */
|
||||||
|
- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||||
|
- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||||
|
- RK3328_CLKGATE_CON(0), 4, GFLAGS),
|
||||||
|
+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
|
||||||
|
+ RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
|
||||||
|
+ ROCKCHIP_DDRCLK_SIP_V2),
|
||||||
|
+
|
||||||
|
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||||
|
RK3328_CLKGATE_CON(18), 6, GFLAGS),
|
||||||
|
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||||
|
--- a/drivers/clk/rockchip/clk.h
|
||||||
|
+++ b/drivers/clk/rockchip/clk.h
|
||||||
|
@@ -486,7 +486,8 @@ struct clk *rockchip_clk_register_mmc(co
|
||||||
|
* DDRCLK flags, including method of setting the rate
|
||||||
|
* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
|
||||||
|
*/
|
||||||
|
-#define ROCKCHIP_DDRCLK_SIP BIT(0)
|
||||||
|
+#define ROCKCHIP_DDRCLK_SIP 0x01
|
||||||
|
+#define ROCKCHIP_DDRCLK_SIP_V2 0x03
|
||||||
|
|
||||||
|
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||||
|
const char *const *parent_names,
|
||||||
|
--- a/include/soc/rockchip/rockchip_sip.h
|
||||||
|
+++ b/include/soc/rockchip/rockchip_sip.h
|
||||||
|
@@ -16,5 +16,16 @@
|
||||||
|
#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
|
||||||
|
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
|
||||||
|
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
|
||||||
|
+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
|
||||||
|
+
|
||||||
|
+#define ROCKCHIP_SIP_SHARE_MEM 0x82000009
|
||||||
|
+
|
||||||
|
+/* Share mem page types */
|
||||||
|
+typedef enum {
|
||||||
|
+ SHARE_PAGE_TYPE_INVALID = 0,
|
||||||
|
+ SHARE_PAGE_TYPE_UARTDBG,
|
||||||
|
+ SHARE_PAGE_TYPE_DDR,
|
||||||
|
+ SHARE_PAGE_TYPE_MAX,
|
||||||
|
+} share_page_type_t;
|
||||||
|
|
||||||
|
#endif
|
||||||
@ -0,0 +1,660 @@
|
|||||||
|
From 4db93c6dad0c71750b86163df2fdb21c35f00d9a Mon Sep 17 00:00:00 2001
|
||||||
|
From: hmz007 <hmz007@gmail.com>
|
||||||
|
Date: Tue, 19 Nov 2019 12:49:48 +0800
|
||||||
|
Subject: [PATCH] PM / devfreq: rockchip-dfi: add more soc support
|
||||||
|
|
||||||
|
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/devfreq/event/rockchip-dfi.c | 554 ++++++++++++++++++++++++---
|
||||||
|
1 file changed, 505 insertions(+), 49 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||||
|
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||||
|
@@ -18,25 +18,66 @@
|
||||||
|
#include <linux/list.h>
|
||||||
|
#include <linux/of.h>
|
||||||
|
|
||||||
|
-#include <soc/rockchip/rk3399_grf.h>
|
||||||
|
-
|
||||||
|
-#define RK3399_DMC_NUM_CH 2
|
||||||
|
+#define PX30_PMUGRF_OS_REG2 0x208
|
||||||
|
|
||||||
|
+#define RK3128_GRF_SOC_CON0 0x140
|
||||||
|
+#define RK3128_GRF_OS_REG1 0x1cc
|
||||||
|
+#define RK3128_GRF_DFI_WRNUM 0x220
|
||||||
|
+#define RK3128_GRF_DFI_RDNUM 0x224
|
||||||
|
+#define RK3128_GRF_DFI_TIMERVAL 0x22c
|
||||||
|
+#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
|
||||||
|
+#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
|
||||||
|
+
|
||||||
|
+#define RK3288_PMU_SYS_REG2 0x9c
|
||||||
|
+#define RK3288_GRF_SOC_CON4 0x254
|
||||||
|
+#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
|
||||||
|
+#define RK3288_DFI_EN (0x30003 << 14)
|
||||||
|
+#define RK3288_DFI_DIS (0x30000 << 14)
|
||||||
|
+#define RK3288_LPDDR_SEL (0x10001 << 13)
|
||||||
|
+#define RK3288_DDR3_SEL (0x10000 << 13)
|
||||||
|
+
|
||||||
|
+#define RK3328_GRF_OS_REG2 0x5d0
|
||||||
|
+
|
||||||
|
+#define RK3368_GRF_DDRC0_CON0 0x600
|
||||||
|
+#define RK3368_GRF_SOC_STATUS5 0x494
|
||||||
|
+#define RK3368_GRF_SOC_STATUS6 0x498
|
||||||
|
+#define RK3368_GRF_SOC_STATUS8 0x4a0
|
||||||
|
+#define RK3368_GRF_SOC_STATUS9 0x4a4
|
||||||
|
+#define RK3368_GRF_SOC_STATUS10 0x4a8
|
||||||
|
+#define RK3368_DFI_EN (0x30003 << 5)
|
||||||
|
+#define RK3368_DFI_DIS (0x30000 << 5)
|
||||||
|
+
|
||||||
|
+#define MAX_DMC_NUM_CH 2
|
||||||
|
+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||||
|
+#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
|
||||||
|
/* DDRMON_CTRL */
|
||||||
|
-#define DDRMON_CTRL 0x04
|
||||||
|
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
|
||||||
|
-#define LPDDR4_EN (0x10001 << 4)
|
||||||
|
-#define HARDWARE_EN (0x10001 << 3)
|
||||||
|
-#define LPDDR3_EN (0x10001 << 2)
|
||||||
|
-#define SOFTWARE_EN (0x10001 << 1)
|
||||||
|
-#define SOFTWARE_DIS (0x10000 << 1)
|
||||||
|
-#define TIME_CNT_EN (0x10001 << 0)
|
||||||
|
+#define DDRMON_CTRL 0x04
|
||||||
|
+#define CLR_DDRMON_CTRL (0x3f0000 << 0)
|
||||||
|
+#define DDR4_EN (0x10001 << 5)
|
||||||
|
+#define LPDDR4_EN (0x10001 << 4)
|
||||||
|
+#define HARDWARE_EN (0x10001 << 3)
|
||||||
|
+#define LPDDR2_3_EN (0x10001 << 2)
|
||||||
|
+#define SOFTWARE_EN (0x10001 << 1)
|
||||||
|
+#define SOFTWARE_DIS (0x10000 << 1)
|
||||||
|
+#define TIME_CNT_EN (0x10001 << 0)
|
||||||
|
|
||||||
|
#define DDRMON_CH0_COUNT_NUM 0x28
|
||||||
|
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
|
||||||
|
#define DDRMON_CH1_COUNT_NUM 0x3c
|
||||||
|
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
|
||||||
|
|
||||||
|
+/* pmu grf */
|
||||||
|
+#define PMUGRF_OS_REG2 0x308
|
||||||
|
+
|
||||||
|
+enum {
|
||||||
|
+ DDR4 = 0,
|
||||||
|
+ DDR3 = 3,
|
||||||
|
+ LPDDR2 = 5,
|
||||||
|
+ LPDDR3 = 6,
|
||||||
|
+ LPDDR4 = 7,
|
||||||
|
+ UNUSED = 0xFF
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
struct dmc_usage {
|
||||||
|
u32 access;
|
||||||
|
u32 total;
|
||||||
|
@@ -50,33 +91,261 @@ struct dmc_usage {
|
||||||
|
struct rockchip_dfi {
|
||||||
|
struct devfreq_event_dev *edev;
|
||||||
|
struct devfreq_event_desc *desc;
|
||||||
|
- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
|
||||||
|
+ struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
|
||||||
|
struct device *dev;
|
||||||
|
void __iomem *regs;
|
||||||
|
struct regmap *regmap_pmu;
|
||||||
|
+ struct regmap *regmap_grf;
|
||||||
|
+ struct regmap *regmap_pmugrf;
|
||||||
|
struct clk *clk;
|
||||||
|
+ u32 dram_type;
|
||||||
|
+ /*
|
||||||
|
+ * available mask, 1: available, 0: not available
|
||||||
|
+ * each bit represent a channel
|
||||||
|
+ */
|
||||||
|
+ u32 ch_msk;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+
|
||||||
|
+ regmap_write(info->regmap_grf,
|
||||||
|
+ RK3128_GRF_SOC_CON0,
|
||||||
|
+ RK3128_DDR_MONITOR_EN);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+
|
||||||
|
+ regmap_write(info->regmap_grf,
|
||||||
|
+ RK3128_GRF_SOC_CON0,
|
||||||
|
+ RK3128_DDR_MONITOR_DISB);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ rk3128_dfi_start_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
|
||||||
|
+ struct devfreq_event_data *edata)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+ unsigned long flags;
|
||||||
|
+ u32 dfi_wr, dfi_rd, dfi_timer;
|
||||||
|
+
|
||||||
|
+ local_irq_save(flags);
|
||||||
|
+
|
||||||
|
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
|
||||||
|
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
|
||||||
|
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
|
||||||
|
+
|
||||||
|
+ edata->load_count = (dfi_wr + dfi_rd) * 4;
|
||||||
|
+ edata->total_count = dfi_timer;
|
||||||
|
+
|
||||||
|
+ rk3128_dfi_start_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ local_irq_restore(flags);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static const struct devfreq_event_ops rk3128_dfi_ops = {
|
||||||
|
+ .disable = rk3128_dfi_disable,
|
||||||
|
+ .enable = rk3128_dfi_enable,
|
||||||
|
+ .get_event = rk3128_dfi_get_event,
|
||||||
|
+ .set_event = rk3128_dfi_set_event,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+
|
||||||
|
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+
|
||||||
|
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ rk3288_dfi_start_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+ u32 tmp, max = 0;
|
||||||
|
+ u32 i, busier_ch = 0;
|
||||||
|
+ u32 rd_count, wr_count, total_count;
|
||||||
|
+
|
||||||
|
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ /* Find out which channel is busier */
|
||||||
|
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||||
|
+ if (!(info->ch_msk & BIT(i)))
|
||||||
|
+ continue;
|
||||||
|
+ regmap_read(info->regmap_grf,
|
||||||
|
+ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
|
||||||
|
+ regmap_read(info->regmap_grf,
|
||||||
|
+ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
|
||||||
|
+ regmap_read(info->regmap_grf,
|
||||||
|
+ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
|
||||||
|
+ info->ch_usage[i].access = (wr_count + rd_count) * 4;
|
||||||
|
+ info->ch_usage[i].total = total_count;
|
||||||
|
+ tmp = info->ch_usage[i].access;
|
||||||
|
+ if (tmp > max) {
|
||||||
|
+ busier_ch = i;
|
||||||
|
+ max = tmp;
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+ rk3288_dfi_start_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ return busier_ch;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
|
||||||
|
+ struct devfreq_event_data *edata)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+ int busier_ch;
|
||||||
|
+ unsigned long flags;
|
||||||
|
+
|
||||||
|
+ local_irq_save(flags);
|
||||||
|
+ busier_ch = rk3288_dfi_get_busier_ch(edev);
|
||||||
|
+ local_irq_restore(flags);
|
||||||
|
+
|
||||||
|
+ edata->load_count = info->ch_usage[busier_ch].access;
|
||||||
|
+ edata->total_count = info->ch_usage[busier_ch].total;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static const struct devfreq_event_ops rk3288_dfi_ops = {
|
||||||
|
+ .disable = rk3288_dfi_disable,
|
||||||
|
+ .enable = rk3288_dfi_enable,
|
||||||
|
+ .get_event = rk3288_dfi_get_event,
|
||||||
|
+ .set_event = rk3288_dfi_set_event,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+
|
||||||
|
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+
|
||||||
|
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ rk3368_dfi_start_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
|
||||||
|
+{
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
|
||||||
|
+ struct devfreq_event_data *edata)
|
||||||
|
+{
|
||||||
|
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
+ unsigned long flags;
|
||||||
|
+ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
|
||||||
|
+
|
||||||
|
+ local_irq_save(flags);
|
||||||
|
+
|
||||||
|
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
|
||||||
|
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
|
||||||
|
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
|
||||||
|
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
|
||||||
|
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
|
||||||
|
+
|
||||||
|
+ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
|
||||||
|
+ edata->total_count = dfi_timer;
|
||||||
|
+
|
||||||
|
+ rk3368_dfi_start_hardware_counter(edev);
|
||||||
|
+
|
||||||
|
+ local_irq_restore(flags);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static const struct devfreq_event_ops rk3368_dfi_ops = {
|
||||||
|
+ .disable = rk3368_dfi_disable,
|
||||||
|
+ .enable = rk3368_dfi_enable,
|
||||||
|
+ .get_event = rk3368_dfi_get_event,
|
||||||
|
+ .set_event = rk3368_dfi_set_event,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||||
|
{
|
||||||
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
void __iomem *dfi_regs = info->regs;
|
||||||
|
- u32 val;
|
||||||
|
- u32 ddr_type;
|
||||||
|
-
|
||||||
|
- /* get ddr type */
|
||||||
|
- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
|
||||||
|
- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
|
||||||
|
- RK3399_PMUGRF_DDRTYPE_MASK;
|
||||||
|
|
||||||
|
/* clear DDRMON_CTRL setting */
|
||||||
|
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
|
||||||
|
|
||||||
|
/* set ddr type to dfi */
|
||||||
|
- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
|
||||||
|
- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
|
||||||
|
- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
|
||||||
|
+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
|
||||||
|
+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
|
||||||
|
+ else if (info->dram_type == LPDDR4)
|
||||||
|
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||||
|
+ else if (info->dram_type == DDR4)
|
||||||
|
+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||||
|
|
||||||
|
/* enable count, use software mode */
|
||||||
|
writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
|
||||||
|
@@ -100,12 +369,22 @@ static int rockchip_dfi_get_busier_ch(st
|
||||||
|
rockchip_dfi_stop_hardware_counter(edev);
|
||||||
|
|
||||||
|
/* Find out which channel is busier */
|
||||||
|
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
|
||||||
|
- info->ch_usage[i].access = readl_relaxed(dfi_regs +
|
||||||
|
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
|
||||||
|
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||||
|
+ if (!(info->ch_msk & BIT(i)))
|
||||||
|
+ continue;
|
||||||
|
+
|
||||||
|
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
||||||
|
DDRMON_CH0_COUNT_NUM + i * 20);
|
||||||
|
- tmp = info->ch_usage[i].access;
|
||||||
|
+
|
||||||
|
+ /* LPDDR4 BL = 16,other DDR type BL = 8 */
|
||||||
|
+ tmp = readl_relaxed(dfi_regs +
|
||||||
|
+ DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
|
||||||
|
+ if (info->dram_type == LPDDR4)
|
||||||
|
+ tmp *= 8;
|
||||||
|
+ else
|
||||||
|
+ tmp *= 4;
|
||||||
|
+ info->ch_usage[i].access = tmp;
|
||||||
|
+
|
||||||
|
if (tmp > max) {
|
||||||
|
busier_ch = i;
|
||||||
|
max = tmp;
|
||||||
|
@@ -121,7 +400,8 @@ static int rockchip_dfi_disable(struct d
|
||||||
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
|
||||||
|
rockchip_dfi_stop_hardware_counter(edev);
|
||||||
|
- clk_disable_unprepare(info->clk);
|
||||||
|
+ if (info->clk)
|
||||||
|
+ clk_disable_unprepare(info->clk);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
@@ -131,10 +411,13 @@ static int rockchip_dfi_enable(struct de
|
||||||
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
- ret = clk_prepare_enable(info->clk);
|
||||||
|
- if (ret) {
|
||||||
|
- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
|
||||||
|
- return ret;
|
||||||
|
+ if (info->clk) {
|
||||||
|
+ ret = clk_prepare_enable(info->clk);
|
||||||
|
+ if (ret) {
|
||||||
|
+ dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
|
||||||
|
+ ret);
|
||||||
|
+ return ret;
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
|
||||||
|
rockchip_dfi_start_hardware_counter(edev);
|
||||||
|
@@ -151,8 +434,11 @@ static int rockchip_dfi_get_event(struct
|
||||||
|
{
|
||||||
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||||
|
int busier_ch;
|
||||||
|
+ unsigned long flags;
|
||||||
|
|
||||||
|
+ local_irq_save(flags);
|
||||||
|
busier_ch = rockchip_dfi_get_busier_ch(edev);
|
||||||
|
+ local_irq_restore(flags);
|
||||||
|
|
||||||
|
edata->load_count = info->ch_usage[busier_ch].access;
|
||||||
|
edata->total_count = info->ch_usage[busier_ch].total;
|
||||||
|
@@ -167,22 +453,116 @@ static const struct devfreq_event_ops ro
|
||||||
|
.set_event = rockchip_dfi_set_event,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||||
|
- { .compatible = "rockchip,rk3399-dfi" },
|
||||||
|
- { },
|
||||||
|
-};
|
||||||
|
-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
||||||
|
+static __init int px30_dfi_init(struct platform_device *pdev,
|
||||||
|
+ struct rockchip_dfi *data,
|
||||||
|
+ struct devfreq_event_desc *desc)
|
||||||
|
+{
|
||||||
|
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||||
|
+ struct resource *res;
|
||||||
|
+ u32 val;
|
||||||
|
|
||||||
|
-static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||||
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
|
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||||
|
+ if (IS_ERR(data->regs))
|
||||||
|
+ return PTR_ERR(data->regs);
|
||||||
|
+
|
||||||
|
+ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
|
||||||
|
+ if (node) {
|
||||||
|
+ data->regmap_pmugrf = syscon_node_to_regmap(node);
|
||||||
|
+ if (IS_ERR(data->regmap_pmugrf))
|
||||||
|
+ return PTR_ERR(data->regmap_pmugrf);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
|
||||||
|
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||||
|
+ data->ch_msk = 1;
|
||||||
|
+ data->clk = NULL;
|
||||||
|
+
|
||||||
|
+ desc->ops = &rockchip_dfi_ops;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static __init int rk3128_dfi_init(struct platform_device *pdev,
|
||||||
|
+ struct rockchip_dfi *data,
|
||||||
|
+ struct devfreq_event_desc *desc)
|
||||||
|
{
|
||||||
|
- struct device *dev = &pdev->dev;
|
||||||
|
- struct rockchip_dfi *data;
|
||||||
|
- struct devfreq_event_desc *desc;
|
||||||
|
struct device_node *np = pdev->dev.of_node, *node;
|
||||||
|
|
||||||
|
- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||||
|
- if (!data)
|
||||||
|
- return -ENOMEM;
|
||||||
|
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||||
|
+ if (node) {
|
||||||
|
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||||
|
+ if (IS_ERR(data->regmap_grf))
|
||||||
|
+ return PTR_ERR(data->regmap_grf);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ desc->ops = &rk3128_dfi_ops;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static __init int rk3288_dfi_init(struct platform_device *pdev,
|
||||||
|
+ struct rockchip_dfi *data,
|
||||||
|
+ struct devfreq_event_desc *desc)
|
||||||
|
+{
|
||||||
|
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||||
|
+ u32 val;
|
||||||
|
+
|
||||||
|
+ node = of_parse_phandle(np, "rockchip,pmu", 0);
|
||||||
|
+ if (node) {
|
||||||
|
+ data->regmap_pmu = syscon_node_to_regmap(node);
|
||||||
|
+ if (IS_ERR(data->regmap_pmu))
|
||||||
|
+ return PTR_ERR(data->regmap_pmu);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||||
|
+ if (node) {
|
||||||
|
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||||
|
+ if (IS_ERR(data->regmap_grf))
|
||||||
|
+ return PTR_ERR(data->regmap_grf);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
|
||||||
|
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||||
|
+ data->ch_msk = READ_CH_INFO(val);
|
||||||
|
+
|
||||||
|
+ if (data->dram_type == DDR3)
|
||||||
|
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||||
|
+ RK3288_DDR3_SEL);
|
||||||
|
+ else
|
||||||
|
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||||
|
+ RK3288_LPDDR_SEL);
|
||||||
|
+
|
||||||
|
+ desc->ops = &rk3288_dfi_ops;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static __init int rk3368_dfi_init(struct platform_device *pdev,
|
||||||
|
+ struct rockchip_dfi *data,
|
||||||
|
+ struct devfreq_event_desc *desc)
|
||||||
|
+{
|
||||||
|
+ struct device *dev = &pdev->dev;
|
||||||
|
+
|
||||||
|
+ if (!dev->parent || !dev->parent->of_node)
|
||||||
|
+ return -EINVAL;
|
||||||
|
+
|
||||||
|
+ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||||
|
+ if (IS_ERR(data->regmap_grf))
|
||||||
|
+ return PTR_ERR(data->regmap_grf);
|
||||||
|
+
|
||||||
|
+ desc->ops = &rk3368_dfi_ops;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static __init int rockchip_dfi_init(struct platform_device *pdev,
|
||||||
|
+ struct rockchip_dfi *data,
|
||||||
|
+ struct devfreq_event_desc *desc)
|
||||||
|
+{
|
||||||
|
+ struct device *dev = &pdev->dev;
|
||||||
|
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||||
|
+ u32 val;
|
||||||
|
|
||||||
|
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||||
|
if (IS_ERR(data->regs))
|
||||||
|
@@ -202,21 +582,95 @@ static int rockchip_dfi_probe(struct pla
|
||||||
|
if (IS_ERR(data->regmap_pmu))
|
||||||
|
return PTR_ERR(data->regmap_pmu);
|
||||||
|
|
||||||
|
- data->dev = dev;
|
||||||
|
+ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
|
||||||
|
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||||
|
+ data->ch_msk = READ_CH_INFO(val);
|
||||||
|
+
|
||||||
|
+ desc->ops = &rockchip_dfi_ops;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static __init int rk3328_dfi_init(struct platform_device *pdev,
|
||||||
|
+ struct rockchip_dfi *data,
|
||||||
|
+ struct devfreq_event_desc *desc)
|
||||||
|
+{
|
||||||
|
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||||
|
+ struct resource *res;
|
||||||
|
+ u32 val;
|
||||||
|
+
|
||||||
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
|
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||||
|
+ if (IS_ERR(data->regs))
|
||||||
|
+ return PTR_ERR(data->regs);
|
||||||
|
+
|
||||||
|
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||||
|
+ if (node) {
|
||||||
|
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||||
|
+ if (IS_ERR(data->regmap_grf))
|
||||||
|
+ return PTR_ERR(data->regmap_grf);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
|
||||||
|
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||||
|
+ data->ch_msk = 1;
|
||||||
|
+ data->clk = NULL;
|
||||||
|
+
|
||||||
|
+ desc->ops = &rockchip_dfi_ops;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||||
|
+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
|
||||||
|
+ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
|
||||||
|
+ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
||||||
|
+ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
||||||
|
+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
||||||
|
+ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||||
|
+ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||||
|
+ { },
|
||||||
|
+};
|
||||||
|
+MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
||||||
|
+
|
||||||
|
+static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||||
|
+{
|
||||||
|
+ struct device *dev = &pdev->dev;
|
||||||
|
+ struct rockchip_dfi *data;
|
||||||
|
+ struct devfreq_event_desc *desc;
|
||||||
|
+ struct device_node *np = pdev->dev.of_node;
|
||||||
|
+ const struct of_device_id *match;
|
||||||
|
+ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
|
||||||
|
+ struct devfreq_event_desc *desc);
|
||||||
|
+
|
||||||
|
+ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||||
|
+ if (!data)
|
||||||
|
+ return -ENOMEM;
|
||||||
|
|
||||||
|
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
||||||
|
if (!desc)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
- desc->ops = &rockchip_dfi_ops;
|
||||||
|
+ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
|
||||||
|
+ if (match) {
|
||||||
|
+ init = match->data;
|
||||||
|
+ if (init) {
|
||||||
|
+ if (init(pdev, data, desc))
|
||||||
|
+ return -EINVAL;
|
||||||
|
+ } else {
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+ } else {
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
desc->driver_data = data;
|
||||||
|
desc->name = np->name;
|
||||||
|
data->desc = desc;
|
||||||
|
+ data->dev = dev;
|
||||||
|
|
||||||
|
- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
|
||||||
|
+ data->edev = devm_devfreq_event_add_edev(dev, desc);
|
||||||
|
if (IS_ERR(data->edev)) {
|
||||||
|
- dev_err(&pdev->dev,
|
||||||
|
- "failed to add devfreq-event device\n");
|
||||||
|
+ dev_err(dev, "failed to add devfreq-event device\n");
|
||||||
|
return PTR_ERR(data->edev);
|
||||||
|
}
|
||||||
|
|
||||||
@ -0,0 +1,27 @@
|
|||||||
|
From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
|
||||||
|
From: hmz007 <hmz007@gmail.com>
|
||||||
|
Date: Tue, 19 Nov 2019 14:21:51 +0800
|
||||||
|
Subject: [PATCH] arm64: dts: rockchip: rk3328: add dfi node
|
||||||
|
|
||||||
|
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||||
|
[adjusted commit title]
|
||||||
|
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 +++++++
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||||
|
@@ -1025,6 +1025,13 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+ dfi: dfi@ff790000 {
|
||||||
|
+ reg = <0x00 0xff790000 0x00 0x400>;
|
||||||
|
+ compatible = "rockchip,rk3328-dfi";
|
||||||
|
+ rockchip,grf = <&grf>;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
gic: interrupt-controller@ff811000 {
|
||||||
|
compatible = "arm,gic-400";
|
||||||
|
#interrupt-cells = <3>;
|
||||||
@ -0,0 +1,126 @@
|
|||||||
|
From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
|
||||||
|
From: hmz007 <hmz007@gmail.com>
|
||||||
|
Date: Tue, 19 Nov 2019 14:21:51 +0800
|
||||||
|
Subject: [PATCH] arm64: dts: nanopi-r2: add rk3328-dmc relate node
|
||||||
|
|
||||||
|
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||||
|
---
|
||||||
|
.../rockchip/rk3328-dram-default-timing.dtsi | 311 ++++++++++++++++++
|
||||||
|
.../dts/rockchip/rk3328-nanopi-r2-common.dtsi | 85 ++++-
|
||||||
|
include/dt-bindings/clock/rockchip-ddr.h | 63 ++++
|
||||||
|
include/dt-bindings/memory/rk3328-dram.h | 159 +++++++++
|
||||||
|
4 files changed, 617 insertions(+), 1 deletion(-)
|
||||||
|
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
|
||||||
|
create mode 100644 include/dt-bindings/clock/rockchip-ddr.h
|
||||||
|
create mode 100644 include/dt-bindings/memory/rk3328-dram.h
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||||
|
@@ -7,6 +7,7 @@
|
||||||
|
|
||||||
|
#include <dt-bindings/input/input.h>
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
+#include "rk3328-dram-default-timing.dtsi"
|
||||||
|
#include "rk3328.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
@@ -114,6 +115,72 @@
|
||||||
|
regulator-boot-on;
|
||||||
|
vin-supply = <&vdd_5v>;
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+ dmc: dmc {
|
||||||
|
+ compatible = "rockchip,rk3328-dmc";
|
||||||
|
+ devfreq-events = <&dfi>;
|
||||||
|
+ center-supply = <&vdd_log>;
|
||||||
|
+ clocks = <&cru SCLK_DDRCLK>;
|
||||||
|
+ clock-names = "dmc_clk";
|
||||||
|
+ operating-points-v2 = <&dmc_opp_table>;
|
||||||
|
+ ddr_timing = <&ddr_timing>;
|
||||||
|
+ upthreshold = <40>;
|
||||||
|
+ downdifferential = <20>;
|
||||||
|
+ auto-min-freq = <786000>;
|
||||||
|
+ auto-freq-en = <0>;
|
||||||
|
+ #cooling-cells = <2>;
|
||||||
|
+ status = "okay";
|
||||||
|
+
|
||||||
|
+ ddr_power_model: ddr_power_model {
|
||||||
|
+ compatible = "ddr_power_model";
|
||||||
|
+ dynamic-power-coefficient = <120>;
|
||||||
|
+ static-power-coefficient = <200>;
|
||||||
|
+ ts = <32000 4700 (-80) 2>;
|
||||||
|
+ thermal-zone = "soc-thermal";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ dmc_opp_table: dmc-opp-table {
|
||||||
|
+ compatible = "operating-points-v2";
|
||||||
|
+
|
||||||
|
+ rockchip,leakage-voltage-sel = <
|
||||||
|
+ 1 10 0
|
||||||
|
+ 11 254 1
|
||||||
|
+ >;
|
||||||
|
+ nvmem-cells = <&logic_leakage>;
|
||||||
|
+ nvmem-cell-names = "ddr_leakage";
|
||||||
|
+
|
||||||
|
+ opp-786000000 {
|
||||||
|
+ opp-hz = /bits/ 64 <786000000>;
|
||||||
|
+ opp-microvolt = <1075000>;
|
||||||
|
+ opp-microvolt-L0 = <1075000>;
|
||||||
|
+ opp-microvolt-L1 = <1050000>;
|
||||||
|
+ };
|
||||||
|
+ opp-798000000 {
|
||||||
|
+ opp-hz = /bits/ 64 <798000000>;
|
||||||
|
+ opp-microvolt = <1075000>;
|
||||||
|
+ opp-microvolt-L0 = <1075000>;
|
||||||
|
+ opp-microvolt-L1 = <1050000>;
|
||||||
|
+ };
|
||||||
|
+ opp-840000000 {
|
||||||
|
+ opp-hz = /bits/ 64 <840000000>;
|
||||||
|
+ opp-microvolt = <1075000>;
|
||||||
|
+ opp-microvolt-L0 = <1075000>;
|
||||||
|
+ opp-microvolt-L1 = <1050000>;
|
||||||
|
+ };
|
||||||
|
+ opp-924000000 {
|
||||||
|
+ opp-hz = /bits/ 64 <924000000>;
|
||||||
|
+ opp-microvolt = <1100000>;
|
||||||
|
+ opp-microvolt-L0 = <1100000>;
|
||||||
|
+ opp-microvolt-L1 = <1075000>;
|
||||||
|
+ };
|
||||||
|
+ opp-1056000000 {
|
||||||
|
+ opp-hz = /bits/ 64 <1056000000>;
|
||||||
|
+ opp-microvolt = <1175000>;
|
||||||
|
+ opp-microvolt-L0 = <1175000>;
|
||||||
|
+ opp-microvolt-L1 = <1150000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu0 {
|
||||||
|
@@ -132,6 +199,10 @@
|
||||||
|
cpu-supply = <&vdd_arm>;
|
||||||
|
};
|
||||||
|
|
||||||
|
+&dfi {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&display_subsystem {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
@@ -199,6 +270,7 @@
|
||||||
|
regulator-name = "vdd_log";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
+ regulator-init-microvolt = <1075000>;
|
||||||
|
regulator-min-microvolt = <712500>;
|
||||||
|
regulator-max-microvolt = <1450000>;
|
||||||
|
regulator-ramp-delay = <12500>;
|
||||||
|
@@ -213,6 +285,7 @@
|
||||||
|
regulator-name = "vdd_arm";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
+ regulator-init-microvolt = <1225000>;
|
||||||
|
regulator-min-microvolt = <712500>;
|
||||||
|
regulator-max-microvolt = <1450000>;
|
||||||
|
regulator-ramp-delay = <12500>;
|
||||||
@ -0,0 +1,44 @@
|
|||||||
|
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Leonidas P. Papadakos <papadakospan@gmail.com>
|
||||||
|
Date: Fri, 1 Mar 2019 21:55:53 +0200
|
||||||
|
Subject: [PATCH v2] arm64: dts: rockchip: add more cpu operating points for
|
||||||
|
RK3328
|
||||||
|
|
||||||
|
This allows for greater max frequency on rk3328 boards,
|
||||||
|
increasing performance.
|
||||||
|
|
||||||
|
It has been included in Armbian (a linux distibution for ARM boards)
|
||||||
|
for a while now without any reported issues
|
||||||
|
|
||||||
|
https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1392mhz-opp.patch
|
||||||
|
https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1512mhz-opp.patch
|
||||||
|
|
||||||
|
Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 15 +++++++++++++++
|
||||||
|
1 files changed, 15 insertions(+)
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||||
|
@@ -142,6 +142,21 @@
|
||||||
|
opp-microvolt = <1300000>;
|
||||||
|
clock-latency-ns = <40000>;
|
||||||
|
};
|
||||||
|
+ opp-1392000000 {
|
||||||
|
+ opp-hz = /bits/ 64 <1392000000>;
|
||||||
|
+ opp-microvolt = <1350000>;
|
||||||
|
+ clock-latency-ns = <40000>;
|
||||||
|
+ };
|
||||||
|
+ opp-1512000000 {
|
||||||
|
+ opp-hz = /bits/ 64 <1512000000>;
|
||||||
|
+ opp-microvolt = <1450000>;
|
||||||
|
+ clock-latency-ns = <40000>;
|
||||||
|
+ };
|
||||||
|
+ opp-1608000000 {
|
||||||
|
+ opp-hz = /bits/ 64 <1608000000>;
|
||||||
|
+ opp-microvolt = <1450000>;
|
||||||
|
+ clock-latency-ns = <40000>;
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
analog_sound: analog-sound {
|
||||||
@ -0,0 +1,46 @@
|
|||||||
|
From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Tianling Shen <cnsztl@immortalwrt.org>
|
||||||
|
Date: Mon, 18 Oct 2021 12:47:30 +0800
|
||||||
|
Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz
|
||||||
|
|
||||||
|
It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
|
||||||
|
and for better performance.
|
||||||
|
|
||||||
|
Co-development-by: gzelvis <gzelvis@gmail.com>
|
||||||
|
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++
|
||||||
|
1 file changed, 16 insertions(+)
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
|
||||||
|
@@ -33,6 +33,14 @@
|
||||||
|
opp-hz = /bits/ 64 <1416000000>;
|
||||||
|
opp-microvolt = <1125000 1125000 1250000>;
|
||||||
|
};
|
||||||
|
+ opp06 {
|
||||||
|
+ opp-hz = /bits/ 64 <1608000000>;
|
||||||
|
+ opp-microvolt = <1225000>;
|
||||||
|
+ };
|
||||||
|
+ opp07 {
|
||||||
|
+ opp-hz = /bits/ 64 <1800000000>;
|
||||||
|
+ opp-microvolt = <1275000>;
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
cluster1_opp: opp-table-1 {
|
||||||
|
@@ -72,6 +80,14 @@
|
||||||
|
opp-hz = /bits/ 64 <1800000000>;
|
||||||
|
opp-microvolt = <1200000 1200000 1250000>;
|
||||||
|
};
|
||||||
|
+ opp08 {
|
||||||
|
+ opp-hz = /bits/ 64 <2016000000>;
|
||||||
|
+ opp-microvolt = <1250000>;
|
||||||
|
+ };
|
||||||
|
+ opp09 {
|
||||||
|
+ opp-hz = /bits/ 64 <2208000000>;
|
||||||
|
+ opp-microvolt = <1325000>;
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
gpu_opp_table: opp-table-2 {
|
||||||
Loading…
Reference in New Issue
Block a user