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atf-rockchip: update rk3568 support
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coolsnowwolf
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commit
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@ -10,9 +10,9 @@ PKG_RELEASE:=1
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PKG_SOURCE_PROTO:=git
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PKG_SOURCE_URL=https://github.com/ARM-software/arm-trusted-firmware
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PKG_SOURCE_DATE:=2024-09-09
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PKG_SOURCE_VERSION:=0631d68d85881d4b8ffa571f49eb8b767c005f6a
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PKG_MIRROR_HASH:=6e8a83c6ee64faab46e1531948180199fa70194bb2ffec4d4a521c2b2d136cf3
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PKG_SOURCE_DATE:=2024-09-21
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PKG_SOURCE_VERSION:=2975ad055bd6e1ea3fc4179e8b785266785f0398
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PKG_MIRROR_HASH:=6cf6e03b43b3d791153dc93f067c8e078f438923cd0781be047a722342c24fe8
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PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
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File diff suppressed because it is too large
Load Diff
@ -1,140 +0,0 @@
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From 35cb9811b8cc2099ce11e2c86d9da6786c28a6c6 Mon Sep 17 00:00:00 2001
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From: XiaoDong Huang <derrick.huang@rock-chips.com>
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Date: Mon, 17 Jun 2024 10:55:27 +0800
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Subject: [PATCH] feat(rk3588): enable crypto function
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The CPU crypto is not default on when power up, need to enable it by
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software.
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Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
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Change-Id: Ifee2eab55d9c13cef5f15926fb80016845e2a66d
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---
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bl31/aarch64/bl31_entrypoint.S | 9 +++
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plat/rockchip/rk3588/drivers/pmu/pmu.c | 79 ++++++++++++++++++++++++++
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plat/rockchip/rk3588/platform.mk | 1 +
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3 files changed, 89 insertions(+)
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--- a/bl31/aarch64/bl31_entrypoint.S
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+++ b/bl31/aarch64/bl31_entrypoint.S
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@@ -16,6 +16,11 @@
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.globl bl31_entrypoint
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.globl bl31_warm_entrypoint
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+#ifdef PLAT_RK_BL31_ENTRYPOINT
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+ .globl plat_rockchip_bl31_entrypoint
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+ .globl plat_rockchip_bl31_entrypoint_set_sp
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+#endif
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+
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/* -----------------------------------------------------
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* bl31_entrypoint() is the cold boot entrypoint,
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* executed only by the primary cpu.
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@@ -23,6 +28,10 @@
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*/
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func bl31_entrypoint
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+#ifdef PLAT_RK_BL31_ENTRYPOINT
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+ bl plat_rockchip_bl31_entrypoint_set_sp
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+ bl plat_rockchip_bl31_entrypoint
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+#endif
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/* ---------------------------------------------------------------
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* Stash the previous bootloader arguments x0 - x3 for later use.
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* ---------------------------------------------------------------
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--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c
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+++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c
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@@ -136,6 +136,22 @@ static __pmusramfunc void dsu_restore_ea
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static __pmusramfunc void ddr_resume(void)
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{
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+ /* check the crypto function had been enabled or not */
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+ if (mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) {
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+ /* enable the crypto function */
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+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
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+ dsb();
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+ isb();
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+
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+ __asm__ volatile ("mov x0, #3\n"
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+ "dsb sy\n"
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+ "msr rmr_el3, x0\n"
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+ "1:\n"
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+ "isb\n"
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+ "wfi\n"
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+ "b 1b\n");
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+ }
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+
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dsu_restore_early();
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}
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@@ -1437,3 +1453,66 @@ void plat_rockchip_pmu_init(void)
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pm_reg_rgns_init();
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}
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+
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+void bl31_entrypoint(void);
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+
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+static uint64_t boot_cpu_save[4];
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+
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+void plat_rockchip_bl31_entrypoint_set_sp(uint64_t reg0, uint64_t reg1,
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+ uint64_t reg2, uint64_t reg3)
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+{
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+ __asm__ volatile("mov x10, %0\n" : : "r" (reg0) : );
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+
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+ reg0 = PSRAM_SP_TOP;
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+ __asm__ volatile("mov sp, %0\n" : : "r" (reg0) : );
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+
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+ __asm__ volatile("mov %0, x10\n" : "=r" (reg0) : :);
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+}
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+
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+void plat_rockchip_bl31_entrypoint(uint64_t reg0, uint64_t reg1,
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+ uint64_t reg2, uint64_t reg3)
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+{
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+ uint32_t tmp = mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4));
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+
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+ /* check the crypto function had been enabled or not */
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+ if (tmp & BIT(4)) {
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+ /* save x0~x3 */
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+ boot_cpu_save[0] = reg0;
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+ boot_cpu_save[1] = reg1;
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+ boot_cpu_save[2] = reg2;
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+ boot_cpu_save[3] = reg3;
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+
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+ /* enable the crypto function */
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+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
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+
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+ /* remap pmusram to 0xffff0000 */
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+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001);
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+ dsb();
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+ psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT;
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+ cpuson_flags[0] = PMU_CPU_HOTPLUG;
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+ cpuson_entry_point[0] = (uintptr_t)bl31_entrypoint;
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+ dsb();
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+
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+ /* to enable the crypto function, must reset the core0 */
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+ __asm__ volatile ("mov x0, #3\n"
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+ "dsb sy\n"
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+ "msr rmr_el3, x0\n"
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+ "1:\n"
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+ "isb\n"
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+ "wfi\n"
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+ "b 1b\n");
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+ } else {
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+ /* remap bootrom to 0xffff0000 */
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+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000);
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+
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+ /*
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+ * the crypto function has been enabled,
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+ * restore the x0~x3.
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+ */
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+ __asm__ volatile ("ldr x0, [%0]\n"
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+ "ldr x1, [%0 , 0x8]\n"
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+ "ldr x2, [%0 , 0x10]\n"
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+ "ldr x3, [%0 , 0x18]\n"
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+ : : "r" (&boot_cpu_save[0]));
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+ }
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+}
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--- a/plat/rockchip/rk3588/platform.mk
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+++ b/plat/rockchip/rk3588/platform.mk
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@@ -96,3 +96,4 @@ ENABLE_SPE_FOR_LOWER_ELS := 0
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$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
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$(eval $(call add_define,PLAT_SKIP_DFS_TLB_DCACHE_MAINTENANCE))
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+$(eval $(call add_define,PLAT_RK_BL31_ENTRYPOINT))
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