mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
merge ipq806x to trunk update
This commit is contained in:
coolsnowwolf
parent
e86b18615a
commit
ae33ef74dc
@ -8,56 +8,47 @@
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board_config_update
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board=$(board_name)
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boardname="${board##*,}"
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case "$board" in
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c2600)
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ucidef_set_led_usbport "usb1" "USB 1" "${board}:white:usb_2" "usb1-port1" "usb2-port1"
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ucidef_set_led_usbport "usb2" "USB 2" "${board}:white:usb_4" "usb3-port1" "usb4-port1"
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ucidef_set_led_switch "wan" "wan" "${board}:white:wan" "switch0" "0x20"
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ucidef_set_led_switch "lan" "lan" "${board}:white:lan" "switch0" "0x1e"
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;;
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d7800 |\
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r7500 |\
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r7500v2 |\
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r7800)
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ucidef_set_led_usbport "usb1" "USB 1" "${board}:white:usb1" "usb1-port1" "usb2-port1"
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ucidef_set_led_usbport "usb2" "USB 2" "${board}:white:usb2" "usb3-port1" "usb4-port1"
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ucidef_set_led_netdev "wan" "WAN" "${board}:white:wan" "eth0"
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ucidef_set_led_ide "esata" "eSATA" "${board}:white:esata"
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;;
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fritz4040)
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ucidef_set_led_wlan "wlan" "WLAN" "$board:green:wlan" "phy0tpt" "phy1tpt"
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ucidef_set_led_switch "wan" "WAN" "${board}:green:wan" "switch0" "0x20"
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ucidef_set_led_switch "lan" "LAN" "${board}:green:lan" "switch0" "0x1e"
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;;
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nbg6817)
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ucidef_set_led_wlan "wlan2g" "WLAN2G" "$board:amber:wifi2g" "phy1tpt"
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ucidef_set_led_wlan "wlan5g" "WLAN5G" "$board:amber:wifi5g" "phy0tpt"
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ucidef_set_led_netdev "wan" "WAN" "$board:white:internet" "eth1"
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;;
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rt-acrh17)
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ucidef_set_led_default "status" "STATUS" "${board}:blue:status" "1"
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ucidef_set_led_wlan "wlan2g" "WLAN2G" "${board}:blue:wlan2g" "phy0tpt"
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ucidef_set_led_wlan "wlan5g" "WLAN5G" "${board}:blue:wlan5g" "phy1tpt"
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ucidef_set_led_switch "wan" "WAN(blue)" "${board}:blue:wan" "switch0" "0x20"
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ucidef_set_led_switch "lan1" "LAN1" "${board}:blue:lan1" "switch0" "0x02"
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ucidef_set_led_switch "lan2" "LAN2" "${board}:blue:lan2" "switch0" "0x04"
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ucidef_set_led_switch "lan3" "LAN3" "${board}:blue:lan3" "switch0" "0x08"
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ucidef_set_led_switch "lan4" "LAN4" "${board}:blue:lan4" "switch0" "0x10"
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;;
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rt-ac58u)
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asus,rt-ac58u)
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ucidef_set_led_wlan "wlan2g" "WLAN2G" "$board:blue:wlan2G" "phy0tpt"
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ucidef_set_led_wlan "wlan5g" "WLAN5G" "$board:blue:wlan5G" "phy1tpt"
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ucidef_set_led_switch "wan" "WAN" "${board}:blue:wan" "switch0" "0x20"
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ucidef_set_led_usbport "usb" "USB" "${board}:blue:usb" "usb1-port1" "usb2-port1" "usb3-port1" "usb4-port1"
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ucidef_set_led_switch "lan" "LAN" "${board}:blue:lan" "switch0" "0x1e"
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;;
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vr2600v)
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ucidef_set_led_usbport "usb" "USB" "${board}:white:usb" "usb1-port1" "usb2-port1" "usb3-port1" "usb4-port1"
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ucidef_set_led_switch "lan" "lan" "${board}:white:lan" "switch0" "0x1e"
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ucidef_set_led_wlan "wlan2g" "WLAN2G" "${board}:white:wlan2g" "phy0tpt"
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ucidef_set_led_wlan "wlan5g" "WLAN5G" "${board}:white:wlan5g" "phy1tpt"
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ucidef_set_led_switch "wan" "wan" "${board}:white:wan" "switch0" "0x20"
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avm,fritzbox-4040)
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ucidef_set_led_wlan "wlan" "WLAN" "fritz4040:green:wlan" "phy0tpt" "phy1tpt"
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ucidef_set_led_netdev "wan" "WAN" "fritz4040:green:wan" "eth1"
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ucidef_set_led_switch "lan" "LAN" "fritz4040:green:lan" "switch0" "0x1e"
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;;
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netgear,d7800 |\
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netgear,r7500 |\
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netgear,r7500v2 |\
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netgear,r7800)
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ucidef_set_led_usbport "usb1" "USB 1" "${boardname}:white:usb1" "usb1-port1" "usb2-port1"
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ucidef_set_led_usbport "usb2" "USB 2" "${boardname}:white:usb2" "usb3-port1" "usb4-port1"
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ucidef_set_led_netdev "wan" "WAN" "${boardname}:white:wan" "eth0"
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ucidef_set_led_ide "esata" "eSATA" "${boardname}:white:esata"
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;;
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tplink,c2600)
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ucidef_set_led_usbport "usb1" "USB 1" "${boardname}:white:usb_2" "usb1-port1" "usb2-port1"
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ucidef_set_led_usbport "usb2" "USB 2" "${boardname}:white:usb_4" "usb3-port1" "usb4-port1"
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ucidef_set_led_switch "wan" "wan" "${boardname}:white:wan" "switch0" "0x20"
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ucidef_set_led_switch "lan" "lan" "${boardname}:white:lan" "switch0" "0x1e"
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;;
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tplink,vr2600v)
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ucidef_set_led_usbport "usb" "USB" "${boardname}:white:usb" "usb1-port1" "usb2-port1" "usb3-port1" "usb4-port1"
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ucidef_set_led_switch "lan" "lan" "${boardname}:white:lan" "switch0" "0x1e"
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ucidef_set_led_wlan "wlan2g" "WLAN2G" "${boardname}:white:wlan2g" "phy0tpt"
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ucidef_set_led_wlan "wlan5g" "WLAN5G" "${boardname}:white:wlan5g" "phy1tpt"
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ucidef_set_led_switch "wan" "wan" "${boardname}:white:wan" "switch0" "0x20"
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;;
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zyxel,nbg6817)
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ucidef_set_led_wlan "wlan2g" "WLAN2G" "${boardname}:amber:wifi2g" "phy1tpt"
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ucidef_set_led_wlan "wlan5g" "WLAN5G" "${boardname}:amber:wifi5g" "phy0tpt"
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ucidef_set_led_netdev "wan" "WAN" "${boardname}:white:internet" "eth1"
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;;
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*)
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;;
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@ -12,57 +12,7 @@ board_config_update
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board=$(board_name)
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case "$board" in
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ap148 |\
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d7800 |\
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r7500 |\
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r7500v2 |\
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r7800 |\
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vr2600v)
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ucidef_add_switch "switch0" \
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"1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0"
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;;
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c2600)
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ucidef_add_switch "switch0" \
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"1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "6@eth1" "5:wan" "0@eth0"
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;;
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db149)
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ucidef_set_interface_lan "eth1 eth2 eth3"
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ucidef_add_switch "switch0" \
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"1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "5:wan" "0u@eth0"
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;;
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ea8500)
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hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
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ucidef_add_switch "switch0" \
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"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan"
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ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
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ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
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;;
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fritz4040)
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lan_mac_addr=$(ipq40xx_get_dt_mac 0)
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wan_mac_addr=$(ipq40xx_get_dt_mac 1)
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ucidef_add_switch "switch0" \
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"0t@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan"
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ucidef_set_interface_macaddr "lan" "$lan_mac_addr"
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ucidef_set_interface_macaddr "wan" "$wan_mac_addr"
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;;
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nbg6817)
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hw_mac_addr=$(mtd_get_mac_ascii 0:APPSBLENV ethaddr)
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ucidef_add_switch "switch0" \
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"1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0"
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ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
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ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 1)"
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;;
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rt-acrh17)
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CI_UBIPART=UBI_DEV
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lan_mac_addr=$(mtd_get_mac_binary_ubi Factory 4102)
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wan_mac_addr=$(mtd_get_mac_binary_ubi Factory 36870)
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ucidef_add_switch "switch0" \
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"0t@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan"
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ucidef_set_interface_macaddr "lan" "$lan_mac_addr"
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ucidef_set_interface_macaddr "wan" "$wan_mac_addr"
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;;
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rt-ac58u)
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asus,rt-ac58u)
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CI_UBIPART=UBI_DEV
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wan_mac_addr=$(mtd_get_mac_binary_ubi Factory 20486)
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lan_mac_addr=$(mtd_get_mac_binary_ubi Factory 4102)
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@ -71,6 +21,46 @@ rt-ac58u)
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ucidef_set_interface_macaddr "lan" "$lan_mac_addr"
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ucidef_set_interface_macaddr "wan" "$wan_mac_addr"
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;;
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avm,fritzbox-4040)
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ucidef_set_interfaces_lan_wan "eth0" "eth1"
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ucidef_add_switch "switch0" \
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"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
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;;
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linksys,ea8500)
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hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
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ucidef_add_switch "switch0" \
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"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan"
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ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
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ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
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;;
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netgear,d7800 |\
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netgear,r7500 |\
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netgear,r7500v2 |\
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netgear,r7800 |\
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qcom,ipq8064-ap148 |\
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tplink,vr2600v)
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ucidef_add_switch "switch0" \
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"1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0"
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;;
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openmesh,a42)
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ucidef_set_interfaces_lan_wan "eth1" "eth0"
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;;
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qcom,ipq8064-db149)
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ucidef_set_interface_lan "eth1 eth2 eth3"
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ucidef_add_switch "switch0" \
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"1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "5:wan" "0u@eth0"
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;;
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tplink,c2600)
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ucidef_add_switch "switch0" \
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"1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "6@eth1" "5:wan" "0@eth0"
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;;
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zyxel,nbg6817)
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hw_mac_addr=$(mtd_get_mac_ascii 0:APPSBLENV ethaddr)
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ucidef_add_switch "switch0" \
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"1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0"
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ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 2)"
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ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 3)"
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;;
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*)
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echo "Unsupported hardware. Network interfaces not intialized"
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;;
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@ -2,12 +2,11 @@
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# Copyright (C) 2016 Henryk Heisig hyniu@o2.pl
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. /lib/functions/leds.sh
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. /lib/ipq806x.sh
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boot="$(ipq806x_get_dt_led boot)"
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failsafe="$(ipq806x_get_dt_led failsafe)"
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running="$(ipq806x_get_dt_led running)"
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upgrade="$(ipq806x_get_dt_led upgrade)"
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boot="$(get_dt_led boot)"
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failsafe="$(get_dt_led failsafe)"
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running="$(get_dt_led running)"
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upgrade="$(get_dt_led upgrade)"
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set_state() {
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status_led="$boot"
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@ -62,81 +62,87 @@ board=$(board_name)
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case "$FIRMWARE" in
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"ath10k/pre-cal-ahb-a000000.wifi.bin")
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case "$board" in
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rt-acrh17 |\
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rt-ac58u)
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asus,rt-ac58u)
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. /lib/upgrade/nand.sh
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CI_UBIPART=UBI_DEV
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ath10kcal_ubi_extract "Factory" 4096 12064
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;;
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fritz4040)
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avm,fritzbox-4040)
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/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
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;;
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openmesh,a42)
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ath10kcal_extract "0:ART" 4096 12064
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;;
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qcom,ap-dk01.1-c1)
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ath10kcal_extract "ART" 4096 12064
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;;
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esac
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;;
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"ath10k/pre-cal-ahb-a800000.wifi.bin")
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case "$board" in
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rt-ac58u)
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asus,rt-ac58u)
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. /lib/upgrade/nand.sh
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CI_UBIPART=UBI_DEV
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ath10kcal_ubi_extract "Factory" 20480 12064
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;;
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fritz4040)
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avm,fritzbox-4040)
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/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
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;;
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openmesh,a42)
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ath10kcal_extract "0:ART" 20480 12064
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;;
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qcom,ap-dk01.1-c1)
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ath10kcal_extract "ART" 20480 12064
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;;
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esac
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;;
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"ath10k/pre-cal-pci-0000:01:00.0.bin")
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case $board in
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rt-acrh17)
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CI_UBIPART=UBI_DEV
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. /lib/upgrade/nand.sh
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ath10kcal_ubi_extract "Factory" 36864 12064
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;;
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c2600)
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ath10kcal_extract "radio" 4096 12064
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# ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 8) -1)
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;;
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d7800 |\
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r7500v2 |\
|
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r7800)
|
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ath10kcal_extract "art" 4096 12064
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;;
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ea8500)
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linksys,ea8500)
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hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
|
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ath10kcal_extract "art" 4096 12064
|
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;;
|
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nbg6817)
|
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ath10kcal_extract "0:ART" 4096 12064
|
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netgear,d7800 |\
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netgear,r7500v2 |\
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netgear,r7800)
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ath10kcal_extract "art" 4096 12064
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;;
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vr2600v)
|
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tplink,c2600)
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ath10kcal_extract "radio" 4096 12064
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# ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 8) -1)
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;;
|
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tplink,vr2600v)
|
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ath10kcal_extract "ART" 4096 12064
|
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;;
|
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zyxel,nbg6817)
|
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ath10kcal_extract "0:ART" 4096 12064
|
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;;
|
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esac
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;;
|
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"ath10k/pre-cal-pci-0001:01:00.0.bin")
|
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case $board in
|
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c2600)
|
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ath10kcal_extract "radio" 20480 12064
|
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# ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 8) -2)
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;;
|
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d7800 |\
|
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r7500v2 |\
|
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r7800)
|
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ath10kcal_extract "art" 20480 12064
|
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;;
|
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ea8500)
|
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linksys,ea8500)
|
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hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
|
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ath10kcal_extract "art" 20480 12064
|
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;;
|
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nbg6817)
|
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ath10kcal_extract "0:ART" 20480 12064
|
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netgear,d7800 |\
|
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netgear,r7500v2 |\
|
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netgear,r7800)
|
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ath10kcal_extract "art" 20480 12064
|
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;;
|
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vr2600v)
|
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tplink,c2600)
|
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ath10kcal_extract "radio" 20480 12064
|
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# ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 8) -2)
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;;
|
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tplink,vr2600v)
|
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ath10kcal_extract "ART" 20480 12064
|
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;;
|
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zyxel,nbg6817)
|
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ath10kcal_extract "0:ART" 20480 12064
|
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;;
|
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esac
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;;
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*)
|
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|
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@ -12,20 +12,23 @@ PHYNBR=${DEVPATH##*/phy}
|
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board=$(board_name)
|
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|
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case "$board" in
|
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c2600)
|
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echo $(macaddr_add $(mtd_get_mac_binary default-mac 8) $(($PHYNBR - 1)) ) > /sys${DEVPATH}/macaddress
|
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;;
|
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d7800 |\
|
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r7500v2 |\
|
||||
r7800)
|
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echo $(macaddr_add $(mtd_get_mac_binary art 6) $(($PHYNBR + 1)) ) > /sys${DEVPATH}/macaddress
|
||||
;;
|
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ea8500)
|
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linksys,ea8500)
|
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echo $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) $(($PHYNBR + 1)) ) > /sys${DEVPATH}/macaddress
|
||||
;;
|
||||
vr2600v)
|
||||
netgear,d7800 |\
|
||||
netgear,r7500v2 |\
|
||||
netgear,r7800)
|
||||
echo $(macaddr_add $(mtd_get_mac_binary art 6) $(($PHYNBR + 1)) ) > /sys${DEVPATH}/macaddress
|
||||
;;
|
||||
tplink,c2600)
|
||||
echo $(macaddr_add $(mtd_get_mac_binary default-mac 8) $(($PHYNBR - 1)) ) > /sys${DEVPATH}/macaddress
|
||||
;;
|
||||
tplink,vr2600v)
|
||||
echo $(macaddr_add $(mtd_get_mac_binary default-mac 0) $(($PHYNBR - 1)) ) > /sys${DEVPATH}/macaddress
|
||||
;;
|
||||
zyxel,nbg6817)
|
||||
echo $(macaddr_add $(mtd_get_mac_ascii 0:APPSBLENV ethaddr) $((1 - $PHYNBR)) ) > /sys${DEVPATH}/macaddress
|
||||
;;
|
||||
*)
|
||||
;;
|
||||
esac
|
||||
|
||||
@ -6,7 +6,7 @@ boot() {
|
||||
. /lib/functions.sh
|
||||
|
||||
case $(board_name) in
|
||||
ea8500)
|
||||
linksys,ea8500)
|
||||
# make sure auto_recovery in uboot is always on
|
||||
AUTO_RECOVERY_ENA="`fw_printenv -n auto_recovery`"
|
||||
if [ "$AUTO_RECOVERY_ENA" != "yes" ] ; then
|
||||
|
||||
@ -1,79 +0,0 @@
|
||||
#!/bin/sh /etc/rc.common
|
||||
|
||||
START=99
|
||||
|
||||
set_irq_affinity() {
|
||||
local name="$1"
|
||||
local val="$2"
|
||||
|
||||
case "$name" in
|
||||
wifi0)
|
||||
local irq_wifi0=`grep -E -m1 'ath10k_ahb|qcom-pcie-msi' /proc/interrupts | cut -d: -f1 | tail -n1 | tr -d ' '`
|
||||
[ -n "$irq_wifi0" ] || echo "$name irq not found."
|
||||
echo "$val" > "/proc/irq/$irq_wifi0/smp_affinity"
|
||||
;;
|
||||
wifi1)
|
||||
local irq_wifi1=`grep -E -m2 'ath10k_ahb|qcom-pcie-msi' /proc/interrupts | cut -d: -f1 | tail -n1 | tr -d ' '`
|
||||
[ -n "$irq_wifi1" ] || echo "$name irq not found."
|
||||
echo "$val" > "/proc/irq/$irq_wifi1/smp_affinity"
|
||||
;;
|
||||
wifi2)
|
||||
local irq_wifi1=`grep -E -m3 'ath10k_ahb|qcom-pcie-msi' /proc/interrupts | cut -d: -f1 | tail -n1 | tr -d ' '`
|
||||
[ -n "$irq_wifi1" ] || echo "$name irq not found."
|
||||
echo "$val" > "/proc/irq/$irq_wifi1/smp_affinity"
|
||||
;;
|
||||
*)
|
||||
local irq=`grep -m 1 "$name" /proc/interrupts | cut -d: -f1 | sed 's, *,,'`
|
||||
[ -n "$irq" ] || echo "$name irq not found."
|
||||
echo "$val" > "/proc/irq/$irq/smp_affinity"
|
||||
;;
|
||||
esac
|
||||
}
|
||||
|
||||
start() {
|
||||
|
||||
. /lib/functions.sh
|
||||
|
||||
local board=$(board_name)
|
||||
|
||||
case "$board" in
|
||||
rt-ac58u |\
|
||||
fritz4040)
|
||||
set_irq_affinity edma_eth_tx4 2
|
||||
set_irq_affinity edma_eth_tx5 2
|
||||
set_irq_affinity edma_eth_tx6 2
|
||||
set_irq_affinity edma_eth_tx7 2
|
||||
set_irq_affinity edma_eth_rx2 2
|
||||
set_irq_affinity edma_eth_tx8 4
|
||||
set_irq_affinity edma_eth_tx9 4
|
||||
set_irq_affinity edma_eth_tx10 4
|
||||
set_irq_affinity edma_eth_tx11 4
|
||||
set_irq_affinity edma_eth_rx4 4
|
||||
set_irq_affinity edma_eth_tx12 8
|
||||
set_irq_affinity edma_eth_tx13 8
|
||||
set_irq_affinity edma_eth_tx14 8
|
||||
set_irq_affinity edma_eth_tx15 8
|
||||
set_irq_affinity edma_eth_rx6 8
|
||||
set_irq_affinity wifi0 2
|
||||
set_irq_affinity wifi1 4
|
||||
set_irq_affinity wifi2 8
|
||||
;;
|
||||
ap148 |\
|
||||
c2600 |\
|
||||
db149 |\
|
||||
d7800 |\
|
||||
ea8500 |\
|
||||
nbg6817 |\
|
||||
r7500 |\
|
||||
r7500v2 |\
|
||||
r7800 |\
|
||||
vr2600v)
|
||||
set_irq_affinity eth0 2
|
||||
set_irq_affinity eth1 2
|
||||
set_irq_affinity wifi0 2
|
||||
;;
|
||||
*)
|
||||
echo "Unsupported hardware. CPU affinity is not adjusted."
|
||||
;;
|
||||
esac
|
||||
}
|
||||
@ -1,91 +0,0 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# Copyright (c) 2014 The Linux Foundation. All rights reserved.
|
||||
# Copyright (C) 2011 OpenWrt.org
|
||||
#
|
||||
|
||||
IPQ806X_BOARD_NAME=
|
||||
IPQ806X_MODEL=
|
||||
|
||||
ipq806x_board_detect() {
|
||||
local machine
|
||||
local name
|
||||
|
||||
machine=$(cat /proc/device-tree/model)
|
||||
|
||||
case "$machine" in
|
||||
*"AP148")
|
||||
name="ap148"
|
||||
;;
|
||||
*"4040")
|
||||
name="fritz4040"
|
||||
;;
|
||||
*"C2600")
|
||||
name="c2600"
|
||||
;;
|
||||
*"D7800")
|
||||
name="d7800"
|
||||
;;
|
||||
*"DB149")
|
||||
name="db149"
|
||||
;;
|
||||
*"NBG6817")
|
||||
name="nbg6817"
|
||||
;;
|
||||
*"R7500")
|
||||
name="r7500"
|
||||
;;
|
||||
*"R7500v2")
|
||||
name="r7500v2"
|
||||
;;
|
||||
*"Linksys EA8500"*)
|
||||
name="ea8500"
|
||||
;;
|
||||
*"R7800")
|
||||
name="r7800"
|
||||
;;
|
||||
*"RT-ACRH17")
|
||||
name="rt-acrh17"
|
||||
;;
|
||||
*"RT-AC58U")
|
||||
name="rt-ac58u"
|
||||
;;
|
||||
*"VR2600v")
|
||||
name="vr2600v"
|
||||
;;
|
||||
esac
|
||||
|
||||
[ -z "$name" ] && name="unknown"
|
||||
|
||||
[ -z "$IPQ806X_BOARD_NAME" ] && IPQ806X_BOARD_NAME="$name"
|
||||
[ -z "$IPQ806X_MODEL" ] && IPQ806X_MODEL="$machine"
|
||||
|
||||
[ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
|
||||
|
||||
echo "$IPQ806X_BOARD_NAME" > /tmp/sysinfo/board_name
|
||||
echo "$IPQ806X_MODEL" > /tmp/sysinfo/model
|
||||
}
|
||||
|
||||
ipq806x_get_dt_led() {
|
||||
local label
|
||||
local ledpath
|
||||
local basepath="/proc/device-tree"
|
||||
local nodepath="$basepath/aliases/led-$1"
|
||||
|
||||
[ -f "$nodepath" ] && ledpath=$(cat "$nodepath")
|
||||
[ -n "$ledpath" ] && label=$(cat "$basepath$ledpath/label")
|
||||
|
||||
echo "$label"
|
||||
}
|
||||
|
||||
ipq40xx_get_dt_mac() {
|
||||
local mac
|
||||
local ethpath
|
||||
local basepath="/sys/firmware/devicetree/base"
|
||||
local nodepath="$basepath/aliases/ethernet$1"
|
||||
|
||||
[ -f "$nodepath" ] && ethpath=$(cat "$nodepath")
|
||||
[ -n "$ethpath" ] && mac=$(cat "$basepath$ethpath/local-mac-address")
|
||||
|
||||
echo "$mac" | hexdump -v -n 6 -e '5/1 "%02x:" 1/1 "%02x"' $part 2>/dev/null
|
||||
}
|
||||
@ -1,12 +0,0 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# Copyright (c) 2014 The Linux Foundation. All rights reserved.
|
||||
#
|
||||
|
||||
do_ipq806x() {
|
||||
. /lib/ipq806x.sh
|
||||
|
||||
ipq806x_board_detect
|
||||
}
|
||||
|
||||
boot_hook_add preinit_main do_ipq806x
|
||||
@ -1,19 +0,0 @@
|
||||
#
|
||||
# Copyright (C) 2014-2015 OpenWrt.org
|
||||
# Copyright (C) 2016 LEDE-Project.org
|
||||
#
|
||||
|
||||
preinit_set_mac_address() {
|
||||
local mac
|
||||
|
||||
. /lib/functions.sh
|
||||
|
||||
case $(board_name) in
|
||||
rt-acrh17)
|
||||
CI_UBIPART=UBI_DEV
|
||||
mac=$(mtd_get_mac_binary_ubi Factory 4102)
|
||||
ifconfig eth0 hw ether $mac 2>/dev/null
|
||||
esac
|
||||
}
|
||||
|
||||
boot_hook_add preinit_main preinit_set_mac_address
|
||||
110
target/linux/ipq806x/base-files/lib/upgrade/openmesh.sh
Normal file
110
target/linux/ipq806x/base-files/lib/upgrade/openmesh.sh
Normal file
@ -0,0 +1,110 @@
|
||||
# The U-Boot loader of the OpenMesh devices requires image sizes and
|
||||
# checksums to be provided in the U-Boot environment.
|
||||
# The OpenMesh devices come with 2 main partitions - while one is active
|
||||
# sysupgrade will flash the other. The boot order is changed to boot the
|
||||
# newly flashed partition. If the new partition can't be booted due to
|
||||
# upgrade failures the previously used partition is loaded.
|
||||
|
||||
platform_do_upgrade_openmesh() {
|
||||
local tar_file="$1"
|
||||
local restore_backup
|
||||
local primary_kernel_mtd
|
||||
|
||||
local setenv_script="/tmp/fw_env_upgrade"
|
||||
|
||||
local kernel_mtd="$(find_mtd_index $PART_NAME)"
|
||||
local kernel_offset="$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)"
|
||||
local total_size="$(cat /sys/class/mtd/mtd${kernel_mtd}/size)"
|
||||
|
||||
# detect to which flash region the new image is written to.
|
||||
#
|
||||
# 1. check what is the mtd index for the first flash region on this
|
||||
# device
|
||||
# 2. check if the target partition ("inactive") has the mtd index of
|
||||
# the first flash region
|
||||
#
|
||||
# - when it is: the new bootseq will be 1,2 and the first region is
|
||||
# modified
|
||||
# - when it isnt: bootseq will be 2,1 and the second region is
|
||||
# modified
|
||||
#
|
||||
# The detection has to be done via the hardcoded mtd partition because
|
||||
# the current boot might be done with the fallback region. Let us
|
||||
# assume that the current bootseq is 1,2. The bootloader detected that
|
||||
# the image in flash region 1 is corrupt and thus switches to flash
|
||||
# region 2. The bootseq in the u-boot-env is now still the same and
|
||||
# the sysupgrade code can now only rely on the actual mtd indexes and
|
||||
# not the bootseq variable to detect the currently booted flash
|
||||
# region/image.
|
||||
#
|
||||
# In the above example, an implementation which uses bootseq ("1,2") to
|
||||
# detect the currently booted image would assume that region 1 is booted
|
||||
# and then overwrite the variables for the wrong flash region (aka the
|
||||
# one which isn't modified). This could result in a device which doesn't
|
||||
# boot anymore to Linux until it was reflashed with ap51-flash.
|
||||
local next_boot_part="1"
|
||||
case "$(board_name)" in
|
||||
openmesh,a42)
|
||||
primary_kernel_mtd=8
|
||||
;;
|
||||
*)
|
||||
echo "failed to detect primary kernel mtd partition for board"
|
||||
return 1
|
||||
;;
|
||||
esac
|
||||
[ "$kernel_mtd" = "$primary_kernel_mtd" ] || next_boot_part="2"
|
||||
|
||||
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
|
||||
board_dir=${board_dir%/}
|
||||
|
||||
local kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c)
|
||||
local rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
|
||||
# rootfs without EOF marker
|
||||
rootfs_length=$((rootfs_length-4))
|
||||
|
||||
local kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5="${kernel_md5%% *}"
|
||||
# md5 checksum of rootfs with EOF marker
|
||||
local rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5="${rootfs_md5%% *}"
|
||||
|
||||
#
|
||||
# add tar support to get_image() to use default_do_upgrade() instead?
|
||||
#
|
||||
|
||||
# take care of restoring a saved config
|
||||
[ "$SAVE_CONFIG" -eq 1 ] && restore_backup="${MTD_CONFIG_ARGS} -j ${CONF_TAR}"
|
||||
|
||||
# write concatinated kernel + rootfs to flash
|
||||
tar xf $tar_file ${board_dir}/kernel ${board_dir}/root -O | \
|
||||
mtd $restore_backup write - $PART_NAME
|
||||
|
||||
# prepare new u-boot env
|
||||
if [ "$next_boot_part" = "1" ]; then
|
||||
echo "bootseq 1,2" > $setenv_script
|
||||
else
|
||||
echo "bootseq 2,1" > $setenv_script
|
||||
fi
|
||||
|
||||
printf "kernel_size_%i 0x%08x\n" $next_boot_part $kernel_length >> $setenv_script
|
||||
printf "vmlinux_start_addr 0x%08x\n" ${kernel_offset} >> $setenv_script
|
||||
printf "vmlinux_size 0x%08x\n" ${kernel_length} >> $setenv_script
|
||||
printf "vmlinux_checksum %s\n" ${kernel_md5} >> $setenv_script
|
||||
|
||||
printf "rootfs_size_%i 0x%08x\n" $next_boot_part $((total_size-kernel_length)) >> $setenv_script
|
||||
printf "rootfs_start_addr 0x%08x\n" $((kernel_offset+kernel_length)) >> $setenv_script
|
||||
printf "rootfs_size 0x%08x\n" ${rootfs_length} >> $setenv_script
|
||||
printf "rootfs_checksum %s\n" ${rootfs_md5} >> $setenv_script
|
||||
|
||||
# store u-boot env changes
|
||||
fw_setenv -s $setenv_script || {
|
||||
echo "failed to update U-Boot environment"
|
||||
return 1
|
||||
}
|
||||
}
|
||||
|
||||
# create /var/lock for the lock "fw_setenv.lock" of fw_setenv
|
||||
# the rest is copied using ipq806x's RAMFS_COPY_BIN and RAMFS_COPY_DATA
|
||||
platform_add_ramfs_ubootenv()
|
||||
{
|
||||
mkdir -p $RAM_ROOT/var/lock
|
||||
}
|
||||
append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv
|
||||
@ -8,7 +8,6 @@ platform_check_image() {
|
||||
local board=$(board_name)
|
||||
|
||||
case "$board" in
|
||||
rt-acrh17 |\
|
||||
rt-ac58u)
|
||||
CI_UBIPART="UBI_DEV"
|
||||
local ubidev=$(nand_find_ubi $CI_UBIPART)
|
||||
@ -34,43 +33,37 @@ EOF
|
||||
|
||||
platform_do_upgrade() {
|
||||
case "$(board_name)" in
|
||||
rt-acrh17)
|
||||
asus,rt-ac58u)
|
||||
CI_UBIPART="UBI_DEV"
|
||||
CI_KERNPART="linux"
|
||||
local ubidev=$(nand_find_ubi $CI_UBIPART)
|
||||
local jffs2=$(nand_find_volume $ubidev jffs2)
|
||||
local linux2=$(nand_find_volume $ubidev linux2)
|
||||
[ -n "$jffs2" ] && ubirmvol /dev/$ubidev --name=jffs2
|
||||
[ -n "$linux2" ] && ubirmvol /dev/$ubidev --name=linux2
|
||||
nand_do_upgrade "$1"
|
||||
;;
|
||||
ap148 |\
|
||||
ap-dk04.1-c1 |\
|
||||
d7800 |\
|
||||
nbg6817 |\
|
||||
r7500 |\
|
||||
r7500v2 |\
|
||||
r7800)
|
||||
linksys,ea8500)
|
||||
platform_do_upgrade_linksys "$ARGV"
|
||||
;;
|
||||
netgear,d7800 |\
|
||||
netgear,r7500 |\
|
||||
netgear,r7500v2 |\
|
||||
netgear,r7800 |\
|
||||
qcom,ap-dk04.1-c1 |\
|
||||
qcom,ipq8064-ap148 |\
|
||||
zyxel,nbg6817)
|
||||
nand_do_upgrade "$ARGV"
|
||||
;;
|
||||
c2600)
|
||||
openmesh,a42)
|
||||
PART_NAME="inactive"
|
||||
platform_do_upgrade_openmesh "$ARGV"
|
||||
;;
|
||||
tplink,c2600)
|
||||
PART_NAME="os-image:rootfs"
|
||||
MTD_CONFIG_ARGS="-s 0x200000"
|
||||
default_do_upgrade "$ARGV"
|
||||
;;
|
||||
ea8500)
|
||||
platform_do_upgrade_linksys "$ARGV"
|
||||
;;
|
||||
vr2600v)
|
||||
tplink,vr2600v)
|
||||
PART_NAME="kernel:rootfs"
|
||||
MTD_CONFIG_ARGS="-s 0x200000"
|
||||
default_do_upgrade "$ARGV"
|
||||
;;
|
||||
rt-ac58u)
|
||||
CI_UBIPART="UBI_DEV"
|
||||
CI_KERNPART="linux"
|
||||
nand_do_upgrade "$1"
|
||||
;;
|
||||
*)
|
||||
default_do_upgrade "$ARGV"
|
||||
;;
|
||||
@ -79,13 +72,13 @@ platform_do_upgrade() {
|
||||
|
||||
platform_nand_pre_upgrade() {
|
||||
case "$(board_name)" in
|
||||
nbg6817)
|
||||
zyxel_do_upgrade "$1"
|
||||
;;
|
||||
rt-ac58u)
|
||||
asus,rt-ac58u)
|
||||
CI_UBIPART="UBI_DEV"
|
||||
CI_KERNPART="linux"
|
||||
;;
|
||||
zyxel,nbg6817)
|
||||
zyxel_do_upgrade "$1"
|
||||
;;
|
||||
esac
|
||||
}
|
||||
|
||||
|
||||
@ -19,9 +19,8 @@ zyxel_get_rootfs() {
|
||||
|
||||
zyxel_do_flash() {
|
||||
local tar_file=$1
|
||||
local board=$2
|
||||
local kernel=$3
|
||||
local rootfs=$4
|
||||
local kernel=$2
|
||||
local rootfs=$3
|
||||
|
||||
# keep sure its unbound
|
||||
losetup --detach-all || {
|
||||
@ -29,14 +28,18 @@ zyxel_do_flash() {
|
||||
reboot -f
|
||||
}
|
||||
|
||||
# use the first found directory in the tar archive
|
||||
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
|
||||
board_dir=${board_dir%/}
|
||||
|
||||
echo "flashing kernel to /dev/${kernel}"
|
||||
tar xf $tar_file sysupgrade-$board/kernel -O >/dev/$kernel
|
||||
tar xf $tar_file ${board_dir}/kernel -O >/dev/$kernel
|
||||
|
||||
echo "flashing rootfs to ${rootfs}"
|
||||
tar xf $tar_file sysupgrade-$board/root -O >"${rootfs}"
|
||||
tar xf $tar_file ${board_dir}/root -O >"${rootfs}"
|
||||
|
||||
# a padded rootfs is needed for overlay fs creation
|
||||
local offset=$(tar xf $tar_file sysupgrade-$board/root -O | wc -c)
|
||||
local offset=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
|
||||
[ $offset -lt 65536 ] && {
|
||||
echo Wrong size for rootfs: $offset
|
||||
sleep 10
|
||||
@ -74,14 +77,25 @@ zyxel_do_upgrade() {
|
||||
|
||||
[ -b "${rootfs}" ] || return 1
|
||||
case "$board" in
|
||||
nbg6817)
|
||||
kernel=mmcblk0p4
|
||||
zyxel,nbg6817)
|
||||
case "$rootfs" in
|
||||
"/dev/mmcblk0p5")
|
||||
kernel=mmcblk0p4
|
||||
;;
|
||||
"/dev/mmcblk0p8")
|
||||
kernel=mmcblk0p7
|
||||
;;
|
||||
*)
|
||||
return 1
|
||||
;;
|
||||
esac
|
||||
;;
|
||||
*)
|
||||
return 1
|
||||
;;
|
||||
esac
|
||||
|
||||
zyxel_do_flash $tar_file $board $kernel $rootfs
|
||||
zyxel_do_flash $tar_file $kernel $rootfs
|
||||
|
||||
return 0
|
||||
}
|
||||
|
||||
@ -477,7 +477,7 @@ CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
# CONFIG_USB_EHCI_HCD is not set
|
||||
# CONFIG_USB_IPQ4019_PHY is not set
|
||||
CONFIG_USB_IPQ4019_PHY=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
# CONFIG_USB_UHCI_HCD is not set
|
||||
CONFIG_USE_OF=y
|
||||
|
||||
@ -1,501 +0,0 @@
|
||||
#include "qcom-ipq8064-v1.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "TP-Link Archer C2600";
|
||||
compatible = "tplink,c2600", "qcom,ipq8064";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0x1e000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power;
|
||||
led-failsafe = &general;
|
||||
led-running = &power;
|
||||
led-upgrade = &general;
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio16", "gpio54", "gpio65";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33",
|
||||
"gpio53", "gpio66";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "gpio18", "gpio19";
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
cs {
|
||||
pins = "gpio20";
|
||||
function = "gpio";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clk {
|
||||
pins = "gpio21";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usb0_pwr_en_pin: usb0_pwr_en_pin {
|
||||
mux {
|
||||
pins = "gpio25";
|
||||
function = "gpio";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
usb1_pwr_en_pin: usb1_pwr_en_pin {
|
||||
mux {
|
||||
pins = "gpio23";
|
||||
function = "gpio";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
gsbi5: gsbi@1a200000 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "ok";
|
||||
|
||||
spi5: spi@1a280000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
SBL1@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x0 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
MIBIB@20000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x20000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SBL2@40000 {
|
||||
label = "SBL2";
|
||||
reg = <0x40000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SBL3@60000 {
|
||||
label = "SBL3";
|
||||
reg = <0x60000 0x30000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
DDRCONFIG@90000 {
|
||||
label = "DDRCONFIG";
|
||||
reg = <0x90000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SSD@a0000 {
|
||||
label = "SSD";
|
||||
reg = <0xa0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
TZ@b0000 {
|
||||
label = "TZ";
|
||||
reg = <0xb0000 0x30000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
RPM@e0000 {
|
||||
label = "RPM";
|
||||
reg = <0xe0000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
fs-uboot@100000 {
|
||||
label = "fs-uboot";
|
||||
reg = <0x100000 0x70000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
uboot-env@170000 {
|
||||
label = "uboot-env";
|
||||
reg = <0x170000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
radio@1b0000 {
|
||||
label = "radio";
|
||||
reg = <0x1b0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
os-image@1f0000 {
|
||||
label = "os-image";
|
||||
reg = <0x1f0000 0x200000>;
|
||||
};
|
||||
|
||||
rootfs@3f0000 {
|
||||
label = "rootfs";
|
||||
reg = <0x3f0000 0x1b00000>;
|
||||
};
|
||||
|
||||
defaultmac: default-mac@1ef0000 {
|
||||
label = "default-mac";
|
||||
reg = <0x1ef0000 0x00200>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
pin@1ef0200 {
|
||||
label = "pin";
|
||||
reg = <0x1ef0200 0x00200>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
product-info@1ef0400 {
|
||||
label = "product-info";
|
||||
reg = <0x1ef0400 0x0fc00>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition-table@1f00000 {
|
||||
label = "partition-table";
|
||||
reg = <0x1f00000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
soft-version@1f10000 {
|
||||
label = "soft-version";
|
||||
reg = <0x1f10000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
support-list@1f20000 {
|
||||
label = "support-list";
|
||||
reg = <0x1f20000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
profile@1f30000 {
|
||||
label = "profile";
|
||||
reg = <0x1f30000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
default-config@1f40000 {
|
||||
label = "default-config";
|
||||
reg = <0x1f40000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
user-config@1f50000 {
|
||||
label = "user-config";
|
||||
reg = <0x1f50000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
qos-db@1f90000 {
|
||||
label = "qos-db";
|
||||
reg = <0x1f90000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
usb-config@1fd0000 {
|
||||
label = "usb-config";
|
||||
reg = <0x1fd0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
log@1fe0000 {
|
||||
label = "log";
|
||||
reg = <0x1fe0000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@0 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb0_pwr_en_pin>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb1_pwr_en_pin>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@37200000 {
|
||||
status = "ok";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <1>;
|
||||
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mtd-mac-address = <&defaultmac 0x8>;
|
||||
mtd-mac-address-increment = <1>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
gmac2: ethernet@37400000 {
|
||||
status = "ok";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
|
||||
mtd-mac-address = <&defaultmac 0x8>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
ledswitch {
|
||||
label = "ledswitch";
|
||||
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_LIGHTS_TOGGLE>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
lan {
|
||||
label = "c2600:white:lan";
|
||||
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb4 {
|
||||
label = "c2600:white:usb_4";
|
||||
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb2 {
|
||||
label = "c2600:white:usb_2";
|
||||
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "c2600:white:wps";
|
||||
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_amber {
|
||||
label = "c2600:amber:wan";
|
||||
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wan_white {
|
||||
label = "c2600:white:wan";
|
||||
gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power: power {
|
||||
label = "c2600:white:power";
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
general: general {
|
||||
label = "c2600:white:general";
|
||||
gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "ok";
|
||||
};
|
||||
@ -1,406 +0,0 @@
|
||||
#include "qcom-ipq8064-v1.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Netgear Nighthawk X4 D7800";
|
||||
compatible = "netgear,d7800", "qcom,ipq8064";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0xe000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power_white;
|
||||
led-failsafe = &power_amber;
|
||||
led-running = &power_white;
|
||||
led-upgrade = &power_amber;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "rootfstype=squashfs noinitrd";
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio54", "gpio65";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
|
||||
"gpio24","gpio26", "gpio53", "gpio64";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
mux {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38", "gpio39",
|
||||
"gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
bias-pull-up;
|
||||
};
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usb0_pwr_en_pins: usb0_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio15";
|
||||
function = "gpio";
|
||||
drive-strength = <12>;
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
usb1_pwr_en_pins: usb1_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio16", "gpio68";
|
||||
function = "gpio";
|
||||
drive-strength = <12>;
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
sata-phy@1b400000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
sata@29000000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@0 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb0_pwr_en_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb1_pwr_en_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&pcie0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
qcadata@0 {
|
||||
label = "qcadata";
|
||||
reg = <0x0000000 0x0c80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL@c80000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x0c80000 0x0500000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBLENV@1180000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x1180000 0x0080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
art: art@1200000 {
|
||||
label = "art";
|
||||
reg = <0x1200000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
artbak: art@1340000 {
|
||||
label = "artbak";
|
||||
reg = <0x1340000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@1480000 {
|
||||
label = "kernel";
|
||||
reg = <0x1480000 0x0200000>;
|
||||
};
|
||||
|
||||
ubi@1680000 {
|
||||
label = "ubi";
|
||||
reg = <0x1680000 0x1E00000>;
|
||||
};
|
||||
|
||||
netgear@3480000 {
|
||||
label = "netgear";
|
||||
reg = <0x3480000 0x4480000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
reserve@7900000 {
|
||||
label = "reserve";
|
||||
reg = <0x7900000 0x0700000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
firmware@1480000 {
|
||||
label = "firmware";
|
||||
reg = <0x1480000 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@37200000 {
|
||||
status = "ok";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy4>;
|
||||
qcom,id = <1>;
|
||||
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mtd-mac-address = <&art 6>;
|
||||
};
|
||||
|
||||
gmac2: ethernet@37400000 {
|
||||
status = "ok";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
|
||||
mtd-mac-address = <&art 0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
usb1 {
|
||||
label = "d7800:white:usb1";
|
||||
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb2 {
|
||||
label = "d7800:white:usb2";
|
||||
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power_amber: power_amber {
|
||||
label = "d7800:amber:power";
|
||||
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_white {
|
||||
label = "d7800:white:wan";
|
||||
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_amber {
|
||||
label = "d7800:amber:wan";
|
||||
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "d7800:white:wps";
|
||||
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
esata {
|
||||
label = "d7800:white:esata";
|
||||
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power_white: power_white {
|
||||
label = "d7800:white:power";
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "d7800:white:wifi";
|
||||
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "ok";
|
||||
};
|
||||
@ -1,399 +0,0 @@
|
||||
#include "qcom-ipq8064-v1.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Linksys EA8500 WiFi Router";
|
||||
compatible = "linksys,ea8500", "qcom,ipq8064";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0x1e000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyMSM0,115200n8";
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
append-rootblock = "ubi.mtd="; /* append to bootargs adding the root deviceblock nbr from bootloader */
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio65", "gpio67", "gpio68";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio53", "gpio54";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
mux {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38", "gpio39",
|
||||
"gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
bias-pull-up;
|
||||
};
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
sata-phy@1b400000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
sata@29000000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie2: pci@1b900000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
SBL1@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x0000000 0x0040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
MIBIB@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x0040000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SBL2@180000 {
|
||||
label = "SBL2";
|
||||
reg = <0x0180000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SBL3@2c0000 {
|
||||
label = "SBL3";
|
||||
reg = <0x02c0000 0x0280000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
DDRCONFIG@540000 {
|
||||
label = "DDRCONFIG";
|
||||
reg = <0x0540000 0x0120000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SSD@660000 {
|
||||
label = "SSD";
|
||||
reg = <0x0660000 0x0120000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
TZ@780000 {
|
||||
label = "TZ";
|
||||
reg = <0x0780000 0x0280000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
RPM@a00000 {
|
||||
label = "RPM";
|
||||
reg = <0x0a00000 0x0280000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
art: art@c80000 {
|
||||
label = "art";
|
||||
reg = <0x0c80000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL@dc0000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x0dc0000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
u_env@ec0000 {
|
||||
label = "u_env";
|
||||
reg = <0x0ec0000 0x0040000>;
|
||||
};
|
||||
|
||||
s_env@f00000 {
|
||||
label = "s_env";
|
||||
reg = <0x0f00000 0x0040000>;
|
||||
};
|
||||
|
||||
devinfo@f40000 {
|
||||
label = "devinfo";
|
||||
reg = <0x0f40000 0x0040000>;
|
||||
};
|
||||
|
||||
linux@f80000 {
|
||||
label = "kernel1";
|
||||
reg = <0x0f80000 0x2800000>; /* 3 MB spill to rootfs*/
|
||||
};
|
||||
|
||||
rootfs@1280000 {
|
||||
label = "rootfs1";
|
||||
reg = <0x1280000 0x2500000>;
|
||||
};
|
||||
|
||||
linux2@3780000 {
|
||||
label = "kernel2";
|
||||
reg = <0x3780000 0x2800000>;
|
||||
};
|
||||
|
||||
rootfs2@3a80000 {
|
||||
label = "rootfs2";
|
||||
reg = <0x3a80000 0x2500000>;
|
||||
};
|
||||
|
||||
syscfg@5f80000 {
|
||||
label = "syscfg";
|
||||
reg = <0x5f80000 0x2080000>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@37200000 {
|
||||
status = "ok";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <1>;
|
||||
qcom,phy_mdio_addr = <4>;
|
||||
qcom,poll_required = <1>;
|
||||
qcom,rgmii_delay = <0>;
|
||||
qcom,emulation = <0>;
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
//lan
|
||||
gmac2: ethernet@37400000 {
|
||||
status = "ok";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
qcom,phy_mdio_addr = <0>; /* none */
|
||||
qcom,poll_required = <0>; /* no polling */
|
||||
qcom,rgmii_delay = <0>;
|
||||
qcom,emulation = <0>;
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
adm_dma: dma@18300000 {
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART >;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wps {
|
||||
label = "ea8500:green:wps";
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power: power {
|
||||
label = "ea8500:white:power";
|
||||
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "ea8500:green:wifi";
|
||||
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,373 +0,0 @@
|
||||
#include "qcom-ipq8064-v1.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Netgear Nighthawk X4 R7500";
|
||||
compatible = "netgear,r7500", "qcom,ipq8064";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0xe000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power_white;
|
||||
led-failsafe = &power_amber;
|
||||
led-running = &power_white;
|
||||
led-upgrade = &power_amber;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "rootfstype=squashfs noinitrd";
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio54", "gpio65";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
|
||||
"gpio24","gpio26", "gpio53", "gpio64";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
mux {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38", "gpio39",
|
||||
"gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
bias-pull-up;
|
||||
};
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
sata-phy@1b400000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
sata@29000000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
qcadata@0 {
|
||||
label = "qcadata";
|
||||
reg = <0x0000000 0x0c80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL@c80000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x0c80000 0x0500000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBLENV@1180000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x1180000 0x0080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
art: art@1200000 {
|
||||
label = "art";
|
||||
reg = <0x1200000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@1340000 {
|
||||
label = "kernel";
|
||||
reg = <0x1340000 0x0200000>;
|
||||
};
|
||||
|
||||
ubi@1540000 {
|
||||
label = "ubi";
|
||||
reg = <0x1540000 0x1800000>;
|
||||
};
|
||||
|
||||
netgear@2d40000 {
|
||||
label = "netgear";
|
||||
reg = <0x2d40000 0x0c00000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
reserve@3940000 {
|
||||
label = "reserve";
|
||||
reg = <0x3940000 0x46c0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
firmware@1340000 {
|
||||
label = "firmware";
|
||||
reg = <0x1340000 0x1a00000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@37200000 {
|
||||
status = "ok";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <1>;
|
||||
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mtd-mac-address = <&art 6>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
gmac2: ethernet@37400000 {
|
||||
status = "ok";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
|
||||
mtd-mac-address = <&art 0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
usb1 {
|
||||
label = "r7500:white:usb1";
|
||||
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb2 {
|
||||
label = "r7500:white:usb2";
|
||||
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power_amber: power_amber {
|
||||
label = "r7500:amber:power";
|
||||
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_white {
|
||||
label = "r7500:white:wan";
|
||||
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_amber {
|
||||
label = "r7500:amber:wan";
|
||||
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "r7500:white:wps";
|
||||
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
esata {
|
||||
label = "r7500:white:esata";
|
||||
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power_white: power_white {
|
||||
label = "r7500:white:power";
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "r7500:white:wifi";
|
||||
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "ok";
|
||||
};
|
||||
@ -1,416 +0,0 @@
|
||||
#include "qcom-ipq8064-v1.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Netgear Nighthawk X4 R7500v2";
|
||||
compatible = "netgear,r7500v2", "qcom,ipq8064";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0x1e000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rsvd@5fe00000 {
|
||||
reg = <0x5fe00000 0x200000>;
|
||||
reusable;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "rootfstype=squashfs noinitrd";
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio54", "gpio65";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
|
||||
"gpio24","gpio26", "gpio53", "gpio64";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
mux {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38", "gpio39",
|
||||
"gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
bias-pull-up;
|
||||
};
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usb0_pwr_en_pins: usb0_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio15";
|
||||
function = "gpio";
|
||||
drive-strength = <12>;
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
usb1_pwr_en_pins: usb1_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio16", "gpio68";
|
||||
function = "gpio";
|
||||
drive-strength = <12>;
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
sata-phy@1b400000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
sata@29000000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@0 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb0_pwr_en_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb1_pwr_en_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
qcadata@0 {
|
||||
label = "qcadata";
|
||||
reg = <0x0000000 0x0c80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL@c80000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x0c80000 0x0500000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBLENV@1180000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x1180000 0x0080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
art: art@1200000 {
|
||||
label = "art";
|
||||
reg = <0x1200000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
artbak: art@1340000 {
|
||||
label = "artbak";
|
||||
reg = <0x1340000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@1480000 {
|
||||
label = "kernel";
|
||||
reg = <0x1480000 0x0200000>;
|
||||
};
|
||||
|
||||
ubi@1680000 {
|
||||
label = "ubi";
|
||||
reg = <0x1680000 0x1E00000>;
|
||||
};
|
||||
|
||||
netgear@3480000 {
|
||||
label = "netgear";
|
||||
reg = <0x3480000 0x4480000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
reserve@7900000 {
|
||||
label = "reserve";
|
||||
reg = <0x7900000 0x0700000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
firmware@1480000 {
|
||||
label = "firmware";
|
||||
reg = <0x1480000 0x2000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x000e4 0xaa545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@37200000 {
|
||||
status = "ok";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <1>;
|
||||
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mtd-mac-address = <&art 6>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
gmac2: ethernet@37400000 {
|
||||
status = "ok";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
|
||||
mtd-mac-address = <&art 0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
usb1 {
|
||||
label = "r7500v2:amber:usb1";
|
||||
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb3 {
|
||||
label = "r7500v2:amber:usb3";
|
||||
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
status {
|
||||
label = "r7500v2:amber:status";
|
||||
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
internet {
|
||||
label = "r7500v2:white:internet";
|
||||
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan {
|
||||
label = "r7500v2:white:wan";
|
||||
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "r7500v2:white:wps";
|
||||
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
esata {
|
||||
label = "r7500v2:white:esata";
|
||||
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power: power {
|
||||
label = "r7500v2:white:power";
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "r7500v2:white:wifi";
|
||||
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "ok";
|
||||
};
|
||||
@ -1,425 +0,0 @@
|
||||
#include "qcom-ipq8064-v1.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "TP-Link Archer VR2600v";
|
||||
compatible = "tplink,vr2600v", "qcom,ipq8064";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0x1e000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power;
|
||||
led-failsafe = &general;
|
||||
led-running = &power;
|
||||
led-upgrade = &general;
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17",
|
||||
"gpio26", "gpio53", "gpio56", "gpio66";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "gpio18", "gpio19";
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
cs {
|
||||
pins = "gpio20";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clk {
|
||||
pins = "gpio21";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
gsbi5: gsbi@1a200000 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "ok";
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash: W25Q128@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
SBL1@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x0 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
MIBIB@20000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x20000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SBL2@40000 {
|
||||
label = "SBL2";
|
||||
reg = <0x40000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SBL3@80000 {
|
||||
label = "SBL3";
|
||||
reg = <0x80000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
DDRCONFIG@100000 {
|
||||
label = "DDRCONFIG";
|
||||
reg = <0x100000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SSD@110000 {
|
||||
label = "SSD";
|
||||
reg = <0x110000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
TZ@120000 {
|
||||
label = "TZ";
|
||||
reg = <0x120000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
RPM@1a0000 {
|
||||
label = "RPM";
|
||||
reg = <0x1a0000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL@220000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x220000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBLENV@2a0000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x2a0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
OLDART@2e0000 {
|
||||
label = "OLDART";
|
||||
reg = <0x2e0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@320000 {
|
||||
label = "kernel";
|
||||
reg = <0x320000 0x200000>;
|
||||
};
|
||||
|
||||
rootfs@520000 {
|
||||
label = "rootfs";
|
||||
reg = <0x520000 0xa60000>;
|
||||
};
|
||||
|
||||
defaultmac: default-mac@0xfaf100 {
|
||||
label = "default-mac";
|
||||
reg = <0xfaf100 0x00200>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
ART@fc0000 {
|
||||
label = "ART";
|
||||
reg = <0xfc0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@37200000 {
|
||||
status = "ok";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <1>;
|
||||
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mtd-mac-address = <&defaultmac 0>;
|
||||
mtd-mac-address-increment = <1>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
gmac2: ethernet@37400000 {
|
||||
status = "ok";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
|
||||
mtd-mac-address = <&defaultmac 0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
dect {
|
||||
label = "dect";
|
||||
gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_PHONE>;
|
||||
};
|
||||
|
||||
ledswitch {
|
||||
label = "ledswitch";
|
||||
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_LIGHTS_TOGGLE>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
dsl {
|
||||
label = "vr2600v:white:dsl";
|
||||
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb {
|
||||
label = "vr2600v:white:usb";
|
||||
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
lan {
|
||||
label = "vr2600v:white:lan";
|
||||
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2g {
|
||||
label = "vr2600v:white:wlan2g";
|
||||
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan5g {
|
||||
label = "vr2600v:white:wlan5g";
|
||||
gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power: power {
|
||||
label = "vr2600v:white:power";
|
||||
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
phone {
|
||||
label = "vr2600v:white:phone";
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan {
|
||||
label = "vr2600v:white:wan";
|
||||
gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
general: general {
|
||||
label = "vr2600v:white:general";
|
||||
gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "ok";
|
||||
};
|
||||
@ -1,388 +0,0 @@
|
||||
#include "qcom-ipq8065-v1.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "ZyXEL NBG6817";
|
||||
compatible = "zyxel,nbg6817", "qcom,ipq8065";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0x1e000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
mdio-gpio0 = &mdio0;
|
||||
sdcc1 = &sdcc1;
|
||||
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/mmcblk0p5 rootfstype=squashfs,ext4 rootwait noinitrd";
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio54", "gpio65";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio9", "gpio26", "gpio33", "gpio64";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
clk {
|
||||
pins = "gpio1";
|
||||
input-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
|
||||
input-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
drive-strength = <10>;
|
||||
bias-none;
|
||||
};
|
||||
|
||||
cs {
|
||||
pins = "gpio20";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0_pwr_en_pins: usb0_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
function = "gpio";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
pwr {
|
||||
pins = "gpio17";
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
|
||||
ovc {
|
||||
pins = "gpio16";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usb1_pwr_en_pins: usb1_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio14", "gpio15";
|
||||
function = "gpio";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
pwr {
|
||||
pins = "gpio14";
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
|
||||
ovc {
|
||||
pins = "gpio15";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
gsbi5: gsbi@1a200000 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "ok";
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <51200000>;
|
||||
reg = <0>;
|
||||
|
||||
linux,part-probe = "qcom-smem";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@0 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb0_pwr_en_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb1_pwr_en_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x000e4 0xaa545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
0x00970 0x1e864443 /* QM_PORT0_CTRL0 */
|
||||
0x00974 0x000001c6 /* QM_PORT0_CTRL1 */
|
||||
0x00978 0x19008643 /* QM_PORT1_CTRL0 */
|
||||
0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */
|
||||
0x00980 0x19008643 /* QM_PORT2_CTRL0 */
|
||||
0x00984 0x000001c6 /* QM_PORT2_CTRL1 */
|
||||
0x00988 0x19008643 /* QM_PORT3_CTRL0 */
|
||||
0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */
|
||||
0x00990 0x19008643 /* QM_PORT4_CTRL0 */
|
||||
0x00994 0x000001c6 /* QM_PORT4_CTRL1 */
|
||||
0x00998 0x1e864443 /* QM_PORT5_CTRL0 */
|
||||
0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */
|
||||
0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */
|
||||
0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */
|
||||
>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <4>;
|
||||
qca,ar8327-initvals = <
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@37200000 {
|
||||
status = "ok";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <1>;
|
||||
qcom,phy_mdio_addr = <4>;
|
||||
qcom,poll_required = <0>;
|
||||
qcom,rgmii_delay = <1>;
|
||||
qcom,phy_mii_type = <0>;
|
||||
qcom,emulation = <0>;
|
||||
qcom,irq = <255>;
|
||||
mdiobus = <&mdio0>;
|
||||
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
gmac2: ethernet@37400000 {
|
||||
status = "ok";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
qcom,phy_mdio_addr = <0>; /* none */
|
||||
qcom,poll_required = <0>; /* no polling */
|
||||
qcom,rgmii_delay = <0>;
|
||||
qcom,phy_mii_type = <1>;
|
||||
qcom,emulation = <0>;
|
||||
qcom,irq = <258>;
|
||||
mdiobus = <&mdio0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
amba {
|
||||
sdcc1: sdcc@12400000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
internet {
|
||||
label = "nbg6817:white:internet";
|
||||
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power: power {
|
||||
label = "nbg6817:white:power";
|
||||
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
wifi2g {
|
||||
label = "nbg6817:amber:wifi2g";
|
||||
gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* wifi2g amber from the manual is missing */
|
||||
|
||||
wifi5g {
|
||||
label = "nbg6817:amber:wifi5g";
|
||||
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* wifi5g amber from the manual is missing */
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "ok";
|
||||
};
|
||||
@ -1,566 +0,0 @@
|
||||
#include "qcom-ipq8065-v1.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Netgear Nighthawk X4S R7800";
|
||||
compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0x1e000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rsvd@5fe00000 {
|
||||
reg = <0x5fe00000 0x200000>;
|
||||
reusable;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power_white;
|
||||
led-failsafe = &power_amber;
|
||||
led-running = &power_white;
|
||||
led-upgrade = &power_amber;
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio54", "gpio65";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
|
||||
"gpio24","gpio26", "gpio53", "gpio64";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
mux {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38", "gpio39",
|
||||
"gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
bias-pull-up;
|
||||
};
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
clk {
|
||||
pins = "gpio1";
|
||||
input-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
|
||||
input-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "gpio18", "gpio19";
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
cs {
|
||||
pins = "gpio20";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clk {
|
||||
pins = "gpio21";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
spi6_pins: spi6_pins {
|
||||
mux {
|
||||
pins = "gpio55", "gpio56", "gpio58";
|
||||
function = "gsbi6";
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
mosi {
|
||||
pins = "gpio55";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
miso {
|
||||
pins = "gpio56";
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
cs {
|
||||
pins = "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clk {
|
||||
pins = "gpio58";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
reset {
|
||||
pins = "gpio33";
|
||||
drive-strength = <10>;
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
usb0_pwr_en_pins: usb0_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio15";
|
||||
function = "gpio";
|
||||
drive-strength = <12>;
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
usb1_pwr_en_pins: usb1_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio16", "gpio68";
|
||||
function = "gpio";
|
||||
drive-strength = <12>;
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
gsbi5: gsbi@1a200000 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "ok";
|
||||
|
||||
spi5: spi@1a280000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
linux,part-probe = "qcom-smem";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi6: gsbi@16500000 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "ok";
|
||||
spi6: spi@16580000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&spi6_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
spi-nor@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <6000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sata-phy@1b400000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
sata@29000000 {
|
||||
ports-implemented = <0x1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@0 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb0_pwr_en_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&usb1_pwr_en_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-bus-width = <8>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
qcadata@0 {
|
||||
label = "qcadata";
|
||||
reg = <0x0000000 0x0c80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL@c80000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x0c80000 0x0500000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBLENV@1180000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x1180000 0x0080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
art: art@1200000 {
|
||||
label = "art";
|
||||
reg = <0x1200000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
artbak: art@1340000 {
|
||||
label = "artbak";
|
||||
reg = <0x1340000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@1480000 {
|
||||
label = "kernel";
|
||||
reg = <0x1480000 0x0200000>;
|
||||
};
|
||||
|
||||
ubi@1680000 {
|
||||
label = "ubi";
|
||||
reg = <0x1680000 0x1E00000>;
|
||||
};
|
||||
|
||||
netgear@3480000 {
|
||||
label = "netgear";
|
||||
reg = <0x3480000 0x4480000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
reserve@7900000 {
|
||||
label = "reserve";
|
||||
reg = <0x7900000 0x0700000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
firmware@1480000 {
|
||||
label = "firmware";
|
||||
reg = <0x1480000 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x000e4 0xaa545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
0x00970 0x1e864443 /* QM_PORT0_CTRL0 */
|
||||
0x00974 0x000001c6 /* QM_PORT0_CTRL1 */
|
||||
0x00978 0x19008643 /* QM_PORT1_CTRL0 */
|
||||
0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */
|
||||
0x00980 0x19008643 /* QM_PORT2_CTRL0 */
|
||||
0x00984 0x000001c6 /* QM_PORT2_CTRL1 */
|
||||
0x00988 0x19008643 /* QM_PORT3_CTRL0 */
|
||||
0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */
|
||||
0x00990 0x19008643 /* QM_PORT4_CTRL0 */
|
||||
0x00994 0x000001c6 /* QM_PORT4_CTRL1 */
|
||||
0x00998 0x1e864443 /* QM_PORT5_CTRL0 */
|
||||
0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */
|
||||
0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */
|
||||
0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */
|
||||
>;
|
||||
qca,ar8327-vlans = <
|
||||
0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */
|
||||
0x2 0x21 /* VLAN2 Ports 0/5 */
|
||||
>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <4>;
|
||||
qca,ar8327-initvals = <
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@37200000 {
|
||||
status = "ok";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <1>;
|
||||
qcom,phy_mdio_addr = <4>;
|
||||
qcom,poll_required = <0>;
|
||||
qcom,rgmii_delay = <1>;
|
||||
qcom,phy_mii_type = <0>;
|
||||
qcom,emulation = <0>;
|
||||
qcom,irq = <255>;
|
||||
mdiobus = <&mdio0>;
|
||||
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mtd-mac-address = <&art 6>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
gmac2: ethernet@37400000 {
|
||||
status = "ok";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
qcom,phy_mdio_addr = <0>; /* none */
|
||||
qcom,poll_required = <0>; /* no polling */
|
||||
qcom,rgmii_delay = <0>;
|
||||
qcom,phy_mii_type = <1>;
|
||||
qcom,emulation = <0>;
|
||||
qcom,irq = <258>;
|
||||
mdiobus = <&mdio0>;
|
||||
|
||||
mtd-mac-address = <&art 0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
debounce-interval = <60>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <60>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
debounce-interval = <60>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power_white: power_white {
|
||||
label = "r7800:white:power";
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
power_amber: power_amber {
|
||||
label = "r7800:amber:power";
|
||||
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_white {
|
||||
label = "r7800:white:wan";
|
||||
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_amber {
|
||||
label = "r7800:amber:wan";
|
||||
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb1 {
|
||||
label = "r7800:white:usb1";
|
||||
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb2 {
|
||||
label = "r7800:white:usb2";
|
||||
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
esata {
|
||||
label = "r7800:white:esata";
|
||||
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "r7800:white:wifi";
|
||||
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "r7800:white:wps";
|
||||
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "ok";
|
||||
};
|
||||
@ -1 +0,0 @@
|
||||
#include "qcom-ipq8065.dtsi"
|
||||
@ -1,153 +0,0 @@
|
||||
#include "qcom-ipq8064.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm IPQ8065";
|
||||
compatible = "qcom,ipq8065", "qcom,ipq8064";
|
||||
|
||||
qcom,pvs {
|
||||
qcom,pvs-format-a;
|
||||
qcom,speed0-pvs0-bin-v0 =
|
||||
< 1725000000 1262500 >,
|
||||
< 1400000000 1175000 >,
|
||||
< 1000000000 1100000 >,
|
||||
< 800000000 1050000 >,
|
||||
< 600000000 1000000 >,
|
||||
< 384000000 975000 >;
|
||||
qcom,speed0-pvs1-bin-v0 =
|
||||
< 1725000000 1225000 >,
|
||||
< 1400000000 1150000 >,
|
||||
< 1000000000 1075000 >,
|
||||
< 800000000 1025000 >,
|
||||
< 600000000 975000 >,
|
||||
< 384000000 950000 >;
|
||||
qcom,speed0-pvs2-bin-v0 =
|
||||
< 1725000000 1200000 >,
|
||||
< 1400000000 1125000 >,
|
||||
< 1000000000 1050000 >,
|
||||
< 800000000 1000000 >,
|
||||
< 600000000 950000 >,
|
||||
< 384000000 925000 >;
|
||||
qcom,speed0-pvs3-bin-v0 =
|
||||
< 1725000000 1175000 >,
|
||||
< 1400000000 1100000 >,
|
||||
< 1000000000 1025000 >,
|
||||
< 800000000 975000 >,
|
||||
< 600000000 925000 >,
|
||||
< 384000000 900000 >;
|
||||
qcom,speed0-pvs4-bin-v0 =
|
||||
< 1725000000 1150000 >,
|
||||
< 1400000000 1075000 >,
|
||||
< 1000000000 1000000 >,
|
||||
< 800000000 950000 >,
|
||||
< 600000000 900000 >,
|
||||
< 384000000 875000 >;
|
||||
qcom,speed0-pvs5-bin-v0 =
|
||||
< 1725000000 1100000 >,
|
||||
< 1400000000 1025000 >,
|
||||
< 1000000000 950000 >,
|
||||
< 800000000 900000 >,
|
||||
< 600000000 850000 >,
|
||||
< 384000000 825000 >;
|
||||
qcom,speed0-pvs6-bin-v0 =
|
||||
< 1725000000 1050000 >,
|
||||
< 1400000000 975000 >,
|
||||
< 1000000000 900000 >,
|
||||
< 800000000 850000 >,
|
||||
< 600000000 800000 >,
|
||||
< 384000000 775000 >;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
|
||||
rpm@108000 {
|
||||
|
||||
regulators {
|
||||
|
||||
smb208_s2a: s2a {
|
||||
regulator-min-microvolt = <775000>;
|
||||
regulator-max-microvolt = <1275000>;
|
||||
};
|
||||
|
||||
smb208_s2b: s2b {
|
||||
regulator-min-microvolt = <775000>;
|
||||
regulator-max-microvolt = <1275000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Temporary fixed regulator */
|
||||
vsdcc_fixed: vsdcc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "SDCC Power";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sdcc1bam:dma@12402000 {
|
||||
compatible = "qcom,bam-v1.3.0";
|
||||
reg = <0x12402000 0x8000>;
|
||||
interrupts = <0 98 0>;
|
||||
clocks = <&gcc SDC1_H_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
sdcc3bam:dma@12182000 {
|
||||
compatible = "qcom,bam-v1.3.0";
|
||||
reg = <0x12182000 0x8000>;
|
||||
interrupts = <0 96 0>;
|
||||
clocks = <&gcc SDC3_H_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
sdcc1: sdcc@12400000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
reg = <0x12400000 0x2000>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cmd_irq";
|
||||
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
bus-width = <8>;
|
||||
max-frequency = <96000000>;
|
||||
non-removable;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
vmmc-supply = <&vsdcc_fixed>;
|
||||
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
sdcc3: sdcc@12180000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
status = "disabled";
|
||||
reg = <0x12180000 0x2000>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cmd_irq";
|
||||
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
bus-width = <8>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <192000000>;
|
||||
#mmc-ddr-1_8v;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
vqmmc-supply = <&vsdcc_fixed>;
|
||||
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,4 +1,5 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
@ -14,27 +15,15 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019-ap.dk01.1.dtsi"
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include "qcom-ipq4019-bus.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "ZyXEL NBG6617";
|
||||
compatible = "zyxel,nbg6617", "qcom,ipq4019";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
model = "OpenMesh A42";
|
||||
compatible = "openmesh,a42", "qcom,ipq4019";
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <0x1>;
|
||||
@ -42,7 +31,7 @@
|
||||
ranges;
|
||||
|
||||
rsvd1@87000000 {
|
||||
reg = <0x87000000 0x0500000>;
|
||||
reg = <0x87000000 0x500000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
@ -58,17 +47,6 @@
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl@0x01000000 {
|
||||
led_pinmux {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
|
||||
drive-strength = <0x8>;
|
||||
bias-pull-up;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
@ -83,7 +61,6 @@
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
@ -96,9 +73,83 @@
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
counter@4a1000 {
|
||||
compatible = "qcom,qca-gcnt";
|
||||
reg = <0x4a1000 0x4>;
|
||||
pinctrl@1000000 {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
pinmux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
};
|
||||
pinmux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
pinconf_cs {
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
blsp_dma: dma@7884000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
spi_0: spi@78b5000 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
cs-gpios = <&tlmm 54 0>;
|
||||
|
||||
m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
/* partitions are passed via bootloader */
|
||||
};
|
||||
};
|
||||
|
||||
serial@78af000 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
cryptobam: dma@8e04000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb2_hs_phy: hsphy@a8000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb2: usb2@60f8800 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
mdio@90000 {
|
||||
@ -119,90 +170,75 @@
|
||||
|
||||
wifi@a000000 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "OM-A42";
|
||||
};
|
||||
|
||||
wifi@a800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
cryptobam: dma@8e04000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "OM-A42";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wlan {
|
||||
label = "wlan";
|
||||
gpios = <&tlmm 0x2 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 0x3f GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 0x4 GPIO_ACTIVE_LOW>;
|
||||
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power: power {
|
||||
label = "nbg6617:green:power";
|
||||
gpios = <&tlmm 0x3 GPIO_ACTIVE_HIGH>;
|
||||
red {
|
||||
label = "a42:red:status";
|
||||
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "nbg6617:green:wps";
|
||||
gpios = <&tlmm 0x1 GPIO_ACTIVE_HIGH>;
|
||||
power: green {
|
||||
label = "a42:green:status";
|
||||
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2G {
|
||||
label = "nbg6617:green:wlan2G";
|
||||
gpios = <&tlmm 0x3a GPIO_ACTIVE_HIGH>;
|
||||
blue {
|
||||
label = "a42:blue:status";
|
||||
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
};
|
||||
|
||||
wlan5G {
|
||||
label = "nbg6617:green:wlan5G";
|
||||
gpios = <&tlmm 0x5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
watchdog {
|
||||
compatible = "linux,wdt-gpio";
|
||||
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
|
||||
hw_algo = "toggle";
|
||||
/* hw_margin_ms is actually 300s but driver limits it to 60s */
|
||||
hw_margin_ms = <60000>;
|
||||
always-running;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&spi_0 { /* BLSP1 QUP1 */
|
||||
status = "ok";
|
||||
|
||||
mx25l25635e@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
n25q128a11@0 {
|
||||
status = "okay";
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition0@0 {
|
||||
label = "all";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
read-only; /* for now */
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
&gmac0 {
|
||||
qcom,phy_mdio_addr = <4>;
|
||||
qcom,poll_required = <1>;
|
||||
qcom,forced_speed = <1000>;
|
||||
qcom,forced_duplex = <1>;
|
||||
vlan_tag = <2 0x20>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
qcom,phy_mdio_addr = <3>;
|
||||
qcom,poll_required = <1>;
|
||||
qcom,forced_speed = <1000>;
|
||||
qcom,forced_duplex = <1>;
|
||||
vlan_tag = <1 0x10>;
|
||||
};
|
||||
@ -14,7 +14,7 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019-ap.dk01.1.dtsi"
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include "qcom-ipq4019-bus.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
@ -24,48 +24,53 @@
|
||||
model = "AVM FRITZ!Box 4040";
|
||||
compatible = "avm,fritzbox-4040", "qcom,ipq4019";
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
ranges;
|
||||
|
||||
rsvd1@87000000 {
|
||||
reg = <0x87000000 0x500000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wifi_dump@87500000 {
|
||||
reg = <0x87500000 0x600000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rsvd2@87B00000 {
|
||||
reg = <0x87b00000 0x500000>;
|
||||
no-map;
|
||||
};
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &flash;
|
||||
led-running = &power;
|
||||
led-upgrade = &flash;
|
||||
};
|
||||
/*
|
||||
This also works. Maybe it could be smaller still.
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
ranges;
|
||||
|
||||
rsvd1@87E00000 {
|
||||
reg = <0x87e00000 0x200000>;
|
||||
tz_apps@87b80000 {
|
||||
reg = <0x87b80000 0x280000>;
|
||||
reusable;
|
||||
};
|
||||
|
||||
smem@87e00000 {
|
||||
reg = <0x87e00000 0x080000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
tz@87e80000 {
|
||||
reg = <0x87e80000 0x180000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
*/
|
||||
|
||||
soc {
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
@ -74,28 +79,42 @@
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
counter@4a1000 {
|
||||
compatible = "qcom,qca-gcnt";
|
||||
reg = <0x4a1000 0x4>;
|
||||
usb2@60f8800 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
mdio@90000 {
|
||||
serial@78af000 {
|
||||
pinctrl-0 = <&serial_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
wifi@a000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wifi@a800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
qca8075: ess-switch@c000000 {
|
||||
status = "okay";
|
||||
|
||||
@ -105,34 +124,14 @@
|
||||
enable-usb-power {
|
||||
gpio-hog;
|
||||
line-name = "enable USB3 power";
|
||||
gpios = <0x7 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <7 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wifi@a000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wifi@a800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
cryptobam: dma@8e04000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
@ -140,7 +139,7 @@
|
||||
|
||||
wlan {
|
||||
label = "wlan";
|
||||
gpios = <&tlmm 0x3a GPIO_ACTIVE_LOW>;
|
||||
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
@ -151,58 +150,85 @@
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &flash;
|
||||
led-running = &power;
|
||||
led-upgrade = &flash;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
wlan {
|
||||
label = "fritz4040:green:wlan";
|
||||
gpios = <&qca8075 0x1 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&qca8075 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
panic: info_red {
|
||||
label = "fritz4040:red:info";
|
||||
gpios = <&qca8075 0x3 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&qca8075 3 GPIO_ACTIVE_HIGH>;
|
||||
panic-indicator;
|
||||
};
|
||||
|
||||
wan {
|
||||
label = "fritz4040:green:wan";
|
||||
gpios = <&qca8075 0x5 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&qca8075 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power: power {
|
||||
label = "fritz4040:green:power";
|
||||
gpios = <&qca8075 0xb GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&qca8075 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
lan {
|
||||
label = "fritz4040:green:lan";
|
||||
gpios = <&qca8075 0xd GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&qca8075 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
flash: info_amber {
|
||||
label = "fritz4040:amber:info";
|
||||
gpios = <&qca8075 0xf GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&qca8075 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi_0 { /* BLSP1 QUP1 */
|
||||
status = "ok";
|
||||
|
||||
mx25l25635e@0 {
|
||||
status = "disabled";
|
||||
&tlmm {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "blsp_uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0_pins: spi_0_pinmux {
|
||||
mux {
|
||||
function = "blsp_spi0";
|
||||
pins = "gpio55", "gpio56", "gpio57";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux_cs {
|
||||
function = "gpio";
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi_0 { /* BLSP1 QUP1 */
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
cs-gpios = <&tlmm 54 0>;
|
||||
|
||||
mx25l25635f@0 {
|
||||
compatible = "mx25l25635f", "jedec,spi-nor";
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
@ -273,12 +299,24 @@
|
||||
};
|
||||
partition11@2A0000 {
|
||||
label = "firmware";
|
||||
reg = <0x002A0000 0x01C60000>;
|
||||
reg = <0x002a0000 0x01c60000>;
|
||||
};
|
||||
partition12@1f00000 {
|
||||
label = "jffs2";
|
||||
reg = <0x01F00000 0x00100000>;
|
||||
reg = <0x01f00000 0x00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
@ -18,7 +18,6 @@
|
||||
#include "qcom-ipq4019-bus.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "ASUS RT-AC58U";
|
||||
@ -47,73 +46,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
counter@4a1000 {
|
||||
compatible = "qcom,qca-gcnt";
|
||||
reg = <0x4a1000 0x4>;
|
||||
};
|
||||
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wifi@a000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wifi@a800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
cryptobam: dma@8e04000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
@ -178,16 +110,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&spi_0 { /* BLSP1 QUP1 */
|
||||
status = "ok";
|
||||
cs-gpios = <&tlmm 54 0>,
|
||||
<&tlmm 59 0>;
|
||||
|
||||
mx25l25635e@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -1,291 +0,0 @@
|
||||
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019-ap.dk04.1.dtsi"
|
||||
#include "qcom-ipq4019-bus.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "ASUS RT-ACRH17";
|
||||
compatible = "asus,rt-acrh17", "qcom,ipq4019";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
led-boot = &power;
|
||||
led-failsafe = &power;
|
||||
led-running = &power;
|
||||
led-upgrade = &power;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
ranges;
|
||||
|
||||
rsvd1@87E00000 {
|
||||
reg = <0x87e00000 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
spi_0: spi@78b5000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0: qcom,pcie@80000 {
|
||||
compatible = "qcom,msm_pcie";
|
||||
cell-index = <0>;
|
||||
qcom,ctrl-amt = <1>;
|
||||
|
||||
reg = <0x80000 0x2000>,
|
||||
<0x99000 0x800>,
|
||||
<0x40000000 0xf1d>,
|
||||
<0x40000f20 0xa8>,
|
||||
<0x40100000 0x1000>,
|
||||
<0x40200000 0x100000>,
|
||||
<0x40300000 0xd00000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi",
|
||||
"conf", "io", "bars";
|
||||
|
||||
#address-cells = <0>;
|
||||
interrupt-parent = <&pcie0>;
|
||||
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
interrupt-map = <0 &intc 0 141 0
|
||||
1 &intc 0 142 0
|
||||
2 &intc 0 143 0
|
||||
3 &intc 0 144 0
|
||||
4 &intc 0 145 0
|
||||
5 &intc 0 146 0
|
||||
6 &intc 0 147 0
|
||||
7 &intc 0 148 0
|
||||
8 &intc 0 149 0
|
||||
9 &intc 0 150 0
|
||||
10 &intc 0 151 0
|
||||
11 &intc 0 152 0 >;
|
||||
|
||||
interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
|
||||
"int_pls_pme", "int_pme_legacy", "int_pls_err",
|
||||
"int_aer_legacy", "int_pls_link_up",
|
||||
"int_pls_link_down", "int_bridge_flush_n","int_wake";
|
||||
|
||||
qcom,ep-latency = <10>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE_AXI_S_CLK>;
|
||||
|
||||
clock-names = "pcie_0_cfg_ahb_clk",
|
||||
"pcie_0_mstr_axi_clk",
|
||||
"pcie_0_slv_axi_clk";
|
||||
|
||||
max-clock-frequency-hz = <0>, <0>, <0>;
|
||||
|
||||
resets = <&gcc PCIE_AXI_M_ARES>,
|
||||
<&gcc PCIE_AXI_S_ARES>,
|
||||
<&gcc PCIE_PIPE_ARES>,
|
||||
<&gcc PCIE_AXI_M_VMIDMT_ARES>,
|
||||
<&gcc PCIE_AXI_S_XPU_ARES>,
|
||||
<&gcc PCIE_PARF_XPU_ARES>,
|
||||
<&gcc PCIE_PHY_ARES>,
|
||||
<&gcc PCIE_AXI_M_STICKY_ARES>,
|
||||
<&gcc PCIE_PIPE_STICKY_ARES>,
|
||||
<&gcc PCIE_PWR_ARES>,
|
||||
<&gcc PCIE_AHB_ARES>,
|
||||
<&gcc PCIE_PHY_AHB_ARES>;
|
||||
|
||||
reset-names = "pcie_rst_axi_m_ares",
|
||||
"pcie_rst_axi_s_ares",
|
||||
"pcie_rst_pipe_ares",
|
||||
"pcie_rst_axi_m_vmidmt_ares",
|
||||
"pcie_rst_axi_s_xpu_ares",
|
||||
"pcie_rst_parf_xpu_ares",
|
||||
"pcie_rst_phy_ares",
|
||||
"pcie_rst_axi_m_sticky_ares",
|
||||
"pcie_rst_pipe_sticky_ares",
|
||||
"pcie_rst_pwr_ares",
|
||||
"pcie_rst_ahb_res",
|
||||
"pcie_rst_phy_ahb_ares";
|
||||
|
||||
status = "ok";
|
||||
perst-gpio = <&tlmm 38 0>;
|
||||
wake-gpio = <&tlmm 50 0>;
|
||||
clkreq-gpio = <&tlmm 39 0>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
/* select hostmode */
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wifi0: wifi@a000000 {
|
||||
status = "ok";
|
||||
core-id = <0x0>;
|
||||
qca,msi_addr = <0x0b006040>;
|
||||
qca,msi_base = <0x40>;
|
||||
wifi_led_num = <2>; /* Wifi 2G */
|
||||
wifi_led_source = <0>; /* source id 0 */
|
||||
qcom,mtd-name = "0:ART";
|
||||
qcom,cal-offset = <0x1000>;
|
||||
qcom,cal-len = <12064>;
|
||||
};
|
||||
|
||||
wifi1: wifi@a800000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power: status {
|
||||
label = "rt-acrh17:blue:status";
|
||||
gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan1 {
|
||||
label = "rt-acrh17:blue:lan1";
|
||||
gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan2 {
|
||||
label = "rt-acrh17:blue:lan2";
|
||||
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan3 {
|
||||
label = "rt-acrh17:blue:lan3";
|
||||
gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan4 {
|
||||
label = "rt-acrh17:blue:lan4";
|
||||
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wan_blue {
|
||||
label = "rt-acrh17:blue:wan";
|
||||
gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan_red {
|
||||
label = "rt-acrh17:red:wan";
|
||||
gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wlan2g {
|
||||
label = "rt-acrh17:blue:wlan2g";
|
||||
gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan5g {
|
||||
label = "rt-acrh17:blue:wlan5g";
|
||||
gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nand_pins {
|
||||
pullups {
|
||||
pins = "gpio53", "gpio58",
|
||||
"gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio55", "gpio56",
|
||||
"gpio57", "gpio60",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_0_pins {
|
||||
pinmux {
|
||||
function = "blsp_i2c0";
|
||||
pins = "gpio10";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio10";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
@ -161,12 +161,11 @@
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
|
||||
@ -346,12 +346,11 @@
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
|
||||
@ -193,6 +193,7 @@
|
||||
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
pinctrl-names = "default";
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
|
||||
@ -157,19 +157,17 @@
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
|
||||
pcie2: pci@1b900000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
|
||||
nand@1ac00000 {
|
||||
status = "ok";
|
||||
|
||||
|
||||
@ -168,6 +168,7 @@
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
|
||||
@ -198,6 +198,7 @@
|
||||
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
pinctrl-names = "default";
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
|
||||
@ -259,12 +259,11 @@
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
|
||||
@ -1,448 +0,0 @@
|
||||
#include "qcom-ipq8064-v1.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Buffalo WXR-2533DHP";
|
||||
compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0x1e000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power_white;
|
||||
led-failsafe = &power_orange;
|
||||
led-running = &power_white;
|
||||
led-upgrade = &power_orange;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyMSM0,115200n8 ubi.mtd=0 ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs";
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
drive-strength = <10>;
|
||||
bias-none;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
mux {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38", "gpio39",
|
||||
"gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
bias-pull-up;
|
||||
};
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22", "gpio23",
|
||||
"gpio24", "gpio25", "gpio26", "gpio53";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio54", "gpio65";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs0 {
|
||||
reg = <0>;
|
||||
compatible = "qcom,nandcs";
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
rootfs@0000000 {
|
||||
label = "rootfs";
|
||||
reg = <0x0000000 0x4000000>;
|
||||
};
|
||||
|
||||
rootfs_1@4000000 {
|
||||
label = "rootfs_1";
|
||||
reg = <0x4000000 0x4000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
|
||||
uart4: serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
gsbi5: gsbi@1a200000 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "ok";
|
||||
|
||||
spi5: spi@1a280000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
SBL1@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x0 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
MIBIB@10000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x10000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SBL2@30000 {
|
||||
label = "SBL2";
|
||||
reg = <0x30000 0x30000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SBL3@60000 {
|
||||
label = "SBL3";
|
||||
reg = <0x60000 0x30000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
DDRCONFIG@90000 {
|
||||
label = "DDRCONFIG";
|
||||
reg = <0x90000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
SSD@a0000 {
|
||||
label = "SSD";
|
||||
reg = <0xa0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
TZ@b0000 {
|
||||
label = "TZ";
|
||||
reg = <0xb0000 0x30000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
RPM@e0000 {
|
||||
label = "RPM";
|
||||
reg = <0xe0000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL@100000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x100000 0x70000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBLENV@170000 {
|
||||
label = "APPSBLENV";
|
||||
reg = <0x170000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
ART: ART@180000 {
|
||||
label = "ART";
|
||||
reg = <0x180000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
BOOTCONFIG@1c0000 {
|
||||
label = "OLDART";
|
||||
reg = <0x1c0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
APPSBL_1@1d0000 {
|
||||
label = "APPSBL_1";
|
||||
reg = <0x1d0000 0x70000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "virtual,mdio-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@37200000 {
|
||||
status = "ok";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <1>;
|
||||
qcom,phy_mdio_addr = <4>;
|
||||
qcom,poll_required = <1>;
|
||||
qcom,rgmii_delay = <0>;
|
||||
qcom,emulation = <0>;
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
mtd-mac-address = <&ART 6>;
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
//lan
|
||||
gmac2: ethernet@37400000 {
|
||||
status = "ok";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
qcom,phy_mdio_addr = <0>; /* none */
|
||||
qcom,poll_required = <0>; /* no polling */
|
||||
qcom,rgmii_delay = <0>;
|
||||
qcom,emulation = <0>;
|
||||
mtd-mac-address = <&ART 0>;
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
aoss {
|
||||
label = "aoss";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power_white: power_white {
|
||||
label = "wxr-2533dhp:white:power";
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
power_orange: power_orange {
|
||||
label = "wxr-2533dhp:orange:power";
|
||||
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
wireless_white: wireless_white {
|
||||
label = "wxr-2533dhp:white:wireless";
|
||||
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wireless_orange: wireless_orange {
|
||||
label = "wxr-2533dhp:orange:wireless";
|
||||
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
internet_white: internet_white {
|
||||
label = "wxr-2533dhp:white:internet";
|
||||
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
internet_orange: internet_orange {
|
||||
label = "wxr-2533dhp:orange:internet";
|
||||
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
router_white: router_white {
|
||||
label = "wxr-2533dhp:white:router";
|
||||
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
router_orange: router_orange {
|
||||
label = "wxr-2533dhp:orange:router";
|
||||
gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb_green: usb_green {
|
||||
label = "wxr-2533dhp:green:usb";
|
||||
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
guest_green: guest_green {
|
||||
label = "wxr-2533dhp:green:guest";
|
||||
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "ok";
|
||||
};
|
||||
@ -967,6 +967,9 @@
|
||||
|
||||
ranges;
|
||||
|
||||
resets = <&gcc USB30_0_MASTER_RESET>;
|
||||
reset-names = "usb30_0_mstr_rst";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
dwc3@11000000 {
|
||||
@ -989,6 +992,9 @@
|
||||
|
||||
ranges;
|
||||
|
||||
resets = <&gcc USB30_1_MASTER_RESET>;
|
||||
reset-names = "usb30_1_mstr_rst";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
dwc3@10000000 {
|
||||
@ -1051,6 +1057,8 @@
|
||||
|
||||
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
phy-tx0-term-offset = <7>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1103,6 +1111,8 @@
|
||||
|
||||
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
||||
|
||||
phy-tx0-term-offset = <7>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1155,6 +1165,8 @@
|
||||
|
||||
perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
|
||||
|
||||
phy-tx0-term-offset = <7>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -33,15 +33,16 @@
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/mmcblk0p5 rootfstype=squashfs,ext4 rootwait noinitrd";
|
||||
bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd";
|
||||
linux,stdout-path = "serial0:115200n8";
|
||||
append-rootblock = "root=/dev/mmcblk0p";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio54", "gpio65";
|
||||
pins = "gpio53", "gpio54", "gpio65";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
@ -228,6 +229,7 @@
|
||||
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
pinctrl-names = "default";
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
mdio0: mdio {
|
||||
@ -334,8 +336,9 @@
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RFKILL>;
|
||||
linux,input-type = <EV_SW>;
|
||||
};
|
||||
|
||||
reset {
|
||||
|
||||
@ -299,12 +299,11 @@
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
|
||||
@ -75,6 +75,17 @@
|
||||
};
|
||||
};
|
||||
|
||||
ss_phy_0: phy@110f8830 {
|
||||
rx_eq = <2>;
|
||||
tx_deamp_3_5db = <32>;
|
||||
mpll = <0xa0>;
|
||||
};
|
||||
ss_phy_1: phy@100f8830 {
|
||||
rx_eq = <2>;
|
||||
tx_deamp_3_5db = <32>;
|
||||
mpll = <0xa0>;
|
||||
};
|
||||
|
||||
/* Temporary fixed regulator */
|
||||
vsdcc_fixed: vsdcc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
@ -3,34 +3,15 @@
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
UBIFS_OPTS = -m 2048 -e 124KiB -c 4096 -U -F
|
||||
|
||||
define Image/Prepare
|
||||
$(CP) $(LINUX_DIR)/vmlinux $(KDIR)/$(IMG_PREFIX)-vmlinux.elf
|
||||
endef
|
||||
|
||||
define Image/BuildKernel
|
||||
$(CP) $(KDIR)/$(IMG_PREFIX)-vmlinux.elf $(BIN_DIR)
|
||||
endef
|
||||
|
||||
define Image/Build/squashfs
|
||||
cp $(KDIR)/root.squashfs $(KDIR)/root.squashfs-raw
|
||||
$(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
|
||||
endef
|
||||
|
||||
define Image/Build
|
||||
$(call Image/Build/$(1),$(1))
|
||||
dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-root.img bs=2k conv=sync
|
||||
endef
|
||||
|
||||
define Device/Default
|
||||
PROFILES := Default
|
||||
KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
|
||||
KERNEL_INITRAMFS_PREFIX := $$(IMG_PREFIX)-$(1)-initramfs
|
||||
KERNEL_PREFIX := $$(IMAGE_PREFIX)
|
||||
KERNEL_LOADADDR = 0x42208000
|
||||
SUPPORTED_DEVICES = $$(BOARD_NAME)
|
||||
IMAGE/sysupgrade.tar = sysupgrade-tar | append-metadata
|
||||
SUPPORTED_DEVICES := $(subst _,$(comma),$(1))
|
||||
IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata
|
||||
IMAGE/sysupgrade.bin/squashfs :=
|
||||
endef
|
||||
|
||||
define Device/LegacyImage
|
||||
@ -53,29 +34,25 @@ endef
|
||||
|
||||
define Device/UbiFit
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGES := nand-factory.ubi nand-sysupgrade.tar
|
||||
IMAGES := nand-factory.ubi nand-sysupgrade.bin
|
||||
IMAGE/nand-factory.ubi := append-ubi
|
||||
IMAGE/nand-sysupgrade.tar := sysupgrade-tar | append-metadata
|
||||
IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
|
||||
define Device/DniImage
|
||||
PROFILES += $$(DEVICE_NAME)
|
||||
FILESYSTEMS := squashfs
|
||||
KERNEL_SUFFIX := -uImage
|
||||
KERNEL = kernel-bin | append-dtb | uImage none
|
||||
KERNEL_NAME := zImage
|
||||
NETGEAR_BOARD_ID :=
|
||||
NETGEAR_HW_ID :=
|
||||
UBINIZE_OPTS := -E 5
|
||||
IMAGES := factory.img sysupgrade.tar
|
||||
IMAGES := factory.img sysupgrade.bin
|
||||
IMAGE/factory.img := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakeroot-hdr | pad-to $$$$(KERNEL_SIZE) | append-ubi | netgear-dni
|
||||
IMAGE/sysupgrade.tar := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakeroot-hdr | sysupgrade-tar kernel=$$$$@ | append-metadata
|
||||
IMAGE/sysupgrade.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakeroot-hdr | sysupgrade-tar kernel=$$$$@ | append-metadata
|
||||
endef
|
||||
DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
|
||||
|
||||
define Device/TpSafeImage
|
||||
PROFILES += $$(DEVICE_NAME)
|
||||
FILESYSTEMS := squashfs
|
||||
KERNEL_SUFFIX := -uImage
|
||||
KERNEL = kernel-bin | append-dtb | uImage none
|
||||
KERNEL_NAME := zImage
|
||||
@ -87,91 +64,16 @@ endef
|
||||
DEVICE_VARS += TPLINK_BOARD_ID
|
||||
|
||||
define Device/ZyXELImage
|
||||
PROFILES += $$(DEVICE_NAME)
|
||||
FILESYSTEMS := squashfs
|
||||
KERNEL_SUFFIX := -uImage
|
||||
KERNEL = kernel-bin | append-dtb | uImage none | pad-to $${KERNEL_SIZE}
|
||||
KERNEL_NAME := zImage
|
||||
IMAGES := sysupgrade.tar mmcblk0p5-rootfs.bin mmcblk0p4-kernel.bin
|
||||
IMAGE/sysupgrade.tar/squashfs := append-rootfs | pad-to $$$${BLOCKSIZE} | sysupgrade-tar rootfs=$$$$@ | append-metadata
|
||||
IMAGES := sysupgrade.bin mmcblk0p5-rootfs.bin mmcblk0p4-kernel.bin
|
||||
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to $$$${BLOCKSIZE} | sysupgrade-tar rootfs=$$$$@ | append-metadata
|
||||
IMAGE/mmcblk0p5-rootfs.bin := append-rootfs | pad-rootfs | pad-to $$$${BLOCKSIZE}
|
||||
IMAGE/mmcblk0p4-kernel.bin := append-kernel
|
||||
endef
|
||||
|
||||
define Device/AP148
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_DTS := qcom-ipq8064-ap148
|
||||
KERNEL_INSTALL := 1
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := ap148
|
||||
DEVICE_TITLE := Qualcomm AP148
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
|
||||
define Device/AP148-legacy
|
||||
$(call Device/LegacyImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_DTS := qcom-ipq8064-ap148
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := ap148
|
||||
DEVICE_TITLE := Qualcomm AP148 (legacy)
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
|
||||
define Device/C2600
|
||||
$(call Device/TpSafeImage)
|
||||
DEVICE_DTS := qcom-ipq8064-c2600
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := c2600
|
||||
TPLINK_BOARD_ID := C2600
|
||||
DEVICE_TITLE := TP-Link Archer C2600
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
|
||||
define Device/D7800
|
||||
$(call Device/DniImage)
|
||||
DEVICE_DTS := qcom-ipq8064-d7800
|
||||
KERNEL_SIZE := 2097152
|
||||
NETGEAR_BOARD_ID := D7800
|
||||
NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := d7800
|
||||
DEVICE_TITLE := Netgear Nighthawk X4 D7800
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
|
||||
define Device/DB149
|
||||
$(call Device/FitImage)
|
||||
DEVICE_DTS := qcom-ipq8064-db149
|
||||
KERNEL_INSTALL := 1
|
||||
BOARD_NAME := db149
|
||||
DEVICE_TITLE := Qualcomm DB149
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
|
||||
define Device/EA8500
|
||||
$(call Device/LegacyImage)
|
||||
DEVICE_DTS := qcom-ipq8064-ea8500
|
||||
PAGESIZE := 2048
|
||||
BLOCKSIZE := 128k
|
||||
KERNEL_SIZE := 3072k
|
||||
FILESYSTEMS := squashfs
|
||||
KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakeroot-hdr
|
||||
PROFILES += $$(DEVICE_NAME)
|
||||
BOARD_NAME := ea8500
|
||||
UBINIZE_OPTS := -E 5
|
||||
IMAGES := factory.bin sysupgrade.tar
|
||||
IMAGE/factory.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-ubi
|
||||
DEVICE_TITLE := Linksys EA8500
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
|
||||
define Device/FRITZ4040
|
||||
define Device/avm_fritzbox-4040
|
||||
$(call Device/FitImageLzma)
|
||||
DEVICE_DTS := qcom-ipq4019-fritz4040
|
||||
KERNEL_LOADADDR := 0x80208000
|
||||
@ -181,12 +83,44 @@ define Device/FRITZ4040
|
||||
DEVICE_TITLE := AVM Fritz!Box 4040
|
||||
IMAGE_SIZE := 29753344
|
||||
IMAGES = sysupgrade.bin
|
||||
FILESYSTEMS := squashfs
|
||||
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-phy-qcom-ipq4019 ipq-wifi-fritz4040 fritz-tffs fritz-caldata u-boot-fritz4040
|
||||
DEVICE_PACKAGES := ipq-wifi-avm_fritzbox-4040 fritz-tffs fritz-caldata u-boot-fritz4040
|
||||
endef
|
||||
TARGET_DEVICES += avm_fritzbox-4040
|
||||
|
||||
define Device/R7500
|
||||
define Device/linksys_ea8500
|
||||
$(call Device/LegacyImage)
|
||||
DEVICE_DTS := qcom-ipq8064-ea8500
|
||||
PAGESIZE := 2048
|
||||
BLOCKSIZE := 128k
|
||||
KERNEL_SIZE := 3072k
|
||||
KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakeroot-hdr
|
||||
BOARD_NAME := ea8500
|
||||
SUPPORTED_DEVICES += ea8500
|
||||
UBINIZE_OPTS := -E 5
|
||||
IMAGES := factory.bin sysupgrade.bin
|
||||
IMAGE/factory.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-ubi
|
||||
DEVICE_TITLE := Linksys EA8500
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
TARGET_DEVICES += linksys_ea8500
|
||||
|
||||
define Device/netgear_d7800
|
||||
$(call Device/DniImage)
|
||||
DEVICE_DTS := qcom-ipq8064-d7800
|
||||
KERNEL_SIZE := 2097152
|
||||
NETGEAR_BOARD_ID := D7800
|
||||
NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := d7800
|
||||
SUPPORTED_DEVICES += d7800
|
||||
DEVICE_TITLE := Netgear Nighthawk X4 D7800
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
TARGET_DEVICES += netgear_d7800
|
||||
|
||||
define Device/netgear_r7500
|
||||
$(call Device/DniImage)
|
||||
DEVICE_DTS := qcom-ipq8064-r7500
|
||||
KERNEL_SIZE := 2097152
|
||||
@ -195,11 +129,13 @@ define Device/R7500
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := r7500
|
||||
SUPPORTED_DEVICES += r7500
|
||||
DEVICE_TITLE := Netgear Nighthawk X4 R7500
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca988x
|
||||
endef
|
||||
TARGET_DEVICES += netgear_r7500
|
||||
|
||||
define Device/R7500v2
|
||||
define Device/netgear_r7500v2
|
||||
$(call Device/DniImage)
|
||||
DEVICE_DTS := qcom-ipq8064-r7500v2
|
||||
KERNEL_SIZE := 2097152
|
||||
@ -208,11 +144,13 @@ define Device/R7500v2
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := r7500v2
|
||||
SUPPORTED_DEVICES += r7500v2
|
||||
DEVICE_TITLE := Netgear Nighthawk X4 R7500v2
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0 ath10k-firmware-qca988x
|
||||
endef
|
||||
TARGET_DEVICES += netgear_r7500v2
|
||||
|
||||
define Device/R7800
|
||||
define Device/netgear_r7800
|
||||
$(call Device/DniImage)
|
||||
DEVICE_DTS := qcom-ipq8065-r7800
|
||||
KERNEL_SIZE := 2097152
|
||||
@ -221,23 +159,26 @@ define Device/R7800
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := r7800
|
||||
SUPPORTED_DEVICES += r7800
|
||||
DEVICE_TITLE := Netgear Nighthawk X4S R7800
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca9984
|
||||
endef
|
||||
TARGET_DEVICES += netgear_r7800
|
||||
|
||||
define Build/copy-file
|
||||
cat "$(1)" > "$@"
|
||||
endef
|
||||
|
||||
define Device/RT-AC58U
|
||||
define Device/asus_rt-ac58u
|
||||
$(call Device/FitImageLzma)
|
||||
DEVICE_DTS := qcom-ipq4019-rt-ac58u
|
||||
KERNEL_LOADADDR := 0x80208000
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DTB_SIZE := 65536
|
||||
BOARD_NAME := rt-ac58u
|
||||
KERNEL_LOADADDR := 0x80208000
|
||||
SUPPORTED_DEVICES += rt-ac58u
|
||||
DEVICE_TITLE := Asus RT-AC58U
|
||||
BOARD_NAME := rt-ac58u
|
||||
IMAGE_SIZE := 20439364
|
||||
FILESYSTEMS := squashfs
|
||||
# Someone - in their infinite wisdom - decided to put the firmware
|
||||
@ -251,53 +192,40 @@ define Device/RT-AC58U
|
||||
IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-phy-qcom-ipq4019 ipq-wifi-rt-ac58u
|
||||
endef
|
||||
TARGET_DEVICES += asus_rt-ac58u
|
||||
|
||||
define Device/RT-ACRH17
|
||||
define Device/openmesh_a42
|
||||
$(call Device/FitImageLzma)
|
||||
DEVICE_DTS := qcom-ipq4019-rt-acrh17
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DTB_SIZE := 65536
|
||||
BOARD_NAME := rt-acrh17
|
||||
DEVICE_DTS := qcom-ipq4019-a42
|
||||
KERNEL_LOADADDR := 0x80208000
|
||||
DEVICE_TITLE := Asus RT-ACRH17
|
||||
IMAGE_SIZE := 20439364
|
||||
FILESYSTEMS := squashfs
|
||||
UIMAGE_NAME:=$(shell echo -e '\03\01\01\01RT-AC82U')
|
||||
IMAGES = sysupgrade.tar flash-factory.trx
|
||||
IMAGE/flash-factory.trx := copy-file $(KDIR)/tmp/$$(KERNEL_INITRAMFS_IMAGE) | uImage none
|
||||
IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-phy-qcom-ipq4019 ath10k-firmware-qca4019 ath10k-firmware-qca9984
|
||||
endef
|
||||
|
||||
define Device/NBG6817
|
||||
DEVICE_DTS := qcom-ipq8065-nbg6817
|
||||
KERNEL_SIZE := 4096k
|
||||
BLOCKSIZE := 64k
|
||||
BOARD_NAME := nbg6817
|
||||
DEVICE_TITLE := ZyXEL NBG6817
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca9984 e2fsprogs losetup
|
||||
$(call Device/ZyXELImage)
|
||||
SUPPORTED_DEVICES := openmesh,a42
|
||||
DEVICE_TITLE := OpenMesh A42
|
||||
KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
|
||||
IMAGE_SIZE := 15616k
|
||||
IMAGES = factory.bin sysupgrade.bin
|
||||
IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A42
|
||||
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca4019 uboot-envtools ipq-wifi-openmesh_a42
|
||||
endef
|
||||
TARGET_DEVICES += openmesh_a42
|
||||
|
||||
define Device/VR2600v
|
||||
PROFILES += $$(DEVICE_NAME)
|
||||
FILESYSTEMS := squashfs
|
||||
KERNEL_SUFFIX := -uImage
|
||||
KERNEL = kernel-bin | append-dtb | uImage none
|
||||
KERNEL_NAME := zImage
|
||||
KERNEL_SIZE := 2097152
|
||||
DEVICE_DTS := qcom-ipq8064-vr2600v
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := vr2600v
|
||||
DEVICE_TITLE := TP-Link Archer VR2600v
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
define Device/qcom_ap-dk01.1-c1
|
||||
DEVICE_TITLE := QCA AP-DK01.1-C1
|
||||
BOARD_NAME := ap-dk01.1-c1
|
||||
DEVICE_DTS := qcom-ipq4019-ap.dk01.1-c1
|
||||
KERNEL_LOADADDR := 0x80208000
|
||||
KERNEL_INSTALL := 1
|
||||
KERNEL_SIZE := 4096k
|
||||
IMAGE_SIZE := 26624k
|
||||
$(call Device/FitImage)
|
||||
IMAGES := sysupgrade.bin
|
||||
IMAGE/sysupgrade.bin := pad-extra 512 | append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
|
||||
IMAGE/sysupgrade.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca4019
|
||||
endef
|
||||
TARGET_DEVICES += qcom_ap-dk01.1-c1
|
||||
|
||||
define Device/AP-DK04.1-C1
|
||||
define Device/qcom_ap-dk04.1-c1
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_DTS := qcom-ipq4019-ap.dk04.1-c1
|
||||
@ -309,10 +237,87 @@ define Device/AP-DK04.1-C1
|
||||
BOARD_NAME := ap-dk04.1-c1
|
||||
DEVICE_TITLE := QCA AP-DK04.1-C1
|
||||
endef
|
||||
TARGET_DEVICES += qcom_ap-dk04.1-c1
|
||||
|
||||
TARGET_DEVICES += AP148 AP148-legacy C2600 D7800 DB149 EA8500 FRITZ4040 R7500 \
|
||||
R7500v2 R7800 RT-AC58U RT-ACRH17 NBG6817 VR2600v AP-DK04.1-C1
|
||||
define Device/qcom_ipq8064-ap148
|
||||
$(call Device/FitImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_DTS := qcom-ipq8064-ap148
|
||||
KERNEL_INSTALL := 1
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := ap148
|
||||
SUPPORTED_DEVICES += ap148
|
||||
DEVICE_TITLE := Qualcomm AP148
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
TARGET_DEVICES += qcom_ipq8064-ap148
|
||||
|
||||
define Device/qcom_ipq8064-ap148-legacy
|
||||
$(call Device/LegacyImage)
|
||||
$(call Device/UbiFit)
|
||||
DEVICE_DTS := qcom-ipq8064-ap148
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := ap148
|
||||
SUPPORTED_DEVICES := qcom,ipq8064-ap148 ap148
|
||||
DEVICE_TITLE := Qualcomm AP148 (legacy)
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
TARGET_DEVICES += qcom_ipq8064-ap148-legacy
|
||||
|
||||
define Device/qcom_ipq8064-db149
|
||||
$(call Device/FitImage)
|
||||
DEVICE_DTS := qcom-ipq8064-db149
|
||||
KERNEL_INSTALL := 1
|
||||
BOARD_NAME := db149
|
||||
DEVICE_TITLE := Qualcomm DB149
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
TARGET_DEVICES += qcom_ipq8064-db149
|
||||
|
||||
define Device/tplink_c2600
|
||||
$(call Device/TpSafeImage)
|
||||
DEVICE_DTS := qcom-ipq8064-c2600
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := c2600
|
||||
SUPPORTED_DEVICES += c2600
|
||||
TPLINK_BOARD_ID := C2600
|
||||
DEVICE_TITLE := TP-Link Archer C2600
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
endef
|
||||
TARGET_DEVICES += tplink_c2600
|
||||
|
||||
define Device/tplink_vr2600v
|
||||
KERNEL_SUFFIX := -uImage
|
||||
KERNEL = kernel-bin | append-dtb | uImage none
|
||||
KERNEL_NAME := zImage
|
||||
KERNEL_SIZE := 2097152
|
||||
DEVICE_DTS := qcom-ipq8064-vr2600v
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
BOARD_NAME := vr2600v
|
||||
SUPPORTED_DEVICES += vr2600v
|
||||
DEVICE_TITLE := TP-Link Archer VR2600v
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0
|
||||
IMAGES := sysupgrade.bin
|
||||
IMAGE/sysupgrade.bin := pad-extra 512 | append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += tplink_vr2600v
|
||||
|
||||
define Device/zyxel_nbg6817
|
||||
DEVICE_DTS := qcom-ipq8065-nbg6817
|
||||
KERNEL_SIZE := 4096k
|
||||
BLOCKSIZE := 64k
|
||||
BOARD_NAME := nbg6817
|
||||
SUPPORTED_DEVICES += nbg6817
|
||||
DEVICE_TITLE := ZyXEL NBG6817
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca9984 e2fsprogs kmod-fs-ext4 losetup
|
||||
$(call Device/ZyXELImage)
|
||||
endef
|
||||
TARGET_DEVICES += zyxel_nbg6817
|
||||
|
||||
.NOTPARALLEL:
|
||||
|
||||
$(eval $(call BuildImage))
|
||||
$(eval $(call BuildImage))
|
||||
|
||||
@ -45,7 +45,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
@@ -81,6 +76,33 @@
|
||||
@@ -81,6 +76,29 @@
|
||||
reg = <0x3>;
|
||||
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
||||
clock-frequency = <0>;
|
||||
@ -71,10 +71,6 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
+ };
|
||||
+ opp@666000000 {
|
||||
+ opp-hz = /bits/ 64 <666000000>;
|
||||
+ clock-latency-ns = <256000>;
|
||||
+ };
|
||||
+ opp@717000000 {
|
||||
+ opp-hz = /bits/ 64 <717000000>;
|
||||
+ clock-latency-ns = <256000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -12,7 +12,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -183,6 +183,8 @@
|
||||
@@ -179,6 +179,8 @@
|
||||
clock-names = "iface", "core";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -17,7 +17,7 @@ Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -179,7 +179,7 @@
|
||||
@@ -175,7 +175,7 @@
|
||||
reg = <0x78b7000 0x6000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
|
||||
@ -12,7 +12,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -171,6 +171,8 @@
|
||||
@@ -167,6 +167,8 @@
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -1,28 +0,0 @@
|
||||
From 47f00399b195e0987c67006b329587bef0692bf4 Mon Sep 17 00:00:00 2001
|
||||
From: Thomas Pedersen <twp@codeaurora.org>
|
||||
Date: Wed, 4 May 2016 12:25:41 -0700
|
||||
Subject: [PATCH 22/69] dts: ipq4019: support ARMv7 PMU
|
||||
|
||||
Add support for cortex-a7-pmu present on ipq4019 SoCs.
|
||||
|
||||
Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
|
||||
Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -112,6 +112,12 @@
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
+ pmu {
|
||||
+ compatible = "arm,cortex-a7-pmu";
|
||||
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
+ IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ };
|
||||
+
|
||||
clocks {
|
||||
sleep_clk: sleep_clk {
|
||||
compatible = "fixed-clock";
|
||||
@ -34,7 +34,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
qcom-msm8960-cdp.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
|
||||
@@ -0,0 +1,21 @@
|
||||
@@ -0,0 +1,22 @@
|
||||
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * Permission to use, copy, modify, and/or distribute this software for any
|
||||
@ -55,6 +55,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
+
|
||||
+/ {
|
||||
+ model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
|
||||
+ compatible = "qcom,ap-dk04.1-c1", "qcom,ipq4019";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
|
||||
@ -32,7 +32,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
|
||||
endmenu
|
||||
--- a/drivers/phy/Makefile
|
||||
+++ b/drivers/phy/Makefile
|
||||
@@ -60,3 +60,4 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-
|
||||
@@ -60,3 +60,4 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
|
||||
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
|
||||
|
||||
@ -1,7 +1,21 @@
|
||||
From 1d6b12f73c98ecf252743936a53242356cc50a34 Mon Sep 17 00:00:00 2001
|
||||
From patchwork Fri Dec 8 09:42:19 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,01/12] ARM: Add Krait L2 register accessor functions
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102101
|
||||
Message-Id: <1512726150-7204-2-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org, Mark Rutland <mark.rutland@arm.com>,
|
||||
Russell King <linux@arm.linux.org.uk>,
|
||||
Courtney Cavin <courtney.cavin@sonymobile.com>
|
||||
Date: Fri, 8 Dec 2017 15:12:19 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:20 -0700
|
||||
Subject: [PATCH 34/69] ARM: Add Krait L2 register accessor functions
|
||||
|
||||
Krait CPUs have a handful of L2 cache controller registers that
|
||||
live behind a cp15 based indirection register. First you program
|
||||
|
||||
@ -1,7 +1,19 @@
|
||||
From 9d381d65eae163d8f50d97a3ad9033bba176f62b Mon Sep 17 00:00:00 2001
|
||||
From patchwork Fri Dec 8 09:42:20 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,02/12] clk: mux: Split out register accessors for reuse
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102103
|
||||
Message-Id: <1512726150-7204-3-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:20 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:21 -0700
|
||||
Subject: [PATCH 35/69] clk: mux: Split out register accessors for reuse
|
||||
|
||||
We want to reuse the logic in clk-mux.c for other clock drivers
|
||||
that don't use readl as register accessors. Fortunately, there
|
||||
@ -12,28 +24,25 @@ that operate on an optional table and some flags so that other
|
||||
drivers can use the same logic.
|
||||
|
||||
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
---
|
||||
drivers/clk/clk-mux.c | 76 ++++++++++++++++++++++++++++----------------
|
||||
include/linux/clk-provider.h | 11 +++++--
|
||||
2 files changed, 57 insertions(+), 30 deletions(-)
|
||||
drivers/clk/clk-mux.c | 75 +++++++++++++++++++++++++++-----------------
|
||||
include/linux/clk-provider.h | 9 ++++--
|
||||
2 files changed, 54 insertions(+), 30 deletions(-)
|
||||
|
||||
--- a/drivers/clk/clk-mux.c
|
||||
+++ b/drivers/clk/clk-mux.c
|
||||
@@ -26,35 +26,27 @@
|
||||
@@ -26,35 +26,24 @@
|
||||
* parent - parent is adjustable through clk_set_parent
|
||||
*/
|
||||
|
||||
-static u8 clk_mux_get_parent(struct clk_hw *hw)
|
||||
+#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
+
|
||||
+unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
|
||||
+ unsigned int *table, unsigned long flags)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
- struct clk_mux *mux = to_clk_mux(hw);
|
||||
int num_parents = clk_hw_get_num_parents(hw);
|
||||
- u32 val;
|
||||
|
||||
-
|
||||
- /*
|
||||
- * FIXME need a mux-specific flag to determine if val is bitwise or numeric
|
||||
- * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
|
||||
@ -43,7 +52,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
- */
|
||||
- val = clk_readl(mux->reg) >> mux->shift;
|
||||
- val &= mux->mask;
|
||||
-
|
||||
|
||||
- if (mux->table) {
|
||||
+ if (table) {
|
||||
int i;
|
||||
@ -64,7 +73,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
val--;
|
||||
|
||||
if (val >= num_parents)
|
||||
@@ -62,23 +54,53 @@ static u8 clk_mux_get_parent(struct clk_
|
||||
@@ -62,23 +51,53 @@ static u8 clk_mux_get_parent(struct clk_
|
||||
|
||||
return val;
|
||||
}
|
||||
@ -80,9 +89,9 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
- if (mux->table) {
|
||||
- index = mux->table[index];
|
||||
+ /*
|
||||
+ * FIXME need a mux-specific flag to determine if val is bitwise or numeric
|
||||
+ * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
|
||||
+ * to 0x7 (index starts at one)
|
||||
+ * FIXME need a mux-specific flag to determine if val is bitwise or
|
||||
+ * numeric e.g. sys_clkin_ck's clksel field is 3 bits wide,
|
||||
+ * but ranges from 0x1 to 0x7 (index starts at one)
|
||||
+ * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
|
||||
+ * val = 0x4 really means "bit 2, index starts at bit 0"
|
||||
+ */
|
||||
@ -126,7 +135,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
if (mux->lock)
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
else
|
||||
@@ -102,14 +124,14 @@ static int clk_mux_set_parent(struct clk
|
||||
@@ -102,14 +121,14 @@ static int clk_mux_set_parent(struct clk
|
||||
}
|
||||
|
||||
const struct clk_ops clk_mux_ops = {
|
||||
@ -143,7 +152,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
|
||||
|
||||
@@ -117,7 +139,7 @@ struct clk_hw *clk_hw_register_mux_table
|
||||
@@ -117,7 +136,7 @@ struct clk_hw *clk_hw_register_mux_table
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u32 mask,
|
||||
@ -175,13 +184,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
struct clk *clk_register_mux(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
@@ -499,12 +504,12 @@ struct clk *clk_register_mux_table(struc
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u32 mask,
|
||||
- u8 clk_mux_flags, u32 *table, spinlock_t *lock);
|
||||
+ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
|
||||
struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
|
||||
@@ -504,7 +509,7 @@ struct clk_hw *clk_hw_register_mux_table
|
||||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u32 mask,
|
||||
|
||||
@ -1,107 +0,0 @@
|
||||
From 88e1d6d9c113fe50810d1b03eb1fdbf015e5d1bd Mon Sep 17 00:00:00 2001
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:22 -0700
|
||||
Subject: [PATCH 36/69] clk: Avoid sending high rates to downstream clocks
|
||||
during set_rate
|
||||
|
||||
If a clock is on and we call clk_set_rate() on it we may get into
|
||||
a situation where the clock temporarily increases in rate
|
||||
dramatically while we walk the tree and call .set_rate() ops. For
|
||||
example, consider a case where a PLL feeds into a divider.
|
||||
Initially the divider is set to divide by 1 and the PLL is
|
||||
running fairly slow (100MHz). The downstream consumer of the
|
||||
divider output can only handle rates =< 400 MHz, but the divider
|
||||
can only choose between divisors of 1 and 4.
|
||||
|
||||
+-----+ +----------------+
|
||||
| PLL |-->| div 1 or div 4 |---> consumer device
|
||||
+-----+ +----------------+
|
||||
|
||||
To achieve a rate of 400MHz on the output of the divider, we
|
||||
would have to set the rate of the PLL to 1.6 GHz and then divide
|
||||
it by 4. The current code would set the PLL to 1.6GHz first while
|
||||
the divider is still set to 1, thus causing the downstream
|
||||
consumer of the clock to receive a few clock cycles of 1.6GHz
|
||||
clock (far beyond it's maximum acceptable rate). We should be
|
||||
changing the divider first before increasing the PLL rate to
|
||||
avoid this problem.
|
||||
|
||||
Therefore, set the rate of any child clocks that are increasing
|
||||
in rate from their current rate so that they can increase their
|
||||
dividers if necessary. We assume that there isn't such a thing as
|
||||
minimum rate requirements.
|
||||
|
||||
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
|
||||
Conflicts:
|
||||
drivers/clk/clk.c
|
||||
---
|
||||
drivers/clk/clk.c | 22 +++++++++++++++-------
|
||||
1 file changed, 15 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/drivers/clk/clk.c
|
||||
+++ b/drivers/clk/clk.c
|
||||
@@ -1466,12 +1466,12 @@ static struct clk_core *clk_propagate_ra
|
||||
* walk down a subtree and set the new rates notifying the rate
|
||||
* change on the way
|
||||
*/
|
||||
-static void clk_change_rate(struct clk_core *core)
|
||||
+static void
|
||||
+clk_change_rate(struct clk_core *core, unsigned long best_parent_rate)
|
||||
{
|
||||
struct clk_core *child;
|
||||
struct hlist_node *tmp;
|
||||
unsigned long old_rate;
|
||||
- unsigned long best_parent_rate = 0;
|
||||
bool skip_set_rate = false;
|
||||
struct clk_core *old_parent;
|
||||
struct clk_core *parent = NULL;
|
||||
@@ -1523,6 +1523,7 @@ static void clk_change_rate(struct clk_c
|
||||
trace_clk_set_rate_complete(core, core->new_rate);
|
||||
|
||||
core->rate = clk_recalc(core, best_parent_rate);
|
||||
+ core->rate = core->new_rate;
|
||||
|
||||
if (core->flags & CLK_SET_RATE_UNGATE) {
|
||||
unsigned long flags;
|
||||
@@ -1550,12 +1551,13 @@ static void clk_change_rate(struct clk_c
|
||||
/* Skip children who will be reparented to another clock */
|
||||
if (child->new_parent && child->new_parent != core)
|
||||
continue;
|
||||
- clk_change_rate(child);
|
||||
+ if (child->new_rate != child->rate)
|
||||
+ clk_change_rate(child, core->new_rate);
|
||||
}
|
||||
|
||||
- /* handle the new child who might not be in core->children yet */
|
||||
- if (core->new_child)
|
||||
- clk_change_rate(core->new_child);
|
||||
+ /* handle the new child who might not be in clk->children yet */
|
||||
+ if (core->new_child && core->new_child->new_rate != core->new_child->rate)
|
||||
+ clk_change_rate(core->new_child, core->new_rate);
|
||||
}
|
||||
|
||||
static int clk_core_set_rate_nolock(struct clk_core *core,
|
||||
@@ -1563,6 +1565,7 @@ static int clk_core_set_rate_nolock(stru
|
||||
{
|
||||
struct clk_core *top, *fail_clk;
|
||||
unsigned long rate = req_rate;
|
||||
+ unsigned long parent_rate;
|
||||
|
||||
if (!core)
|
||||
return 0;
|
||||
@@ -1588,8 +1591,13 @@ static int clk_core_set_rate_nolock(stru
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
+ if (top->parent)
|
||||
+ parent_rate = top->parent->rate;
|
||||
+ else
|
||||
+ parent_rate = 0;
|
||||
+
|
||||
/* change the rates */
|
||||
- clk_change_rate(top);
|
||||
+ clk_change_rate(top, parent_rate);
|
||||
|
||||
core->req_rate = req_rate;
|
||||
|
||||
@ -1,158 +0,0 @@
|
||||
From a1adfb782789ae9b25c928dfe3d639288563a86c Mon Sep 17 00:00:00 2001
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:23 -0700
|
||||
Subject: [PATCH 37/69] clk: Add safe switch hook
|
||||
|
||||
Sometimes clocks can't accept their parent source turning off
|
||||
while the source is reprogrammed to a different rate. Most
|
||||
notably CPU clocks require a way to switch away from the current
|
||||
PLL they're running on, reprogram that PLL to a new rate, and
|
||||
then switch back to the PLL with the new rate once they're done.
|
||||
Add a hook that drivers can implement allowing them to return a
|
||||
'safe parent' and 'safe frequency' that they can switch their
|
||||
parent to while the upstream source is reprogrammed to support
|
||||
this.
|
||||
|
||||
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
---
|
||||
drivers/clk/clk.c | 73 +++++++++++++++++++++++++++++++++++++++++---
|
||||
include/linux/clk-provider.h | 2 ++
|
||||
2 files changed, 70 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/clk/clk.c
|
||||
+++ b/drivers/clk/clk.c
|
||||
@@ -51,9 +51,13 @@ struct clk_core {
|
||||
struct clk_core **parents;
|
||||
u8 num_parents;
|
||||
u8 new_parent_index;
|
||||
+ u8 safe_parent_index;
|
||||
unsigned long rate;
|
||||
unsigned long req_rate;
|
||||
+ unsigned long old_rate;
|
||||
unsigned long new_rate;
|
||||
+ unsigned long safe_freq;
|
||||
+ struct clk_core *safe_parent;
|
||||
struct clk_core *new_parent;
|
||||
struct clk_core *new_child;
|
||||
unsigned long flags;
|
||||
@@ -1310,7 +1314,9 @@ out:
|
||||
static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
|
||||
struct clk_core *new_parent, u8 p_index)
|
||||
{
|
||||
- struct clk_core *child;
|
||||
+ struct clk_core *child, *parent;
|
||||
+ struct clk_hw *parent_hw;
|
||||
+ unsigned long safe_freq = 0;
|
||||
|
||||
core->new_rate = new_rate;
|
||||
core->new_parent = new_parent;
|
||||
@@ -1320,6 +1326,23 @@ static void clk_calc_subtree(struct clk_
|
||||
if (new_parent && new_parent != core->parent)
|
||||
new_parent->new_child = core;
|
||||
|
||||
+ if (core->ops->get_safe_parent) {
|
||||
+ parent_hw = core->ops->get_safe_parent(core->hw, &safe_freq);
|
||||
+ if (parent_hw) {
|
||||
+ parent = parent_hw->core;
|
||||
+ p_index = clk_fetch_parent_index(core, parent);
|
||||
+ core->safe_parent_index = p_index;
|
||||
+ core->safe_parent = parent;
|
||||
+ if (safe_freq)
|
||||
+ core->safe_freq = safe_freq;
|
||||
+ else
|
||||
+ core->safe_freq = 0;
|
||||
+ }
|
||||
+ } else {
|
||||
+ core->safe_parent = NULL;
|
||||
+ core->safe_freq = 0;
|
||||
+ }
|
||||
+
|
||||
hlist_for_each_entry(child, &core->children, child_node) {
|
||||
child->new_rate = clk_recalc(child, new_rate);
|
||||
clk_calc_subtree(child, child->new_rate, NULL, 0);
|
||||
@@ -1432,14 +1455,51 @@ static struct clk_core *clk_propagate_ra
|
||||
unsigned long event)
|
||||
{
|
||||
struct clk_core *child, *tmp_clk, *fail_clk = NULL;
|
||||
+ struct clk_core *old_parent;
|
||||
int ret = NOTIFY_DONE;
|
||||
|
||||
- if (core->rate == core->new_rate)
|
||||
+ if (core->rate == core->new_rate && event != POST_RATE_CHANGE)
|
||||
return NULL;
|
||||
|
||||
+ switch (event) {
|
||||
+ case PRE_RATE_CHANGE:
|
||||
+ if (core->safe_parent) {
|
||||
+ if (core->safe_freq)
|
||||
+ core->ops->set_rate_and_parent(core->hw,
|
||||
+ core->safe_freq,
|
||||
+ core->safe_parent->rate,
|
||||
+ core->safe_parent_index);
|
||||
+ else
|
||||
+ core->ops->set_parent(core->hw,
|
||||
+ core->safe_parent_index);
|
||||
+ }
|
||||
+ core->old_rate = core->rate;
|
||||
+ break;
|
||||
+ case POST_RATE_CHANGE:
|
||||
+ if (core->safe_parent) {
|
||||
+ old_parent = __clk_set_parent_before(core,
|
||||
+ core->new_parent);
|
||||
+ if (core->ops->set_rate_and_parent) {
|
||||
+ core->ops->set_rate_and_parent(core->hw,
|
||||
+ core->new_rate,
|
||||
+ core->new_parent ?
|
||||
+ core->new_parent->rate : 0,
|
||||
+ core->new_parent_index);
|
||||
+ } else if (core->ops->set_parent) {
|
||||
+ core->ops->set_parent(core->hw,
|
||||
+ core->new_parent_index);
|
||||
+ }
|
||||
+ __clk_set_parent_after(core, core->new_parent,
|
||||
+ old_parent);
|
||||
+ }
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
if (core->notifier_count) {
|
||||
- ret = __clk_notify(core, event, core->rate, core->new_rate);
|
||||
- if (ret & NOTIFY_STOP_MASK)
|
||||
+ if (event != POST_RATE_CHANGE || core->old_rate != core->rate)
|
||||
+ ret = __clk_notify(core, event, core->old_rate,
|
||||
+ core->new_rate);
|
||||
+ if (ret & NOTIFY_STOP_MASK && event != POST_RATE_CHANGE)
|
||||
fail_clk = core;
|
||||
}
|
||||
|
||||
@@ -1495,7 +1555,8 @@ clk_change_rate(struct clk_core *core, u
|
||||
clk_enable_unlock(flags);
|
||||
}
|
||||
|
||||
- if (core->new_parent && core->new_parent != core->parent) {
|
||||
+ if (core->new_parent && core->new_parent != core->parent &&
|
||||
+ !core->safe_parent) {
|
||||
old_parent = __clk_set_parent_before(core, core->new_parent);
|
||||
trace_clk_set_parent(core, core->new_parent);
|
||||
|
||||
@@ -1601,6 +1662,8 @@ static int clk_core_set_rate_nolock(stru
|
||||
|
||||
core->req_rate = req_rate;
|
||||
|
||||
+ clk_propagate_rate_change(top, POST_RATE_CHANGE);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/include/linux/clk-provider.h
|
||||
+++ b/include/linux/clk-provider.h
|
||||
@@ -206,6 +206,8 @@ struct clk_ops {
|
||||
struct clk_rate_request *req);
|
||||
int (*set_parent)(struct clk_hw *hw, u8 index);
|
||||
u8 (*get_parent)(struct clk_hw *hw);
|
||||
+ struct clk_hw *(*get_safe_parent)(struct clk_hw *hw,
|
||||
+ unsigned long *safe_freq);
|
||||
int (*set_rate)(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
int (*set_rate_and_parent)(struct clk_hw *hw,
|
||||
@ -1,7 +1,19 @@
|
||||
From f044ffe2d612dcaa2de36c918aaab79c8db1482e Mon Sep 17 00:00:00 2001
|
||||
From patchwork Fri Dec 8 09:42:21 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,03/12] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102083
|
||||
Message-Id: <1512726150-7204-4-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:21 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:24 -0700
|
||||
Subject: [PATCH 38/69] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
|
||||
|
||||
HFPLLs are the main frequency source for Krait CPU clocks. Add
|
||||
support for changing the rate of these PLLs.
|
||||
@ -105,7 +117,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ * H/W requires a 5us delay between disabling the bypass and
|
||||
+ * de-asserting the reset. Delay 10us just to be safe.
|
||||
+ */
|
||||
+ udelay(10);
|
||||
+ usleep_range(10, 100);
|
||||
+
|
||||
+ /* De-assert active-low PLL reset. */
|
||||
+ regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
|
||||
@ -116,7 +128,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ regmap_read(regmap, hd->status_reg, &val);
|
||||
+ } while (!(val & BIT(hd->lock_bit)));
|
||||
+ } else {
|
||||
+ udelay(60);
|
||||
+ usleep_range(60, 100);
|
||||
+ }
|
||||
+
|
||||
+ /* Enable PLL output. */
|
||||
@ -151,7 +163,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ * and assert the reset.
|
||||
+ */
|
||||
+ regmap_update_bits(regmap, hd->mode_reg,
|
||||
+ PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
|
||||
+ PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
|
||||
+}
|
||||
+
|
||||
+static void clk_hfpll_disable(struct clk_hw *hw)
|
||||
@ -252,7 +264,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ regmap_read(regmap, hd->status_reg, &status);
|
||||
+ if (!(status & BIT(hd->lock_bit))) {
|
||||
+ WARN(1, "HFPLL %s is ON, but not locked!\n",
|
||||
+ __clk_get_name(hw->clk));
|
||||
+ __clk_get_name(hw->clk));
|
||||
+ clk_hfpll_disable(hw);
|
||||
+ __clk_hfpll_init_once(hw);
|
||||
+ }
|
||||
|
||||
@ -1,7 +1,19 @@
|
||||
From 23f680d03e5894f494572a5162d21328bd86890c Mon Sep 17 00:00:00 2001
|
||||
From patchwork Fri Dec 8 09:42:22 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,04/12] clk: qcom: Add HFPLL driver
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102079
|
||||
Message-Id: <1512726150-7204-5-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:22 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:25 -0700
|
||||
Subject: [PATCH 39/69] clk: qcom: Add HFPLL driver
|
||||
|
||||
On some devices (MSM8974 for example), the HFPLLs are
|
||||
instantiated within the Krait processor subsystem as separate
|
||||
@ -10,7 +22,6 @@ provide HFPLL clocks for use by the system.
|
||||
|
||||
Cc: <devicetree@vger.kernel.org>
|
||||
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
---
|
||||
.../devicetree/bindings/clock/qcom,hfpll.txt | 40 ++++++++
|
||||
drivers/clk/qcom/Kconfig | 8 ++
|
||||
@ -171,7 +182,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
+ return PTR_ERR(regmap);
|
||||
+
|
||||
+ if (of_property_read_string_index(dev->of_node, "clock-output-names",
|
||||
+ 0, &init.name))
|
||||
+ 0, &init.name))
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ h->d = &hdata;
|
||||
|
||||
@ -1,14 +1,26 @@
|
||||
From 0dfdf84ee3982e88a62123b3de1c094d2c0829af Mon Sep 17 00:00:00 2001
|
||||
From patchwork Fri Dec 8 09:42:24 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,06/12] clk: qcom: Add IPQ806X's HFPLLs
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102047
|
||||
Message-Id: <1512726150-7204-7-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:24 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:27 -0700
|
||||
Subject: [PATCH 40/69] clk: qcom: Add IPQ806X's HFPLLs
|
||||
|
||||
Describe the HFPLLs present on IPQ806X devices.
|
||||
|
||||
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq806x.c | 83 ++++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 83 insertions(+)
|
||||
drivers/clk/qcom/gcc-ipq806x.c | 82 ++++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 82 insertions(+)
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq806x.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq806x.c
|
||||
@ -20,7 +32,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
#include "reset.h"
|
||||
|
||||
static struct clk_pll pll0 = {
|
||||
@@ -113,6 +114,85 @@ static struct clk_regmap pll8_vote = {
|
||||
@@ -113,6 +114,84 @@ static struct clk_regmap pll8_vote = {
|
||||
},
|
||||
};
|
||||
|
||||
@ -101,12 +113,11 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ },
|
||||
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
|
||||
+};
|
||||
+
|
||||
+
|
||||
static struct clk_pll pll14 = {
|
||||
.l_reg = 0x31c4,
|
||||
.m_reg = 0x31c8,
|
||||
@@ -2801,6 +2881,9 @@ static struct clk_regmap *gcc_ipq806x_cl
|
||||
@@ -2801,6 +2880,9 @@ static struct clk_regmap *gcc_ipq806x_cl
|
||||
[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
|
||||
[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
|
||||
[NSSTCM_CLK] = &nss_tcm_clk.clkr,
|
||||
|
||||
@ -1,7 +1,19 @@
|
||||
From b9747125a8e7633ed2701a70e32dbb0442193774 Mon Sep 17 00:00:00 2001
|
||||
From patchwork Fri Dec 8 09:42:25 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,07/12] clk: qcom: Add support for Krait clocks
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102051
|
||||
Message-Id: <1512726150-7204-8-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:25 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:28 -0700
|
||||
Subject: [PATCH 41/69] clk: qcom: Add support for Krait clocks
|
||||
|
||||
The Krait clocks are made up of a series of muxes and a divider
|
||||
that choose between a fixed rate clock and dedicated HFPLLs for
|
||||
@ -13,9 +25,9 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
---
|
||||
drivers/clk/qcom/Kconfig | 4 ++
|
||||
drivers/clk/qcom/Makefile | 1 +
|
||||
drivers/clk/qcom/clk-krait.c | 167 +++++++++++++++++++++++++++++++++++++++++++
|
||||
drivers/clk/qcom/clk-krait.h | 49 +++++++++++++
|
||||
4 files changed, 221 insertions(+)
|
||||
drivers/clk/qcom/clk-krait.c | 134 +++++++++++++++++++++++++++++++++++++++++++
|
||||
drivers/clk/qcom/clk-krait.h | 48 ++++++++++++++++
|
||||
4 files changed, 187 insertions(+)
|
||||
create mode 100644 drivers/clk/qcom/clk-krait.c
|
||||
create mode 100644 drivers/clk/qcom/clk-krait.h
|
||||
|
||||
@ -41,7 +53,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/qcom/clk-krait.c
|
||||
@@ -0,0 +1,167 @@
|
||||
@@ -0,0 +1,134 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
@ -103,6 +115,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ /* Don't touch mux if CPU is off as it won't work */
|
||||
+ if (__clk_is_enabled(hw->clk))
|
||||
+ __krait_mux_set_sel(mux, sel);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
@ -119,44 +132,10 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
|
||||
+}
|
||||
+
|
||||
+static struct clk_hw *krait_mux_get_safe_parent(struct clk_hw *hw,
|
||||
+ unsigned long *safe_freq)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
|
||||
+ int num_parents = clk_hw_get_num_parents(hw);
|
||||
+
|
||||
+ i = mux->safe_sel;
|
||||
+ for (i = 0; i < num_parents; i++)
|
||||
+ if (mux->safe_sel == mux->parent_map[i])
|
||||
+ break;
|
||||
+
|
||||
+ return clk_hw_get_parent_by_index(hw, i);
|
||||
+}
|
||||
+
|
||||
+static int krait_mux_enable(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
|
||||
+
|
||||
+ __krait_mux_set_sel(mux, mux->en_mask);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void krait_mux_disable(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
|
||||
+
|
||||
+ __krait_mux_set_sel(mux, mux->safe_sel);
|
||||
+}
|
||||
+
|
||||
+const struct clk_ops krait_mux_clk_ops = {
|
||||
+ .enable = krait_mux_enable,
|
||||
+ .disable = krait_mux_disable,
|
||||
+ .set_parent = krait_mux_set_parent,
|
||||
+ .get_parent = krait_mux_get_parent,
|
||||
+ .determine_rate = __clk_mux_determine_rate_closest,
|
||||
+ .get_safe_parent = krait_mux_get_safe_parent,
|
||||
+};
|
||||
+EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
|
||||
+
|
||||
@ -169,7 +148,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+}
|
||||
+
|
||||
+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
+ unsigned long parent_rate)
|
||||
+ unsigned long parent_rate)
|
||||
+{
|
||||
+ struct krait_div2_clk *d = to_krait_div2_clk(hw);
|
||||
+ unsigned long flags;
|
||||
@ -211,7 +190,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/qcom/clk-krait.h
|
||||
@@ -0,0 +1,49 @@
|
||||
@@ -0,0 +1,48 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
@ -232,8 +211,6 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+
|
||||
+struct krait_mux_clk {
|
||||
+ unsigned int *parent_map;
|
||||
+ bool has_safe_parent;
|
||||
+ u8 safe_sel;
|
||||
+ u32 offset;
|
||||
+ u32 mask;
|
||||
+ u32 shift;
|
||||
@ -241,6 +218,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ bool lpl;
|
||||
+
|
||||
+ struct clk_hw hw;
|
||||
+ struct notifier_block clk_nb;
|
||||
+};
|
||||
+
|
||||
+#define to_krait_mux_clk(_hw) container_of(_hw, struct krait_mux_clk, hw)
|
||||
|
||||
@ -1,7 +1,19 @@
|
||||
From 6039eb63fabdd6871fc70940aa98102665c78eed Mon Sep 17 00:00:00 2001
|
||||
From patchwork Fri Dec 8 09:42:26 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,08/12] clk: qcom: Add KPSS ACC/GCC driver
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102023
|
||||
Message-Id: <1512726150-7204-9-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:26 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:29 -0700
|
||||
Subject: [PATCH 42/69] clk: qcom: Add KPSS ACC/GCC driver
|
||||
|
||||
The ACC and GCC regions present in KPSSv1 contain registers to
|
||||
control clocks and power to each Krait CPU and L2. For CPUfreq
|
||||
@ -15,8 +27,8 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
.../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 28 +++++++
|
||||
drivers/clk/qcom/Kconfig | 8 ++
|
||||
drivers/clk/qcom/Makefile | 1 +
|
||||
drivers/clk/qcom/kpss-xcc.c | 95 ++++++++++++++++++++++
|
||||
5 files changed, 139 insertions(+)
|
||||
drivers/clk/qcom/kpss-xcc.c | 96 ++++++++++++++++++++++
|
||||
5 files changed, 140 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
|
||||
create mode 100644 drivers/clk/qcom/kpss-xcc.c
|
||||
|
||||
@ -98,7 +110,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/qcom/kpss-xcc.c
|
||||
@@ -0,0 +1,95 @@
|
||||
@@ -0,0 +1,96 @@
|
||||
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
@ -158,7 +170,8 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+
|
||||
+ if (id->data) {
|
||||
+ if (of_property_read_string_index(pdev->dev.of_node,
|
||||
+ "clock-output-names", 0, &name))
|
||||
+ "clock-output-names",
|
||||
+ 0, &name))
|
||||
+ return -ENODEV;
|
||||
+ base += 0x14;
|
||||
+ } else {
|
||||
|
||||
@ -1,7 +1,19 @@
|
||||
From 7fb5976eb0231a06f484a6bde5e5fbfee7ee4f4a Mon Sep 17 00:00:00 2001
|
||||
From patchwork Fri Dec 8 09:42:27 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,09/12] clk: qcom: Add Krait clock controller driver
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102061
|
||||
Message-Id: <1512726150-7204-10-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:27 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:30 -0700
|
||||
Subject: [PATCH 43/69] clk: qcom: Add Krait clock controller driver
|
||||
|
||||
The Krait CPU clocks are made up of a primary mux and secondary
|
||||
mux for each CPU and the L2, controlled via cp15 accessors. For
|
||||
@ -15,8 +27,8 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
.../devicetree/bindings/clock/qcom,krait-cc.txt | 22 ++
|
||||
drivers/clk/qcom/Kconfig | 8 +
|
||||
drivers/clk/qcom/Makefile | 1 +
|
||||
drivers/clk/qcom/krait-cc.c | 352 +++++++++++++++++++++
|
||||
4 files changed, 383 insertions(+)
|
||||
drivers/clk/qcom/krait-cc.c | 350 +++++++++++++++++++++
|
||||
4 files changed, 381 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
|
||||
create mode 100644 drivers/clk/qcom/krait-cc.c
|
||||
|
||||
@ -71,7 +83,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+obj-$(CONFIG_KRAITCC) += krait-cc.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/qcom/krait-cc.c
|
||||
@@ -0,0 +1,352 @@
|
||||
@@ -0,0 +1,350 @@
|
||||
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
@ -110,7 +122,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+};
|
||||
+
|
||||
+static int
|
||||
+krait_add_div(struct device *dev, int id, const char *s, unsigned offset)
|
||||
+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
|
||||
+{
|
||||
+ struct krait_div2_clk *div;
|
||||
+ struct clk_init_data init = {
|
||||
@ -150,8 +162,8 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned offset,
|
||||
+ bool unique_aux)
|
||||
+krait_add_sec_mux(struct device *dev, int id, const char *s,
|
||||
+ unsigned int offset, bool unique_aux)
|
||||
+{
|
||||
+ struct krait_mux_clk *mux;
|
||||
+ static const char *sec_mux_list[] = {
|
||||
@ -172,8 +184,6 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+
|
||||
+ mux->offset = offset;
|
||||
+ mux->lpl = id >= 0;
|
||||
+ mux->has_safe_parent = true;
|
||||
+ mux->safe_sel = 2;
|
||||
+ mux->mask = 0x3;
|
||||
+ mux->shift = 2;
|
||||
+ mux->parent_map = sec_mux_map;
|
||||
@ -201,7 +211,8 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+}
|
||||
+
|
||||
+static struct clk *
|
||||
+krait_add_pri_mux(struct device *dev, int id, const char *s, unsigned offset)
|
||||
+krait_add_pri_mux(struct device *dev, int id, const char *s,
|
||||
+ unsigned int offset)
|
||||
+{
|
||||
+ struct krait_mux_clk *mux;
|
||||
+ const char *p_names[3];
|
||||
@ -217,8 +228,6 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ if (!mux)
|
||||
+ return ERR_PTR(-ENOMEM);
|
||||
+
|
||||
+ mux->has_safe_parent = true;
|
||||
+ mux->safe_sel = 0;
|
||||
+ mux->mask = 0x3;
|
||||
+ mux->shift = 0;
|
||||
+ mux->offset = offset;
|
||||
@ -264,7 +273,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
|
||||
+{
|
||||
+ int ret;
|
||||
+ unsigned offset;
|
||||
+ unsigned int offset;
|
||||
+ void *p = NULL;
|
||||
+ const char *s;
|
||||
+ struct clk *clk;
|
||||
@ -332,7 +341,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
|
||||
+ clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1);
|
||||
+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
|
||||
+ if (IS_ERR(clk))
|
||||
+ return PTR_ERR(clk);
|
||||
+
|
||||
@ -370,7 +379,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ for_each_online_cpu(cpu) {
|
||||
+ clk_prepare_enable(l2_pri_mux_clk);
|
||||
+ WARN(clk_prepare_enable(clks[cpu]),
|
||||
+ "Unable to turn on CPU%d clock", cpu);
|
||||
+ "Unable to turn on CPU%d clock", cpu);
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
@ -401,6 +410,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
|
||||
+ cur_rate = aux_rate;
|
||||
+ }
|
||||
+
|
||||
+ clk_set_rate(clk, aux_rate);
|
||||
+ clk_set_rate(clk, 2);
|
||||
+ clk_set_rate(clk, cur_rate);
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
From patchwork Fri Dec 8 09:42:28 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,10/12] clk: qcom: Add safe switch hook for krait mux clocks
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102057
|
||||
Message-Id: <1512726150-7204-11-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:28 +0530
|
||||
|
||||
When the Hfplls are reprogrammed during the rate change,
|
||||
the primary muxes which are sourced from the same hfpll
|
||||
for higher frequencies, needs to be switched to the 'safe
|
||||
secondary mux' as the parent for that small window. This
|
||||
is done by registering a clk notifier for the muxes and
|
||||
switching to the safe parent in the PRE_RATE_CHANGE notifier
|
||||
and back to the original parent in the POST_RATE_CHANGE notifier.
|
||||
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
---
|
||||
drivers/clk/qcom/clk-krait.c | 2 ++
|
||||
drivers/clk/qcom/clk-krait.h | 3 +++
|
||||
drivers/clk/qcom/krait-cc.c | 56 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 61 insertions(+)
|
||||
|
||||
--- a/drivers/clk/qcom/clk-krait.c
|
||||
+++ b/drivers/clk/qcom/clk-krait.c
|
||||
@@ -60,6 +60,8 @@ static int krait_mux_set_parent(struct c
|
||||
if (__clk_is_enabled(hw->clk))
|
||||
__krait_mux_set_sel(mux, sel);
|
||||
|
||||
+ mux->reparent = true;
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/drivers/clk/qcom/clk-krait.h
|
||||
+++ b/drivers/clk/qcom/clk-krait.h
|
||||
@@ -23,6 +23,9 @@ struct krait_mux_clk {
|
||||
u32 shift;
|
||||
u32 en_mask;
|
||||
bool lpl;
|
||||
+ u8 safe_sel;
|
||||
+ u8 old_index;
|
||||
+ bool reparent;
|
||||
|
||||
struct clk_hw hw;
|
||||
struct notifier_block clk_nb;
|
||||
--- a/drivers/clk/qcom/krait-cc.c
|
||||
+++ b/drivers/clk/qcom/krait-cc.c
|
||||
@@ -35,6 +35,49 @@ static unsigned int pri_mux_map[] = {
|
||||
0,
|
||||
};
|
||||
|
||||
+/*
|
||||
+ * Notifier function for switching the muxes to safe parent
|
||||
+ * while the hfpll is getting reprogrammed.
|
||||
+ */
|
||||
+static int krait_notifier_cb(struct notifier_block *nb,
|
||||
+ unsigned long event,
|
||||
+ void *data)
|
||||
+{
|
||||
+ int ret = 0;
|
||||
+ struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
|
||||
+ clk_nb);
|
||||
+ /* Switch to safe parent */
|
||||
+ if (event == PRE_RATE_CHANGE) {
|
||||
+ mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw);
|
||||
+ ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel);
|
||||
+ mux->reparent = false;
|
||||
+ /*
|
||||
+ * By the time POST_RATE_CHANGE notifier is called,
|
||||
+ * clk framework itself would have changed the parent for the new rate.
|
||||
+ * Only otherwise, put back to the old parent.
|
||||
+ */
|
||||
+ } else if (event == POST_RATE_CHANGE) {
|
||||
+ if (!mux->reparent)
|
||||
+ ret = krait_mux_clk_ops.set_parent(&mux->hw,
|
||||
+ mux->old_index);
|
||||
+ }
|
||||
+
|
||||
+ return notifier_from_errno(ret);
|
||||
+}
|
||||
+
|
||||
+static int krait_notifier_register(struct device *dev, struct clk *clk,
|
||||
+ struct krait_mux_clk *mux)
|
||||
+{
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ mux->clk_nb.notifier_call = krait_notifier_cb;
|
||||
+ ret = clk_notifier_register(clk, &mux->clk_nb);
|
||||
+ if (ret)
|
||||
+ dev_err(dev, "failed to register clock notifier: %d\n", ret);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
static int
|
||||
krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
|
||||
{
|
||||
@@ -79,6 +122,7 @@ static int
|
||||
krait_add_sec_mux(struct device *dev, int id, const char *s,
|
||||
unsigned int offset, bool unique_aux)
|
||||
{
|
||||
+ int ret;
|
||||
struct krait_mux_clk *mux;
|
||||
static const char *sec_mux_list[] = {
|
||||
"acpu_aux",
|
||||
@@ -102,6 +146,7 @@ krait_add_sec_mux(struct device *dev, in
|
||||
mux->shift = 2;
|
||||
mux->parent_map = sec_mux_map;
|
||||
mux->hw.init = &init;
|
||||
+ mux->safe_sel = 0;
|
||||
|
||||
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
|
||||
if (!init.name)
|
||||
@@ -117,6 +162,11 @@ krait_add_sec_mux(struct device *dev, in
|
||||
|
||||
clk = devm_clk_register(dev, &mux->hw);
|
||||
|
||||
+ ret = krait_notifier_register(dev, clk, mux);
|
||||
+ if (ret)
|
||||
+ goto unique_aux;
|
||||
+
|
||||
+unique_aux:
|
||||
if (unique_aux)
|
||||
kfree(sec_mux_list[0]);
|
||||
err_aux:
|
||||
@@ -128,6 +178,7 @@ static struct clk *
|
||||
krait_add_pri_mux(struct device *dev, int id, const char *s,
|
||||
unsigned int offset)
|
||||
{
|
||||
+ int ret;
|
||||
struct krait_mux_clk *mux;
|
||||
const char *p_names[3];
|
||||
struct clk_init_data init = {
|
||||
@@ -148,6 +199,7 @@ krait_add_pri_mux(struct device *dev, in
|
||||
mux->lpl = id >= 0;
|
||||
mux->parent_map = pri_mux_map;
|
||||
mux->hw.init = &init;
|
||||
+ mux->safe_sel = 2;
|
||||
|
||||
init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
|
||||
if (!init.name)
|
||||
@@ -173,6 +225,10 @@ krait_add_pri_mux(struct device *dev, in
|
||||
|
||||
clk = devm_clk_register(dev, &mux->hw);
|
||||
|
||||
+ ret = krait_notifier_register(dev, clk, mux);
|
||||
+ if (ret)
|
||||
+ goto err_p3;
|
||||
+err_p3:
|
||||
kfree(p_names[2]);
|
||||
err_p2:
|
||||
kfree(p_names[1]);
|
||||
@ -1,23 +0,0 @@
|
||||
From 58f8215f1d9397f9130657cc2c15a956bd99210e Mon Sep 17 00:00:00 2001
|
||||
From: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
Date: Wed, 13 Jul 2016 15:22:25 +0300
|
||||
Subject: [PATCH 44/69] clk: qcom: krait: Remove CLK_IS_ROOT
|
||||
|
||||
The flag CLK_IS_ROOT is no-op now. Remove it.
|
||||
|
||||
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
---
|
||||
drivers/clk/qcom/krait-cc.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/qcom/krait-cc.c
|
||||
+++ b/drivers/clk/qcom/krait-cc.c
|
||||
@@ -258,7 +258,7 @@ static int krait_cc_probe(struct platfor
|
||||
return -ENODEV;
|
||||
|
||||
/* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
|
||||
- clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1);
|
||||
+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
@ -1,7 +1,19 @@
|
||||
From 42eea6bc2858ab9649cf6931455e391e48939685 Mon Sep 17 00:00:00 2001
|
||||
From patchwork Fri Dec 8 09:42:29 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,11/12] cpufreq: Add module to register cpufreq on Krait CPUs
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102075
|
||||
Message-Id: <1512726150-7204-12-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:29 +0530
|
||||
|
||||
From: Stephen Boyd <sboyd@codeaurora.org>
|
||||
Date: Fri, 20 Mar 2015 23:45:31 -0700
|
||||
Subject: [PATCH 45/69] cpufreq: Add module to register cpufreq on Krait CPUs
|
||||
|
||||
Register a cpufreq-generic device whenever we detect that a
|
||||
"qcom,krait" compatible CPU is present in DT.
|
||||
@ -111,7 +123,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/pm_opp.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/cpufreq-dt.h>
|
||||
+#include "cpufreq-dt.h"
|
||||
+
|
||||
+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver)
|
||||
+{
|
||||
@ -227,7 +239,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
||||
+ }
|
||||
+
|
||||
+ snprintf(table_name, sizeof(table_name),
|
||||
+ "qcom,speed%d-pvs%d-bin-v%d", speed, pvs, pvs_ver);
|
||||
+ "qcom,speed%d-pvs%d-bin-v%d", speed, pvs, pvs_ver);
|
||||
+
|
||||
+ if (!of_find_property(np, table_name, &len))
|
||||
+ return -EINVAL;
|
||||
|
||||
@ -1,25 +1,31 @@
|
||||
ipq806x: support independent core clocks with kernel 4.9+
|
||||
From patchwork Fri Dec 8 09:42:30 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v4,12/12] cpufreq: dt: Reintroduce independent_clocks platform data
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10102073
|
||||
Message-Id: <1512726150-7204-13-git-send-email-sricharan@codeaurora.org>
|
||||
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
||||
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Fri, 8 Dec 2017 15:12:30 +0530
|
||||
|
||||
Add back support for the independent_clocks definition that has been
|
||||
removed between kernel 4.4 and 4.9 by upstream commits
|
||||
eb96924acddc709db58221c210ca05cd9effb1df and
|
||||
e86eee6bc2aaa6b3637f6497b26beee09a91bde9
|
||||
The Platform data was removed earlier by,
|
||||
'commit eb96924acddc ("cpufreq: dt: Kill platform-data")'
|
||||
since there were no users at that time.
|
||||
Now this is required when the each of the cpu clocks
|
||||
can be scaled independently, which is the case
|
||||
for krait cores. So reintroduce it.
|
||||
|
||||
* extend the new cpufreq_dt_platform_data definition in cpufreq-dt.h
|
||||
* use new cpufreq-dt.h in qcom-cpufreq.c
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
---
|
||||
drivers/cpufreq/cpufreq-dt.c | 7 ++++++-
|
||||
drivers/cpufreq/cpufreq-dt.h | 6 ++++++
|
||||
2 files changed, 12 insertions(+), 1 deletion(-)
|
||||
|
||||
Signed-off-by: Hannu Nyman <hannu.nyman@iki.fi>
|
||||
|
||||
--- a/drivers/cpufreq/cpufreq-dt.h
|
||||
+++ b/drivers/cpufreq/cpufreq-dt.h
|
||||
@@ -14,6 +14,7 @@
|
||||
|
||||
struct cpufreq_dt_platform_data {
|
||||
bool have_governor_per_policy;
|
||||
+ bool independent_clocks;
|
||||
};
|
||||
|
||||
#endif /* __CPUFREQ_DT_H__ */
|
||||
--- a/drivers/cpufreq/cpufreq-dt.c
|
||||
+++ b/drivers/cpufreq/cpufreq-dt.c
|
||||
@@ -221,7 +221,10 @@ static int cpufreq_init(struct cpufreq_p
|
||||
@ -38,19 +44,23 @@ Signed-off-by: Hannu Nyman <hannu.nyman@iki.fi>
|
||||
if (data && data->have_governor_per_policy)
|
||||
dt_cpufreq_driver.flags |= CPUFREQ_HAVE_GOVERNOR_PER_POLICY;
|
||||
|
||||
+ dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);
|
||||
+ dt_cpufreq_driver.driver_data = data;
|
||||
+
|
||||
ret = cpufreq_register_driver(&dt_cpufreq_driver);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "failed register driver: %d\n", ret);
|
||||
--- a/drivers/cpufreq/qcom-cpufreq.c
|
||||
+++ b/drivers/cpufreq/qcom-cpufreq.c
|
||||
@@ -20,7 +20,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_opp.h>
|
||||
#include <linux/slab.h>
|
||||
-#include <linux/cpufreq-dt.h>
|
||||
+#include "cpufreq-dt.h"
|
||||
--- a/drivers/cpufreq/cpufreq-dt.h
|
||||
+++ b/drivers/cpufreq/cpufreq-dt.h
|
||||
@@ -13,6 +13,12 @@
|
||||
#include <linux/types.h>
|
||||
|
||||
struct cpufreq_dt_platform_data {
|
||||
+ /*
|
||||
+ * True when each CPU has its own clock to control its
|
||||
+ * frequency, false when all CPUs are controlled by a single
|
||||
+ * clock.
|
||||
+ */
|
||||
+ bool independent_clocks;
|
||||
bool have_governor_per_policy;
|
||||
};
|
||||
|
||||
static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver)
|
||||
{
|
||||
|
||||
@ -1,372 +0,0 @@
|
||||
From f72c5aa18281c44945fea6181d0d816a7605505c Mon Sep 17 00:00:00 2001
|
||||
From: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
Date: Wed, 18 Mar 2015 17:23:29 +0200
|
||||
Subject: [PATCH 57/69] clk: qcom: Add regmap mux-div clocks support
|
||||
|
||||
Add support for hardware that can switch both parent clocks and divider
|
||||
at the same time. This avoids generating intermediate frequencies from
|
||||
either the old parent clock and new divider or new parent clock and
|
||||
old divider combinations.
|
||||
|
||||
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
---
|
||||
drivers/clk/qcom/Makefile | 1 +
|
||||
drivers/clk/qcom/clk-regmap-mux-div.c | 272 ++++++++++++++++++++++++++++++++++
|
||||
drivers/clk/qcom/clk-regmap-mux-div.h | 65 ++++++++
|
||||
3 files changed, 338 insertions(+)
|
||||
create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.c
|
||||
create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.h
|
||||
|
||||
--- a/drivers/clk/qcom/Makefile
|
||||
+++ b/drivers/clk/qcom/Makefile
|
||||
@@ -9,6 +9,7 @@ clk-qcom-y += clk-rcg2.o
|
||||
clk-qcom-y += clk-branch.o
|
||||
clk-qcom-y += clk-regmap-divider.o
|
||||
clk-qcom-y += clk-regmap-mux.o
|
||||
+clk-qcom-y += clk-regmap-mux-div.o
|
||||
clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
|
||||
clk-qcom-y += clk-hfpll.o
|
||||
clk-qcom-y += reset.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/qcom/clk-regmap-mux-div.c
|
||||
@@ -0,0 +1,272 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2015, Linaro Limited
|
||||
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * This software is licensed under the terms of the GNU General Public
|
||||
+ * License version 2, as published by the Free Software Foundation, and
|
||||
+ * may be copied, distributed, and modified under those terms.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/bitops.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/export.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/regmap.h>
|
||||
+
|
||||
+#include "clk-regmap-mux-div.h"
|
||||
+
|
||||
+#define CMD_RCGR 0x0
|
||||
+#define CMD_RCGR_UPDATE BIT(0)
|
||||
+#define CMD_RCGR_DIRTY_CFG BIT(4)
|
||||
+#define CMD_RCGR_ROOT_OFF BIT(31)
|
||||
+#define CFG_RCGR 0x4
|
||||
+
|
||||
+#define to_clk_regmap_mux_div(_hw) \
|
||||
+ container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)
|
||||
+
|
||||
+int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div)
|
||||
+{
|
||||
+ int ret, count;
|
||||
+ u32 val, mask;
|
||||
+ const char *name = clk_hw_get_name(&md->clkr.hw);
|
||||
+
|
||||
+ val = (div << md->hid_shift) | (src << md->src_shift);
|
||||
+ mask = ((BIT(md->hid_width) - 1) << md->hid_shift) |
|
||||
+ ((BIT(md->src_width) - 1) << md->src_shift);
|
||||
+
|
||||
+ ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset,
|
||||
+ mask, val);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset,
|
||||
+ CMD_RCGR_UPDATE, CMD_RCGR_UPDATE);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* Wait for update to take effect */
|
||||
+ for (count = 500; count > 0; count--) {
|
||||
+ ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset,
|
||||
+ &val);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ if (!(val & CMD_RCGR_UPDATE))
|
||||
+ return 0;
|
||||
+ udelay(1);
|
||||
+ }
|
||||
+
|
||||
+ pr_err("%s: RCG did not update its configuration", name);
|
||||
+ return -EBUSY;
|
||||
+}
|
||||
+
|
||||
+static void __mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
|
||||
+ u32 *div)
|
||||
+{
|
||||
+ u32 val, __div, __src;
|
||||
+ const char *name = clk_hw_get_name(&md->clkr.hw);
|
||||
+
|
||||
+ regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
|
||||
+
|
||||
+ if (val & CMD_RCGR_DIRTY_CFG) {
|
||||
+ pr_err("%s: RCG configuration is pending\n", name);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
|
||||
+ __src = (val >> md->src_shift);
|
||||
+ __src &= BIT(md->src_width) - 1;
|
||||
+ *src = __src;
|
||||
+
|
||||
+ __div = (val >> md->hid_shift);
|
||||
+ __div &= BIT(md->hid_width) - 1;
|
||||
+ *div = __div;
|
||||
+}
|
||||
+
|
||||
+static int mux_div_enable(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+
|
||||
+ return __mux_div_set_src_div(md, md->src, md->div);
|
||||
+}
|
||||
+
|
||||
+static inline bool is_better_rate(unsigned long req, unsigned long best,
|
||||
+ unsigned long new)
|
||||
+{
|
||||
+ return (req <= new && new < best) || (best < req && best < new);
|
||||
+}
|
||||
+
|
||||
+static int mux_div_determine_rate(struct clk_hw *hw,
|
||||
+ struct clk_rate_request *req)
|
||||
+{
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+ unsigned int i, div, max_div;
|
||||
+ unsigned long actual_rate, best_rate = 0;
|
||||
+ unsigned long req_rate = req->rate;
|
||||
+
|
||||
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
|
||||
+ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
|
||||
+ unsigned long parent_rate = clk_hw_get_rate(parent);
|
||||
+
|
||||
+ max_div = BIT(md->hid_width) - 1;
|
||||
+ for (div = 1; div < max_div; div++) {
|
||||
+ parent_rate = mult_frac(req_rate, div, 2);
|
||||
+ parent_rate = clk_hw_round_rate(parent, parent_rate);
|
||||
+ actual_rate = mult_frac(parent_rate, 2, div);
|
||||
+
|
||||
+ if (is_better_rate(req_rate, best_rate, actual_rate)) {
|
||||
+ best_rate = actual_rate;
|
||||
+ req->rate = best_rate;
|
||||
+ req->best_parent_rate = parent_rate;
|
||||
+ req->best_parent_hw = parent;
|
||||
+ }
|
||||
+
|
||||
+ if (actual_rate < req_rate || best_rate <= req_rate)
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (!best_rate)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
|
||||
+ unsigned long prate, u32 src)
|
||||
+{
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+ int ret;
|
||||
+ u32 div, max_div, best_src = 0, best_div = 0;
|
||||
+ unsigned int i;
|
||||
+ unsigned long actual_rate, best_rate = 0;
|
||||
+
|
||||
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
|
||||
+ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
|
||||
+ unsigned long parent_rate = clk_hw_get_rate(parent);
|
||||
+
|
||||
+ max_div = BIT(md->hid_width) - 1;
|
||||
+ for (div = 1; div < max_div; div++) {
|
||||
+ parent_rate = mult_frac(rate, div, 2);
|
||||
+ parent_rate = clk_hw_round_rate(parent, parent_rate);
|
||||
+ actual_rate = mult_frac(parent_rate, 2, div);
|
||||
+
|
||||
+ if (is_better_rate(rate, best_rate, actual_rate)) {
|
||||
+ best_rate = actual_rate;
|
||||
+ best_src = md->parent_map[i].cfg;
|
||||
+ best_div = div - 1;
|
||||
+ }
|
||||
+
|
||||
+ if (actual_rate < rate || best_rate <= rate)
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ ret = __mux_div_set_src_div(md, best_src, best_div);
|
||||
+ if (!ret) {
|
||||
+ md->div = best_div;
|
||||
+ md->src = best_src;
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static u8 mux_div_get_parent(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+ const char *name = clk_hw_get_name(hw);
|
||||
+ u32 i, div, src = 0;
|
||||
+
|
||||
+ __mux_div_get_src_div(md, &src, &div);
|
||||
+
|
||||
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++)
|
||||
+ if (src == md->parent_map[i].cfg)
|
||||
+ return i;
|
||||
+
|
||||
+ pr_err("%s: Can't find parent with src %d\n", name, src);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int mux_div_set_parent(struct clk_hw *hw, u8 index)
|
||||
+{
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+
|
||||
+ return __mux_div_set_src_div(md, md->parent_map[index].cfg, md->div);
|
||||
+}
|
||||
+
|
||||
+static int mux_div_set_rate(struct clk_hw *hw,
|
||||
+ unsigned long rate, unsigned long prate)
|
||||
+{
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+
|
||||
+ return __mux_div_set_rate_and_parent(hw, rate, prate, md->src);
|
||||
+}
|
||||
+
|
||||
+static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
|
||||
+ unsigned long prate, u8 index)
|
||||
+{
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+
|
||||
+ return __mux_div_set_rate_and_parent(hw, rate, prate,
|
||||
+ md->parent_map[index].cfg);
|
||||
+}
|
||||
+
|
||||
+static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
|
||||
+{
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+ u32 div, src;
|
||||
+ int i, num_parents = clk_hw_get_num_parents(hw);
|
||||
+ const char *name = clk_hw_get_name(hw);
|
||||
+
|
||||
+ __mux_div_get_src_div(md, &src, &div);
|
||||
+ for (i = 0; i < num_parents; i++)
|
||||
+ if (src == md->parent_map[i].cfg) {
|
||||
+ struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
|
||||
+ unsigned long parent_rate = clk_hw_get_rate(p);
|
||||
+
|
||||
+ return mult_frac(parent_rate, 2, div + 1);
|
||||
+ }
|
||||
+
|
||||
+ pr_err("%s: Can't find parent %d\n", name, src);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct clk_hw *mux_div_get_safe_parent(struct clk_hw *hw,
|
||||
+ unsigned long *safe_freq)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+
|
||||
+ if (md->safe_freq)
|
||||
+ *safe_freq = md->safe_freq;
|
||||
+
|
||||
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++)
|
||||
+ if (md->safe_src == md->parent_map[i].cfg)
|
||||
+ break;
|
||||
+
|
||||
+ return clk_hw_get_parent_by_index(hw, i);
|
||||
+}
|
||||
+
|
||||
+static void mux_div_disable(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
|
||||
+
|
||||
+ __mux_div_set_src_div(md, md->safe_src, md->safe_div);
|
||||
+}
|
||||
+
|
||||
+const struct clk_ops clk_regmap_mux_div_ops = {
|
||||
+ .enable = mux_div_enable,
|
||||
+ .disable = mux_div_disable,
|
||||
+ .get_parent = mux_div_get_parent,
|
||||
+ .set_parent = mux_div_set_parent,
|
||||
+ .set_rate = mux_div_set_rate,
|
||||
+ .set_rate_and_parent = mux_div_set_rate_and_parent,
|
||||
+ .determine_rate = mux_div_determine_rate,
|
||||
+ .recalc_rate = mux_div_recalc_rate,
|
||||
+ .get_safe_parent = mux_div_get_safe_parent,
|
||||
+};
|
||||
+EXPORT_SYMBOL_GPL(clk_regmap_mux_div_ops);
|
||||
--- /dev/null
|
||||
+++ b/drivers/clk/qcom/clk-regmap-mux-div.h
|
||||
@@ -0,0 +1,65 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2015, Linaro Limited
|
||||
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * This software is licensed under the terms of the GNU General Public
|
||||
+ * License version 2, as published by the Free Software Foundation, and
|
||||
+ * may be copied, distributed, and modified under those terms.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ */
|
||||
+
|
||||
+#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__
|
||||
+#define __QCOM_CLK_REGMAP_MUX_DIV_H__
|
||||
+
|
||||
+#include <linux/clk-provider.h>
|
||||
+#include "clk-rcg.h"
|
||||
+#include "clk-regmap.h"
|
||||
+
|
||||
+/**
|
||||
+ * struct mux_div_clk - combined mux/divider clock
|
||||
+ * @reg_offset: offset of the mux/divider register
|
||||
+ * @hid_width: number of bits in half integer divider
|
||||
+ * @hid_shift: lowest bit of hid value field
|
||||
+ * @src_width: number of bits in source select
|
||||
+ * @src_shift: lowest bit of source select field
|
||||
+ * @div: the divider raw configuration value
|
||||
+ * @src: the mux index which will be used if the clock is enabled
|
||||
+ * @safe_src: the safe source mux value we switch to, while the main PLL is
|
||||
+ * reconfigured
|
||||
+ * @safe_div: the safe divider value that we set, while the main PLL is
|
||||
+ * reconfigured
|
||||
+ * @safe_freq: When switching rates from A to B, the mux div clock will
|
||||
+ * instead switch from A -> safe_freq -> B. This allows the
|
||||
+ * mux_div clock to change rates while enabled, even if this
|
||||
+ * behavior is not supported by the parent clocks.
|
||||
+ * If changing the rate of parent A also causes the rate of
|
||||
+ * parent B to change, then safe_freq must be defined.
|
||||
+ * safe_freq is expected to have a source clock which is always
|
||||
+ * on and runs at only one rate.
|
||||
+ * @parent_map: pointer to parent_map struct
|
||||
+ * @clkr: handle between common and hardware-specific interfaces
|
||||
+ */
|
||||
+
|
||||
+struct clk_regmap_mux_div {
|
||||
+ u32 reg_offset;
|
||||
+ u32 hid_width;
|
||||
+ u32 hid_shift;
|
||||
+ u32 src_width;
|
||||
+ u32 src_shift;
|
||||
+ u32 div;
|
||||
+ u32 src;
|
||||
+ u32 safe_src;
|
||||
+ u32 safe_div;
|
||||
+ unsigned long safe_freq;
|
||||
+ const struct parent_map *parent_map;
|
||||
+ struct clk_regmap clkr;
|
||||
+};
|
||||
+
|
||||
+extern const struct clk_ops clk_regmap_mux_div_ops;
|
||||
+int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div);
|
||||
+
|
||||
+#endif
|
||||
@ -14,7 +14,7 @@ Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
|
||||
|
||||
--- a/drivers/clk/qcom/gcc-ipq806x.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq806x.c
|
||||
@@ -1234,6 +1234,8 @@ static struct clk_rcg prng_src = {
|
||||
@@ -1233,6 +1233,8 @@ static struct clk_rcg prng_src = {
|
||||
.parent_map = gcc_pxo_pll8_map,
|
||||
},
|
||||
.clkr = {
|
||||
|
||||
@ -15,7 +15,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
||||
# testing for a specific architecture or later rather impossible.
|
||||
arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
|
||||
-arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
|
||||
+arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15 -mtune=cortex-a15
|
||||
+arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15
|
||||
arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
|
||||
# Only override the compiler option if ARMv6. The ARMv6K extensions are
|
||||
# always available in ARMv7
|
||||
|
||||
@ -5,19 +5,18 @@ Subject: [PATCH 69/69] arm: boot: add dts files
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/arm/boot/dts/Makefile | 9 ++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
arch/arm/boot/dts/Makefile | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -618,7 +618,19 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
@@ -618,7 +618,18 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-apq8084-mtp.dtb \
|
||||
qcom-ipq4019-ap.dk01.1-c1.dtb \
|
||||
qcom-ipq4019-ap.dk04.1-c1.dtb \
|
||||
+ qcom-ipq4019-fritz4040.dtb \
|
||||
+ qcom-ipq4019-nbg6617.dtb \
|
||||
+ qcom-ipq4019-a42.dtb \
|
||||
+ qcom-ipq4019-rt-ac58u.dtb \
|
||||
+ qcom-ipq4019-rt-acrh17.dtb \
|
||||
qcom-ipq8064-ap148.dtb \
|
||||
+ qcom-ipq8064-c2600.dtb \
|
||||
+ qcom-ipq8064-d7800.dtb \
|
||||
|
||||
@ -0,0 +1,95 @@
|
||||
From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001
|
||||
From: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
Date: Tue, 19 Jul 2016 18:44:49 +0530
|
||||
Subject: PCI: qcom: Fixed IPQ806x specific clocks
|
||||
|
||||
Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e
|
||||
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
---
|
||||
drivers/pci/host/pcie-qcom.c | 38 +++++++++++++++++++++++++++++++++-----
|
||||
1 file changed, 33 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -53,6 +53,8 @@ struct qcom_pcie_resources_v0 {
|
||||
struct clk *iface_clk;
|
||||
struct clk *core_clk;
|
||||
struct clk *phy_clk;
|
||||
+ struct clk *aux_clk;
|
||||
+ struct clk *ref_clk;
|
||||
struct reset_control *pci_reset;
|
||||
struct reset_control *axi_reset;
|
||||
struct reset_control *ahb_reset;
|
||||
@@ -160,6 +162,14 @@ static int qcom_pcie_get_resources_v0(st
|
||||
if (IS_ERR(res->phy_clk))
|
||||
return PTR_ERR(res->phy_clk);
|
||||
|
||||
+ res->aux_clk = devm_clk_get(dev, "aux");
|
||||
+ if (IS_ERR(res->aux_clk))
|
||||
+ return PTR_ERR(res->aux_clk);
|
||||
+
|
||||
+ res->ref_clk = devm_clk_get(dev, "ref");
|
||||
+ if (IS_ERR(res->ref_clk))
|
||||
+ return PTR_ERR(res->ref_clk);
|
||||
+
|
||||
res->pci_reset = devm_reset_control_get(dev, "pci");
|
||||
if (IS_ERR(res->pci_reset))
|
||||
return PTR_ERR(res->pci_reset);
|
||||
@@ -227,6 +237,8 @@ static void qcom_pcie_deinit_v0(struct q
|
||||
clk_disable_unprepare(res->iface_clk);
|
||||
clk_disable_unprepare(res->core_clk);
|
||||
clk_disable_unprepare(res->phy_clk);
|
||||
+ clk_disable_unprepare(res->aux_clk);
|
||||
+ clk_disable_unprepare(res->ref_clk);
|
||||
regulator_disable(res->vdda);
|
||||
regulator_disable(res->vdda_phy);
|
||||
regulator_disable(res->vdda_refclk);
|
||||
@@ -269,16 +281,28 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
goto err_assert_ahb;
|
||||
}
|
||||
|
||||
+ ret = clk_prepare_enable(res->core_clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "cannot prepare/enable core clock\n");
|
||||
+ goto err_clk_core;
|
||||
+ }
|
||||
+
|
||||
ret = clk_prepare_enable(res->phy_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable phy clock\n");
|
||||
goto err_clk_phy;
|
||||
}
|
||||
|
||||
- ret = clk_prepare_enable(res->core_clk);
|
||||
+ ret = clk_prepare_enable(res->aux_clk);
|
||||
if (ret) {
|
||||
- dev_err(dev, "cannot prepare/enable core clock\n");
|
||||
- goto err_clk_core;
|
||||
+ dev_err(dev, "cannot prepare/enable aux clock\n");
|
||||
+ goto err_clk_aux;
|
||||
+ }
|
||||
+
|
||||
+ ret = clk_prepare_enable(res->ref_clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "cannot prepare/enable ref clock\n");
|
||||
+ goto err_clk_ref;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(res->ahb_reset);
|
||||
@@ -327,10 +351,14 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
return 0;
|
||||
|
||||
err_deassert_ahb:
|
||||
- clk_disable_unprepare(res->core_clk);
|
||||
-err_clk_core:
|
||||
+ clk_disable_unprepare(res->ref_clk);
|
||||
+err_clk_ref:
|
||||
+ clk_disable_unprepare(res->aux_clk);
|
||||
+err_clk_aux:
|
||||
clk_disable_unprepare(res->phy_clk);
|
||||
err_clk_phy:
|
||||
+ clk_disable_unprepare(res->core_clk);
|
||||
+err_clk_core:
|
||||
clk_disable_unprepare(res->iface_clk);
|
||||
err_assert_ahb:
|
||||
regulator_disable(res->vdda_phy);
|
||||
@ -0,0 +1,85 @@
|
||||
From 490d103232287eb51c92c49a4ef8865fd0a9d59e Mon Sep 17 00:00:00 2001
|
||||
From: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
Date: Tue, 19 Jul 2016 18:58:18 +0530
|
||||
Subject: PCI: qcom: Fixed IPQ806x PCIE reset changes
|
||||
|
||||
Change-Id: Ia6590e960b9754b1e8b7a51f318788cd63e9e321
|
||||
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
---
|
||||
drivers/pci/host/pcie-qcom.c | 24 +++++++++++++++++++-----
|
||||
1 file changed, 19 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -60,6 +60,7 @@ struct qcom_pcie_resources_v0 {
|
||||
struct reset_control *ahb_reset;
|
||||
struct reset_control *por_reset;
|
||||
struct reset_control *phy_reset;
|
||||
+ struct reset_control *ext_reset;
|
||||
struct regulator *vdda;
|
||||
struct regulator *vdda_phy;
|
||||
struct regulator *vdda_refclk;
|
||||
@@ -190,6 +191,10 @@ static int qcom_pcie_get_resources_v0(st
|
||||
if (IS_ERR(res->phy_reset))
|
||||
return PTR_ERR(res->phy_reset);
|
||||
|
||||
+ res->ext_reset = devm_reset_control_get(dev, "ext");
|
||||
+ if (IS_ERR(res->ext_reset))
|
||||
+ return PTR_ERR(res->ext_reset);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -234,6 +239,7 @@ static void qcom_pcie_deinit_v0(struct q
|
||||
reset_control_assert(res->ahb_reset);
|
||||
reset_control_assert(res->por_reset);
|
||||
reset_control_assert(res->pci_reset);
|
||||
+ reset_control_assert(res->ext_reset);
|
||||
clk_disable_unprepare(res->iface_clk);
|
||||
clk_disable_unprepare(res->core_clk);
|
||||
clk_disable_unprepare(res->phy_clk);
|
||||
@@ -251,6 +257,12 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
+ ret = reset_control_assert(res->ahb_reset);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "cannot assert ahb reset\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
ret = regulator_enable(res->vdda);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot enable vdda regulator\n");
|
||||
@@ -269,16 +281,16 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
goto err_vdda_phy;
|
||||
}
|
||||
|
||||
- ret = reset_control_assert(res->ahb_reset);
|
||||
+ ret = reset_control_deassert(res->ext_reset);
|
||||
if (ret) {
|
||||
- dev_err(dev, "cannot assert ahb reset\n");
|
||||
- goto err_assert_ahb;
|
||||
+ dev_err(dev, "cannot assert ext reset\n");
|
||||
+ goto err_reset_ext;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(res->iface_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable iface clock\n");
|
||||
- goto err_assert_ahb;
|
||||
+ goto err_iface;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(res->core_clk);
|
||||
@@ -360,7 +372,9 @@ err_clk_phy:
|
||||
clk_disable_unprepare(res->core_clk);
|
||||
err_clk_core:
|
||||
clk_disable_unprepare(res->iface_clk);
|
||||
-err_assert_ahb:
|
||||
+err_iface:
|
||||
+ reset_control_assert(res->ext_reset);
|
||||
+err_reset_ext:
|
||||
regulator_disable(res->vdda_phy);
|
||||
err_vdda_phy:
|
||||
regulator_disable(res->vdda_refclk);
|
||||
@ -0,0 +1,127 @@
|
||||
From eddd13215d0f2b549ebc5f0e8796d5b1231f90a0 Mon Sep 17 00:00:00 2001
|
||||
From: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
Date: Tue, 19 Jul 2016 19:58:22 +0530
|
||||
Subject: PCI: qcom: Fixed IPQ806x PCIE init changes
|
||||
|
||||
Change-Id: Ic319b1aec27a47809284759f8fcb6a8815b7cf7e
|
||||
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
---
|
||||
drivers/pci/host/pcie-qcom.c | 62 +++++++++++++++++++++++++++++++++++++-------
|
||||
1 file changed, 53 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -37,7 +37,13 @@
|
||||
#include "pcie-designware.h"
|
||||
|
||||
#define PCIE20_PARF_PHY_CTRL 0x40
|
||||
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16)
|
||||
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
|
||||
+
|
||||
#define PCIE20_PARF_PHY_REFCLK 0x4C
|
||||
+#define REF_SSP_EN BIT(16)
|
||||
+#define REF_USE_PAD BIT(12)
|
||||
+
|
||||
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
|
||||
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
|
||||
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
|
||||
@@ -48,6 +54,18 @@
|
||||
#define PCIE20_CAP 0x70
|
||||
|
||||
#define PERST_DELAY_US 1000
|
||||
+/* PARF registers */
|
||||
+#define PCIE20_PARF_PCS_DEEMPH 0x34
|
||||
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16)
|
||||
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8)
|
||||
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0)
|
||||
+
|
||||
+#define PCIE20_PARF_PCS_SWING 0x38
|
||||
+#define PCS_SWING_TX_SWING_FULL(x) (x << 8)
|
||||
+#define PCS_SWING_TX_SWING_LOW(x) (x << 0)
|
||||
+
|
||||
+#define PCIE20_PARF_CONFIG_BITS 0x50
|
||||
+#define PHY_RX0_EQ(x) (x << 24)
|
||||
|
||||
struct qcom_pcie_resources_v0 {
|
||||
struct clk *iface_clk;
|
||||
@@ -64,6 +82,7 @@ struct qcom_pcie_resources_v0 {
|
||||
struct regulator *vdda;
|
||||
struct regulator *vdda_phy;
|
||||
struct regulator *vdda_refclk;
|
||||
+ uint8_t phy_tx0_term_offset;
|
||||
};
|
||||
|
||||
struct qcom_pcie_resources_v1 {
|
||||
@@ -100,6 +119,16 @@ struct qcom_pcie {
|
||||
|
||||
#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
|
||||
|
||||
+static inline void
|
||||
+writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
|
||||
+{
|
||||
+ u32 val = readl(addr);
|
||||
+
|
||||
+ val &= ~clear_mask;
|
||||
+ val |= set_mask;
|
||||
+ writel(val, addr);
|
||||
+}
|
||||
+
|
||||
static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
|
||||
{
|
||||
gpiod_set_value(pcie->reset, 1);
|
||||
@@ -195,6 +224,10 @@ static int qcom_pcie_get_resources_v0(st
|
||||
if (IS_ERR(res->ext_reset))
|
||||
return PTR_ERR(res->ext_reset);
|
||||
|
||||
+ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
|
||||
+ &res->phy_tx0_term_offset))
|
||||
+ res->phy_tx0_term_offset = 0;
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -254,7 +287,6 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
{
|
||||
struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
|
||||
struct device *dev = pcie->pp.dev;
|
||||
- u32 val;
|
||||
int ret;
|
||||
|
||||
ret = reset_control_assert(res->ahb_reset);
|
||||
@@ -323,15 +355,27 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
goto err_deassert_ahb;
|
||||
}
|
||||
|
||||
- /* enable PCIe clocks and resets */
|
||||
- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
|
||||
- val &= ~BIT(0);
|
||||
- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
|
||||
-
|
||||
- /* enable external reference clock */
|
||||
- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
|
||||
- val |= BIT(16);
|
||||
- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
|
||||
+ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
|
||||
+
|
||||
+ /* Set Tx termination offset */
|
||||
+ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL,
|
||||
+ PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
|
||||
+ PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
|
||||
+
|
||||
+ /* PARF programming */
|
||||
+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
|
||||
+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
|
||||
+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
|
||||
+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
|
||||
+ writel(PCS_SWING_TX_SWING_FULL(0x78) |
|
||||
+ PCS_SWING_TX_SWING_LOW(0x78),
|
||||
+ pcie->parf + PCIE20_PARF_PCS_SWING);
|
||||
+ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
|
||||
+
|
||||
+ /* Enable reference clock */
|
||||
+ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK,
|
||||
+ REF_USE_PAD, REF_SSP_EN);
|
||||
+
|
||||
|
||||
ret = reset_control_deassert(res->phy_reset);
|
||||
if (ret) {
|
||||
@ -0,0 +1,68 @@
|
||||
From e833cdb5c792912d459773cc23153e5d78875d34 Mon Sep 17 00:00:00 2001
|
||||
From: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
Date: Tue, 19 Jul 2016 20:05:25 +0530
|
||||
Subject: PCIE: designware: Fixed PCI host init
|
||||
|
||||
Change-Id: I949b302d77199fc09342acf26b7bb45a7ec467ee
|
||||
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
---
|
||||
drivers/pci/host/pcie-designware.c | 9 +++++++--
|
||||
drivers/pci/host/pcie-designware.h | 2 +-
|
||||
drivers/pci/host/pcie-qcom.c | 5 +++--
|
||||
3 files changed, 11 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/pci/host/pcie-designware.c
|
||||
+++ b/drivers/pci/host/pcie-designware.c
|
||||
@@ -637,8 +637,13 @@ int dw_pcie_host_init(struct pcie_port *
|
||||
}
|
||||
}
|
||||
|
||||
- if (pp->ops->host_init)
|
||||
- pp->ops->host_init(pp);
|
||||
+ if (pp->ops->host_init) {
|
||||
+ ret = pp->ops->host_init(pp);
|
||||
+ if (ret) {
|
||||
+ dev_err(pp->dev, "hostinit failed\n");
|
||||
+ return 0;
|
||||
+ }
|
||||
+ }
|
||||
|
||||
pp->root_bus_nr = pp->busn->start;
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
--- a/drivers/pci/host/pcie-designware.h
|
||||
+++ b/drivers/pci/host/pcie-designware.h
|
||||
@@ -63,7 +63,7 @@ struct pcie_host_ops {
|
||||
int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
|
||||
unsigned int devfn, int where, int size, u32 val);
|
||||
int (*link_up)(struct pcie_port *pp);
|
||||
- void (*host_init)(struct pcie_port *pp);
|
||||
+ int (*host_init)(struct pcie_port *pp);
|
||||
void (*msi_set_irq)(struct pcie_port *pp, int irq);
|
||||
void (*msi_clear_irq)(struct pcie_port *pp, int irq);
|
||||
phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -515,7 +515,7 @@ static int qcom_pcie_link_up(struct pcie
|
||||
return !!(val & PCI_EXP_LNKSTA_DLLLA);
|
||||
}
|
||||
|
||||
-static void qcom_pcie_host_init(struct pcie_port *pp)
|
||||
+static int qcom_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
struct qcom_pcie *pcie = to_qcom_pcie(pp);
|
||||
int ret;
|
||||
@@ -541,12 +541,13 @@ static void qcom_pcie_host_init(struct p
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
- return;
|
||||
+ return 0;
|
||||
err:
|
||||
qcom_ep_reset_assert(pcie);
|
||||
phy_power_off(pcie->phy);
|
||||
err_deinit:
|
||||
pcie->ops->deinit(pcie);
|
||||
+ return ret;
|
||||
}
|
||||
|
||||
static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
|
||||
@ -0,0 +1,113 @@
|
||||
From d27c303e828d7e42f339a459d2abfe30c51698e9 Mon Sep 17 00:00:00 2001
|
||||
From: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
Date: Tue, 26 Jul 2016 12:28:31 +0530
|
||||
Subject: PCI: qcom: Programming the PCIE iATU for IPQ806x
|
||||
|
||||
Resolved PCIE EP detection errors caused due to missing iATU programming.
|
||||
|
||||
Change-Id: Ie95c0f8cb940abc0192a8a3c4e825ddba54b72fe
|
||||
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
---
|
||||
drivers/pci/host/pcie-qcom.c | 77 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 77 insertions(+)
|
||||
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -52,6 +52,29 @@
|
||||
#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
|
||||
|
||||
#define PCIE20_CAP 0x70
|
||||
+#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
|
||||
+
|
||||
+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
|
||||
+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
|
||||
+
|
||||
+#define PCIE20_PLR_IATU_VIEWPORT 0x900
|
||||
+#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31)
|
||||
+#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0)
|
||||
+
|
||||
+#define PCIE20_PLR_IATU_CTRL1 0x904
|
||||
+#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0)
|
||||
+#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0)
|
||||
+
|
||||
+#define PCIE20_PLR_IATU_CTRL2 0x908
|
||||
+#define PCIE20_PLR_IATU_ENABLE BIT(31)
|
||||
+
|
||||
+#define PCIE20_PLR_IATU_LBAR 0x90C
|
||||
+#define PCIE20_PLR_IATU_UBAR 0x910
|
||||
+#define PCIE20_PLR_IATU_LAR 0x914
|
||||
+#define PCIE20_PLR_IATU_LTAR 0x918
|
||||
+#define PCIE20_PLR_IATU_UTAR 0x91c
|
||||
+
|
||||
+#define MSM_PCIE_DEV_CFG_ADDR 0x01000000
|
||||
|
||||
#define PERST_DELAY_US 1000
|
||||
/* PARF registers */
|
||||
@@ -163,6 +186,57 @@ static int qcom_pcie_establish_link(stru
|
||||
return dw_pcie_wait_for_link(&pcie->pp);
|
||||
}
|
||||
|
||||
+static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
|
||||
+{
|
||||
+ struct pcie_port *pp = &pcie->pp;
|
||||
+
|
||||
+ /*
|
||||
+ * program and enable address translation region 0 (device config
|
||||
+ * address space); region type config;
|
||||
+ * axi config address range to device config address range
|
||||
+ */
|
||||
+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
|
||||
+ PCIE20_PLR_IATU_REGION_INDEX(0),
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
|
||||
+
|
||||
+ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
|
||||
+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
|
||||
+ writel(pp->cfg0_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
|
||||
+ writel((pp->cfg0_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
|
||||
+ writel((pp->cfg0_base + pp->cfg0_size - 1),
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
|
||||
+ writel(busdev, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
|
||||
+ writel(0, pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
|
||||
+}
|
||||
+
|
||||
+static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
|
||||
+{
|
||||
+ struct pcie_port *pp = &pcie->pp;
|
||||
+
|
||||
+ /*
|
||||
+ * program and enable address translation region 2 (device resource
|
||||
+ * address space); region type memory;
|
||||
+ * axi device bar address range to device bar address range
|
||||
+ */
|
||||
+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
|
||||
+ PCIE20_PLR_IATU_REGION_INDEX(2),
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
|
||||
+
|
||||
+ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
|
||||
+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
|
||||
+ writel(pp->mem_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
|
||||
+ writel((pp->mem_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
|
||||
+ writel(pp->mem_base + pp->mem_size - 1,
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
|
||||
+ writel(pp->mem_bus_addr, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
|
||||
+ writel(upper_32_bits(pp->mem_bus_addr),
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
|
||||
+
|
||||
+ /* 256B PCIE buffer setting */
|
||||
+ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
|
||||
+ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
|
||||
+}
|
||||
+
|
||||
static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
|
||||
{
|
||||
struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
|
||||
@@ -404,6 +478,9 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
/* wait for clock acquisition */
|
||||
usleep_range(1000, 1500);
|
||||
|
||||
+ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
|
||||
+ qcom_pcie_prog_viewport_mem2_outbound(pcie);
|
||||
+
|
||||
return 0;
|
||||
|
||||
err_deassert_ahb:
|
||||
@ -0,0 +1,61 @@
|
||||
From 4910cfd150342ec7b038892262923c725a9c4001 Mon Sep 17 00:00:00 2001
|
||||
From: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
Date: Wed, 7 Sep 2016 16:44:28 +0530
|
||||
Subject: PCI: qcom: Force GEN1 support
|
||||
|
||||
Change-Id: Ica54ddb737d7b851469deab1745f54bf431bd3f0
|
||||
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
|
||||
---
|
||||
drivers/pci/host/pcie-qcom.c | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -90,6 +90,8 @@
|
||||
#define PCIE20_PARF_CONFIG_BITS 0x50
|
||||
#define PHY_RX0_EQ(x) (x << 24)
|
||||
|
||||
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
|
||||
+
|
||||
struct qcom_pcie_resources_v0 {
|
||||
struct clk *iface_clk;
|
||||
struct clk *core_clk;
|
||||
@@ -138,6 +140,7 @@ struct qcom_pcie {
|
||||
struct phy *phy;
|
||||
struct gpio_desc *reset;
|
||||
struct qcom_pcie_ops *ops;
|
||||
+ uint32_t force_gen1;
|
||||
};
|
||||
|
||||
#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
|
||||
@@ -477,6 +480,11 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
|
||||
/* wait for clock acquisition */
|
||||
usleep_range(1000, 1500);
|
||||
+ if (pcie->force_gen1) {
|
||||
+ writel_relaxed((readl_relaxed(
|
||||
+ pcie->pp.dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
|
||||
+ pcie->pp.dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
|
||||
+ }
|
||||
|
||||
qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
|
||||
qcom_pcie_prog_viewport_mem2_outbound(pcie);
|
||||
@@ -666,6 +674,8 @@ static int qcom_pcie_probe(struct platfo
|
||||
struct qcom_pcie *pcie;
|
||||
struct pcie_port *pp;
|
||||
int ret;
|
||||
+ uint32_t force_gen1 = 0;
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
|
||||
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
@@ -678,6 +688,9 @@ static int qcom_pcie_probe(struct platfo
|
||||
if (IS_ERR(pcie->reset))
|
||||
return PTR_ERR(pcie->reset);
|
||||
|
||||
+ of_property_read_u32(np, "force_gen1", &force_gen1);
|
||||
+ pcie->force_gen1 = force_gen1;
|
||||
+
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
|
||||
pcie->parf = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(pcie->parf))
|
||||
@ -0,0 +1,69 @@
|
||||
From edff8f777c6321ca89bb950a382f409c4a126e28 Mon Sep 17 00:00:00 2001
|
||||
From: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
|
||||
Date: Thu, 15 Dec 2016 17:38:18 +0530
|
||||
Subject: pcie: Set PCIE MRRS and MPS to 256B
|
||||
|
||||
Set Max Read Request Size and Max Payload Size to 256 bytes,
|
||||
per chip team recommendation.
|
||||
|
||||
Change-Id: I097004be2ced1b3096ffc10c318aae0b2bb155e8
|
||||
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
|
||||
---
|
||||
drivers/pci/host/pcie-qcom.c | 37 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 37 insertions(+)
|
||||
|
||||
(limited to 'drivers/pci/host/pcie-qcom.c')
|
||||
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -92,6 +92,14 @@
|
||||
|
||||
#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
|
||||
|
||||
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
|
||||
+#define __mask(a, b) (((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1))
|
||||
+#define PCIE20_DEV_CAS 0x78
|
||||
+#define PCIE20_MRRS_MASK __mask(14, 12)
|
||||
+#define PCIE20_MRRS(x) __set(x, 14, 12)
|
||||
+#define PCIE20_MPS_MASK __mask(7, 5)
|
||||
+#define PCIE20_MPS(x) __set(x, 7, 5)
|
||||
+
|
||||
struct qcom_pcie_resources_v0 {
|
||||
struct clk *iface_clk;
|
||||
struct clk *core_clk;
|
||||
@@ -745,6 +753,35 @@ static int qcom_pcie_probe(struct platfo
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void qcom_pcie_fixup_final(struct pci_dev *dev)
|
||||
+{
|
||||
+ int cap, err;
|
||||
+ u16 ctl, reg_val;
|
||||
+
|
||||
+ cap = pci_pcie_cap(dev);
|
||||
+ if (!cap)
|
||||
+ return;
|
||||
+
|
||||
+ err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
||||
+
|
||||
+ if (err)
|
||||
+ return;
|
||||
+
|
||||
+ reg_val = ctl;
|
||||
+
|
||||
+ if (((reg_val & PCIE20_MRRS_MASK) >> 12) > 1)
|
||||
+ reg_val = (reg_val & ~(PCIE20_MRRS_MASK)) | PCIE20_MRRS(0x1);
|
||||
+
|
||||
+ if (((ctl & PCIE20_MPS_MASK) >> 5) > 1)
|
||||
+ reg_val = (reg_val & ~(PCIE20_MPS_MASK)) | PCIE20_MPS(0x1);
|
||||
+
|
||||
+ err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, reg_val);
|
||||
+
|
||||
+ if (err)
|
||||
+ pr_err("pcie config write failed %d\n", err);
|
||||
+}
|
||||
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final);
|
||||
+
|
||||
static const struct of_device_id qcom_pcie_match[] = {
|
||||
{ .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
|
||||
{ .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
|
||||
@ -0,0 +1,91 @@
|
||||
From b74bab6186131eea09459eedf5d737645a3559c9 Mon Sep 17 00:00:00 2001
|
||||
From: Abhishek Sahu <absahu@codeaurora.org>
|
||||
Date: Thu, 22 Dec 2016 11:18:45 +0530
|
||||
Subject: pcie: qcom: Fixed pcie_phy_clk branch issue
|
||||
|
||||
Following backtraces are observed in PCIe deinit operation.
|
||||
|
||||
Hardware name: Qualcomm (Flattened Device Tree)
|
||||
(unwind_backtrace) from [] (show_stack+0x10/0x14)
|
||||
(show_stack) from [] (dump_stack+0x84/0x98)
|
||||
(dump_stack) from [] (warn_slowpath_common+0x9c/0xb8)
|
||||
(warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
|
||||
(warn_slowpath_fmt) from [] (clk_branch_wait+0x114/0x120)
|
||||
(clk_branch_wait) from [] (clk_core_disable+0xd0/0x1f4)
|
||||
(clk_core_disable) from [] (clk_disable+0x24/0x30)
|
||||
(clk_disable) from [] (qcom_pcie_deinit_v0+0x6c/0xb8)
|
||||
(qcom_pcie_deinit_v0) from [] (qcom_pcie_host_init+0xe0/0xe8)
|
||||
(qcom_pcie_host_init) from [] (dw_pcie_host_init+0x3b0/0x538)
|
||||
(dw_pcie_host_init) from [] (qcom_pcie_probe+0x20c/0x2e4)
|
||||
|
||||
pcie_phy_clk is generated for PCIe controller itself and the
|
||||
GCC controls its branch operation. This error is coming since
|
||||
the assert operations turn off the parent clock before branch
|
||||
clock. Now this patch moves clk_disable_unprepare before assert
|
||||
operations.
|
||||
|
||||
Similarly, during probe function, the clock branch operation
|
||||
should be done after dessert operation. Currently, it does not
|
||||
generate any error since bootloader enables the pcie_phy_clk
|
||||
but the same error is coming during probe, if bootloader
|
||||
disables pcie_phy_clk.
|
||||
|
||||
Change-Id: Ib29c154d10eb64363d9cc982ce5fd8107af5627d
|
||||
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
|
||||
---
|
||||
drivers/pci/host/pcie-qcom.c | 16 +++++++---------
|
||||
1 file changed, 7 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -352,6 +352,7 @@ static void qcom_pcie_deinit_v0(struct q
|
||||
{
|
||||
struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
|
||||
|
||||
+ clk_disable_unprepare(res->phy_clk);
|
||||
reset_control_assert(res->pci_reset);
|
||||
reset_control_assert(res->axi_reset);
|
||||
reset_control_assert(res->ahb_reset);
|
||||
@@ -360,7 +361,6 @@ static void qcom_pcie_deinit_v0(struct q
|
||||
reset_control_assert(res->ext_reset);
|
||||
clk_disable_unprepare(res->iface_clk);
|
||||
clk_disable_unprepare(res->core_clk);
|
||||
- clk_disable_unprepare(res->phy_clk);
|
||||
clk_disable_unprepare(res->aux_clk);
|
||||
clk_disable_unprepare(res->ref_clk);
|
||||
regulator_disable(res->vdda);
|
||||
@@ -416,12 +416,6 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
goto err_clk_core;
|
||||
}
|
||||
|
||||
- ret = clk_prepare_enable(res->phy_clk);
|
||||
- if (ret) {
|
||||
- dev_err(dev, "cannot prepare/enable phy clock\n");
|
||||
- goto err_clk_phy;
|
||||
- }
|
||||
-
|
||||
ret = clk_prepare_enable(res->aux_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable aux clock\n");
|
||||
@@ -486,6 +480,12 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ ret = clk_prepare_enable(res->phy_clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "cannot prepare/enable phy clock\n");
|
||||
+ goto err_deassert_ahb;
|
||||
+ }
|
||||
+
|
||||
/* wait for clock acquisition */
|
||||
usleep_range(1000, 1500);
|
||||
if (pcie->force_gen1) {
|
||||
@@ -504,8 +504,6 @@ err_deassert_ahb:
|
||||
err_clk_ref:
|
||||
clk_disable_unprepare(res->aux_clk);
|
||||
err_clk_aux:
|
||||
- clk_disable_unprepare(res->phy_clk);
|
||||
-err_clk_phy:
|
||||
clk_disable_unprepare(res->core_clk);
|
||||
err_clk_core:
|
||||
clk_disable_unprepare(res->iface_clk);
|
||||
@ -0,0 +1,25 @@
|
||||
From 1a9c48123bd09f75562b6a2ee0f0a7b2d533cd45 Mon Sep 17 00:00:00 2001
|
||||
From: Abhishek Sahu <absahu@codeaurora.org>
|
||||
Date: Thu, 22 Dec 2016 11:50:49 +0530
|
||||
Subject: pcie: qcom: change duplicate pci reset to phy reset
|
||||
|
||||
The deinit issues reset_control_assert for pci twice and
|
||||
does not contain phy reset.
|
||||
|
||||
Change-Id: Iba849963c7e5f9a2a1063f0e2e89635df70b8a99
|
||||
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
|
||||
---
|
||||
drivers/pci/host/pcie-qcom.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -353,7 +353,7 @@ static void qcom_pcie_deinit_v0(struct q
|
||||
struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
|
||||
|
||||
clk_disable_unprepare(res->phy_clk);
|
||||
- reset_control_assert(res->pci_reset);
|
||||
+ reset_control_assert(res->phy_reset);
|
||||
reset_control_assert(res->axi_reset);
|
||||
reset_control_assert(res->ahb_reset);
|
||||
reset_control_assert(res->por_reset);
|
||||
@ -1,308 +0,0 @@
|
||||
--- a/drivers/pci/host/pcie-qcom.c
|
||||
+++ b/drivers/pci/host/pcie-qcom.c
|
||||
@@ -36,8 +36,50 @@
|
||||
|
||||
#include "pcie-designware.h"
|
||||
|
||||
+/* DBI registers */
|
||||
+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
|
||||
+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
|
||||
+
|
||||
+#define PCIE20_PLR_IATU_VIEWPORT 0x900
|
||||
+#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31)
|
||||
+#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0)
|
||||
+
|
||||
+#define PCIE20_PLR_IATU_CTRL1 0x904
|
||||
+#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0)
|
||||
+#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0)
|
||||
+
|
||||
+#define PCIE20_PLR_IATU_CTRL2 0x908
|
||||
+#define PCIE20_PLR_IATU_ENABLE BIT(31)
|
||||
+
|
||||
+#define PCIE20_PLR_IATU_LBAR 0x90C
|
||||
+#define PCIE20_PLR_IATU_UBAR 0x910
|
||||
+#define PCIE20_PLR_IATU_LAR 0x914
|
||||
+#define PCIE20_PLR_IATU_LTAR 0x918
|
||||
+#define PCIE20_PLR_IATU_UTAR 0x91c
|
||||
+
|
||||
+#define MSM_PCIE_DEV_CFG_ADDR 0x01000000
|
||||
+
|
||||
+/* PARF registers */
|
||||
+#define PCIE20_PARF_PCS_DEEMPH 0x34
|
||||
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16)
|
||||
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8)
|
||||
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0)
|
||||
+
|
||||
+#define PCIE20_PARF_PCS_SWING 0x38
|
||||
+#define PCS_SWING_TX_SWING_FULL(x) (x << 8)
|
||||
+#define PCS_SWING_TX_SWING_LOW(x) (x << 0)
|
||||
+
|
||||
#define PCIE20_PARF_PHY_CTRL 0x40
|
||||
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16)
|
||||
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
|
||||
+
|
||||
#define PCIE20_PARF_PHY_REFCLK 0x4C
|
||||
+#define REF_SSP_EN BIT(16)
|
||||
+#define REF_USE_PAD BIT(12)
|
||||
+
|
||||
+#define PCIE20_PARF_CONFIG_BITS 0x50
|
||||
+#define PHY_RX0_EQ(x) (x << 24)
|
||||
+
|
||||
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
|
||||
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
|
||||
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
|
||||
@@ -53,14 +95,18 @@ struct qcom_pcie_resources_v0 {
|
||||
struct clk *iface_clk;
|
||||
struct clk *core_clk;
|
||||
struct clk *phy_clk;
|
||||
+ struct clk *aux_clk;
|
||||
+ struct clk *ref_clk;
|
||||
struct reset_control *pci_reset;
|
||||
struct reset_control *axi_reset;
|
||||
struct reset_control *ahb_reset;
|
||||
struct reset_control *por_reset;
|
||||
struct reset_control *phy_reset;
|
||||
+ struct reset_control *ext_reset;
|
||||
struct regulator *vdda;
|
||||
struct regulator *vdda_phy;
|
||||
struct regulator *vdda_refclk;
|
||||
+ uint8_t phy_tx0_term_offset;
|
||||
};
|
||||
|
||||
struct qcom_pcie_resources_v1 {
|
||||
@@ -82,6 +128,7 @@ struct qcom_pcie;
|
||||
struct qcom_pcie_ops {
|
||||
int (*get_resources)(struct qcom_pcie *pcie);
|
||||
int (*init)(struct qcom_pcie *pcie);
|
||||
+ void (*configure)(struct qcom_pcie *pcie);
|
||||
void (*deinit)(struct qcom_pcie *pcie);
|
||||
};
|
||||
|
||||
@@ -160,6 +207,14 @@ static int qcom_pcie_get_resources_v0(st
|
||||
if (IS_ERR(res->phy_clk))
|
||||
return PTR_ERR(res->phy_clk);
|
||||
|
||||
+ res->aux_clk = devm_clk_get(dev, "aux");
|
||||
+ if (IS_ERR(res->aux_clk))
|
||||
+ return PTR_ERR(res->aux_clk);
|
||||
+
|
||||
+ res->ref_clk = devm_clk_get(dev, "ref");
|
||||
+ if (IS_ERR(res->ref_clk))
|
||||
+ return PTR_ERR(res->ref_clk);
|
||||
+
|
||||
res->pci_reset = devm_reset_control_get(dev, "pci");
|
||||
if (IS_ERR(res->pci_reset))
|
||||
return PTR_ERR(res->pci_reset);
|
||||
@@ -180,6 +235,14 @@ static int qcom_pcie_get_resources_v0(st
|
||||
if (IS_ERR(res->phy_reset))
|
||||
return PTR_ERR(res->phy_reset);
|
||||
|
||||
+ res->ext_reset = devm_reset_control_get(dev, "ext");
|
||||
+ if (IS_ERR(res->ext_reset))
|
||||
+ return PTR_ERR(res->ext_reset);
|
||||
+
|
||||
+ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
|
||||
+ &res->phy_tx0_term_offset))
|
||||
+ res->phy_tx0_term_offset = 0;
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -223,15 +286,69 @@ static void qcom_pcie_deinit_v0(struct q
|
||||
reset_control_assert(res->axi_reset);
|
||||
reset_control_assert(res->ahb_reset);
|
||||
reset_control_assert(res->por_reset);
|
||||
- reset_control_assert(res->pci_reset);
|
||||
+ reset_control_assert(res->phy_reset);
|
||||
+ reset_control_assert(res->ext_reset);
|
||||
clk_disable_unprepare(res->iface_clk);
|
||||
clk_disable_unprepare(res->core_clk);
|
||||
clk_disable_unprepare(res->phy_clk);
|
||||
+ clk_disable_unprepare(res->aux_clk);
|
||||
+ clk_disable_unprepare(res->ref_clk);
|
||||
regulator_disable(res->vdda);
|
||||
regulator_disable(res->vdda_phy);
|
||||
regulator_disable(res->vdda_refclk);
|
||||
}
|
||||
|
||||
+static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
|
||||
+{
|
||||
+ struct pcie_port *pp = &pcie->pp;
|
||||
+
|
||||
+ /*
|
||||
+ * program and enable address translation region 0 (device config
|
||||
+ * address space); region type config;
|
||||
+ * axi config address range to device config address range
|
||||
+ */
|
||||
+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
|
||||
+ PCIE20_PLR_IATU_REGION_INDEX(0),
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
|
||||
+
|
||||
+ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
|
||||
+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
|
||||
+ writel(pp->cfg0_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
|
||||
+ writel((pp->cfg0_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
|
||||
+ writel((pp->cfg0_base + pp->cfg0_size - 1),
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
|
||||
+ writel(busdev, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
|
||||
+ writel(0, pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
|
||||
+}
|
||||
+
|
||||
+static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
|
||||
+{
|
||||
+ struct pcie_port *pp = &pcie->pp;
|
||||
+
|
||||
+ /*
|
||||
+ * program and enable address translation region 2 (device resource
|
||||
+ * address space); region type memory;
|
||||
+ * axi device bar address range to device bar address range
|
||||
+ */
|
||||
+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
|
||||
+ PCIE20_PLR_IATU_REGION_INDEX(2),
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
|
||||
+
|
||||
+ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
|
||||
+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
|
||||
+ writel(pp->mem_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
|
||||
+ writel((pp->mem_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
|
||||
+ writel(pp->mem_base + pp->mem_size - 1,
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
|
||||
+ writel(pp->mem_bus_addr, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
|
||||
+ writel(upper_32_bits(pp->mem_bus_addr),
|
||||
+ pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
|
||||
+
|
||||
+ /* 256B PCIE buffer setting */
|
||||
+ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
|
||||
+ writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
|
||||
+}
|
||||
+
|
||||
static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
|
||||
{
|
||||
struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
|
||||
@@ -260,13 +377,19 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
ret = reset_control_assert(res->ahb_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot assert ahb reset\n");
|
||||
- goto err_assert_ahb;
|
||||
+ goto err_assert_reset;
|
||||
+ }
|
||||
+
|
||||
+ ret = reset_control_deassert(res->ext_reset);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "cannot deassert ext reset\n");
|
||||
+ goto err_assert_reset;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(res->iface_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable iface clock\n");
|
||||
- goto err_assert_ahb;
|
||||
+ goto err_assert_reset;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(res->phy_clk);
|
||||
@@ -281,22 +404,53 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
goto err_clk_core;
|
||||
}
|
||||
|
||||
+ ret = clk_prepare_enable(res->aux_clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "cannot prepare/enable aux clock\n");
|
||||
+ goto err_clk_aux;
|
||||
+ }
|
||||
+
|
||||
+ ret = clk_prepare_enable(res->ref_clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "cannot prepare/enable ref clock\n");
|
||||
+ goto err_clk_ref;
|
||||
+ }
|
||||
+
|
||||
ret = reset_control_deassert(res->ahb_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert ahb reset\n");
|
||||
goto err_deassert_ahb;
|
||||
}
|
||||
+ udelay(1);
|
||||
|
||||
/* enable PCIe clocks and resets */
|
||||
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
|
||||
val &= ~BIT(0);
|
||||
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
|
||||
|
||||
- /* enable external reference clock */
|
||||
+ /* Set Tx termination offset */
|
||||
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
|
||||
+ val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
|
||||
+ val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset);
|
||||
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
|
||||
+
|
||||
+ /* PARF programming */
|
||||
+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
|
||||
+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
|
||||
+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
|
||||
+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
|
||||
+ writel(PCS_SWING_TX_SWING_FULL(0x78) |
|
||||
+ PCS_SWING_TX_SWING_LOW(0x78),
|
||||
+ pcie->parf + PCIE20_PARF_PCS_SWING);
|
||||
+ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
|
||||
+
|
||||
+ /* Enable reference clock */
|
||||
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
|
||||
- val |= BIT(16);
|
||||
+ val &= ~REF_USE_PAD;
|
||||
+ val |= REF_SSP_EN;
|
||||
writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
|
||||
|
||||
+ /* De-assert PHY, PCIe, POR and AXI resets */
|
||||
ret = reset_control_deassert(res->phy_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert phy reset\n");
|
||||
@@ -327,12 +481,16 @@ static int qcom_pcie_init_v0(struct qcom
|
||||
return 0;
|
||||
|
||||
err_deassert_ahb:
|
||||
+ clk_disable_unprepare(res->ref_clk);
|
||||
+err_clk_ref:
|
||||
+ clk_disable_unprepare(res->aux_clk);
|
||||
+err_clk_aux:
|
||||
clk_disable_unprepare(res->core_clk);
|
||||
err_clk_core:
|
||||
clk_disable_unprepare(res->phy_clk);
|
||||
err_clk_phy:
|
||||
clk_disable_unprepare(res->iface_clk);
|
||||
-err_assert_ahb:
|
||||
+err_assert_reset:
|
||||
regulator_disable(res->vdda_phy);
|
||||
err_vdda_phy:
|
||||
regulator_disable(res->vdda_refclk);
|
||||
@@ -342,6 +500,12 @@ err_refclk:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static void qcom_pcie_configure_v0(struct qcom_pcie *pcie)
|
||||
+{
|
||||
+ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
|
||||
+ qcom_pcie_prog_viewport_mem2_outbound(pcie);
|
||||
+}
|
||||
+
|
||||
static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
|
||||
{
|
||||
struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
|
||||
@@ -455,6 +619,9 @@ static void qcom_pcie_host_init(struct p
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
+ if (pcie->ops->init)
|
||||
+ pcie->ops->init(pcie);
|
||||
+
|
||||
return;
|
||||
err:
|
||||
qcom_ep_reset_assert(pcie);
|
||||
@@ -486,6 +653,7 @@ static struct pcie_host_ops qcom_pcie_dw
|
||||
static const struct qcom_pcie_ops ops_v0 = {
|
||||
.get_resources = qcom_pcie_get_resources_v0,
|
||||
.init = qcom_pcie_init_v0,
|
||||
+ .configure = qcom_pcie_configure_v0,
|
||||
.deinit = qcom_pcie_deinit_v0,
|
||||
};
|
||||
|
||||
@ -16,6 +16,8 @@ Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
|
||||
|
||||
(limited to 'drivers/usb/dwc3/dwc3-of-simple.c')
|
||||
|
||||
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
|
||||
index f9e92ef..49bf556 100644
|
||||
--- a/drivers/usb/dwc3/dwc3-of-simple.c
|
||||
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
|
||||
@@ -26,6 +26,7 @@
|
||||
@ -34,10 +36,10 @@ Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
|
||||
+ struct reset_control *mstr_rst_30_1;
|
||||
};
|
||||
|
||||
static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count)
|
||||
@@ -100,6 +103,20 @@ static int dwc3_of_simple_probe(struct p
|
||||
if (ret)
|
||||
return ret;
|
||||
static int dwc3_of_simple_probe(struct platform_device *pdev)
|
||||
@@ -89,6 +92,20 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
|
||||
simple->clks[i] = clk;
|
||||
}
|
||||
|
||||
+ simple->mstr_rst_30_0 = devm_reset_control_get(dev, "usb30_0_mstr_rst");
|
||||
+
|
||||
@ -56,7 +58,7 @@ Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
|
||||
ret = of_platform_populate(np, NULL, NULL, dev);
|
||||
if (ret) {
|
||||
for (i = 0; i < simple->num_clocks; i++) {
|
||||
@@ -128,6 +145,12 @@ static int dwc3_of_simple_remove(struct
|
||||
@@ -117,6 +134,12 @@ static int dwc3_of_simple_remove(struct platform_device *pdev)
|
||||
clk_put(simple->clks[i]);
|
||||
}
|
||||
|
||||
@ -69,3 +71,5 @@ Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
|
||||
of_platform_depopulate(dev);
|
||||
|
||||
pm_runtime_put_sync(dev);
|
||||
--
|
||||
cgit v1.1
|
||||
|
||||
@ -1,516 +0,0 @@
|
||||
From 941e3869bdeddb2bebcc52ebfd57efe014887bc6 Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com>
|
||||
In-Reply-To: <d45ae31e888ad858d9f4396cabb4dc32a3f0365e.1500038134.git.chunkeey@googlemail.com>
|
||||
References: <d45ae31e888ad858d9f4396cabb4dc32a3f0365e.1500038134.git.chunkeey@googlemail.com>
|
||||
From: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Date: Wed, 10 May 2017 12:51:51 +0200
|
||||
Subject: [PATCH v3 2/3] pinctrl: qcom: ipq4019: add most remaining pin
|
||||
definitions
|
||||
To: linux-gpio@vger.kernel.org,
|
||||
devicetree@vger.kernel.org
|
||||
Cc: Linus Walleij <linus.walleij@linaro.org>,
|
||||
Rob Herring <robh+dt@kernel.org>,
|
||||
Mark Rutland <mark.rutland@arm.com>
|
||||
|
||||
This patch adds multiple pinctrl functions and mappings
|
||||
for SDIO, NAND, I2S, WIFI, PCIE, LEDs, etc... that have
|
||||
been missing from the current minimal version.
|
||||
|
||||
This patch has been updated from the original version
|
||||
that was posted by Ram Chandra Jangir on the LEDE-DEV ML:
|
||||
<https://patchwork.ozlabs.org/patch/752962/>. A short
|
||||
summary of the changes are documented in the device-tree
|
||||
patch of this series:
|
||||
"dt-bindings: pinctrl: add most other IPQ4019 pin functions and groups"
|
||||
|
||||
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
Cc: John Crispin <john@phrozen.org>
|
||||
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
---
|
||||
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 431 ++++++++++++++++++++++++++-------
|
||||
1 file changed, 346 insertions(+), 85 deletions(-)
|
||||
|
||||
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
index 743d1f458205..9e7f23d29cda 100644
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
@@ -277,12 +277,49 @@ DECLARE_QCA_GPIO_PINS(99);
|
||||
|
||||
enum ipq4019_functions {
|
||||
qca_mux_gpio,
|
||||
- qca_mux_blsp_uart1,
|
||||
+ qca_mux_aud_pin,
|
||||
+ qca_mux_audio_pwm,
|
||||
qca_mux_blsp_i2c0,
|
||||
qca_mux_blsp_i2c1,
|
||||
- qca_mux_blsp_uart0,
|
||||
- qca_mux_blsp_spi1,
|
||||
qca_mux_blsp_spi0,
|
||||
+ qca_mux_blsp_spi1,
|
||||
+ qca_mux_blsp_uart0,
|
||||
+ qca_mux_blsp_uart1,
|
||||
+ qca_mux_chip_rst,
|
||||
+ qca_mux_i2s_rx,
|
||||
+ qca_mux_i2s_spdif_in,
|
||||
+ qca_mux_i2s_spdif_out,
|
||||
+ qca_mux_i2s_td,
|
||||
+ qca_mux_i2s_tx,
|
||||
+ qca_mux_jtag,
|
||||
+ qca_mux_led0,
|
||||
+ qca_mux_led1,
|
||||
+ qca_mux_led2,
|
||||
+ qca_mux_led3,
|
||||
+ qca_mux_led4,
|
||||
+ qca_mux_led5,
|
||||
+ qca_mux_led6,
|
||||
+ qca_mux_led7,
|
||||
+ qca_mux_led8,
|
||||
+ qca_mux_led9,
|
||||
+ qca_mux_led10,
|
||||
+ qca_mux_led11,
|
||||
+ qca_mux_mdc,
|
||||
+ qca_mux_mdio,
|
||||
+ qca_mux_pcie,
|
||||
+ qca_mux_pmu,
|
||||
+ qca_mux_prng_rosc,
|
||||
+ qca_mux_qpic,
|
||||
+ qca_mux_rgmii,
|
||||
+ qca_mux_rmii,
|
||||
+ qca_mux_sdio,
|
||||
+ qca_mux_smart0,
|
||||
+ qca_mux_smart1,
|
||||
+ qca_mux_smart2,
|
||||
+ qca_mux_smart3,
|
||||
+ qca_mux_tm,
|
||||
+ qca_mux_wifi0,
|
||||
+ qca_mux_wifi1,
|
||||
qca_mux_NA,
|
||||
};
|
||||
|
||||
@@ -303,108 +340,331 @@ static const char * const gpio_groups[] = {
|
||||
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
|
||||
"gpio99",
|
||||
};
|
||||
-
|
||||
-static const char * const blsp_uart1_groups[] = {
|
||||
- "gpio8", "gpio9", "gpio10", "gpio11",
|
||||
+static const char * const aud_pin_groups[] = {
|
||||
+ "gpio48", "gpio49", "gpio50", "gpio51",
|
||||
+};
|
||||
+static const char * const audio_pwm_groups[] = {
|
||||
+ "gpio30", "gpio31", "gpio32", "gpio33", "gpio64", "gpio65", "gpio66",
|
||||
+ "gpio67",
|
||||
};
|
||||
static const char * const blsp_i2c0_groups[] = {
|
||||
"gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59",
|
||||
};
|
||||
-static const char * const blsp_spi0_groups[] = {
|
||||
- "gpio12", "gpio13", "gpio14", "gpio15", "gpio45",
|
||||
- "gpio54", "gpio55", "gpio56", "gpio57",
|
||||
-};
|
||||
static const char * const blsp_i2c1_groups[] = {
|
||||
"gpio12", "gpio13", "gpio34", "gpio35",
|
||||
};
|
||||
-static const char * const blsp_uart0_groups[] = {
|
||||
- "gpio16", "gpio17", "gpio60", "gpio61",
|
||||
+static const char * const blsp_spi0_groups[] = {
|
||||
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio45", "gpio54", "gpio55",
|
||||
+ "gpio56", "gpio57",
|
||||
};
|
||||
static const char * const blsp_spi1_groups[] = {
|
||||
"gpio44", "gpio45", "gpio46", "gpio47",
|
||||
};
|
||||
+static const char * const blsp_uart0_groups[] = {
|
||||
+ "gpio16", "gpio17", "gpio60", "gpio61",
|
||||
+};
|
||||
+static const char * const blsp_uart1_groups[] = {
|
||||
+ "gpio8", "gpio9", "gpio10", "gpio11",
|
||||
+};
|
||||
+static const char * const chip_rst_groups[] = {
|
||||
+ "gpio62",
|
||||
+};
|
||||
+static const char * const i2s_rx_groups[] = {
|
||||
+ "gpio0", "gpio1", "gpio2", "gpio20", "gpio21", "gpio22", "gpio23",
|
||||
+ "gpio58", "gpio60", "gpio61", "gpio63",
|
||||
+};
|
||||
+static const char * const i2s_spdif_in_groups[] = {
|
||||
+ "gpio34", "gpio59", "gpio63",
|
||||
+};
|
||||
+static const char * const i2s_spdif_out_groups[] = {
|
||||
+ "gpio35", "gpio62", "gpio63",
|
||||
+};
|
||||
+static const char * const i2s_td_groups[] = {
|
||||
+ "gpio27", "gpio28", "gpio29", "gpio54", "gpio55", "gpio56", "gpio63",
|
||||
+};
|
||||
+static const char * const i2s_tx_groups[] = {
|
||||
+ "gpio24", "gpio25", "gpio26", "gpio52", "gpio53", "gpio57", "gpio60",
|
||||
+ "gpio61",
|
||||
+};
|
||||
+static const char * const jtag_groups[] = {
|
||||
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
|
||||
+};
|
||||
+static const char * const led0_groups[] = {
|
||||
+ "gpio16", "gpio36", "gpio60",
|
||||
+};
|
||||
+static const char * const led1_groups[] = {
|
||||
+ "gpio17", "gpio37", "gpio61",
|
||||
+};
|
||||
+static const char * const led2_groups[] = {
|
||||
+ "gpio36", "gpio38", "gpio58",
|
||||
+};
|
||||
+static const char * const led3_groups[] = {
|
||||
+ "gpio39",
|
||||
+};
|
||||
+static const char * const led4_groups[] = {
|
||||
+ "gpio40",
|
||||
+};
|
||||
+static const char * const led5_groups[] = {
|
||||
+ "gpio44",
|
||||
+};
|
||||
+static const char * const led6_groups[] = {
|
||||
+ "gpio45",
|
||||
+};
|
||||
+static const char * const led7_groups[] = {
|
||||
+ "gpio46",
|
||||
+};
|
||||
+static const char * const led8_groups[] = {
|
||||
+ "gpio47",
|
||||
+};
|
||||
+static const char * const led9_groups[] = {
|
||||
+ "gpio48",
|
||||
+};
|
||||
+static const char * const led10_groups[] = {
|
||||
+ "gpio49",
|
||||
+};
|
||||
+static const char * const led11_groups[] = {
|
||||
+ "gpio50",
|
||||
+};
|
||||
+static const char * const mdc_groups[] = {
|
||||
+ "gpio7", "gpio52",
|
||||
+};
|
||||
+static const char * const mdio_groups[] = {
|
||||
+ "gpio6", "gpio53",
|
||||
+};
|
||||
+static const char * const pcie_groups[] = {
|
||||
+ "gpio39", "gpio52",
|
||||
+};
|
||||
+static const char * const pmu_groups[] = {
|
||||
+ "gpio54", "gpio55",
|
||||
+};
|
||||
+static const char * const prng_rosc_groups[] = {
|
||||
+ "gpio53",
|
||||
+};
|
||||
+static const char * const qpic_groups[] = {
|
||||
+ "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
|
||||
+ "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
|
||||
+ "gpio66", "gpio67", "gpio68", "gpio69",
|
||||
+};
|
||||
+static const char * const rgmii_groups[] = {
|
||||
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
|
||||
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
|
||||
+};
|
||||
+static const char * const rmii_groups[] = {
|
||||
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
|
||||
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
|
||||
+ "gpio50", "gpio51",
|
||||
+};
|
||||
+static const char * const sdio_groups[] = {
|
||||
+ "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
|
||||
+ "gpio30", "gpio31", "gpio32",
|
||||
+};
|
||||
+static const char * const smart0_groups[] = {
|
||||
+ "gpio0", "gpio1", "gpio2", "gpio5", "gpio44", "gpio45", "gpio46",
|
||||
+ "gpio47",
|
||||
+};
|
||||
+static const char * const smart1_groups[] = {
|
||||
+ "gpio8", "gpio9", "gpio16", "gpio17", "gpio58", "gpio59", "gpio60",
|
||||
+ "gpio61",
|
||||
+};
|
||||
+static const char * const smart2_groups[] = {
|
||||
+ "gpio40", "gpio41", "gpio48", "gpio49",
|
||||
+};
|
||||
+static const char * const smart3_groups[] = {
|
||||
+ "gpio58", "gpio59", "gpio60", "gpio61",
|
||||
+};
|
||||
+static const char * const tm_groups[] = {
|
||||
+ "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
|
||||
+ "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
|
||||
+};
|
||||
+static const char * const wifi0_groups[] = {
|
||||
+ "gpio37", "gpio40", "gpio41", "gpio42", "gpio50", "gpio51", "gpio52",
|
||||
+ "gpio53", "gpio56", "gpio57", "gpio58", "gpio98",
|
||||
+};
|
||||
+static const char * const wifi1_groups[] = {
|
||||
+ "gpio37", "gpio40", "gpio41", "gpio43", "gpio50", "gpio51", "gpio52",
|
||||
+ "gpio53", "gpio56", "gpio57", "gpio58", "gpio98",
|
||||
+};
|
||||
|
||||
static const struct msm_function ipq4019_functions[] = {
|
||||
- FUNCTION(gpio),
|
||||
- FUNCTION(blsp_uart1),
|
||||
+ FUNCTION(aud_pin),
|
||||
+ FUNCTION(audio_pwm),
|
||||
FUNCTION(blsp_i2c0),
|
||||
FUNCTION(blsp_i2c1),
|
||||
- FUNCTION(blsp_uart0),
|
||||
- FUNCTION(blsp_spi1),
|
||||
FUNCTION(blsp_spi0),
|
||||
+ FUNCTION(blsp_spi1),
|
||||
+ FUNCTION(blsp_uart0),
|
||||
+ FUNCTION(blsp_uart1),
|
||||
+ FUNCTION(chip_rst),
|
||||
+ FUNCTION(gpio),
|
||||
+ FUNCTION(i2s_rx),
|
||||
+ FUNCTION(i2s_spdif_in),
|
||||
+ FUNCTION(i2s_spdif_out),
|
||||
+ FUNCTION(i2s_td),
|
||||
+ FUNCTION(i2s_tx),
|
||||
+ FUNCTION(jtag),
|
||||
+ FUNCTION(led0),
|
||||
+ FUNCTION(led1),
|
||||
+ FUNCTION(led2),
|
||||
+ FUNCTION(led3),
|
||||
+ FUNCTION(led4),
|
||||
+ FUNCTION(led5),
|
||||
+ FUNCTION(led6),
|
||||
+ FUNCTION(led7),
|
||||
+ FUNCTION(led8),
|
||||
+ FUNCTION(led9),
|
||||
+ FUNCTION(led10),
|
||||
+ FUNCTION(led11),
|
||||
+ FUNCTION(mdc),
|
||||
+ FUNCTION(mdio),
|
||||
+ FUNCTION(pcie),
|
||||
+ FUNCTION(pmu),
|
||||
+ FUNCTION(prng_rosc),
|
||||
+ FUNCTION(qpic),
|
||||
+ FUNCTION(rgmii),
|
||||
+ FUNCTION(rmii),
|
||||
+ FUNCTION(sdio),
|
||||
+ FUNCTION(smart0),
|
||||
+ FUNCTION(smart1),
|
||||
+ FUNCTION(smart2),
|
||||
+ FUNCTION(smart3),
|
||||
+ FUNCTION(tm),
|
||||
+ FUNCTION(wifi0),
|
||||
+ FUNCTION(wifi1),
|
||||
};
|
||||
|
||||
static const struct msm_pingroup ipq4019_groups[] = {
|
||||
- PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(0, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(1, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(2, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(3, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(4, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(5, jtag, smart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
+ PINGROUP(6, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(7, mdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(8, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(9, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
+ PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
+ PINGROUP(16, blsp_uart0, led0, smart1, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(17, blsp_uart0, led1, smart1, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(20, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(21, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(22, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
+ PINGROUP(23, sdio, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(24, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(25, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(26, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(27, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(28, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(29, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(30, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(31, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(32, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(33, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(34, blsp_i2c1, i2s_spdif_in, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA, NA),
|
||||
+ PINGROUP(35, blsp_i2c1, i2s_spdif_out, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA, NA),
|
||||
+ PINGROUP(36, rmii, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
+ PINGROUP(37, rmii, wifi0, wifi1, led1, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(38, rmii, led2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
+ PINGROUP(39, rmii, pcie, led3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
+ PINGROUP(40, rmii, wifi0, wifi1, smart2, led4, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(41, rmii, wifi0, wifi1, smart2, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(42, rmii, wifi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
+ PINGROUP(43, rmii, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
+ PINGROUP(44, rmii, blsp_spi1, smart0, led5, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(45, rmii, blsp_spi1, blsp_spi0, smart0, led6, NA, NA, NA, NA,
|
||||
+ NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(46, rmii, blsp_spi1, smart0, led7, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(47, rmii, blsp_spi1, smart0, led8, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(48, rmii, aud_pin, smart2, led9, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(49, rmii, aud_pin, smart2, led10, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(50, rmii, aud_pin, wifi0, wifi1, led11, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA, NA),
|
||||
+ PINGROUP(51, rmii, aud_pin, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(52, qpic, mdc, pcie, i2s_tx, NA, NA, NA, tm, wifi0, wifi1, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(53, qpic, mdio, i2s_tx, prng_rosc, NA, tm, wifi0, wifi1, NA,
|
||||
+ NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(54, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(55, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA,
|
||||
+ NA, NA, NA),
|
||||
+ PINGROUP(56, qpic, blsp_spi0, i2s_td, NA, NA, tm, wifi0, wifi1, NA, NA,
|
||||
+ NA, NA, NA, NA),
|
||||
+ PINGROUP(57, qpic, blsp_spi0, i2s_tx, NA, NA, tm, wifi0, wifi1, NA, NA,
|
||||
+ NA, NA, NA, NA),
|
||||
+ PINGROUP(58, qpic, led2, blsp_i2c0, smart3, smart1, i2s_rx, NA, NA, tm,
|
||||
+ wifi0, wifi1, NA, NA, NA),
|
||||
+ PINGROUP(59, qpic, blsp_i2c0, smart3, smart1, i2s_spdif_in, NA, NA, NA,
|
||||
+ NA, NA, tm, NA, NA, NA),
|
||||
+ PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, i2s_tx, i2s_rx,
|
||||
+ NA, NA, NA, NA, NA, tm, NA),
|
||||
+ PINGROUP(61, qpic, blsp_uart0, smart1, smart3, led1, i2s_tx, i2s_rx,
|
||||
+ NA, NA, NA, NA, NA, tm, NA),
|
||||
+ PINGROUP(62, qpic, chip_rst, NA, NA, i2s_spdif_out, NA, NA, NA, NA, NA,
|
||||
+ tm, NA, NA, NA),
|
||||
+ PINGROUP(63, qpic, NA, NA, NA, i2s_td, i2s_rx, i2s_spdif_out,
|
||||
+ i2s_spdif_in, NA, NA, NA, NA, tm, NA),
|
||||
+ PINGROUP(64, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(65, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(66, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(67, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA, NA),
|
||||
+ PINGROUP(68, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(69, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
@@ -433,7 +693,8 @@ static const struct msm_pingroup ipq4019_groups[] = {
|
||||
PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
- PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
+ PINGROUP(98, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
|
||||
+ NA),
|
||||
PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
};
|
||||
|
||||
--
|
||||
2.13.2
|
||||
|
||||
@ -1,149 +0,0 @@
|
||||
From 895bbe5061fe2a6825503f57263a4eff9bb78a3c Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <895bbe5061fe2a6825503f57263a4eff9bb78a3c.1500038134.git.chunkeey@googlemail.com>
|
||||
In-Reply-To: <941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com>
|
||||
References: <d45ae31e888ad858d9f4396cabb4dc32a3f0365e.1500038134.git.chunkeey@googlemail.com>
|
||||
<941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com>
|
||||
From: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Date: Sun, 4 Jun 2017 21:38:21 +0200
|
||||
Subject: [PATCH v3 3/3] pinctrl: msm: add support to configure ipq40xx
|
||||
GPIO_PULL bits
|
||||
To: linux-gpio@vger.kernel.org,
|
||||
devicetree@vger.kernel.org
|
||||
Cc: Linus Walleij <linus.walleij@linaro.org>,
|
||||
Rob Herring <robh+dt@kernel.org>,
|
||||
Mark Rutland <mark.rutland@arm.com>
|
||||
|
||||
GPIO_PULL bits configurations in TLMM_GPIO_CFG register
|
||||
differs for IPQ40xx from rest of the other qcom SoCs.
|
||||
As it does not support the keeper state and therefore can't
|
||||
support bias-bus-hold property.
|
||||
|
||||
This patch adds a pull_no_keeper setting which configures the
|
||||
msm_gpio_pull bits for ipq40xx. This is required to fix the
|
||||
proper configurations of gpio-pull bits for nand pins mux.
|
||||
|
||||
IPQ40xx SoC:
|
||||
2'b10: Internal pull up enable.
|
||||
2'b11: Unsupport
|
||||
|
||||
For other SoC's:
|
||||
2'b10: Keeper
|
||||
2'b11: Pull-Up
|
||||
|
||||
Note: Due to pull_no_keeper length, all kerneldoc entries
|
||||
in the msm_pinctrl_soc_data struct had to be realigned.
|
||||
|
||||
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
---
|
||||
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-msm.c | 25 +++++++++++++++++++------
|
||||
drivers/pinctrl/qcom/pinctrl-msm.h | 16 +++++++++-------
|
||||
3 files changed, 29 insertions(+), 13 deletions(-)
|
||||
|
||||
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
index 9e7f23d29cda..1979b14b6fc3 100644
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
@@ -706,6 +706,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
|
||||
.groups = ipq4019_groups,
|
||||
.ngroups = ARRAY_SIZE(ipq4019_groups),
|
||||
.ngpios = 100,
|
||||
+ .pull_no_keeper = true,
|
||||
};
|
||||
|
||||
static int ipq4019_pinctrl_probe(struct platform_device *pdev)
|
||||
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
index 273badd92561..e5e27d79f5ef 100644
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
@@ -202,10 +202,11 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
|
||||
return 0;
|
||||
}
|
||||
|
||||
-#define MSM_NO_PULL 0
|
||||
-#define MSM_PULL_DOWN 1
|
||||
-#define MSM_KEEPER 2
|
||||
-#define MSM_PULL_UP 3
|
||||
+#define MSM_NO_PULL 0
|
||||
+#define MSM_PULL_DOWN 1
|
||||
+#define MSM_KEEPER 2
|
||||
+#define MSM_PULL_UP_NO_KEEPER 2
|
||||
+#define MSM_PULL_UP 3
|
||||
|
||||
static unsigned msm_regval_to_drive(u32 val)
|
||||
{
|
||||
@@ -243,10 +244,16 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
|
||||
arg = arg == MSM_PULL_DOWN;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_BUS_HOLD:
|
||||
+ if (pctrl->soc->pull_no_keeper)
|
||||
+ return -ENOTSUPP;
|
||||
+
|
||||
arg = arg == MSM_KEEPER;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
- arg = arg == MSM_PULL_UP;
|
||||
+ if (pctrl->soc->pull_no_keeper)
|
||||
+ arg = arg == MSM_PULL_UP_NO_KEEPER;
|
||||
+ else
|
||||
+ arg = arg == MSM_PULL_UP;
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
arg = msm_regval_to_drive(arg);
|
||||
@@ -309,10 +316,16 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
|
||||
arg = MSM_PULL_DOWN;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_BUS_HOLD:
|
||||
+ if (pctrl->soc->pull_no_keeper)
|
||||
+ return -ENOTSUPP;
|
||||
+
|
||||
arg = MSM_KEEPER;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
- arg = MSM_PULL_UP;
|
||||
+ if (pctrl->soc->pull_no_keeper)
|
||||
+ arg = MSM_PULL_UP_NO_KEEPER;
|
||||
+ else
|
||||
+ arg = MSM_PULL_UP;
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
/* Check for invalid values */
|
||||
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
|
||||
index 54fdd04ce9d5..9b9feea540ff 100644
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
|
||||
@@ -99,13 +99,14 @@ struct msm_pingroup {
|
||||
|
||||
/**
|
||||
* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
|
||||
- * @pins: An array describing all pins the pin controller affects.
|
||||
- * @npins: The number of entries in @pins.
|
||||
- * @functions: An array describing all mux functions the SoC supports.
|
||||
- * @nfunctions: The number of entries in @functions.
|
||||
- * @groups: An array describing all pin groups the pin SoC supports.
|
||||
- * @ngroups: The numbmer of entries in @groups.
|
||||
- * @ngpio: The number of pingroups the driver should expose as GPIOs.
|
||||
+ * @pins: An array describing all pins the pin controller affects.
|
||||
+ * @npins: The number of entries in @pins.
|
||||
+ * @functions: An array describing all mux functions the SoC supports.
|
||||
+ * @nfunctions: The number of entries in @functions.
|
||||
+ * @groups: An array describing all pin groups the pin SoC supports.
|
||||
+ * @ngroups: The numbmer of entries in @groups.
|
||||
+ * @ngpio: The number of pingroups the driver should expose as GPIOs.
|
||||
+ * @pull_no_keeper: The SoC does not support keeper bias.
|
||||
*/
|
||||
struct msm_pinctrl_soc_data {
|
||||
const struct pinctrl_pin_desc *pins;
|
||||
@@ -115,6 +116,7 @@ struct msm_pinctrl_soc_data {
|
||||
const struct msm_pingroup *groups;
|
||||
unsigned ngroups;
|
||||
unsigned ngpios;
|
||||
+ bool pull_no_keeper;
|
||||
};
|
||||
|
||||
int msm_pinctrl_probe(struct platform_device *pdev,
|
||||
--
|
||||
2.13.2
|
||||
|
||||
@ -1,28 +0,0 @@
|
||||
From 830a63791185f4daaecb8d1102c4ee3c9210c03c Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Date: Mon, 1 May 2017 13:42:41 +0200
|
||||
Subject: [PATCH 1/2] qcom: ipq4019: fix i2c_0 node
|
||||
|
||||
This patch fixes two typos in the i2c_0 node for the ipq4019.
|
||||
The register size is just 0x600. The core clock is
|
||||
GCC_BLSP1_QUP1_I2C_APPS_CLK. GCC_BLSP1_QUP2_I2C_APPS_CLK is
|
||||
used by the second i2c.
|
||||
|
||||
Fixes: e76b4284b520ba3 ("qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree")
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -184,7 +184,7 @@
|
||||
|
||||
i2c_0: i2c@78b7000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
- reg = <0x78b7000 0x6000>;
|
||||
+ reg = <0x78b7000 0x600>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
|
||||
@ -1,46 +0,0 @@
|
||||
From 5110346bcc17b037edd5b0193f31ad046e6242db Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Date: Mon, 1 May 2017 13:53:07 +0200
|
||||
Subject: [PATCH 2/2] qcom: ipq4019: add second i2c
|
||||
|
||||
This patch adds the second i2c block to the IPQ4019 platform.
|
||||
The second i2c has been successfully tested on the
|
||||
Cisco Meraki MR33.
|
||||
|
||||
Cc: Chris Blake <chrisrblake93@gmail.com>
|
||||
Cc: Matthew McClintock <msm-oss@mcclintock.net>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -26,6 +26,7 @@
|
||||
aliases {
|
||||
spi0 = &spi_0;
|
||||
i2c0 = &i2c_0;
|
||||
+ i2c1 = &i2c_1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -196,6 +197,19 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ i2c_1: i2c@78b8000 {
|
||||
+ compatible = "qcom,i2c-qup-v2.2.1";
|
||||
+ reg = <0x78b8000 0x600>;
|
||||
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
||||
+ clock-names = "iface", "core";
|
||||
+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
|
||||
+ dma-names = "rx", "tx";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
|
||||
cryptobam: dma@8e04000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
@ -17,7 +17,7 @@ Changes:
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -35,19 +35,27 @@
|
||||
@@ -34,19 +34,27 @@
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
@ -47,7 +47,7 @@ Changes:
|
||||
qcom,acc = <&acc1>;
|
||||
qcom,saw = <&saw1>;
|
||||
reg = <0x1>;
|
||||
@@ -59,7 +67,8 @@
|
||||
@@ -58,7 +66,8 @@
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
@ -57,7 +57,7 @@ Changes:
|
||||
qcom,acc = <&acc2>;
|
||||
qcom,saw = <&saw2>;
|
||||
reg = <0x2>;
|
||||
@@ -71,7 +80,8 @@
|
||||
@@ -70,7 +79,8 @@
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
@ -67,7 +67,7 @@ Changes:
|
||||
qcom,acc = <&acc3>;
|
||||
qcom,saw = <&saw3>;
|
||||
reg = <0x3>;
|
||||
@@ -236,22 +246,22 @@
|
||||
@@ -212,22 +222,22 @@
|
||||
};
|
||||
|
||||
acc0: clock-controller@b088000 {
|
||||
@ -94,7 +94,7 @@ Changes:
|
||||
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
|
||||
};
|
||||
|
||||
@@ -279,6 +289,12 @@
|
||||
@@ -255,6 +265,12 @@
|
||||
regulator;
|
||||
};
|
||||
|
||||
|
||||
@ -51,7 +51,7 @@ Changes:
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -331,5 +331,76 @@
|
||||
@@ -307,5 +307,76 @@
|
||||
compatible = "qcom,pshold";
|
||||
reg = <0x4ab000 0x4>;
|
||||
};
|
||||
|
||||
@ -1,100 +1,57 @@
|
||||
From 45e183ad169db4e233ce8337cf8b735545151f0e Mon Sep 17 00:00:00 2001
|
||||
From 6091a49b0b06bf838fed80498c4f5f40d0fbd447 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sat, 19 Nov 2016 01:22:46 +0100
|
||||
Subject: [PATCH] arm: dts: qcom: add both IPQ4019 wifi blocks
|
||||
Subject: [PATCH] dts: ipq4019: add both IPQ4019 wifi block definitions
|
||||
|
||||
This patch adds and enables the device-tree definitions for
|
||||
both qcom,ipq4019-wifi blocks for the IPQ4019.
|
||||
The IPQ4019 has two ath10k blocks on the AHB. Both wifi's
|
||||
are already supported by ath10k.
|
||||
|
||||
Support for these have been added into the ath10k driver since:
|
||||
280e762e9c72 ("ath10k: enable ipq4019 device probe in ahb module")
|
||||
|
||||
The binding documentation was added in commit:
|
||||
a47aaa69de88 ("dt: bindings: add new dt entry for pre calibration in qcom, ath10k.txt")
|
||||
|
||||
This has been tested on an ASUS RT-AC58U (IPQ4019),
|
||||
an AVM Fritz!Box 4040 (IPQ4018), a Compex WPJ428(IPQ4028)
|
||||
and a Meraki MR33 (IPQ4029).
|
||||
|
||||
| a000000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff [...]
|
||||
| a000000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1
|
||||
| a000000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p,mfp,[...]
|
||||
| a000000.wifi: board_file api 2 bmi_id 0:16 crc32 5773b188
|
||||
| a000000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...]
|
||||
...
|
||||
| a800000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff sub 0000:0000
|
||||
| a800000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1
|
||||
| a800000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p, [...]
|
||||
| a800000.wifi: board_file api 2 bmi_id 0:17 crc32 5773b188
|
||||
| a800000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...]
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 +++
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++++++++++
|
||||
2 files changed, 92 insertions(+)
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 84 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
index c25d8f5c669d..cfa0c9970d5b 100644
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -112,5 +112,13 @@
|
||||
watchdog@b017000 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ wifi@a000000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ wifi@a800000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
index d1a56331ce96..1ddcc96b510c 100644
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -291,5 +291,89 @@
|
||||
compatible = "qcom,pshold";
|
||||
reg = <0x4ab000 0x4>;
|
||||
@@ -378,5 +378,89 @@
|
||||
dr_mode = "host";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ wifi0: wifi@a000000 {
|
||||
+ compatible = "qcom,ipq4019-wifi";
|
||||
+ reg = <0xa000000 0x200000>;
|
||||
+ resets = <&gcc WIFI0_CPU_INIT_RESET>,
|
||||
+ <&gcc WIFI0_RADIO_SRIF_RESET>,
|
||||
+ <&gcc WIFI0_RADIO_WARM_RESET>,
|
||||
+ <&gcc WIFI0_RADIO_COLD_RESET>,
|
||||
+ <&gcc WIFI0_CORE_WARM_RESET>,
|
||||
+ <&gcc WIFI0_CORE_COLD_RESET>;
|
||||
+ resets = <&gcc WIFI0_CPU_INIT_RESET
|
||||
+ &gcc WIFI0_RADIO_SRIF_RESET
|
||||
+ &gcc WIFI0_RADIO_WARM_RESET
|
||||
+ &gcc WIFI0_RADIO_COLD_RESET
|
||||
+ &gcc WIFI0_CORE_WARM_RESET
|
||||
+ &gcc WIFI0_CORE_COLD_RESET>;
|
||||
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
|
||||
+ "wifi_radio_warm", "wifi_radio_cold",
|
||||
+ "wifi_core_warm", "wifi_core_cold";
|
||||
+ clocks = <&gcc GCC_WCSS2G_CLK>,
|
||||
+ <&gcc GCC_WCSS2G_REF_CLK>,
|
||||
+ <&gcc GCC_WCSS2G_RTC_CLK>;
|
||||
+ clocks = <&gcc GCC_WCSS2G_CLK
|
||||
+ &gcc GCC_WCSS2G_REF_CLK
|
||||
+ &gcc GCC_WCSS2G_RTC_CLK>;
|
||||
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
|
||||
+ "wifi_wcss_rtc";
|
||||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 168 IRQ_TYPE_NONE>;
|
||||
+ interrupts = <0 32 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 33 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 34 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 35 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 36 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 37 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 38 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 39 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 40 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 41 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 42 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 43 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 44 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 45 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 46 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 47 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 168 IRQ_TYPE_NONE>;
|
||||
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
+ "msi4", "msi5", "msi6", "msi7",
|
||||
+ "msi8", "msi9", "msi10", "msi11",
|
||||
@ -106,37 +63,37 @@ index d1a56331ce96..1ddcc96b510c 100644
|
||||
+ wifi1: wifi@a800000 {
|
||||
+ compatible = "qcom,ipq4019-wifi";
|
||||
+ reg = <0xa800000 0x200000>;
|
||||
+ resets = <&gcc WIFI1_CPU_INIT_RESET>,
|
||||
+ <&gcc WIFI1_RADIO_SRIF_RESET>,
|
||||
+ <&gcc WIFI1_RADIO_WARM_RESET>,
|
||||
+ <&gcc WIFI1_RADIO_COLD_RESET>,
|
||||
+ <&gcc WIFI1_CORE_WARM_RESET>,
|
||||
+ <&gcc WIFI1_CORE_COLD_RESET>;
|
||||
+ resets = <&gcc WIFI1_CPU_INIT_RESET
|
||||
+ &gcc WIFI1_RADIO_SRIF_RESET
|
||||
+ &gcc WIFI1_RADIO_WARM_RESET
|
||||
+ &gcc WIFI1_RADIO_COLD_RESET
|
||||
+ &gcc WIFI1_CORE_WARM_RESET
|
||||
+ &gcc WIFI1_CORE_COLD_RESET>;
|
||||
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
|
||||
+ "wifi_radio_warm", "wifi_radio_cold",
|
||||
+ "wifi_core_warm", "wifi_core_cold";
|
||||
+ clocks = <&gcc GCC_WCSS5G_CLK>,
|
||||
+ <&gcc GCC_WCSS5G_REF_CLK>,
|
||||
+ <&gcc GCC_WCSS5G_RTC_CLK>;
|
||||
+ clocks = <&gcc GCC_WCSS5G_CLK
|
||||
+ &gcc GCC_WCSS5G_REF_CLK
|
||||
+ &gcc GCC_WCSS5G_RTC_CLK>;
|
||||
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
|
||||
+ "wifi_wcss_rtc";
|
||||
+ interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
|
||||
+ <GIC_SPI 169 IRQ_TYPE_NONE>;
|
||||
+ interrupts = <0 48 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 49 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 50 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 51 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 52 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 53 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 54 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 55 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 56 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 57 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 58 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 59 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 60 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 61 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 62 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 63 IRQ_TYPE_EDGE_RISING
|
||||
+ 0 169 IRQ_TYPE_NONE>;
|
||||
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
+ "msi4", "msi5", "msi6", "msi7",
|
||||
+ "msi8", "msi9", "msi10", "msi11",
|
||||
@ -146,6 +103,3 @@ index d1a56331ce96..1ddcc96b510c 100644
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--
|
||||
2.13.3
|
||||
|
||||
|
||||
@ -13,7 +13,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -295,6 +295,13 @@
|
||||
@@ -271,6 +271,13 @@
|
||||
regulator;
|
||||
};
|
||||
|
||||
|
||||
@ -1,25 +0,0 @@
|
||||
From: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Date: Mon, 20 Mar 2017 18:08:03 +0100
|
||||
Subject: [PATCH] dts: ARM: qcom-ipq4019: add scm node
|
||||
|
||||
This patch adds the device-tree node necessary for communicating
|
||||
with Qualcomm's TrustZone/Secure Execution Environment
|
||||
implementation.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
---
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -137,6 +137,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ firmware {
|
||||
+ scm {
|
||||
+ compatible = "qcom,scm-ipq4019", "qcom,scm-ipq40xx";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -1,98 +0,0 @@
|
||||
--- a/drivers/firmware/qcom_scm-32.c
|
||||
+++ b/drivers/firmware/qcom_scm-32.c
|
||||
@@ -578,3 +578,33 @@ int __qcom_scm_pinmux_write(u32 svc_id,
|
||||
|
||||
return ret;
|
||||
}
|
||||
+
|
||||
+int __qcom_scm_fuse(struct device *dev, u32 address, u32 *val)
|
||||
+{
|
||||
+ __le32 *otp_value;
|
||||
+ dma_addr_t in;
|
||||
+ int ret;
|
||||
+
|
||||
+ otp_value = kzalloc(PAGE_ALIGN(sizeof(*otp_value)), GFP_KERNEL);
|
||||
+ if (!otp_value)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ in = dma_map_single(dev, otp_value, sizeof(in), DMA_FROM_DEVICE);
|
||||
+
|
||||
+ ret = dma_mapping_error(dev, in);
|
||||
+ if (ret != 0) {
|
||||
+ kfree(otp_value);
|
||||
+ pr_err("DMA Mapping Error %d\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = qcom_scm_call(dev, QCOM_SCM_SVC_FUSE, address,
|
||||
+ &in, sizeof(in), NULL, 0);
|
||||
+
|
||||
+ dma_unmap_single(dev, in, sizeof(in), DMA_FROM_DEVICE);
|
||||
+
|
||||
+ *val = le32_to_cpu(*otp_value);
|
||||
+ kfree(otp_value);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
--- a/drivers/firmware/qcom_scm.c
|
||||
+++ b/drivers/firmware/qcom_scm.c
|
||||
@@ -165,6 +165,25 @@ int qcom_scm_hdcp_req(struct qcom_scm_hd
|
||||
EXPORT_SYMBOL(qcom_scm_hdcp_req);
|
||||
|
||||
/**
|
||||
+ * qcom_scm_fuse() - Reads a value from the OTP
|
||||
+ * @address: address
|
||||
+ *
|
||||
+ * Returns the value of the OTP at the specified address.
|
||||
+ */
|
||||
+int qcom_scm_fuse(u32 address, u32 *val)
|
||||
+{
|
||||
+ int ret = qcom_scm_clk_enable();
|
||||
+
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = __qcom_scm_fuse(__scm->dev, address, val);
|
||||
+ qcom_scm_clk_disable();
|
||||
+ return ret;
|
||||
+}
|
||||
+EXPORT_SYMBOL(qcom_scm_fuse);
|
||||
+
|
||||
+/**
|
||||
* qcom_scm_pas_supported() - Check if the peripheral authentication service is
|
||||
* available for the given peripherial
|
||||
* @peripheral: peripheral id
|
||||
--- a/drivers/firmware/qcom_scm.h
|
||||
+++ b/drivers/firmware/qcom_scm.h
|
||||
@@ -63,6 +63,9 @@ extern int __qcom_scm_pas_mss_reset(str
|
||||
s32 __qcom_scm_pinmux_read(u32 svc_id, u32 cmd_id, u32 arg1);
|
||||
s32 __qcom_scm_pinmux_write(u32 svc_id, u32 cmd_id, u32 arg1, u32 arg2);
|
||||
|
||||
+#define QCOM_SCM_SVC_FUSE 0x8
|
||||
+extern int __qcom_scm_fuse(struct device *dev, u32 address, u32 *val);
|
||||
+
|
||||
/* common error codes */
|
||||
#define QCOM_SCM_V2_EBUSY -12
|
||||
#define QCOM_SCM_ENOMEM -5
|
||||
--- a/include/linux/qcom_scm.h
|
||||
+++ b/include/linux/qcom_scm.h
|
||||
@@ -48,4 +48,7 @@ extern u32 qcom_scm_get_version(void);
|
||||
|
||||
extern s32 qcom_scm_pinmux_read(u32 arg1);
|
||||
extern s32 qcom_scm_pinmux_write(u32 arg1, u32 arg2);
|
||||
+
|
||||
+extern int qcom_scm_fuse(u32 address, u32 *val);
|
||||
+
|
||||
#endif
|
||||
--- a/drivers/firmware/qcom_scm-64.c
|
||||
+++ b/drivers/firmware/qcom_scm-64.c
|
||||
@@ -374,3 +374,9 @@ int __qcom_scm_pinmux_write(u32 svc_id,
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
+
|
||||
+int __qcom_scm_fuse(struct device *dev, u32 address, u32 *val)
|
||||
+{
|
||||
+ *val = -1;
|
||||
+ return -ENOTSUPP;
|
||||
+}
|
||||
@ -15,7 +15,7 @@ so the info might change.
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -345,6 +345,34 @@
|
||||
@@ -315,6 +315,34 @@
|
||||
reg = <0x4ab000 0x4>;
|
||||
};
|
||||
|
||||
|
||||
@ -14,7 +14,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -373,6 +373,29 @@
|
||||
@@ -343,6 +343,29 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -16,16 +16,16 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -27,6 +27,8 @@
|
||||
@@ -26,6 +26,8 @@
|
||||
aliases {
|
||||
spi0 = &spi_0;
|
||||
i2c0 = &i2c_0;
|
||||
i2c1 = &i2c_1;
|
||||
+ ethernet0 = &gmac0;
|
||||
+ ethernet1 = &gmac1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -396,6 +398,64 @@
|
||||
@@ -366,6 +368,64 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -291,7 +291,7 @@ Changed:
|
||||
+MODULE_DESCRIPTION("USB3 QCA BALDUR HSPHY driver");
|
||||
--- /dev/null
|
||||
+++ b/drivers/usb/phy/phy-qca-uniphy.c
|
||||
@@ -0,0 +1,202 @@
|
||||
@@ -0,0 +1,135 @@
|
||||
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
|
||||
+ *
|
||||
+ * Permission to use, copy, modify, and/or distribute this software for any
|
||||
@ -318,18 +318,6 @@ Changed:
|
||||
+#include <linux/usb/phy.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/qcom_scm.h>
|
||||
+
|
||||
+#define USB_CALIBRATION_CMD 0x10
|
||||
+#define USB3PHY_SPARE_1 0x7FC
|
||||
+#define RX_LOS_1 0x7C8
|
||||
+#define MISC_SOURCE_REG 0x21c
|
||||
+#define CDR_CONTROL_REG_1 0x80
|
||||
+#define PCS_INTERNAL_CONTROL14 0x364
|
||||
+#define MMD1_REG_REG_MASK (0x7F << 8)
|
||||
+#define OTP_MASK (0x7F << 5)
|
||||
+#define MMD1_REG_AUTOLOAD_MASK (0x1 << 7)
|
||||
+#define SPARE_1_BIT14_MASK (0x1 << 14)
|
||||
+
|
||||
+struct qca_uni_ss_phy {
|
||||
+ struct usb_phy phy;
|
||||
@ -350,60 +338,6 @@ Changed:
|
||||
+ reset_control_assert(phy->por_rst);
|
||||
+}
|
||||
+
|
||||
+int qca_uni_ss_phy_usb_los_calibration(void __iomem *base)
|
||||
+{
|
||||
+ int err;
|
||||
+ uint32_t data, otp_val = 0;
|
||||
+
|
||||
+ /* Get OTP value */
|
||||
+ err = qcom_scm_fuse(USB_CALIBRATION_CMD, &otp_val);
|
||||
+ if (err < 0 || !(otp_val & OTP_MASK)) {
|
||||
+ pr_err("USB Calibration Failed with error %d %d\n", err, otp_val);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ pr_info("Raw USB3 Calibration value %x\n", otp_val);
|
||||
+
|
||||
+ /*
|
||||
+ * Read the USB3PHY_SPARE_1 register and
|
||||
+ * set bit 14 to 0
|
||||
+ */
|
||||
+ data = readl_relaxed(base + USB3PHY_SPARE_1);
|
||||
+ data = data & (~SPARE_1_BIT14_MASK);
|
||||
+ writel(data, base + USB3PHY_SPARE_1);
|
||||
+ udelay(100);
|
||||
+
|
||||
+ /*
|
||||
+ * Get bit 11:5 value, add with 0x14 and set to the
|
||||
+ * register USB3PHY_RX_LOS_1 bit MMD1_REG_REG
|
||||
+ */
|
||||
+ data = readl_relaxed(base + RX_LOS_1);
|
||||
+ otp_val = ((otp_val & OTP_MASK) >> 5) + 0x14;
|
||||
+ otp_val = otp_val << 8;
|
||||
+ data = data & (~MMD1_REG_REG_MASK);
|
||||
+ data = data | otp_val;
|
||||
+ writel(data, base + RX_LOS_1);
|
||||
+ udelay(100);
|
||||
+
|
||||
+ /*
|
||||
+ * Set bit MMD1_REG_AUTOLOAD_SEL_RX_LOS_THRES in
|
||||
+ * USB3PHY_RX_LOS_1 to 1
|
||||
+ */
|
||||
+ data = readl_relaxed(base + RX_LOS_1);
|
||||
+ data = data | MMD1_REG_AUTOLOAD_MASK;
|
||||
+ writel(data, base + RX_LOS_1);
|
||||
+ udelay(100);
|
||||
+
|
||||
+ writel(0x4000, base + PCS_INTERNAL_CONTROL14);
|
||||
+ udelay(100);
|
||||
+ writel(0xaa0a, base + MISC_SOURCE_REG);
|
||||
+ udelay(100);
|
||||
+ writel(0x0202, base + CDR_CONTROL_REG_1);
|
||||
+ udelay(100);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qca_uni_ss_phy_init(struct usb_phy *x)
|
||||
+{
|
||||
+ struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
|
||||
@ -416,8 +350,7 @@ Changed:
|
||||
+ /* deassert SS PHY POR reset */
|
||||
+ reset_control_deassert(phy->por_rst);
|
||||
+
|
||||
+ /* USB LOS Calibration */
|
||||
+ return qca_uni_ss_phy_usb_los_calibration(phy->base);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qca_uni_ss_get_resources(struct platform_device *pdev,
|
||||
|
||||
@ -15,7 +15,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
|
||||
--- a/drivers/usb/dwc3/dwc3-of-simple.c
|
||||
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
|
||||
@@ -197,6 +197,7 @@ static const struct dev_pm_ops dwc3_of_s
|
||||
@@ -174,6 +174,7 @@ static const struct dev_pm_ops dwc3_of_s
|
||||
|
||||
static const struct of_device_id of_dwc3_simple_match[] = {
|
||||
{ .compatible = "qcom,dwc3" },
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,236 @@
|
||||
From e77af7de404eb464f7da9e0daeb8b362cc66a7ba Mon Sep 17 00:00:00 2001
|
||||
From: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Date: Tue, 9 May 2017 11:45:00 +0530
|
||||
Subject: [PATCH] msm: pinctrl: Add support to configure ipq40xx GPIO_PULL bits
|
||||
|
||||
GPIO_PULL bits configurations in TLMM_GPIO_CFG register
|
||||
differs for IPQ40xx from rest of the other qcom SoC's.
|
||||
This change add support to configure the msm_gpio_pull
|
||||
bits for ipq40xx, It is required to fix the proper
|
||||
configurations of gpio-pull bits for nand pins mux.
|
||||
|
||||
IPQ40xx SoC:
|
||||
2'b10: Internal pull up enable.
|
||||
2'b11: Unsupport
|
||||
|
||||
For other SoC's:
|
||||
2'b10: Keeper
|
||||
2'b11: Pull-Up
|
||||
|
||||
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
---
|
||||
drivers/pinctrl/qcom/pinctrl-apq8064.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-apq8084.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 8 ++++++++
|
||||
drivers/pinctrl/qcom/pinctrl-ipq8064.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-mdm9615.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-msm.c | 21 ++++++++-------------
|
||||
drivers/pinctrl/qcom/pinctrl-msm.h | 19 +++++++++++++++++++
|
||||
drivers/pinctrl/qcom/pinctrl-msm8660.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-msm8916.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-msm8960.c | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-msm8x74.c | 1 +
|
||||
11 files changed, 43 insertions(+), 13 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
|
||||
@@ -597,6 +597,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = apq8064_groups,
|
||||
.ngroups = ARRAY_SIZE(apq8064_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int apq8064_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
|
||||
@@ -1206,6 +1206,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = apq8084_groups,
|
||||
.ngroups = ARRAY_SIZE(apq8084_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int apq8084_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
|
||||
@@ -1531,6 +1531,13 @@ static const struct msm_pingroup ipq4019
|
||||
PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
||||
};
|
||||
|
||||
+static const struct msm_pinctrl_gpio_pull ipq4019_gpio_pull = {
|
||||
+ .no_pull = 0,
|
||||
+ .pull_down = 1,
|
||||
+ .keeper = 0,
|
||||
+ .pull_up = 2,
|
||||
+};
|
||||
+
|
||||
static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
|
||||
.pins = ipq4019_pins,
|
||||
.npins = ARRAY_SIZE(ipq4019_pins),
|
||||
@@ -1539,6 +1546,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = ipq4019_groups,
|
||||
.ngroups = ARRAY_SIZE(ipq4019_groups),
|
||||
.ngpios = 100,
|
||||
+ .gpio_pull = &ipq4019_gpio_pull,
|
||||
};
|
||||
|
||||
static int ipq4019_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
|
||||
@@ -630,6 +630,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = ipq8064_groups,
|
||||
.ngroups = ARRAY_SIZE(ipq8064_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int ipq8064_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
|
||||
@@ -444,6 +444,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = mdm9615_groups,
|
||||
.ngroups = ARRAY_SIZE(mdm9615_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int mdm9615_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
@@ -203,11 +203,6 @@ static int msm_config_reg(struct msm_pin
|
||||
return 0;
|
||||
}
|
||||
|
||||
-#define MSM_NO_PULL 0
|
||||
-#define MSM_PULL_DOWN 1
|
||||
-#define MSM_KEEPER 2
|
||||
-#define MSM_PULL_UP 3
|
||||
-
|
||||
static unsigned msm_regval_to_drive(u32 val)
|
||||
{
|
||||
return (val + 1) * 2;
|
||||
@@ -238,16 +233,16 @@ static int msm_config_group_get(struct p
|
||||
/* Convert register value to pinconf value */
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
- arg = arg == MSM_NO_PULL;
|
||||
+ arg = arg == pctrl->soc->gpio_pull->no_pull;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
- arg = arg == MSM_PULL_DOWN;
|
||||
+ arg = arg == pctrl->soc->gpio_pull->pull_down;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_BUS_HOLD:
|
||||
- arg = arg == MSM_KEEPER;
|
||||
+ arg = arg == pctrl->soc->gpio_pull->keeper;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
- arg = arg == MSM_PULL_UP;
|
||||
+ arg = arg == pctrl->soc->gpio_pull->pull_up;
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
arg = msm_regval_to_drive(arg);
|
||||
@@ -304,16 +299,16 @@ static int msm_config_group_set(struct p
|
||||
/* Convert pinconf values to register values */
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
- arg = MSM_NO_PULL;
|
||||
+ arg = pctrl->soc->gpio_pull->no_pull;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
- arg = MSM_PULL_DOWN;
|
||||
+ arg = pctrl->soc->gpio_pull->pull_down;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_BUS_HOLD:
|
||||
- arg = MSM_KEEPER;
|
||||
+ arg = pctrl->soc->gpio_pull->keeper;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
- arg = MSM_PULL_UP;
|
||||
+ arg = pctrl->soc->gpio_pull->pull_up;
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
/* Check for invalid values */
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
|
||||
@@ -98,6 +98,16 @@ struct msm_pingroup {
|
||||
};
|
||||
|
||||
/**
|
||||
+ * struct msm_pinctrl_gpio_pull - pinctrl pull value bit field descriptor
|
||||
+ */
|
||||
+struct msm_pinctrl_gpio_pull {
|
||||
+ unsigned no_pull;
|
||||
+ unsigned pull_down;
|
||||
+ unsigned keeper;
|
||||
+ unsigned pull_up;
|
||||
+};
|
||||
+
|
||||
+/**
|
||||
* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
|
||||
* @pins: An array describing all pins the pin controller affects.
|
||||
* @npins: The number of entries in @pins.
|
||||
@@ -106,6 +116,7 @@ struct msm_pingroup {
|
||||
* @groups: An array describing all pin groups the pin SoC supports.
|
||||
* @ngroups: The numbmer of entries in @groups.
|
||||
* @ngpio: The number of pingroups the driver should expose as GPIOs.
|
||||
+ * @gpio_pull_val: The pull value bit field descriptor.
|
||||
*/
|
||||
struct msm_pinctrl_soc_data {
|
||||
const struct pinctrl_pin_desc *pins;
|
||||
@@ -115,6 +126,14 @@ struct msm_pinctrl_soc_data {
|
||||
const struct msm_pingroup *groups;
|
||||
unsigned ngroups;
|
||||
unsigned ngpios;
|
||||
+ const struct msm_pinctrl_gpio_pull *gpio_pull;
|
||||
+};
|
||||
+
|
||||
+static const struct msm_pinctrl_gpio_pull msm_gpio_pull = {
|
||||
+ .no_pull = 0,
|
||||
+ .pull_down = 1,
|
||||
+ .keeper = 2,
|
||||
+ .pull_up = 3,
|
||||
};
|
||||
|
||||
int msm_pinctrl_probe(struct platform_device *pdev,
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm8660.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c
|
||||
@@ -979,6 +979,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = msm8660_groups,
|
||||
.ngroups = ARRAY_SIZE(msm8660_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int msm8660_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm8916.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c
|
||||
@@ -967,6 +967,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = msm8916_groups,
|
||||
.ngroups = ARRAY_SIZE(msm8916_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int msm8916_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
|
||||
@@ -1244,6 +1244,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = msm8960_groups,
|
||||
.ngroups = ARRAY_SIZE(msm8960_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int msm8960_pinctrl_probe(struct platform_device *pdev)
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
|
||||
@@ -1069,6 +1069,7 @@ static const struct msm_pinctrl_soc_data
|
||||
.groups = msm8x74_groups,
|
||||
.ngroups = ARRAY_SIZE(msm8x74_groups),
|
||||
.ngpios = NUM_GPIO_PINGROUPS,
|
||||
+ .gpio_pull = &msm_gpio_pull,
|
||||
};
|
||||
|
||||
static int msm8x74_pinctrl_probe(struct platform_device *pdev)
|
||||
@ -15,17 +15,78 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
@@ -88,6 +88,26 @@
|
||||
@@ -88,6 +88,86 @@
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ nand_pins: nand_pins {
|
||||
+
|
||||
+ mux_1 {
|
||||
+ pins = "gpio52", "gpio53", "gpio54",
|
||||
+ "gpio55", "gpio56", "gpio61",
|
||||
+ "gpio62", "gpio63", "gpio69";
|
||||
+ function = "qpic_pad";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_2 {
|
||||
+ pins = "gpio67";
|
||||
+ function = "qpic_pad0";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_3 {
|
||||
+ pins = "gpio64";
|
||||
+ function = "qpic_pad1";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_4 {
|
||||
+ pins = "gpio65";
|
||||
+ function = "qpic_pad2";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_5 {
|
||||
+ pins = "gpio66";
|
||||
+ function = "qpic_pad3";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_6 {
|
||||
+ pins = "gpio57";
|
||||
+ function = "qpic_pad4";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_7 {
|
||||
+ pins = "gpio58";
|
||||
+ function = "qpic_pad5";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_8 {
|
||||
+ pins = "gpio59";
|
||||
+ function = "qpic_pad6";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_9 {
|
||||
+ pins = "gpio60";
|
||||
+ function = "qpic_pad7";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ mux_10 {
|
||||
+ pins = "gpio68";
|
||||
+ function = "qpic_pad8";
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ pullups {
|
||||
+ pins = "gpio52", "gpio53", "gpio58",
|
||||
+ "gpio59";
|
||||
+ function = "qpic";
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
@ -35,14 +96,13 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
+ "gpio62", "gpio63", "gpio64",
|
||||
+ "gpio65", "gpio66", "gpio67",
|
||||
+ "gpio68", "gpio69";
|
||||
+ function = "qpic";
|
||||
+ bias-pull-down;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
blsp_dma: dma@7884000 {
|
||||
@@ -159,5 +179,15 @@
|
||||
@@ -159,5 +239,15 @@
|
||||
watchdog@b017000 {
|
||||
status = "ok";
|
||||
};
|
||||
@ -60,7 +120,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -609,5 +609,43 @@
|
||||
@@ -580,5 +580,43 @@
|
||||
"legacy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -0,0 +1,44 @@
|
||||
From patchwork Mon Jul 3 07:47:12 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v3,1/2] dts: ipq4019: Fix pinctrl node name
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
X-Patchwork-Id: 9822099
|
||||
Message-Id: <1499068033-24000-2-git-send-email-varada@codeaurora.org>
|
||||
To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org,
|
||||
mark.rutland@arm.com, linux@armlinux.org.uk,
|
||||
linux-arm-msm@vger.kernel.org,
|
||||
linux-soc@vger.kernel.org, devicetree@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
|
||||
Cc: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Mon, 3 Jul 2017 13:17:12 +0530
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -40,7 +40,7 @@
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
- pinctrl@0x01000000 {
|
||||
+ pinctrl@1000000 {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio60", "gpio61";
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -149,7 +149,7 @@
|
||||
reg = <0x1800000 0x60000>;
|
||||
};
|
||||
|
||||
- tlmm: pinctrl@0x01000000 {
|
||||
+ tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq4019-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
gpio-controller;
|
||||
@ -0,0 +1,78 @@
|
||||
From patchwork Mon Jul 3 07:47:13 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v3,2/2] dts: ipq4019: Move xo and timer nodes to SoC dtsi
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
X-Patchwork-Id: 9822107
|
||||
Message-Id: <1499068033-24000-3-git-send-email-varada@codeaurora.org>
|
||||
To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org,
|
||||
mark.rutland@arm.com, linux@armlinux.org.uk,
|
||||
linux-arm-msm@vger.kernel.org,
|
||||
linux-soc@vger.kernel.org, devicetree@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
|
||||
Cc: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Mon, 3 Jul 2017 13:17:13 +0530
|
||||
|
||||
The node for xo and timer belong to the SoC DTS file.
|
||||
Else, new board DT files may not inherit these nodes.
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 19 -------------------
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 15 +++++++++++++++
|
||||
2 files changed, 15 insertions(+), 19 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -20,26 +20,7 @@
|
||||
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
|
||||
compatible = "qcom,ipq4019";
|
||||
|
||||
- clocks {
|
||||
- xo: xo {
|
||||
- compatible = "fixed-clock";
|
||||
- clock-frequency = <48000000>;
|
||||
- #clock-cells = <0>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
soc {
|
||||
-
|
||||
-
|
||||
- timer {
|
||||
- compatible = "arm,armv7-timer";
|
||||
- interrupts = <1 2 0xf08>,
|
||||
- <1 3 0xf08>,
|
||||
- <1 4 0xf08>,
|
||||
- <1 1 0xf08>;
|
||||
- clock-frequency = <48000000>;
|
||||
- };
|
||||
-
|
||||
pinctrl@1000000 {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -126,6 +126,21 @@
|
||||
clock-frequency = <32768>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
+
|
||||
+ xo: xo {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <48000000>;
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv7-timer";
|
||||
+ interrupts = <1 2 0xf08>,
|
||||
+ <1 3 0xf08>,
|
||||
+ <1 4 0xf08>,
|
||||
+ <1 1 0xf08>;
|
||||
+ clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
@ -0,0 +1,11 @@
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
@@ -38,7 +38,7 @@
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
- pinctrl@0x01000000 {
|
||||
+ pinctrl@1000000 {
|
||||
serial_0_pins: serial_pinmux {
|
||||
mux {
|
||||
pins = "gpio16", "gpio17";
|
||||
@ -0,0 +1,27 @@
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
|
||||
@@ -20,24 +20,7 @@
|
||||
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
|
||||
compatible = "qcom,ipq4019";
|
||||
|
||||
- clocks {
|
||||
- xo: xo {
|
||||
- compatible = "fixed-clock";
|
||||
- clock-frequency = <48000000>;
|
||||
- #clock-cells = <0>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
soc {
|
||||
- timer {
|
||||
- compatible = "arm,armv7-timer";
|
||||
- interrupts = <1 2 0xf08>,
|
||||
- <1 3 0xf08>,
|
||||
- <1 4 0xf08>,
|
||||
- <1 1 0xf08>;
|
||||
- clock-frequency = <48000000>;
|
||||
- };
|
||||
-
|
||||
pinctrl@1000000 {
|
||||
serial_0_pins: serial_pinmux {
|
||||
mux {
|
||||
@ -0,0 +1,42 @@
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -15,12 +15,39 @@
|
||||
*/
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
+#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
|
||||
compatible = "qcom,ipq4019";
|
||||
|
||||
soc {
|
||||
+ tcsr@194b000 {
|
||||
+ /* select hostmode */
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x194b000 0x100>;
|
||||
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ ess_tcsr@1953000 {
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x1953000 0x1000>;
|
||||
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
+ };
|
||||
+
|
||||
+ tcsr@1949000 {
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x1949000 0x100>;
|
||||
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
+ };
|
||||
+
|
||||
+ tcsr@1957000 {
|
||||
+ compatible = "qcom,tcsr";
|
||||
+ reg = <0x1957000 0x100>;
|
||||
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
+ };
|
||||
+
|
||||
pinctrl@1000000 {
|
||||
serial_pins: serial_pinmux {
|
||||
mux {
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user