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Merge branch 'master' of https://github.com/coolsnowwolf/lede

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This commit is contained in:
lean 2021-12-23 00:40:24 +08:00
commit ad4916ff3f
19 changed files with 2536 additions and 446 deletions
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15
package/boot/uboot-rockchip/Makefile
View File

@ -60,6 +60,18 @@ define U-Boot/orangepi-r1-plus-rk3328
USE_RKBIN:=1
endef
define U-Boot/orangepi-r1-plus-lts-rk3328
BUILD_SUBTARGET:=armv8
NAME:=Orange Pi R1 Plus LTS
BUILD_DEVICES:= \
xunlong_orangepi-r1-plus-lts
DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-lts-rk3328:arm-trusted-firmware-rk3328
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
ATF:=rk322xh_bl31_v1.46.elf
OF_PLATDATA:=$(1)
USE_RKBIN:=1
endef
define U-Boot/doornet1-rk3328
BUILD_SUBTARGET:=armv8
NAME:=DoorNet1
@ -135,7 +147,8 @@ UBOOT_TARGETS := \
doornet1-rk3328 \
nanopi-r2c-rk3328 \
nanopi-r2s-rk3328 \
orangepi-r1-plus-rk3328
orangepi-r1-plus-rk3328 \
orangepi-r1-plus-lts-rk3328
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes

144
package/boot/uboot-rockchip/patches/202-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch Normal file
View File

@ -0,0 +1,144 @@
From 68836b81f7d6328a1a5a6cce5a00bf4010f742e5 Mon Sep 17 00:00:00 2001
From: baiywt <baiywt_gj@163.com>
Date: Wed, 24 Nov 2021 19:59:38 +0800
Subject: [PATCH] Add support for Orangepi R1 Plus LTS
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 7 ++
configs/orangepi-r1-plus-lts-rk3328_defconfig | 98 +++++++++++++++++++
3 files changed, 106 insertions(+)
create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index adfe6c3f..3d4e0f59 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-orangepi-r1-plus.dtb \
+ rk3328-orangepi-r1-plus-lts.dtb \
rk3328-roc-cc.dtb \
rk3328-rock64.dtb \
rk3328-rock-pi-e.dtb
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
new file mode 100644
index 00000000..e6225b0c
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1 Plus LTS";
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
new file mode 100644
index 00000000..3cb3b5c3
--- /dev/null
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYSINFO=y
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--
2.25.1

23
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h Normal file
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@ -0,0 +1,23 @@
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(syscon);

154
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c Normal file
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@ -0,0 +1,154 @@
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: serial_at_ff130000 ns16550_serial
* 4: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x3a,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_sd_highspeed = true,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.sd_uhs_sdr104 = true,
.sd_uhs_sdr12 = true,
.sd_uhs_sdr25 = true,
.sd_uhs_sdr50 = true,
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x4b,
.vqmmc_supply = 0x1e,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 3
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x26,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/*
* Node /syscon@ff100000 index 4
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};

51
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h Normal file
View File

@ -0,0 +1,51 @@
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_sd_highspeed;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool sd_uhs_sdr104;
bool sd_uhs_sdr12;
bool sd_uhs_sdr25;
bool sd_uhs_sdr50;
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
fdt32_t vqmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};

8
package/lean/UnblockNeteaseMusic/Makefile
View File

@ -5,14 +5,14 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=UnblockNeteaseMusic
PKG_BASE_VERSION:=0.27.0-rc.2
PKG_BASE_VERSION:=0.27.0-rc.4
PKG_RELEASE:=$(AUTORELEASE)
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/UnblockNeteaseMusic/server.git
PKG_SOURCE_DATE:=2021-11-27
PKG_SOURCE_VERSION:=36c39d7b3ee94ef9ad5023be340f23fb47443c9b
PKG_MIRROR_HASH:=89fc9f1e62dfbf54c426512b664d5a58113dea7618160992248bab5e8db218a6
PKG_SOURCE_DATE:=2021-12-21
PKG_SOURCE_VERSION:=54b7a60b07a85dea3b52a5d9f1ada456aba12609
PKG_MIRROR_HASH:=1865a01021ced0a57bcb1f0d63ef72b0e517771602ad7e4026d18222713a77ac
PKG_VERSION:=$(PKG_BASE_VERSION)-$(PKG_SOURCE_DATE)-$(call version_abbrev,$(PKG_SOURCE_VERSION))

1
package/lean/luci-app-frpc/luasrc/model/cbi/frp/basic.lua
View File

@ -86,7 +86,6 @@ e.rmempty = false
e:depends("protocol","tcp")
e = t:taboption("other", Value, "http_proxy", translate("HTTP PROXY"))
e.datatype = "uinteger"
e.placeholder = "http://user:pwd@192.168.1.128:8080"
e:depends("enable_http_proxy",1)
e.optional = false

3
target/linux/rockchip/armv8/base-files/etc/board.d/01_leds
View File

@ -12,7 +12,8 @@ case $board in
embedfire,doornet1|\
friendlyarm,nanopi-r2c|\
friendlyarm,nanopi-r2s|\
xunlong,orangepi-r1-plus)
xunlong,orangepi-r1-plus|\
xunlong,orangepi-r1-plus-lts)
ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0"
ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1"
;;

6
target/linux/rockchip/armv8/base-files/etc/board.d/02_network
View File

@ -14,7 +14,8 @@ rockchip_setup_interfaces()
friendlyarm,nanopi-r2s|\
friendlyarm,nanopi-r4s|\
sharevdi,guangmiao-g4c|\
xunlong,orangepi-r1-plus)
xunlong,orangepi-r1-plus|\
xunlong,orangepi-r1-plus-lts)
ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
;;
*)
@ -50,7 +51,8 @@ rockchip_setup_macs()
wan_mac=$(get_mac_binary "/sys/bus/i2c/devices/2-0051/eeprom" 0xfa)
lan_mac=$(macaddr_setbit_la "$wan_mac")
;;
xunlong,orangepi-r1-plus)
xunlong,orangepi-r1-plus|\
xunlong,orangepi-r1-plus-lts)
lan_mac=$(cat /sys/class/net/eth1/address)
wan_mac=$(macaddr_add "$lan_mac" -1)
;;

3
target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity
View File

@ -31,7 +31,8 @@ case "$(board_name)" in
embedfire,doornet1|\
friendlyarm,nanopi-r2c|\
friendlyarm,nanopi-r2s|\
xunlong,orangepi-r1-plus)
xunlong,orangepi-r1-plus|\
xunlong,orangepi-r1-plus-lts)
set_interface_core 2 "eth0"
set_interface_core 4 "eth1" "xhci-hcd:usb3"
;;

10
target/linux/rockchip/image/armv8.mk
View File

@ -92,3 +92,13 @@ define Device/xunlong_orangepi-r1-plus
DEVICE_PACKAGES := kmod-usb-net-rtl8152
endef
TARGET_DEVICES += xunlong_orangepi-r1-plus
define Device/xunlong_orangepi-r1-plus-lts
DEVICE_VENDOR := Xunlong
DEVICE_MODEL := Orange Pi R1 Plus LTS
SOC := rk3328
UBOOT_DEVICE_NAME := orangepi-r1-plus-lts-rk3328
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
DEVICE_PACKAGES := kmod-usb-net-rtl8152
endef
TARGET_DEVICES += xunlong_orangepi-r1-plus-lts

101
target/linux/rockchip/patches-5.10/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch Normal file
View File

@ -0,0 +1,101 @@
From 9f0bfe430a5a67b34bc2274a898b4375a321810b Mon Sep 17 00:00:00 2001
From: baiywt <baiywt_gj@163.com>
Date: Mon, 15 Nov 2021 16:51:43 +0800
Subject: [PATCH] Add support for OrangePi R1 Plus LTS
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../rockchip/rk3328-orangepi-r1-plus-lts.dts | 44 +++++++++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 23373c752..552d97555 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -5,6 +5,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
new file mode 100644
index 000000000..c65f7c417
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1 Plus LTS";
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
+
+/delete-node/ &rtl8211e;
+&gmac2io {
+ phy-handle = <&ethphy3>;
+ snps,reset-delays-us = <0 15000 50000>;
+ tx_delay = <0x19>;
+ rx_delay = <0x05>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy3: ethernet-phy@0 {
+ reg = <0x0>;
+ keep-clkout-on;
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+ pinctrl-names = "default";
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_io_sdio>;
+ status = "okay";
+};
+
+&dmc_opp_table {
+ opp-1056000000 {
+ status = "disabled";
+ };
+ opp-924000000 {
+ status = "disabled";
+ };
+ opp-840000000 {
+ status = "disabled";
+ };
+ opp-798000000 {
+ status = "disabled";
+ };
+};
+
+&sys_led {
+ label = "orangepi-r1-plus-lts:red:sys";
+};
+
+&wan_led {
+ label = "orangepi-r1-plus-lts:green:wan";
+};
+
+&lan_led {
+ label = "orangepi-r1-plus-lts:green:lan";
+};
--
2.25.1

101
target/linux/rockchip/patches-5.4/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch Normal file
View File

@ -0,0 +1,101 @@
From 9f0bfe430a5a67b34bc2274a898b4375a321810b Mon Sep 17 00:00:00 2001
From: baiywt <baiywt_gj@163.com>
Date: Mon, 15 Nov 2021 16:51:43 +0800
Subject: [PATCH] Add support for OrangePi R1 Plus LTS
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../rockchip/rk3328-orangepi-r1-plus-lts.dts | 44 +++++++++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 23373c752..552d97555 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -5,6 +5,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
new file mode 100644
index 000000000..c65f7c417
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1 Plus LTS";
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
+
+/delete-node/ &rtl8211e;
+&gmac2io {
+ phy-handle = <&ethphy3>;
+ snps,reset-delays-us = <0 15000 50000>;
+ tx_delay = <0x19>;
+ rx_delay = <0x05>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy3: ethernet-phy@0 {
+ reg = <0x0>;
+ keep-clkout-on;
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+ pinctrl-names = "default";
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_io_sdio>;
+ status = "okay";
+};
+
+&dmc_opp_table {
+ opp-1056000000 {
+ status = "disabled";
+ };
+ opp-924000000 {
+ status = "disabled";
+ };
+ opp-840000000 {
+ status = "disabled";
+ };
+ opp-798000000 {
+ status = "disabled";
+ };
+};
+
+&sys_led {
+ label = "orangepi-r1-plus-lts:red:sys";
+};
+
+&wan_led {
+ label = "orangepi-r1-plus-lts:green:wan";
+};
+
+&lan_led {
+ label = "orangepi-r1-plus-lts:green:lan";
+};
--
2.25.1

1955
target/linux/rockchip/patches-5.4/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch
View File

File diff suppressed because it is too large Load Diff

5
tools/mkimage/Makefile
View File

@ -7,14 +7,14 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=mkimage
PKG_VERSION:=2021.01
PKG_VERSION:=2021.10
PKG_SOURCE:=u-boot-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:= \
https://mirror.cyberbits.eu/u-boot \
https://ftp.denx.de/pub/u-boot \
ftp://ftp.denx.de/pub/u-boot
PKG_HASH:=b407e1510a74e863b8b5cb42a24625344f0e0c2fc7582d8c866bd899367d0454
PKG_HASH:=cde723e19262e646f2670d25e5ec4b1b368490de950d4e26275a988c36df0bd4
HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/u-boot-$(PKG_VERSION)
@ -37,6 +37,7 @@ define Host/Compile
CONFIG_FIT=y \
CONFIG_FIT_SIGNATURE=y \
CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000 \
CONFIG_TOOLS_LIBCRYPTO=y \
tools-only
endef

12
tools/mkimage/patches/030-allow-to-use-different-magic.patch
View File

@ -2,7 +2,7 @@ This patch makes it possible to set a custom image magic.
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -21,6 +21,7 @@ static struct image_tool_params params =
@@ -24,6 +24,7 @@ static struct image_tool_params params =
.arch = IH_ARCH_PPC,
.type = IH_TYPE_KERNEL,
.comp = IH_COMP_GZIP,
@ -10,7 +10,7 @@ This patch makes it possible to set a custom image magic.
.dtc = MKIMAGE_DEFAULT_DTC_OPTIONS,
.imagename = "",
.imagename2 = "",
@@ -82,11 +83,12 @@ static void usage(const char *msg)
@@ -85,11 +86,12 @@ static void usage(const char *msg)
" -l ==> list image header information\n",
params.cmdname);
fprintf(stderr,
@ -24,16 +24,16 @@ This patch makes it possible to set a custom image magic.
" -a ==> set load address to 'addr' (hex)\n"
" -e ==> set entry point to 'ep' (hex)\n"
" -n ==> set image name to 'name'\n"
@@ -150,7 +152,7 @@ static void process_args(int argc, char
@@ -155,7 +157,7 @@ static void process_args(int argc, char
int opt;
while ((opt = getopt(argc, argv,
- "a:A:b:B:c:C:d:D:e:Ef:Fk:i:K:ln:N:p:O:rR:qstT:vVx")) != -1) {
+ "a:A:b:B:c:C:d:D:e:Ef:Fk:i:K:lM:n:N:p:O:rR:qstT:vVx")) != -1) {
- "a:A:b:B:c:C:d:D:e:Ef:FG:k:i:K:ln:N:p:O:rR:qstT:vVx")) != -1) {
+ "a:A:b:B:c:C:d:D:e:Ef:FG:k:i:K:lM:n:N:p:O:rR:qstT:vVx")) != -1) {
switch (opt) {
case 'a':
params.addr = strtoull(optarg, &ptr, 16);
@@ -237,6 +239,14 @@ static void process_args(int argc, char
@@ -245,6 +247,14 @@ static void process_args(int argc, char
case 'l':
params.lflag = 1;
break;

4
tools/mkimage/patches/050-Add-compatibility-with-non-Linux-hosts.patch
View File

@ -15,11 +15,9 @@ __u64 is not available on FreeBSD, remove its usage.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
include/image.h | 2 ++
include/imx8image.h | 5 +++++
include/linux/posix_types.h | 2 ++
include/linux/types.h | 4 +++-
lib/rsa/rsa-sign.c | 2 +-
5 files changed, 13 insertions(+), 2 deletions(-)
3 files changed, 7 insertions(+), 1 deletion(-)
--- a/include/image.h
+++ b/include/image.h

134
tools/mkimage/patches/080-mtk_image-add-support-for-booting-ARM64-images.patch
View File

@ -1,134 +0,0 @@
From 44165e4c676d266f73fda2e6ba82b4bf3262daf2 Mon Sep 17 00:00:00 2001
From: Fabien Parent <fparent@baylibre.com>
Date: Fri, 16 Oct 2020 19:52:37 +0200
Subject: [PATCH] tools: mtk_image: add support for booting ARM64 images
mkimage is only able to package aarch32 binaries. Add support for
AArch64 images.
One can create a ARM64 image using the following command line:
mkimage -T mtk_image -a 0x201000 -e 0x201000 -n "media=emmc;arm64=1"
-d bl2.bin bl2.img
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
tools/mtk_image.c | 28 ++++++++++++++++++++++++----
tools/mtk_image.h | 6 +++++-
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/tools/mtk_image.c b/tools/mtk_image.c
index 2ca519483d..bde1e5da4b 100644
--- a/tools/mtk_image.c
+++ b/tools/mtk_image.c
@@ -246,6 +246,7 @@ static const struct brom_img_type {
/* Image type selected by user */
static enum brlyt_img_type hdr_media;
static int use_lk_hdr;
+static bool is_arm64_image;
/* LK image name */
static char lk_name[32] = "U-Boot";
@@ -276,6 +277,7 @@ static int mtk_brom_parse_imagename(const char *imagename)
static const char *media = "";
static const char *nandinfo = "";
static const char *lk = "";
+ static const char *arm64_param = "";
key = buf;
while (key) {
@@ -323,6 +325,9 @@ static int mtk_brom_parse_imagename(const char *imagename)
if (!strcmp(key, "lkname"))
snprintf(lk_name, sizeof(lk_name), "%s", val);
+
+ if (!strcmp(key, "arm64"))
+ arm64_param = val;
}
if (next)
@@ -354,6 +359,9 @@ static int mtk_brom_parse_imagename(const char *imagename)
}
}
+ if (arm64_param && arm64_param[0] == '1')
+ is_arm64_image = true;
+
free(buf);
if (hdr_media == BRLYT_TYPE_INVALID) {
@@ -458,6 +466,9 @@ static int mtk_image_verify_gen_header(const uint8_t *ptr, int print)
le32_to_cpu(gfh->file_info.load_addr) +
le32_to_cpu(gfh->file_info.jump_offset));
+ if (print)
+ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM");
+
return 0;
}
@@ -523,6 +534,9 @@ static int mtk_image_verify_nand_header(const uint8_t *ptr, int print)
le32_to_cpu(gfh->file_info.load_addr) +
le32_to_cpu(gfh->file_info.jump_offset));
+ if (print)
+ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM");
+
return 0;
}
@@ -581,6 +595,8 @@ static void put_ghf_common_header(struct gfh_common_header *gfh, int size,
static void put_ghf_header(struct gfh_header *gfh, int file_size,
int dev_hdr_size, int load_addr, int flash_type)
{
+ uint32_t cfg_bits;
+
memset(gfh, 0, sizeof(struct gfh_header));
/* GFH_FILE_INFO header */
@@ -608,11 +624,15 @@ static void put_ghf_header(struct gfh_header *gfh, int file_size,
/* GFH_BROM_CFG header */
put_ghf_common_header(&gfh->brom_cfg.gfh, sizeof(gfh->brom_cfg),
GFH_TYPE_BROM_CFG, 3);
- gfh->brom_cfg.cfg_bits = cpu_to_le32(
- GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS |
- GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN |
- GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN);
+ cfg_bits = GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS |
+ GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN |
+ GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN;
gfh->brom_cfg.usbdl_by_kcol0_timeout_ms = cpu_to_le32(5000);
+ if (is_arm64_image) {
+ gfh->brom_cfg.jump_bl_arm64 = GFH_BROM_CFG_JUMP_BL_ARM64;
+ cfg_bits |= GFH_BROM_CFG_JUMP_BL_ARM64_EN;
+ }
+ gfh->brom_cfg.cfg_bits = cpu_to_le32(cfg_bits);
/* GFH_BL_SEC_KEY header */
put_ghf_common_header(&gfh->bl_sec_key.gfh, sizeof(gfh->bl_sec_key),
diff --git a/tools/mtk_image.h b/tools/mtk_image.h
index 4e78b3d0ff..7dda71ce88 100644
--- a/tools/mtk_image.h
+++ b/tools/mtk_image.h
@@ -136,7 +136,9 @@ struct gfh_brom_cfg {
struct gfh_common_header gfh;
uint32_t cfg_bits;
uint32_t usbdl_by_auto_detect_timeout_ms;
- uint8_t unused[0x48];
+ uint8_t unused[0x45];
+ uint8_t jump_bl_arm64;
+ uint8_t unused2[2];
uint32_t usbdl_by_kcol0_timeout_ms;
uint32_t usbdl_by_flag_timeout_ms;
uint32_t pad;
@@ -146,6 +148,8 @@ struct gfh_brom_cfg {
#define GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS 0x10
#define GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN 0x80
#define GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN 0x100
+#define GFH_BROM_CFG_JUMP_BL_ARM64_EN 0x1000
+#define GFH_BROM_CFG_JUMP_BL_ARM64 0x64
struct gfh_bl_sec_key {
struct gfh_common_header gfh;
--
2.30.1

226
tools/mkimage/patches/081-mtk_image-add-an-option-to-set-device-header-offset.patch
View File

@ -1,226 +0,0 @@
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From: Weijie Gao <weijie.gao@mediatek.com>
To: <u-boot@lists.denx.de>
CC: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>, Weijie Gao
<weijie.gao@mediatek.com>
Subject: [PATCH] tools: mtk_image: add an option to set device header offset
Date: Tue, 9 Mar 2021 15:52:31 +0800
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This patch adds an option which allows setting the device header offset.
This is useful if this tool is used to generate ATF BL2 image of mt7622 for
SD cards.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
tools/mtk_image.c | 50 ++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 47 insertions(+), 3 deletions(-)
diff --git a/tools/mtk_image.c b/tools/mtk_image.c
index bde1e5da4b..418c5fd54b 100644
--- a/tools/mtk_image.c
+++ b/tools/mtk_image.c
@@ -243,8 +243,13 @@ static const struct brom_img_type {
}
};
+/* Indicates whether we're generating or verifying */
+static bool img_gen;
+static uint32_t img_size;
+
/* Image type selected by user */
static enum brlyt_img_type hdr_media;
+static uint32_t hdr_offset;
static int use_lk_hdr;
static bool is_arm64_image;
@@ -275,6 +280,7 @@ static int mtk_brom_parse_imagename(const char *imagename)
/* User passed arguments from image name */
static const char *media = "";
+ static const char *hdr_offs = "";
static const char *nandinfo = "";
static const char *lk = "";
static const char *arm64_param = "";
@@ -317,6 +323,9 @@ static int mtk_brom_parse_imagename(const char *imagename)
if (!strcmp(key, "media"))
media = val;
+ if (!strcmp(key, "hdroffset"))
+ hdr_offs = val;
+
if (!strcmp(key, "nandinfo"))
nandinfo = val;
@@ -359,6 +368,10 @@ static int mtk_brom_parse_imagename(const char *imagename)
}
}
+ /* parse device header offset */
+ if (hdr_offs && hdr_offs[0])
+ hdr_offset = strtoul(hdr_offs, NULL, 0);
+
if (arm64_param && arm64_param[0] == '1')
is_arm64_image = true;
@@ -422,6 +435,7 @@ static int mtk_image_vrec_header(struct image_tool_params *params,
static int mtk_image_verify_gen_header(const uint8_t *ptr, int print)
{
union gen_boot_header *gbh = (union gen_boot_header *)ptr;
+ uint32_t gfh_offset, total_size, devh_size;
struct brom_layout_header *bh;
struct gfh_header *gfh;
const char *bootmedia;
@@ -453,7 +467,32 @@ static int mtk_image_verify_gen_header(const uint8_t *ptr, int print)
le32_to_cpu(bh->type) != BRLYT_TYPE_SDMMC))
return -1;
- gfh = (struct gfh_header *)(ptr + le32_to_cpu(bh->header_size));
+ devh_size = sizeof(struct gen_device_header);
+
+ if (img_gen) {
+ gfh_offset = devh_size;
+ } else {
+ gfh_offset = le32_to_cpu(bh->header_size);
+
+ if (gfh_offset + sizeof(struct gfh_header) > img_size) {
+ /*
+ * This may happen if the hdr_offset used to generate
+ * this image is not zero.
+ * Since device header size is not fixed, we can't
+ * cover all possible cases.
+ * Assuming the image is valid only if the real
+ * device header size equals to devh_size.
+ */
+ total_size = le32_to_cpu(bh->total_size);
+
+ if (total_size - gfh_offset > img_size - devh_size)
+ return -1;
+
+ gfh_offset = devh_size;
+ }
+ }
+
+ gfh = (struct gfh_header *)(ptr + gfh_offset);
if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME))
return -1;
@@ -549,6 +588,8 @@ static int mtk_image_verify_header(unsigned char *ptr, int image_size,
if (le32_to_cpu(lk->magic) == LK_PART_MAGIC)
return 0;
+ img_size = image_size;
+
if (!strcmp((char *)ptr, NAND_BOOT_NAME))
return mtk_image_verify_nand_header(ptr, 0);
else
@@ -682,8 +723,8 @@ static void mtk_image_set_gen_header(void *ptr, off_t filesize,
/* BRLYT header */
put_brom_layout_header(&hdr->brlyt, hdr_media);
- hdr->brlyt.header_size = cpu_to_le32(sizeof(struct gen_device_header));
- hdr->brlyt.total_size = cpu_to_le32(filesize);
+ hdr->brlyt.header_size = cpu_to_le32(hdr_offset + sizeof(*hdr));
+ hdr->brlyt.total_size = cpu_to_le32(hdr_offset + filesize);
hdr->brlyt.header_size_2 = hdr->brlyt.header_size;
hdr->brlyt.total_size_2 = hdr->brlyt.total_size;
@@ -747,6 +788,9 @@ static void mtk_image_set_header(void *ptr, struct stat *sbuf, int ifd,
return;
}
+ img_gen = true;
+ img_size = sbuf->st_size;
+
if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND)
mtk_image_set_nand_header(ptr, sbuf->st_size, params->addr);
else