From ab8cac3519b876ab954baa530e35d7d32c6eb502 Mon Sep 17 00:00:00 2001 From: coolsnowwolf Date: Fri, 22 Nov 2024 10:57:43 +0800 Subject: [PATCH] rockchip: backport upstream rk3576 support for kernel 6.6 --- target/linux/rockchip/armv8/config-6.6 | 1 + ...ip-grf-Add-rk3576-default-GRF-values.patch | 73 + ...-rockchip-Add-rk3576-pinctrl-support.patch | 307 + ...s-clock-reset-Add-support-for-rk3576.patch | 1250 +++ ...chip-Add-new-pll-type-pll_rk3588_ddr.patch | 51 + ...-Add-clock-controller-for-the-RK3576.patch | 2605 ++++++ ...et-fix-top-comment-indentation-rk357.patch | 58 + ...hip-fix-finding-of-maximum-clock-ID.patch} | 0 ...ngs-power-Add-support-for-RK3576-SoC.patch | 63 + ...-rockchip-Add-support-for-RK3576-SoC.patch | 98 + ...pmdomain-rockchip-Add-gating-support.patch | 80 + ...rockchip-Add-gating-masks-for-rk3576.patch | 109 + ...sb2-convert-clock-management-to-bulk.patch | 119 + ...sb2-Add-usb2-phys-support-for-rk3576.patch | 143 + ...p-usbdp-add-rk3576-device-match-data.patch | 73 + ...an-the-format-of-the-GPIO-version-ID.patch | 37 + ...ange-the-GPIO-version-judgment-logic.patch | 46 + ...io-rockchip-support-new-version-GPIO.patch | 34 + ...-rockchip-Add-internal-phase-support.patch | 260 + ...rockchip-Add-support-for-rk3576-SoCs.patch | 111 + ...ac-dwmac-rk-Fix-typo-for-RK3588-code.patch | 40 + ...dwmac-rk-Add-GMAC-support-for-RK3576.patch | 189 + ...-dts-rockchip-Add-rk3576-SoC-base-DT.patch | 7486 +++++++++++++++++ .../patches-6.6/106-rockchip-rock-pi-4.patch | 4 +- ...icro-stmmac-Add-SGMII-QSGMII-support.patch | 10 +- ...chip-naneng-combo-add-rk3576-support.patch | 375 + ...-support-for-FriendlyARM-NanoPi-Neo3.patch | 2 +- ...ip-rk356x-add-support-for-new-boards.patch | 4 +- ...chip-rk3399-add-support-more-devices.patch | 2 +- ...ip-rk3528-add-support-for-new-boards.patch | 2 +- ...-pinctrl-rockchip-add-rk3528-support.patch | 24 +- ...-rockchip-power-domain-Add-always-on.patch | 8 +- ...chip-power-domain-add-rk3528-support.patch | 12 +- ...-add-clock-controller-for-the-RK3528.patch | 9 +- ...stmmac-dwmac-rk3528-add-GMAC-support.patch | 4 +- ...inno-usb2-add-phy-support-for-rk3528.patch | 6 +- ...ip-naneng-combphy-add-support-rk3528.patch | 14 +- ...w_mmc-rockchip-add-v2-tuning-support.patch | 24 +- ...setting-ddr-clock-via-SIP-Version-2-.patch | 2 +- ...m64-dts-rockchip-rk3328-add-dfi-node.patch | 2 +- 40 files changed, 13674 insertions(+), 63 deletions(-) create mode 100644 target/linux/rockchip/patches-6.6/030-09-v6.12-soc-rockchip-grf-Add-rk3576-default-GRF-values.patch create mode 100644 target/linux/rockchip/patches-6.6/030-10-v6.12-pinctrl-rockchip-Add-rk3576-pinctrl-support.patch create mode 100644 target/linux/rockchip/patches-6.6/030-11-v6.12-dt-bindings-clock-reset-Add-support-for-rk3576.patch create mode 100644 target/linux/rockchip/patches-6.6/030-12-v6.12-clk-rockchip-Add-new-pll-type-pll_rk3588_ddr.patch create mode 100644 target/linux/rockchip/patches-6.6/030-13-v6.12-clk-rockchip-Add-clock-controller-for-the-RK3576.patch create mode 100644 target/linux/rockchip/patches-6.6/030-14-v6.12-dt-bindings-clock-reset-fix-top-comment-indentation-rk357.patch rename target/linux/rockchip/patches-6.6/{035-v6.12-clk-rockchip-fix-finding-of-maximum-clock-ID.patch => 030-15-v6.12-clk-rockchip-fix-finding-of-maximum-clock-ID.patch} (100%) create mode 100644 target/linux/rockchip/patches-6.6/031-03-v6.12-dt-bindings-power-Add-support-for-RK3576-SoC.patch create mode 100644 target/linux/rockchip/patches-6.6/031-04-v6.12-pmdomain-rockchip-Add-support-for-RK3576-SoC.patch create mode 100644 target/linux/rockchip/patches-6.6/031-05-v6.12-pmdomain-rockchip-Add-gating-support.patch create mode 100644 target/linux/rockchip/patches-6.6/031-06-v6.12-pmdomain-rockchip-Add-gating-masks-for-rk3576.patch create mode 100644 target/linux/rockchip/patches-6.6/032-06-v6.13-phy-rockchip-inno-usb2-convert-clock-management-to-bulk.patch create mode 100644 target/linux/rockchip/patches-6.6/032-07-v6.13-phy-rockchip-inno-usb2-Add-usb2-phys-support-for-rk3576.patch create mode 100644 target/linux/rockchip/patches-6.6/032-08-v6.13-phy-rockchip-usbdp-add-rk3576-device-match-data.patch create mode 100644 target/linux/rockchip/patches-6.6/033-01-v6.13-gpio-rockchip-explan-the-format-of-the-GPIO-version-ID.patch create mode 100644 target/linux/rockchip/patches-6.6/033-02-v6.13-gpio-rockchip-change-the-GPIO-version-judgment-logic.patch create mode 100644 target/linux/rockchip/patches-6.6/033-03-v6.13-gpio-rockchip-support-new-version-GPIO.patch create mode 100644 target/linux/rockchip/patches-6.6/035-01-v6.12-mmc-dw_mmc-rockchip-Add-internal-phase-support.patch create mode 100644 target/linux/rockchip/patches-6.6/035-02-v6.12-mmc-dw_mmc-rockchip-Add-support-for-rk3576-SoCs.patch create mode 100644 target/linux/rockchip/patches-6.6/036-01-v6.12-ethernet-stmmac-dwmac-rk-Fix-typo-for-RK3588-code.patch create mode 100644 target/linux/rockchip/patches-6.6/036-02-v6.12-ethernet-stmmac-dwmac-rk-Add-GMAC-support-for-RK3576.patch create mode 100644 target/linux/rockchip/patches-6.6/060-v6.13-arm64-dts-rockchip-Add-rk3576-SoC-base-DT.patch create mode 100644 target/linux/rockchip/patches-6.6/120-phy-rockchip-naneng-combo-add-rk3576-support.patch diff --git a/target/linux/rockchip/armv8/config-6.6 b/target/linux/rockchip/armv8/config-6.6 index 6bb5d3186..5c11cc278 100644 --- a/target/linux/rockchip/armv8/config-6.6 +++ b/target/linux/rockchip/armv8/config-6.6 @@ -137,6 +137,7 @@ CONFIG_CLK_RK3368=y CONFIG_CLK_RK3399=y CONFIG_CLK_RK3528=y CONFIG_CLK_RK3568=y +CONFIG_CLK_RK3576=y CONFIG_CLK_RK3588=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMA=y diff --git a/target/linux/rockchip/patches-6.6/030-09-v6.12-soc-rockchip-grf-Add-rk3576-default-GRF-values.patch b/target/linux/rockchip/patches-6.6/030-09-v6.12-soc-rockchip-grf-Add-rk3576-default-GRF-values.patch new file mode 100644 index 000000000..ef60264be --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-09-v6.12-soc-rockchip-grf-Add-rk3576-default-GRF-values.patch @@ -0,0 +1,73 @@ +From e1aaecacfa135cd264a0db331d3ab8b2a04a54a3 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Thu, 22 Aug 2024 15:53:37 -0400 +Subject: [PATCH] soc: rockchip: grf: Add rk3576 default GRF values + +Set SW controlled i3c weak pull up and disable JTAG function on SDMMC IO. + +The i3c weak pull up is activated to let all gpio banks be controlled +by the pinctrl driver. + +Disabling the JTAG function lets the SDMMC core use its full IO width. + +Signed-off-by: Detlev Casanova +Acked-by: Dragan Simic +Link: https://lore.kernel.org/r/20240822195706.920567-3-detlev.casanova@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/soc/rockchip/grf.c | 30 +++++++++++++++++++++++++++++- + 1 file changed, 29 insertions(+), 1 deletion(-) + +--- a/drivers/soc/rockchip/grf.c ++++ b/drivers/soc/rockchip/grf.c +@@ -121,6 +121,29 @@ static const struct rockchip_grf_info rk + .num_values = ARRAY_SIZE(rk3566_defaults), + }; + ++#define RK3576_SYSGRF_SOC_CON1 0x0004 ++ ++static const struct rockchip_grf_value rk3576_defaults_sys_grf[] __initconst = { ++ { "i3c0 weakpull", RK3576_SYSGRF_SOC_CON1, HIWORD_UPDATE(3, 3, 6) }, ++ { "i3c1 weakpull", RK3576_SYSGRF_SOC_CON1, HIWORD_UPDATE(3, 3, 8) }, ++}; ++ ++static const struct rockchip_grf_info rk3576_sysgrf __initconst = { ++ .values = rk3576_defaults_sys_grf, ++ .num_values = ARRAY_SIZE(rk3576_defaults_sys_grf), ++}; ++ ++#define RK3576_IOCGRF_MISC_CON 0x04F0 ++ ++static const struct rockchip_grf_value rk3576_defaults_ioc_grf[] __initconst = { ++ { "jtag switching", RK3576_IOCGRF_MISC_CON, HIWORD_UPDATE(0, 1, 1) }, ++}; ++ ++static const struct rockchip_grf_info rk3576_iocgrf __initconst = { ++ .values = rk3576_defaults_ioc_grf, ++ .num_values = ARRAY_SIZE(rk3576_defaults_ioc_grf), ++}; ++ + #define RK3588_GRF_SOC_CON6 0x0318 + + static const struct rockchip_grf_value rk3588_defaults[] __initconst = { +@@ -132,7 +155,6 @@ static const struct rockchip_grf_info rk + .num_values = ARRAY_SIZE(rk3588_defaults), + }; + +- + static const struct of_device_id rockchip_grf_dt_match[] __initconst = { + { + .compatible = "rockchip,rk3036-grf", +@@ -159,6 +181,12 @@ static const struct of_device_id rockchi + .compatible = "rockchip,rk3566-pipe-grf", + .data = (void *)&rk3566_pipegrf, + }, { ++ .compatible = "rockchip,rk3576-sys-grf", ++ .data = (void *)&rk3576_sysgrf, ++ }, { ++ .compatible = "rockchip,rk3576-ioc-grf", ++ .data = (void *)&rk3576_iocgrf, ++ }, { + .compatible = "rockchip,rk3588-sys-grf", + .data = (void *)&rk3588_sysgrf, + }, diff --git a/target/linux/rockchip/patches-6.6/030-10-v6.12-pinctrl-rockchip-Add-rk3576-pinctrl-support.patch b/target/linux/rockchip/patches-6.6/030-10-v6.12-pinctrl-rockchip-Add-rk3576-pinctrl-support.patch new file mode 100644 index 000000000..9a3493728 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-10-v6.12-pinctrl-rockchip-Add-rk3576-pinctrl-support.patch @@ -0,0 +1,307 @@ +From 69c6343ed03486c86271c7a4fdd5a2af4637c38b Mon Sep 17 00:00:00 2001 +From: Steven Liu +Date: Thu, 22 Aug 2024 15:53:39 -0400 +Subject: [PATCH] pinctrl: rockchip: Add rk3576 pinctrl support + +Add support for the 5 rk3576 GPIO banks. + +Signed-off-by: Steven Liu +Signed-off-by: Detlev Casanova +Acked-by: Dragan Simic +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/20240822195706.920567-5-detlev.casanova@collabora.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/pinctrl-rockchip.c | 207 +++++++++++++++++++++++++++++ + drivers/pinctrl/pinctrl-rockchip.h | 1 + + 2 files changed, 208 insertions(+) + +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -84,6 +84,27 @@ + }, \ + } + ++#define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \ ++ iom1, iom2, iom3, \ ++ offset0, offset1, \ ++ offset2, offset3, pull0, \ ++ pull1, pull2, pull3) \ ++ { \ ++ .bank_num = id, \ ++ .nr_pins = pins, \ ++ .name = label, \ ++ .iomux = { \ ++ { .type = iom0, .offset = offset0 }, \ ++ { .type = iom1, .offset = offset1 }, \ ++ { .type = iom2, .offset = offset2 }, \ ++ { .type = iom3, .offset = offset3 }, \ ++ }, \ ++ .pull_type[0] = pull0, \ ++ .pull_type[1] = pull1, \ ++ .pull_type[2] = pull2, \ ++ .pull_type[3] = pull3, \ ++ } ++ + #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ + { \ + .bank_num = id, \ +@@ -1120,6 +1141,11 @@ static int rockchip_get_mux(struct rockc + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + ++ if (ctrl->type == RK3576) { ++ if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) ++ reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ ++ } ++ + if (ctrl->type == RK3588) { + if (bank->bank_num == 0) { + if ((pin >= RK_PB4) && (pin <= RK_PD7)) { +@@ -1234,6 +1260,11 @@ static int rockchip_set_mux(struct rockc + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + ++ if (ctrl->type == RK3576) { ++ if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) ++ reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ ++ } ++ + if (ctrl->type == RK3588) { + if (bank->bank_num == 0) { + if ((pin >= RK_PB4) && (pin <= RK_PD7)) { +@@ -2038,6 +2069,142 @@ static int rk3568_calc_drv_reg_and_bit(s + return 0; + } + ++#define RK3576_DRV_BITS_PER_PIN 4 ++#define RK3576_DRV_PINS_PER_REG 4 ++#define RK3576_DRV_GPIO0_AL_OFFSET 0x10 ++#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014 ++#define RK3576_DRV_GPIO1_OFFSET 0x6020 ++#define RK3576_DRV_GPIO2_OFFSET 0x6040 ++#define RK3576_DRV_GPIO3_OFFSET 0x6060 ++#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080 ++#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090 ++#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098 ++ ++static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ ++ if (bank->bank_num == 0 && pin_num < 12) ++ *reg = RK3576_DRV_GPIO0_AL_OFFSET; ++ else if (bank->bank_num == 0) ++ *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc; ++ else if (bank->bank_num == 1) ++ *reg = RK3576_DRV_GPIO1_OFFSET; ++ else if (bank->bank_num == 2) ++ *reg = RK3576_DRV_GPIO2_OFFSET; ++ else if (bank->bank_num == 3) ++ *reg = RK3576_DRV_GPIO3_OFFSET; ++ else if (bank->bank_num == 4 && pin_num < 16) ++ *reg = RK3576_DRV_GPIO4_AL_OFFSET; ++ else if (bank->bank_num == 4 && pin_num < 24) ++ *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10; ++ else if (bank->bank_num == 4) ++ *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18; ++ else ++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); ++ ++ *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3576_DRV_PINS_PER_REG; ++ *bit *= RK3576_DRV_BITS_PER_PIN; ++ ++ return 0; ++} ++ ++#define RK3576_PULL_BITS_PER_PIN 2 ++#define RK3576_PULL_PINS_PER_REG 8 ++#define RK3576_PULL_GPIO0_AL_OFFSET 0x20 ++#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028 ++#define RK3576_PULL_GPIO1_OFFSET 0x6110 ++#define RK3576_PULL_GPIO2_OFFSET 0x6120 ++#define RK3576_PULL_GPIO3_OFFSET 0x6130 ++#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140 ++#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148 ++#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C ++ ++static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ ++ if (bank->bank_num == 0 && pin_num < 12) ++ *reg = RK3576_PULL_GPIO0_AL_OFFSET; ++ else if (bank->bank_num == 0) ++ *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4; ++ else if (bank->bank_num == 1) ++ *reg = RK3576_PULL_GPIO1_OFFSET; ++ else if (bank->bank_num == 2) ++ *reg = RK3576_PULL_GPIO2_OFFSET; ++ else if (bank->bank_num == 3) ++ *reg = RK3576_PULL_GPIO3_OFFSET; ++ else if (bank->bank_num == 4 && pin_num < 16) ++ *reg = RK3576_PULL_GPIO4_AL_OFFSET; ++ else if (bank->bank_num == 4 && pin_num < 24) ++ *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8; ++ else if (bank->bank_num == 4) ++ *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc; ++ else ++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); ++ ++ *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3576_PULL_PINS_PER_REG; ++ *bit *= RK3576_PULL_BITS_PER_PIN; ++ ++ return 0; ++} ++ ++#define RK3576_SMT_BITS_PER_PIN 1 ++#define RK3576_SMT_PINS_PER_REG 8 ++#define RK3576_SMT_GPIO0_AL_OFFSET 0x30 ++#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040 ++#define RK3576_SMT_GPIO1_OFFSET 0x6210 ++#define RK3576_SMT_GPIO2_OFFSET 0x6220 ++#define RK3576_SMT_GPIO3_OFFSET 0x6230 ++#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240 ++#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248 ++#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C ++ ++static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, ++ struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ ++ if (bank->bank_num == 0 && pin_num < 12) ++ *reg = RK3576_SMT_GPIO0_AL_OFFSET; ++ else if (bank->bank_num == 0) ++ *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4; ++ else if (bank->bank_num == 1) ++ *reg = RK3576_SMT_GPIO1_OFFSET; ++ else if (bank->bank_num == 2) ++ *reg = RK3576_SMT_GPIO2_OFFSET; ++ else if (bank->bank_num == 3) ++ *reg = RK3576_SMT_GPIO3_OFFSET; ++ else if (bank->bank_num == 4 && pin_num < 16) ++ *reg = RK3576_SMT_GPIO4_AL_OFFSET; ++ else if (bank->bank_num == 4 && pin_num < 24) ++ *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8; ++ else if (bank->bank_num == 4) ++ *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc; ++ else ++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); ++ ++ *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3576_SMT_PINS_PER_REG; ++ *bit *= RK3576_SMT_BITS_PER_PIN; ++ ++ return 0; ++} ++ + #define RK3588_PMU1_IOC_REG (0x0000) + #define RK3588_PMU2_IOC_REG (0x4000) + #define RK3588_BUS_IOC_REG (0x8000) +@@ -2332,6 +2499,10 @@ static int rockchip_set_drive_perpin(str + rmask_bits = RK3568_DRV_BITS_PER_PIN; + ret = (1 << (strength + 1)) - 1; + goto config; ++ } else if (ctrl->type == RK3576) { ++ rmask_bits = RK3576_DRV_BITS_PER_PIN; ++ ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1)); ++ goto config; + } + + if (ctrl->type == RV1126) { +@@ -2469,6 +2640,7 @@ static int rockchip_get_pull(struct rock + case RK3368: + case RK3399: + case RK3568: ++ case RK3576: + case RK3588: + pull_type = bank->pull_type[pin_num / 8]; + data >>= bit; +@@ -2528,6 +2700,7 @@ static int rockchip_set_pull(struct rock + case RK3368: + case RK3399: + case RK3568: ++ case RK3576: + case RK3588: + pull_type = bank->pull_type[pin_num / 8]; + ret = -EINVAL; +@@ -2793,6 +2966,7 @@ static bool rockchip_pinconf_pull_valid( + case RK3368: + case RK3399: + case RK3568: ++ case RK3576: + case RK3588: + return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); + } +@@ -3956,6 +4130,37 @@ static struct rockchip_pin_ctrl rk3568_p + .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, + }; + ++#define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \ ++ PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \ ++ IOMUX_WIDTH_4BIT, \ ++ IOMUX_WIDTH_4BIT, \ ++ IOMUX_WIDTH_4BIT, \ ++ IOMUX_WIDTH_4BIT, \ ++ OFFSET0, OFFSET1, \ ++ OFFSET2, OFFSET3, \ ++ PULL_TYPE_IO_1V8_ONLY, \ ++ PULL_TYPE_IO_1V8_ONLY, \ ++ PULL_TYPE_IO_1V8_ONLY, \ ++ PULL_TYPE_IO_1V8_ONLY) ++ ++static struct rockchip_pin_bank rk3576_pin_banks[] = { ++ RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C), ++ RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038), ++ RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058), ++ RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078), ++ RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398), ++}; ++ ++static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = { ++ .pin_banks = rk3576_pin_banks, ++ .nr_banks = ARRAY_SIZE(rk3576_pin_banks), ++ .label = "RK3576-GPIO", ++ .type = RK3576, ++ .pull_calc_reg = rk3576_calc_pull_reg_and_bit, ++ .drv_calc_reg = rk3576_calc_drv_reg_and_bit, ++ .schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit, ++}; ++ + static struct rockchip_pin_bank rk3588_pin_banks[] = { + RK3588_PIN_BANK_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), +@@ -4012,6 +4217,8 @@ static const struct of_device_id rockchi + .data = &rk3399_pin_ctrl }, + { .compatible = "rockchip,rk3568-pinctrl", + .data = &rk3568_pin_ctrl }, ++ { .compatible = "rockchip,rk3576-pinctrl", ++ .data = &rk3576_pin_ctrl }, + { .compatible = "rockchip,rk3588-pinctrl", + .data = &rk3588_pin_ctrl }, + {}, +--- a/drivers/pinctrl/pinctrl-rockchip.h ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -197,6 +197,7 @@ enum rockchip_pinctrl_type { + RK3368, + RK3399, + RK3568, ++ RK3576, + RK3588, + }; + diff --git a/target/linux/rockchip/patches-6.6/030-11-v6.12-dt-bindings-clock-reset-Add-support-for-rk3576.patch b/target/linux/rockchip/patches-6.6/030-11-v6.12-dt-bindings-clock-reset-Add-support-for-rk3576.patch new file mode 100644 index 000000000..e0f618061 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-11-v6.12-dt-bindings-clock-reset-Add-support-for-rk3576.patch @@ -0,0 +1,1250 @@ +From 49c04453db81fc806906e26ef9fc53bdb635ff39 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Wed, 28 Aug 2024 15:42:50 +0000 +Subject: [PATCH] dt-bindings: clock, reset: Add support for rk3576 + +Add clock and reset ID defines for rk3576. + +Compared to the downstream bindings written by Elaine, this uses +continous gapless IDs starting at 0. Thus all numbers are +different between downstream and upstream, but names are kept +exactly the same. + +Also add documentation for the rk3576 CRU core. + +Signed-off-by: Elaine Zhang +Signed-off-by: Sugar Zhang +Signed-off-by: Detlev Casanova +Reviewed-by: Rob Herring (Arm) +Link: https://lore.kernel.org/r/0102019199a76766-f3a2b53f-d063-458b-b0d1-dfbc2ea1893c-000000@eu-west-1.amazonses.com +Signed-off-by: Heiko Stuebner +--- + .../bindings/clock/rockchip,rk3576-cru.yaml | 56 ++ + .../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++++++++++++++++++ + .../dt-bindings/reset/rockchip,rk3576-cru.h | 564 +++++++++++++++++ + 3 files changed, 1212 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml + create mode 100644 include/dt-bindings/clock/rockchip,rk3576-cru.h + create mode 100644 include/dt-bindings/reset/rockchip,rk3576-cru.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml +@@ -0,0 +1,56 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip rk3576 Family Clock and Reset Control Module ++ ++maintainers: ++ - Elaine Zhang ++ - Heiko Stuebner ++ - Detlev Casanova ++ ++description: ++ The RK3576 clock controller generates the clock and also implements a reset ++ controller for SoC peripherals. For example it provides SCLK_UART2 and ++ PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART ++ module. ++ ++properties: ++ compatible: ++ const: rockchip,rk3576-cru ++ ++ reg: ++ maxItems: 1 ++ ++ "#clock-cells": ++ const: 1 ++ ++ "#reset-cells": ++ const: 1 ++ ++ clocks: ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: xin24m ++ - const: xin32k ++ ++required: ++ - compatible ++ - reg ++ - "#clock-cells" ++ - "#reset-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ clock-controller@27200000 { ++ compatible = "rockchip,rk3576-cru"; ++ reg = <0xfd7c0000 0x5c000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; +--- /dev/null ++++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h +@@ -0,0 +1,592 @@ ++/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ ++/* ++* Copyright (c) 2023 Rockchip Electronics Co. Ltd. ++* Copyright (c) 2024 Collabora Ltd. ++* ++* Author: Elaine Zhang ++* Author: Detlev Casanova ++*/ ++ ++#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H ++#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H ++ ++/* cru-clocks indices */ ++ ++/* cru plls */ ++#define PLL_BPLL 0 ++#define PLL_LPLL 1 ++#define PLL_VPLL 2 ++#define PLL_AUPLL 3 ++#define PLL_CPLL 4 ++#define PLL_GPLL 5 ++#define PLL_PPLL 6 ++#define ARMCLK_L 7 ++#define ARMCLK_B 8 ++ ++/* cru clocks */ ++#define CLK_CPLL_DIV20 9 ++#define CLK_CPLL_DIV10 10 ++#define CLK_GPLL_DIV8 11 ++#define CLK_GPLL_DIV6 12 ++#define CLK_CPLL_DIV4 13 ++#define CLK_GPLL_DIV4 14 ++#define CLK_SPLL_DIV2 15 ++#define CLK_GPLL_DIV3 16 ++#define CLK_CPLL_DIV2 17 ++#define CLK_GPLL_DIV2 18 ++#define CLK_SPLL_DIV1 19 ++#define PCLK_TOP_ROOT 20 ++#define ACLK_TOP 21 ++#define HCLK_TOP 22 ++#define CLK_AUDIO_FRAC_0 23 ++#define CLK_AUDIO_FRAC_1 24 ++#define CLK_AUDIO_FRAC_2 25 ++#define CLK_AUDIO_FRAC_3 26 ++#define CLK_UART_FRAC_0 27 ++#define CLK_UART_FRAC_1 28 ++#define CLK_UART_FRAC_2 29 ++#define CLK_UART1_SRC_TOP 30 ++#define CLK_AUDIO_INT_0 31 ++#define CLK_AUDIO_INT_1 32 ++#define CLK_AUDIO_INT_2 33 ++#define CLK_PDM0_SRC_TOP 34 ++#define CLK_PDM1_OUT 35 ++#define CLK_GMAC0_125M_SRC 36 ++#define CLK_GMAC1_125M_SRC 37 ++#define LCLK_ASRC_SRC_0 38 ++#define LCLK_ASRC_SRC_1 39 ++#define REF_CLK0_OUT_PLL 40 ++#define REF_CLK1_OUT_PLL 41 ++#define REF_CLK2_OUT_PLL 42 ++#define REFCLKO25M_GMAC0_OUT 43 ++#define REFCLKO25M_GMAC1_OUT 44 ++#define CLK_CIFOUT_OUT 45 ++#define CLK_GMAC0_RMII_CRU 46 ++#define CLK_GMAC1_RMII_CRU 47 ++#define CLK_OTPC_AUTO_RD_G 48 ++#define CLK_OTP_PHY_G 49 ++#define CLK_MIPI_CAMERAOUT_M0 50 ++#define CLK_MIPI_CAMERAOUT_M1 51 ++#define CLK_MIPI_CAMERAOUT_M2 52 ++#define MCLK_PDM0_SRC_TOP 53 ++#define HCLK_AUDIO_ROOT 54 ++#define HCLK_ASRC_2CH_0 55 ++#define HCLK_ASRC_2CH_1 56 ++#define HCLK_ASRC_4CH_0 57 ++#define HCLK_ASRC_4CH_1 58 ++#define CLK_ASRC_2CH_0 59 ++#define CLK_ASRC_2CH_1 60 ++#define CLK_ASRC_4CH_0 61 ++#define CLK_ASRC_4CH_1 62 ++#define MCLK_SAI0_8CH_SRC 63 ++#define MCLK_SAI0_8CH 64 ++#define HCLK_SAI0_8CH 65 ++#define HCLK_SPDIF_RX0 66 ++#define MCLK_SPDIF_RX0 67 ++#define HCLK_SPDIF_RX1 68 ++#define MCLK_SPDIF_RX1 69 ++#define MCLK_SAI1_8CH_SRC 70 ++#define MCLK_SAI1_8CH 71 ++#define HCLK_SAI1_8CH 72 ++#define MCLK_SAI2_2CH_SRC 73 ++#define MCLK_SAI2_2CH 74 ++#define HCLK_SAI2_2CH 75 ++#define MCLK_SAI3_2CH_SRC 76 ++#define MCLK_SAI3_2CH 77 ++#define HCLK_SAI3_2CH 78 ++#define MCLK_SAI4_2CH_SRC 79 ++#define MCLK_SAI4_2CH 80 ++#define HCLK_SAI4_2CH 81 ++#define HCLK_ACDCDIG_DSM 82 ++#define MCLK_ACDCDIG_DSM 83 ++#define CLK_PDM1 84 ++#define HCLK_PDM1 85 ++#define MCLK_PDM1 86 ++#define HCLK_SPDIF_TX0 87 ++#define MCLK_SPDIF_TX0 88 ++#define HCLK_SPDIF_TX1 89 ++#define MCLK_SPDIF_TX1 90 ++#define CLK_SAI1_MCLKOUT 91 ++#define CLK_SAI2_MCLKOUT 92 ++#define CLK_SAI3_MCLKOUT 93 ++#define CLK_SAI4_MCLKOUT 94 ++#define CLK_SAI0_MCLKOUT 95 ++#define HCLK_BUS_ROOT 96 ++#define PCLK_BUS_ROOT 97 ++#define ACLK_BUS_ROOT 98 ++#define HCLK_CAN0 99 ++#define CLK_CAN0 100 ++#define HCLK_CAN1 101 ++#define CLK_CAN1 102 ++#define CLK_KEY_SHIFT 103 ++#define PCLK_I2C1 104 ++#define PCLK_I2C2 105 ++#define PCLK_I2C3 106 ++#define PCLK_I2C4 107 ++#define PCLK_I2C5 108 ++#define PCLK_I2C6 109 ++#define PCLK_I2C7 110 ++#define PCLK_I2C8 111 ++#define PCLK_I2C9 112 ++#define PCLK_WDT_BUSMCU 113 ++#define TCLK_WDT_BUSMCU 114 ++#define ACLK_GIC 115 ++#define CLK_I2C1 116 ++#define CLK_I2C2 117 ++#define CLK_I2C3 118 ++#define CLK_I2C4 119 ++#define CLK_I2C5 120 ++#define CLK_I2C6 121 ++#define CLK_I2C7 122 ++#define CLK_I2C8 123 ++#define CLK_I2C9 124 ++#define PCLK_SARADC 125 ++#define CLK_SARADC 126 ++#define PCLK_TSADC 127 ++#define CLK_TSADC 128 ++#define PCLK_UART0 129 ++#define PCLK_UART2 130 ++#define PCLK_UART3 131 ++#define PCLK_UART4 132 ++#define PCLK_UART5 133 ++#define PCLK_UART6 134 ++#define PCLK_UART7 135 ++#define PCLK_UART8 136 ++#define PCLK_UART9 137 ++#define PCLK_UART10 138 ++#define PCLK_UART11 139 ++#define SCLK_UART0 140 ++#define SCLK_UART2 141 ++#define SCLK_UART3 142 ++#define SCLK_UART4 143 ++#define SCLK_UART5 144 ++#define SCLK_UART6 145 ++#define SCLK_UART7 146 ++#define SCLK_UART8 147 ++#define SCLK_UART9 148 ++#define SCLK_UART10 149 ++#define SCLK_UART11 150 ++#define PCLK_SPI0 151 ++#define PCLK_SPI1 152 ++#define PCLK_SPI2 153 ++#define PCLK_SPI3 154 ++#define PCLK_SPI4 155 ++#define CLK_SPI0 156 ++#define CLK_SPI1 157 ++#define CLK_SPI2 158 ++#define CLK_SPI3 159 ++#define CLK_SPI4 160 ++#define PCLK_WDT0 161 ++#define TCLK_WDT0 162 ++#define PCLK_PWM1 163 ++#define CLK_PWM1 164 ++#define CLK_OSC_PWM1 165 ++#define CLK_RC_PWM1 166 ++#define PCLK_BUSTIMER0 167 ++#define PCLK_BUSTIMER1 168 ++#define CLK_TIMER0_ROOT 169 ++#define CLK_TIMER0 170 ++#define CLK_TIMER1 171 ++#define CLK_TIMER2 172 ++#define CLK_TIMER3 173 ++#define CLK_TIMER4 174 ++#define CLK_TIMER5 175 ++#define PCLK_MAILBOX0 176 ++#define PCLK_GPIO1 177 ++#define DBCLK_GPIO1 178 ++#define PCLK_GPIO2 179 ++#define DBCLK_GPIO2 180 ++#define PCLK_GPIO3 181 ++#define DBCLK_GPIO3 182 ++#define PCLK_GPIO4 183 ++#define DBCLK_GPIO4 184 ++#define ACLK_DECOM 185 ++#define PCLK_DECOM 186 ++#define DCLK_DECOM 187 ++#define CLK_TIMER1_ROOT 188 ++#define CLK_TIMER6 189 ++#define CLK_TIMER7 190 ++#define CLK_TIMER8 191 ++#define CLK_TIMER9 192 ++#define CLK_TIMER10 193 ++#define CLK_TIMER11 194 ++#define ACLK_DMAC0 195 ++#define ACLK_DMAC1 196 ++#define ACLK_DMAC2 197 ++#define ACLK_SPINLOCK 198 ++#define HCLK_I3C0 199 ++#define HCLK_I3C1 200 ++#define HCLK_BUS_CM0_ROOT 201 ++#define FCLK_BUS_CM0_CORE 202 ++#define CLK_BUS_CM0_RTC 203 ++#define PCLK_PMU2 204 ++#define PCLK_PWM2 205 ++#define CLK_PWM2 206 ++#define CLK_RC_PWM2 207 ++#define CLK_OSC_PWM2 208 ++#define CLK_FREQ_PWM1 209 ++#define CLK_COUNTER_PWM1 210 ++#define SAI_SCLKIN_FREQ 211 ++#define SAI_SCLKIN_COUNTER 212 ++#define CLK_I3C0 213 ++#define CLK_I3C1 214 ++#define PCLK_CSIDPHY1 215 ++#define PCLK_DDR_ROOT 216 ++#define PCLK_DDR_MON_CH0 217 ++#define TMCLK_DDR_MON_CH0 218 ++#define ACLK_DDR_ROOT 219 ++#define HCLK_DDR_ROOT 220 ++#define FCLK_DDR_CM0_CORE 221 ++#define CLK_DDR_TIMER_ROOT 222 ++#define CLK_DDR_TIMER0 223 ++#define CLK_DDR_TIMER1 224 ++#define TCLK_WDT_DDR 225 ++#define PCLK_WDT 226 ++#define PCLK_TIMER 227 ++#define CLK_DDR_CM0_RTC 228 ++#define ACLK_RKNN0 229 ++#define ACLK_RKNN1 230 ++#define HCLK_RKNN_ROOT 231 ++#define CLK_RKNN_DSU0 232 ++#define PCLK_NPUTOP_ROOT 233 ++#define PCLK_NPU_TIMER 234 ++#define CLK_NPUTIMER_ROOT 235 ++#define CLK_NPUTIMER0 236 ++#define CLK_NPUTIMER1 237 ++#define PCLK_NPU_WDT 238 ++#define TCLK_NPU_WDT 239 ++#define ACLK_RKNN_CBUF 240 ++#define HCLK_NPU_CM0_ROOT 241 ++#define FCLK_NPU_CM0_CORE 242 ++#define CLK_NPU_CM0_RTC 243 ++#define HCLK_RKNN_CBUF 244 ++#define HCLK_NVM_ROOT 245 ++#define ACLK_NVM_ROOT 246 ++#define SCLK_FSPI_X2 247 ++#define HCLK_FSPI 248 ++#define CCLK_SRC_EMMC 249 ++#define HCLK_EMMC 250 ++#define ACLK_EMMC 251 ++#define BCLK_EMMC 252 ++#define TCLK_EMMC 253 ++#define PCLK_PHP_ROOT 254 ++#define ACLK_PHP_ROOT 255 ++#define PCLK_PCIE0 256 ++#define CLK_PCIE0_AUX 257 ++#define ACLK_PCIE0_MST 258 ++#define ACLK_PCIE0_SLV 259 ++#define ACLK_PCIE0_DBI 260 ++#define ACLK_USB3OTG1 261 ++#define CLK_REF_USB3OTG1 262 ++#define CLK_SUSPEND_USB3OTG1 263 ++#define ACLK_MMU0 264 ++#define ACLK_SLV_MMU0 265 ++#define ACLK_MMU1 266 ++#define ACLK_SLV_MMU1 267 ++#define PCLK_PCIE1 268 ++#define CLK_PCIE1_AUX 269 ++#define ACLK_PCIE1_MST 270 ++#define ACLK_PCIE1_SLV 271 ++#define ACLK_PCIE1_DBI 272 ++#define CLK_RXOOB0 273 ++#define CLK_RXOOB1 274 ++#define CLK_PMALIVE0 275 ++#define CLK_PMALIVE1 276 ++#define ACLK_SATA0 277 ++#define ACLK_SATA1 278 ++#define CLK_USB3OTG1_PIPE_PCLK 279 ++#define CLK_USB3OTG1_UTMI 280 ++#define CLK_USB3OTG0_PIPE_PCLK 281 ++#define CLK_USB3OTG0_UTMI 282 ++#define HCLK_SDGMAC_ROOT 283 ++#define ACLK_SDGMAC_ROOT 284 ++#define PCLK_SDGMAC_ROOT 285 ++#define ACLK_GMAC0 286 ++#define ACLK_GMAC1 287 ++#define PCLK_GMAC0 288 ++#define PCLK_GMAC1 289 ++#define CCLK_SRC_SDIO 290 ++#define HCLK_SDIO 291 ++#define CLK_GMAC1_PTP_REF 292 ++#define CLK_GMAC0_PTP_REF 293 ++#define CLK_GMAC1_PTP_REF_SRC 294 ++#define CLK_GMAC0_PTP_REF_SRC 295 ++#define CCLK_SRC_SDMMC0 296 ++#define HCLK_SDMMC0 297 ++#define SCLK_FSPI1_X2 298 ++#define HCLK_FSPI1 299 ++#define ACLK_DSMC_ROOT 300 ++#define ACLK_DSMC 301 ++#define PCLK_DSMC 302 ++#define CLK_DSMC_SYS 303 ++#define HCLK_HSGPIO 304 ++#define CLK_HSGPIO_TX 305 ++#define CLK_HSGPIO_RX 306 ++#define ACLK_HSGPIO 307 ++#define PCLK_PHPPHY_ROOT 308 ++#define PCLK_PCIE2_COMBOPHY0 309 ++#define PCLK_PCIE2_COMBOPHY1 310 ++#define CLK_PCIE_100M_SRC 311 ++#define CLK_PCIE_100M_NDUTY_SRC 312 ++#define CLK_REF_PCIE0_PHY 313 ++#define CLK_REF_PCIE1_PHY 314 ++#define CLK_REF_MPHY_26M 315 ++#define HCLK_RKVDEC_ROOT 316 ++#define ACLK_RKVDEC_ROOT 317 ++#define HCLK_RKVDEC 318 ++#define CLK_RKVDEC_HEVC_CA 319 ++#define CLK_RKVDEC_CORE 320 ++#define ACLK_UFS_ROOT 321 ++#define ACLK_USB_ROOT 322 ++#define PCLK_USB_ROOT 323 ++#define ACLK_USB3OTG0 324 ++#define CLK_REF_USB3OTG0 325 ++#define CLK_SUSPEND_USB3OTG0 326 ++#define ACLK_MMU2 327 ++#define ACLK_SLV_MMU2 328 ++#define ACLK_UFS_SYS 329 ++#define ACLK_VPU_ROOT 330 ++#define ACLK_VPU_MID_ROOT 331 ++#define HCLK_VPU_ROOT 332 ++#define ACLK_JPEG_ROOT 333 ++#define ACLK_VPU_LOW_ROOT 334 ++#define HCLK_RGA2E_0 335 ++#define ACLK_RGA2E_0 336 ++#define CLK_CORE_RGA2E_0 337 ++#define ACLK_JPEG 338 ++#define HCLK_JPEG 339 ++#define HCLK_VDPP 340 ++#define ACLK_VDPP 341 ++#define CLK_CORE_VDPP 342 ++#define HCLK_RGA2E_1 343 ++#define ACLK_RGA2E_1 344 ++#define CLK_CORE_RGA2E_1 345 ++#define DCLK_EBC_FRAC_SRC 346 ++#define HCLK_EBC 347 ++#define ACLK_EBC 348 ++#define DCLK_EBC 349 ++#define HCLK_VEPU0_ROOT 350 ++#define ACLK_VEPU0_ROOT 351 ++#define HCLK_VEPU0 352 ++#define ACLK_VEPU0 353 ++#define CLK_VEPU0_CORE 354 ++#define ACLK_VI_ROOT 355 ++#define HCLK_VI_ROOT 356 ++#define PCLK_VI_ROOT 357 ++#define DCLK_VICAP 358 ++#define ACLK_VICAP 359 ++#define HCLK_VICAP 360 ++#define CLK_ISP_CORE 361 ++#define CLK_ISP_CORE_MARVIN 362 ++#define CLK_ISP_CORE_VICAP 363 ++#define ACLK_ISP 364 ++#define HCLK_ISP 365 ++#define ACLK_VPSS 366 ++#define HCLK_VPSS 367 ++#define CLK_CORE_VPSS 368 ++#define PCLK_CSI_HOST_0 369 ++#define PCLK_CSI_HOST_1 370 ++#define PCLK_CSI_HOST_2 371 ++#define PCLK_CSI_HOST_3 372 ++#define PCLK_CSI_HOST_4 373 ++#define ICLK_CSIHOST01 374 ++#define ICLK_CSIHOST0 375 ++#define CLK_ISP_PVTPLL_SRC 376 ++#define ACLK_VI_ROOT_INTER 377 ++#define CLK_VICAP_I0CLK 378 ++#define CLK_VICAP_I1CLK 379 ++#define CLK_VICAP_I2CLK 380 ++#define CLK_VICAP_I3CLK 381 ++#define CLK_VICAP_I4CLK 382 ++#define ACLK_VOP_ROOT 383 ++#define HCLK_VOP_ROOT 384 ++#define PCLK_VOP_ROOT 385 ++#define HCLK_VOP 386 ++#define ACLK_VOP 387 ++#define DCLK_VP0_SRC 388 ++#define DCLK_VP1_SRC 389 ++#define DCLK_VP2_SRC 390 ++#define DCLK_VP0 391 ++#define DCLK_VP1 392 ++#define DCLK_VP2 393 ++#define PCLK_VOPGRF 394 ++#define ACLK_VO0_ROOT 395 ++#define HCLK_VO0_ROOT 396 ++#define PCLK_VO0_ROOT 397 ++#define PCLK_VO0_GRF 398 ++#define ACLK_HDCP0 399 ++#define HCLK_HDCP0 400 ++#define PCLK_HDCP0 401 ++#define CLK_TRNG0_SKP 402 ++#define PCLK_DSIHOST0 403 ++#define CLK_DSIHOST0 404 ++#define PCLK_HDMITX0 405 ++#define CLK_HDMITX0_EARC 406 ++#define CLK_HDMITX0_REF 407 ++#define PCLK_EDP0 408 ++#define CLK_EDP0_24M 409 ++#define CLK_EDP0_200M 410 ++#define MCLK_SAI5_8CH_SRC 411 ++#define MCLK_SAI5_8CH 412 ++#define HCLK_SAI5_8CH 413 ++#define MCLK_SAI6_8CH_SRC 414 ++#define MCLK_SAI6_8CH 415 ++#define HCLK_SAI6_8CH 416 ++#define HCLK_SPDIF_TX2 417 ++#define MCLK_SPDIF_TX2 418 ++#define HCLK_SPDIF_RX2 419 ++#define MCLK_SPDIF_RX2 420 ++#define HCLK_SAI8_8CH 421 ++#define MCLK_SAI8_8CH_SRC 422 ++#define MCLK_SAI8_8CH 423 ++#define ACLK_VO1_ROOT 424 ++#define HCLK_VO1_ROOT 425 ++#define PCLK_VO1_ROOT 426 ++#define MCLK_SAI7_8CH_SRC 427 ++#define MCLK_SAI7_8CH 428 ++#define HCLK_SAI7_8CH 429 ++#define HCLK_SPDIF_TX3 430 ++#define HCLK_SPDIF_TX4 431 ++#define HCLK_SPDIF_TX5 432 ++#define MCLK_SPDIF_TX3 433 ++#define CLK_AUX16MHZ_0 434 ++#define ACLK_DP0 435 ++#define PCLK_DP0 436 ++#define PCLK_VO1_GRF 437 ++#define ACLK_HDCP1 438 ++#define HCLK_HDCP1 439 ++#define PCLK_HDCP1 440 ++#define CLK_TRNG1_SKP 441 ++#define HCLK_SAI9_8CH 442 ++#define MCLK_SAI9_8CH_SRC 443 ++#define MCLK_SAI9_8CH 444 ++#define MCLK_SPDIF_TX4 445 ++#define MCLK_SPDIF_TX5 446 ++#define CLK_GPU_SRC_PRE 447 ++#define CLK_GPU 448 ++#define PCLK_GPU_ROOT 449 ++#define ACLK_CENTER_ROOT 450 ++#define ACLK_CENTER_LOW_ROOT 451 ++#define HCLK_CENTER_ROOT 452 ++#define PCLK_CENTER_ROOT 453 ++#define ACLK_DMA2DDR 454 ++#define ACLK_DDR_SHAREMEM 455 ++#define PCLK_DMA2DDR 456 ++#define PCLK_SHAREMEM 457 ++#define HCLK_VEPU1_ROOT 458 ++#define ACLK_VEPU1_ROOT 459 ++#define HCLK_VEPU1 460 ++#define ACLK_VEPU1 461 ++#define CLK_VEPU1_CORE 462 ++#define CLK_JDBCK_DAP 463 ++#define PCLK_MIPI_DCPHY 464 ++#define CLK_32K_USB2DEBUG 465 ++#define PCLK_CSIDPHY 466 ++#define PCLK_USBDPPHY 467 ++#define CLK_PMUPHY_REF_SRC 468 ++#define CLK_USBDP_COMBO_PHY_IMMORTAL 469 ++#define CLK_HDMITXHDP 470 ++#define PCLK_MPHY 471 ++#define CLK_REF_OSC_MPHY 472 ++#define CLK_REF_UFS_CLKOUT 473 ++#define HCLK_PMU1_ROOT 474 ++#define HCLK_PMU_CM0_ROOT 475 ++#define CLK_200M_PMU_SRC 476 ++#define CLK_100M_PMU_SRC 477 ++#define CLK_50M_PMU_SRC 478 ++#define FCLK_PMU_CM0_CORE 479 ++#define CLK_PMU_CM0_RTC 480 ++#define PCLK_PMU1 481 ++#define CLK_PMU1 482 ++#define PCLK_PMU1WDT 483 ++#define TCLK_PMU1WDT 484 ++#define PCLK_PMUTIMER 485 ++#define CLK_PMUTIMER_ROOT 486 ++#define CLK_PMUTIMER0 487 ++#define CLK_PMUTIMER1 488 ++#define PCLK_PMU1PWM 489 ++#define CLK_PMU1PWM 490 ++#define CLK_PMU1PWM_OSC 491 ++#define PCLK_PMUPHY_ROOT 492 ++#define PCLK_I2C0 493 ++#define CLK_I2C0 494 ++#define SCLK_UART1 495 ++#define PCLK_UART1 496 ++#define CLK_PMU1PWM_RC 497 ++#define CLK_PDM0 498 ++#define HCLK_PDM0 499 ++#define MCLK_PDM0 500 ++#define HCLK_VAD 501 ++#define CLK_OSCCHK_PVTM 502 ++#define CLK_PDM0_OUT 503 ++#define CLK_HPTIMER_SRC 504 ++#define PCLK_PMU0_ROOT 505 ++#define PCLK_PMU0 506 ++#define PCLK_GPIO0 507 ++#define DBCLK_GPIO0 508 ++#define CLK_OSC0_PMU1 509 ++#define PCLK_PMU1_ROOT 510 ++#define XIN_OSC0_DIV 511 ++#define ACLK_USB 512 ++#define ACLK_UFS 513 ++#define ACLK_SDGMAC 514 ++#define HCLK_SDGMAC 515 ++#define PCLK_SDGMAC 516 ++#define HCLK_VO1 517 ++#define HCLK_VO0 518 ++#define PCLK_CCI_ROOT 519 ++#define ACLK_CCI_ROOT 520 ++#define HCLK_VO0VOP_CHANNEL 521 ++#define ACLK_VO0VOP_CHANNEL 522 ++#define ACLK_TOP_MID 523 ++#define ACLK_SECURE_HIGH 524 ++#define CLK_USBPHY_REF_SRC 525 ++#define CLK_PHY_REF_SRC 526 ++#define CLK_CPLL_REF_SRC 527 ++#define CLK_AUPLL_REF_SRC 528 ++#define PCLK_SECURE_NS 529 ++#define HCLK_SECURE_NS 530 ++#define ACLK_SECURE_NS 531 ++#define PCLK_OTPC_NS 532 ++#define HCLK_CRYPTO_NS 533 ++#define HCLK_TRNG_NS 534 ++#define CLK_OTPC_NS 535 ++#define SCLK_DSU 536 ++#define SCLK_DDR 537 ++#define ACLK_CRYPTO_NS 538 ++#define CLK_PKA_CRYPTO_NS 539 ++#define ACLK_RKVDEC_ROOT_BAK 540 ++#define CLK_AUDIO_FRAC_0_SRC 541 ++#define CLK_AUDIO_FRAC_1_SRC 542 ++#define CLK_AUDIO_FRAC_2_SRC 543 ++#define CLK_AUDIO_FRAC_3_SRC 544 ++#define PCLK_HDPTX_APB 545 ++ ++/* secure clk */ ++#define CLK_STIMER0_ROOT 546 ++#define CLK_STIMER1_ROOT 547 ++#define PCLK_SECURE_S 548 ++#define HCLK_SECURE_S 549 ++#define ACLK_SECURE_S 550 ++#define CLK_PKA_CRYPTO_S 551 ++#define HCLK_VO1_S 552 ++#define PCLK_VO1_S 553 ++#define HCLK_VO0_S 554 ++#define PCLK_VO0_S 555 ++#define PCLK_KLAD 556 ++#define HCLK_CRYPTO_S 557 ++#define HCLK_KLAD 558 ++#define ACLK_CRYPTO_S 559 ++#define HCLK_TRNG_S 560 ++#define PCLK_OTPC_S 561 ++#define CLK_OTPC_S 562 ++#define PCLK_WDT_S 563 ++#define TCLK_WDT_S 564 ++#define PCLK_HDCP0_TRNG 565 ++#define PCLK_HDCP1_TRNG 566 ++#define HCLK_HDCP_KEY0 567 ++#define HCLK_HDCP_KEY1 568 ++#define PCLK_EDP_S 569 ++#define ACLK_KLAD 570 ++ ++#endif +--- /dev/null ++++ b/include/dt-bindings/reset/rockchip,rk3576-cru.h +@@ -0,0 +1,564 @@ ++/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ ++/* ++* Copyright (c) 2023 Rockchip Electronics Co. Ltd. ++* Copyright (c) 2024 Collabora Ltd. ++* ++* Author: Elaine Zhang ++* Author: Detlev Casanova ++*/ ++ ++#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H ++#define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H ++ ++#define SRST_A_TOP_BIU 0 ++#define SRST_P_TOP_BIU 1 ++#define SRST_A_TOP_MID_BIU 2 ++#define SRST_A_SECURE_HIGH_BIU 3 ++#define SRST_H_TOP_BIU 4 ++ ++#define SRST_H_VO0VOP_CHANNEL_BIU 5 ++#define SRST_A_VO0VOP_CHANNEL_BIU 6 ++ ++#define SRST_BISRINTF 7 ++ ++#define SRST_H_AUDIO_BIU 8 ++#define SRST_H_ASRC_2CH_0 9 ++#define SRST_H_ASRC_2CH_1 10 ++#define SRST_H_ASRC_4CH_0 11 ++#define SRST_H_ASRC_4CH_1 12 ++#define SRST_ASRC_2CH_0 13 ++#define SRST_ASRC_2CH_1 14 ++#define SRST_ASRC_4CH_0 15 ++#define SRST_ASRC_4CH_1 16 ++#define SRST_M_SAI0_8CH 17 ++#define SRST_H_SAI0_8CH 18 ++#define SRST_H_SPDIF_RX0 19 ++#define SRST_M_SPDIF_RX0 20 ++ ++#define SRST_H_SPDIF_RX1 21 ++#define SRST_M_SPDIF_RX1 22 ++#define SRST_M_SAI1_8CH 23 ++#define SRST_H_SAI1_8CH 24 ++#define SRST_M_SAI2_2CH 25 ++#define SRST_H_SAI2_2CH 26 ++#define SRST_M_SAI3_2CH 27 ++#define SRST_H_SAI3_2CH 28 ++ ++#define SRST_M_SAI4_2CH 29 ++#define SRST_H_SAI4_2CH 30 ++#define SRST_H_ACDCDIG_DSM 31 ++#define SRST_M_ACDCDIG_DSM 32 ++#define SRST_PDM1 33 ++#define SRST_H_PDM1 34 ++#define SRST_M_PDM1 35 ++#define SRST_H_SPDIF_TX0 36 ++#define SRST_M_SPDIF_TX0 37 ++#define SRST_H_SPDIF_TX1 38 ++#define SRST_M_SPDIF_TX1 39 ++ ++#define SRST_A_BUS_BIU 40 ++#define SRST_P_BUS_BIU 41 ++#define SRST_P_CRU 42 ++#define SRST_H_CAN0 43 ++#define SRST_CAN0 44 ++#define SRST_H_CAN1 45 ++#define SRST_CAN1 46 ++#define SRST_P_INTMUX2BUS 47 ++#define SRST_P_VCCIO_IOC 48 ++#define SRST_H_BUS_BIU 49 ++#define SRST_KEY_SHIFT 50 ++ ++#define SRST_P_I2C1 51 ++#define SRST_P_I2C2 52 ++#define SRST_P_I2C3 53 ++#define SRST_P_I2C4 54 ++#define SRST_P_I2C5 55 ++#define SRST_P_I2C6 56 ++#define SRST_P_I2C7 57 ++#define SRST_P_I2C8 58 ++#define SRST_P_I2C9 59 ++#define SRST_P_WDT_BUSMCU 60 ++#define SRST_T_WDT_BUSMCU 61 ++#define SRST_A_GIC 62 ++#define SRST_I2C1 63 ++#define SRST_I2C2 64 ++#define SRST_I2C3 65 ++#define SRST_I2C4 66 ++ ++#define SRST_I2C5 67 ++#define SRST_I2C6 68 ++#define SRST_I2C7 69 ++#define SRST_I2C8 70 ++#define SRST_I2C9 71 ++#define SRST_P_SARADC 72 ++#define SRST_SARADC 73 ++#define SRST_P_TSADC 74 ++#define SRST_TSADC 75 ++#define SRST_P_UART0 76 ++#define SRST_P_UART2 77 ++#define SRST_P_UART3 78 ++#define SRST_P_UART4 79 ++#define SRST_P_UART5 80 ++#define SRST_P_UART6 81 ++ ++#define SRST_P_UART7 82 ++#define SRST_P_UART8 83 ++#define SRST_P_UART9 84 ++#define SRST_P_UART10 85 ++#define SRST_P_UART11 86 ++#define SRST_S_UART0 87 ++#define SRST_S_UART2 88 ++#define SRST_S_UART3 89 ++#define SRST_S_UART4 90 ++#define SRST_S_UART5 91 ++ ++#define SRST_S_UART6 92 ++#define SRST_S_UART7 93 ++#define SRST_S_UART8 94 ++#define SRST_S_UART9 95 ++#define SRST_S_UART10 96 ++#define SRST_S_UART11 97 ++#define SRST_P_SPI0 98 ++#define SRST_P_SPI1 99 ++#define SRST_P_SPI2 100 ++ ++#define SRST_P_SPI3 101 ++#define SRST_P_SPI4 102 ++#define SRST_SPI0 103 ++#define SRST_SPI1 104 ++#define SRST_SPI2 105 ++#define SRST_SPI3 106 ++#define SRST_SPI4 107 ++#define SRST_P_WDT0 108 ++#define SRST_T_WDT0 109 ++#define SRST_P_SYS_GRF 110 ++#define SRST_P_PWM1 111 ++#define SRST_PWM1 112 ++ ++#define SRST_P_BUSTIMER0 113 ++#define SRST_P_BUSTIMER1 114 ++#define SRST_TIMER0 115 ++#define SRST_TIMER1 116 ++#define SRST_TIMER2 117 ++#define SRST_TIMER3 118 ++#define SRST_TIMER4 119 ++#define SRST_TIMER5 120 ++#define SRST_P_BUSIOC 121 ++#define SRST_P_MAILBOX0 122 ++#define SRST_P_GPIO1 123 ++ ++#define SRST_GPIO1 124 ++#define SRST_P_GPIO2 125 ++#define SRST_GPIO2 126 ++#define SRST_P_GPIO3 127 ++#define SRST_GPIO3 128 ++#define SRST_P_GPIO4 129 ++#define SRST_GPIO4 130 ++#define SRST_A_DECOM 131 ++#define SRST_P_DECOM 132 ++#define SRST_D_DECOM 133 ++#define SRST_TIMER6 134 ++#define SRST_TIMER7 135 ++#define SRST_TIMER8 136 ++#define SRST_TIMER9 137 ++#define SRST_TIMER10 138 ++ ++#define SRST_TIMER11 139 ++#define SRST_A_DMAC0 140 ++#define SRST_A_DMAC1 141 ++#define SRST_A_DMAC2 142 ++#define SRST_A_SPINLOCK 143 ++#define SRST_REF_PVTPLL_BUS 144 ++#define SRST_H_I3C0 145 ++#define SRST_H_I3C1 146 ++#define SRST_H_BUS_CM0_BIU 147 ++#define SRST_F_BUS_CM0_CORE 148 ++#define SRST_T_BUS_CM0_JTAG 149 ++ ++#define SRST_P_INTMUX2PMU 150 ++#define SRST_P_INTMUX2DDR 151 ++#define SRST_P_PVTPLL_BUS 152 ++#define SRST_P_PWM2 153 ++#define SRST_PWM2 154 ++#define SRST_FREQ_PWM1 155 ++#define SRST_COUNTER_PWM1 156 ++#define SRST_I3C0 157 ++#define SRST_I3C1 158 ++ ++#define SRST_P_DDR_MON_CH0 159 ++#define SRST_P_DDR_BIU 160 ++#define SRST_P_DDR_UPCTL_CH0 161 ++#define SRST_TM_DDR_MON_CH0 162 ++#define SRST_A_DDR_BIU 163 ++#define SRST_DFI_CH0 164 ++#define SRST_DDR_MON_CH0 165 ++#define SRST_P_DDR_HWLP_CH0 166 ++#define SRST_P_DDR_MON_CH1 167 ++#define SRST_P_DDR_HWLP_CH1 168 ++ ++#define SRST_P_DDR_UPCTL_CH1 169 ++#define SRST_TM_DDR_MON_CH1 170 ++#define SRST_DFI_CH1 171 ++#define SRST_A_DDR01_MSCH0 172 ++#define SRST_A_DDR01_MSCH1 173 ++#define SRST_DDR_MON_CH1 174 ++#define SRST_DDR_SCRAMBLE_CH0 175 ++#define SRST_DDR_SCRAMBLE_CH1 176 ++#define SRST_P_AHB2APB 177 ++#define SRST_H_AHB2APB 178 ++#define SRST_H_DDR_BIU 179 ++#define SRST_F_DDR_CM0_CORE 180 ++ ++#define SRST_P_DDR01_MSCH0 181 ++#define SRST_P_DDR01_MSCH1 182 ++#define SRST_DDR_TIMER0 183 ++#define SRST_DDR_TIMER1 184 ++#define SRST_T_WDT_DDR 185 ++#define SRST_P_WDT 186 ++#define SRST_P_TIMER 187 ++#define SRST_T_DDR_CM0_JTAG 188 ++#define SRST_P_DDR_GRF 189 ++ ++#define SRST_DDR_UPCTL_CH0 190 ++#define SRST_A_DDR_UPCTL_0_CH0 191 ++#define SRST_A_DDR_UPCTL_1_CH0 192 ++#define SRST_A_DDR_UPCTL_2_CH0 193 ++#define SRST_A_DDR_UPCTL_3_CH0 194 ++#define SRST_A_DDR_UPCTL_4_CH0 195 ++ ++#define SRST_DDR_UPCTL_CH1 196 ++#define SRST_A_DDR_UPCTL_0_CH1 197 ++#define SRST_A_DDR_UPCTL_1_CH1 198 ++#define SRST_A_DDR_UPCTL_2_CH1 199 ++#define SRST_A_DDR_UPCTL_3_CH1 200 ++#define SRST_A_DDR_UPCTL_4_CH1 201 ++ ++#define SRST_REF_PVTPLL_DDR 202 ++#define SRST_P_PVTPLL_DDR 203 ++ ++#define SRST_A_RKNN0 204 ++#define SRST_A_RKNN0_BIU 205 ++#define SRST_L_RKNN0_BIU 206 ++ ++#define SRST_A_RKNN1 207 ++#define SRST_A_RKNN1_BIU 208 ++#define SRST_L_RKNN1_BIU 209 ++ ++#define SRST_NPU_DAP 210 ++#define SRST_L_NPUSUBSYS_BIU 211 ++#define SRST_P_NPUTOP_BIU 212 ++#define SRST_P_NPU_TIMER 213 ++#define SRST_NPUTIMER0 214 ++#define SRST_NPUTIMER1 215 ++#define SRST_P_NPU_WDT 216 ++#define SRST_T_NPU_WDT 217 ++ ++#define SRST_A_RKNN_CBUF 218 ++#define SRST_A_RVCORE0 219 ++#define SRST_P_NPU_GRF 220 ++#define SRST_P_PVTPLL_NPU 221 ++#define SRST_NPU_PVTPLL 222 ++#define SRST_H_NPU_CM0_BIU 223 ++#define SRST_F_NPU_CM0_CORE 224 ++#define SRST_T_NPU_CM0_JTAG 225 ++#define SRST_A_RKNNTOP_BIU 226 ++#define SRST_H_RKNN_CBUF 227 ++#define SRST_H_RKNNTOP_BIU 228 ++ ++#define SRST_H_NVM_BIU 229 ++#define SRST_A_NVM_BIU 230 ++#define SRST_S_FSPI 231 ++#define SRST_H_FSPI 232 ++#define SRST_C_EMMC 233 ++#define SRST_H_EMMC 234 ++#define SRST_A_EMMC 235 ++#define SRST_B_EMMC 236 ++#define SRST_T_EMMC 237 ++ ++#define SRST_P_GRF 238 ++#define SRST_P_PHP_BIU 239 ++#define SRST_A_PHP_BIU 240 ++#define SRST_P_PCIE0 241 ++#define SRST_PCIE0_POWER_UP 242 ++ ++#define SRST_A_USB3OTG1 243 ++#define SRST_A_MMU0 244 ++#define SRST_A_SLV_MMU0 245 ++#define SRST_A_MMU1 246 ++ ++#define SRST_A_SLV_MMU1 247 ++#define SRST_P_PCIE1 248 ++#define SRST_PCIE1_POWER_UP 249 ++ ++#define SRST_RXOOB0 250 ++#define SRST_RXOOB1 251 ++#define SRST_PMALIVE0 252 ++#define SRST_PMALIVE1 253 ++#define SRST_A_SATA0 254 ++#define SRST_A_SATA1 255 ++#define SRST_ASIC1 256 ++#define SRST_ASIC0 257 ++ ++#define SRST_P_CSIDPHY1 258 ++#define SRST_SCAN_CSIDPHY1 259 ++ ++#define SRST_P_SDGMAC_GRF 260 ++#define SRST_P_SDGMAC_BIU 261 ++#define SRST_A_SDGMAC_BIU 262 ++#define SRST_H_SDGMAC_BIU 263 ++#define SRST_A_GMAC0 264 ++#define SRST_A_GMAC1 265 ++#define SRST_P_GMAC0 266 ++#define SRST_P_GMAC1 267 ++#define SRST_H_SDIO 268 ++ ++#define SRST_H_SDMMC0 269 ++#define SRST_S_FSPI1 270 ++#define SRST_H_FSPI1 271 ++#define SRST_A_DSMC_BIU 272 ++#define SRST_A_DSMC 273 ++#define SRST_P_DSMC 274 ++#define SRST_H_HSGPIO 275 ++#define SRST_HSGPIO 276 ++#define SRST_A_HSGPIO 277 ++ ++#define SRST_H_RKVDEC 278 ++#define SRST_H_RKVDEC_BIU 279 ++#define SRST_A_RKVDEC_BIU 280 ++#define SRST_RKVDEC_HEVC_CA 281 ++#define SRST_RKVDEC_CORE 282 ++ ++#define SRST_A_USB_BIU 283 ++#define SRST_P_USBUFS_BIU 284 ++#define SRST_A_USB3OTG0 285 ++#define SRST_A_UFS_BIU 286 ++#define SRST_A_MMU2 287 ++#define SRST_A_SLV_MMU2 288 ++#define SRST_A_UFS_SYS 289 ++ ++#define SRST_A_UFS 290 ++#define SRST_P_USBUFS_GRF 291 ++#define SRST_P_UFS_GRF 292 ++ ++#define SRST_H_VPU_BIU 293 ++#define SRST_A_JPEG_BIU 294 ++#define SRST_A_RGA_BIU 295 ++#define SRST_A_VDPP_BIU 296 ++#define SRST_A_EBC_BIU 297 ++#define SRST_H_RGA2E_0 298 ++#define SRST_A_RGA2E_0 299 ++#define SRST_CORE_RGA2E_0 300 ++ ++#define SRST_A_JPEG 301 ++#define SRST_H_JPEG 302 ++#define SRST_H_VDPP 303 ++#define SRST_A_VDPP 304 ++#define SRST_CORE_VDPP 305 ++#define SRST_H_RGA2E_1 306 ++#define SRST_A_RGA2E_1 307 ++#define SRST_CORE_RGA2E_1 308 ++#define SRST_H_EBC 309 ++#define SRST_A_EBC 310 ++#define SRST_D_EBC 311 ++ ++#define SRST_H_VEPU0_BIU 312 ++#define SRST_A_VEPU0_BIU 313 ++#define SRST_H_VEPU0 314 ++#define SRST_A_VEPU0 315 ++#define SRST_VEPU0_CORE 316 ++ ++#define SRST_A_VI_BIU 317 ++#define SRST_H_VI_BIU 318 ++#define SRST_P_VI_BIU 319 ++#define SRST_D_VICAP 320 ++#define SRST_A_VICAP 321 ++#define SRST_H_VICAP 322 ++#define SRST_ISP0 323 ++#define SRST_ISP0_VICAP 324 ++ ++#define SRST_CORE_VPSS 325 ++#define SRST_P_CSI_HOST_0 326 ++#define SRST_P_CSI_HOST_1 327 ++#define SRST_P_CSI_HOST_2 328 ++#define SRST_P_CSI_HOST_3 329 ++#define SRST_P_CSI_HOST_4 330 ++ ++#define SRST_CIFIN 331 ++#define SRST_VICAP_I0CLK 332 ++#define SRST_VICAP_I1CLK 333 ++#define SRST_VICAP_I2CLK 334 ++#define SRST_VICAP_I3CLK 335 ++#define SRST_VICAP_I4CLK 336 ++ ++#define SRST_A_VOP_BIU 337 ++#define SRST_A_VOP2_BIU 338 ++#define SRST_H_VOP_BIU 339 ++#define SRST_P_VOP_BIU 340 ++#define SRST_H_VOP 341 ++#define SRST_A_VOP 342 ++#define SRST_D_VP0 343 ++ ++#define SRST_D_VP1 344 ++#define SRST_D_VP2 345 ++#define SRST_P_VOP2_BIU 346 ++#define SRST_P_VOPGRF 347 ++ ++#define SRST_H_VO0_BIU 348 ++#define SRST_P_VO0_BIU 349 ++#define SRST_A_HDCP0_BIU 350 ++#define SRST_P_VO0_GRF 351 ++#define SRST_A_HDCP0 352 ++#define SRST_H_HDCP0 353 ++#define SRST_HDCP0 354 ++ ++#define SRST_P_DSIHOST0 355 ++#define SRST_DSIHOST0 356 ++#define SRST_P_HDMITX0 357 ++#define SRST_HDMITX0_REF 358 ++#define SRST_P_EDP0 359 ++#define SRST_EDP0_24M 360 ++ ++#define SRST_M_SAI5_8CH 361 ++#define SRST_H_SAI5_8CH 362 ++#define SRST_M_SAI6_8CH 363 ++#define SRST_H_SAI6_8CH 364 ++#define SRST_H_SPDIF_TX2 365 ++#define SRST_M_SPDIF_TX2 366 ++#define SRST_H_SPDIF_RX2 367 ++#define SRST_M_SPDIF_RX2 368 ++ ++#define SRST_H_SAI8_8CH 369 ++#define SRST_M_SAI8_8CH 370 ++ ++#define SRST_H_VO1_BIU 371 ++#define SRST_P_VO1_BIU 372 ++#define SRST_M_SAI7_8CH 373 ++#define SRST_H_SAI7_8CH 374 ++#define SRST_H_SPDIF_TX3 375 ++#define SRST_H_SPDIF_TX4 376 ++#define SRST_H_SPDIF_TX5 377 ++#define SRST_M_SPDIF_TX3 378 ++ ++#define SRST_DP0 379 ++#define SRST_P_VO1_GRF 380 ++#define SRST_A_HDCP1_BIU 381 ++#define SRST_A_HDCP1 382 ++#define SRST_H_HDCP1 383 ++#define SRST_HDCP1 384 ++#define SRST_H_SAI9_8CH 385 ++#define SRST_M_SAI9_8CH 386 ++#define SRST_M_SPDIF_TX4 387 ++#define SRST_M_SPDIF_TX5 388 ++ ++#define SRST_GPU 389 ++#define SRST_A_S_GPU_BIU 390 ++#define SRST_A_M0_GPU_BIU 391 ++#define SRST_P_GPU_BIU 392 ++#define SRST_P_GPU_GRF 393 ++#define SRST_GPU_PVTPLL 394 ++#define SRST_P_PVTPLL_GPU 395 ++ ++#define SRST_A_CENTER_BIU 396 ++#define SRST_A_DMA2DDR 397 ++#define SRST_A_DDR_SHAREMEM 398 ++#define SRST_A_DDR_SHAREMEM_BIU 399 ++#define SRST_H_CENTER_BIU 400 ++#define SRST_P_CENTER_GRF 401 ++#define SRST_P_DMA2DDR 402 ++#define SRST_P_SHAREMEM 403 ++#define SRST_P_CENTER_BIU 404 ++ ++#define SRST_LINKSYM_HDMITXPHY0 405 ++ ++#define SRST_DP0_PIXELCLK 406 ++#define SRST_PHY_DP0_TX 407 ++#define SRST_DP1_PIXELCLK 408 ++#define SRST_DP2_PIXELCLK 409 ++ ++#define SRST_H_VEPU1_BIU 410 ++#define SRST_A_VEPU1_BIU 411 ++#define SRST_H_VEPU1 412 ++#define SRST_A_VEPU1 413 ++#define SRST_VEPU1_CORE 414 ++ ++#define SRST_P_PHPPHY_CRU 415 ++#define SRST_P_APB2ASB_SLV_CHIP_TOP 416 ++#define SRST_P_PCIE2_COMBOPHY0 417 ++#define SRST_P_PCIE2_COMBOPHY0_GRF 418 ++#define SRST_P_PCIE2_COMBOPHY1 419 ++#define SRST_P_PCIE2_COMBOPHY1_GRF 420 ++ ++#define SRST_PCIE0_PIPE_PHY 421 ++#define SRST_PCIE1_PIPE_PHY 422 ++ ++#define SRST_H_CRYPTO_NS 423 ++#define SRST_H_TRNG_NS 424 ++#define SRST_P_OTPC_NS 425 ++#define SRST_OTPC_NS 426 ++ ++#define SRST_P_HDPTX_GRF 427 ++#define SRST_P_HDPTX_APB 428 ++#define SRST_P_MIPI_DCPHY 429 ++#define SRST_P_DCPHY_GRF 430 ++#define SRST_P_BOT0_APB2ASB 431 ++#define SRST_P_BOT1_APB2ASB 432 ++#define SRST_USB2DEBUG 433 ++#define SRST_P_CSIPHY_GRF 434 ++#define SRST_P_CSIPHY 435 ++#define SRST_P_USBPHY_GRF_0 436 ++#define SRST_P_USBPHY_GRF_1 437 ++#define SRST_P_USBDP_GRF 438 ++#define SRST_P_USBDPPHY 439 ++#define SRST_USBDP_COMBO_PHY_INIT 440 ++ ++#define SRST_USBDP_COMBO_PHY_CMN 441 ++#define SRST_USBDP_COMBO_PHY_LANE 442 ++#define SRST_USBDP_COMBO_PHY_PCS 443 ++#define SRST_M_MIPI_DCPHY 444 ++#define SRST_S_MIPI_DCPHY 445 ++#define SRST_SCAN_CSIPHY 446 ++#define SRST_P_VCCIO6_IOC 447 ++#define SRST_OTGPHY_0 448 ++#define SRST_OTGPHY_1 449 ++#define SRST_HDPTX_INIT 450 ++#define SRST_HDPTX_CMN 451 ++#define SRST_HDPTX_LANE 452 ++#define SRST_HDMITXHDP 453 ++ ++#define SRST_MPHY_INIT 454 ++#define SRST_P_MPHY_GRF 455 ++#define SRST_P_VCCIO7_IOC 456 ++ ++#define SRST_H_PMU1_BIU 457 ++#define SRST_P_PMU1_NIU 458 ++#define SRST_H_PMU_CM0_BIU 459 ++#define SRST_PMU_CM0_CORE 460 ++#define SRST_PMU_CM0_JTAG 461 ++ ++#define SRST_P_CRU_PMU1 462 ++#define SRST_P_PMU1_GRF 463 ++#define SRST_P_PMU1_IOC 464 ++#define SRST_P_PMU1WDT 465 ++#define SRST_T_PMU1WDT 466 ++#define SRST_P_PMUTIMER 467 ++#define SRST_PMUTIMER0 468 ++#define SRST_PMUTIMER1 469 ++#define SRST_P_PMU1PWM 470 ++#define SRST_PMU1PWM 471 ++ ++#define SRST_P_I2C0 472 ++#define SRST_I2C0 473 ++#define SRST_S_UART1 474 ++#define SRST_P_UART1 475 ++#define SRST_PDM0 476 ++#define SRST_H_PDM0 477 ++ ++#define SRST_M_PDM0 478 ++#define SRST_H_VAD 479 ++ ++#define SRST_P_PMU0GRF 480 ++#define SRST_P_PMU0IOC 481 ++#define SRST_P_GPIO0 482 ++#define SRST_DB_GPIO0 483 ++ ++#endif diff --git a/target/linux/rockchip/patches-6.6/030-12-v6.12-clk-rockchip-Add-new-pll-type-pll_rk3588_ddr.patch b/target/linux/rockchip/patches-6.6/030-12-v6.12-clk-rockchip-Add-new-pll-type-pll_rk3588_ddr.patch new file mode 100644 index 000000000..0d68f687f --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-12-v6.12-clk-rockchip-Add-new-pll-type-pll_rk3588_ddr.patch @@ -0,0 +1,51 @@ +From e781bffc296766b55dbd048890d558655031e8d1 Mon Sep 17 00:00:00 2001 +From: Elaine Zhang +Date: Wed, 28 Aug 2024 15:42:52 +0000 +Subject: [PATCH] clk: rockchip: Add new pll type pll_rk3588_ddr + +That PLL type is similar to the other rk3588 pll types but the actual +rate is twice the configured rate. +Therefore, the returned calculated rate must be multiplied by two. + +Signed-off-by: Elaine Zhang +Signed-off-by: Detlev Casanova +Acked-by: Dragan Simic +Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-pll.c | 6 +++++- + drivers/clk/rockchip/clk.h | 1 + + 2 files changed, 6 insertions(+), 1 deletion(-) + +--- a/drivers/clk/rockchip/clk-pll.c ++++ b/drivers/clk/rockchip/clk-pll.c +@@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll + } + rate64 = rate64 >> cur.s; + +- return (unsigned long)rate64; ++ if (pll->type == pll_rk3588_ddr) ++ return (unsigned long)rate64 * 2; ++ else ++ return (unsigned long)rate64; + } + + static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, +@@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(st + break; + case pll_rk3588: + case pll_rk3588_core: ++ case pll_rk3588_ddr: + if (!pll->rate_table) + init.ops = &rockchip_rk3588_pll_clk_norate_ops; + else +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -287,6 +287,7 @@ enum rockchip_pll_type { + pll_rk3399, + pll_rk3588, + pll_rk3588_core, ++ pll_rk3588_ddr, + }; + + #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ diff --git a/target/linux/rockchip/patches-6.6/030-13-v6.12-clk-rockchip-Add-clock-controller-for-the-RK3576.patch b/target/linux/rockchip/patches-6.6/030-13-v6.12-clk-rockchip-Add-clock-controller-for-the-RK3576.patch new file mode 100644 index 000000000..90b7e8bf5 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-13-v6.12-clk-rockchip-Add-clock-controller-for-the-RK3576.patch @@ -0,0 +1,2605 @@ +From cc40f5baa91bb7b031f5622e11a4e443cb771527 Mon Sep 17 00:00:00 2001 +From: Elaine Zhang +Date: Wed, 28 Aug 2024 15:42:55 +0000 +Subject: [PATCH] clk: rockchip: Add clock controller for the RK3576 + +Add the clock and reset tree definitions for the new RK3576 +SoC. + +As opposed to the other rockchip CRU drivers, the GRF node is looked up +via compatible instead of a phandle, which simplifies the device tree +bindings. + +Signed-off-by: Elaine Zhang +Signed-off-by: Finley Xiao +Signed-off-by: YouMin Chen +Signed-off-by: Liang Chen +Signed-off-by: Sugar Zhang +Signed-off-by: Detlev Casanova +Reviewed-by: Elaine Zhang +Tested-by: Shawn Lin +Acked-by: Dragan Simic +Link: https://lore.kernel.org/r/0102019199a7781a-888440f0-a3f7-4a7d-a831-491260cbdfe7-000000@eu-west-1.amazonses.com +[dropped additional blank line at EOF in rst-rk3576.c + dropped the whole (non-)working as module part] +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/Kconfig | 7 + + drivers/clk/rockchip/Makefile | 1 + + drivers/clk/rockchip/clk-rk3576.c | 1820 +++++++++++++++++++++++++++++ + drivers/clk/rockchip/clk.h | 53 + + drivers/clk/rockchip/rst-rk3576.c | 651 +++++++++++ + 5 files changed, 2532 insertions(+) + create mode 100644 drivers/clk/rockchip/clk-rk3576.c + create mode 100644 drivers/clk/rockchip/rst-rk3576.c + +--- a/drivers/clk/rockchip/Kconfig ++++ b/drivers/clk/rockchip/Kconfig +@@ -100,6 +100,13 @@ config CLK_RK3568 + help + Build the driver for RK3568 Clock Driver. + ++config CLK_RK3576 ++ bool "Rockchip RK3576 clock controller support" ++ depends on ARM64 || COMPILE_TEST ++ default y ++ help ++ Build the driver for RK3576 Clock Driver. ++ + config CLK_RK3588 + bool "Rockchip RK3588 clock controller support" + depends on ARM64 || COMPILE_TEST +--- a/drivers/clk/rockchip/Makefile ++++ b/drivers/clk/rockchip/Makefile +@@ -28,4 +28,5 @@ obj-$(CONFIG_CLK_RK3328) += clk-r + obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o + obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o + obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o ++obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o + obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o +--- /dev/null ++++ b/drivers/clk/rockchip/clk-rk3576.c +@@ -0,0 +1,1820 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 Rockchip Electronics Co. Ltd. ++ * Author: Elaine Zhang ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "clk.h" ++ ++#define RK3576_GRF_SOC_STATUS0 0x600 ++#define RK3576_PMU0_GRF_OSC_CON6 0x18 ++ ++enum rk3576_plls { ++ bpll, lpll, vpll, aupll, cpll, gpll, ppll, ++}; ++ ++static struct rockchip_pll_rate_table rk3576_pll_rates[] = { ++ /* _mhz, _p, _m, _s, _k */ ++ RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), ++ RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), ++ RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), ++ RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), ++ RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), ++ RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), ++ RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), ++ RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), ++ RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), ++ RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), ++ RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), ++ RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), ++ RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), ++ RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), ++ RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), ++ RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), ++ RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), ++ RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), ++ RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), ++ RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), ++ RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), ++ RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), ++ RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), ++ RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), ++ RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), ++ RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), ++ RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), ++ RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), ++ RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), ++ RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), ++ RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), ++ RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), ++ RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), ++ RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), ++ RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), ++ RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), ++ RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), ++ RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), ++ RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), ++ RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), ++ RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), ++ RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), ++ RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), ++ RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), ++ RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), ++ RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), ++ RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), ++ RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), ++ RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), ++ RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), ++ RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), ++ RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), ++ RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), ++ RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), ++ RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), ++ RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), ++ RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), ++ RK3588_PLL_RATE(900000000, 2, 300, 2, 0), ++ RK3588_PLL_RATE(816000000, 2, 272, 2, 0), ++ RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), ++ RK3588_PLL_RATE(786000000, 1, 131, 2, 0), ++ RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), ++ RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), ++ RK3588_PLL_RATE(600000000, 2, 200, 2, 0), ++ RK3588_PLL_RATE(594000000, 2, 198, 2, 0), ++ RK3588_PLL_RATE(408000000, 2, 272, 3, 0), ++ RK3588_PLL_RATE(312000000, 2, 208, 3, 0), ++ RK3588_PLL_RATE(216000000, 2, 288, 4, 0), ++ RK3588_PLL_RATE(96000000, 2, 256, 5, 0), ++ { /* sentinel */ }, ++}; ++ ++static struct rockchip_pll_rate_table rk3576_ppll_rates[] = { ++ /* _mhz, _p, _m, _s, _k */ ++ RK3588_PLL_RATE(1300000000, 3, 325, 2, 0), ++ { /* sentinel */ }, ++}; ++ ++#define RK3576_ACLK_M_BIGCORE_DIV_MASK 0x1f ++#define RK3576_ACLK_M_BIGCORE_DIV_SHIFT 0 ++#define RK3576_ACLK_M_LITCORE_DIV_MASK 0x1f ++#define RK3576_ACLK_M_LITCORE_DIV_SHIFT 8 ++#define RK3576_PCLK_DBG_LITCORE_DIV_MASK 0x1f ++#define RK3576_PCLK_DBG_LITCORE_DIV_SHIFT 0 ++#define RK3576_ACLK_CCI_DIV_MASK 0x1f ++#define RK3576_ACLK_CCI_DIV_SHIFT 7 ++#define RK3576_ACLK_CCI_MUX_MASK 0x3 ++#define RK3576_ACLK_CCI_MUX_SHIFT 12 ++ ++#define RK3576_BIGCORE_CLKSEL2(_amcore) \ ++{ \ ++ .reg = RK3576_BIGCORE_CLKSEL_CON(2), \ ++ .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_BIGCORE_DIV_MASK, \ ++ RK3576_ACLK_M_BIGCORE_DIV_SHIFT), \ ++} ++ ++#define RK3576_LITCORE_CLKSEL1(_amcore) \ ++{ \ ++ .reg = RK3576_LITCORE_CLKSEL_CON(1), \ ++ .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_LITCORE_DIV_MASK, \ ++ RK3576_ACLK_M_LITCORE_DIV_SHIFT), \ ++} ++ ++#define RK3576_LITCORE_CLKSEL2(_pclkdbg) \ ++{ \ ++ .reg = RK3576_LITCORE_CLKSEL_CON(2), \ ++ .val = HIWORD_UPDATE(_pclkdbg - 1, RK3576_PCLK_DBG_LITCORE_DIV_MASK, \ ++ RK3576_PCLK_DBG_LITCORE_DIV_SHIFT), \ ++} ++ ++#define RK3576_CCI_CLKSEL4(_ccisel, _div) \ ++{ \ ++ .reg = RK3576_CCI_CLKSEL_CON(4), \ ++ .val = HIWORD_UPDATE(_ccisel, RK3576_ACLK_CCI_MUX_MASK, \ ++ RK3576_ACLK_CCI_MUX_SHIFT) | \ ++ HIWORD_UPDATE(_div - 1, RK3576_ACLK_CCI_DIV_MASK, \ ++ RK3576_ACLK_CCI_DIV_SHIFT), \ ++} ++ ++#define RK3576_CPUBCLK_RATE(_prate, _amcore) \ ++{ \ ++ .prate = _prate##U, \ ++ .divs = { \ ++ RK3576_BIGCORE_CLKSEL2(_amcore), \ ++ }, \ ++} ++ ++#define RK3576_CPULCLK_RATE(_prate, _amcore, _pclkdbg, _ccisel) \ ++{ \ ++ .prate = _prate##U, \ ++ .divs = { \ ++ RK3576_LITCORE_CLKSEL1(_amcore), \ ++ RK3576_LITCORE_CLKSEL2(_pclkdbg), \ ++ }, \ ++ .pre_muxs = { \ ++ RK3576_CCI_CLKSEL4(2, 2), \ ++ }, \ ++ .post_muxs = { \ ++ RK3576_CCI_CLKSEL4(_ccisel, 2), \ ++ }, \ ++} ++ ++static struct rockchip_cpuclk_rate_table rk3576_cpubclk_rates[] __initdata = { ++ RK3576_CPUBCLK_RATE(2496000000, 2), ++ RK3576_CPUBCLK_RATE(2400000000, 2), ++ RK3576_CPUBCLK_RATE(2304000000, 2), ++ RK3576_CPUBCLK_RATE(2208000000, 2), ++ RK3576_CPUBCLK_RATE(2184000000, 2), ++ RK3576_CPUBCLK_RATE(2088000000, 2), ++ RK3576_CPUBCLK_RATE(2040000000, 2), ++ RK3576_CPUBCLK_RATE(2016000000, 2), ++ RK3576_CPUBCLK_RATE(1992000000, 2), ++ RK3576_CPUBCLK_RATE(1896000000, 2), ++ RK3576_CPUBCLK_RATE(1800000000, 2), ++ RK3576_CPUBCLK_RATE(1704000000, 2), ++ RK3576_CPUBCLK_RATE(1608000000, 2), ++ RK3576_CPUBCLK_RATE(1584000000, 2), ++ RK3576_CPUBCLK_RATE(1560000000, 2), ++ RK3576_CPUBCLK_RATE(1536000000, 2), ++ RK3576_CPUBCLK_RATE(1512000000, 2), ++ RK3576_CPUBCLK_RATE(1488000000, 2), ++ RK3576_CPUBCLK_RATE(1464000000, 2), ++ RK3576_CPUBCLK_RATE(1440000000, 2), ++ RK3576_CPUBCLK_RATE(1416000000, 2), ++ RK3576_CPUBCLK_RATE(1392000000, 2), ++ RK3576_CPUBCLK_RATE(1368000000, 2), ++ RK3576_CPUBCLK_RATE(1344000000, 2), ++ RK3576_CPUBCLK_RATE(1320000000, 2), ++ RK3576_CPUBCLK_RATE(1296000000, 2), ++ RK3576_CPUBCLK_RATE(1272000000, 2), ++ RK3576_CPUBCLK_RATE(1248000000, 2), ++ RK3576_CPUBCLK_RATE(1224000000, 2), ++ RK3576_CPUBCLK_RATE(1200000000, 2), ++ RK3576_CPUBCLK_RATE(1104000000, 2), ++ RK3576_CPUBCLK_RATE(1008000000, 2), ++ RK3576_CPUBCLK_RATE(912000000, 2), ++ RK3576_CPUBCLK_RATE(816000000, 2), ++ RK3576_CPUBCLK_RATE(696000000, 2), ++ RK3576_CPUBCLK_RATE(600000000, 2), ++ RK3576_CPUBCLK_RATE(408000000, 2), ++ RK3576_CPUBCLK_RATE(312000000, 2), ++ RK3576_CPUBCLK_RATE(216000000, 2), ++ RK3576_CPUBCLK_RATE(96000000, 2), ++}; ++ ++static const struct rockchip_cpuclk_reg_data rk3576_cpubclk_data = { ++ .core_reg[0] = RK3576_BIGCORE_CLKSEL_CON(1), ++ .div_core_shift[0] = 7, ++ .div_core_mask[0] = 0x1f, ++ .num_cores = 1, ++ .mux_core_alt = 1, ++ .mux_core_main = 0, ++ .mux_core_shift = 12, ++ .mux_core_mask = 0x3, ++}; ++ ++static struct rockchip_cpuclk_rate_table rk3576_cpulclk_rates[] __initdata = { ++ RK3576_CPULCLK_RATE(2400000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(2304000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(2208000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(2184000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(2088000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(2040000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(2016000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1992000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1896000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1800000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1704000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1608000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1584000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1560000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1536000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1512000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1488000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1464000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1440000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1416000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1392000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1368000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1344000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1320000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1296000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1272000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1248000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1224000000, 2, 6, 3), ++ RK3576_CPULCLK_RATE(1200000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(1104000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(1008000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(912000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(816000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(696000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(600000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(408000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(312000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(216000000, 2, 6, 2), ++ RK3576_CPULCLK_RATE(96000000, 2, 6, 2), ++}; ++ ++static const struct rockchip_cpuclk_reg_data rk3576_cpulclk_data = { ++ .core_reg[0] = RK3576_LITCORE_CLKSEL_CON(0), ++ .div_core_shift[0] = 7, ++ .div_core_mask[0] = 0x1f, ++ .num_cores = 1, ++ .mux_core_alt = 1, ++ .mux_core_main = 0, ++ .mux_core_shift = 12, ++ .mux_core_mask = 0x3, ++}; ++ ++#define MFLAGS CLK_MUX_HIWORD_MASK ++#define DFLAGS CLK_DIVIDER_HIWORD_MASK ++#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) ++ ++PNAME(mux_pll_p) = { "xin24m", "xin32k" }; ++PNAME(mux_24m_32k_p) = { "xin24m", "xin_osc0_div" }; ++PNAME(mux_armclkl_p) = { "xin24m", "pll_lpll", "lpll" }; ++PNAME(mux_armclkb_p) = { "xin24m", "pll_bpll", "bpll" }; ++PNAME(gpll_24m_p) = { "gpll", "xin24m" }; ++PNAME(cpll_24m_p) = { "cpll", "xin24m" }; ++PNAME(gpll_cpll_p) = { "gpll", "cpll" }; ++PNAME(gpll_spll_p) = { "gpll", "spll" }; ++PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll" }; ++PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" }; ++PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; ++PNAME(gpll_cpll_aupll_24m_p) = { "gpll", "cpll", "aupll", "xin24m" }; ++PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; ++PNAME(gpll_cpll_aupll_spll_lpll_p) = { "gpll", "cpll", "aupll", "spll", "lpll_dummy" }; ++PNAME(gpll_cpll_spll_bpll_p) = { "gpll", "cpll", "spll", "bpll_dummy" }; ++PNAME(gpll_cpll_lpll_bpll_p) = { "gpll", "cpll", "lpll_dummy", "bpll_dummy" }; ++PNAME(gpll_spll_cpll_bpll_lpll_p) = { "gpll", "spll", "cpll", "bpll_dummy", "lpll_dummy" }; ++PNAME(gpll_cpll_vpll_aupll_24m_p) = { "gpll", "cpll", "vpll", "aupll", "xin24m" }; ++PNAME(gpll_cpll_spll_aupll_bpll_p) = { "gpll", "cpll", "spll", "aupll", "bpll_dummy" }; ++PNAME(gpll_cpll_spll_bpll_lpll_p) = { "gpll", "cpll", "spll", "bpll_dummy", "lpll_dummy" }; ++PNAME(gpll_cpll_spll_lpll_bpll_p) = { "gpll", "cpll", "spll", "lpll_dummy", "bpll_dummy" }; ++PNAME(gpll_cpll_vpll_bpll_lpll_p) = { "gpll", "cpll", "vpll", "bpll_dummy", "lpll_dummy" }; ++PNAME(gpll_spll_aupll_bpll_lpll_p) = { "gpll", "spll", "aupll", "bpll_dummy", "lpll_dummy" }; ++PNAME(gpll_spll_isppvtpll_bpll_lpll_p) = { "gpll", "spll", "isp_pvtpll", "bpll_dummy", "lpll_dummy" }; ++PNAME(gpll_cpll_spll_aupll_lpll_24m_p) = { "gpll", "cpll", "spll", "aupll", "lpll_dummy", "xin24m" }; ++PNAME(gpll_cpll_spll_vpll_bpll_lpll_p) = { "gpll", "cpll", "spll", "vpll", "bpll_dummy", "lpll_dummy" }; ++PNAME(cpll_vpll_lpll_bpll_p) = { "cpll", "vpll", "lpll_dummy", "bpll_dummy" }; ++PNAME(mux_24m_ccipvtpll_gpll_lpll_p) = { "xin24m", "cci_pvtpll", "gpll", "lpll" }; ++PNAME(mux_24m_spll_gpll_cpll_p) = {"xin24m", "spll", "gpll", "cpll" }; ++PNAME(audio_frac_int_p) = { "xin24m", "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2", ++ "clk_audio_frac_3", "clk_audio_int_0", "clk_audio_int_1", "clk_audio_int_2" }; ++PNAME(audio_frac_p) = { "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2", "clk_audio_frac_3" }; ++PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" }; ++PNAME(mux_100m_50m_24m_p) = { "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; ++PNAME(mux_100m_24m_lclk0_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_0" }; ++PNAME(mux_100m_24m_lclk1_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_1" }; ++PNAME(mux_150m_100m_50m_24m_p) = { "clk_gpll_div8", "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; ++PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; ++PNAME(mux_400m_200m_100m_24m_p) = { "clk_gpll_div3", "clk_gpll_div6", "clk_cpll_div10", "xin24m" }; ++PNAME(mux_500m_250m_100m_24m_p) = { "clk_cpll_div2", "clk_cpll_div4", "clk_cpll_div10", "xin24m" }; ++PNAME(mux_600m_400m_300m_24m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div4", "xin24m" }; ++PNAME(mux_350m_175m_116m_24m_p) = { "clk_spll_div2", "clk_spll_div4", "clk_spll_div6", "xin24m" }; ++PNAME(mux_175m_116m_58m_24m_p) = { "clk_spll_div4", "clk_spll_div6", "clk_spll_div12", "xin24m" }; ++PNAME(mux_116m_58m_24m_p) = { "clk_spll_div6", "clk_spll_div12", "xin24m" }; ++PNAME(mclk_sai0_8ch_p) = { "mclk_sai0_8ch_src", "sai0_mclkin", "sai1_mclkin" }; ++PNAME(mclk_sai1_8ch_p) = { "mclk_sai1_8ch_src", "sai1_mclkin" }; ++PNAME(mclk_sai2_2ch_p) = { "mclk_sai2_2ch_src", "sai2_mclkin", "sai1_mclkin" }; ++PNAME(mclk_sai3_2ch_p) = { "mclk_sai3_2ch_src", "sai3_mclkin", "sai1_mclkin" }; ++PNAME(mclk_sai4_2ch_p) = { "mclk_sai4_2ch_src", "sai4_mclkin", "sai1_mclkin" }; ++PNAME(mclk_sai5_8ch_p) = { "mclk_sai5_8ch_src", "sai1_mclkin" }; ++PNAME(mclk_sai6_8ch_p) = { "mclk_sai6_8ch_src", "sai1_mclkin" }; ++PNAME(mclk_sai7_8ch_p) = { "mclk_sai7_8ch_src", "sai1_mclkin" }; ++PNAME(mclk_sai8_8ch_p) = { "mclk_sai8_8ch_src", "sai1_mclkin" }; ++PNAME(mclk_sai9_8ch_p) = { "mclk_sai9_8ch_src", "sai1_mclkin" }; ++PNAME(uart1_p) = { "clk_uart1_src_top", "xin24m" }; ++PNAME(pdm0_p) = { "clk_pdm0_src_top", "xin24m" }; ++PNAME(mclk_pdm0_p) = { "mclk_pdm0_src_top", "xin24m" }; ++PNAME(clk_gmac1_ptp_ref_src_p) = { "gpll", "cpll", "gmac1_ptp_refclk_in" }; ++PNAME(clk_gmac0_ptp_ref_src_p) = { "gpll", "cpll", "gmac0_ptp_refclk_in" }; ++PNAME(dclk_ebc_p) = { "gpll", "cpll", "vpll", "aupll", "lpll_dummy", ++ "dclk_ebc_frac", "xin24m" }; ++PNAME(dclk_vp0_p) = { "dclk_vp0_src", "clk_hdmiphy_pixel0" }; ++PNAME(dclk_vp1_p) = { "dclk_vp1_src", "clk_hdmiphy_pixel0" }; ++PNAME(dclk_vp2_p) = { "dclk_vp2_src", "clk_hdmiphy_pixel0" }; ++PNAME(clk_uart_p) = { "gpll", "cpll", "aupll", "xin24m", "clk_uart_frac_0", ++ "clk_uart_frac_1", "clk_uart_frac_2"}; ++PNAME(clk_freq_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", "sai2_mclkin", ++ "sai3_mclkin", "sai4_mclkin", "sai_sclkin_freq"}; ++PNAME(clk_counter_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", "sai2_mclkin", ++ "sai3_mclkin", "sai4_mclkin", "sai_sclkin_counter"}; ++PNAME(sai_sclkin_freq_p) = { "sai0_sclk_in", "sai1_sclk_in", "sai2_sclk_in", ++ "sai3_sclk_in", "sai4_sclk_in"}; ++PNAME(clk_ref_pcie0_phy_p) = { "clk_pcie_100m_src", "clk_pcie_100m_nduty_src", ++ "xin24m"}; ++PNAME(hclk_vi_root_p) = { "clk_gpll_div6", "clk_cpll_div10", ++ "aclk_vi_root_inter", "xin24m"}; ++PNAME(clk_ref_osc_mphy_p) = { "xin24m", "clk_gpio_mphy_i", "clk_ref_mphy_26m"}; ++PNAME(mux_pmu200m_pmu100m_pmu50m_24m_p) = { "clk_200m_pmu_src", "clk_100m_pmu_src", ++ "clk_50m_pmu_src", "xin24m" }; ++PNAME(mux_pmu100m_pmu50m_24m_p) = { "clk_100m_pmu_src", "clk_50m_pmu_src", "xin24m" }; ++PNAME(mux_pmu100m_24m_32k_p) = { "clk_100m_pmu_src", "xin24m", "xin_osc0_div" }; ++PNAME(clk_phy_ref_src_p) = { "xin24m", "clk_pmuphy_ref_src" }; ++PNAME(clk_usbphy_ref_src_p) = { "usbphy0_24m", "usbphy1_24m" }; ++PNAME(clk_cpll_ref_src_p) = { "xin24m", "clk_usbphy_ref_src" }; ++PNAME(clk_aupll_ref_src_p) = { "xin24m", "clk_aupll_ref_io" }; ++ ++static struct rockchip_pll_clock rk3576_pll_clks[] __initdata = { ++ [bpll] = PLL(pll_rk3588_core, PLL_BPLL, "bpll", mux_pll_p, ++ 0, RK3576_PLL_CON(0), ++ RK3576_BPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), ++ [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, ++ 0, RK3576_LPLL_CON(16), ++ RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), ++ [vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p, ++ 0, RK3576_PLL_CON(88), ++ RK3576_MODE_CON0, 4, 15, 0, rk3576_pll_rates), ++ [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, ++ 0, RK3576_PLL_CON(96), ++ RK3576_MODE_CON0, 6, 15, 0, rk3576_pll_rates), ++ [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3576_PLL_CON(104), ++ RK3576_MODE_CON0, 8, 15, 0, rk3576_pll_rates), ++ [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3576_PLL_CON(112), ++ RK3576_MODE_CON0, 2, 15, 0, rk3576_pll_rates), ++ [ppll] = PLL(pll_rk3588_ddr, PLL_PPLL, "ppll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3576_PMU_PLL_CON(128), ++ RK3576_MODE_CON0, 10, 15, 0, rk3576_ppll_rates), ++}; ++ ++static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { ++ /* ++ * CRU Clock-Architecture ++ */ ++ /* fixed */ ++ FACTOR(0, "xin12m", "xin24m", 0, 1, 2), ++ ++ COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IS_CRITICAL, ++ RK3576_PMU_CLKSEL_CON(21), 0, ++ RK3576_PMU_CLKGATE_CON(7), 11, GFLAGS), ++ ++ FACTOR(0, "clk_spll_div12", "spll", 0, 1, 12), ++ FACTOR(0, "clk_spll_div6", "spll", 0, 1, 6), ++ FACTOR(0, "clk_spll_div4", "spll", 0, 1, 4), ++ FACTOR(0, "lpll_div2", "lpll", 0, 1, 2), ++ FACTOR(0, "bpll_div4", "bpll", 0, 1, 4), ++ ++ /* top */ ++ COMPOSITE(CLK_CPLL_DIV20, "clk_cpll_div20", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 0, GFLAGS), ++ COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 1, GFLAGS), ++ COMPOSITE(CLK_GPLL_DIV8, "clk_gpll_div8", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 2, GFLAGS), ++ COMPOSITE(CLK_GPLL_DIV6, "clk_gpll_div6", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 3, GFLAGS), ++ COMPOSITE(CLK_CPLL_DIV4, "clk_cpll_div4", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 4, GFLAGS), ++ COMPOSITE(CLK_GPLL_DIV4, "clk_gpll_div4", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 5, GFLAGS), ++ COMPOSITE(CLK_SPLL_DIV2, "clk_spll_div2", gpll_cpll_spll_bpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(3), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 6, GFLAGS), ++ COMPOSITE(CLK_GPLL_DIV3, "clk_gpll_div3", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(3), 12, 1, MFLAGS, 7, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 7, GFLAGS), ++ COMPOSITE(CLK_CPLL_DIV2, "clk_cpll_div2", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 9, GFLAGS), ++ COMPOSITE(CLK_GPLL_DIV2, "clk_gpll_div2", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 10, GFLAGS), ++ COMPOSITE(CLK_SPLL_DIV1, "clk_spll_div1", gpll_cpll_spll_bpll_lpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(6), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(0), 12, GFLAGS), ++ COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(8), 7, 2, MFLAGS, ++ RK3576_CLKGATE_CON(1), 1, GFLAGS), ++ COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_aupll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(9), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(1), 3, GFLAGS), ++ COMPOSITE(ACLK_TOP_MID, "aclk_top_mid", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(10), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(1), 6, GFLAGS), ++ COMPOSITE(ACLK_SECURE_HIGH, "aclk_secure_high", gpll_spll_aupll_bpll_lpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(10), 11, 3, MFLAGS, 6, 5, DFLAGS, ++ RK3576_CLKGATE_CON(1), 7, GFLAGS), ++ COMPOSITE_NODIV(HCLK_TOP, "hclk_top", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(19), 2, 2, MFLAGS, ++ RK3576_CLKGATE_CON(1), 14, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VO0VOP_CHANNEL, "hclk_vo0vop_channel", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(19), 6, 2, MFLAGS, ++ RK3576_CLKGATE_CON(2), 0, GFLAGS), ++ COMPOSITE(ACLK_VO0VOP_CHANNEL, "aclk_vo0vop_channel", gpll_cpll_lpll_bpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(19), 12, 2, MFLAGS, 8, 4, DFLAGS, ++ RK3576_CLKGATE_CON(2), 1, GFLAGS), ++ MUX(CLK_AUDIO_FRAC_0_SRC, "clk_audio_frac_0_src", gpll_cpll_aupll_24m_p, 0, ++ RK3576_CLKSEL_CON(13), 0, 2, MFLAGS), ++ COMPOSITE_FRAC(CLK_AUDIO_FRAC_0, "clk_audio_frac_0", "clk_audio_frac_0_src", 0, ++ RK3576_CLKSEL_CON(12), 0, ++ RK3576_CLKGATE_CON(1), 10, GFLAGS), ++ MUX(CLK_AUDIO_FRAC_1_SRC, "clk_audio_frac_1_src", gpll_cpll_aupll_24m_p, 0, ++ RK3576_CLKSEL_CON(15), 0, 2, MFLAGS), ++ COMPOSITE_FRAC(CLK_AUDIO_FRAC_1, "clk_audio_frac_1", "clk_audio_frac_1_src", 0, ++ RK3576_CLKSEL_CON(14), 0, ++ RK3576_CLKGATE_CON(1), 11, GFLAGS), ++ MUX(CLK_AUDIO_FRAC_2_SRC, "clk_audio_frac_2_src", gpll_cpll_aupll_24m_p, 0, ++ RK3576_CLKSEL_CON(17), 0, 2, MFLAGS), ++ COMPOSITE_FRAC(CLK_AUDIO_FRAC_2, "clk_audio_frac_2", "clk_audio_frac_2_src", 0, ++ RK3576_CLKSEL_CON(16), 0, ++ RK3576_CLKGATE_CON(1), 12, GFLAGS), ++ MUX(CLK_AUDIO_FRAC_3_SRC, "clk_audio_frac_3_src", gpll_cpll_aupll_24m_p, 0, ++ RK3576_CLKSEL_CON(19), 0, 2, MFLAGS), ++ COMPOSITE_FRAC(CLK_AUDIO_FRAC_3, "clk_audio_frac_3", "clk_audio_frac_3_src", 0, ++ RK3576_CLKSEL_CON(18), 0, ++ RK3576_CLKGATE_CON(1), 13, GFLAGS), ++ MUX(0, "clk_uart_frac_0_src", gpll_cpll_aupll_24m_p, 0, ++ RK3576_CLKSEL_CON(22), 0, 2, MFLAGS), ++ COMPOSITE_FRAC(CLK_UART_FRAC_0, "clk_uart_frac_0", "clk_uart_frac_0_src", 0, ++ RK3576_CLKSEL_CON(21), 0, ++ RK3576_CLKGATE_CON(2), 5, GFLAGS), ++ MUX(0, "clk_uart_frac_1_src", gpll_cpll_aupll_24m_p, 0, ++ RK3576_CLKSEL_CON(24), 0, 2, MFLAGS), ++ COMPOSITE_FRAC(CLK_UART_FRAC_1, "clk_uart_frac_1", "clk_uart_frac_1_src", 0, ++ RK3576_CLKSEL_CON(23), 0, ++ RK3576_CLKGATE_CON(2), 6, GFLAGS), ++ MUX(0, "clk_uart_frac_2_src", gpll_cpll_aupll_24m_p, 0, ++ RK3576_CLKSEL_CON(26), 0, 2, MFLAGS), ++ COMPOSITE_FRAC(CLK_UART_FRAC_2, "clk_uart_frac_2", "clk_uart_frac_2_src", 0, ++ RK3576_CLKSEL_CON(25), 0, ++ RK3576_CLKGATE_CON(2), 7, GFLAGS), ++ COMPOSITE(CLK_UART1_SRC_TOP, "clk_uart1_src_top", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(27), 13, 3, MFLAGS, 5, 8, DFLAGS, ++ RK3576_CLKGATE_CON(2), 13, GFLAGS), ++ COMPOSITE_NOMUX(CLK_AUDIO_INT_0, "clk_audio_int_0", "gpll", 0, ++ RK3576_CLKSEL_CON(28), 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(2), 14, GFLAGS), ++ COMPOSITE_NOMUX(CLK_AUDIO_INT_1, "clk_audio_int_1", "cpll", 0, ++ RK3576_CLKSEL_CON(28), 5, 5, DFLAGS, ++ RK3576_CLKGATE_CON(2), 15, GFLAGS), ++ COMPOSITE_NOMUX(CLK_AUDIO_INT_2, "clk_audio_int_2", "aupll", 0, ++ RK3576_CLKSEL_CON(28), 10, 5, DFLAGS, ++ RK3576_CLKGATE_CON(3), 0, GFLAGS), ++ COMPOSITE(CLK_PDM0_SRC_TOP, "clk_pdm0_src_top", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(29), 9, 3, MFLAGS, 0, 9, DFLAGS, ++ RK3576_CLKGATE_CON(3), 2, GFLAGS), ++ COMPOSITE_NOMUX(CLK_GMAC0_125M_SRC, "clk_gmac0_125m_src", "cpll", 0, ++ RK3576_CLKSEL_CON(30), 10, 5, DFLAGS, ++ RK3576_CLKGATE_CON(3), 6, GFLAGS), ++ COMPOSITE_NOMUX(CLK_GMAC1_125M_SRC, "clk_gmac1_125m_src", "cpll", 0, ++ RK3576_CLKSEL_CON(31), 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(3), 7, GFLAGS), ++ COMPOSITE(LCLK_ASRC_SRC_0, "lclk_asrc_src_0", audio_frac_p, 0, ++ RK3576_CLKSEL_CON(31), 10, 2, MFLAGS, 5, 5, DFLAGS, ++ RK3576_CLKGATE_CON(3), 10, GFLAGS), ++ COMPOSITE(LCLK_ASRC_SRC_1, "lclk_asrc_src_1", audio_frac_p, 0, ++ RK3576_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(3), 11, GFLAGS), ++ COMPOSITE(REF_CLK0_OUT_PLL, "ref_clk0_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0, ++ RK3576_CLKSEL_CON(33), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(4), 1, GFLAGS), ++ COMPOSITE(REF_CLK1_OUT_PLL, "ref_clk1_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0, ++ RK3576_CLKSEL_CON(34), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(4), 2, GFLAGS), ++ COMPOSITE(REF_CLK2_OUT_PLL, "ref_clk2_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0, ++ RK3576_CLKSEL_CON(35), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(4), 3, GFLAGS), ++ COMPOSITE(REFCLKO25M_GMAC0_OUT, "refclko25m_gmac0_out", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS, ++ RK3576_CLKGATE_CON(5), 10, GFLAGS), ++ COMPOSITE(REFCLKO25M_GMAC1_OUT, "refclko25m_gmac1_out", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(36), 15, 1, MFLAGS, 8, 7, DFLAGS, ++ RK3576_CLKGATE_CON(5), 11, GFLAGS), ++ COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, ++ RK3576_CLKSEL_CON(37), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(5), 12, GFLAGS), ++ GATE(CLK_GMAC0_RMII_CRU, "clk_gmac0_rmii_cru", "clk_cpll_div20", 0, ++ RK3576_CLKGATE_CON(5), 13, GFLAGS), ++ GATE(CLK_GMAC1_RMII_CRU, "clk_gmac1_rmii_cru", "clk_cpll_div20", 0, ++ RK3576_CLKGATE_CON(5), 14, GFLAGS), ++ GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, ++ RK3576_CLKGATE_CON(5), 15, GFLAGS), ++ COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(6), 3, GFLAGS), ++ COMPOSITE(CLK_MIPI_CAMERAOUT_M1, "clk_mipi_cameraout_m1", mux_24m_spll_gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(6), 4, GFLAGS), ++ COMPOSITE(CLK_MIPI_CAMERAOUT_M2, "clk_mipi_cameraout_m2", mux_24m_spll_gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(6), 5, GFLAGS), ++ COMPOSITE(MCLK_PDM0_SRC_TOP, "mclk_pdm0_src_top", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(41), 7, 3, MFLAGS, 2, 5, DFLAGS, ++ RK3576_CLKGATE_CON(6), 8, GFLAGS), ++ ++ /* bus */ ++ COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(55), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(11), 0, GFLAGS), ++ COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(55), 2, 2, MFLAGS, ++ RK3576_CLKGATE_CON(11), 1, GFLAGS), ++ COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(55), 9, 1, MFLAGS, 4, 5, DFLAGS, ++ RK3576_CLKGATE_CON(11), 2, GFLAGS), ++ GATE(HCLK_CAN0, "hclk_can0", "hclk_bus_root", 0, ++ RK3576_CLKGATE_CON(11), 6, GFLAGS), ++ COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_24m_p, 0, ++ RK3576_CLKSEL_CON(56), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(11), 7, GFLAGS), ++ GATE(HCLK_CAN1, "hclk_can1", "hclk_bus_root", 0, ++ RK3576_CLKGATE_CON(11), 8, GFLAGS), ++ COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_24m_p, 0, ++ RK3576_CLKSEL_CON(56), 12, 2, MFLAGS, 7, 5, DFLAGS, ++ RK3576_CLKGATE_CON(11), 9, GFLAGS), ++ GATE(CLK_KEY_SHIFT, "clk_key_shift", "xin24m", CLK_IS_CRITICAL, ++ RK3576_CLKGATE_CON(11), 15, GFLAGS), ++ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 0, GFLAGS), ++ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 1, GFLAGS), ++ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 2, GFLAGS), ++ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 3, GFLAGS), ++ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 4, GFLAGS), ++ GATE(PCLK_I2C6, "pclk_i2c6", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 5, GFLAGS), ++ GATE(PCLK_I2C7, "pclk_i2c7", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 6, GFLAGS), ++ GATE(PCLK_I2C8, "pclk_i2c8", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 7, GFLAGS), ++ GATE(PCLK_I2C9, "pclk_i2c9", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 8, GFLAGS), ++ GATE(PCLK_WDT_BUSMCU, "pclk_wdt_busmcu", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(12), 9, GFLAGS), ++ GATE(TCLK_WDT_BUSMCU, "tclk_wdt_busmcu", "xin24m", 0, ++ RK3576_CLKGATE_CON(12), 10, GFLAGS), ++ GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, ++ RK3576_CLKGATE_CON(12), 11, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(57), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(12), 12, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(57), 2, 2, MFLAGS, ++ RK3576_CLKGATE_CON(12), 13, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(57), 4, 2, MFLAGS, ++ RK3576_CLKGATE_CON(12), 14, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(57), 6, 2, MFLAGS, ++ RK3576_CLKGATE_CON(12), 15, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(57), 8, 2, MFLAGS, ++ RK3576_CLKGATE_CON(13), 0, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(57), 10, 2, MFLAGS, ++ RK3576_CLKGATE_CON(13), 1, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(57), 12, 2, MFLAGS, ++ RK3576_CLKGATE_CON(13), 2, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(57), 14, 2, MFLAGS, ++ RK3576_CLKGATE_CON(13), 3, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C9, "clk_i2c9", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(58), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(13), 4, GFLAGS), ++ GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(13), 6, GFLAGS), ++ COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, ++ RK3576_CLKSEL_CON(58), 12, 1, MFLAGS, 4, 8, DFLAGS, ++ RK3576_CLKGATE_CON(13), 7, GFLAGS), ++ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(13), 8, GFLAGS), ++ COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, ++ RK3576_CLKSEL_CON(59), 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(13), 9, GFLAGS), ++ GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(13), 10, GFLAGS), ++ GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(13), 11, GFLAGS), ++ GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(13), 12, GFLAGS), ++ GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(13), 13, GFLAGS), ++ GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(13), 14, GFLAGS), ++ GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(13), 15, GFLAGS), ++ GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(14), 0, GFLAGS), ++ GATE(PCLK_UART8, "pclk_uart8", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(14), 1, GFLAGS), ++ GATE(PCLK_UART9, "pclk_uart9", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(14), 2, GFLAGS), ++ GATE(PCLK_UART10, "pclk_uart10", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(14), 3, GFLAGS), ++ GATE(PCLK_UART11, "pclk_uart11", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(14), 4, GFLAGS), ++ COMPOSITE(SCLK_UART0, "sclk_uart0", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(60), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(14), 5, GFLAGS), ++ COMPOSITE(SCLK_UART2, "sclk_uart2", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(61), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(14), 6, GFLAGS), ++ COMPOSITE(SCLK_UART3, "sclk_uart3", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(62), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(14), 9, GFLAGS), ++ COMPOSITE(SCLK_UART4, "sclk_uart4", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(63), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(14), 12, GFLAGS), ++ COMPOSITE(SCLK_UART5, "sclk_uart5", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(64), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(14), 15, GFLAGS), ++ COMPOSITE(SCLK_UART6, "sclk_uart6", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(65), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(15), 2, GFLAGS), ++ COMPOSITE(SCLK_UART7, "sclk_uart7", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(66), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(15), 5, GFLAGS), ++ COMPOSITE(SCLK_UART8, "sclk_uart8", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(67), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(15), 8, GFLAGS), ++ COMPOSITE(SCLK_UART9, "sclk_uart9", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(68), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(15), 9, GFLAGS), ++ COMPOSITE(SCLK_UART10, "sclk_uart10", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(69), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(15), 10, GFLAGS), ++ COMPOSITE(SCLK_UART11, "sclk_uart11", clk_uart_p, 0, ++ RK3576_CLKSEL_CON(70), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(15), 11, GFLAGS), ++ GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(15), 13, GFLAGS), ++ GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(15), 14, GFLAGS), ++ GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(15), 15, GFLAGS), ++ GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(16), 0, GFLAGS), ++ GATE(PCLK_SPI4, "pclk_spi4", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(16), 1, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(70), 13, 2, MFLAGS, ++ RK3576_CLKGATE_CON(16), 2, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(71), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(16), 3, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(71), 2, 2, MFLAGS, ++ RK3576_CLKGATE_CON(16), 4, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(71), 4, 2, MFLAGS, ++ RK3576_CLKGATE_CON(16), 5, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(71), 6, 2, MFLAGS, ++ RK3576_CLKGATE_CON(16), 6, GFLAGS), ++ GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(16), 7, GFLAGS), ++ GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, ++ RK3576_CLKGATE_CON(16), 8, GFLAGS), ++ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(16), 10, GFLAGS), ++ COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(71), 8, 2, MFLAGS, ++ RK3576_CLKGATE_CON(16), 11, GFLAGS), ++ GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0, ++ RK3576_CLKGATE_CON(16), 13, GFLAGS), ++ GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_pvtm_clkout", 0, ++ RK3576_CLKGATE_CON(16), 15, GFLAGS), ++ GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(17), 3, GFLAGS), ++ GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(17), 4, GFLAGS), ++ COMPOSITE_NODIV(CLK_TIMER0_ROOT, "clk_timer0_root", mux_100m_24m_p, 0, ++ RK3576_CLKSEL_CON(71), 14, 1, MFLAGS, ++ RK3576_CLKGATE_CON(17), 5, GFLAGS), ++ GATE(CLK_TIMER0, "clk_timer0", "clk_timer0_root", 0, ++ RK3576_CLKGATE_CON(17), 6, GFLAGS), ++ GATE(CLK_TIMER1, "clk_timer1", "clk_timer0_root", 0, ++ RK3576_CLKGATE_CON(17), 7, GFLAGS), ++ GATE(CLK_TIMER2, "clk_timer2", "clk_timer0_root", 0, ++ RK3576_CLKGATE_CON(17), 8, GFLAGS), ++ GATE(CLK_TIMER3, "clk_timer3", "clk_timer0_root", 0, ++ RK3576_CLKGATE_CON(17), 9, GFLAGS), ++ GATE(CLK_TIMER4, "clk_timer4", "clk_timer0_root", 0, ++ RK3576_CLKGATE_CON(17), 10, GFLAGS), ++ GATE(CLK_TIMER5, "clk_timer5", "clk_timer0_root", 0, ++ RK3576_CLKGATE_CON(17), 11, GFLAGS), ++ GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(17), 13, GFLAGS), ++ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(17), 15, GFLAGS), ++ GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, ++ RK3576_CLKGATE_CON(18), 0, GFLAGS), ++ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(18), 1, GFLAGS), ++ GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, ++ RK3576_CLKGATE_CON(18), 2, GFLAGS), ++ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(18), 3, GFLAGS), ++ GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, ++ RK3576_CLKGATE_CON(18), 4, GFLAGS), ++ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(18), 5, GFLAGS), ++ GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, ++ RK3576_CLKGATE_CON(18), 6, GFLAGS), ++ GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, ++ RK3576_CLKGATE_CON(18), 7, GFLAGS), ++ GATE(PCLK_DECOM, "pclk_decom", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(18), 8, GFLAGS), ++ COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, ++ RK3576_CLKSEL_CON(72), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(18), 9, GFLAGS), ++ COMPOSITE_NODIV(CLK_TIMER1_ROOT, "clk_timer1_root", mux_100m_24m_p, 0, ++ RK3576_CLKSEL_CON(72), 6, 1, MFLAGS, ++ RK3576_CLKGATE_CON(18), 10, GFLAGS), ++ GATE(CLK_TIMER6, "clk_timer6", "clk_timer1_root", 0, ++ RK3576_CLKGATE_CON(18), 11, GFLAGS), ++ COMPOSITE(CLK_TIMER7, "clk_timer7", mux_100m_24m_lclk0_p, 0, ++ RK3576_CLKSEL_CON(72), 12, 2, MFLAGS, 7, 5, DFLAGS, ++ RK3576_CLKGATE_CON(18), 12, GFLAGS), ++ COMPOSITE(CLK_TIMER8, "clk_timer8", mux_100m_24m_lclk1_p, 0, ++ RK3576_CLKSEL_CON(73), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(18), 13, GFLAGS), ++ GATE(CLK_TIMER9, "clk_timer9", "clk_timer1_root", 0, ++ RK3576_CLKGATE_CON(18), 14, GFLAGS), ++ GATE(CLK_TIMER10, "clk_timer10", "clk_timer1_root", 0, ++ RK3576_CLKGATE_CON(18), 15, GFLAGS), ++ GATE(CLK_TIMER11, "clk_timer11", "clk_timer1_root", 0, ++ RK3576_CLKGATE_CON(19), 0, GFLAGS), ++ GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, ++ RK3576_CLKGATE_CON(19), 1, GFLAGS), ++ GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, ++ RK3576_CLKGATE_CON(19), 2, GFLAGS), ++ GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, ++ RK3576_CLKGATE_CON(19), 3, GFLAGS), ++ GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0, ++ RK3576_CLKGATE_CON(19), 4, GFLAGS), ++ GATE(HCLK_I3C0, "hclk_i3c0", "hclk_bus_root", 0, ++ RK3576_CLKGATE_CON(19), 7, GFLAGS), ++ GATE(HCLK_I3C1, "hclk_i3c1", "hclk_bus_root", 0, ++ RK3576_CLKGATE_CON(19), 9, GFLAGS), ++ COMPOSITE_NODIV(HCLK_BUS_CM0_ROOT, "hclk_bus_cm0_root", mux_400m_200m_100m_24m_p, 0, ++ RK3576_CLKSEL_CON(73), 13, 2, MFLAGS, ++ RK3576_CLKGATE_CON(19), 10, GFLAGS), ++ GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus_cm0_root", 0, ++ RK3576_CLKGATE_CON(19), 12, GFLAGS), ++ COMPOSITE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", mux_24m_32k_p, 0, ++ RK3576_CLKSEL_CON(74), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(19), 14, GFLAGS), ++ GATE(PCLK_PMU2, "pclk_pmu2", "pclk_bus_root", CLK_IS_CRITICAL, ++ RK3576_CLKGATE_CON(19), 15, GFLAGS), ++ GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(20), 4, GFLAGS), ++ COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(74), 6, 2, MFLAGS, ++ RK3576_CLKGATE_CON(20), 5, GFLAGS), ++ GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0, ++ RK3576_CLKGATE_CON(20), 7, GFLAGS), ++ GATE(CLK_RC_PWM2, "clk_rc_pwm2", "clk_pvtm_clkout", 0, ++ RK3576_CLKGATE_CON(20), 6, GFLAGS), ++ COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_freq_pwm1_p, 0, ++ RK3576_CLKSEL_CON(74), 8, 3, MFLAGS, ++ RK3576_CLKGATE_CON(20), 8, GFLAGS), ++ COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", clk_counter_pwm1_p, 0, ++ RK3576_CLKSEL_CON(74), 11, 3, MFLAGS, ++ RK3576_CLKGATE_CON(20), 9, GFLAGS), ++ COMPOSITE_NODIV(SAI_SCLKIN_FREQ, "sai_sclkin_freq", sai_sclkin_freq_p, 0, ++ RK3576_CLKSEL_CON(75), 0, 3, MFLAGS, ++ RK3576_CLKGATE_CON(20), 10, GFLAGS), ++ COMPOSITE_NODIV(SAI_SCLKIN_COUNTER, "sai_sclkin_counter", sai_sclkin_freq_p, 0, ++ RK3576_CLKSEL_CON(75), 3, 3, MFLAGS, ++ RK3576_CLKGATE_CON(20), 11, GFLAGS), ++ COMPOSITE(CLK_I3C0, "clk_i3c0", gpll_cpll_aupll_spll_p, 0, ++ RK3576_CLKSEL_CON(78), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(20), 12, GFLAGS), ++ COMPOSITE(CLK_I3C1, "clk_i3c1", gpll_cpll_aupll_spll_p, 0, ++ RK3576_CLKSEL_CON(78), 12, 2, MFLAGS, 7, 5, DFLAGS, ++ RK3576_CLKGATE_CON(20), 13, GFLAGS), ++ GATE(PCLK_CSIDPHY1, "pclk_csidphy1", "pclk_bus_root", 0, ++ RK3576_CLKGATE_CON(40), 2, GFLAGS), ++ ++ /* cci */ ++ COMPOSITE(PCLK_CCI_ROOT, "pclk_cci_root", mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL, ++ RK3576_CCI_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CCI_CLKGATE_CON(1), 10, GFLAGS), ++ COMPOSITE(ACLK_CCI_ROOT, "aclk_cci_root", mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL, ++ RK3576_CCI_CLKSEL_CON(4), 12, 2, MFLAGS, 7, 5, DFLAGS, ++ RK3576_CCI_CLKGATE_CON(1), 11, GFLAGS), ++ ++ /* center */ ++ COMPOSITE_DIV_OFFSET(ACLK_CENTER_ROOT, "aclk_center_root", gpll_cpll_spll_aupll_bpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(168), 5, 3, MFLAGS, ++ RK3576_CLKSEL_CON(167), 9, 5, DFLAGS, ++ RK3576_CLKGATE_CON(72), 0, GFLAGS), ++ COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(168), 8, 2, MFLAGS, ++ RK3576_CLKGATE_CON(72), 1, GFLAGS), ++ COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(168), 10, 2, MFLAGS, ++ RK3576_CLKGATE_CON(72), 2, GFLAGS), ++ COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(168), 12, 2, MFLAGS, ++ RK3576_CLKGATE_CON(72), 3, GFLAGS), ++ GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IGNORE_UNUSED, ++ RK3576_CLKGATE_CON(72), 5, GFLAGS), ++ GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IGNORE_UNUSED, ++ RK3576_CLKGATE_CON(72), 6, GFLAGS), ++ GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IGNORE_UNUSED, ++ RK3576_CLKGATE_CON(72), 10, GFLAGS), ++ GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IGNORE_UNUSED, ++ RK3576_CLKGATE_CON(72), 11, GFLAGS), ++ ++ /* ddr */ ++ COMPOSITE(PCLK_DDR_ROOT, "pclk_ddr_root", gpll_cpll_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(76), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(21), 0, GFLAGS), ++ GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", CLK_IGNORE_UNUSED, ++ RK3576_CLKGATE_CON(21), 1, GFLAGS), ++ COMPOSITE(HCLK_DDR_ROOT, "hclk_ddr_root", gpll_cpll_p, CLK_IGNORE_UNUSED, ++ RK3576_CLKSEL_CON(77), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(22), 11, GFLAGS), ++ GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_ddr_root", CLK_IS_CRITICAL, ++ RK3576_CLKGATE_CON(22), 15, GFLAGS), ++ COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_100m_24m_p, 0, ++ RK3576_CLKSEL_CON(77), 6, 1, MFLAGS, ++ RK3576_CLKGATE_CON(23), 3, GFLAGS), ++ GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, ++ RK3576_CLKGATE_CON(23), 4, GFLAGS), ++ GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, ++ RK3576_CLKGATE_CON(23), 5, GFLAGS), ++ GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, ++ RK3576_CLKGATE_CON(23), 6, GFLAGS), ++ GATE(PCLK_WDT, "pclk_wdt", "pclk_ddr_root", 0, ++ RK3576_CLKGATE_CON(23), 7, GFLAGS), ++ GATE(PCLK_TIMER, "pclk_timer", "pclk_ddr_root", 0, ++ RK3576_CLKGATE_CON(23), 8, GFLAGS), ++ COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, 0, ++ RK3576_CLKSEL_CON(77), 12, 1, MFLAGS, 7, 5, DFLAGS, ++ RK3576_CLKGATE_CON(23), 10, GFLAGS), ++ ++ /* gpu */ ++ COMPOSITE(CLK_GPU_SRC_PRE, "clk_gpu_src_pre", gpll_cpll_aupll_spll_lpll_p, 0, ++ RK3576_CLKSEL_CON(165), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(69), 1, GFLAGS), ++ GATE(CLK_GPU, "clk_gpu", "clk_gpu_src_pre", 0, ++ RK3576_CLKGATE_CON(69), 3, GFLAGS), ++ COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(166), 10, 2, MFLAGS, ++ RK3576_CLKGATE_CON(69), 8, GFLAGS), ++ ++ /* npu */ ++ COMPOSITE_NODIV(HCLK_RKNN_ROOT, "hclk_rknn_root", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(86), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(31), 4, GFLAGS), ++ COMPOSITE(CLK_RKNN_DSU0, "clk_rknn_dsu0", gpll_cpll_aupll_spll_p, 0, ++ RK3576_CLKSEL_CON(86), 7, 2, MFLAGS, 2, 5, DFLAGS, ++ RK3576_CLKGATE_CON(31), 5, GFLAGS), ++ GATE(ACLK_RKNN0, "aclk_rknn0", "clk_rknn_dsu0", 0, ++ RK3576_CLKGATE_CON(28), 9, GFLAGS), ++ GATE(ACLK_RKNN1, "aclk_rknn1", "clk_rknn_dsu0", 0, ++ RK3576_CLKGATE_CON(29), 0, GFLAGS), ++ COMPOSITE_NODIV(PCLK_NPUTOP_ROOT, "pclk_nputop_root", mux_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(87), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(31), 8, GFLAGS), ++ GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_nputop_root", 0, ++ RK3576_CLKGATE_CON(31), 10, GFLAGS), ++ COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_100m_24m_p, 0, ++ RK3576_CLKSEL_CON(87), 2, 1, MFLAGS, ++ RK3576_CLKGATE_CON(31), 11, GFLAGS), ++ GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, ++ RK3576_CLKGATE_CON(31), 12, GFLAGS), ++ GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, ++ RK3576_CLKGATE_CON(31), 13, GFLAGS), ++ GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_nputop_root", 0, ++ RK3576_CLKGATE_CON(31), 14, GFLAGS), ++ GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, ++ RK3576_CLKGATE_CON(31), 15, GFLAGS), ++ GATE(ACLK_RKNN_CBUF, "aclk_rknn_cbuf", "clk_rknn_dsu0", 0, ++ RK3576_CLKGATE_CON(32), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, ++ RK3576_CLKSEL_CON(87), 3, 2, MFLAGS, ++ RK3576_CLKGATE_CON(32), 5, GFLAGS), ++ GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, ++ RK3576_CLKGATE_CON(32), 7, GFLAGS), ++ COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, ++ RK3576_CLKSEL_CON(87), 10, 1, MFLAGS, 5, 5, DFLAGS, ++ RK3576_CLKGATE_CON(32), 9, GFLAGS), ++ GATE(HCLK_RKNN_CBUF, "hclk_rknn_cbuf", "hclk_rknn_root", 0, ++ RK3576_CLKGATE_CON(32), 12, GFLAGS), ++ ++ /* nvm */ ++ COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(88), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(33), 0, GFLAGS), ++ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(88), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3576_CLKGATE_CON(33), 1, GFLAGS), ++ COMPOSITE(SCLK_FSPI_X2, "sclk_fspi_x2", gpll_cpll_24m_p, 0, ++ RK3576_CLKSEL_CON(89), 6, 2, MFLAGS, 0, 6, DFLAGS, ++ RK3576_CLKGATE_CON(33), 6, GFLAGS), ++ GATE(HCLK_FSPI, "hclk_fspi", "hclk_nvm_root", 0, ++ RK3576_CLKGATE_CON(33), 7, GFLAGS), ++ COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", gpll_cpll_24m_p, 0, ++ RK3576_CLKSEL_CON(89), 14, 2, MFLAGS, 8, 6, DFLAGS, ++ RK3576_CLKGATE_CON(33), 8, GFLAGS), ++ GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm_root", 0, ++ RK3576_CLKGATE_CON(33), 9, GFLAGS), ++ GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, ++ RK3576_CLKGATE_CON(33), 10, GFLAGS), ++ COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(90), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(33), 11, GFLAGS), ++ GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, ++ RK3576_CLKGATE_CON(33), 12, GFLAGS), ++ ++ /* usb */ ++ COMPOSITE(ACLK_UFS_ROOT, "aclk_ufs_root", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(115), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(47), 0, GFLAGS), ++ COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(115), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3576_CLKGATE_CON(47), 1, GFLAGS), ++ COMPOSITE_NODIV(PCLK_USB_ROOT, "pclk_usb_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(115), 12, 2, MFLAGS, ++ RK3576_CLKGATE_CON(47), 2, GFLAGS), ++ GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb_root", 0, ++ RK3576_CLKGATE_CON(47), 5, GFLAGS), ++ GATE(CLK_REF_USB3OTG0, "clk_ref_usb3otg0", "xin24m", 0, ++ RK3576_CLKGATE_CON(47), 6, GFLAGS), ++ GATE(CLK_SUSPEND_USB3OTG0, "clk_suspend_usb3otg0", "xin24m", 0, ++ RK3576_CLKGATE_CON(47), 7, GFLAGS), ++ GATE(ACLK_MMU2, "aclk_mmu2", "aclk_usb_root", 0, ++ RK3576_CLKGATE_CON(47), 12, GFLAGS), ++ GATE(ACLK_SLV_MMU2, "aclk_slv_mmu2", "aclk_usb_root", 0, ++ RK3576_CLKGATE_CON(47), 13, GFLAGS), ++ GATE(ACLK_UFS_SYS, "aclk_ufs_sys", "aclk_ufs_root", 0, ++ RK3576_CLKGATE_CON(47), 15, GFLAGS), ++ ++ /* vdec */ ++ COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(110), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(45), 0, GFLAGS), ++ COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", gpll_cpll_aupll_spll_p, 0, ++ RK3576_CLKSEL_CON(110), 7, 2, MFLAGS, 2, 5, DFLAGS, ++ RK3576_CLKGATE_CON(45), 1, GFLAGS), ++ COMPOSITE(ACLK_RKVDEC_ROOT_BAK, "aclk_rkvdec_root_bak", cpll_vpll_lpll_bpll_p, 0, ++ RK3576_CLKSEL_CON(110), 14, 2, MFLAGS, 9, 5, DFLAGS, ++ RK3576_CLKGATE_CON(45), 2, GFLAGS), ++ GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0, ++ RK3576_CLKGATE_CON(45), 3, GFLAGS), ++ COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_lpll_bpll_p, 0, ++ RK3576_CLKSEL_CON(111), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(45), 8, GFLAGS), ++ GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "aclk_rkvdec_root", 0, ++ RK3576_CLKGATE_CON(45), 9, GFLAGS), ++ ++ /* venc */ ++ COMPOSITE_NODIV(HCLK_VEPU0_ROOT, "hclk_vepu0_root", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(124), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(51), 0, GFLAGS), ++ COMPOSITE(ACLK_VEPU0_ROOT, "aclk_vepu0_root", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3576_CLKGATE_CON(51), 1, GFLAGS), ++ COMPOSITE(CLK_VEPU0_CORE, "clk_vepu0_core", gpll_cpll_spll_lpll_bpll_p, 0, ++ RK3576_CLKSEL_CON(124), 13, 3, MFLAGS, 8, 5, DFLAGS, ++ RK3576_CLKGATE_CON(51), 6, GFLAGS), ++ GATE(HCLK_VEPU0, "hclk_vepu0", "hclk_vepu0_root", 0, ++ RK3576_CLKGATE_CON(51), 4, GFLAGS), ++ GATE(ACLK_VEPU0, "aclk_vepu0", "aclk_vepu0_root", 0, ++ RK3576_CLKGATE_CON(51), 5, GFLAGS), ++ ++ /* vi */ ++ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_spll_isppvtpll_bpll_lpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(128), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(53), 0, GFLAGS), ++ COMPOSITE_NOMUX(ACLK_VI_ROOT_INTER, "aclk_vi_root_inter", "aclk_vi_root", 0, ++ RK3576_CLKSEL_CON(130), 10, 3, DFLAGS, ++ RK3576_CLKGATE_CON(54), 13, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", hclk_vi_root_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(128), 8, 2, MFLAGS, ++ RK3576_CLKGATE_CON(53), 1, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(128), 10, 2, MFLAGS, ++ RK3576_CLKGATE_CON(53), 2, GFLAGS), ++ COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(129), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(53), 6, GFLAGS), ++ GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, ++ RK3576_CLKGATE_CON(53), 7, GFLAGS), ++ GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, ++ RK3576_CLKGATE_CON(53), 8, GFLAGS), ++ COMPOSITE(CLK_ISP_CORE, "clk_isp_core", gpll_spll_isppvtpll_bpll_lpll_p, 0, ++ RK3576_CLKSEL_CON(129), 11, 3, MFLAGS, 6, 5, DFLAGS, ++ RK3576_CLKGATE_CON(53), 9, GFLAGS), ++ GATE(CLK_ISP_CORE_MARVIN, "clk_isp_core_marvin", "clk_isp_core", 0, ++ RK3576_CLKGATE_CON(53), 10, GFLAGS), ++ GATE(CLK_ISP_CORE_VICAP, "clk_isp_core_vicap", "clk_isp_core", 0, ++ RK3576_CLKGATE_CON(53), 11, GFLAGS), ++ GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0, ++ RK3576_CLKGATE_CON(53), 12, GFLAGS), ++ GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0, ++ RK3576_CLKGATE_CON(53), 13, GFLAGS), ++ GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0, ++ RK3576_CLKGATE_CON(53), 15, GFLAGS), ++ GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0, ++ RK3576_CLKGATE_CON(54), 0, GFLAGS), ++ GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_isp_core", 0, ++ RK3576_CLKGATE_CON(54), 1, GFLAGS), ++ GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, ++ RK3576_CLKGATE_CON(54), 4, GFLAGS), ++ GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, ++ RK3576_CLKGATE_CON(54), 5, GFLAGS), ++ GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, ++ RK3576_CLKGATE_CON(54), 6, GFLAGS), ++ GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, ++ RK3576_CLKGATE_CON(54), 7, GFLAGS), ++ GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, ++ RK3576_CLKGATE_CON(54), 8, GFLAGS), ++ COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, ++ RK3576_CLKSEL_CON(130), 7, 2, MFLAGS, ++ RK3576_CLKGATE_CON(54), 10, GFLAGS), ++ GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, ++ RK3576_CLKGATE_CON(54), 11, GFLAGS), ++ COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_aupll_spll_lpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(144), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(61), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(144), 10, 2, MFLAGS, ++ RK3576_CLKGATE_CON(61), 2, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(144), 12, 2, MFLAGS, ++ RK3576_CLKGATE_CON(61), 3, GFLAGS), ++ GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, ++ RK3576_CLKGATE_CON(61), 8, GFLAGS), ++ GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0, ++ RK3576_CLKGATE_CON(61), 9, GFLAGS), ++ COMPOSITE(DCLK_VP0_SRC, "dclk_vp0_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT, ++ RK3576_CLKSEL_CON(145), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(61), 10, GFLAGS), ++ COMPOSITE(DCLK_VP1_SRC, "dclk_vp1_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT, ++ RK3576_CLKSEL_CON(146), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(61), 11, GFLAGS), ++ COMPOSITE(DCLK_VP2_SRC, "dclk_vp2_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT, ++ RK3576_CLKSEL_CON(147), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(61), 12, GFLAGS), ++ COMPOSITE_NODIV(DCLK_VP0, "dclk_vp0", dclk_vp0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3576_CLKSEL_CON(147), 11, 1, MFLAGS, ++ RK3576_CLKGATE_CON(61), 13, GFLAGS), ++ COMPOSITE_NODIV(DCLK_VP1, "dclk_vp1", dclk_vp1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3576_CLKSEL_CON(147), 12, 1, MFLAGS, ++ RK3576_CLKGATE_CON(62), 0, GFLAGS), ++ COMPOSITE_NODIV(DCLK_VP2, "dclk_vp2", dclk_vp2_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3576_CLKSEL_CON(147), 13, 1, MFLAGS, ++ RK3576_CLKGATE_CON(62), 1, GFLAGS), ++ ++ /* vo0 */ ++ COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_lpll_bpll_p, 0, ++ RK3576_CLKSEL_CON(149), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(63), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(149), 7, 2, MFLAGS, ++ RK3576_CLKGATE_CON(63), 1, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_150m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(149), 11, 2, MFLAGS, ++ RK3576_CLKGATE_CON(63), 3, GFLAGS), ++ GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(63), 12, GFLAGS), ++ GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(63), 13, GFLAGS), ++ GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(63), 14, GFLAGS), ++ GATE(CLK_TRNG0_SKP, "clk_trng0_skp", "aclk_hdcp0", 0, ++ RK3576_CLKGATE_CON(64), 4, GFLAGS), ++ GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(64), 5, GFLAGS), ++ COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_spll_vpll_bpll_lpll_p, 0, ++ RK3576_CLKSEL_CON(151), 7, 3, MFLAGS, 0, 7, DFLAGS, ++ RK3576_CLKGATE_CON(64), 6, GFLAGS), ++ GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(64), 7, GFLAGS), ++ COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(151), 15, 1, MFLAGS, 10, 5, DFLAGS, ++ RK3576_CLKGATE_CON(64), 8, GFLAGS), ++ GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(64), 9, GFLAGS), ++ GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(64), 13, GFLAGS), ++ GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, ++ RK3576_CLKGATE_CON(64), 14, GFLAGS), ++ COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(152), 1, 2, MFLAGS, ++ RK3576_CLKGATE_CON(64), 15, GFLAGS), ++ COMPOSITE(MCLK_SAI5_8CH_SRC, "mclk_sai5_8ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(154), 10, 3, MFLAGS, 2, 8, DFLAGS, ++ RK3576_CLKGATE_CON(65), 3, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI5_8CH, "mclk_sai5_8ch", mclk_sai5_8ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(154), 13, 1, MFLAGS, ++ RK3576_CLKGATE_CON(65), 4, GFLAGS), ++ GATE(HCLK_SAI5_8CH, "hclk_sai5_8ch", "hclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(65), 5, GFLAGS), ++ COMPOSITE(MCLK_SAI6_8CH_SRC, "mclk_sai6_8ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(155), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(65), 7, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI6_8CH, "mclk_sai6_8ch", mclk_sai6_8ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(155), 11, 1, MFLAGS, ++ RK3576_CLKGATE_CON(65), 8, GFLAGS), ++ GATE(HCLK_SAI6_8CH, "hclk_sai6_8ch", "hclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(65), 9, GFLAGS), ++ GATE(HCLK_SPDIF_TX2, "hclk_spdif_tx2", "hclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(65), 10, GFLAGS), ++ COMPOSITE(MCLK_SPDIF_TX2, "mclk_spdif_tx2", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(156), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(65), 13, GFLAGS), ++ GATE(HCLK_SPDIF_RX2, "hclk_spdif_rx2", "hclk_vo0_root", 0, ++ RK3576_CLKGATE_CON(65), 14, GFLAGS), ++ COMPOSITE(MCLK_SPDIF_RX2, "mclk_spdif_rx2", gpll_cpll_aupll_p, 0, ++ RK3576_CLKSEL_CON(156), 13, 2, MFLAGS, 8, 5, DFLAGS, ++ RK3576_CLKGATE_CON(65), 15, GFLAGS), ++ ++ /* vo1 */ ++ COMPOSITE(ACLK_VO1_ROOT, "aclk_vo1_root", gpll_cpll_lpll_bpll_p, 0, ++ RK3576_CLKSEL_CON(158), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(67), 1, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(158), 7, 2, MFLAGS, ++ RK3576_CLKGATE_CON(67), 2, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(158), 9, 2, MFLAGS, ++ RK3576_CLKGATE_CON(67), 3, GFLAGS), ++ COMPOSITE(MCLK_SAI8_8CH_SRC, "mclk_sai8_8ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(157), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(66), 1, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI8_8CH, "mclk_sai8_8ch", mclk_sai8_8ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(157), 11, 1, MFLAGS, ++ RK3576_CLKGATE_CON(66), 2, GFLAGS), ++ GATE(HCLK_SAI8_8CH, "hclk_sai8_8ch", "hclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(66), 0, GFLAGS), ++ COMPOSITE(MCLK_SAI7_8CH_SRC, "mclk_sai7_8ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(159), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(67), 8, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI7_8CH, "mclk_sai7_8ch", mclk_sai7_8ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(159), 11, 1, MFLAGS, ++ RK3576_CLKGATE_CON(67), 9, GFLAGS), ++ GATE(HCLK_SAI7_8CH, "hclk_sai7_8ch", "hclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(67), 10, GFLAGS), ++ GATE(HCLK_SPDIF_TX3, "hclk_spdif_tx3", "hclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(67), 11, GFLAGS), ++ GATE(HCLK_SPDIF_TX4, "hclk_spdif_tx4", "hclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(67), 12, GFLAGS), ++ GATE(HCLK_SPDIF_TX5, "hclk_spdif_tx5", "hclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(67), 13, GFLAGS), ++ COMPOSITE(MCLK_SPDIF_TX3, "mclk_spdif_tx3", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(160), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(67), 14, GFLAGS), ++ COMPOSITE_NOMUX(CLK_AUX16MHZ_0, "clk_aux16mhz_0", "gpll", 0, ++ RK3576_CLKSEL_CON(161), 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(67), 15, GFLAGS), ++ GATE(ACLK_DP0, "aclk_dp0", "aclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(68), 0, GFLAGS), ++ GATE(PCLK_DP0, "pclk_dp0", "pclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(68), 1, GFLAGS), ++ GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(68), 4, GFLAGS), ++ GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(68), 5, GFLAGS), ++ GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(68), 6, GFLAGS), ++ GATE(CLK_TRNG1_SKP, "clk_trng1_skp", "aclk_hdcp1", 0, ++ RK3576_CLKGATE_CON(68), 7, GFLAGS), ++ GATE(HCLK_SAI9_8CH, "hclk_sai9_8ch", "hclk_vo1_root", 0, ++ RK3576_CLKGATE_CON(68), 9, GFLAGS), ++ COMPOSITE(MCLK_SAI9_8CH_SRC, "mclk_sai9_8ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(162), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(68), 10, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI9_8CH, "mclk_sai9_8ch", mclk_sai9_8ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(162), 11, 1, MFLAGS, ++ RK3576_CLKGATE_CON(68), 11, GFLAGS), ++ COMPOSITE(MCLK_SPDIF_TX4, "mclk_spdif_tx4", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(163), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(68), 12, GFLAGS), ++ COMPOSITE(MCLK_SPDIF_TX5, "mclk_spdif_tx5", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(164), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(68), 13, GFLAGS), ++ ++ /* vpu */ ++ COMPOSITE(ACLK_VPU_ROOT, "aclk_vpu_root", gpll_spll_cpll_bpll_lpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(118), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(49), 0, GFLAGS), ++ COMPOSITE_NODIV(ACLK_VPU_MID_ROOT, "aclk_vpu_mid_root", mux_600m_400m_300m_24m_p, 0, ++ RK3576_CLKSEL_CON(118), 8, 2, MFLAGS, ++ RK3576_CLKGATE_CON(49), 1, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(118), 10, 2, MFLAGS, ++ RK3576_CLKGATE_CON(49), 2, GFLAGS), ++ COMPOSITE(ACLK_JPEG_ROOT, "aclk_jpeg_root", gpll_cpll_aupll_spll_p, 0, ++ RK3576_CLKSEL_CON(119), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(49), 3, GFLAGS), ++ COMPOSITE_NODIV(ACLK_VPU_LOW_ROOT, "aclk_vpu_low_root", mux_400m_200m_100m_24m_p, 0, ++ RK3576_CLKSEL_CON(119), 7, 2, MFLAGS, ++ RK3576_CLKGATE_CON(49), 4, GFLAGS), ++ GATE(HCLK_RGA2E_0, "hclk_rga2e_0", "hclk_vpu_root", 0, ++ RK3576_CLKGATE_CON(49), 13, GFLAGS), ++ GATE(ACLK_RGA2E_0, "aclk_rga2e_0", "aclk_vpu_root", 0, ++ RK3576_CLKGATE_CON(49), 14, GFLAGS), ++ COMPOSITE(CLK_CORE_RGA2E_0, "clk_core_rga2e_0", gpll_spll_cpll_bpll_lpll_p, 0, ++ RK3576_CLKSEL_CON(120), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(49), 15, GFLAGS), ++ GATE(ACLK_JPEG, "aclk_jpeg", "aclk_jpeg_root", 0, ++ RK3576_CLKGATE_CON(50), 0, GFLAGS), ++ GATE(HCLK_JPEG, "hclk_jpeg", "hclk_vpu_root", 0, ++ RK3576_CLKGATE_CON(50), 1, GFLAGS), ++ GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vpu_root", 0, ++ RK3576_CLKGATE_CON(50), 2, GFLAGS), ++ GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vpu_mid_root", 0, ++ RK3576_CLKGATE_CON(50), 3, GFLAGS), ++ COMPOSITE(CLK_CORE_VDPP, "clk_core_vdpp", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(120), 13, 1, MFLAGS, 8, 5, DFLAGS, ++ RK3576_CLKGATE_CON(50), 4, GFLAGS), ++ GATE(HCLK_RGA2E_1, "hclk_rga2e_1", "hclk_vpu_root", 0, ++ RK3576_CLKGATE_CON(50), 5, GFLAGS), ++ GATE(ACLK_RGA2E_1, "aclk_rga2e_1", "aclk_vpu_root", 0, ++ RK3576_CLKGATE_CON(50), 6, GFLAGS), ++ COMPOSITE(CLK_CORE_RGA2E_1, "clk_core_rga2e_1", gpll_spll_cpll_bpll_lpll_p, 0, ++ RK3576_CLKSEL_CON(121), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(50), 7, GFLAGS), ++ MUX(0, "dclk_ebc_frac_src_p", gpll_cpll_vpll_aupll_24m_p, 0, ++ RK3576_CLKSEL_CON(123), 0, 3, MFLAGS), ++ COMPOSITE_FRAC(DCLK_EBC_FRAC_SRC, "dclk_ebc_frac_src", "dclk_ebc_frac_src_p", 0, ++ RK3576_CLKSEL_CON(122), 0, ++ RK3576_CLKGATE_CON(50), 9, GFLAGS), ++ GATE(ACLK_EBC, "aclk_ebc", "aclk_vpu_low_root", 0, ++ RK3576_CLKGATE_CON(50), 11, GFLAGS), ++ GATE(HCLK_EBC, "hclk_ebc", "hclk_vpu_root", 0, ++ RK3576_CLKGATE_CON(50), 10, GFLAGS), ++ COMPOSITE(DCLK_EBC, "dclk_ebc", dclk_ebc_p, CLK_SET_RATE_NO_REPARENT, ++ RK3576_CLKSEL_CON(123), 12, 3, MFLAGS, 3, 9, DFLAGS, ++ RK3576_CLKGATE_CON(50), 12, GFLAGS), ++ ++ /* vepu */ ++ COMPOSITE_NODIV(HCLK_VEPU1_ROOT, "hclk_vepu1_root", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(178), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(78), 0, GFLAGS), ++ COMPOSITE(ACLK_VEPU1_ROOT, "aclk_vepu1_root", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(180), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(79), 0, GFLAGS), ++ GATE(HCLK_VEPU1, "hclk_vepu1", "hclk_vepu1_root", 0, ++ RK3576_CLKGATE_CON(79), 3, GFLAGS), ++ GATE(ACLK_VEPU1, "aclk_vepu1", "aclk_vepu1_root", 0, ++ RK3576_CLKGATE_CON(79), 4, GFLAGS), ++ COMPOSITE(CLK_VEPU1_CORE, "clk_vepu1_core", gpll_cpll_spll_lpll_bpll_p, 0, ++ RK3576_CLKSEL_CON(180), 11, 3, MFLAGS, 6, 5, DFLAGS, ++ RK3576_CLKGATE_CON(79), 5, GFLAGS), ++ ++ /* php */ ++ COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(92), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(34), 0, GFLAGS), ++ COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(92), 9, 1, MFLAGS, 4, 5, DFLAGS, ++ RK3576_CLKGATE_CON(34), 7, GFLAGS), ++ GATE(PCLK_PCIE0, "pclk_pcie0", "pclk_php_root", 0, ++ RK3576_CLKGATE_CON(34), 13, GFLAGS), ++ GATE(CLK_PCIE0_AUX, "clk_pcie0_aux", "xin24m", 0, ++ RK3576_CLKGATE_CON(34), 14, GFLAGS), ++ GATE(ACLK_PCIE0_MST, "aclk_pcie0_mst", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(34), 15, GFLAGS), ++ GATE(ACLK_PCIE0_SLV, "aclk_pcie0_slv", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(35), 0, GFLAGS), ++ GATE(ACLK_PCIE0_DBI, "aclk_pcie0_dbi", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(35), 1, GFLAGS), ++ GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(35), 3, GFLAGS), ++ GATE(CLK_REF_USB3OTG1, "clk_ref_usb3otg1", "xin24m", 0, ++ RK3576_CLKGATE_CON(35), 4, GFLAGS), ++ GATE(CLK_SUSPEND_USB3OTG1, "clk_suspend_usb3otg1", "xin24m", 0, ++ RK3576_CLKGATE_CON(35), 5, GFLAGS), ++ GATE(ACLK_MMU0, "aclk_mmu0", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(35), 11, GFLAGS), ++ GATE(ACLK_SLV_MMU0, "aclk_slv_mmu0", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(35), 13, GFLAGS), ++ GATE(ACLK_MMU1, "aclk_mmu1", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(35), 14, GFLAGS), ++ GATE(ACLK_SLV_MMU1, "aclk_slv_mmu1", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(36), 0, GFLAGS), ++ GATE(PCLK_PCIE1, "pclk_pcie1", "pclk_php_root", 0, ++ RK3576_CLKGATE_CON(36), 7, GFLAGS), ++ GATE(CLK_PCIE1_AUX, "clk_pcie1_aux", "xin24m", 0, ++ RK3576_CLKGATE_CON(36), 8, GFLAGS), ++ GATE(ACLK_PCIE1_MST, "aclk_pcie1_mst", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(36), 9, GFLAGS), ++ GATE(ACLK_PCIE1_SLV, "aclk_pcie1_slv", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(36), 10, GFLAGS), ++ GATE(ACLK_PCIE1_DBI, "aclk_pcie1_dbi", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(36), 11, GFLAGS), ++ COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(93), 7, 1, MFLAGS, 0, 7, DFLAGS, ++ RK3576_CLKGATE_CON(37), 0, GFLAGS), ++ COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(93), 15, 1, MFLAGS, 8, 7, DFLAGS, ++ RK3576_CLKGATE_CON(37), 1, GFLAGS), ++ GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", CLK_IS_CRITICAL, ++ RK3576_CLKGATE_CON(37), 2, GFLAGS), ++ GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", CLK_IS_CRITICAL, ++ RK3576_CLKGATE_CON(37), 3, GFLAGS), ++ GATE(ACLK_SATA0, "aclk_sata0", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(37), 4, GFLAGS), ++ GATE(ACLK_SATA1, "aclk_sata1", "aclk_php_root", 0, ++ RK3576_CLKGATE_CON(37), 5, GFLAGS), ++ ++ /* audio */ ++ COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(42), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(7), 1, GFLAGS), ++ GATE(HCLK_ASRC_2CH_0, "hclk_asrc_2ch_0", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(7), 3, GFLAGS), ++ GATE(HCLK_ASRC_2CH_1, "hclk_asrc_2ch_1", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(7), 4, GFLAGS), ++ GATE(HCLK_ASRC_4CH_0, "hclk_asrc_4ch_0", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(7), 5, GFLAGS), ++ GATE(HCLK_ASRC_4CH_1, "hclk_asrc_4ch_1", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(7), 6, GFLAGS), ++ COMPOSITE(CLK_ASRC_2CH_0, "clk_asrc_2ch_0", gpll_cpll_aupll_p, 0, ++ RK3576_CLKSEL_CON(42), 7, 2, MFLAGS, 2, 5, DFLAGS, ++ RK3576_CLKGATE_CON(7), 7, GFLAGS), ++ COMPOSITE(CLK_ASRC_2CH_1, "clk_asrc_2ch_1", gpll_cpll_aupll_p, 0, ++ RK3576_CLKSEL_CON(42), 14, 2, MFLAGS, 9, 5, DFLAGS, ++ RK3576_CLKGATE_CON(7), 8, GFLAGS), ++ COMPOSITE(CLK_ASRC_4CH_0, "clk_asrc_4ch_0", gpll_cpll_aupll_p, 0, ++ RK3576_CLKSEL_CON(43), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(7), 9, GFLAGS), ++ COMPOSITE(CLK_ASRC_4CH_1, "clk_asrc_4ch_1", gpll_cpll_aupll_p, 0, ++ RK3576_CLKSEL_CON(43), 12, 2, MFLAGS, 7, 5, DFLAGS, ++ RK3576_CLKGATE_CON(7), 10, GFLAGS), ++ COMPOSITE(MCLK_SAI0_8CH_SRC, "mclk_sai0_8ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(44), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(7), 11, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI0_8CH, "mclk_sai0_8ch", mclk_sai0_8ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(44), 11, 2, MFLAGS, ++ RK3576_CLKGATE_CON(7), 12, GFLAGS), ++ GATE(HCLK_SAI0_8CH, "hclk_sai0_8ch", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(7), 13, GFLAGS), ++ GATE(HCLK_SPDIF_RX0, "hclk_spdif_rx0", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(7), 14, GFLAGS), ++ COMPOSITE(MCLK_SPDIF_RX0, "mclk_spdif_rx0", gpll_cpll_aupll_p, 0, ++ RK3576_CLKSEL_CON(45), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(7), 15, GFLAGS), ++ GATE(HCLK_SPDIF_RX1, "hclk_spdif_rx1", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(8), 0, GFLAGS), ++ COMPOSITE(MCLK_SPDIF_RX1, "mclk_spdif_rx1", gpll_cpll_aupll_p, 0, ++ RK3576_CLKSEL_CON(45), 12, 2, MFLAGS, 7, 5, DFLAGS, ++ RK3576_CLKGATE_CON(8), 1, GFLAGS), ++ COMPOSITE(MCLK_SAI1_8CH_SRC, "mclk_sai1_8ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(46), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(8), 4, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI1_8CH, "mclk_sai1_8ch", mclk_sai1_8ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(46), 11, 1, MFLAGS, ++ RK3576_CLKGATE_CON(8), 5, GFLAGS), ++ GATE(HCLK_SAI1_8CH, "hclk_sai1_8ch", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(8), 6, GFLAGS), ++ COMPOSITE(MCLK_SAI2_2CH_SRC, "mclk_sai2_2ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(47), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(8), 7, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI2_2CH, "mclk_sai2_2ch", mclk_sai2_2ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(47), 11, 2, MFLAGS, ++ RK3576_CLKGATE_CON(8), 8, GFLAGS), ++ GATE(HCLK_SAI2_2CH, "hclk_sai2_2ch", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(8), 10, GFLAGS), ++ COMPOSITE(MCLK_SAI3_2CH_SRC, "mclk_sai3_2ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(48), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(8), 11, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI3_2CH, "mclk_sai3_2ch", mclk_sai3_2ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(48), 11, 2, MFLAGS, ++ RK3576_CLKGATE_CON(8), 12, GFLAGS), ++ GATE(HCLK_SAI3_2CH, "hclk_sai3_2ch", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(8), 14, GFLAGS), ++ COMPOSITE(MCLK_SAI4_2CH_SRC, "mclk_sai4_2ch_src", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(49), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(8), 15, GFLAGS), ++ COMPOSITE_NODIV(MCLK_SAI4_2CH, "mclk_sai4_2ch", mclk_sai4_2ch_p, CLK_SET_RATE_PARENT, ++ RK3576_CLKSEL_CON(49), 11, 2, MFLAGS, ++ RK3576_CLKGATE_CON(9), 0, GFLAGS), ++ GATE(HCLK_SAI4_2CH, "hclk_sai4_2ch", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(9), 2, GFLAGS), ++ GATE(HCLK_ACDCDIG_DSM, "hclk_acdcdig_dsm", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(9), 3, GFLAGS), ++ GATE(MCLK_ACDCDIG_DSM, "mclk_acdcdig_dsm", "mclk_sai4_2ch", 0, ++ RK3576_CLKGATE_CON(9), 4, GFLAGS), ++ COMPOSITE(CLK_PDM1, "clk_pdm1", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(50), 9, 3, MFLAGS, 0, 9, DFLAGS, ++ RK3576_CLKGATE_CON(9), 5, GFLAGS), ++ GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(9), 7, GFLAGS), ++ GATE(CLK_PDM1_OUT, "clk_pdm1_out", "clk_pdm1", 0, ++ RK3576_CLKGATE_CON(3), 5, GFLAGS), ++ COMPOSITE(MCLK_PDM1, "mclk_pdm1", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(51), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(9), 8, GFLAGS), ++ GATE(HCLK_SPDIF_TX0, "hclk_spdif_tx0", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(9), 9, GFLAGS), ++ COMPOSITE(MCLK_SPDIF_TX0, "mclk_spdif_tx0", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(52), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(9), 10, GFLAGS), ++ GATE(HCLK_SPDIF_TX1, "hclk_spdif_tx1", "hclk_audio_root", 0, ++ RK3576_CLKGATE_CON(9), 11, GFLAGS), ++ COMPOSITE(MCLK_SPDIF_TX1, "mclk_spdif_tx1", audio_frac_int_p, 0, ++ RK3576_CLKSEL_CON(53), 8, 3, MFLAGS, 0, 8, DFLAGS, ++ RK3576_CLKGATE_CON(9), 12, GFLAGS), ++ GATE(CLK_SAI1_MCLKOUT, "clk_sai1_mclkout", "mclk_sai1_8ch", 0, ++ RK3576_CLKGATE_CON(9), 13, GFLAGS), ++ GATE(CLK_SAI2_MCLKOUT, "clk_sai2_mclkout", "mclk_sai2_2ch", 0, ++ RK3576_CLKGATE_CON(9), 14, GFLAGS), ++ GATE(CLK_SAI3_MCLKOUT, "clk_sai3_mclkout", "mclk_sai3_2ch", 0, ++ RK3576_CLKGATE_CON(9), 15, GFLAGS), ++ GATE(CLK_SAI4_MCLKOUT, "clk_sai4_mclkout", "mclk_sai4_2ch", 0, ++ RK3576_CLKGATE_CON(10), 0, GFLAGS), ++ GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0, ++ RK3576_CLKGATE_CON(10), 1, GFLAGS), ++ ++ /* sdgmac */ ++ COMPOSITE_NODIV(HCLK_SDGMAC_ROOT, "hclk_sdgmac_root", mux_200m_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(103), 0, 2, MFLAGS, ++ RK3576_CLKGATE_CON(42), 0, GFLAGS), ++ COMPOSITE(ACLK_SDGMAC_ROOT, "aclk_sdgmac_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(103), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3576_CLKGATE_CON(42), 1, GFLAGS), ++ COMPOSITE_NODIV(PCLK_SDGMAC_ROOT, "pclk_sdgmac_root", mux_100m_50m_24m_p, 0, ++ RK3576_CLKSEL_CON(103), 8, 2, MFLAGS, ++ RK3576_CLKGATE_CON(42), 2, GFLAGS), ++ GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(42), 7, GFLAGS), ++ GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(42), 8, GFLAGS), ++ GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(42), 9, GFLAGS), ++ GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(42), 10, GFLAGS), ++ COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, ++ RK3576_CLKSEL_CON(104), 6, 2, MFLAGS, 0, 6, DFLAGS, ++ RK3576_CLKGATE_CON(42), 11, GFLAGS), ++ GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(42), 12, GFLAGS), ++ COMPOSITE(CLK_GMAC1_PTP_REF_SRC, "clk_gmac1_ptp_ref_src", clk_gmac1_ptp_ref_src_p, 0, ++ RK3576_CLKSEL_CON(104), 13, 2, MFLAGS, 8, 5, DFLAGS, ++ RK3576_CLKGATE_CON(42), 15, GFLAGS), ++ COMPOSITE(CLK_GMAC0_PTP_REF_SRC, "clk_gmac0_ptp_ref_src", clk_gmac0_ptp_ref_src_p, 0, ++ RK3576_CLKSEL_CON(105), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(43), 0, GFLAGS), ++ GATE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", "clk_gmac1_ptp_ref_src", 0, ++ RK3576_CLKGATE_CON(42), 13, GFLAGS), ++ GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_src", 0, ++ RK3576_CLKGATE_CON(42), 14, GFLAGS), ++ COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", gpll_cpll_24m_p, 0, ++ RK3576_CLKSEL_CON(105), 13, 2, MFLAGS, 7, 6, DFLAGS, ++ RK3576_CLKGATE_CON(43), 1, GFLAGS), ++ GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(43), 2, GFLAGS), ++ COMPOSITE(SCLK_FSPI1_X2, "sclk_fspi1_x2", gpll_cpll_24m_p, 0, ++ RK3576_CLKSEL_CON(106), 6, 2, MFLAGS, 0, 6, DFLAGS, ++ RK3576_CLKGATE_CON(43), 3, GFLAGS), ++ GATE(HCLK_FSPI1, "hclk_fspi1", "hclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(43), 4, GFLAGS), ++ COMPOSITE(ACLK_DSMC_ROOT, "aclk_dsmc_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3576_CLKSEL_CON(106), 13, 1, MFLAGS, 8, 5, DFLAGS, ++ RK3576_CLKGATE_CON(43), 5, GFLAGS), ++ GATE(ACLK_DSMC, "aclk_dsmc", "aclk_dsmc_root", 0, ++ RK3576_CLKGATE_CON(43), 7, GFLAGS), ++ GATE(PCLK_DSMC, "pclk_dsmc", "pclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(43), 8, GFLAGS), ++ COMPOSITE(CLK_DSMC_SYS, "clk_dsmc_sys", gpll_cpll_p, 0, ++ RK3576_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(43), 9, GFLAGS), ++ GATE(HCLK_HSGPIO, "hclk_hsgpio", "hclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(43), 10, GFLAGS), ++ COMPOSITE(CLK_HSGPIO_TX, "clk_hsgpio_tx", gpll_cpll_24m_p, 0, ++ RK3576_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, ++ RK3576_CLKGATE_CON(43), 11, GFLAGS), ++ COMPOSITE(CLK_HSGPIO_RX, "clk_hsgpio_rx", gpll_cpll_24m_p, 0, ++ RK3576_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3576_CLKGATE_CON(43), 12, GFLAGS), ++ GATE(ACLK_HSGPIO, "aclk_hsgpio", "aclk_sdgmac_root", 0, ++ RK3576_CLKGATE_CON(43), 13, GFLAGS), ++ ++ /* phpphy */ ++ GATE(PCLK_PHPPHY_ROOT, "pclk_phpphy_root", "pclk_bus_root", CLK_IS_CRITICAL, ++ RK3576_PHP_CLKGATE_CON(0), 2, GFLAGS), ++ GATE(PCLK_PCIE2_COMBOPHY0, "pclk_pcie2_combophy0", "pclk_phpphy_root", 0, ++ RK3576_PHP_CLKGATE_CON(0), 5, GFLAGS), ++ GATE(PCLK_PCIE2_COMBOPHY1, "pclk_pcie2_combophy1", "pclk_phpphy_root", 0, ++ RK3576_PHP_CLKGATE_CON(0), 7, GFLAGS), ++ COMPOSITE_NOMUX(CLK_PCIE_100M_SRC, "clk_pcie_100m_src", "ppll", 0, ++ RK3576_PHP_CLKSEL_CON(0), 2, 5, DFLAGS, ++ RK3576_PHP_CLKGATE_CON(1), 1, GFLAGS), ++ COMPOSITE_NOMUX(CLK_PCIE_100M_NDUTY_SRC, "clk_pcie_100m_nduty_src", "ppll", 0, ++ RK3576_PHP_CLKSEL_CON(0), 7, 5, DFLAGS, ++ RK3576_PHP_CLKGATE_CON(1), 2, GFLAGS), ++ COMPOSITE_NODIV(CLK_REF_PCIE0_PHY, "clk_ref_pcie0_phy", clk_ref_pcie0_phy_p, 0, ++ RK3576_PHP_CLKSEL_CON(0), 12, 2, MFLAGS, ++ RK3576_PHP_CLKGATE_CON(1), 5, GFLAGS), ++ COMPOSITE_NODIV(CLK_REF_PCIE1_PHY, "clk_ref_pcie1_phy", clk_ref_pcie0_phy_p, 0, ++ RK3576_PHP_CLKSEL_CON(0), 14, 2, MFLAGS, ++ RK3576_PHP_CLKGATE_CON(1), 8, GFLAGS), ++ COMPOSITE_NOMUX(CLK_REF_MPHY_26M, "clk_ref_mphy_26m", "ppll", CLK_IS_CRITICAL, ++ RK3576_PHP_CLKSEL_CON(1), 0, 8, DFLAGS, ++ RK3576_PHP_CLKGATE_CON(1), 9, GFLAGS), ++ ++ /* pmu */ ++ GATE(CLK_200M_PMU_SRC, "clk_200m_pmu_src", "clk_gpll_div6", 0, ++ RK3576_PMU_CLKGATE_CON(3), 2, GFLAGS), ++ COMPOSITE_NOMUX(CLK_100M_PMU_SRC, "clk_100m_pmu_src", "cpll", 0, ++ RK3576_PMU_CLKSEL_CON(4), 4, 5, DFLAGS, ++ RK3576_PMU_CLKGATE_CON(3), 3, GFLAGS), ++ FACTOR_GATE(CLK_50M_PMU_SRC, "clk_50m_pmu_src", "clk_100m_pmu_src", 0, 1, 2, ++ RK3576_PMU_CLKGATE_CON(3), 4, GFLAGS), ++ COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", mux_pmu200m_pmu100m_pmu50m_24m_p, CLK_IS_CRITICAL, ++ RK3576_PMU_CLKSEL_CON(4), 0, 2, MFLAGS, ++ RK3576_PMU_CLKGATE_CON(3), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", mux_pmu200m_pmu100m_pmu50m_24m_p, 0, ++ RK3576_PMU_CLKSEL_CON(4), 2, 2, MFLAGS, ++ RK3576_PMU_CLKGATE_CON(3), 1, GFLAGS), ++ COMPOSITE_NODIV(PCLK_PMU0_ROOT, "pclk_pmu0_root", mux_pmu100m_pmu50m_24m_p, 0, ++ RK3576_PMU_CLKSEL_CON(20), 0, 2, MFLAGS, ++ RK3576_PMU_CLKGATE_CON(7), 0, GFLAGS), ++ GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, ++ RK3576_PMU_CLKGATE_CON(7), 3, GFLAGS), ++ GATE(PCLK_PMU1_ROOT, "pclk_pmu1_root", "pclk_pmu0_root", CLK_IS_CRITICAL, ++ RK3576_PMU_CLKGATE_CON(7), 9, GFLAGS), ++ GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu1_root", CLK_IS_CRITICAL, ++ RK3576_PMU_CLKGATE_CON(3), 15, GFLAGS), ++ GATE(CLK_PMU1, "clk_pmu1", "xin24m", CLK_IS_CRITICAL, ++ RK3576_PMU_CLKGATE_CON(4), 2, GFLAGS), ++ GATE(PCLK_PMUPHY_ROOT, "pclk_pmuphy_root", "pclk_pmu1_root", CLK_IS_CRITICAL, ++ RK3576_PMU_CLKGATE_CON(5), 0, GFLAGS), ++ GATE(PCLK_HDPTX_APB, "pclk_hdptx_apb", "pclk_pmuphy_root", 0, ++ RK3576_PMU_CLKGATE_CON(0), 1, GFLAGS), ++ GATE(PCLK_MIPI_DCPHY, "pclk_mipi_dcphy", "pclk_pmuphy_root", 0, ++ RK3576_PMU_CLKGATE_CON(0), 2, GFLAGS), ++ GATE(PCLK_CSIDPHY, "pclk_csidphy", "pclk_pmuphy_root", 0, ++ RK3576_PMU_CLKGATE_CON(0), 8, GFLAGS), ++ GATE(PCLK_USBDPPHY, "pclk_usbdpphy", "pclk_pmuphy_root", 0, ++ RK3576_PMU_CLKGATE_CON(0), 12, GFLAGS), ++ COMPOSITE_NOMUX(CLK_PMUPHY_REF_SRC, "clk_pmuphy_ref_src", "cpll", 0, ++ RK3576_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, ++ RK3576_PMU_CLKGATE_CON(0), 13, GFLAGS), ++ GATE(CLK_USBDP_COMBO_PHY_IMMORTAL, "clk_usbdp_combo_phy_immortal", "xin24m", 0, ++ RK3576_PMU_CLKGATE_CON(0), 15, GFLAGS), ++ GATE(CLK_HDMITXHDP, "clk_hdmitxhdp", "xin24m", 0, ++ RK3576_PMU_CLKGATE_CON(1), 13, GFLAGS), ++ GATE(PCLK_MPHY, "pclk_mphy", "pclk_pmuphy_root", 0, ++ RK3576_PMU_CLKGATE_CON(2), 0, GFLAGS), ++ MUX(CLK_REF_OSC_MPHY, "clk_ref_osc_mphy", clk_ref_osc_mphy_p, 0, ++ RK3576_PMU_CLKSEL_CON(3), 0, 2, MFLAGS), ++ GATE(CLK_REF_UFS_CLKOUT, "clk_ref_ufs_clkout", "clk_ref_osc_mphy", 0, ++ RK3576_PMU_CLKGATE_CON(2), 5, GFLAGS), ++ GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", 0, ++ RK3576_PMU_CLKGATE_CON(3), 12, GFLAGS), ++ COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, 0, ++ RK3576_PMU_CLKSEL_CON(4), 14, 1, MFLAGS, 9, 5, DFLAGS, ++ RK3576_PMU_CLKGATE_CON(3), 14, GFLAGS), ++ GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu1_root", 0, ++ RK3576_PMU_CLKGATE_CON(4), 5, GFLAGS), ++ COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, ++ RK3576_PMU_CLKSEL_CON(4), 15, 1, MFLAGS, ++ RK3576_PMU_CLKGATE_CON(4), 6, GFLAGS), ++ GATE(PCLK_PMUTIMER, "pclk_pmutimer", "pclk_pmu1_root", 0, ++ RK3576_PMU_CLKGATE_CON(4), 7, GFLAGS), ++ COMPOSITE_NODIV(CLK_PMUTIMER_ROOT, "clk_pmutimer_root", mux_pmu100m_24m_32k_p, 0, ++ RK3576_PMU_CLKSEL_CON(5), 0, 2, MFLAGS, ++ RK3576_PMU_CLKGATE_CON(4), 8, GFLAGS), ++ GATE(CLK_PMUTIMER0, "clk_pmutimer0", "clk_pmutimer_root", 0, ++ RK3576_PMU_CLKGATE_CON(4), 9, GFLAGS), ++ GATE(CLK_PMUTIMER1, "clk_pmutimer1", "clk_pmutimer_root", 0, ++ RK3576_PMU_CLKGATE_CON(4), 10, GFLAGS), ++ GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu1_root", 0, ++ RK3576_PMU_CLKGATE_CON(4), 11, GFLAGS), ++ COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", mux_pmu100m_pmu50m_24m_p, 0, ++ RK3576_PMU_CLKSEL_CON(5), 2, 2, MFLAGS, ++ RK3576_PMU_CLKGATE_CON(4), 12, GFLAGS), ++ GATE(CLK_PMU1PWM_OSC, "clk_pmu1pwm_osc", "xin24m", 0, ++ RK3576_PMU_CLKGATE_CON(4), 13, GFLAGS), ++ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu1_root", 0, ++ RK3576_PMU_CLKGATE_CON(5), 1, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_pmu200m_pmu100m_pmu50m_24m_p, 0, ++ RK3576_PMU_CLKSEL_CON(6), 7, 2, MFLAGS, ++ RK3576_PMU_CLKGATE_CON(5), 2, GFLAGS), ++ COMPOSITE_NODIV(SCLK_UART1, "sclk_uart1", uart1_p, 0, ++ RK3576_PMU_CLKSEL_CON(8), 0, 1, MFLAGS, ++ RK3576_PMU_CLKGATE_CON(5), 5, GFLAGS), ++ GATE(PCLK_UART1, "pclk_uart1", "pclk_pmu1_root", 0, ++ RK3576_PMU_CLKGATE_CON(5), 6, GFLAGS), ++ GATE(CLK_PDM0, "clk_pdm0", "clk_pdm0_src_top", 0, ++ RK3576_PMU_CLKGATE_CON(5), 13, GFLAGS), ++ GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, ++ RK3576_PMU_CLKGATE_CON(5), 15, GFLAGS), ++ GATE(MCLK_PDM0, "mclk_pdm0", "mclk_pdm0_src_top", 0, ++ RK3576_PMU_CLKGATE_CON(6), 0, GFLAGS), ++ GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, ++ RK3576_PMU_CLKGATE_CON(6), 1, GFLAGS), ++ GATE(CLK_PDM0_OUT, "clk_pdm0_out", "clk_pdm0", 0, ++ RK3576_PMU_CLKGATE_CON(6), 8, GFLAGS), ++ COMPOSITE(CLK_HPTIMER_SRC, "clk_hptimer_src", cpll_24m_p, CLK_IS_CRITICAL, ++ RK3576_PMU_CLKSEL_CON(11), 6, 1, MFLAGS, 1, 5, DFLAGS, ++ RK3576_PMU_CLKGATE_CON(6), 10, GFLAGS), ++ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, ++ RK3576_PMU_CLKGATE_CON(7), 6, GFLAGS), ++ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, ++ RK3576_PMU_CLKSEL_CON(20), 2, 1, MFLAGS, ++ RK3576_PMU_CLKGATE_CON(7), 7, GFLAGS), ++ GATE(CLK_OSC0_PMU1, "clk_osc0_pmu1", "xin24m", CLK_IS_CRITICAL, ++ RK3576_PMU_CLKGATE_CON(7), 8, GFLAGS), ++ GATE(CLK_PMU1PWM_RC, "clk_pmu1pwm_rc", "clk_pvtm_clkout", 0, ++ RK3576_PMU_CLKGATE_CON(5), 7, GFLAGS), ++ ++ /* phy ref */ ++ MUXGRF(CLK_PHY_REF_SRC, "clk_phy_ref_src", clk_phy_ref_src_p, 0, ++ RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS), ++ MUXGRF(CLK_USBPHY_REF_SRC, "clk_usbphy_ref_src", clk_usbphy_ref_src_p, 0, ++ RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS), ++ MUXGRF(CLK_CPLL_REF_SRC, "clk_cpll_ref_src", clk_cpll_ref_src_p, 0, ++ RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS), ++ MUXGRF(CLK_AUPLL_REF_SRC, "clk_aupll_ref_src", clk_aupll_ref_src_p, 0, ++ RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS), ++ ++ /* secure ns */ ++ COMPOSITE_NODIV(ACLK_SECURE_NS, "aclk_secure_ns", mux_350m_175m_116m_24m_p, CLK_IS_CRITICAL, ++ RK3576_SECURE_NS_CLKSEL_CON(0), 0, 2, MFLAGS, ++ RK3576_SECURE_NS_CLKGATE_CON(0), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_SECURE_NS, "hclk_secure_ns", mux_175m_116m_58m_24m_p, CLK_IS_CRITICAL, ++ RK3576_SECURE_NS_CLKSEL_CON(0), 2, 2, MFLAGS, ++ RK3576_SECURE_NS_CLKGATE_CON(0), 1, GFLAGS), ++ COMPOSITE_NODIV(PCLK_SECURE_NS, "pclk_secure_ns", mux_116m_58m_24m_p, CLK_IS_CRITICAL, ++ RK3576_SECURE_NS_CLKSEL_CON(0), 4, 2, MFLAGS, ++ RK3576_SECURE_NS_CLKGATE_CON(0), 2, GFLAGS), ++ GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_ns", 0, ++ RK3576_SECURE_NS_CLKGATE_CON(0), 3, GFLAGS), ++ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_secure_ns", 0, ++ RK3576_SECURE_NS_CLKGATE_CON(0), 8, GFLAGS), ++ GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, ++ RK3576_SECURE_NS_CLKGATE_CON(0), 9, GFLAGS), ++ GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_s", 0, ++ RK3576_NON_SECURE_GATING_CON00, 14, GFLAGS), ++ GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_s", 0, ++ RK3576_NON_SECURE_GATING_CON00, 13, GFLAGS), ++ GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto_s", 0, ++ RK3576_NON_SECURE_GATING_CON00, 1, GFLAGS), ++ ++ /* io */ ++ GATE(CLK_VICAP_I0CLK, "clk_vicap_i0clk", "clk_csihost0_clkdata_i", 0, ++ RK3576_CLKGATE_CON(59), 1, GFLAGS), ++ GATE(CLK_VICAP_I1CLK, "clk_vicap_i1clk", "clk_csihost1_clkdata_i", 0, ++ RK3576_CLKGATE_CON(59), 2, GFLAGS), ++ GATE(CLK_VICAP_I2CLK, "clk_vicap_i2clk", "clk_csihost2_clkdata_i", 0, ++ RK3576_CLKGATE_CON(59), 3, GFLAGS), ++ GATE(CLK_VICAP_I3CLK, "clk_vicap_i3clk", "clk_csihost3_clkdata_i", 0, ++ RK3576_CLKGATE_CON(59), 4, GFLAGS), ++ GATE(CLK_VICAP_I4CLK, "clk_vicap_i4clk", "clk_csihost4_clkdata_i", 0, ++ RK3576_CLKGATE_CON(59), 5, GFLAGS), ++}; ++ ++static void __init rk3576_clk_init(struct device_node *np) ++{ ++ struct rockchip_clk_provider *ctx; ++ unsigned long clk_nr_clks; ++ void __iomem *reg_base; ++ struct regmap *grf; ++ ++ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches, ++ ARRAY_SIZE(rk3576_clk_branches)) + 1; ++ ++ grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf"); ++ if (IS_ERR(grf)) { ++ pr_err("%s: could not get PMU0 GRF syscon\n", __func__); ++ return; ++ } ++ ++ reg_base = of_iomap(np, 0); ++ if (!reg_base) { ++ pr_err("%s: could not map cru region\n", __func__); ++ return; ++ } ++ ++ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); ++ if (IS_ERR(ctx)) { ++ pr_err("%s: rockchip clk init failed\n", __func__); ++ iounmap(reg_base); ++ return; ++ } ++ ++ ctx->grf = grf; ++ ++ rockchip_clk_register_plls(ctx, rk3576_pll_clks, ++ ARRAY_SIZE(rk3576_pll_clks), ++ RK3576_GRF_SOC_STATUS0); ++ ++ rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", ++ mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), ++ &rk3576_cpulclk_data, rk3576_cpulclk_rates, ++ ARRAY_SIZE(rk3576_cpulclk_rates)); ++ rockchip_clk_register_armclk(ctx, ARMCLK_B, "armclk_b", ++ mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), ++ &rk3576_cpubclk_data, rk3576_cpubclk_rates, ++ ARRAY_SIZE(rk3576_cpubclk_rates)); ++ ++ rockchip_clk_register_branches(ctx, rk3576_clk_branches, ++ ARRAY_SIZE(rk3576_clk_branches)); ++ ++ rk3576_rst_init(np, reg_base); ++ ++ rockchip_register_restart_notifier(ctx, RK3576_GLB_SRST_FST, NULL); ++ ++ rockchip_clk_of_add_provider(np, ctx); ++} ++ ++CLK_OF_DECLARE(rk3576_cru, "rockchip,rk3576-cru", rk3576_clk_init); ++ ++struct clk_rk3576_inits { ++ void (*inits)(struct device_node *np); ++}; ++ ++static const struct clk_rk3576_inits clk_rk3576_cru_init = { ++ .inits = rk3576_clk_init, ++}; ++ ++static const struct of_device_id clk_rk3576_match_table[] = { ++ { ++ .compatible = "rockchip,rk3576-cru", ++ .data = &clk_rk3576_cru_init, ++ }, ++ { } ++}; ++ ++static int clk_rk3576_probe(struct platform_device *pdev) ++{ ++ const struct clk_rk3576_inits *init_data; ++ struct device *dev = &pdev->dev; ++ ++ init_data = device_get_match_data(dev); ++ if (!init_data) ++ return -EINVAL; ++ ++ if (init_data->inits) ++ init_data->inits(dev->of_node); ++ ++ return 0; ++} ++ ++static struct platform_driver clk_rk3576_driver = { ++ .probe = clk_rk3576_probe, ++ .driver = { ++ .name = "clk-rk3576", ++ .of_match_table = clk_rk3576_match_table, ++ .suppress_bind_attrs = true, ++ }, ++}; ++builtin_platform_driver_probe(clk_rk3576_driver, clk_rk3576_probe); +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -235,6 +235,58 @@ struct clk; + #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) + #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) + ++#define RK3576_PHP_CRU_BASE 0x8000 ++#define RK3576_SECURE_NS_CRU_BASE 0x10000 ++#define RK3576_PMU_CRU_BASE 0x20000 ++#define RK3576_BIGCORE_CRU_BASE 0x38000 ++#define RK3576_LITCORE_CRU_BASE 0x40000 ++#define RK3576_CCI_CRU_BASE 0x48000 ++ ++#define RK3576_PLL_CON(x) RK2928_PLL_CON(x) ++#define RK3576_MODE_CON0 0x280 ++#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) ++#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) ++#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) ++#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) ++#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) ++#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) ++#define RK3576_GLB_CNT_TH 0xc00 ++#define RK3576_GLB_SRST_FST 0xc08 ++#define RK3576_GLB_SRST_SND 0xc0c ++#define RK3576_GLB_RST_CON 0xc10 ++#define RK3576_GLB_RST_ST 0xc04 ++#define RK3576_SDIO_CON0 0xC24 ++#define RK3576_SDIO_CON1 0xC28 ++#define RK3576_SDMMC_CON0 0xC30 ++#define RK3576_SDMMC_CON1 0xC34 ++ ++#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300) ++#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800) ++#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00) ++ ++#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) ++#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300) ++#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800) ++#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00) ++ ++#define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300) ++#define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800) ++#define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00) ++ ++#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300) ++#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800) ++#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00) ++ ++#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) ++#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300) ++#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800) ++#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00) ++#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) ++#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300) ++#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800) ++#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00) ++#define RK3576_NON_SECURE_GATING_CON00 0xc48 ++ + #define RK3588_PHP_CRU_BASE 0x8000 + #define RK3588_PMU_CRU_BASE 0x30000 + #define RK3588_BIGCORE0_CRU_BASE 0x50000 +@@ -1026,6 +1078,7 @@ static inline void rockchip_register_sof + return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); + } + ++void rk3576_rst_init(struct device_node *np, void __iomem *reg_base); + void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); + + #endif +--- /dev/null ++++ b/drivers/clk/rockchip/rst-rk3576.c +@@ -0,0 +1,651 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2024 Collabora Ltd. ++ * Author: Detlev Casanova ++ * Based on Sebastien Reichel's implementation for RK3588 ++ */ ++ ++#include ++#include ++#include ++#include "clk.h" ++ ++/* 0x27200000 + 0x0A00 */ ++#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) ++/* 0x27208000 + 0x0A00 */ ++#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) ++/* 0x27210000 + 0x0A00 */ ++#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) ++/* 0x27220000 + 0x0A00 */ ++#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) ++ ++/* mapping table for reset ID to register offset */ ++static const int rk3576_register_offset[] = { ++ /* SOFTRST_CON01 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14), ++ ++ /* SOFTRST_CON02 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1), ++ ++ /* SOFTRST_CON06 */ ++ RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2), ++ ++ /* SOFTRST_CON07 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15), ++ ++ /* SOFTRST_CON08 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14), ++ ++ /* SOFTRST_CON09 */ ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12), ++ ++ /* SOFTRST_CON11 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15), ++ ++ /* SOFTRST_CON12 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15), ++ ++ /* SOFTRST_CON13 */ ++ RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15), ++ ++ /* SOFTRST_CON14 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15), ++ ++ /* SOFTRST_CON15 */ ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15), ++ ++ /* SOFTRST_CON16 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11), ++ ++ /* SOFTRST_CON17 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15), ++ ++ /* SOFTRST_CON18 */ ++ RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15), ++ ++ /* SOFTRST_CON19 */ ++ RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13), ++ ++ /* SOFTRST_CON20 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13), ++ ++ /* SOFTRST_CON21 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15), ++ ++ /* SOFTRST_CON22 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15), ++ ++ /* SOFTRST_CON23 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11), ++ ++ /* SOFTRST_CON25 */ ++ RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6), ++ ++ /* SOFTRST_CON26 */ ++ RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6), ++ ++ /* SOFTRST_CON27 */ ++ RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1), ++ ++ /* SOFTRST_CON28 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12), ++ ++ /* SOFTRST_CON29 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3), ++ ++ /* SOFTRST_CON31 */ ++ RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15), ++ ++ /* SOFTRST_CON32 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13), ++ ++ /* SOFTRST_CON33 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12), ++ ++ /* SOFTRST_CON34 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15), ++ ++ /* SOFTRST_CON35 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14), ++ ++ /* SOFTRST_CON36 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9), ++ ++ /* SOFTRST_CON37 */ ++ RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7), ++ ++ /* SOFTRST_CON40 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3), ++ ++ /* SOFTRST_CON42 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12), ++ ++ /* SOFTRST_CON43 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13), ++ ++ /* SOFTRST_CON45 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9), ++ ++ /* SOFTRST_CON47 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15), ++ ++ /* SOFTRST_CON48 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2), ++ ++ /* SOFTRST_CON49 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15), ++ ++ /* SOFTRST_CON50 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12), ++ ++ /* SOFTRST_CON51 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6), ++ ++ /* SOFTRST_CON53 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11), ++ ++ /* SOFTRST_CON54 */ ++ RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8), ++ ++ /* SOFTRST_CON59 */ ++ RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5), ++ ++ /* SOFTRST_CON61 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13), ++ ++ /* SOFTRST_CON62 */ ++ RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3), ++ ++ /* SOFTRST_CON63 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14), ++ ++ /* SOFTRST_CON64 */ ++ RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14), ++ ++ /* SOFTRST_CON65 */ ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15), ++ ++ /* SOFTRST_CON66 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2), ++ ++ /* SOFTRST_CON67 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14), ++ ++ /* SOFTRST_CON68 */ ++ RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0), ++ RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12), ++ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13), ++ ++ /* SOFTRST_CON69 */ ++ RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13), ++ RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14), ++ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15), ++ ++ /* SOFTRST_CON72 */ ++ RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6), ++ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7), ++ RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8), ++ RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9), ++ RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10), ++ RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11), ++ RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12), ++ ++ /* SOFTRST_CON75 */ ++ RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1), ++ ++ /* SOFTRST_CON78 */ ++ RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4), ++ ++ /* SOFTRST_CON79 */ ++ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2), ++ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3), ++ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4), ++ RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5), ++ ++ /* PPLL_SOFTRST_CON00 */ ++ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1), ++ RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3), ++ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5), ++ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6), ++ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7), ++ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8), ++ ++ /* PPLL_SOFTRST_CON01 */ ++ RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5), ++ RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8), ++ ++ /* SECURENS_SOFTRST_CON00 */ ++ RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3), ++ RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4), ++ RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8), ++ RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9), ++ ++ /* PMU1_SOFTRST_CON00 */ ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15), ++ ++ /* PMU1_SOFTRST_CON01 */ ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13), ++ ++ /* PMU1_SOFTRST_CON02 */ ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3), ++ ++ /* PMU1_SOFTRST_CON03 */ ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13), ++ ++ /* PMU1_SOFTRST_CON04 */ ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12), ++ ++ /* PMU1_SOFTRST_CON05 */ ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15), ++ ++ /* PMU1_SOFTRST_CON06 */ ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1), ++ ++ /* PMU1_SOFTRST_CON07 */ ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6), ++ RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7), ++}; ++ ++void rk3576_rst_init(struct device_node *np, void __iomem *reg_base) ++{ ++ rockchip_register_softrst_lut(np, ++ rk3576_register_offset, ++ ARRAY_SIZE(rk3576_register_offset), ++ reg_base + RK3576_SOFTRST_CON(0), ++ ROCKCHIP_SOFTRST_HIWORD_MASK); ++} diff --git a/target/linux/rockchip/patches-6.6/030-14-v6.12-dt-bindings-clock-reset-fix-top-comment-indentation-rk357.patch b/target/linux/rockchip/patches-6.6/030-14-v6.12-dt-bindings-clock-reset-fix-top-comment-indentation-rk357.patch new file mode 100644 index 000000000..96ec2af60 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-14-v6.12-dt-bindings-clock-reset-fix-top-comment-indentation-rk357.patch @@ -0,0 +1,58 @@ +From eb3b3f520518003cd363239fc160bdd7ed327319 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 10 Sep 2024 00:31:49 +0200 +Subject: [PATCH] dt-bindings: clock, reset: fix top-comment indentation rk3576 + headers + +Block comments should align the * on each line, as checkpatch rightfully +pointed out, so fix that style issue on the newly added rk3576 headers. + +Fixes: 49c04453db81 ("dt-bindings: clock, reset: Add support for rk3576") +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20240909223149.85364-1-heiko@sntech.de +Signed-off-by: Stephen Boyd +--- + include/dt-bindings/clock/rockchip,rk3576-cru.h | 12 ++++++------ + include/dt-bindings/reset/rockchip,rk3576-cru.h | 12 ++++++------ + 2 files changed, 12 insertions(+), 12 deletions(-) + +--- a/include/dt-bindings/clock/rockchip,rk3576-cru.h ++++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h +@@ -1,11 +1,11 @@ + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + /* +-* Copyright (c) 2023 Rockchip Electronics Co. Ltd. +-* Copyright (c) 2024 Collabora Ltd. +-* +-* Author: Elaine Zhang +-* Author: Detlev Casanova +-*/ ++ * Copyright (c) 2023 Rockchip Electronics Co. Ltd. ++ * Copyright (c) 2024 Collabora Ltd. ++ * ++ * Author: Elaine Zhang ++ * Author: Detlev Casanova ++ */ + + #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H + #define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H +--- a/include/dt-bindings/reset/rockchip,rk3576-cru.h ++++ b/include/dt-bindings/reset/rockchip,rk3576-cru.h +@@ -1,11 +1,11 @@ + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + /* +-* Copyright (c) 2023 Rockchip Electronics Co. Ltd. +-* Copyright (c) 2024 Collabora Ltd. +-* +-* Author: Elaine Zhang +-* Author: Detlev Casanova +-*/ ++ * Copyright (c) 2023 Rockchip Electronics Co. Ltd. ++ * Copyright (c) 2024 Collabora Ltd. ++ * ++ * Author: Elaine Zhang ++ * Author: Detlev Casanova ++ */ + + #ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H + #define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H diff --git a/target/linux/rockchip/patches-6.6/035-v6.12-clk-rockchip-fix-finding-of-maximum-clock-ID.patch b/target/linux/rockchip/patches-6.6/030-15-v6.12-clk-rockchip-fix-finding-of-maximum-clock-ID.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/035-v6.12-clk-rockchip-fix-finding-of-maximum-clock-ID.patch rename to target/linux/rockchip/patches-6.6/030-15-v6.12-clk-rockchip-fix-finding-of-maximum-clock-ID.patch diff --git a/target/linux/rockchip/patches-6.6/031-03-v6.12-dt-bindings-power-Add-support-for-RK3576-SoC.patch b/target/linux/rockchip/patches-6.6/031-03-v6.12-dt-bindings-power-Add-support-for-RK3576-SoC.patch new file mode 100644 index 000000000..5f4e81616 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/031-03-v6.12-dt-bindings-power-Add-support-for-RK3576-SoC.patch @@ -0,0 +1,63 @@ +From 77c5e7b623032502ee49fe7e7868eaca6786d7ed Mon Sep 17 00:00:00 2001 +From: Finley Xiao +Date: Wed, 14 Aug 2024 18:26:41 -0400 +Subject: [PATCH] dt-bindings: power: Add support for RK3576 SoC + +Define power domain IDs as described in the TRM and add compatible for +rockchip,rk3576-power-controller + +Signed-off-by: Finley Xiao +Co-Developed-by: Detlev Casanova +Signed-off-by: Detlev Casanova +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20240814222824.3170-2-detlev.casanova@collabora.com +Signed-off-by: Ulf Hansson +--- + .../power/rockchip,power-controller.yaml | 1 + + .../dt-bindings/power/rockchip,rk3576-power.h | 30 +++++++++++++++++++ + 2 files changed, 31 insertions(+) + create mode 100644 include/dt-bindings/power/rockchip,rk3576-power.h + +--- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml ++++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +@@ -41,6 +41,7 @@ properties: + - rockchip,rk3368-power-controller + - rockchip,rk3399-power-controller + - rockchip,rk3568-power-controller ++ - rockchip,rk3576-power-controller + - rockchip,rk3588-power-controller + - rockchip,rv1126-power-controller + +--- /dev/null ++++ b/include/dt-bindings/power/rockchip,rk3576-power.h +@@ -0,0 +1,30 @@ ++/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ ++#ifndef __DT_BINDINGS_POWER_RK3576_POWER_H__ ++#define __DT_BINDINGS_POWER_RK3576_POWER_H__ ++ ++/* VD_NPU */ ++#define RK3576_PD_NPU 0 ++#define RK3576_PD_NPUTOP 1 ++#define RK3576_PD_NPU0 2 ++#define RK3576_PD_NPU1 3 ++ ++/* VD_GPU */ ++#define RK3576_PD_GPU 4 ++ ++/* VD_LOGIC */ ++#define RK3576_PD_NVM 5 ++#define RK3576_PD_SDGMAC 6 ++#define RK3576_PD_USB 7 ++#define RK3576_PD_PHP 8 ++#define RK3576_PD_SUBPHP 9 ++#define RK3576_PD_AUDIO 10 ++#define RK3576_PD_VEPU0 11 ++#define RK3576_PD_VEPU1 12 ++#define RK3576_PD_VPU 13 ++#define RK3576_PD_VDEC 14 ++#define RK3576_PD_VI 15 ++#define RK3576_PD_VO0 16 ++#define RK3576_PD_VO1 17 ++#define RK3576_PD_VOP 18 ++ ++#endif diff --git a/target/linux/rockchip/patches-6.6/031-04-v6.12-pmdomain-rockchip-Add-support-for-RK3576-SoC.patch b/target/linux/rockchip/patches-6.6/031-04-v6.12-pmdomain-rockchip-Add-support-for-RK3576-SoC.patch new file mode 100644 index 000000000..cc4455691 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/031-04-v6.12-pmdomain-rockchip-Add-support-for-RK3576-SoC.patch @@ -0,0 +1,98 @@ +From cfee1b50775869de9076d021ea11a8438854dcba Mon Sep 17 00:00:00 2001 +From: Finley Xiao +Date: Wed, 14 Aug 2024 18:26:42 -0400 +Subject: [PATCH] pmdomain: rockchip: Add support for RK3576 SoC + +Add configuration for RK3576 SoC and list the power domains. + +Signed-off-by: Finley Xiao +Signed-off-by: Detlev Casanova +Reviewed-by: Elaine Zhang +Link: https://lore.kernel.org/r/20240814222824.3170-3-detlev.casanova@collabora.com +Signed-off-by: Ulf Hansson +--- + drivers/pmdomain/rockchip/pm-domains.c | 45 ++++++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +--- a/drivers/pmdomain/rockchip/pm-domains.c ++++ b/drivers/pmdomain/rockchip/pm-domains.c +@@ -31,6 +31,7 @@ + #include + #include + #include ++#include + #include + + struct rockchip_domain_info { +@@ -173,6 +174,9 @@ struct rockchip_pmu { + #define DOMAIN_RK3568(name, pwr, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) + ++#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \ ++ DOMAIN_M_O_R(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, wakeup) ++ + /* + * Dynamic Memory Controller may need to coordinate with us -- see + * rockchip_pmu_block(). +@@ -1111,6 +1115,28 @@ static const struct rockchip_domain_info + [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false), + }; + ++static const struct rockchip_domain_info rk3576_pm_domains[] = { ++ [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, false), ++ [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), false), ++ [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), false), ++ [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), false), ++ [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), false), ++ [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, false), ++ [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, false), ++ [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), false), ++ [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), false), ++ [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), true), ++ [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), false), ++ [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), false), ++ [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), false), ++ [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), false), ++ [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), false), ++ [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, false), ++ [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), false), ++ [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), false), ++ [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), false), ++}; ++ + static const struct rockchip_domain_info rk3588_pm_domains[] = { + [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false), + [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false), +@@ -1289,6 +1315,21 @@ static const struct rockchip_pmu_info rk + .domain_info = rk3568_pm_domains, + }; + ++static const struct rockchip_pmu_info rk3576_pmu = { ++ .pwr_offset = 0x210, ++ .status_offset = 0x230, ++ .chain_status_offset = 0x248, ++ .mem_status_offset = 0x250, ++ .mem_pwr_offset = 0x300, ++ .req_offset = 0x110, ++ .idle_offset = 0x128, ++ .ack_offset = 0x120, ++ .repair_status_offset = 0x570, ++ ++ .num_domains = ARRAY_SIZE(rk3576_pm_domains), ++ .domain_info = rk3576_pm_domains, ++}; ++ + static const struct rockchip_pmu_info rk3588_pmu = { + .pwr_offset = 0x14c, + .status_offset = 0x180, +@@ -1365,6 +1406,10 @@ static const struct of_device_id rockchi + .data = (void *)&rk3568_pmu, + }, + { ++ .compatible = "rockchip,rk3576-power-controller", ++ .data = (void *)&rk3576_pmu, ++ }, ++ { + .compatible = "rockchip,rk3588-power-controller", + .data = (void *)&rk3588_pmu, + }, diff --git a/target/linux/rockchip/patches-6.6/031-05-v6.12-pmdomain-rockchip-Add-gating-support.patch b/target/linux/rockchip/patches-6.6/031-05-v6.12-pmdomain-rockchip-Add-gating-support.patch new file mode 100644 index 000000000..44efff35a --- /dev/null +++ b/target/linux/rockchip/patches-6.6/031-05-v6.12-pmdomain-rockchip-Add-gating-support.patch @@ -0,0 +1,80 @@ +From 8b579881de295d49a75f6312547f7813b1551a83 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Thu, 29 Aug 2024 16:20:47 -0400 +Subject: [PATCH] pmdomain: rockchip: Add gating support + +Some rockchip SoC need to ungate power domains before their power status +can be changed. + +Each power domain has a gate mask that is set to 1 to ungate it when +manipulating power status, then set back to 0 to gate it again. + +Signed-off-by: Detlev Casanova +Link: https://lore.kernel.org/r/20240829202732.75961-2-detlev.casanova@collabora.com +Signed-off-by: Ulf Hansson +--- + drivers/pmdomain/rockchip/pm-domains.c | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/drivers/pmdomain/rockchip/pm-domains.c ++++ b/drivers/pmdomain/rockchip/pm-domains.c +@@ -44,6 +44,7 @@ struct rockchip_domain_info { + bool active_wakeup; + int pwr_w_mask; + int req_w_mask; ++ int clk_ungate_mask; + int mem_status_mask; + int repair_status_mask; + u32 pwr_offset; +@@ -61,6 +62,7 @@ struct rockchip_pmu_info { + u32 chain_status_offset; + u32 mem_status_offset; + u32 repair_status_offset; ++ u32 clk_ungate_offset; + + u32 core_pwrcnt_offset; + u32 gpu_pwrcnt_offset; +@@ -301,6 +303,26 @@ static unsigned int rockchip_pmu_read_ac + return val; + } + ++static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate) ++{ ++ const struct rockchip_domain_info *pd_info = pd->info; ++ struct rockchip_pmu *pmu = pd->pmu; ++ unsigned int val; ++ int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16; ++ ++ if (!pd_info->clk_ungate_mask) ++ return 0; ++ ++ if (!pmu->info->clk_ungate_offset) ++ return 0; ++ ++ val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) : ++ clk_ungate_w_mask; ++ regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val); ++ ++ return 0; ++} ++ + static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, + bool idle) + { +@@ -541,6 +563,8 @@ static int rockchip_pd_power(struct rock + return ret; + } + ++ rockchip_pmu_ungate_clk(pd, true); ++ + if (!power_on) { + rockchip_pmu_save_qos(pd); + +@@ -557,6 +581,7 @@ static int rockchip_pd_power(struct rock + rockchip_pmu_restore_qos(pd); + } + ++ rockchip_pmu_ungate_clk(pd, false); + clk_bulk_disable(pd->num_clks, pd->clks); + } + diff --git a/target/linux/rockchip/patches-6.6/031-06-v6.12-pmdomain-rockchip-Add-gating-masks-for-rk3576.patch b/target/linux/rockchip/patches-6.6/031-06-v6.12-pmdomain-rockchip-Add-gating-masks-for-rk3576.patch new file mode 100644 index 000000000..e3a56840a --- /dev/null +++ b/target/linux/rockchip/patches-6.6/031-06-v6.12-pmdomain-rockchip-Add-gating-masks-for-rk3576.patch @@ -0,0 +1,109 @@ +From d030e94d8127d79d941a94211250060431720614 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Thu, 29 Aug 2024 16:20:48 -0400 +Subject: [PATCH] pmdomain: rockchip: Add gating masks for rk3576 + +The RK3576 SoC needs to ungate the power domains before their status can +be modified. + +The values have been taken from the rockchip downstream driver. + +Signed-off-by: Detlev Casanova +Link: https://lore.kernel.org/r/20240829202732.75961-3-detlev.casanova@collabora.com +Signed-off-by: Ulf Hansson +--- + drivers/pmdomain/rockchip/pm-domains.c | 62 +++++++++++++++++--------- + 1 file changed, 41 insertions(+), 21 deletions(-) + +--- a/drivers/pmdomain/rockchip/pm-domains.c ++++ b/drivers/pmdomain/rockchip/pm-domains.c +@@ -145,6 +145,25 @@ struct rockchip_pmu { + .active_wakeup = wakeup, \ + } + ++#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \ ++{ \ ++ .name = _name, \ ++ .pwr_offset = p_offset, \ ++ .pwr_w_mask = (pwr) << 16, \ ++ .pwr_mask = (pwr), \ ++ .status_mask = (status), \ ++ .mem_offset = m_offset, \ ++ .mem_status_mask = (m_status), \ ++ .repair_status_mask = (r_status), \ ++ .req_offset = r_offset, \ ++ .req_w_mask = (req) << 16, \ ++ .req_mask = (req), \ ++ .idle_mask = (idle), \ ++ .clk_ungate_mask = (g_mask), \ ++ .ack_mask = (ack), \ ++ .active_wakeup = wakeup, \ ++} ++ + #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ + { \ + .name = _name, \ +@@ -176,8 +195,8 @@ struct rockchip_pmu { + #define DOMAIN_RK3568(name, pwr, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) + +-#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \ +- DOMAIN_M_O_R(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, wakeup) ++#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \ ++ DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup) + + /* + * Dynamic Memory Controller may need to coordinate with us -- see +@@ -1141,25 +1160,25 @@ static const struct rockchip_domain_info + }; + + static const struct rockchip_domain_info rk3576_pm_domains[] = { +- [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, false), +- [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), false), +- [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), false), +- [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), false), +- [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), false), +- [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, false), +- [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, false), +- [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), false), +- [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), false), +- [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), true), +- [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), false), +- [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), false), +- [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), false), +- [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), false), +- [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), false), +- [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, false), +- [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), false), +- [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), false), +- [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), false), ++ [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, false), ++ [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), false), ++ [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, false), ++ [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), false), ++ [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), false), ++ [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, false), ++ [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false), ++ [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false), ++ [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false), ++ [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true), ++ [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false), ++ [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false), ++ [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false), ++ [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false), ++ [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false), ++ [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false), ++ [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false), ++ [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false), ++ [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false), + }; + + static const struct rockchip_domain_info rk3588_pm_domains[] = { +@@ -1350,6 +1369,7 @@ static const struct rockchip_pmu_info rk + .idle_offset = 0x128, + .ack_offset = 0x120, + .repair_status_offset = 0x570, ++ .clk_ungate_offset = 0x140, + + .num_domains = ARRAY_SIZE(rk3576_pm_domains), + .domain_info = rk3576_pm_domains, diff --git a/target/linux/rockchip/patches-6.6/032-06-v6.13-phy-rockchip-inno-usb2-convert-clock-management-to-bulk.patch b/target/linux/rockchip/patches-6.6/032-06-v6.13-phy-rockchip-inno-usb2-convert-clock-management-to-bulk.patch new file mode 100644 index 000000000..a13320d90 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/032-06-v6.13-phy-rockchip-inno-usb2-convert-clock-management-to-bulk.patch @@ -0,0 +1,119 @@ +From 86e2ed4e9a9680013ec9ab7c0428c9b8c5108efe Mon Sep 17 00:00:00 2001 +From: Frank Wang +Date: Wed, 16 Oct 2024 15:37:10 +0800 +Subject: [PATCH] phy: rockchip: inno-usb2: convert clock management to bulk + +Since some Rockchip SoCs (e.g RK3576) have more than one clock, +this converts the clock management from single to bulk method to +make the driver more flexible. + +Signed-off-by: Frank Wang +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20241016073713.14133-1-frawang.cn@gmail.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 45 +++++++++++++++---- + 1 file changed, 37 insertions(+), 8 deletions(-) + +--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +@@ -225,9 +225,10 @@ struct rockchip_usb2phy_port { + * @dev: pointer to device. + * @grf: General Register Files regmap. + * @usbgrf: USB General Register Files regmap. +- * @clk: clock struct of phy input clk. ++ * @clks: array of phy input clocks. + * @clk480m: clock struct of phy output clk. + * @clk480m_hw: clock struct of phy output clk management. ++ * @num_clks: number of phy input clocks. + * @phy_reset: phy reset control. + * @chg_state: states involved in USB charger detection. + * @chg_type: USB charger types. +@@ -242,9 +243,10 @@ struct rockchip_usb2phy { + struct device *dev; + struct regmap *grf; + struct regmap *usbgrf; +- struct clk *clk; ++ struct clk_bulk_data *clks; + struct clk *clk480m; + struct clk_hw clk480m_hw; ++ int num_clks; + struct reset_control *phy_reset; + enum usb_chg_state chg_state; + enum power_supply_type chg_type; +@@ -306,6 +308,13 @@ static int rockchip_usb2phy_reset(struct + return 0; + } + ++static void rockchip_usb2phy_clk_bulk_disable(void *data) ++{ ++ struct rockchip_usb2phy *rphy = data; ++ ++ clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks); ++} ++ + static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) + { + struct rockchip_usb2phy *rphy = +@@ -372,7 +381,9 @@ rockchip_usb2phy_clk480m_register(struct + { + struct device_node *node = rphy->dev->of_node; + struct clk_init_data init; ++ struct clk *refclk = NULL; + const char *clk_name; ++ int i; + int ret = 0; + + init.flags = 0; +@@ -382,8 +393,15 @@ rockchip_usb2phy_clk480m_register(struct + /* optional override of the clockname */ + of_property_read_string(node, "clock-output-names", &init.name); + +- if (rphy->clk) { +- clk_name = __clk_get_name(rphy->clk); ++ for (i = 0; i < rphy->num_clks; i++) { ++ if (!strncmp(rphy->clks[i].id, "phyclk", 6)) { ++ refclk = rphy->clks[i].clk; ++ break; ++ } ++ } ++ ++ if (!IS_ERR(refclk)) { ++ clk_name = __clk_get_name(refclk); + init.parent_names = &clk_name; + init.num_parents = 1; + } else { +@@ -1385,11 +1403,13 @@ static int rockchip_usb2phy_probe(struct + if (IS_ERR(rphy->phy_reset)) + return PTR_ERR(rphy->phy_reset); + +- rphy->clk = devm_clk_get_optional_enabled(dev, "phyclk"); +- if (IS_ERR(rphy->clk)) { +- return dev_err_probe(&pdev->dev, PTR_ERR(rphy->clk), +- "failed to get phyclk\n"); +- } ++ ret = devm_clk_bulk_get_all(dev, &rphy->clks); ++ if (ret == -EPROBE_DEFER) ++ return dev_err_probe(&pdev->dev, -EPROBE_DEFER, ++ "failed to get phy clock\n"); ++ ++ /* Clocks are optional */ ++ rphy->num_clks = ret < 0 ? 0 : ret; + + ret = rockchip_usb2phy_clk480m_register(rphy); + if (ret) { +@@ -1397,6 +1417,14 @@ static int rockchip_usb2phy_probe(struct + return ret; + } + ++ ret = clk_bulk_prepare_enable(rphy->num_clks, rphy->clks); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to enable phy clock\n"); ++ ++ ret = devm_add_action_or_reset(dev, rockchip_usb2phy_clk_bulk_disable, rphy); ++ if (ret) ++ return ret; ++ + if (rphy->phy_cfg->phy_tuning) { + ret = rphy->phy_cfg->phy_tuning(rphy); + if (ret) diff --git a/target/linux/rockchip/patches-6.6/032-07-v6.13-phy-rockchip-inno-usb2-Add-usb2-phys-support-for-rk3576.patch b/target/linux/rockchip/patches-6.6/032-07-v6.13-phy-rockchip-inno-usb2-Add-usb2-phys-support-for-rk3576.patch new file mode 100644 index 000000000..74ea98ae6 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/032-07-v6.13-phy-rockchip-inno-usb2-Add-usb2-phys-support-for-rk3576.patch @@ -0,0 +1,143 @@ +From 3d7de6e870ece5a32153382df9df6fb87613335e Mon Sep 17 00:00:00 2001 +From: William Wu +Date: Wed, 16 Oct 2024 15:37:13 +0800 +Subject: [PATCH] phy: rockchip: inno-usb2: Add usb2 phys support for rk3576 + +The RK3576 SoC has two independent USB2.0 PHYs, and each PHY has +one port. This adds device specific data for it. + +Signed-off-by: William Wu +Signed-off-by: Frank Wang +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20241016073713.14133-4-frawang.cn@gmail.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 103 ++++++++++++++++++ + 1 file changed, 103 insertions(+) + +--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +@@ -1494,6 +1494,30 @@ put_child: + return ret; + } + ++static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy) ++{ ++ int ret; ++ u32 reg = rphy->phy_cfg->reg; ++ ++ /* Deassert SIDDQ to power on analog block */ ++ ret = regmap_write(rphy->grf, reg + 0x0010, GENMASK(29, 29) | 0x0000); ++ if (ret) ++ return ret; ++ ++ /* Do reset after exit IDDQ mode */ ++ ret = rockchip_usb2phy_reset(rphy); ++ if (ret) ++ return ret; ++ ++ /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ ++ ret |= regmap_write(rphy->grf, reg + 0x000c, GENMASK(27, 24) | 0x0900); ++ ++ /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ ++ ret |= regmap_write(rphy->grf, reg + 0x0010, GENMASK(20, 19) | 0x0010); ++ ++ return ret; ++} ++ + static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) + { + int ret; +@@ -1856,6 +1880,84 @@ static const struct rockchip_usb2phy_cfg + { /* sentinel */ } + }; + ++static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = { ++ { ++ .reg = 0x0, ++ .num_ports = 1, ++ .phy_tuning = rk3576_usb2phy_tuning, ++ .clkout_ctl = { 0x0008, 0, 0, 1, 0 }, ++ .port_cfgs = { ++ [USB2PHY_PORT_OTG] = { ++ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, ++ .bvalid_det_en = { 0x00c0, 1, 1, 0, 1 }, ++ .bvalid_det_st = { 0x00c4, 1, 1, 0, 1 }, ++ .bvalid_det_clr = { 0x00c8, 1, 1, 0, 1 }, ++ .ls_det_en = { 0x00c0, 0, 0, 0, 1 }, ++ .ls_det_st = { 0x00c4, 0, 0, 0, 1 }, ++ .ls_det_clr = { 0x00c8, 0, 0, 0, 1 }, ++ .disfall_en = { 0x00c0, 6, 6, 0, 1 }, ++ .disfall_st = { 0x00c4, 6, 6, 0, 1 }, ++ .disfall_clr = { 0x00c8, 6, 6, 0, 1 }, ++ .disrise_en = { 0x00c0, 5, 5, 0, 1 }, ++ .disrise_st = { 0x00c4, 5, 5, 0, 1 }, ++ .disrise_clr = { 0x00c8, 5, 5, 0, 1 }, ++ .utmi_avalid = { 0x0080, 1, 1, 0, 1 }, ++ .utmi_bvalid = { 0x0080, 0, 0, 0, 1 }, ++ .utmi_ls = { 0x0080, 5, 4, 0, 1 }, ++ } ++ }, ++ .chg_det = { ++ .cp_det = { 0x0080, 8, 8, 0, 1 }, ++ .dcp_det = { 0x0080, 8, 8, 0, 1 }, ++ .dp_det = { 0x0080, 9, 9, 1, 0 }, ++ .idm_sink_en = { 0x0010, 5, 5, 1, 0 }, ++ .idp_sink_en = { 0x0010, 5, 5, 0, 1 }, ++ .idp_src_en = { 0x0010, 14, 14, 0, 1 }, ++ .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 }, ++ .vdm_src_en = { 0x0010, 7, 6, 0, 3 }, ++ .vdp_src_en = { 0x0010, 7, 6, 0, 3 }, ++ }, ++ }, ++ { ++ .reg = 0x2000, ++ .num_ports = 1, ++ .phy_tuning = rk3576_usb2phy_tuning, ++ .clkout_ctl = { 0x2008, 0, 0, 1, 0 }, ++ .port_cfgs = { ++ [USB2PHY_PORT_OTG] = { ++ .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 }, ++ .bvalid_det_en = { 0x20c0, 1, 1, 0, 1 }, ++ .bvalid_det_st = { 0x20c4, 1, 1, 0, 1 }, ++ .bvalid_det_clr = { 0x20c8, 1, 1, 0, 1 }, ++ .ls_det_en = { 0x20c0, 0, 0, 0, 1 }, ++ .ls_det_st = { 0x20c4, 0, 0, 0, 1 }, ++ .ls_det_clr = { 0x20c8, 0, 0, 0, 1 }, ++ .disfall_en = { 0x20c0, 6, 6, 0, 1 }, ++ .disfall_st = { 0x20c4, 6, 6, 0, 1 }, ++ .disfall_clr = { 0x20c8, 6, 6, 0, 1 }, ++ .disrise_en = { 0x20c0, 5, 5, 0, 1 }, ++ .disrise_st = { 0x20c4, 5, 5, 0, 1 }, ++ .disrise_clr = { 0x20c8, 5, 5, 0, 1 }, ++ .utmi_avalid = { 0x2080, 1, 1, 0, 1 }, ++ .utmi_bvalid = { 0x2080, 0, 0, 0, 1 }, ++ .utmi_ls = { 0x2080, 5, 4, 0, 1 }, ++ } ++ }, ++ .chg_det = { ++ .cp_det = { 0x2080, 8, 8, 0, 1 }, ++ .dcp_det = { 0x2080, 8, 8, 0, 1 }, ++ .dp_det = { 0x2080, 9, 9, 1, 0 }, ++ .idm_sink_en = { 0x2010, 5, 5, 1, 0 }, ++ .idp_sink_en = { 0x2010, 5, 5, 0, 1 }, ++ .idp_src_en = { 0x2010, 14, 14, 0, 1 }, ++ .rdm_pdwn_en = { 0x2010, 14, 14, 0, 1 }, ++ .vdm_src_en = { 0x2010, 7, 6, 0, 3 }, ++ .vdp_src_en = { 0x2010, 7, 6, 0, 3 }, ++ }, ++ }, ++ { /* sentinel */ } ++}; ++ + static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { + { + .reg = 0x0000, +@@ -2026,6 +2128,7 @@ static const struct of_device_id rockchi + { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, + { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, + { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, ++ { .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs }, + { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs }, + { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, + {} diff --git a/target/linux/rockchip/patches-6.6/032-08-v6.13-phy-rockchip-usbdp-add-rk3576-device-match-data.patch b/target/linux/rockchip/patches-6.6/032-08-v6.13-phy-rockchip-usbdp-add-rk3576-device-match-data.patch new file mode 100644 index 000000000..36bb98679 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/032-08-v6.13-phy-rockchip-usbdp-add-rk3576-device-match-data.patch @@ -0,0 +1,73 @@ +From a76de028c619dd18f89786805bcc7bb4d379ea9f Mon Sep 17 00:00:00 2001 +From: Frank Wang +Date: Mon, 14 Oct 2024 10:03:42 +0800 +Subject: [PATCH] phy: rockchip: usbdp: add rk3576 device match data + +This adds RK3576 device match data support. + +Signed-off-by: Frank Wang +Acked-by: Dragan Simic +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20241014020342.15974-2-frawang.cn@gmail.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/phy-rockchip-usbdp.c | 41 +++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c ++++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c +@@ -1538,6 +1538,43 @@ static const char * const rk_udphy_rst_l + "init", "cmn", "lane", "pcs_apb", "pma_apb" + }; + ++static const struct rk_udphy_cfg rk3576_udphy_cfgs = { ++ .num_phys = 1, ++ .phy_ids = { 0x2b010000 }, ++ .num_rsts = ARRAY_SIZE(rk_udphy_rst_list), ++ .rst_list = rk_udphy_rst_list, ++ .grfcfg = { ++ /* u2phy-grf */ ++ .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0010, 1, 0, 0x2, 0x3), ++ .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0000, 15, 14, 0x1, 0x3), ++ ++ /* usb-grf */ ++ .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x0030, 15, 0, 0x1100, 0x0188), ++ ++ /* usbdpphy-grf */ ++ .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1), ++ .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1), ++ }, ++ .vogrfcfg = { ++ { ++ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3), ++ .dp_lane_reg = 0x0000, ++ }, ++ }, ++ .dp_tx_ctrl_cfg = { ++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, ++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, ++ rk3588_dp_tx_drv_ctrl_hbr2, ++ rk3588_dp_tx_drv_ctrl_hbr3, ++ }, ++ .dp_tx_ctrl_cfg_typec = { ++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, ++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, ++ rk3588_dp_tx_drv_ctrl_hbr2, ++ rk3588_dp_tx_drv_ctrl_hbr3, ++ }, ++}; ++ + static const struct rk_udphy_cfg rk3588_udphy_cfgs = { + .num_phys = 2, + .phy_ids = { +@@ -1585,6 +1622,10 @@ static const struct rk_udphy_cfg rk3588_ + + static const struct of_device_id rk_udphy_dt_match[] = { + { ++ .compatible = "rockchip,rk3576-usbdp-phy", ++ .data = &rk3576_udphy_cfgs ++ }, ++ { + .compatible = "rockchip,rk3588-usbdp-phy", + .data = &rk3588_udphy_cfgs + }, diff --git a/target/linux/rockchip/patches-6.6/033-01-v6.13-gpio-rockchip-explan-the-format-of-the-GPIO-version-ID.patch b/target/linux/rockchip/patches-6.6/033-01-v6.13-gpio-rockchip-explan-the-format-of-the-GPIO-version-ID.patch new file mode 100644 index 000000000..38a171acf --- /dev/null +++ b/target/linux/rockchip/patches-6.6/033-01-v6.13-gpio-rockchip-explan-the-format-of-the-GPIO-version-ID.patch @@ -0,0 +1,37 @@ +From 591ae6bed250e4067db926313ff7279d23a1c7d1 Mon Sep 17 00:00:00 2001 +From: Ye Zhang +Date: Tue, 12 Nov 2024 09:54:05 +0800 +Subject: [PATCH] gpio: rockchip: explan the format of the GPIO version ID + +Remove redundant comments and provide a detailed explanation of the +GPIO version ID. + +Signed-off-by: Ye Zhang +Reviewed-by: Andy Shevchenko +Reviewed-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20241112015408.3139996-2-ye.zhang@rock-chips.com +Signed-off-by: Bartosz Golaszewski +--- + drivers/gpio/gpio-rockchip.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -26,9 +26,15 @@ + #include "../pinctrl/core.h" + #include "../pinctrl/pinctrl-rockchip.h" + ++/* ++ * Version ID Register ++ * Bits [31:24] - Major Version ++ * Bits [23:16] - Minor Version ++ * Bits [15:0] - Revision Number ++ */ + #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ +-#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */ +-#define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */ ++#define GPIO_TYPE_V2 (0x01000C2B) ++#define GPIO_TYPE_V2_1 (0x0101157C) + + static const struct rockchip_gpio_regs gpio_regs_v1 = { + .port_dr = 0x00, diff --git a/target/linux/rockchip/patches-6.6/033-02-v6.13-gpio-rockchip-change-the-GPIO-version-judgment-logic.patch b/target/linux/rockchip/patches-6.6/033-02-v6.13-gpio-rockchip-change-the-GPIO-version-judgment-logic.patch new file mode 100644 index 000000000..13bfa981e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/033-02-v6.13-gpio-rockchip-change-the-GPIO-version-judgment-logic.patch @@ -0,0 +1,46 @@ +From 41209307cad7f14c387c68375a93b50e54261a53 Mon Sep 17 00:00:00 2001 +From: Ye Zhang +Date: Tue, 12 Nov 2024 09:54:06 +0800 +Subject: [PATCH] gpio: rockchip: change the GPIO version judgment logic + +Have a list of valid IDs and default to -ENODEV. + +Signed-off-by: Ye Zhang +Reviewed-by: Sebastian Reichel +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20241112015408.3139996-3-ye.zhang@rock-chips.com +Signed-off-by: Bartosz Golaszewski +--- + drivers/gpio/gpio-rockchip.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -667,8 +667,9 @@ static int rockchip_get_bank_data(struct + clk_prepare_enable(bank->clk); + id = readl(bank->reg_base + gpio_regs_v2.version_id); + +- /* If not gpio v2, that is default to v1. */ +- if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) { ++ switch (id) { ++ case GPIO_TYPE_V2: ++ case GPIO_TYPE_V2_1: + bank->gpio_regs = &gpio_regs_v2; + bank->gpio_type = GPIO_TYPE_V2; + bank->db_clk = of_clk_get(bank->of_node, 1); +@@ -677,9 +678,14 @@ static int rockchip_get_bank_data(struct + clk_disable_unprepare(bank->clk); + return -EINVAL; + } +- } else { ++ break; ++ case GPIO_TYPE_V1: + bank->gpio_regs = &gpio_regs_v1; + bank->gpio_type = GPIO_TYPE_V1; ++ break; ++ default: ++ dev_err(bank->dev, "unsupported version ID: 0x%08x\n", id); ++ return -ENODEV; + } + + return 0; diff --git a/target/linux/rockchip/patches-6.6/033-03-v6.13-gpio-rockchip-support-new-version-GPIO.patch b/target/linux/rockchip/patches-6.6/033-03-v6.13-gpio-rockchip-support-new-version-GPIO.patch new file mode 100644 index 000000000..4c10f80e6 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/033-03-v6.13-gpio-rockchip-support-new-version-GPIO.patch @@ -0,0 +1,34 @@ +From 8bcbd0379c05c66ce2e842c7e8901aa317cdf04e Mon Sep 17 00:00:00 2001 +From: Ye Zhang +Date: Tue, 12 Nov 2024 09:54:07 +0800 +Subject: [PATCH] gpio: rockchip: support new version GPIO + +Support the next version GPIO controller on SoCs like rk3576. + +Signed-off-by: Ye Zhang +Reviewed-by: Andy Shevchenko +Reviewed-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20241112015408.3139996-4-ye.zhang@rock-chips.com +Signed-off-by: Bartosz Golaszewski +--- + drivers/gpio/gpio-rockchip.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -35,6 +35,7 @@ + #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ + #define GPIO_TYPE_V2 (0x01000C2B) + #define GPIO_TYPE_V2_1 (0x0101157C) ++#define GPIO_TYPE_V2_2 (0x010219C8) + + static const struct rockchip_gpio_regs gpio_regs_v1 = { + .port_dr = 0x00, +@@ -670,6 +671,7 @@ static int rockchip_get_bank_data(struct + switch (id) { + case GPIO_TYPE_V2: + case GPIO_TYPE_V2_1: ++ case GPIO_TYPE_V2_2: + bank->gpio_regs = &gpio_regs_v2; + bank->gpio_type = GPIO_TYPE_V2; + bank->db_clk = of_clk_get(bank->of_node, 1); diff --git a/target/linux/rockchip/patches-6.6/035-01-v6.12-mmc-dw_mmc-rockchip-Add-internal-phase-support.patch b/target/linux/rockchip/patches-6.6/035-01-v6.12-mmc-dw_mmc-rockchip-Add-internal-phase-support.patch new file mode 100644 index 000000000..663adaa9e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/035-01-v6.12-mmc-dw_mmc-rockchip-Add-internal-phase-support.patch @@ -0,0 +1,260 @@ +From 59903441f5e49d46478fefcccec41e2ba896b740 Mon Sep 17 00:00:00 2001 +From: Shawn Lin +Date: Wed, 28 Aug 2024 15:24:55 +0000 +Subject: [PATCH] mmc: dw_mmc-rockchip: Add internal phase support + +Some Rockchip devices put the phase settings into the dw_mmc controller. + +When the feature is present, the ciu-drive and ciu-sample clocks are +not used and the phase configuration is done directly through the mmc +controller. + +Signed-off-by: Shawn Lin +Signed-off-by: Detlev Casanova +Acked-by: Shawn Lin +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/010201919996fdae-8a9f843e-00a8-4131-98bf-a9da4ed04bfd-000000@eu-west-1.amazonses.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/dw_mmc-rockchip.c | 171 +++++++++++++++++++++++++++-- + 1 file changed, 160 insertions(+), 11 deletions(-) + +--- a/drivers/mmc/host/dw_mmc-rockchip.c ++++ b/drivers/mmc/host/dw_mmc-rockchip.c +@@ -15,7 +15,17 @@ + #include "dw_mmc.h" + #include "dw_mmc-pltfm.h" + +-#define RK3288_CLKGEN_DIV 2 ++#define RK3288_CLKGEN_DIV 2 ++#define SDMMC_TIMING_CON0 0x130 ++#define SDMMC_TIMING_CON1 0x134 ++#define ROCKCHIP_MMC_DELAY_SEL BIT(10) ++#define ROCKCHIP_MMC_DEGREE_MASK 0x3 ++#define ROCKCHIP_MMC_DEGREE_OFFSET 1 ++#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 ++#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) ++#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 ++#define HIWORD_UPDATE(val, mask, shift) \ ++ ((val) << (shift) | (mask) << ((shift) + 16)) + + static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 }; + +@@ -24,8 +34,143 @@ struct dw_mci_rockchip_priv_data { + struct clk *sample_clk; + int default_sample_phase; + int num_phases; ++ bool internal_phase; + }; + ++/* ++ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to ++ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. ++ */ ++static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample) ++{ ++ unsigned long rate = clk_get_rate(host->ciu_clk); ++ u32 raw_value; ++ u16 degrees; ++ u32 delay_num = 0; ++ ++ /* Constant signal, no measurable phase shift */ ++ if (!rate) ++ return 0; ++ ++ if (sample) ++ raw_value = mci_readl(host, TIMING_CON1); ++ else ++ raw_value = mci_readl(host, TIMING_CON0); ++ ++ raw_value >>= ROCKCHIP_MMC_DEGREE_OFFSET; ++ degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; ++ ++ if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { ++ /* degrees/delaynum * 1000000 */ ++ unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * ++ 36 * (rate / 10000); ++ ++ delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); ++ delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; ++ degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); ++ } ++ ++ return degrees % 360; ++} ++ ++static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) ++{ ++ struct dw_mci_rockchip_priv_data *priv = host->priv; ++ struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; ++ ++ if (priv->internal_phase) ++ return rockchip_mmc_get_internal_phase(host, sample); ++ else ++ return clk_get_phase(clock); ++} ++ ++static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees) ++{ ++ unsigned long rate = clk_get_rate(host->ciu_clk); ++ u8 nineties, remainder; ++ u8 delay_num; ++ u32 raw_value; ++ u32 delay; ++ ++ /* ++ * The below calculation is based on the output clock from ++ * MMC host to the card, which expects the phase clock inherits ++ * the clock rate from its parent, namely the output clock ++ * provider of MMC host. However, things may go wrong if ++ * (1) It is orphan. ++ * (2) It is assigned to the wrong parent. ++ * ++ * This check help debug the case (1), which seems to be the ++ * most likely problem we often face and which makes it difficult ++ * for people to debug unstable mmc tuning results. ++ */ ++ if (!rate) { ++ dev_err(host->dev, "%s: invalid clk rate\n", __func__); ++ return -EINVAL; ++ } ++ ++ nineties = degrees / 90; ++ remainder = (degrees % 90); ++ ++ /* ++ * Due to the inexact nature of the "fine" delay, we might ++ * actually go non-monotonic. We don't go _too_ monotonic ++ * though, so we should be OK. Here are options of how we may ++ * work: ++ * ++ * Ideally we end up with: ++ * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 ++ * ++ * On one extreme (if delay is actually 44ps): ++ * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 ++ * The other (if delay is actually 77ps): ++ * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 ++ * ++ * It's possible we might make a delay that is up to 25 ++ * degrees off from what we think we're making. That's OK ++ * though because we should be REALLY far from any bad range. ++ */ ++ ++ /* ++ * Convert to delay; do a little extra work to make sure we ++ * don't overflow 32-bit / 64-bit numbers. ++ */ ++ delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ ++ delay *= remainder; ++ delay = DIV_ROUND_CLOSEST(delay, ++ (rate / 1000) * 36 * ++ (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); ++ ++ delay_num = (u8) min_t(u32, delay, 255); ++ ++ raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; ++ raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; ++ raw_value |= nineties; ++ ++ if (sample) ++ mci_writel(host, TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); ++ else ++ mci_writel(host, TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1)); ++ ++ dev_dbg(host->dev, "set %s_phase(%d) delay_nums=%u actual_degrees=%d\n", ++ sample ? "sample" : "drv", degrees, delay_num, ++ rockchip_mmc_get_phase(host, sample) ++ ); ++ ++ return 0; ++} ++ ++static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees) ++{ ++ struct dw_mci_rockchip_priv_data *priv = host->priv; ++ struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; ++ ++ if (priv->internal_phase) ++ return rockchip_mmc_set_internal_phase(host, sample, degrees); ++ else ++ return clk_set_phase(clock, degrees); ++} ++ + static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) + { + struct dw_mci_rockchip_priv_data *priv = host->priv; +@@ -64,7 +209,7 @@ static void dw_mci_rk3288_set_ios(struct + + /* Make sure we use phases which we can enumerate with */ + if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS) +- clk_set_phase(priv->sample_clk, priv->default_sample_phase); ++ rockchip_mmc_set_phase(host, true, priv->default_sample_phase); + + /* + * Set the drive phase offset based on speed mode to achieve hold times. +@@ -127,7 +272,7 @@ static void dw_mci_rk3288_set_ios(struct + break; + } + +- clk_set_phase(priv->drv_clk, phase); ++ rockchip_mmc_set_phase(host, false, phase); + } + } + +@@ -151,6 +296,7 @@ static int dw_mci_rk3288_execute_tuning( + int longest_range_len = -1; + int longest_range = -1; + int middle_phase; ++ int phase; + + if (IS_ERR(priv->sample_clk)) { + dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); +@@ -164,8 +310,10 @@ static int dw_mci_rk3288_execute_tuning( + + /* Try each phase and extract good ranges */ + for (i = 0; i < priv->num_phases; ) { +- clk_set_phase(priv->sample_clk, +- TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); ++ rockchip_mmc_set_phase(host, true, ++ TUNING_ITERATION_TO_PHASE( ++ i, ++ priv->num_phases)); + + v = !mmc_send_tuning(mmc, opcode, NULL); + +@@ -211,7 +359,8 @@ static int dw_mci_rk3288_execute_tuning( + } + + if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) { +- clk_set_phase(priv->sample_clk, priv->default_sample_phase); ++ rockchip_mmc_set_phase(host, true, priv->default_sample_phase); ++ + dev_info(host->dev, "All phases work, using default phase %d.", + priv->default_sample_phase); + goto free; +@@ -248,12 +397,10 @@ static int dw_mci_rk3288_execute_tuning( + + middle_phase = ranges[longest_range].start + longest_range_len / 2; + middle_phase %= priv->num_phases; +- dev_info(host->dev, "Successfully tuned phase to %d\n", +- TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases)); ++ phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases); ++ dev_info(host->dev, "Successfully tuned phase to %d\n", phase); + +- clk_set_phase(priv->sample_clk, +- TUNING_ITERATION_TO_PHASE(middle_phase, +- priv->num_phases)); ++ rockchip_mmc_set_phase(host, true, phase); + + free: + kfree(ranges); +@@ -287,6 +434,8 @@ static int dw_mci_rk3288_parse_dt(struct + + host->priv = priv; + ++ priv->internal_phase = false; ++ + return 0; + } + diff --git a/target/linux/rockchip/patches-6.6/035-02-v6.12-mmc-dw_mmc-rockchip-Add-support-for-rk3576-SoCs.patch b/target/linux/rockchip/patches-6.6/035-02-v6.12-mmc-dw_mmc-rockchip-Add-support-for-rk3576-SoCs.patch new file mode 100644 index 000000000..402c0026b --- /dev/null +++ b/target/linux/rockchip/patches-6.6/035-02-v6.12-mmc-dw_mmc-rockchip-Add-support-for-rk3576-SoCs.patch @@ -0,0 +1,111 @@ +From 73abb1f16e28d5a41d0abea779a3f0b75cf8823e Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Wed, 28 Aug 2024 15:24:56 +0000 +Subject: [PATCH] mmc: dw_mmc-rockchip: Add support for rk3576 SoCs + +On rk3576 the tunable clocks are inside the controller itself, removing +the need for the "ciu-drive" and "ciu-sample" clocks. + +That makes it a new type of controller that has its own dt_parse function. + +Signed-off-by: Detlev Casanova +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/010201919997044d-c3a008d1-afbc-462f-a928-fc1ece785bdb-000000@eu-west-1.amazonses.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/dw_mmc-rockchip.c | 48 ++++++++++++++++++++++++++---- + 1 file changed, 43 insertions(+), 5 deletions(-) + +--- a/drivers/mmc/host/dw_mmc-rockchip.c ++++ b/drivers/mmc/host/dw_mmc-rockchip.c +@@ -407,7 +407,7 @@ free: + return ret; + } + +-static int dw_mci_rk3288_parse_dt(struct dw_mci *host) ++static int dw_mci_common_parse_dt(struct dw_mci *host) + { + struct device_node *np = host->dev->of_node; + struct dw_mci_rockchip_priv_data *priv; +@@ -417,13 +417,29 @@ static int dw_mci_rk3288_parse_dt(struct + return -ENOMEM; + + if (of_property_read_u32(np, "rockchip,desired-num-phases", +- &priv->num_phases)) ++ &priv->num_phases)) + priv->num_phases = 360; + + if (of_property_read_u32(np, "rockchip,default-sample-phase", +- &priv->default_sample_phase)) ++ &priv->default_sample_phase)) + priv->default_sample_phase = 0; + ++ host->priv = priv; ++ ++ return 0; ++} ++ ++static int dw_mci_rk3288_parse_dt(struct dw_mci *host) ++{ ++ struct dw_mci_rockchip_priv_data *priv; ++ int err; ++ ++ err = dw_mci_common_parse_dt(host); ++ if (err) ++ return err; ++ ++ priv = host->priv; ++ + priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); + if (IS_ERR(priv->drv_clk)) + dev_dbg(host->dev, "ciu-drive not available\n"); +@@ -432,13 +448,25 @@ static int dw_mci_rk3288_parse_dt(struct + if (IS_ERR(priv->sample_clk)) + dev_dbg(host->dev, "ciu-sample not available\n"); + +- host->priv = priv; +- + priv->internal_phase = false; + + return 0; + } + ++static int dw_mci_rk3576_parse_dt(struct dw_mci *host) ++{ ++ struct dw_mci_rockchip_priv_data *priv; ++ int err = dw_mci_common_parse_dt(host); ++ if (err) ++ return err; ++ ++ priv = host->priv; ++ ++ priv->internal_phase = true; ++ ++ return 0; ++} ++ + static int dw_mci_rockchip_init(struct dw_mci *host) + { + int ret, i; +@@ -480,11 +508,21 @@ static const struct dw_mci_drv_data rk32 + .init = dw_mci_rockchip_init, + }; + ++static const struct dw_mci_drv_data rk3576_drv_data = { ++ .common_caps = MMC_CAP_CMD23, ++ .set_ios = dw_mci_rk3288_set_ios, ++ .execute_tuning = dw_mci_rk3288_execute_tuning, ++ .parse_dt = dw_mci_rk3576_parse_dt, ++ .init = dw_mci_rockchip_init, ++}; ++ + static const struct of_device_id dw_mci_rockchip_match[] = { + { .compatible = "rockchip,rk2928-dw-mshc", + .data = &rk2928_drv_data }, + { .compatible = "rockchip,rk3288-dw-mshc", + .data = &rk3288_drv_data }, ++ { .compatible = "rockchip,rk3576-dw-mshc", ++ .data = &rk3576_drv_data }, + {}, + }; + MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match); diff --git a/target/linux/rockchip/patches-6.6/036-01-v6.12-ethernet-stmmac-dwmac-rk-Fix-typo-for-RK3588-code.patch b/target/linux/rockchip/patches-6.6/036-01-v6.12-ethernet-stmmac-dwmac-rk-Fix-typo-for-RK3588-code.patch new file mode 100644 index 000000000..f15275023 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/036-01-v6.12-ethernet-stmmac-dwmac-rk-Fix-typo-for-RK3588-code.patch @@ -0,0 +1,40 @@ +From 78a60497a020ff526ae067125eef0dee10df5771 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Fri, 23 Aug 2024 10:11:13 -0400 +Subject: [PATCH] ethernet: stmmac: dwmac-rk: Fix typo for RK3588 code + +Fix SELET -> SELECT in RK3588_GMAC_CLK_SELET_CRU and +RK3588_GMAC_CLK_SELET_IO + +Signed-off-by: Detlev Casanova +Reviewed-by: Heiko Stuebner +Link: https://patch.msgid.link/20240823141318.51201-2-detlev.casanova@collabora.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -1143,8 +1143,8 @@ static const struct rk_gmac_ops rk3568_o + #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) + #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) + +-#define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4) +-#define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4) ++#define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) ++#define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) + + #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) + #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) +@@ -1242,8 +1242,8 @@ err: + static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, + bool enable) + { +- unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->id) : +- RK3588_GMAC_CLK_SELET_CRU(bsp_priv->id); ++ unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : ++ RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); + + val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : + RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); diff --git a/target/linux/rockchip/patches-6.6/036-02-v6.12-ethernet-stmmac-dwmac-rk-Add-GMAC-support-for-RK3576.patch b/target/linux/rockchip/patches-6.6/036-02-v6.12-ethernet-stmmac-dwmac-rk-Add-GMAC-support-for-RK3576.patch new file mode 100644 index 000000000..5d3063657 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/036-02-v6.12-ethernet-stmmac-dwmac-rk-Add-GMAC-support-for-RK3576.patch @@ -0,0 +1,189 @@ +From f9cc9997cba9defaf00c8e70d25f88271cbd6d4d Mon Sep 17 00:00:00 2001 +From: David Wu +Date: Fri, 23 Aug 2024 10:11:15 -0400 +Subject: [PATCH] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3576 + +Add constants and callback functions for the dwmac on RK3576 soc. + +Signed-off-by: David Wu +[rebase, extracted bindings] +Signed-off-by: Detlev Casanova +Reviewed-by: Heiko Stuebner +Link: https://patch.msgid.link/20240823141318.51201-4-detlev.casanova@collabora.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 156 ++++++++++++++++++ + 1 file changed, 156 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +@@ -1118,6 +1118,161 @@ static const struct rk_gmac_ops rk3568_o + }, + }; + ++/* VCCIO0_1_3_IOC */ ++#define RK3576_VCCIO0_1_3_IOC_CON2 0X6408 ++#define RK3576_VCCIO0_1_3_IOC_CON3 0X640c ++#define RK3576_VCCIO0_1_3_IOC_CON4 0X6410 ++#define RK3576_VCCIO0_1_3_IOC_CON5 0X6414 ++ ++#define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) ++#define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) ++#define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) ++#define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) ++ ++#define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) ++#define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) ++ ++/* SDGMAC_GRF */ ++#define RK3576_GRF_GMAC_CON0 0X0020 ++#define RK3576_GRF_GMAC_CON1 0X0024 ++ ++#define RK3576_GMAC_RMII_MODE GRF_BIT(3) ++#define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) ++ ++#define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) ++#define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) ++ ++#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) ++#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) ++ ++#define RK3576_GMAC_CLK_RGMII_DIV1 \ ++ (GRF_CLR_BIT(6) | GRF_CLR_BIT(5)) ++#define RK3576_GMAC_CLK_RGMII_DIV5 \ ++ (GRF_BIT(6) | GRF_BIT(5)) ++#define RK3576_GMAC_CLK_RGMII_DIV50 \ ++ (GRF_BIT(6) | GRF_CLR_BIT(5)) ++ ++#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) ++#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) ++ ++static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, ++ int tx_delay, int rx_delay) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ unsigned int offset_con; ++ ++ if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { ++ dev_err(dev, "Missing rockchip,grf or rockchip,php-grf property\n"); ++ return; ++ } ++ ++ offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : ++ RK3576_GRF_GMAC_CON0; ++ ++ regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); ++ ++ offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : ++ RK3576_VCCIO0_1_3_IOC_CON2; ++ ++ /* m0 && m1 delay enabled */ ++ regmap_write(bsp_priv->php_grf, offset_con, ++ DELAY_ENABLE(RK3576, tx_delay, rx_delay)); ++ regmap_write(bsp_priv->php_grf, offset_con + 0x4, ++ DELAY_ENABLE(RK3576, tx_delay, rx_delay)); ++ ++ /* m0 && m1 delay value */ ++ regmap_write(bsp_priv->php_grf, offset_con, ++ RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | ++ RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); ++ regmap_write(bsp_priv->php_grf, offset_con + 0x4, ++ RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) | ++ RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); ++} ++ ++static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ unsigned int offset_con; ++ ++ if (IS_ERR(bsp_priv->grf)) { ++ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); ++ return; ++ } ++ ++ offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : ++ RK3576_GRF_GMAC_CON0; ++ ++ regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); ++} ++ ++static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) ++{ ++ struct device *dev = &bsp_priv->pdev->dev; ++ unsigned int val = 0, offset_con; ++ ++ switch (speed) { ++ case 10: ++ if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) ++ val = RK3576_GMAC_CLK_RMII_DIV20; ++ else ++ val = RK3576_GMAC_CLK_RGMII_DIV50; ++ break; ++ case 100: ++ if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) ++ val = RK3576_GMAC_CLK_RMII_DIV2; ++ else ++ val = RK3576_GMAC_CLK_RGMII_DIV5; ++ break; ++ case 1000: ++ if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) ++ val = RK3576_GMAC_CLK_RGMII_DIV1; ++ else ++ goto err; ++ break; ++ default: ++ goto err; ++ } ++ ++ offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : ++ RK3576_GRF_GMAC_CON0; ++ ++ regmap_write(bsp_priv->grf, offset_con, val); ++ ++ return; ++err: ++ dev_err(dev, "unknown speed value for GMAC speed=%d", speed); ++} ++ ++static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, ++ bool enable) ++{ ++ unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO : ++ RK3576_GMAC_CLK_SELECT_CRU; ++ unsigned int offset_con; ++ ++ val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE : ++ RK3576_GMAC_CLK_RMII_GATE; ++ ++ offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : ++ RK3576_GRF_GMAC_CON0; ++ ++ regmap_write(bsp_priv->grf, offset_con, val); ++} ++ ++static const struct rk_gmac_ops rk3576_ops = { ++ .set_to_rgmii = rk3576_set_to_rgmii, ++ .set_to_rmii = rk3576_set_to_rmii, ++ .set_rgmii_speed = rk3576_set_gmac_speed, ++ .set_rmii_speed = rk3576_set_gmac_speed, ++ .set_clock_selection = rk3576_set_clock_selection, ++ .regs_valid = true, ++ .regs = { ++ 0x2a220000, /* gmac0 */ ++ 0x2a230000, /* gmac1 */ ++ 0x0, /* sentinel */ ++ }, ++}; ++ + /* sys_grf */ + #define RK3588_GRF_GMAC_CON7 0X031c + #define RK3588_GRF_GMAC_CON8 0X0320 +@@ -1914,6 +2069,7 @@ static const struct of_device_id rk_gmac + { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, + { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, + { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, ++ { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, + { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, + { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, + { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops }, diff --git a/target/linux/rockchip/patches-6.6/060-v6.13-arm64-dts-rockchip-Add-rk3576-SoC-base-DT.patch b/target/linux/rockchip/patches-6.6/060-v6.13-arm64-dts-rockchip-Add-rk3576-SoC-base-DT.patch new file mode 100644 index 000000000..7bfdee07f --- /dev/null +++ b/target/linux/rockchip/patches-6.6/060-v6.13-arm64-dts-rockchip-Add-rk3576-SoC-base-DT.patch @@ -0,0 +1,7486 @@ +From 4b9dc5d536b988fbd84e68e8d8ac420752b185b6 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Tue, 3 Sep 2024 11:22:38 -0400 +Subject: [PATCH] arm64: dts: rockchip: Add rk3576 SoC base DT + +This device tree contains all devices necessary for booting from network +or SD Card. + +It supports CPU, CRU, PM domains, dma, interrupts, timers, UART, I2C +and SDHCI (everything necessary to boot Linux on this system on chip) +as well as Ethernet, SPI, GPU and RTC. + +Signed-off-by: Liang Chen +Signed-off-by: Finley Xiao +Signed-off-by: Yifeng Zhao +Signed-off-by: Elaine Zhang +Signed-off-by: Detlev Casanova +Tested-by: Liang Chen +Link: https://lore.kernel.org/r/20240903152308.13565-9-detlev.casanova@collabora.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3576-pinctrl.dtsi | 5775 +++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1678 +++++ + 2 files changed, 7453 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi + create mode 100644 arch/arm64/boot/dts/rockchip/rk3576.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi +@@ -0,0 +1,5775 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2023 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include "rockchip-pinconf.dtsi" ++ ++/* ++ * This file is auto generated by pin2dts tool, please keep these code ++ * by adding changes at end of this file. ++ */ ++&pinctrl { ++ aupll_clk { ++ /omit-if-no-ref/ ++ aupll_clkm0_pins: aupll_clkm0-pins { ++ rockchip,pins = ++ /* aupll_clk_in_m0 */ ++ <0 RK_PA0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ aupll_clkm1_pins: aupll_clkm1-pins { ++ rockchip,pins = ++ /* aupll_clk_in_m1 */ ++ <0 RK_PB0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ aupll_clkm2_pins: aupll_clkm2-pins { ++ rockchip,pins = ++ /* aupll_clk_in_m2 */ ++ <4 RK_PA2 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ cam_clk0 { ++ /omit-if-no-ref/ ++ cam_clk0m0_clk0: cam_clk0m0-clk0 { ++ rockchip,pins = ++ /* cam_clk0_out_m0 */ ++ <3 RK_PD7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ cam_clk0m1_clk0: cam_clk0m1-clk0 { ++ rockchip,pins = ++ /* cam_clk0_out_m1 */ ++ <2 RK_PD2 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ cam_clk1 { ++ /omit-if-no-ref/ ++ cam_clk1m0_clk1: cam_clk1m0-clk1 { ++ rockchip,pins = ++ /* cam_clk1_out_m0 */ ++ <4 RK_PA0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ cam_clk1m1_clk1: cam_clk1m1-clk1 { ++ rockchip,pins = ++ /* cam_clk1_out_m1 */ ++ <2 RK_PD6 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ cam_clk2 { ++ /omit-if-no-ref/ ++ cam_clk2m0_clk2: cam_clk2m0-clk2 { ++ rockchip,pins = ++ /* cam_clk2_out_m0 */ ++ <4 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ cam_clk2m1_clk2: cam_clk2m1-clk2 { ++ rockchip,pins = ++ /* cam_clk2_out_m1 */ ++ <2 RK_PD7 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ can0 { ++ /omit-if-no-ref/ ++ can0m0_pins: can0m0-pins { ++ rockchip,pins = ++ /* can0_rx_m0 */ ++ <2 RK_PA0 13 &pcfg_pull_none>, ++ /* can0_tx_m0 */ ++ <2 RK_PA1 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can0m1_pins: can0m1-pins { ++ rockchip,pins = ++ /* can0_rx_m1 */ ++ <4 RK_PC3 12 &pcfg_pull_none>, ++ /* can0_tx_m1 */ ++ <4 RK_PC2 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can0m2_pins: can0m2-pins { ++ rockchip,pins = ++ /* can0_rx_m2 */ ++ <4 RK_PA6 13 &pcfg_pull_none>, ++ /* can0_tx_m2 */ ++ <4 RK_PA4 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can0m3_pins: can0m3-pins { ++ rockchip,pins = ++ /* can0_rx_m3 */ ++ <3 RK_PC1 12 &pcfg_pull_none>, ++ /* can0_tx_m3 */ ++ <3 RK_PC4 12 &pcfg_pull_none>; ++ }; ++ }; ++ ++ can1 { ++ /omit-if-no-ref/ ++ can1m0_pins: can1m0-pins { ++ rockchip,pins = ++ /* can1_rx_m0 */ ++ <2 RK_PA2 13 &pcfg_pull_none>, ++ /* can1_tx_m0 */ ++ <2 RK_PA3 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can1m1_pins: can1m1-pins { ++ rockchip,pins = ++ /* can1_rx_m1 */ ++ <4 RK_PC7 13 &pcfg_pull_none>, ++ /* can1_tx_m1 */ ++ <4 RK_PC6 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can1m2_pins: can1m2-pins { ++ rockchip,pins = ++ /* can1_rx_m2 */ ++ <4 RK_PB4 13 &pcfg_pull_none>, ++ /* can1_tx_m2 */ ++ <4 RK_PB5 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can1m3_pins: can1m3-pins { ++ rockchip,pins = ++ /* can1_rx_m3 */ ++ <3 RK_PA3 11 &pcfg_pull_none>, ++ /* can1_tx_m3 */ ++ <3 RK_PA2 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ clk0_32k { ++ /omit-if-no-ref/ ++ clk0_32k_pins: clk0_32k-pins { ++ rockchip,pins = ++ /* clk0_32k_out */ ++ <0 RK_PA2 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ clk1_32k { ++ /omit-if-no-ref/ ++ clk1_32k_pins: clk1_32k-pins { ++ rockchip,pins = ++ /* clk1_32k_out */ ++ <1 RK_PD5 13 &pcfg_pull_none>; ++ }; ++ }; ++ ++ clk_32k { ++ /omit-if-no-ref/ ++ clk_32k_pins: clk_32k-pins { ++ rockchip,pins = ++ /* clk_32k_in */ ++ <0 RK_PA2 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ cpubig { ++ /omit-if-no-ref/ ++ cpubig_pins: cpubig-pins { ++ rockchip,pins = ++ /* cpubig_avs */ ++ <0 RK_PD2 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ cpulit { ++ /omit-if-no-ref/ ++ cpulit_pins: cpulit-pins { ++ rockchip,pins = ++ /* cpulit_avs */ ++ <0 RK_PC0 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ debug0_test { ++ /omit-if-no-ref/ ++ debug0_test_pins: debug0_test-pins { ++ rockchip,pins = ++ /* debug0_test_out */ ++ <1 RK_PC4 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ debug1_test { ++ /omit-if-no-ref/ ++ debug1_test_pins: debug1_test-pins { ++ rockchip,pins = ++ /* debug1_test_out */ ++ <1 RK_PC5 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ debug2_test { ++ /omit-if-no-ref/ ++ debug2_test_pins: debug2_test-pins { ++ rockchip,pins = ++ /* debug2_test_out */ ++ <1 RK_PC6 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ debug3_test { ++ /omit-if-no-ref/ ++ debug3_test_pins: debug3_test-pins { ++ rockchip,pins = ++ /* debug3_test_out */ ++ <1 RK_PC7 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ debug4_test { ++ /omit-if-no-ref/ ++ debug4_test_pins: debug4_test-pins { ++ rockchip,pins = ++ /* debug4_test_out */ ++ <1 RK_PD0 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ debug5_test { ++ /omit-if-no-ref/ ++ debug5_test_pins: debug5_test-pins { ++ rockchip,pins = ++ /* debug5_test_out */ ++ <1 RK_PD1 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ debug6_test { ++ /omit-if-no-ref/ ++ debug6_test_pins: debug6_test-pins { ++ rockchip,pins = ++ /* debug6_test_out */ ++ <1 RK_PD2 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ debug7_test { ++ /omit-if-no-ref/ ++ debug7_test_pins: debug7_test-pins { ++ rockchip,pins = ++ /* debug7_test_out */ ++ <1 RK_PD3 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ dp { ++ /omit-if-no-ref/ ++ dpm0_pins: dpm0-pins { ++ rockchip,pins = ++ /* dp_hpdin_m0 */ ++ <4 RK_PC4 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dpm1_pins: dpm1-pins { ++ rockchip,pins = ++ /* dp_hpdin_m1 */ ++ <0 RK_PC5 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ dsm_aud { ++ /omit-if-no-ref/ ++ dsm_audm0_ln: dsm_audm0-ln { ++ rockchip,pins = ++ /* dsm_aud_ln_m0 */ ++ <2 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dsm_audm0_lp: dsm_audm0-lp { ++ rockchip,pins = ++ /* dsm_aud_lp_m0 */ ++ <2 RK_PA0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dsm_audm0_rn: dsm_audm0-rn { ++ rockchip,pins = ++ /* dsm_aud_rn_m0 */ ++ <2 RK_PA3 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dsm_audm0_rp: dsm_audm0-rp { ++ rockchip,pins = ++ /* dsm_aud_rp_m0 */ ++ <2 RK_PA2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dsm_audm1_ln: dsm_audm1-ln { ++ rockchip,pins = ++ /* dsm_aud_ln_m1 */ ++ <4 RK_PC1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dsm_audm1_lp: dsm_audm1-lp { ++ rockchip,pins = ++ /* dsm_aud_lp_m1 */ ++ <4 RK_PC0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dsm_audm1_rn: dsm_audm1-rn { ++ rockchip,pins = ++ /* dsm_aud_rn_m1 */ ++ <4 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dsm_audm1_rp: dsm_audm1-rp { ++ rockchip,pins = ++ /* dsm_aud_rp_m1 */ ++ <4 RK_PC2 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ dsmc { ++ /omit-if-no-ref/ ++ dsmc_clkn: dsmc-clkn { ++ rockchip,pins = ++ /* dsmc_clkn */ ++ <3 RK_PD6 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_clkp: dsmc-clkp { ++ rockchip,pins = ++ /* dsmc_clkp */ ++ <3 RK_PD5 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_csn0: dsmc-csn0 { ++ rockchip,pins = ++ /* dsmc_csn0 */ ++ <3 RK_PD3 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_csn1: dsmc-csn1 { ++ rockchip,pins = ++ /* dsmc_csn1 */ ++ <3 RK_PB0 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_csn2: dsmc-csn2 { ++ rockchip,pins = ++ /* dsmc_csn2 */ ++ <3 RK_PD1 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_csn3: dsmc-csn3 { ++ rockchip,pins = ++ /* dsmc_csn3 */ ++ <3 RK_PD2 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data0: dsmc-data0 { ++ rockchip,pins = ++ /* dsmc_data0 */ ++ <3 RK_PD4 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data1: dsmc-data1 { ++ rockchip,pins = ++ /* dsmc_data1 */ ++ <3 RK_PD0 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data2: dsmc-data2 { ++ rockchip,pins = ++ /* dsmc_data2 */ ++ <3 RK_PC7 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data3: dsmc-data3 { ++ rockchip,pins = ++ /* dsmc_data3 */ ++ <3 RK_PC6 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data4: dsmc-data4 { ++ rockchip,pins = ++ /* dsmc_data4 */ ++ <3 RK_PC5 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data5: dsmc-data5 { ++ rockchip,pins = ++ /* dsmc_data5 */ ++ <3 RK_PC4 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data6: dsmc-data6 { ++ rockchip,pins = ++ /* dsmc_data6 */ ++ <3 RK_PC1 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data7: dsmc-data7 { ++ rockchip,pins = ++ /* dsmc_data7 */ ++ <3 RK_PC0 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data8: dsmc-data8 { ++ rockchip,pins = ++ /* dsmc_data8 */ ++ <3 RK_PB5 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data9: dsmc-data9 { ++ rockchip,pins = ++ /* dsmc_data9 */ ++ <3 RK_PB4 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data10: dsmc-data10 { ++ rockchip,pins = ++ /* dsmc_data10 */ ++ <3 RK_PB3 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data11: dsmc-data11 { ++ rockchip,pins = ++ /* dsmc_data11 */ ++ <3 RK_PB2 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data12: dsmc-data12 { ++ rockchip,pins = ++ /* dsmc_data12 */ ++ <3 RK_PB1 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data13: dsmc-data13 { ++ rockchip,pins = ++ /* dsmc_data13 */ ++ <3 RK_PA7 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data14: dsmc-data14 { ++ rockchip,pins = ++ /* dsmc_data14 */ ++ <3 RK_PA6 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_data15: dsmc-data15 { ++ rockchip,pins = ++ /* dsmc_data15 */ ++ <3 RK_PA5 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_dqs0: dsmc-dqs0 { ++ rockchip,pins = ++ /* dsmc_dqs0 */ ++ <3 RK_PB7 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_dqs1: dsmc-dqs1 { ++ rockchip,pins = ++ /* dsmc_dqs1 */ ++ <3 RK_PB6 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_int0: dsmc-int0 { ++ rockchip,pins = ++ /* dsmc_int0 */ ++ <4 RK_PA0 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_int1: dsmc-int1 { ++ rockchip,pins = ++ /* dsmc_int1 */ ++ <3 RK_PC2 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_int2: dsmc-int2 { ++ rockchip,pins = ++ /* dsmc_int2 */ ++ <4 RK_PA1 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_int3: dsmc-int3 { ++ rockchip,pins = ++ /* dsmc_int3 */ ++ <3 RK_PC3 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_rdyn: dsmc-rdyn { ++ rockchip,pins = ++ /* dsmc_rdyn */ ++ <3 RK_PA4 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ dsmc_resetn: dsmc-resetn { ++ rockchip,pins = ++ /* dsmc_resetn */ ++ <3 RK_PD7 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ dsmc_testclk { ++ /omit-if-no-ref/ ++ dsmc_testclk_out: dsmc-testclk-out { ++ rockchip,pins = ++ /* dsmc_testclk_out */ ++ <3 RK_PC2 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ dsmc_testdata { ++ /omit-if-no-ref/ ++ dsmc_testdata_out: dsmc-testdata-out { ++ rockchip,pins = ++ /* dsmc_testdata_out */ ++ <3 RK_PC3 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ edp_tx { ++ /omit-if-no-ref/ ++ edp_txm0_pins: edp_txm0-pins { ++ rockchip,pins = ++ /* edp_tx_hpdin_m0 */ ++ <4 RK_PC1 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ edp_txm1_pins: edp_txm1-pins { ++ rockchip,pins = ++ /* edp_tx_hpdin_m1 */ ++ <0 RK_PB6 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ emmc { ++ /omit-if-no-ref/ ++ emmc_rstnout: emmc-rstnout { ++ rockchip,pins = ++ /* emmc_rstn */ ++ <1 RK_PB3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_bus8: emmc-bus8 { ++ rockchip,pins = ++ /* emmc_d0 */ ++ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d1 */ ++ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d2 */ ++ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d3 */ ++ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d4 */ ++ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d5 */ ++ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d6 */ ++ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d7 */ ++ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_clk: emmc-clk { ++ rockchip,pins = ++ /* emmc_clk */ ++ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_cmd: emmc-cmd { ++ rockchip,pins = ++ /* emmc_cmd */ ++ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_strb: emmc-strb { ++ rockchip,pins = ++ /* emmc_strb */ ++ <1 RK_PB2 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ emmc_testclk { ++ /omit-if-no-ref/ ++ emmc_testclk_test: emmc_testclk-test { ++ rockchip,pins = ++ /* emmc_testclk_out */ ++ <1 RK_PB3 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ emmc_testdata { ++ /omit-if-no-ref/ ++ emmc_testdata_test: emmc_testdata-test { ++ rockchip,pins = ++ /* emmc_testdata_out */ ++ <1 RK_PB7 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth0 { ++ /omit-if-no-ref/ ++ eth0m0_miim: eth0m0-miim { ++ rockchip,pins = ++ /* eth0_mdc_m0 */ ++ <3 RK_PA6 3 &pcfg_pull_none>, ++ /* eth0_mdio_m0 */ ++ <3 RK_PA5 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m0_rx_bus2: eth0m0-rx_bus2 { ++ rockchip,pins = ++ /* eth0_rxctl_m0 */ ++ <3 RK_PA7 3 &pcfg_pull_none>, ++ /* eth0_rxd0_m0 */ ++ <3 RK_PB2 3 &pcfg_pull_none>, ++ /* eth0_rxd1_m0 */ ++ <3 RK_PB1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m0_tx_bus2: eth0m0-tx_bus2 { ++ rockchip,pins = ++ /* eth0_txctl_m0 */ ++ <3 RK_PB3 3 &pcfg_pull_none>, ++ /* eth0_txd0_m0 */ ++ <3 RK_PB5 3 &pcfg_pull_none>, ++ /* eth0_txd1_m0 */ ++ <3 RK_PB4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m0_rgmii_clk: eth0m0-rgmii_clk { ++ rockchip,pins = ++ /* eth0_rxclk_m0 */ ++ <3 RK_PD1 3 &pcfg_pull_none>, ++ /* eth0_txclk_m0 */ ++ <3 RK_PB6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m0_rgmii_bus: eth0m0-rgmii_bus { ++ rockchip,pins = ++ /* eth0_rxd2_m0 */ ++ <3 RK_PD3 3 &pcfg_pull_none>, ++ /* eth0_rxd3_m0 */ ++ <3 RK_PD2 3 &pcfg_pull_none>, ++ /* eth0_txd2_m0 */ ++ <3 RK_PC3 3 &pcfg_pull_none>, ++ /* eth0_txd3_m0 */ ++ <3 RK_PC2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m0_mclk: eth0m0-mclk { ++ rockchip,pins = ++ /* eth0m0_mclk */ ++ <3 RK_PB0 3 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ eth0m0_ppsclk: eth0m0-ppsclk { ++ rockchip,pins = ++ /* eth0m0_ppsclk */ ++ <3 RK_PC0 3 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ eth0m0_ppstrig: eth0m0-ppstrig { ++ rockchip,pins = ++ /* eth0m0_ppstrig */ ++ <3 RK_PB7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m1_miim: eth0m1-miim { ++ rockchip,pins = ++ /* eth0_mdc_m1 */ ++ <3 RK_PA1 3 &pcfg_pull_none>, ++ /* eth0_mdio_m1 */ ++ <3 RK_PA0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m1_rx_bus2: eth0m1-rx_bus2 { ++ rockchip,pins = ++ /* eth0_rxctl_m1 */ ++ <3 RK_PA2 3 &pcfg_pull_none>, ++ /* eth0_rxd0_m1 */ ++ <2 RK_PA6 3 &pcfg_pull_none>, ++ /* eth0_rxd1_m1 */ ++ <3 RK_PA3 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m1_tx_bus2: eth0m1-tx_bus2 { ++ rockchip,pins = ++ /* eth0_txctl_m1 */ ++ <2 RK_PA7 3 &pcfg_pull_none>, ++ /* eth0_txd0_m1 */ ++ <2 RK_PB1 3 &pcfg_pull_none>, ++ /* eth0_txd1_m1 */ ++ <2 RK_PB0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m1_rgmii_clk: eth0m1-rgmii_clk { ++ rockchip,pins = ++ /* eth0_rxclk_m1 */ ++ <2 RK_PB5 3 &pcfg_pull_none>, ++ /* eth0_txclk_m1 */ ++ <2 RK_PB3 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m1_rgmii_bus: eth0m1-rgmii_bus { ++ rockchip,pins = ++ /* eth0_rxd2_m1 */ ++ <2 RK_PB7 3 &pcfg_pull_none>, ++ /* eth0_rxd3_m1 */ ++ <2 RK_PB6 3 &pcfg_pull_none>, ++ /* eth0_txd2_m1 */ ++ <2 RK_PB4 3 &pcfg_pull_none>, ++ /* eth0_txd3_m1 */ ++ <2 RK_PB2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m1_mclk: eth0m1-mclk { ++ rockchip,pins = ++ /* eth0m1_mclk */ ++ <2 RK_PD6 3 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ eth0m1_ppsclk: eth0m1-ppsclk { ++ rockchip,pins = ++ /* eth0m1_ppsclk */ ++ <2 RK_PC1 3 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ eth0m1_ppstrig: eth0m1-ppstrig { ++ rockchip,pins = ++ /* eth0m1_ppstrig */ ++ <2 RK_PC2 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth1 { ++ /omit-if-no-ref/ ++ eth1m0_miim: eth1m0-miim { ++ rockchip,pins = ++ /* eth1_mdc_m0 */ ++ <2 RK_PD4 2 &pcfg_pull_none>, ++ /* eth1_mdio_m0 */ ++ <2 RK_PD5 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m0_rx_bus2: eth1m0-rx_bus2 { ++ rockchip,pins = ++ /* eth1_rxctl_m0 */ ++ <2 RK_PD3 2 &pcfg_pull_none>, ++ /* eth1_rxd0_m0 */ ++ <2 RK_PD1 2 &pcfg_pull_none>, ++ /* eth1_rxd1_m0 */ ++ <2 RK_PD2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m0_tx_bus2: eth1m0-tx_bus2 { ++ rockchip,pins = ++ /* eth1_txctl_m0 */ ++ <2 RK_PD0 2 &pcfg_pull_none>, ++ /* eth1_txd0_m0 */ ++ <2 RK_PC6 2 &pcfg_pull_none>, ++ /* eth1_txd1_m0 */ ++ <2 RK_PC7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m0_rgmii_clk: eth1m0-rgmii_clk { ++ rockchip,pins = ++ /* eth1_rxclk_m0 */ ++ <2 RK_PC2 2 &pcfg_pull_none>, ++ /* eth1_txclk_m0 */ ++ <2 RK_PC5 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m0_rgmii_bus: eth1m0-rgmii_bus { ++ rockchip,pins = ++ /* eth1_rxd2_m0 */ ++ <2 RK_PC0 2 &pcfg_pull_none>, ++ /* eth1_rxd3_m0 */ ++ <2 RK_PC1 2 &pcfg_pull_none>, ++ /* eth1_txd2_m0 */ ++ <2 RK_PC3 2 &pcfg_pull_none>, ++ /* eth1_txd3_m0 */ ++ <2 RK_PC4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m0_mclk: eth1m0-mclk { ++ rockchip,pins = ++ /* eth1m0_mclk */ ++ <2 RK_PD7 2 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ eth1m0_ppsclk: eth1m0-ppsclk { ++ rockchip,pins = ++ /* eth1m0_ppsclk */ ++ <3 RK_PA2 2 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ eth1m0_ppstrig: eth1m0-ppstrig { ++ rockchip,pins = ++ /* eth1m0_ppstrig */ ++ <3 RK_PA1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m1_miim: eth1m1-miim { ++ rockchip,pins = ++ /* eth1_mdc_m1 */ ++ <1 RK_PD2 1 &pcfg_pull_none>, ++ /* eth1_mdio_m1 */ ++ <1 RK_PD3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m1_rx_bus2: eth1m1-rx_bus2 { ++ rockchip,pins = ++ /* eth1_rxctl_m1 */ ++ <1 RK_PD1 1 &pcfg_pull_none>, ++ /* eth1_rxd0_m1 */ ++ <1 RK_PC7 1 &pcfg_pull_none>, ++ /* eth1_rxd1_m1 */ ++ <1 RK_PD0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m1_tx_bus2: eth1m1-tx_bus2 { ++ rockchip,pins = ++ /* eth1_txctl_m1 */ ++ <1 RK_PC6 1 &pcfg_pull_none>, ++ /* eth1_txd0_m1 */ ++ <1 RK_PC4 1 &pcfg_pull_none>, ++ /* eth1_txd1_m1 */ ++ <1 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m1_rgmii_clk: eth1m1-rgmii_clk { ++ rockchip,pins = ++ /* eth1_rxclk_m1 */ ++ <1 RK_PB6 1 &pcfg_pull_none>, ++ /* eth1_txclk_m1 */ ++ <1 RK_PC1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m1_rgmii_bus: eth1m1-rgmii_bus { ++ rockchip,pins = ++ /* eth1_rxd2_m1 */ ++ <1 RK_PB4 1 &pcfg_pull_none>, ++ /* eth1_rxd3_m1 */ ++ <1 RK_PB5 1 &pcfg_pull_none>, ++ /* eth1_txd2_m1 */ ++ <1 RK_PB7 1 &pcfg_pull_none>, ++ /* eth1_txd3_m1 */ ++ <1 RK_PC0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m1_mclk: eth1m1-mclk { ++ rockchip,pins = ++ /* eth1m1_mclk */ ++ <1 RK_PD4 1 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ eth1m1_ppsclk: eth1m1-ppsclk { ++ rockchip,pins = ++ /* eth1m1_ppsclk */ ++ <1 RK_PC2 1 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ eth1m1_ppstrig: eth1m1-ppstrig { ++ rockchip,pins = ++ /* eth1m1_ppstrig */ ++ <1 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth0_ptp { ++ /omit-if-no-ref/ ++ eth0m0_ptp_refclk: eth0m0-ptp-refclk { ++ rockchip,pins = ++ /* eth0m0_ptp_refclk */ ++ <3 RK_PC1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0m1_ptp_refclk: eth0m1-ptp-refclk { ++ rockchip,pins = ++ /* eth0m1_ptp_refclk */ ++ <2 RK_PC0 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth0_testrxclk { ++ /omit-if-no-ref/ ++ eth0_testrxclkm0_test: eth0_testrxclkm0-test { ++ rockchip,pins = ++ /* eth0_testrxclk_out_m0 */ ++ <3 RK_PC7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0_testrxclkm1_test: eth0_testrxclkm1-test { ++ rockchip,pins = ++ /* eth0_testrxclk_out_m1 */ ++ <2 RK_PC5 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth0_testrxd { ++ /omit-if-no-ref/ ++ eth0_testrxdm0_test: eth0_testrxdm0-test { ++ rockchip,pins = ++ /* eth0_testrxd_out_m0 */ ++ <3 RK_PD0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth0_testrxdm1_test: eth0_testrxdm1-test { ++ rockchip,pins = ++ /* eth0_testrxd_out_m1 */ ++ <2 RK_PC4 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth1_ptp { ++ /omit-if-no-ref/ ++ eth1m0_ptp_refclk: eth1m0-ptp-refclk { ++ rockchip,pins = ++ /* eth1m0_ptp_refclk */ ++ <3 RK_PA3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1m1_ptp_refclk: eth1m1-ptp-refclk { ++ rockchip,pins = ++ /* eth1m1_ptp_refclk */ ++ <2 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth1_testrxclk { ++ /omit-if-no-ref/ ++ eth1_testrxclkm0_test: eth1_testrxclkm0-test { ++ rockchip,pins = ++ /* eth1_testrxclk_out_m0 */ ++ <3 RK_PA1 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1_testrxclkm1_test: eth1_testrxclkm1-test { ++ rockchip,pins = ++ /* eth1_testrxclk_out_m1 */ ++ <1 RK_PC3 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth1_testrxd { ++ /omit-if-no-ref/ ++ eth1_testrxdm0_test: eth1_testrxdm0-test { ++ rockchip,pins = ++ /* eth1_testrxd_out_m0 */ ++ <3 RK_PA0 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ eth1_testrxdm1_test: eth1_testrxdm1-test { ++ rockchip,pins = ++ /* eth1_testrxd_out_m1 */ ++ <1 RK_PC2 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth_clk0_25m { ++ /omit-if-no-ref/ ++ ethm0_clk0_25m_out: ethm0-clk0-25m-out { ++ rockchip,pins = ++ /* ethm0_clk0_25m_out */ ++ <3 RK_PA4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ ethm1_clk0_25m_out: ethm1-clk0-25m-out { ++ rockchip,pins = ++ /* ethm1_clk0_25m_out */ ++ <2 RK_PD7 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth_clk1_25m { ++ /omit-if-no-ref/ ++ ethm0_clk1_25m_out: ethm0-clk1-25m-out { ++ rockchip,pins = ++ /* ethm0_clk1_25m_out */ ++ <2 RK_PD6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ ethm1_clk1_25m_out: ethm1-clk1-25m-out { ++ rockchip,pins = ++ /* ethm1_clk1_25m_out */ ++ <1 RK_PD5 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ flexbus0 { ++ /omit-if-no-ref/ ++ flexbus0m0_csn: flexbus0m0-csn { ++ rockchip,pins = ++ /* flexbus0_csn_m0 */ ++ <3 RK_PA4 8 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m0_d13: flexbus0m0-d13 { ++ rockchip,pins = ++ /* flexbus0_d13_m0 */ ++ <4 RK_PA0 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m0_d14: flexbus0m0-d14 { ++ rockchip,pins = ++ /* flexbus0_d14_m0 */ ++ <4 RK_PA1 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m0_d15: flexbus0m0-d15 { ++ rockchip,pins = ++ /* flexbus0_d15_m0 */ ++ <3 RK_PD7 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m1_csn: flexbus0m1-csn { ++ rockchip,pins = ++ /* flexbus0_csn_m1 */ ++ <4 RK_PA1 8 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m1_d13: flexbus0m1-d13 { ++ rockchip,pins = ++ /* flexbus0_d13_m1 */ ++ <4 RK_PA4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m1_d14: flexbus0m1-d14 { ++ rockchip,pins = ++ /* flexbus0_d14_m1 */ ++ <4 RK_PA6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m1_d15: flexbus0m1-d15 { ++ rockchip,pins = ++ /* flexbus0_d15_m1 */ ++ <4 RK_PB5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m2_csn: flexbus0m2-csn { ++ rockchip,pins = ++ /* flexbus0_csn_m2 */ ++ <3 RK_PC3 8 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m3_csn: flexbus0m3-csn { ++ rockchip,pins = ++ /* flexbus0_csn_m3 */ ++ <3 RK_PD2 8 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0m4_csn: flexbus0m4-csn { ++ rockchip,pins = ++ /* flexbus0_csn_m4 */ ++ <4 RK_PB4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_clk: flexbus0-clk { ++ rockchip,pins = ++ /* flexbus0_clk */ ++ <3 RK_PB6 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d10: flexbus0-d10 { ++ rockchip,pins = ++ /* flexbus0_d10 */ ++ <3 RK_PC3 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d11: flexbus0-d11 { ++ rockchip,pins = ++ /* flexbus0_d11 */ ++ <3 RK_PD1 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d12: flexbus0-d12 { ++ rockchip,pins = ++ /* flexbus0_d12 */ ++ <3 RK_PD2 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d0: flexbus0-d0 { ++ rockchip,pins = ++ /* flexbus0_d0 */ ++ <3 RK_PB5 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d1: flexbus0-d1 { ++ rockchip,pins = ++ /* flexbus0_d1 */ ++ <3 RK_PB4 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d2: flexbus0-d2 { ++ rockchip,pins = ++ /* flexbus0_d2 */ ++ <3 RK_PB3 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d3: flexbus0-d3 { ++ rockchip,pins = ++ /* flexbus0_d3 */ ++ <3 RK_PB2 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d4: flexbus0-d4 { ++ rockchip,pins = ++ /* flexbus0_d4 */ ++ <3 RK_PB1 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d5: flexbus0-d5 { ++ rockchip,pins = ++ /* flexbus0_d5 */ ++ <3 RK_PA7 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d6: flexbus0-d6 { ++ rockchip,pins = ++ /* flexbus0_d6 */ ++ <3 RK_PA6 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d7: flexbus0-d7 { ++ rockchip,pins = ++ /* flexbus0_d7 */ ++ <3 RK_PA5 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d8: flexbus0-d8 { ++ rockchip,pins = ++ /* flexbus0_d8 */ ++ <3 RK_PB0 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus0_d9: flexbus0-d9 { ++ rockchip,pins = ++ /* flexbus0_d9 */ ++ <3 RK_PC2 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ flexbus1 { ++ /omit-if-no-ref/ ++ flexbus1m0_csn: flexbus1m0-csn { ++ rockchip,pins = ++ /* flexbus1_csn_m0 */ ++ <3 RK_PB7 8 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m0_d12: flexbus1m0-d12 { ++ rockchip,pins = ++ /* flexbus1_d12_m0 */ ++ <3 RK_PD7 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m0_d13: flexbus1m0-d13 { ++ rockchip,pins = ++ /* flexbus1_d13_m0 */ ++ <4 RK_PA1 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m0_d14: flexbus1m0-d14 { ++ rockchip,pins = ++ /* flexbus1_d14_m0 */ ++ <4 RK_PA0 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m0_d15: flexbus1m0-d15 { ++ rockchip,pins = ++ /* flexbus1_d15_m0 */ ++ <3 RK_PD2 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m1_csn: flexbus1m1-csn { ++ rockchip,pins = ++ /* flexbus1_csn_m1 */ ++ <3 RK_PD7 8 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m1_d12: flexbus1m1-d12 { ++ rockchip,pins = ++ /* flexbus1_d12_m1 */ ++ <4 RK_PA5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m1_d13: flexbus1m1-d13 { ++ rockchip,pins = ++ /* flexbus1_d13_m1 */ ++ <4 RK_PB0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m1_d14: flexbus1m1-d14 { ++ rockchip,pins = ++ /* flexbus1_d14_m1 */ ++ <4 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m1_d15: flexbus1m1-d15 { ++ rockchip,pins = ++ /* flexbus1_d15_m1 */ ++ <4 RK_PB2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m2_csn: flexbus1m2-csn { ++ rockchip,pins = ++ /* flexbus1_csn_m2 */ ++ <3 RK_PD1 8 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m3_csn: flexbus1m3-csn { ++ rockchip,pins = ++ /* flexbus1_csn_m3 */ ++ <4 RK_PA0 8 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1m4_csn: flexbus1m4-csn { ++ rockchip,pins = ++ /* flexbus1_csn_m4 */ ++ <4 RK_PA3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_clk: flexbus1-clk { ++ rockchip,pins = ++ /* flexbus1_clk */ ++ <3 RK_PD6 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d10: flexbus1-d10 { ++ rockchip,pins = ++ /* flexbus1_d10 */ ++ <3 RK_PB7 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d11: flexbus1-d11 { ++ rockchip,pins = ++ /* flexbus1_d11 */ ++ <3 RK_PA4 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d0: flexbus1-d0 { ++ rockchip,pins = ++ /* flexbus1_d0 */ ++ <3 RK_PD5 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d1: flexbus1-d1 { ++ rockchip,pins = ++ /* flexbus1_d1 */ ++ <3 RK_PD4 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d2: flexbus1-d2 { ++ rockchip,pins = ++ /* flexbus1_d2 */ ++ <3 RK_PD3 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d3: flexbus1-d3 { ++ rockchip,pins = ++ /* flexbus1_d3 */ ++ <3 RK_PD0 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d4: flexbus1-d4 { ++ rockchip,pins = ++ /* flexbus1_d4 */ ++ <3 RK_PC7 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d5: flexbus1-d5 { ++ rockchip,pins = ++ /* flexbus1_d5 */ ++ <3 RK_PC6 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d6: flexbus1-d6 { ++ rockchip,pins = ++ /* flexbus1_d6 */ ++ <3 RK_PC5 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d7: flexbus1-d7 { ++ rockchip,pins = ++ /* flexbus1_d7 */ ++ <3 RK_PC4 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d8: flexbus1-d8 { ++ rockchip,pins = ++ /* flexbus1_d8 */ ++ <3 RK_PC1 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ flexbus1_d9: flexbus1-d9 { ++ rockchip,pins = ++ /* flexbus1_d9 */ ++ <3 RK_PC0 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ flexbus0_testclk { ++ /omit-if-no-ref/ ++ flexbus0_testclk_testclk: flexbus0_testclk-testclk { ++ rockchip,pins = ++ /* flexbus0_testclk_out */ ++ <2 RK_PA3 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ flexbus0_testdata { ++ /omit-if-no-ref/ ++ flexbus0_testdata_testdata: flexbus0_testdata-testdata { ++ rockchip,pins = ++ /* flexbus0_testdata_out */ ++ <2 RK_PA2 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ flexbus1_testclk { ++ /omit-if-no-ref/ ++ flexbus1_testclk_testclk: flexbus1_testclk-testclk { ++ rockchip,pins = ++ /* flexbus1_testclk_out */ ++ <2 RK_PA5 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ flexbus1_testdata { ++ /omit-if-no-ref/ ++ flexbus1_testdata_testdata: flexbus1_testdata-testdata { ++ rockchip,pins = ++ /* flexbus1_testdata_out */ ++ <2 RK_PA4 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ fspi0 { ++ /omit-if-no-ref/ ++ fspi0_pins: fspi0-pins { ++ rockchip,pins = ++ /* fspi0_clk */ ++ <1 RK_PB1 2 &pcfg_pull_none>, ++ /* fspi0_d0 */ ++ <1 RK_PA0 2 &pcfg_pull_none>, ++ /* fspi0_d1 */ ++ <1 RK_PA1 2 &pcfg_pull_none>, ++ /* fspi0_d2 */ ++ <1 RK_PA2 2 &pcfg_pull_none>, ++ /* fspi0_d3 */ ++ <1 RK_PA3 2 &pcfg_pull_none>, ++ /* fspi0_d4 */ ++ <1 RK_PA4 2 &pcfg_pull_none>, ++ /* fspi0_d5 */ ++ <1 RK_PA5 2 &pcfg_pull_none>, ++ /* fspi0_d6 */ ++ <1 RK_PA6 2 &pcfg_pull_none>, ++ /* fspi0_d7 */ ++ <1 RK_PA7 2 &pcfg_pull_none>, ++ /* fspi0_dqs */ ++ <1 RK_PB2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspi0_csn0: fspi0-csn0 { ++ rockchip,pins = ++ /* fspi0_csn0 */ ++ <1 RK_PB3 2 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ fspi0_csn1: fspi0-csn1 { ++ rockchip,pins = ++ /* fspi0_csn1 */ ++ <1 RK_PB0 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ fspi1 { ++ /omit-if-no-ref/ ++ fspi1m0_pins: fspi1m0-pins { ++ rockchip,pins = ++ /* fspi1_clk_m0 */ ++ <2 RK_PA5 2 &pcfg_pull_none>, ++ /* fspi1_d0_m0 */ ++ <2 RK_PA0 2 &pcfg_pull_none>, ++ /* fspi1_d1_m0 */ ++ <2 RK_PA1 2 &pcfg_pull_none>, ++ /* fspi1_d2_m0 */ ++ <2 RK_PA2 2 &pcfg_pull_none>, ++ /* fspi1_d3_m0 */ ++ <2 RK_PA3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspi1m0_csn0: fspi1m0-csn0 { ++ rockchip,pins = ++ /* fspi1m0_csn0 */ ++ <2 RK_PA4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspi1m1_pins: fspi1m1-pins { ++ rockchip,pins = ++ /* fspi1_clk_m1 */ ++ <1 RK_PD5 3 &pcfg_pull_none>, ++ /* fspi1_d0_m1 */ ++ <1 RK_PC4 3 &pcfg_pull_none>, ++ /* fspi1_d1_m1 */ ++ <1 RK_PC5 3 &pcfg_pull_none>, ++ /* fspi1_d2_m1 */ ++ <1 RK_PC6 3 &pcfg_pull_none>, ++ /* fspi1_d3_m1 */ ++ <1 RK_PC7 3 &pcfg_pull_none>, ++ /* fspi1_d4_m1 */ ++ <1 RK_PD0 3 &pcfg_pull_none>, ++ /* fspi1_d5_m1 */ ++ <1 RK_PD1 3 &pcfg_pull_none>, ++ /* fspi1_d6_m1 */ ++ <1 RK_PD2 3 &pcfg_pull_none>, ++ /* fspi1_d7_m1 */ ++ <1 RK_PD3 3 &pcfg_pull_none>, ++ /* fspi1_dqs_m1 */ ++ <1 RK_PD4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspi1m1_csn0: fspi1m1-csn0 { ++ rockchip,pins = ++ /* fspi1m1_csn0 */ ++ <1 RK_PC3 3 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ fspi1m1_csn1: fspi1m1-csn1 { ++ rockchip,pins = ++ /* fspi1m1_csn1 */ ++ <1 RK_PC2 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ fspi0_testclk { ++ /omit-if-no-ref/ ++ fspi0_testclk_test: fspi0_testclk-test { ++ rockchip,pins = ++ /* fspi0_testclk_out */ ++ <1 RK_PB0 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ fspi0_testdata { ++ /omit-if-no-ref/ ++ fspi0_testdata_test: fspi0_testdata-test { ++ rockchip,pins = ++ /* fspi0_testdata_out */ ++ <1 RK_PB7 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ fspi1_testclk { ++ /omit-if-no-ref/ ++ fspi1_testclkm1_test: fspi1_testclkm1-test { ++ rockchip,pins = ++ /* fspi1_testclk_out_m1 */ ++ <1 RK_PC1 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ fspi1_testdata { ++ /omit-if-no-ref/ ++ fspi1_testdatam1_test: fspi1_testdatam1-test { ++ rockchip,pins = ++ /* fspi1_testdata_out_m1 */ ++ <1 RK_PB7 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ gpu { ++ /omit-if-no-ref/ ++ gpu_pins: gpu-pins { ++ rockchip,pins = ++ /* gpu_avs */ ++ <0 RK_PD3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ hdmi_tx { ++ /omit-if-no-ref/ ++ hdmi_txm0_pins: hdmi_txm0-pins { ++ rockchip,pins = ++ /* hdmi_tx_cec_m0 */ ++ <4 RK_PC0 9 &pcfg_pull_none>, ++ /* hdmi_tx_hpdin_m0 */ ++ <4 RK_PC1 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_txm1_pins: hdmi_txm1-pins { ++ rockchip,pins = ++ /* hdmi_tx_cec_m1 */ ++ <0 RK_PC3 9 &pcfg_pull_none>, ++ /* hdmi_tx_hpdin_m1 */ ++ <0 RK_PB6 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_tx_scl: hdmi-tx-scl { ++ rockchip,pins = ++ /* hdmi_tx_scl */ ++ <4 RK_PC2 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ hdmi_tx_sda: hdmi-tx-sda { ++ rockchip,pins = ++ /* hdmi_tx_sda */ ++ <4 RK_PC3 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2c0 { ++ /omit-if-no-ref/ ++ i2c0m0_xfer: i2c0m0-xfer { ++ rockchip,pins = ++ /* i2c0_scl_m0 */ ++ <0 RK_PB0 11 &pcfg_pull_none_smt>, ++ /* i2c0_sda_m0 */ ++ <0 RK_PB1 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c0m1_xfer: i2c0m1-xfer { ++ rockchip,pins = ++ /* i2c0_scl_m1 */ ++ <0 RK_PC1 9 &pcfg_pull_none_smt>, ++ /* i2c0_sda_m1 */ ++ <0 RK_PC2 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c1 { ++ /omit-if-no-ref/ ++ i2c1m0_xfer: i2c1m0-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m0 */ ++ <0 RK_PB2 11 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m0 */ ++ <0 RK_PB3 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c1m1_xfer: i2c1m1-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m1 */ ++ <0 RK_PB4 9 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m1 */ ++ <0 RK_PB5 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c2 { ++ /omit-if-no-ref/ ++ i2c2m0_xfer: i2c2m0-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m0 */ ++ <0 RK_PB7 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m0 */ ++ <0 RK_PC0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2m1_xfer: i2c2m1-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m1 */ ++ <1 RK_PA0 10 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m1 */ ++ <1 RK_PA1 10 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2m2_xfer: i2c2m2-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m2 */ ++ <4 RK_PA3 11 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m2 */ ++ <4 RK_PA5 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2m3_xfer: i2c2m3-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m3 */ ++ <4 RK_PC2 11 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m3 */ ++ <4 RK_PC3 11 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c3 { ++ /omit-if-no-ref/ ++ i2c3m0_xfer: i2c3m0-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m0 */ ++ <4 RK_PB5 11 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m0 */ ++ <4 RK_PB4 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3m1_xfer: i2c3m1-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m1 */ ++ <0 RK_PC6 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m1 */ ++ <0 RK_PC7 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3m2_xfer: i2c3m2-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m2 */ ++ <3 RK_PD4 11 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m2 */ ++ <3 RK_PD5 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3m3_xfer: i2c3m3-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m3 */ ++ <4 RK_PC4 11 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m3 */ ++ <4 RK_PC5 11 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c4 { ++ /omit-if-no-ref/ ++ i2c4m0_xfer: i2c4m0-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m0 */ ++ <0 RK_PD2 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m0 */ ++ <0 RK_PD3 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4m1_xfer: i2c4m1-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m1 */ ++ <4 RK_PA4 11 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m1 */ ++ <4 RK_PA6 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4m2_xfer: i2c4m2-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m2 */ ++ <2 RK_PA6 11 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m2 */ ++ <2 RK_PA7 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4m3_xfer: i2c4m3-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m3 */ ++ <3 RK_PC0 11 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m3 */ ++ <3 RK_PB7 11 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c5 { ++ /omit-if-no-ref/ ++ i2c5m0_xfer: i2c5m0-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m0 */ ++ <2 RK_PA5 11 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m0 */ ++ <2 RK_PA4 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c5m1_xfer: i2c5m1-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m1 */ ++ <1 RK_PD4 10 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m1 */ ++ <1 RK_PD5 10 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c5m2_xfer: i2c5m2-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m2 */ ++ <2 RK_PC6 11 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m2 */ ++ <2 RK_PC7 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c5m3_xfer: i2c5m3-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m3 */ ++ <3 RK_PC4 11 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m3 */ ++ <3 RK_PC1 11 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c6 { ++ /omit-if-no-ref/ ++ i2c6m0_xfer: i2c6m0-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m0 */ ++ <0 RK_PA2 11 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m0 */ ++ <0 RK_PA5 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c6m1_xfer: i2c6m1-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m1 */ ++ <1 RK_PC2 10 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m1 */ ++ <1 RK_PC3 10 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c6m2_xfer: i2c6m2-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m2 */ ++ <2 RK_PD0 11 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m2 */ ++ <2 RK_PD1 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c6m3_xfer: i2c6m3-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m3 */ ++ <4 RK_PC6 11 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m3 */ ++ <4 RK_PC7 11 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c7 { ++ /omit-if-no-ref/ ++ i2c7m0_xfer: i2c7m0-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m0 */ ++ <1 RK_PB0 10 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m0 */ ++ <1 RK_PB3 10 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c7m1_xfer: i2c7m1-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m1 */ ++ <3 RK_PA0 11 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m1 */ ++ <3 RK_PA1 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c7m2_xfer: i2c7m2-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m2 */ ++ <4 RK_PA0 11 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m2 */ ++ <4 RK_PA1 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c7m3_xfer: i2c7m3-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m3 */ ++ <4 RK_PC0 11 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m3 */ ++ <4 RK_PC1 11 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c8 { ++ /omit-if-no-ref/ ++ i2c8m0_xfer: i2c8m0-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m0 */ ++ <2 RK_PA0 11 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m0 */ ++ <2 RK_PA1 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c8m1_xfer: i2c8m1-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m1 */ ++ <1 RK_PC6 10 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m1 */ ++ <1 RK_PC7 10 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c8m2_xfer: i2c8m2-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m2 */ ++ <2 RK_PB6 11 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m2 */ ++ <2 RK_PB7 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c8m3_xfer: i2c8m3-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m3 */ ++ <3 RK_PB3 11 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m3 */ ++ <3 RK_PB2 11 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c9 { ++ /omit-if-no-ref/ ++ i2c9m0_xfer: i2c9m0-xfer { ++ rockchip,pins = ++ /* i2c9_scl_m0 */ ++ <1 RK_PA5 10 &pcfg_pull_none_smt>, ++ /* i2c9_sda_m0 */ ++ <1 RK_PA6 10 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c9m1_xfer: i2c9m1-xfer { ++ rockchip,pins = ++ /* i2c9_scl_m1 */ ++ <1 RK_PB5 10 &pcfg_pull_none_smt>, ++ /* i2c9_sda_m1 */ ++ <1 RK_PB4 10 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c9m2_xfer: i2c9m2-xfer { ++ rockchip,pins = ++ /* i2c9_scl_m2 */ ++ <2 RK_PD5 11 &pcfg_pull_none_smt>, ++ /* i2c9_sda_m2 */ ++ <2 RK_PD4 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c9m3_xfer: i2c9m3-xfer { ++ rockchip,pins = ++ /* i2c9_scl_m3 */ ++ <3 RK_PC2 11 &pcfg_pull_none_smt>, ++ /* i2c9_sda_m3 */ ++ <3 RK_PC3 11 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i3c0 { ++ /omit-if-no-ref/ ++ i3c0m0_xfer: i3c0m0-xfer { ++ rockchip,pins = ++ /* i3c0_scl_m0 */ ++ <0 RK_PC1 11 &pcfg_pull_none_smt>, ++ /* i3c0_sda_m0 */ ++ <0 RK_PC2 11 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i3c0m1_xfer: i3c0m1-xfer { ++ rockchip,pins = ++ /* i3c0_scl_m1 */ ++ <1 RK_PD2 10 &pcfg_pull_none_smt>, ++ /* i3c0_sda_m1 */ ++ <1 RK_PD3 10 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i3c1 { ++ /omit-if-no-ref/ ++ i3c1m0_xfer: i3c1m0-xfer { ++ rockchip,pins = ++ /* i3c1_scl_m0 */ ++ <2 RK_PD2 12 &pcfg_pull_none_smt>, ++ /* i3c1_sda_m0 */ ++ <2 RK_PD3 12 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i3c1m1_xfer: i3c1m1-xfer { ++ rockchip,pins = ++ /* i3c1_scl_m1 */ ++ <2 RK_PA2 14 &pcfg_pull_none_smt>, ++ /* i3c1_sda_m1 */ ++ <2 RK_PA3 14 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i3c1m2_xfer: i3c1m2-xfer { ++ rockchip,pins = ++ /* i3c1_scl_m2 */ ++ <3 RK_PD3 11 &pcfg_pull_none_smt>, ++ /* i3c1_sda_m2 */ ++ <3 RK_PD2 11 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i3c0_sda { ++ /omit-if-no-ref/ ++ i3c0_sdam0_pu: i3c0_sdam0-pu { ++ rockchip,pins = ++ /* i3c0_sda_pu_m0 */ ++ <0 RK_PC5 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i3c0_sdam1_pu: i3c0_sdam1-pu { ++ rockchip,pins = ++ /* i3c0_sda_pu_m1 */ ++ <1 RK_PD1 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i3c1_sda { ++ /omit-if-no-ref/ ++ i3c1_sdam0_pu: i3c1_sdam0-pu { ++ rockchip,pins = ++ /* i3c1_sda_pu_m0 */ ++ <2 RK_PD6 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i3c1_sdam1_pu: i3c1_sdam1-pu { ++ rockchip,pins = ++ /* i3c1_sda_pu_m1 */ ++ <2 RK_PA5 14 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i3c1_sdam2_pu: i3c1_sdam2-pu { ++ rockchip,pins = ++ /* i3c1_sda_pu_m2 */ ++ <3 RK_PD1 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ isp_flash { ++ /omit-if-no-ref/ ++ isp_flashm0_pins: isp_flashm0-pins { ++ rockchip,pins = ++ /* isp_flash_trigout_m0 */ ++ <2 RK_PD5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ isp_flashm1_pins: isp_flashm1-pins { ++ rockchip,pins = ++ /* isp_flash_trigout_m1 */ ++ <4 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ isp_prelight { ++ /omit-if-no-ref/ ++ isp_prelightm0_pins: isp_prelightm0-pins { ++ rockchip,pins = ++ /* isp_prelight_trig_m0 */ ++ <2 RK_PD4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ isp_prelightm1_pins: isp_prelightm1-pins { ++ rockchip,pins = ++ /* isp_prelight_trig_m1 */ ++ <4 RK_PC4 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ jtag { ++ /omit-if-no-ref/ ++ jtagm0_pins: jtagm0-pins { ++ rockchip,pins = ++ /* jtag_tck_m0 */ ++ <2 RK_PA2 9 &pcfg_pull_none>, ++ /* jtag_tms_m0 */ ++ <2 RK_PA3 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ jtagm1_pins: jtagm1-pins { ++ rockchip,pins = ++ /* jtag_tck_m1 */ ++ <0 RK_PD4 10 &pcfg_pull_none>, ++ /* jtag_tms_m1 */ ++ <0 RK_PD5 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ mipi { ++ /omit-if-no-ref/ ++ mipim0_pins: mipim0-pins { ++ rockchip,pins = ++ /* mipi_te_m0 */ ++ <4 RK_PB2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_pins: mipim1-pins { ++ rockchip,pins = ++ /* mipi_te_m1 */ ++ <3 RK_PA2 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim2_pins: mipim2-pins { ++ rockchip,pins = ++ /* mipi_te_m2 */ ++ <4 RK_PA0 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim3_pins: mipim3-pins { ++ rockchip,pins = ++ /* mipi_te_m3 */ ++ <1 RK_PB3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ npu { ++ /omit-if-no-ref/ ++ npu_pins: npu-pins { ++ rockchip,pins = ++ /* npu_avs */ ++ <0 RK_PB7 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie0 { ++ /omit-if-no-ref/ ++ pcie0m0_pins: pcie0m0-pins { ++ rockchip,pins = ++ /* pcie21_port0_clkreq_m0 */ ++ <2 RK_PB2 11 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie0m1_pins: pcie0m1-pins { ++ rockchip,pins = ++ /* pcie0_clkreq_m1 */ ++ <1 RK_PB6 12 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie0m2_pins: pcie0m2-pins { ++ rockchip,pins = ++ /* pcie0_clkreq_m2 */ ++ <4 RK_PB5 12 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie0m3_pins: pcie0m3-pins { ++ rockchip,pins = ++ /* pcie0_clkreq_m3 */ ++ <4 RK_PC6 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie0_buttonrst: pcie21-port0-buttonrst { ++ rockchip,pins = ++ /* pcie0_buttonrst */ ++ <1 RK_PC4 12 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie1 { ++ /omit-if-no-ref/ ++ pcie1m0_pins: pcie1m0-pins { ++ rockchip,pins = ++ /* pcie1_clkreq_m0 */ ++ <2 RK_PB3 11 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie1m1_pins: pcie1m1-pins { ++ rockchip,pins = ++ /* pcie1_clkreq_m1 */ ++ <1 RK_PB4 12 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie1m2_pins: pcie1m2-pins { ++ rockchip,pins = ++ /* pcie1_clkreq_m2 */ ++ <4 RK_PA5 12 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie1m3_pins: pcie1m3-pins { ++ rockchip,pins = ++ /* pcie1_clkreq_m3 */ ++ <4 RK_PC1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie1_buttonrst: pcie21-port1-buttonrst { ++ rockchip,pins = ++ /* pcie1_buttonrst */ ++ <1 RK_PC5 12 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pdm0 { ++ /omit-if-no-ref/ ++ pdm0m0_clk0: pdm0m0-clk0 { ++ rockchip,pins = ++ /* pdm0_clk0_m0 */ ++ <0 RK_PC4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_clk1: pdm0m0-clk1 { ++ rockchip,pins = ++ /* pdm0_clk1_m0 */ ++ <0 RK_PC3 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi0: pdm0m0-sdi0 { ++ rockchip,pins = ++ /* pdm0_sdi0_m0 */ ++ <0 RK_PD0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi1: pdm0m0-sdi1 { ++ rockchip,pins = ++ /* pdm0_sdi1_m0 */ ++ <0 RK_PD1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi2: pdm0m0-sdi2 { ++ rockchip,pins = ++ /* pdm0_sdi2_m0 */ ++ <0 RK_PD2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi3: pdm0m0-sdi3 { ++ rockchip,pins = ++ /* pdm0_sdi3_m0 */ ++ <0 RK_PD3 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_clk0: pdm0m1-clk0 { ++ rockchip,pins = ++ /* pdm0_clk0_m1 */ ++ <1 RK_PB1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_clk1: pdm0m1-clk1 { ++ rockchip,pins = ++ /* pdm0_clk1_m1 */ ++ <1 RK_PA6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi0: pdm0m1-sdi0 { ++ rockchip,pins = ++ /* pdm0_sdi0_m1 */ ++ <1 RK_PB2 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi1: pdm0m1-sdi1 { ++ rockchip,pins = ++ /* pdm0_sdi1_m1 */ ++ <1 RK_PA3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi2: pdm0m1-sdi2 { ++ rockchip,pins = ++ /* pdm0_sdi2_m1 */ ++ <1 RK_PA5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi3: pdm0m1-sdi3 { ++ rockchip,pins = ++ /* pdm0_sdi3_m1 */ ++ <1 RK_PA2 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m2_clk0: pdm0m2-clk0 { ++ rockchip,pins = ++ /* pdm0_clk0_m2 */ ++ <1 RK_PC1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m2_clk1: pdm0m2-clk1 { ++ rockchip,pins = ++ /* pdm0_clk1_m2 */ ++ <1 RK_PD5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m2_sdi0: pdm0m2-sdi0 { ++ rockchip,pins = ++ /* pdm0_sdi0_m2 */ ++ <1 RK_PC6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m2_sdi1: pdm0m2-sdi1 { ++ rockchip,pins = ++ /* pdm0_sdi1_m2 */ ++ <1 RK_PC7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m2_sdi2: pdm0m2-sdi2 { ++ rockchip,pins = ++ /* pdm0_sdi2_m2 */ ++ <1 RK_PC0 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m2_sdi3: pdm0m2-sdi3 { ++ rockchip,pins = ++ /* pdm0_sdi3_m2 */ ++ <1 RK_PD4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m3_clk0: pdm0m3-clk0 { ++ rockchip,pins = ++ /* pdm0_clk0_m3 */ ++ <2 RK_PB5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m3_clk1: pdm0m3-clk1 { ++ rockchip,pins = ++ /* pdm0_clk1_m3 */ ++ <2 RK_PB3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m3_sdi0: pdm0m3-sdi0 { ++ rockchip,pins = ++ /* pdm0_sdi0_m3 */ ++ <2 RK_PB4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m3_sdi1: pdm0m3-sdi1 { ++ rockchip,pins = ++ /* pdm0_sdi1_m3 */ ++ <2 RK_PB2 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m3_sdi2: pdm0m3-sdi2 { ++ rockchip,pins = ++ /* pdm0_sdi2_m3 */ ++ <2 RK_PB1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m3_sdi3: pdm0m3-sdi3 { ++ rockchip,pins = ++ /* pdm0_sdi3_m3 */ ++ <2 RK_PB0 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pdm1 { ++ /omit-if-no-ref/ ++ pdm1m0_clk0: pdm1m0-clk0 { ++ rockchip,pins = ++ /* pdm1_clk0_m0 */ ++ <2 RK_PC5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_clk1: pdm1m0-clk1 { ++ rockchip,pins = ++ /* pdm1_clk1_m0 */ ++ <2 RK_PC1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi0: pdm1m0-sdi0 { ++ rockchip,pins = ++ /* pdm1_sdi0_m0 */ ++ <2 RK_PC4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi1: pdm1m0-sdi1 { ++ rockchip,pins = ++ /* pdm1_sdi1_m0 */ ++ <2 RK_PC0 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi2: pdm1m0-sdi2 { ++ rockchip,pins = ++ /* pdm1_sdi2_m0 */ ++ <2 RK_PC2 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi3: pdm1m0-sdi3 { ++ rockchip,pins = ++ /* pdm1_sdi3_m0 */ ++ <2 RK_PC3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_clk0: pdm1m1-clk0 { ++ rockchip,pins = ++ /* pdm1_clk0_m1 */ ++ <4 RK_PA6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_clk1: pdm1m1-clk1 { ++ rockchip,pins = ++ /* pdm1_clk1_m1 */ ++ <4 RK_PB0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi0: pdm1m1-sdi0 { ++ rockchip,pins = ++ /* pdm1_sdi0_m1 */ ++ <4 RK_PB3 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi1: pdm1m1-sdi1 { ++ rockchip,pins = ++ /* pdm1_sdi1_m1 */ ++ <4 RK_PB2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi2: pdm1m1-sdi2 { ++ rockchip,pins = ++ /* pdm1_sdi2_m1 */ ++ <4 RK_PB1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi3: pdm1m1-sdi3 { ++ rockchip,pins = ++ /* pdm1_sdi3_m1 */ ++ <4 RK_PA4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m2_clk0: pdm1m2-clk0 { ++ rockchip,pins = ++ /* pdm1_clk0_m2 */ ++ <3 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m2_clk1: pdm1m2-clk1 { ++ rockchip,pins = ++ /* pdm1_clk1_m2 */ ++ <3 RK_PA7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m2_sdi0: pdm1m2-sdi0 { ++ rockchip,pins = ++ /* pdm1_sdi0_m2 */ ++ <3 RK_PB3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m2_sdi1: pdm1m2-sdi1 { ++ rockchip,pins = ++ /* pdm1_sdi1_m2 */ ++ <3 RK_PB2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m2_sdi2: pdm1m2-sdi2 { ++ rockchip,pins = ++ /* pdm1_sdi2_m2 */ ++ <3 RK_PA6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m2_sdi3: pdm1m2-sdi3 { ++ rockchip,pins = ++ /* pdm1_sdi3_m2 */ ++ <3 RK_PA5 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmu_debug_test { ++ /omit-if-no-ref/ ++ pmu_debug_test_pins: pmu_debug_test-pins { ++ rockchip,pins = ++ /* pmu_debug_test_out */ ++ <0 RK_PB0 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm0 { ++ /omit-if-no-ref/ ++ pwm0m0_ch0: pwm0m0-ch0 { ++ rockchip,pins = ++ /* pwm0_ch0_m0 */ ++ <0 RK_PC4 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m0_ch1: pwm0m0-ch1 { ++ rockchip,pins = ++ /* pwm0_ch1_m0 */ ++ <0 RK_PC3 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m1_ch0: pwm0m1-ch0 { ++ rockchip,pins = ++ /* pwm0_ch0_m1 */ ++ <1 RK_PC0 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m1_ch1: pwm0m1-ch1 { ++ rockchip,pins = ++ /* pwm0_ch1_m1 */ ++ <4 RK_PC1 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m2_ch0: pwm0m2-ch0 { ++ rockchip,pins = ++ /* pwm0_ch0_m2 */ ++ <2 RK_PC3 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m2_ch1: pwm0m2-ch1 { ++ rockchip,pins = ++ /* pwm0_ch1_m2 */ ++ <2 RK_PC7 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m3_ch0: pwm0m3-ch0 { ++ rockchip,pins = ++ /* pwm0_ch0_m3 */ ++ <3 RK_PB0 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m3_ch1: pwm0m3-ch1 { ++ rockchip,pins = ++ /* pwm0_ch1_m3 */ ++ <3 RK_PB6 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ }; ++ ++ pwm1 { ++ /omit-if-no-ref/ ++ pwm1m0_ch0: pwm1m0-ch0 { ++ rockchip,pins = ++ /* pwm1_ch0_m0 */ ++ <0 RK_PB4 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m0_ch1: pwm1m0-ch1 { ++ rockchip,pins = ++ /* pwm1_ch1_m0 */ ++ <0 RK_PB5 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m0_ch2: pwm1m0-ch2 { ++ rockchip,pins = ++ /* pwm1_ch2_m0 */ ++ <0 RK_PB6 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m0_ch3: pwm1m0-ch3 { ++ rockchip,pins = ++ /* pwm1_ch3_m0 */ ++ <0 RK_PC0 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m0_ch4: pwm1m0-ch4 { ++ rockchip,pins = ++ /* pwm1_ch4_m0 */ ++ <0 RK_PB7 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m0_ch5: pwm1m0-ch5 { ++ rockchip,pins = ++ /* pwm1_ch5_m0 */ ++ <0 RK_PD2 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m1_ch0: pwm1m1-ch0 { ++ rockchip,pins = ++ /* pwm1_ch0_m1 */ ++ <1 RK_PB4 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m1_ch1: pwm1m1-ch1 { ++ rockchip,pins = ++ /* pwm1_ch1_m1 */ ++ <1 RK_PB5 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m1_ch2: pwm1m1-ch2 { ++ rockchip,pins = ++ /* pwm1_ch2_m1 */ ++ <1 RK_PC2 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m1_ch3: pwm1m1-ch3 { ++ rockchip,pins = ++ /* pwm1_ch3_m1 */ ++ <1 RK_PD2 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m1_ch4: pwm1m1-ch4 { ++ rockchip,pins = ++ /* pwm1_ch4_m1 */ ++ <1 RK_PD3 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m1_ch5: pwm1m1-ch5 { ++ rockchip,pins = ++ /* pwm1_ch5_m1 */ ++ <4 RK_PC0 14 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m2_ch0: pwm1m2-ch0 { ++ rockchip,pins = ++ /* pwm1_ch0_m2 */ ++ <2 RK_PC0 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m2_ch1: pwm1m2-ch1 { ++ rockchip,pins = ++ /* pwm1_ch1_m2 */ ++ <2 RK_PC1 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m2_ch2: pwm1m2-ch2 { ++ rockchip,pins = ++ /* pwm1_ch2_m2 */ ++ <2 RK_PC2 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m2_ch3: pwm1m2-ch3 { ++ rockchip,pins = ++ /* pwm1_ch3_m2 */ ++ <2 RK_PC4 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m2_ch4: pwm1m2-ch4 { ++ rockchip,pins = ++ /* pwm1_ch4_m2 */ ++ <2 RK_PC5 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m2_ch5: pwm1m2-ch5 { ++ rockchip,pins = ++ /* pwm1_ch5_m2 */ ++ <2 RK_PC6 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m3_ch0: pwm1m3-ch0 { ++ rockchip,pins = ++ /* pwm1_ch0_m3 */ ++ <3 RK_PA4 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m3_ch1: pwm1m3-ch1 { ++ rockchip,pins = ++ /* pwm1_ch1_m3 */ ++ <3 RK_PA5 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m3_ch2: pwm1m3-ch2 { ++ rockchip,pins = ++ /* pwm1_ch2_m3 */ ++ <3 RK_PA6 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m3_ch3: pwm1m3-ch3 { ++ rockchip,pins = ++ /* pwm1_ch3_m3 */ ++ <3 RK_PB1 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m3_ch4: pwm1m3-ch4 { ++ rockchip,pins = ++ /* pwm1_ch4_m3 */ ++ <3 RK_PB4 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m3_ch5: pwm1m3-ch5 { ++ rockchip,pins = ++ /* pwm1_ch5_m3 */ ++ <3 RK_PB5 12 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm2 { ++ /omit-if-no-ref/ ++ pwm2m0_ch0: pwm2m0-ch0 { ++ rockchip,pins = ++ /* pwm2_ch0_m0 */ ++ <0 RK_PD3 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m0_ch1: pwm2m0-ch1 { ++ rockchip,pins = ++ /* pwm2_ch1_m0 */ ++ <1 RK_PB3 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m0_ch2: pwm2m0-ch2 { ++ rockchip,pins = ++ /* pwm2_ch2_m0 */ ++ <2 RK_PA0 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m0_ch3: pwm2m0-ch3 { ++ rockchip,pins = ++ /* pwm2_ch3_m0 */ ++ <2 RK_PA1 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m0_ch4: pwm2m0-ch4 { ++ rockchip,pins = ++ /* pwm2_ch4_m0 */ ++ <2 RK_PA4 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m0_ch5: pwm2m0-ch5 { ++ rockchip,pins = ++ /* pwm2_ch5_m0 */ ++ <4 RK_PA2 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m0_ch6: pwm2m0-ch6 { ++ rockchip,pins = ++ /* pwm2_ch6_m0 */ ++ <4 RK_PA7 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m0_ch7: pwm2m0-ch7 { ++ rockchip,pins = ++ /* pwm2_ch7_m0 */ ++ <4 RK_PB3 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_ch0: pwm2m1-ch0 { ++ rockchip,pins = ++ /* pwm2_ch0_m1 */ ++ <4 RK_PC2 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_ch1: pwm2m1-ch1 { ++ rockchip,pins = ++ /* pwm2_ch1_m1 */ ++ <4 RK_PC3 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_ch2: pwm2m1-ch2 { ++ rockchip,pins = ++ /* pwm2_ch2_m1 */ ++ <4 RK_PC6 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_ch3: pwm2m1-ch3 { ++ rockchip,pins = ++ /* pwm2_ch3_m1 */ ++ <4 RK_PC7 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_ch4: pwm2m1-ch4 { ++ rockchip,pins = ++ /* pwm2_ch4_m1 */ ++ <4 RK_PA3 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_ch5: pwm2m1-ch5 { ++ rockchip,pins = ++ /* pwm2_ch5_m1 */ ++ <4 RK_PC5 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_ch6: pwm2m1-ch6 { ++ rockchip,pins = ++ /* pwm2_ch6_m1 */ ++ <4 RK_PC4 14 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_ch7: pwm2m1-ch7 { ++ rockchip,pins = ++ /* pwm2_ch7_m1 */ ++ <1 RK_PB1 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m2_ch0: pwm2m2-ch0 { ++ rockchip,pins = ++ /* pwm2_ch0_m2 */ ++ <2 RK_PD0 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m2_ch1: pwm2m2-ch1 { ++ rockchip,pins = ++ /* pwm2_ch1_m2 */ ++ <2 RK_PD1 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m2_ch2: pwm2m2-ch2 { ++ rockchip,pins = ++ /* pwm2_ch2_m2 */ ++ <2 RK_PD2 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m2_ch3: pwm2m2-ch3 { ++ rockchip,pins = ++ /* pwm2_ch3_m2 */ ++ <2 RK_PD3 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m2_ch4: pwm2m2-ch4 { ++ rockchip,pins = ++ /* pwm2_ch4_m2 */ ++ <2 RK_PD4 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m2_ch5: pwm2m2-ch5 { ++ rockchip,pins = ++ /* pwm2_ch5_m2 */ ++ <2 RK_PD5 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m2_ch6: pwm2m2-ch6 { ++ rockchip,pins = ++ /* pwm2_ch6_m2 */ ++ <2 RK_PD6 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m2_ch7: pwm2m2-ch7 { ++ rockchip,pins = ++ /* pwm2_ch7_m2 */ ++ <2 RK_PD7 13 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m3_ch0: pwm2m3-ch0 { ++ rockchip,pins = ++ /* pwm2_ch0_m3 */ ++ <3 RK_PC2 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m3_ch1: pwm2m3-ch1 { ++ rockchip,pins = ++ /* pwm2_ch1_m3 */ ++ <3 RK_PC3 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m3_ch2: pwm2m3-ch2 { ++ rockchip,pins = ++ /* pwm2_ch2_m3 */ ++ <3 RK_PC5 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m3_ch3: pwm2m3-ch3 { ++ rockchip,pins = ++ /* pwm2_ch3_m3 */ ++ <3 RK_PD0 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m3_ch4: pwm2m3-ch4 { ++ rockchip,pins = ++ /* pwm2_ch4_m3 */ ++ <3 RK_PD2 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m3_ch5: pwm2m3-ch5 { ++ rockchip,pins = ++ /* pwm2_ch5_m3 */ ++ <3 RK_PD3 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m3_ch6: pwm2m3-ch6 { ++ rockchip,pins = ++ /* pwm2_ch6_m3 */ ++ <3 RK_PD6 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m3_ch7: pwm2m3-ch7 { ++ rockchip,pins = ++ /* pwm2_ch7_m3 */ ++ <3 RK_PD7 12 &pcfg_pull_none_drv_level_2>; ++ }; ++ }; ++ ++ ref_clk0 { ++ /omit-if-no-ref/ ++ ref_clk0_clk0: ref_clk0-clk0 { ++ rockchip,pins = ++ /* ref_clk0_out */ ++ <0 RK_PA0 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ref_clk1 { ++ /omit-if-no-ref/ ++ ref_clk1_clk1: ref_clk1-clk1 { ++ rockchip,pins = ++ /* ref_clk1_out */ ++ <0 RK_PB4 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ref_clk2 { ++ /omit-if-no-ref/ ++ ref_clk2_clk2: ref_clk2-clk2 { ++ rockchip,pins = ++ /* ref_clk2_out */ ++ <0 RK_PB5 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sai0 { ++ /omit-if-no-ref/ ++ sai0m0_lrck: sai0m0-lrck { ++ rockchip,pins = ++ /* sai0_lrck_m0 */ ++ <2 RK_PB7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_mclk: sai0m0-mclk { ++ rockchip,pins = ++ /* sai0_mclk_m0 */ ++ <2 RK_PB5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_sclk: sai0m0-sclk { ++ rockchip,pins = ++ /* sai0_sclk_m0 */ ++ <2 RK_PB6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_sdi0: sai0m0-sdi0 { ++ rockchip,pins = ++ /* sai0_sdi0_m0 */ ++ <2 RK_PB0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_sdi1: sai0m0-sdi1 { ++ rockchip,pins = ++ /* sai0_sdi1_m0 */ ++ <2 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_sdi2: sai0m0-sdi2 { ++ rockchip,pins = ++ /* sai0_sdi2_m0 */ ++ <2 RK_PB2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_sdi3: sai0m0-sdi3 { ++ rockchip,pins = ++ /* sai0_sdi3_m0 */ ++ <2 RK_PB4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_sdo0: sai0m0-sdo0 { ++ rockchip,pins = ++ /* sai0_sdo0_m0 */ ++ <2 RK_PA6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_sdo1: sai0m0-sdo1 { ++ rockchip,pins = ++ /* sai0_sdo1_m0 */ ++ <2 RK_PA7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_sdo2: sai0m0-sdo2 { ++ rockchip,pins = ++ /* sai0_sdo2_m0 */ ++ <2 RK_PB3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m0_sdo3: sai0m0-sdo3 { ++ rockchip,pins = ++ /* sai0_sdo3_m0 */ ++ <2 RK_PD7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_lrck: sai0m1-lrck { ++ rockchip,pins = ++ /* sai0_lrck_m1 */ ++ <0 RK_PC7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_mclk: sai0m1-mclk { ++ rockchip,pins = ++ /* sai0_mclk_m1 */ ++ <0 RK_PC4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_sclk: sai0m1-sclk { ++ rockchip,pins = ++ /* sai0_sclk_m1 */ ++ <0 RK_PC6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_sdi0: sai0m1-sdi0 { ++ rockchip,pins = ++ /* sai0_sdi0_m1 */ ++ <0 RK_PD0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_sdi1: sai0m1-sdi1 { ++ rockchip,pins = ++ /* sai0_sdi1_m1 */ ++ <0 RK_PD1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_sdi2: sai0m1-sdi2 { ++ rockchip,pins = ++ /* sai0_sdi2_m1 */ ++ <0 RK_PD2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_sdi3: sai0m1-sdi3 { ++ rockchip,pins = ++ /* sai0_sdi3_m1 */ ++ <0 RK_PD3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_sdo0: sai0m1-sdo0 { ++ rockchip,pins = ++ /* sai0_sdo0_m1 */ ++ <0 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_sdo1: sai0m1-sdo1 { ++ rockchip,pins = ++ /* sai0_sdo1_m1 */ ++ <0 RK_PD3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_sdo2: sai0m1-sdo2 { ++ rockchip,pins = ++ /* sai0_sdo2_m1 */ ++ <0 RK_PD2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m1_sdo3: sai0m1-sdo3 { ++ rockchip,pins = ++ /* sai0_sdo3_m1 */ ++ <0 RK_PD1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_lrck: sai0m2-lrck { ++ rockchip,pins = ++ /* sai0_lrck_m2 */ ++ <1 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_mclk: sai0m2-mclk { ++ rockchip,pins = ++ /* sai0_mclk_m2 */ ++ <1 RK_PA4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_sclk: sai0m2-sclk { ++ rockchip,pins = ++ /* sai0_sclk_m2 */ ++ <1 RK_PA0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_sdi0: sai0m2-sdi0 { ++ rockchip,pins = ++ /* sai0_sdi0_m2 */ ++ <1 RK_PB2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_sdi1: sai0m2-sdi1 { ++ rockchip,pins = ++ /* sai0_sdi1_m2 */ ++ <1 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_sdi2: sai0m2-sdi2 { ++ rockchip,pins = ++ /* sai0_sdi2_m2 */ ++ <1 RK_PA3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_sdi3: sai0m2-sdi3 { ++ rockchip,pins = ++ /* sai0_sdi3_m2 */ ++ <1 RK_PA2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_sdo0: sai0m2-sdo0 { ++ rockchip,pins = ++ /* sai0_sdo0_m2 */ ++ <1 RK_PA7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_sdo1: sai0m2-sdo1 { ++ rockchip,pins = ++ /* sai0_sdo1_m2 */ ++ <1 RK_PA2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_sdo2: sai0m2-sdo2 { ++ rockchip,pins = ++ /* sai0_sdo2_m2 */ ++ <1 RK_PA3 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai0m2_sdo3: sai0m2-sdo3 { ++ rockchip,pins = ++ /* sai0_sdo3_m2 */ ++ <1 RK_PB1 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sai1 { ++ /omit-if-no-ref/ ++ sai1m0_lrck: sai1m0-lrck { ++ rockchip,pins = ++ /* sai1_lrck_m0 */ ++ <4 RK_PA5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_mclk: sai1m0-mclk { ++ rockchip,pins = ++ /* sai1_mclk_m0 */ ++ <4 RK_PA2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_sclk: sai1m0-sclk { ++ rockchip,pins = ++ /* sai1_sclk_m0 */ ++ <4 RK_PA3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_sdi0: sai1m0-sdi0 { ++ rockchip,pins = ++ /* sai1_sdi0_m0 */ ++ <4 RK_PB3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_sdi1: sai1m0-sdi1 { ++ rockchip,pins = ++ /* sai1_sdi1_m0 */ ++ <4 RK_PB2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_sdi2: sai1m0-sdi2 { ++ rockchip,pins = ++ /* sai1_sdi2_m0 */ ++ <4 RK_PB1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_sdi3: sai1m0-sdi3 { ++ rockchip,pins = ++ /* sai1_sdi3_m0 */ ++ <4 RK_PB0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_sdo0: sai1m0-sdo0 { ++ rockchip,pins = ++ /* sai1_sdo0_m0 */ ++ <4 RK_PA7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_sdo1: sai1m0-sdo1 { ++ rockchip,pins = ++ /* sai1_sdo1_m0 */ ++ <4 RK_PB0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_sdo2: sai1m0-sdo2 { ++ rockchip,pins = ++ /* sai1_sdo2_m0 */ ++ <4 RK_PB1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m0_sdo3: sai1m0-sdo3 { ++ rockchip,pins = ++ /* sai1_sdo3_m0 */ ++ <4 RK_PB2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_lrck: sai1m1-lrck { ++ rockchip,pins = ++ /* sai1_lrck_m1 */ ++ <3 RK_PC6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_mclk: sai1m1-mclk { ++ rockchip,pins = ++ /* sai1_mclk_m1 */ ++ <3 RK_PD0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_sclk: sai1m1-sclk { ++ rockchip,pins = ++ /* sai1_sclk_m1 */ ++ <3 RK_PC7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_sdi0: sai1m1-sdi0 { ++ rockchip,pins = ++ /* sai1_sdi0_m1 */ ++ <3 RK_PB7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_sdi1: sai1m1-sdi1 { ++ rockchip,pins = ++ /* sai1_sdi1_m1 */ ++ <3 RK_PD4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_sdi2: sai1m1-sdi2 { ++ rockchip,pins = ++ /* sai1_sdi2_m1 */ ++ <3 RK_PD5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_sdi3: sai1m1-sdi3 { ++ rockchip,pins = ++ /* sai1_sdi3_m1 */ ++ <3 RK_PD6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_sdo0: sai1m1-sdo0 { ++ rockchip,pins = ++ /* sai1_sdo0_m1 */ ++ <3 RK_PC5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_sdo1: sai1m1-sdo1 { ++ rockchip,pins = ++ /* sai1_sdo1_m1 */ ++ <3 RK_PC4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_sdo2: sai1m1-sdo2 { ++ rockchip,pins = ++ /* sai1_sdo2_m1 */ ++ <3 RK_PC1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai1m1_sdo3: sai1m1-sdo3 { ++ rockchip,pins = ++ /* sai1_sdo3_m1 */ ++ <3 RK_PC0 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sai2 { ++ /omit-if-no-ref/ ++ sai2m0_lrck: sai2m0-lrck { ++ rockchip,pins = ++ /* sai2_lrck_m0 */ ++ <1 RK_PD2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m0_mclk: sai2m0-mclk { ++ rockchip,pins = ++ /* sai2_mclk_m0 */ ++ <1 RK_PD4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m0_sclk: sai2m0-sclk { ++ rockchip,pins = ++ /* sai2_sclk_m0 */ ++ <1 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m0_sdi: sai2m0-sdi { ++ rockchip,pins = ++ /* sai2m0_sdi */ ++ <1 RK_PD3 4 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai2m0_sdo: sai2m0-sdo { ++ rockchip,pins = ++ /* sai2m0_sdo */ ++ <1 RK_PD0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m1_lrck: sai2m1-lrck { ++ rockchip,pins = ++ /* sai2_lrck_m1 */ ++ <2 RK_PC3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m1_mclk: sai2m1-mclk { ++ rockchip,pins = ++ /* sai2_mclk_m1 */ ++ <2 RK_PC1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m1_sclk: sai2m1-sclk { ++ rockchip,pins = ++ /* sai2_sclk_m1 */ ++ <2 RK_PC2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m1_sdi: sai2m1-sdi { ++ rockchip,pins = ++ /* sai2m1_sdi */ ++ <2 RK_PC5 4 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai2m1_sdo: sai2m1-sdo { ++ rockchip,pins = ++ /* sai2m1_sdo */ ++ <2 RK_PC4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m2_lrck: sai2m2-lrck { ++ rockchip,pins = ++ /* sai2_lrck_m2 */ ++ <3 RK_PC3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m2_mclk: sai2m2-mclk { ++ rockchip,pins = ++ /* sai2_mclk_m2 */ ++ <3 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m2_sclk: sai2m2-sclk { ++ rockchip,pins = ++ /* sai2_sclk_m2 */ ++ <3 RK_PC2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai2m2_sdi: sai2m2-sdi { ++ rockchip,pins = ++ /* sai2m2_sdi */ ++ <3 RK_PD2 4 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai2m2_sdo: sai2m2-sdo { ++ rockchip,pins = ++ /* sai2m2_sdo */ ++ <3 RK_PD3 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sai3 { ++ /omit-if-no-ref/ ++ sai3m0_lrck: sai3m0-lrck { ++ rockchip,pins = ++ /* sai3_lrck_m0 */ ++ <1 RK_PA6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m0_mclk: sai3m0-mclk { ++ rockchip,pins = ++ /* sai3_mclk_m0 */ ++ <1 RK_PA4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m0_sclk: sai3m0-sclk { ++ rockchip,pins = ++ /* sai3_sclk_m0 */ ++ <1 RK_PA5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m0_sdi: sai3m0-sdi { ++ rockchip,pins = ++ /* sai3m0_sdi */ ++ <1 RK_PA7 4 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai3m0_sdo: sai3m0-sdo { ++ rockchip,pins = ++ /* sai3m0_sdo */ ++ <1 RK_PB2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m1_lrck: sai3m1-lrck { ++ rockchip,pins = ++ /* sai3_lrck_m1 */ ++ <1 RK_PB5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m1_mclk: sai3m1-mclk { ++ rockchip,pins = ++ /* sai3_mclk_m1 */ ++ <1 RK_PC1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m1_sclk: sai3m1-sclk { ++ rockchip,pins = ++ /* sai3_sclk_m1 */ ++ <1 RK_PB4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m1_sdi: sai3m1-sdi { ++ rockchip,pins = ++ /* sai3m1_sdi */ ++ <1 RK_PB7 4 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai3m1_sdo: sai3m1-sdo { ++ rockchip,pins = ++ /* sai3m1_sdo */ ++ <1 RK_PB6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m2_lrck: sai3m2-lrck { ++ rockchip,pins = ++ /* sai3_lrck_m2 */ ++ <3 RK_PA1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m2_mclk: sai3m2-mclk { ++ rockchip,pins = ++ /* sai3_mclk_m2 */ ++ <2 RK_PD6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m2_sclk: sai3m2-sclk { ++ rockchip,pins = ++ /* sai3_sclk_m2 */ ++ <3 RK_PA0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m2_sdi: sai3m2-sdi { ++ rockchip,pins = ++ /* sai3m2_sdi */ ++ <3 RK_PA3 4 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai3m2_sdo: sai3m2-sdo { ++ rockchip,pins = ++ /* sai3m2_sdo */ ++ <3 RK_PA2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m3_lrck: sai3m3-lrck { ++ rockchip,pins = ++ /* sai3_lrck_m3 */ ++ <2 RK_PA2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m3_mclk: sai3m3-mclk { ++ rockchip,pins = ++ /* sai3_mclk_m3 */ ++ <2 RK_PA1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m3_sclk: sai3m3-sclk { ++ rockchip,pins = ++ /* sai3_sclk_m3 */ ++ <2 RK_PA5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai3m3_sdi: sai3m3-sdi { ++ rockchip,pins = ++ /* sai3m3_sdi */ ++ <2 RK_PA3 4 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai3m3_sdo: sai3m3-sdo { ++ rockchip,pins = ++ /* sai3m3_sdo */ ++ <2 RK_PA4 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sai4 { ++ /omit-if-no-ref/ ++ sai4m0_lrck: sai4m0-lrck { ++ rockchip,pins = ++ /* sai4_lrck_m0 */ ++ <4 RK_PA6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m0_mclk: sai4m0-mclk { ++ rockchip,pins = ++ /* sai4_mclk_m0 */ ++ <4 RK_PA2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m0_sclk: sai4m0-sclk { ++ rockchip,pins = ++ /* sai4_sclk_m0 */ ++ <4 RK_PA4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m0_sdi: sai4m0-sdi { ++ rockchip,pins = ++ /* sai4m0_sdi */ ++ <4 RK_PA7 2 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai4m0_sdo: sai4m0-sdo { ++ rockchip,pins = ++ /* sai4m0_sdo */ ++ <4 RK_PB3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m1_lrck: sai4m1-lrck { ++ rockchip,pins = ++ /* sai4_lrck_m1 */ ++ <4 RK_PA0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m1_mclk: sai4m1-mclk { ++ rockchip,pins = ++ /* sai4_mclk_m1 */ ++ <3 RK_PB0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m1_sclk: sai4m1-sclk { ++ rockchip,pins = ++ /* sai4_sclk_m1 */ ++ <3 RK_PD7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m1_sdi: sai4m1-sdi { ++ rockchip,pins = ++ /* sai4m1_sdi */ ++ <3 RK_PA4 4 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai4m1_sdo: sai4m1-sdo { ++ rockchip,pins = ++ /* sai4m1_sdo */ ++ <4 RK_PA1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m2_lrck: sai4m2-lrck { ++ rockchip,pins = ++ /* sai4_lrck_m2 */ ++ <4 RK_PC4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m2_mclk: sai4m2-mclk { ++ rockchip,pins = ++ /* sai4_mclk_m2 */ ++ <4 RK_PC0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m2_sclk: sai4m2-sclk { ++ rockchip,pins = ++ /* sai4_sclk_m2 */ ++ <4 RK_PC7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m2_sdi: sai4m2-sdi { ++ rockchip,pins = ++ /* sai4m2_sdi */ ++ <4 RK_PC6 2 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai4m2_sdo: sai4m2-sdo { ++ rockchip,pins = ++ /* sai4m2_sdo */ ++ <4 RK_PC5 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m3_lrck: sai4m3-lrck { ++ rockchip,pins = ++ /* sai4_lrck_m3 */ ++ <2 RK_PC7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m3_mclk: sai4m3-mclk { ++ rockchip,pins = ++ /* sai4_mclk_m3 */ ++ <2 RK_PD2 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m3_sclk: sai4m3-sclk { ++ rockchip,pins = ++ /* sai4_sclk_m3 */ ++ <2 RK_PC6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sai4m3_sdi: sai4m3-sdi { ++ rockchip,pins = ++ /* sai4m3_sdi */ ++ <2 RK_PD0 4 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ sai4m3_sdo: sai4m3-sdo { ++ rockchip,pins = ++ /* sai4m3_sdo */ ++ <2 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata30 { ++ /omit-if-no-ref/ ++ sata30_sata: sata30-sata { ++ rockchip,pins = ++ /* sata30_cpdet */ ++ <1 RK_PC7 12 &pcfg_pull_none>, ++ /* sata30_cppod */ ++ <1 RK_PC6 12 &pcfg_pull_none>, ++ /* sata30_mpswit */ ++ <1 RK_PD5 12 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata30_port0 { ++ /omit-if-no-ref/ ++ sata30_port0m0_port0: sata30_port0m0-port0 { ++ rockchip,pins = ++ /* sata30_port0_actled_m0 */ ++ <2 RK_PB4 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sata30_port0m1_port0: sata30_port0m1-port0 { ++ rockchip,pins = ++ /* sata30_port0_actled_m1 */ ++ <4 RK_PC6 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata30_port1 { ++ /omit-if-no-ref/ ++ sata30_port1m0_port1: sata30_port1m0-port1 { ++ rockchip,pins = ++ /* sata30_port1_actled_m0 */ ++ <2 RK_PB5 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sata30_port1m1_port1: sata30_port1m1-port1 { ++ rockchip,pins = ++ /* sata30_port1_actled_m1 */ ++ <4 RK_PC5 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc0 { ++ /omit-if-no-ref/ ++ sdmmc0_bus4: sdmmc0-bus4 { ++ rockchip,pins = ++ /* sdmmc0_d0 */ ++ <2 RK_PA0 1 &pcfg_pull_up_drv_level_3>, ++ /* sdmmc0_d1 */ ++ <2 RK_PA1 1 &pcfg_pull_up_drv_level_3>, ++ /* sdmmc0_d2 */ ++ <2 RK_PA2 1 &pcfg_pull_up_drv_level_3>, ++ /* sdmmc0_d3 */ ++ <2 RK_PA3 1 &pcfg_pull_up_drv_level_3>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc0_clk: sdmmc0-clk { ++ rockchip,pins = ++ /* sdmmc0_clk */ ++ <2 RK_PA5 1 &pcfg_pull_up_drv_level_3>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc0_cmd: sdmmc0-cmd { ++ rockchip,pins = ++ /* sdmmc0_cmd */ ++ <2 RK_PA4 1 &pcfg_pull_up_drv_level_3>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc0_det: sdmmc0-det { ++ rockchip,pins = ++ /* sdmmc0_detn */ ++ <0 RK_PA7 1 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc0_pwren: sdmmc0-pwren { ++ rockchip,pins = ++ /* sdmmc0_pwren */ ++ <0 RK_PB6 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc1 { ++ /omit-if-no-ref/ ++ sdmmc1m0_bus4: sdmmc1m0-bus4 { ++ rockchip,pins = ++ /* sdmmc1_d0_m0 */ ++ <1 RK_PB4 2 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc1_d1_m0 */ ++ <1 RK_PB5 2 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc1_d2_m0 */ ++ <1 RK_PB6 2 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc1_d3_m0 */ ++ <1 RK_PB7 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m0_clk: sdmmc1m0-clk { ++ rockchip,pins = ++ /* sdmmc1_clk_m0 */ ++ <1 RK_PC1 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m0_cmd: sdmmc1m0-cmd { ++ rockchip,pins = ++ /* sdmmc1_cmd_m0 */ ++ <1 RK_PC0 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m0_det: sdmmc1m0-det { ++ rockchip,pins = ++ /* sdmmc1_detn_m0 */ ++ <1 RK_PC3 2 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m0_pwren: sdmmc1m0-pwren { ++ rockchip,pins = ++ /* sdmmc1m0_pwren */ ++ <1 RK_PC2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m1_bus4: sdmmc1m1-bus4 { ++ rockchip,pins = ++ /* sdmmc1_d0_m1 */ ++ <2 RK_PA6 2 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc1_d1_m1 */ ++ <2 RK_PA7 2 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc1_d2_m1 */ ++ <2 RK_PB0 2 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc1_d3_m1 */ ++ <2 RK_PB1 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m1_clk: sdmmc1m1-clk { ++ rockchip,pins = ++ /* sdmmc1_clk_m1 */ ++ <2 RK_PB3 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m1_cmd: sdmmc1m1-cmd { ++ rockchip,pins = ++ /* sdmmc1_cmd_m1 */ ++ <2 RK_PB2 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m1_det: sdmmc1m1-det { ++ rockchip,pins = ++ /* sdmmc1_detn_m1 */ ++ <2 RK_PB5 2 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m1_pwren: sdmmc1m1-pwren { ++ rockchip,pins = ++ /* sdmmc1m1_pwren */ ++ <2 RK_PB4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc1m2_det: sdmmc1m2-det { ++ rockchip,pins = ++ /* sdmmc1_detn_m2 */ ++ <0 RK_PB6 2 &pcfg_pull_up>; ++ }; ++ }; ++ ++ sdmmc0_testclk { ++ /omit-if-no-ref/ ++ sdmmc0_testclk_test: sdmmc0_testclk-test { ++ rockchip,pins = ++ /* sdmmc0_testclk_out */ ++ <1 RK_PC4 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc0_testdata { ++ /omit-if-no-ref/ ++ sdmmc0_testdata_test: sdmmc0_testdata-test { ++ rockchip,pins = ++ /* sdmmc0_testdata_out */ ++ <1 RK_PC5 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc1_testclk { ++ /omit-if-no-ref/ ++ sdmmc1_testclkm0_test: sdmmc1_testclkm0-test { ++ rockchip,pins = ++ /* sdmmc1_testclk_out_m0 */ ++ <1 RK_PC4 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc1_testdata { ++ /omit-if-no-ref/ ++ sdmmc1_testdatam0_test: sdmmc1_testdatam0-test { ++ rockchip,pins = ++ /* sdmmc1_testdata_out_m0 */ ++ <1 RK_PC5 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spdif { ++ /omit-if-no-ref/ ++ spdifm0_rx0: spdifm0-rx0 { ++ rockchip,pins = ++ /* spdif_rx0_m0 */ ++ <4 RK_PB4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm0_rx1: spdifm0-rx1 { ++ rockchip,pins = ++ /* spdif_rx1_m0 */ ++ <3 RK_PB4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm0_tx0: spdifm0-tx0 { ++ rockchip,pins = ++ /* spdif_tx0_m0 */ ++ <4 RK_PB5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm0_tx1: spdifm0-tx1 { ++ rockchip,pins = ++ /* spdif_tx1_m0 */ ++ <3 RK_PB5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm1_rx0: spdifm1-rx0 { ++ rockchip,pins = ++ /* spdif_rx0_m1 */ ++ <4 RK_PA0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm1_rx1: spdifm1-rx1 { ++ rockchip,pins = ++ /* spdif_rx1_m1 */ ++ <3 RK_PA2 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm1_tx0: spdifm1-tx0 { ++ rockchip,pins = ++ /* spdif_tx0_m1 */ ++ <4 RK_PA1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm1_tx1: spdifm1-tx1 { ++ rockchip,pins = ++ /* spdif_tx1_m1 */ ++ <3 RK_PA3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm2_rx0: spdifm2-rx0 { ++ rockchip,pins = ++ /* spdif_rx0_m2 */ ++ <2 RK_PD6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm2_rx1: spdifm2-rx1 { ++ rockchip,pins = ++ /* spdif_rx1_m2 */ ++ <1 RK_PD4 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm2_tx0: spdifm2-tx0 { ++ rockchip,pins = ++ /* spdif_tx0_m2 */ ++ <2 RK_PD7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdifm2_tx1: spdifm2-tx1 { ++ rockchip,pins = ++ /* spdif_tx1_m2 */ ++ <1 RK_PD5 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spi0 { ++ /omit-if-no-ref/ ++ spi0m0_pins: spi0m0-pins { ++ rockchip,pins = ++ /* spi0_clk_m0 */ ++ <0 RK_PC7 11 &pcfg_pull_none>, ++ /* spi0_miso_m0 */ ++ <0 RK_PD1 11 &pcfg_pull_none>, ++ /* spi0_mosi_m0 */ ++ <0 RK_PD0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m0_csn0: spi0m0-csn0 { ++ rockchip,pins = ++ /* spi0m0_csn0 */ ++ <0 RK_PC6 11 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi0m0_csn1: spi0m0-csn1 { ++ rockchip,pins = ++ /* spi0m0_csn1 */ ++ <0 RK_PC3 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m1_pins: spi0m1-pins { ++ rockchip,pins = ++ /* spi0_clk_m1 */ ++ <2 RK_PA5 12 &pcfg_pull_none>, ++ /* spi0_miso_m1 */ ++ <2 RK_PA1 12 &pcfg_pull_none>, ++ /* spi0_mosi_m1 */ ++ <2 RK_PA0 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m1_csn0: spi0m1-csn0 { ++ rockchip,pins = ++ /* spi0m1_csn0 */ ++ <2 RK_PA4 12 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi0m1_csn1: spi0m1-csn1 { ++ rockchip,pins = ++ /* spi0m1_csn1 */ ++ <2 RK_PA2 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m2_pins: spi0m2-pins { ++ rockchip,pins = ++ /* spi0_clk_m2 */ ++ <1 RK_PA7 9 &pcfg_pull_none>, ++ /* spi0_miso_m2 */ ++ <1 RK_PA6 9 &pcfg_pull_none>, ++ /* spi0_mosi_m2 */ ++ <1 RK_PA5 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m2_csn0: spi0m2-csn0 { ++ rockchip,pins = ++ /* spi0m2_csn0 */ ++ <1 RK_PA4 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi0m2_csn1: spi0m2-csn1 { ++ rockchip,pins = ++ /* spi0m2_csn1 */ ++ <1 RK_PB2 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spi1 { ++ /omit-if-no-ref/ ++ spi1m0_pins: spi1m0-pins { ++ rockchip,pins = ++ /* spi1_clk_m0 */ ++ <1 RK_PB4 11 &pcfg_pull_none>, ++ /* spi1_miso_m0 */ ++ <1 RK_PB6 11 &pcfg_pull_none>, ++ /* spi1_mosi_m0 */ ++ <1 RK_PB5 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m0_csn0: spi1m0-csn0 { ++ rockchip,pins = ++ /* spi1m0_csn0 */ ++ <1 RK_PB7 11 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi1m0_csn1: spi1m0-csn1 { ++ rockchip,pins = ++ /* spi1m0_csn1 */ ++ <1 RK_PC0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m1_pins: spi1m1-pins { ++ rockchip,pins = ++ /* spi1_clk_m1 */ ++ <2 RK_PC5 10 &pcfg_pull_none>, ++ /* spi1_miso_m1 */ ++ <2 RK_PC3 10 &pcfg_pull_none>, ++ /* spi1_mosi_m1 */ ++ <2 RK_PC2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m1_csn0: spi1m1-csn0 { ++ rockchip,pins = ++ /* spi1m1_csn0 */ ++ <2 RK_PC4 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi1m1_csn1: spi1m1-csn1 { ++ rockchip,pins = ++ /* spi1m1_csn1 */ ++ <2 RK_PC1 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m2_pins: spi1m2-pins { ++ rockchip,pins = ++ /* spi1_clk_m2 */ ++ <3 RK_PC7 10 &pcfg_pull_none>, ++ /* spi1_miso_m2 */ ++ <3 RK_PC5 10 &pcfg_pull_none>, ++ /* spi1_mosi_m2 */ ++ <3 RK_PC6 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m2_csn0: spi1m2-csn0 { ++ rockchip,pins = ++ /* spi1m2_csn0 */ ++ <3 RK_PD0 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi1m2_csn1: spi1m2-csn1 { ++ rockchip,pins = ++ /* spi1m2_csn1 */ ++ <4 RK_PA0 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spi2 { ++ /omit-if-no-ref/ ++ spi2m0_pins: spi2m0-pins { ++ rockchip,pins = ++ /* spi2_clk_m0 */ ++ <0 RK_PB2 9 &pcfg_pull_none>, ++ /* spi2_miso_m0 */ ++ <0 RK_PB1 9 &pcfg_pull_none>, ++ /* spi2_mosi_m0 */ ++ <0 RK_PB3 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m0_csn0: spi2m0-csn0 { ++ rockchip,pins = ++ /* spi2m0_csn0 */ ++ <0 RK_PB0 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi2m0_csn1: spi2m0-csn1 { ++ rockchip,pins = ++ /* spi2m0_csn1 */ ++ <0 RK_PA7 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m1_pins: spi2m1-pins { ++ rockchip,pins = ++ /* spi2_clk_m1 */ ++ <1 RK_PD5 11 &pcfg_pull_none>, ++ /* spi2_miso_m1 */ ++ <1 RK_PC5 11 &pcfg_pull_none>, ++ /* spi2_mosi_m1 */ ++ <1 RK_PC4 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m1_csn0: spi2m1-csn0 { ++ rockchip,pins = ++ /* spi2m1_csn0 */ ++ <1 RK_PC3 11 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi2m1_csn1: spi2m1-csn1 { ++ rockchip,pins = ++ /* spi2m1_csn1 */ ++ <1 RK_PC2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m2_pins: spi2m2-pins { ++ rockchip,pins = ++ /* spi2_clk_m2 */ ++ <3 RK_PA4 10 &pcfg_pull_none>, ++ /* spi2_miso_m2 */ ++ <3 RK_PC1 10 &pcfg_pull_none>, ++ /* spi2_mosi_m2 */ ++ <3 RK_PB0 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m2_csn0: spi2m2-csn0 { ++ rockchip,pins = ++ /* spi2m2_csn0 */ ++ <3 RK_PC4 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi2m2_csn1: spi2m2-csn1 { ++ rockchip,pins = ++ /* spi2m2_csn1 */ ++ <3 RK_PA5 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spi3 { ++ /omit-if-no-ref/ ++ spi3m0_pins: spi3m0-pins { ++ rockchip,pins = ++ /* spi3_clk_m0 */ ++ <3 RK_PA0 10 &pcfg_pull_none>, ++ /* spi3_miso_m0 */ ++ <3 RK_PA2 10 &pcfg_pull_none>, ++ /* spi3_mosi_m0 */ ++ <3 RK_PA1 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m0_csn0: spi3m0-csn0 { ++ rockchip,pins = ++ /* spi3m0_csn0 */ ++ <3 RK_PA3 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi3m0_csn1: spi3m0-csn1 { ++ rockchip,pins = ++ /* spi3m0_csn1 */ ++ <2 RK_PD7 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m1_pins: spi3m1-pins { ++ rockchip,pins = ++ /* spi3_clk_m1 */ ++ <3 RK_PD4 10 &pcfg_pull_none>, ++ /* spi3_miso_m1 */ ++ <3 RK_PD5 10 &pcfg_pull_none>, ++ /* spi3_mosi_m1 */ ++ <3 RK_PD6 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m1_csn0: spi3m1-csn0 { ++ rockchip,pins = ++ /* spi3m1_csn0 */ ++ <3 RK_PB6 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi3m1_csn1: spi3m1-csn1 { ++ rockchip,pins = ++ /* spi3m1_csn1 */ ++ <3 RK_PD7 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m2_pins: spi3m2-pins { ++ rockchip,pins = ++ /* spi3_clk_m2 */ ++ <4 RK_PA7 9 &pcfg_pull_none>, ++ /* spi3_miso_m2 */ ++ <4 RK_PA6 9 &pcfg_pull_none>, ++ /* spi3_mosi_m2 */ ++ <4 RK_PA4 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m2_csn0: spi3m2-csn0 { ++ rockchip,pins = ++ /* spi3m2_csn0 */ ++ <4 RK_PA3 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi3m2_csn1: spi3m2-csn1 { ++ rockchip,pins = ++ /* spi3m2_csn1 */ ++ <4 RK_PB3 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spi4 { ++ /omit-if-no-ref/ ++ spi4m0_pins: spi4m0-pins { ++ rockchip,pins = ++ /* spi4_clk_m0 */ ++ <4 RK_PC7 12 &pcfg_pull_none>, ++ /* spi4_miso_m0 */ ++ <4 RK_PC6 12 &pcfg_pull_none>, ++ /* spi4_mosi_m0 */ ++ <4 RK_PC5 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m0_csn0: spi4m0-csn0 { ++ rockchip,pins = ++ /* spi4m0_csn0 */ ++ <4 RK_PC4 12 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi4m0_csn1: spi4m0-csn1 { ++ rockchip,pins = ++ /* spi4m0_csn1 */ ++ <4 RK_PC0 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m1_pins: spi4m1-pins { ++ rockchip,pins = ++ /* spi4_clk_m1 */ ++ <3 RK_PD1 10 &pcfg_pull_none>, ++ /* spi4_miso_m1 */ ++ <3 RK_PC2 10 &pcfg_pull_none>, ++ /* spi4_mosi_m1 */ ++ <3 RK_PC3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m1_csn0: spi4m1-csn0 { ++ rockchip,pins = ++ /* spi4m1_csn0 */ ++ <3 RK_PB1 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi4m1_csn1: spi4m1-csn1 { ++ rockchip,pins = ++ /* spi4m1_csn1 */ ++ <3 RK_PD2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m2_pins: spi4m2-pins { ++ rockchip,pins = ++ /* spi4_clk_m2 */ ++ <4 RK_PB0 9 &pcfg_pull_none>, ++ /* spi4_miso_m2 */ ++ <4 RK_PB2 9 &pcfg_pull_none>, ++ /* spi4_mosi_m2 */ ++ <4 RK_PB1 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m2_csn0: spi4m2-csn0 { ++ rockchip,pins = ++ /* spi4m2_csn0 */ ++ <4 RK_PB3 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi4m2_csn1: spi4m2-csn1 { ++ rockchip,pins = ++ /* spi4m2_csn1 */ ++ <4 RK_PA5 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m3_pins: spi4m3-pins { ++ rockchip,pins = ++ /* spi4_clk_m3 */ ++ <2 RK_PB3 10 &pcfg_pull_none>, ++ /* spi4_miso_m3 */ ++ <2 RK_PB5 10 &pcfg_pull_none>, ++ /* spi4_mosi_m3 */ ++ <2 RK_PB4 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m3_csn0: spi4m3-csn0 { ++ rockchip,pins = ++ /* spi4m3_csn0 */ ++ <2 RK_PB2 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ spi4m3_csn1: spi4m3-csn1 { ++ rockchip,pins = ++ /* spi4m3_csn1 */ ++ <2 RK_PA6 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ test_clk { ++ /omit-if-no-ref/ ++ test_clk_pins: test_clk-pins { ++ rockchip,pins = ++ /* test_clk_out */ ++ <2 RK_PA5 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ tsadc { ++ /omit-if-no-ref/ ++ tsadcm0_pins: tsadcm0-pins { ++ rockchip,pins = ++ /* tsadc_ctrl_m0 */ ++ <0 RK_PA1 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ tsadcm1_pins: tsadcm1-pins { ++ rockchip,pins = ++ /* tsadc_ctrl_m1 */ ++ <0 RK_PA3 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ tsadc_ctrl { ++ /omit-if-no-ref/ ++ tsadc_ctrl_pins: tsadc_ctrl-pins { ++ rockchip,pins = ++ /* tsadc_ctrl_org */ ++ <0 RK_PA1 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart0 { ++ /omit-if-no-ref/ ++ uart0m0_xfer: uart0m0-xfer { ++ rockchip,pins = ++ /* uart0_rx_m0 */ ++ <0 RK_PD5 9 &pcfg_pull_up>, ++ /* uart0_tx_m0 */ ++ <0 RK_PD4 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0m1_xfer: uart0m1-xfer { ++ rockchip,pins = ++ /* uart0_rx_m1 */ ++ <2 RK_PA0 9 &pcfg_pull_up>, ++ /* uart0_tx_m1 */ ++ <2 RK_PA1 9 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart1 { ++ /omit-if-no-ref/ ++ uart1m0_xfer: uart1m0-xfer { ++ rockchip,pins = ++ /* uart1_rx_m0 */ ++ <0 RK_PC0 10 &pcfg_pull_up>, ++ /* uart1_tx_m0 */ ++ <0 RK_PB7 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m0_ctsn: uart1m0-ctsn { ++ rockchip,pins = ++ /* uart1m0_ctsn */ ++ <0 RK_PD2 13 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart1m0_rtsn: uart1m0-rtsn { ++ rockchip,pins = ++ /* uart1m0_rtsn */ ++ <0 RK_PD3 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m1_xfer: uart1m1-xfer { ++ rockchip,pins = ++ /* uart1_rx_m1 */ ++ <2 RK_PB1 9 &pcfg_pull_up>, ++ /* uart1_tx_m1 */ ++ <2 RK_PB0 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m1_ctsn: uart1m1-ctsn { ++ rockchip,pins = ++ /* uart1m1_ctsn */ ++ <2 RK_PB2 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart1m1_rtsn: uart1m1-rtsn { ++ rockchip,pins = ++ /* uart1m1_rtsn */ ++ <2 RK_PB3 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m2_xfer: uart1m2-xfer { ++ rockchip,pins = ++ /* uart1_rx_m2 */ ++ <3 RK_PA6 9 &pcfg_pull_up>, ++ /* uart1_tx_m2 */ ++ <3 RK_PA7 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m2_ctsn: uart1m2-ctsn { ++ rockchip,pins = ++ /* uart1m2_ctsn */ ++ <3 RK_PA4 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart1m2_rtsn: uart1m2-rtsn { ++ rockchip,pins = ++ /* uart1m2_rtsn */ ++ <3 RK_PA5 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart2 { ++ /omit-if-no-ref/ ++ uart2m0_xfer: uart2m0-xfer { ++ rockchip,pins = ++ /* uart2_rx_m0 */ ++ <1 RK_PC7 9 &pcfg_pull_up>, ++ /* uart2_tx_m0 */ ++ <1 RK_PC6 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2m0_ctsn: uart2m0-ctsn { ++ rockchip,pins = ++ /* uart2m0_ctsn */ ++ <1 RK_PC5 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart2m0_rtsn: uart2m0-rtsn { ++ rockchip,pins = ++ /* uart2m0_rtsn */ ++ <1 RK_PC4 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2m1_xfer: uart2m1-xfer { ++ rockchip,pins = ++ /* uart2_rx_m1 */ ++ <4 RK_PB4 10 &pcfg_pull_up>, ++ /* uart2_tx_m1 */ ++ <4 RK_PB5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2m1_ctsn: uart2m1-ctsn { ++ rockchip,pins = ++ /* uart2m1_ctsn */ ++ <4 RK_PB1 12 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart2m1_rtsn: uart2m1-rtsn { ++ rockchip,pins = ++ /* uart2m1_rtsn */ ++ <4 RK_PB0 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2m2_xfer: uart2m2-xfer { ++ rockchip,pins = ++ /* uart2_rx_m2 */ ++ <3 RK_PB7 9 &pcfg_pull_up>, ++ /* uart2_tx_m2 */ ++ <3 RK_PC0 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2m2_ctsn: uart2m2-ctsn { ++ rockchip,pins = ++ /* uart2m2_ctsn */ ++ <3 RK_PD3 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart2m2_rtsn: uart2m2-rtsn { ++ rockchip,pins = ++ /* uart2m2_rtsn */ ++ <3 RK_PD2 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart3 { ++ /omit-if-no-ref/ ++ uart3m0_xfer: uart3m0-xfer { ++ rockchip,pins = ++ /* uart3_rx_m0 */ ++ <3 RK_PA1 9 &pcfg_pull_up>, ++ /* uart3_tx_m0 */ ++ <3 RK_PA0 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3m0_ctsn: uart3m0-ctsn { ++ rockchip,pins = ++ /* uart3m0_ctsn */ ++ <3 RK_PA2 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart3m0_rtsn: uart3m0-rtsn { ++ rockchip,pins = ++ /* uart3m0_rtsn */ ++ <3 RK_PA3 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3m1_xfer: uart3m1-xfer { ++ rockchip,pins = ++ /* uart3_rx_m1 */ ++ <4 RK_PA1 9 &pcfg_pull_up>, ++ /* uart3_tx_m1 */ ++ <4 RK_PA0 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3m1_ctsn: uart3m1-ctsn { ++ rockchip,pins = ++ /* uart3m1_ctsn */ ++ <3 RK_PB7 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart3m1_rtsn: uart3m1-rtsn { ++ rockchip,pins = ++ /* uart3m1_rtsn */ ++ <3 RK_PC0 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3m2_xfer: uart3m2-xfer { ++ rockchip,pins = ++ /* uart3_rx_m2 */ ++ <1 RK_PC1 9 &pcfg_pull_up>, ++ /* uart3_tx_m2 */ ++ <1 RK_PC0 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3m2_ctsn: uart3m2-ctsn { ++ rockchip,pins = ++ /* uart3m2_ctsn */ ++ <1 RK_PB6 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart3m2_rtsn: uart3m2-rtsn { ++ rockchip,pins = ++ /* uart3m2_rtsn */ ++ <1 RK_PB7 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart4 { ++ /omit-if-no-ref/ ++ uart4m0_xfer: uart4m0-xfer { ++ rockchip,pins = ++ /* uart4_rx_m0 */ ++ <2 RK_PD1 9 &pcfg_pull_up>, ++ /* uart4_tx_m0 */ ++ <2 RK_PD0 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4m0_ctsn: uart4m0-ctsn { ++ rockchip,pins = ++ /* uart4m0_ctsn */ ++ <2 RK_PC6 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart4m0_rtsn: uart4m0-rtsn { ++ rockchip,pins = ++ /* uart4m0_rtsn */ ++ <2 RK_PC7 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4m1_xfer: uart4m1-xfer { ++ rockchip,pins = ++ /* uart4_rx_m1 */ ++ <1 RK_PC5 9 &pcfg_pull_up>, ++ /* uart4_tx_m1 */ ++ <1 RK_PC4 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4m1_ctsn: uart4m1-ctsn { ++ rockchip,pins = ++ /* uart4m1_ctsn */ ++ <1 RK_PC3 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart4m1_rtsn: uart4m1-rtsn { ++ rockchip,pins = ++ /* uart4m1_rtsn */ ++ <1 RK_PC2 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4m2_xfer: uart4m2-xfer { ++ rockchip,pins = ++ /* uart4_rx_m2 */ ++ <0 RK_PB5 10 &pcfg_pull_up>, ++ /* uart4_tx_m2 */ ++ <0 RK_PB4 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart5 { ++ /omit-if-no-ref/ ++ uart5m0_xfer: uart5m0-xfer { ++ rockchip,pins = ++ /* uart5_rx_m0 */ ++ <3 RK_PD4 9 &pcfg_pull_up>, ++ /* uart5_tx_m0 */ ++ <3 RK_PD5 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m0_ctsn: uart5m0-ctsn { ++ rockchip,pins = ++ /* uart5m0_ctsn */ ++ <3 RK_PD6 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart5m0_rtsn: uart5m0-rtsn { ++ rockchip,pins = ++ /* uart5m0_rtsn */ ++ <3 RK_PD7 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m1_xfer: uart5m1-xfer { ++ rockchip,pins = ++ /* uart5_rx_m1 */ ++ <4 RK_PB1 10 &pcfg_pull_up>, ++ /* uart5_tx_m1 */ ++ <4 RK_PB0 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m1_ctsn: uart5m1-ctsn { ++ rockchip,pins = ++ /* uart5m1_ctsn */ ++ <4 RK_PA5 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart5m1_rtsn: uart5m1-rtsn { ++ rockchip,pins = ++ /* uart5m1_rtsn */ ++ <4 RK_PA3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m2_xfer: uart5m2-xfer { ++ rockchip,pins = ++ /* uart5_rx_m2 */ ++ <2 RK_PA4 9 &pcfg_pull_up>, ++ /* uart5_tx_m2 */ ++ <2 RK_PA5 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m2_ctsn: uart5m2-ctsn { ++ rockchip,pins = ++ /* uart5m2_ctsn */ ++ <2 RK_PA3 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart5m2_rtsn: uart5m2-rtsn { ++ rockchip,pins = ++ /* uart5m2_rtsn */ ++ <2 RK_PA2 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart6 { ++ /omit-if-no-ref/ ++ uart6m0_xfer: uart6m0-xfer { ++ rockchip,pins = ++ /* uart6_rx_m0 */ ++ <4 RK_PA6 10 &pcfg_pull_up>, ++ /* uart6_tx_m0 */ ++ <4 RK_PA4 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m0_ctsn: uart6m0-ctsn { ++ rockchip,pins = ++ /* uart6m0_ctsn */ ++ <4 RK_PB1 11 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart6m0_rtsn: uart6m0-rtsn { ++ rockchip,pins = ++ /* uart6m0_rtsn */ ++ <4 RK_PB0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m1_xfer: uart6m1-xfer { ++ rockchip,pins = ++ /* uart6_rx_m1 */ ++ <2 RK_PD3 9 &pcfg_pull_up>, ++ /* uart6_tx_m1 */ ++ <2 RK_PD2 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m1_ctsn: uart6m1-ctsn { ++ rockchip,pins = ++ /* uart6m1_ctsn */ ++ <2 RK_PD5 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart6m1_rtsn: uart6m1-rtsn { ++ rockchip,pins = ++ /* uart6m1_rtsn */ ++ <2 RK_PD4 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m2_xfer: uart6m2-xfer { ++ rockchip,pins = ++ /* uart6_rx_m2 */ ++ <1 RK_PB3 9 &pcfg_pull_up>, ++ /* uart6_tx_m2 */ ++ <1 RK_PB0 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m2_ctsn: uart6m2-ctsn { ++ rockchip,pins = ++ /* uart6m2_ctsn */ ++ <1 RK_PA3 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart6m2_rtsn: uart6m2-rtsn { ++ rockchip,pins = ++ /* uart6m2_rtsn */ ++ <1 RK_PA2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m3_xfer: uart6m3-xfer { ++ rockchip,pins = ++ /* uart6_rx_m3 */ ++ <4 RK_PC5 13 &pcfg_pull_up>, ++ /* uart6_tx_m3 */ ++ <4 RK_PC4 13 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart7 { ++ /omit-if-no-ref/ ++ uart7m0_xfer: uart7m0-xfer { ++ rockchip,pins = ++ /* uart7_rx_m0 */ ++ <2 RK_PB7 9 &pcfg_pull_up>, ++ /* uart7_tx_m0 */ ++ <2 RK_PB6 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m0_ctsn: uart7m0-ctsn { ++ rockchip,pins = ++ /* uart7m0_ctsn */ ++ <2 RK_PB4 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart7m0_rtsn: uart7m0-rtsn { ++ rockchip,pins = ++ /* uart7m0_rtsn */ ++ <2 RK_PB5 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m1_xfer: uart7m1-xfer { ++ rockchip,pins = ++ /* uart7_rx_m1 */ ++ <1 RK_PA3 9 &pcfg_pull_up>, ++ /* uart7_tx_m1 */ ++ <1 RK_PA2 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m1_ctsn: uart7m1-ctsn { ++ rockchip,pins = ++ /* uart7m1_ctsn */ ++ <1 RK_PA1 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart7m1_rtsn: uart7m1-rtsn { ++ rockchip,pins = ++ /* uart7m1_rtsn */ ++ <1 RK_PA0 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m2_xfer: uart7m2-xfer { ++ rockchip,pins = ++ /* uart7_rx_m2 */ ++ <2 RK_PA0 10 &pcfg_pull_up>, ++ /* uart7_tx_m2 */ ++ <2 RK_PA1 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart8 { ++ /omit-if-no-ref/ ++ uart8m0_xfer: uart8m0-xfer { ++ rockchip,pins = ++ /* uart8_rx_m0 */ ++ <3 RK_PC5 9 &pcfg_pull_up>, ++ /* uart8_tx_m0 */ ++ <3 RK_PC6 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m0_ctsn: uart8m0-ctsn { ++ rockchip,pins = ++ /* uart8m0_ctsn */ ++ <3 RK_PD0 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart8m0_rtsn: uart8m0-rtsn { ++ rockchip,pins = ++ /* uart8m0_rtsn */ ++ <3 RK_PC7 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m1_xfer: uart8m1-xfer { ++ rockchip,pins = ++ /* uart8_rx_m1 */ ++ <2 RK_PA7 9 &pcfg_pull_up>, ++ /* uart8_tx_m1 */ ++ <2 RK_PA6 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m1_ctsn: uart8m1-ctsn { ++ rockchip,pins = ++ /* uart8m1_ctsn */ ++ <2 RK_PB7 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart8m1_rtsn: uart8m1-rtsn { ++ rockchip,pins = ++ /* uart8m1_rtsn */ ++ <2 RK_PB6 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m2_xfer: uart8m2-xfer { ++ rockchip,pins = ++ /* uart8_rx_m2 */ ++ <0 RK_PC2 10 &pcfg_pull_up>, ++ /* uart8_tx_m2 */ ++ <0 RK_PC1 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart9 { ++ /omit-if-no-ref/ ++ uart9m0_xfer: uart9m0-xfer { ++ rockchip,pins = ++ /* uart9_rx_m0 */ ++ <2 RK_PC0 9 &pcfg_pull_up>, ++ /* uart9_tx_m0 */ ++ <2 RK_PC1 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m0_ctsn: uart9m0-ctsn { ++ rockchip,pins = ++ /* uart9m0_ctsn */ ++ <2 RK_PD7 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart9m0_rtsn: uart9m0-rtsn { ++ rockchip,pins = ++ /* uart9m0_rtsn */ ++ <2 RK_PD6 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m1_xfer: uart9m1-xfer { ++ rockchip,pins = ++ /* uart9_rx_m1 */ ++ <3 RK_PB2 9 &pcfg_pull_up>, ++ /* uart9_tx_m1 */ ++ <3 RK_PB3 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m1_ctsn: uart9m1-ctsn { ++ rockchip,pins = ++ /* uart9m1_ctsn */ ++ <3 RK_PB5 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart9m1_rtsn: uart9m1-rtsn { ++ rockchip,pins = ++ /* uart9m1_rtsn */ ++ <3 RK_PB4 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m2_xfer: uart9m2-xfer { ++ rockchip,pins = ++ /* uart9_rx_m2 */ ++ <4 RK_PC3 13 &pcfg_pull_up>, ++ /* uart9_tx_m2 */ ++ <4 RK_PC2 13 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart10 { ++ /omit-if-no-ref/ ++ uart10m0_xfer: uart10m0-xfer { ++ rockchip,pins = ++ /* uart10_rx_m0 */ ++ <3 RK_PB0 9 &pcfg_pull_up>, ++ /* uart10_tx_m0 */ ++ <3 RK_PB1 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart10m0_ctsn: uart10m0-ctsn { ++ rockchip,pins = ++ /* uart10m0_ctsn */ ++ <3 RK_PA6 10 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart10m0_rtsn: uart10m0-rtsn { ++ rockchip,pins = ++ /* uart10m0_rtsn */ ++ <3 RK_PA7 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart10m1_xfer: uart10m1-xfer { ++ rockchip,pins = ++ /* uart10_rx_m1 */ ++ <1 RK_PD1 9 &pcfg_pull_up>, ++ /* uart10_tx_m1 */ ++ <1 RK_PD0 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart10m1_ctsn: uart10m1-ctsn { ++ rockchip,pins = ++ /* uart10m1_ctsn */ ++ <1 RK_PD5 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart10m1_rtsn: uart10m1-rtsn { ++ rockchip,pins = ++ /* uart10m1_rtsn */ ++ <1 RK_PD4 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart10m2_xfer: uart10m2-xfer { ++ rockchip,pins = ++ /* uart10_rx_m2 */ ++ <0 RK_PC5 10 &pcfg_pull_up>, ++ /* uart10_tx_m2 */ ++ <0 RK_PC4 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart11 { ++ /omit-if-no-ref/ ++ uart11m0_xfer: uart11m0-xfer { ++ rockchip,pins = ++ /* uart11_rx_m0 */ ++ <3 RK_PC1 9 &pcfg_pull_up>, ++ /* uart11_tx_m0 */ ++ <3 RK_PC4 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart11m0_ctsn: uart11m0-ctsn { ++ rockchip,pins = ++ /* uart11m0_ctsn */ ++ <3 RK_PC3 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart11m0_rtsn: uart11m0-rtsn { ++ rockchip,pins = ++ /* uart11m0_rtsn */ ++ <3 RK_PC2 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart11m1_xfer: uart11m1-xfer { ++ rockchip,pins = ++ /* uart11_rx_m1 */ ++ <2 RK_PC5 9 &pcfg_pull_up>, ++ /* uart11_tx_m1 */ ++ <2 RK_PC4 9 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart11m1_ctsn: uart11m1-ctsn { ++ rockchip,pins = ++ /* uart11m1_ctsn */ ++ <2 RK_PC2 9 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ uart11m1_rtsn: uart11m1-rtsn { ++ rockchip,pins = ++ /* uart11m1_rtsn */ ++ <2 RK_PC3 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart11m2_xfer: uart11m2-xfer { ++ rockchip,pins = ++ /* uart11_rx_m2 */ ++ <4 RK_PC1 13 &pcfg_pull_up>, ++ /* uart11_tx_m2 */ ++ <4 RK_PC0 13 &pcfg_pull_up>; ++ }; ++ }; ++ ++ ufs { ++ /omit-if-no-ref/ ++ ufs_refclk: ufs-refclk { ++ rockchip,pins = ++ /* ufs_refclk */ ++ <4 RK_PD1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ ufs_rst: ufs-rst { ++ rockchip,pins = ++ /* ufs_rstn */ ++ <4 RK_PD0 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ufs_testdata0 { ++ /omit-if-no-ref/ ++ ufs_testdata0_test: ufs_testdata0-test { ++ rockchip,pins = ++ /* ufs_testdata0_out */ ++ <4 RK_PC4 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ufs_testdata1 { ++ /omit-if-no-ref/ ++ ufs_testdata1_test: ufs_testdata1-test { ++ rockchip,pins = ++ /* ufs_testdata1_out */ ++ <4 RK_PC5 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ufs_testdata2 { ++ /omit-if-no-ref/ ++ ufs_testdata2_test: ufs_testdata2-test { ++ rockchip,pins = ++ /* ufs_testdata2_out */ ++ <4 RK_PC6 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ufs_testdata3 { ++ /omit-if-no-ref/ ++ ufs_testdata3_test: ufs_testdata3-test { ++ rockchip,pins = ++ /* ufs_testdata3_out */ ++ <4 RK_PC7 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vi_cif { ++ /omit-if-no-ref/ ++ vi_cif_pins: vi_cif-pins { ++ rockchip,pins = ++ /* vi_cif_clki */ ++ <3 RK_PA3 1 &pcfg_pull_none>, ++ /* vi_cif_clko */ ++ <3 RK_PA2 1 &pcfg_pull_none>, ++ /* vi_cif_d0 */ ++ <2 RK_PC5 1 &pcfg_pull_none>, ++ /* vi_cif_d1 */ ++ <2 RK_PC4 1 &pcfg_pull_none>, ++ /* vi_cif_d2 */ ++ <2 RK_PC3 1 &pcfg_pull_none>, ++ /* vi_cif_d3 */ ++ <2 RK_PC2 1 &pcfg_pull_none>, ++ /* vi_cif_d4 */ ++ <2 RK_PC1 1 &pcfg_pull_none>, ++ /* vi_cif_d5 */ ++ <2 RK_PC0 1 &pcfg_pull_none>, ++ /* vi_cif_d6 */ ++ <2 RK_PB7 1 &pcfg_pull_none>, ++ /* vi_cif_d7 */ ++ <2 RK_PB6 1 &pcfg_pull_none>, ++ /* vi_cif_d8 */ ++ <2 RK_PB5 1 &pcfg_pull_none>, ++ /* vi_cif_d9 */ ++ <2 RK_PB4 1 &pcfg_pull_none>, ++ /* vi_cif_d10 */ ++ <2 RK_PB3 1 &pcfg_pull_none>, ++ /* vi_cif_d11 */ ++ <2 RK_PB2 1 &pcfg_pull_none>, ++ /* vi_cif_d12 */ ++ <2 RK_PB1 1 &pcfg_pull_none>, ++ /* vi_cif_d13 */ ++ <2 RK_PB0 1 &pcfg_pull_none>, ++ /* vi_cif_d14 */ ++ <2 RK_PA7 1 &pcfg_pull_none>, ++ /* vi_cif_d15 */ ++ <2 RK_PA6 1 &pcfg_pull_none>, ++ /* vi_cif_href */ ++ <3 RK_PA0 1 &pcfg_pull_none>, ++ /* vi_cif_vsync */ ++ <3 RK_PA1 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vo_lcdc { ++ /omit-if-no-ref/ ++ vo_lcdc_pins: vo_lcdc-pins { ++ rockchip,pins = ++ /* vo_lcdc_clk */ ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d0 */ ++ <3 RK_PD3 1 &pcfg_pull_none>, ++ /* vo_lcdc_d1 */ ++ <3 RK_PD2 1 &pcfg_pull_none>, ++ /* vo_lcdc_d2 */ ++ <3 RK_PD1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d3 */ ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d4 */ ++ <3 RK_PC7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d5 */ ++ <3 RK_PC6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d6 */ ++ <3 RK_PC5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d7 */ ++ <3 RK_PC4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d8 */ ++ <3 RK_PC3 1 &pcfg_pull_none>, ++ /* vo_lcdc_d9 */ ++ <3 RK_PC2 1 &pcfg_pull_none>, ++ /* vo_lcdc_d10 */ ++ <3 RK_PC1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d11 */ ++ <3 RK_PC0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d12 */ ++ <3 RK_PB7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d13 */ ++ <3 RK_PB6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d14 */ ++ <3 RK_PB5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d15 */ ++ <3 RK_PB4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d16 */ ++ <3 RK_PB3 1 &pcfg_pull_none>, ++ /* vo_lcdc_d17 */ ++ <3 RK_PB2 1 &pcfg_pull_none>, ++ /* vo_lcdc_d18 */ ++ <3 RK_PB1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d19 */ ++ <3 RK_PB0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d20 */ ++ <3 RK_PA7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d21 */ ++ <3 RK_PA6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d22 */ ++ <3 RK_PA5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d23 */ ++ <3 RK_PA4 1 &pcfg_pull_none>, ++ /* vo_lcdc_den */ ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ /* vo_lcdc_hsync */ ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ /* vo_lcdc_vsync */ ++ <3 RK_PD6 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vo_post { ++ /omit-if-no-ref/ ++ vo_post_pins: vo_post-pins { ++ rockchip,pins = ++ /* vo_post_empty */ ++ <4 RK_PA1 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vp0_sync { ++ /omit-if-no-ref/ ++ vp0_sync_pins: vp0_sync-pins { ++ rockchip,pins = ++ /* vp0_sync_out */ ++ <4 RK_PC5 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vp1_sync { ++ /omit-if-no-ref/ ++ vp1_sync_pins: vp1_sync-pins { ++ rockchip,pins = ++ /* vp1_sync_out */ ++ <4 RK_PC6 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vp2_sync { ++ /omit-if-no-ref/ ++ vp2_sync_pins: vp2_sync-pins { ++ rockchip,pins = ++ /* vp2_sync_out */ ++ <4 RK_PC7 3 &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++/* ++ * This part is edited handly. ++ */ ++&pinctrl { ++ pmic { ++ /omit-if-no-ref/ ++ pmic_pins: pmic-pins { ++ rockchip,pins = ++ /* pmic_int */ ++ <0 RK_PA6 9 &pcfg_pull_up>, ++ /* pmic_sleep */ ++ <0 RK_PA4 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vo { ++ /omit-if-no-ref/ ++ bt1120_pins: bt1120-pins { ++ rockchip,pins = ++ /* vo_lcdc_clk */ ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d3 */ ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d4 */ ++ <3 RK_PC7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d5 */ ++ <3 RK_PC6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d6 */ ++ <3 RK_PC5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d7 */ ++ <3 RK_PC4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d10 */ ++ <3 RK_PC1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d11 */ ++ <3 RK_PC0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d12 */ ++ <3 RK_PB7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d13 */ ++ <3 RK_PB6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d14 */ ++ <3 RK_PB5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d15 */ ++ <3 RK_PB4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d19 */ ++ <3 RK_PB0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d20 */ ++ <3 RK_PA7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d21 */ ++ <3 RK_PA6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d22 */ ++ <3 RK_PA5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d23 */ ++ <3 RK_PA4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ bt656_pins: bt656-pins { ++ rockchip,pins = ++ /* vo_lcdc_clk */ ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d3 */ ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d4 */ ++ <3 RK_PC7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d5 */ ++ <3 RK_PC6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d6 */ ++ <3 RK_PC5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d7 */ ++ <3 RK_PC4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d10 */ ++ <3 RK_PC1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d11 */ ++ <3 RK_PC0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d12 */ ++ <3 RK_PB7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ rgb3x8_pins_m0: rgb3x8-pins-m0 { ++ rockchip,pins = ++ /* vo_lcdc_clk */ ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d3 */ ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d4 */ ++ <3 RK_PC7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d5 */ ++ <3 RK_PC6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d6 */ ++ <3 RK_PC5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d7 */ ++ <3 RK_PC4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d10 */ ++ <3 RK_PC1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d11 */ ++ <3 RK_PC0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d12 */ ++ <3 RK_PB7 1 &pcfg_pull_none>, ++ /* vo_lcdc_den */ ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ /* vo_lcdc_hsync */ ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ /* vo_lcdc_vsync */ ++ <3 RK_PD6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ rgb3x8_pins_m1: rgb3x8-pins-m1 { ++ rockchip,pins = ++ /* vo_lcdc_clk */ ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d13 */ ++ <3 RK_PB6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d14 */ ++ <3 RK_PB5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d15 */ ++ <3 RK_PB4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d19 */ ++ <3 RK_PB0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d20 */ ++ <3 RK_PA7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d21 */ ++ <3 RK_PA6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d22 */ ++ <3 RK_PA5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d23 */ ++ <3 RK_PA4 1 &pcfg_pull_none>, ++ /* vo_lcdc_den */ ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ /* vo_lcdc_hsync */ ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ /* vo_lcdc_vsync */ ++ <3 RK_PD6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ rgb565_pins: rgb565-pins { ++ rockchip,pins = ++ /* vo_lcdc_clk */ ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d3 */ ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d4 */ ++ <3 RK_PC7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d5 */ ++ <3 RK_PC6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d6 */ ++ <3 RK_PC5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d7 */ ++ <3 RK_PC4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d10 */ ++ <3 RK_PC1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d11 */ ++ <3 RK_PC0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d12 */ ++ <3 RK_PB7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d13 */ ++ <3 RK_PB6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d14 */ ++ <3 RK_PB5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d15 */ ++ <3 RK_PB4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d19 */ ++ <3 RK_PB0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d20 */ ++ <3 RK_PA7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d21 */ ++ <3 RK_PA6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d22 */ ++ <3 RK_PA5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d23 */ ++ <3 RK_PA4 1 &pcfg_pull_none>, ++ /* vo_lcdc_den */ ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ /* vo_lcdc_hsync */ ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ /* vo_lcdc_vsync */ ++ <3 RK_PD6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ rgb666_pins: rgb666-pins { ++ rockchip,pins = ++ /* vo_lcdc_clk */ ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d2 */ ++ <3 RK_PD1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d3 */ ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d4 */ ++ <3 RK_PC7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d5 */ ++ <3 RK_PC6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d6 */ ++ <3 RK_PC5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d7 */ ++ <3 RK_PC4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d10 */ ++ <3 RK_PC1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d11 */ ++ <3 RK_PC0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d12 */ ++ <3 RK_PB7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d13 */ ++ <3 RK_PB6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d14 */ ++ <3 RK_PB5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d15 */ ++ <3 RK_PB4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d18 */ ++ <3 RK_PB1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d19 */ ++ <3 RK_PB0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d20 */ ++ <3 RK_PA7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d21 */ ++ <3 RK_PA6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d22 */ ++ <3 RK_PA5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d23 */ ++ <3 RK_PA4 1 &pcfg_pull_none>, ++ /* vo_lcdc_den */ ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ /* vo_lcdc_hsync */ ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ /* vo_lcdc_vsync */ ++ <3 RK_PD6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ rgb888_pins: rgb888-pins { ++ rockchip,pins = ++ /* vo_lcdc_clk */ ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d0 */ ++ <3 RK_PD3 1 &pcfg_pull_none>, ++ /* vo_lcdc_d1 */ ++ <3 RK_PD2 1 &pcfg_pull_none>, ++ /* vo_lcdc_d2 */ ++ <3 RK_PD1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d3 */ ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d4 */ ++ <3 RK_PC7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d5 */ ++ <3 RK_PC6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d6 */ ++ <3 RK_PC5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d7 */ ++ <3 RK_PC4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d8 */ ++ <3 RK_PC3 1 &pcfg_pull_none>, ++ /* vo_lcdc_d9 */ ++ <3 RK_PC2 1 &pcfg_pull_none>, ++ /* vo_lcdc_d10 */ ++ <3 RK_PC1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d11 */ ++ <3 RK_PC0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d12 */ ++ <3 RK_PB7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d13 */ ++ <3 RK_PB6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d14 */ ++ <3 RK_PB5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d15 */ ++ <3 RK_PB4 1 &pcfg_pull_none>, ++ /* vo_lcdc_d16 */ ++ <3 RK_PB3 1 &pcfg_pull_none>, ++ /* vo_lcdc_d17 */ ++ <3 RK_PB2 1 &pcfg_pull_none>, ++ /* vo_lcdc_d18 */ ++ <3 RK_PB1 1 &pcfg_pull_none>, ++ /* vo_lcdc_d19 */ ++ <3 RK_PB0 1 &pcfg_pull_none>, ++ /* vo_lcdc_d20 */ ++ <3 RK_PA7 1 &pcfg_pull_none>, ++ /* vo_lcdc_d21 */ ++ <3 RK_PA6 1 &pcfg_pull_none>, ++ /* vo_lcdc_d22 */ ++ <3 RK_PA5 1 &pcfg_pull_none>, ++ /* vo_lcdc_d23 */ ++ <3 RK_PA4 1 &pcfg_pull_none>, ++ /* vo_lcdc_den */ ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ /* vo_lcdc_hsync */ ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ /* vo_lcdc_vsync */ ++ <3 RK_PD6 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vo_ebc { ++ /omit-if-no-ref/ ++ vo_ebc_pins: vo_ebc-pins { ++ rockchip,pins = ++ /* vo_ebc_gdclk */ ++ <3 RK_PD5 2 &pcfg_pull_none>, ++ /* vo_ebc_gdoe */ ++ <3 RK_PA6 2 &pcfg_pull_none>, ++ /* vo_ebc_gdsp */ ++ <3 RK_PA5 2 &pcfg_pull_none>, ++ /* vo_ebc_sdce0 */ ++ <3 RK_PB3 2 &pcfg_pull_none>, ++ /* vo_ebc_sdclk */ ++ <3 RK_PD6 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo0 */ ++ <3 RK_PD3 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo1 */ ++ <3 RK_PD2 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo2 */ ++ <3 RK_PD1 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo3 */ ++ <3 RK_PD0 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo4 */ ++ <3 RK_PC7 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo5 */ ++ <3 RK_PC6 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo6 */ ++ <3 RK_PC5 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo7 */ ++ <3 RK_PC4 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo8 */ ++ <3 RK_PC3 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo9 */ ++ <3 RK_PC2 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo10 */ ++ <3 RK_PC1 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo11 */ ++ <3 RK_PC0 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo12 */ ++ <3 RK_PB7 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo13 */ ++ <3 RK_PB6 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo14 */ ++ <3 RK_PB5 2 &pcfg_pull_none>, ++ /* vo_ebc_sddo15 */ ++ <3 RK_PB4 2 &pcfg_pull_none>, ++ /* vo_ebc_sdle */ ++ <3 RK_PD4 2 &pcfg_pull_none>, ++ /* vo_ebc_sdoe */ ++ <3 RK_PD7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ vo_ebc_extern: vo_ebc-extern { ++ rockchip,pins = ++ /* vo_ebc_sdce1 */ ++ <3 RK_PB2 2 &pcfg_pull_none>, ++ /* vo_ebc_sdce2 */ ++ <3 RK_PB1 2 &pcfg_pull_none>, ++ /* vo_ebc_sdce3 */ ++ <3 RK_PB0 2 &pcfg_pull_none>, ++ /* vo_ebc_sdshr */ ++ <3 RK_PA4 2 &pcfg_pull_none>, ++ /* vo_ebc_vcom */ ++ <3 RK_PA7 2 &pcfg_pull_none>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi +@@ -0,0 +1,1678 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2023 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/ { ++ compatible = "rockchip,rk3576"; ++ ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ aliases { ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ i2c7 = &i2c7; ++ i2c8 = &i2c8; ++ i2c9 = &i2c9; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial5 = &uart5; ++ serial6 = &uart6; ++ serial7 = &uart7; ++ serial8 = &uart8; ++ serial9 = &uart9; ++ serial10 = &uart10; ++ serial11 = &uart11; ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; ++ spi4 = &spi4; ++ }; ++ ++ xin32k: clock-xin32k { ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "xin32k"; ++ #clock-cells = <0>; ++ }; ++ ++ xin24m: clock-xin24m { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ clock-output-names = "xin24m"; ++ }; ++ ++ spll: clock-spll { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <702000000>; ++ clock-output-names = "spll"; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu-map { ++ cluster0 { ++ core0 { ++ cpu = <&cpu_l0>; ++ }; ++ core1 { ++ cpu = <&cpu_l1>; ++ }; ++ core2 { ++ cpu = <&cpu_l2>; ++ }; ++ core3 { ++ cpu = <&cpu_l3>; ++ }; ++ }; ++ cluster1 { ++ core0 { ++ cpu = <&cpu_b0>; ++ }; ++ core1 { ++ cpu = <&cpu_b1>; ++ }; ++ core2 { ++ cpu = <&cpu_b2>; ++ }; ++ core3 { ++ cpu = <&cpu_b3>; ++ }; ++ }; ++ }; ++ ++ cpu_l0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <485>; ++ clocks = <&scmi_clk ARMCLK_L>; ++ operating-points-v2 = <&cluster0_opp_table>; ++ #cooling-cells = <2>; ++ dynamic-power-coefficient = <120>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ }; ++ ++ cpu_l1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x1>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <485>; ++ clocks = <&scmi_clk ARMCLK_L>; ++ operating-points-v2 = <&cluster0_opp_table>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ }; ++ ++ cpu_l2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x2>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <485>; ++ clocks = <&scmi_clk ARMCLK_L>; ++ operating-points-v2 = <&cluster0_opp_table>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ }; ++ ++ cpu_l3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x3>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <485>; ++ clocks = <&scmi_clk ARMCLK_L>; ++ operating-points-v2 = <&cluster0_opp_table>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ }; ++ ++ cpu_b0: cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x100>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk ARMCLK_B>; ++ operating-points-v2 = <&cluster1_opp_table>; ++ #cooling-cells = <2>; ++ dynamic-power-coefficient = <320>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ }; ++ ++ cpu_b1: cpu@101 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x101>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk ARMCLK_B>; ++ operating-points-v2 = <&cluster1_opp_table>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ }; ++ ++ cpu_b2: cpu@102 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x102>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk ARMCLK_B>; ++ operating-points-v2 = <&cluster1_opp_table>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ }; ++ ++ cpu_b3: cpu@103 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x103>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk ARMCLK_B>; ++ operating-points-v2 = <&cluster1_opp_table>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ }; ++ ++ idle-states { ++ entry-method = "psci"; ++ ++ CPU_SLEEP: cpu-sleep { ++ compatible = "arm,idle-state"; ++ arm,psci-suspend-param = <0x0010000>; ++ entry-latency-us = <120>; ++ exit-latency-us = <250>; ++ min-residency-us = <900>; ++ local-timer-stop; ++ }; ++ }; ++ }; ++ ++ cluster0_opp_table: opp-table-cluster0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <725000 725000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <825000 825000 950000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <900000 900000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <950000 950000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster1_opp_table: opp-table-cluster1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <700000 700000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <712500 712500 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <737500 737500 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <800000 800000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <862500 862500 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <925000 925000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ ++ opp-2304000000 { ++ opp-hz = /bits/ 64 <2304000000>; ++ opp-microvolt = <950000 950000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ gpu_opp_table: opp-table-gpu { ++ compatible = "operating-points-v2"; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <700000 700000 850000>; ++ }; ++ ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <700000 700000 850000>; ++ }; ++ ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <700000 700000 850000>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <700000 700000 850000>; ++ }; ++ ++ opp-700000000 { ++ opp-hz = /bits/ 64 <700000000>; ++ opp-microvolt = <725000 725000 850000>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <775000 775000 850000>; ++ }; ++ ++ opp-900000000 { ++ opp-hz = /bits/ 64 <900000000>; ++ opp-microvolt = <825000 825000 850000>; ++ }; ++ ++ opp-950000000 { ++ opp-hz = /bits/ 64 <950000000>; ++ opp-microvolt = <850000 850000 850000>; ++ }; ++ }; ++ ++ firmware { ++ scmi: scmi { ++ compatible = "arm,scmi-smc"; ++ arm,smc-id = <0x82000010>; ++ shmem = <&scmi_shmem>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ scmi_clk: protocol@14 { ++ reg = <0x14>; ++ #clock-cells = <1>; ++ }; ++ }; ++ }; ++ ++ pmu_a53: pmu-a53 { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; ++ }; ++ ++ pmu_a72: pmu-a72 { ++ compatible = "arm,cortex-a72-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ sys_grf: syscon@2600a000 { ++ compatible = "rockchip,rk3576-sys-grf", "syscon"; ++ reg = <0x0 0x2600a000 0x0 0x2000>; ++ }; ++ ++ bigcore_grf: syscon@2600c000 { ++ compatible = "rockchip,rk3576-bigcore-grf", "syscon"; ++ reg = <0x0 0x2600c000 0x0 0x2000>; ++ }; ++ ++ litcore_grf: syscon@2600e000 { ++ compatible = "rockchip,rk3576-litcore-grf", "syscon"; ++ reg = <0x0 0x2600e000 0x0 0x2000>; ++ }; ++ ++ cci_grf: syscon@26010000 { ++ compatible = "rockchip,rk3576-cci-grf", "syscon"; ++ reg = <0x0 0x26010000 0x0 0x2000>; ++ }; ++ ++ gpu_grf: syscon@26016000 { ++ compatible = "rockchip,rk3576-gpu-grf", "syscon"; ++ reg = <0x0 0x26016000 0x0 0x2000>; ++ }; ++ ++ npu_grf: syscon@26018000 { ++ compatible = "rockchip,rk3576-npu-grf", "syscon"; ++ reg = <0x0 0x26018000 0x0 0x2000>; ++ }; ++ ++ vo0_grf: syscon@2601a000 { ++ compatible = "rockchip,rk3576-vo0-grf", "syscon"; ++ reg = <0x0 0x2601a000 0x0 0x2000>; ++ }; ++ ++ usb_grf: syscon@2601e000 { ++ compatible = "rockchip,rk3576-usb-grf", "syscon"; ++ reg = <0x0 0x2601e000 0x0 0x1000>; ++ }; ++ ++ php_grf: syscon@26020000 { ++ compatible = "rockchip,rk3576-php-grf", "syscon"; ++ reg = <0x0 0x26020000 0x0 0x2000>; ++ }; ++ ++ pmu0_grf: syscon@26024000 { ++ compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; ++ reg = <0x0 0x26024000 0x0 0x1000>; ++ }; ++ ++ pmu1_grf: syscon@26026000 { ++ compatible = "rockchip,rk3576-pmu1-grf", "syscon"; ++ reg = <0x0 0x26026000 0x0 0x1000>; ++ }; ++ ++ pipe_phy0_grf: syscon@26028000 { ++ compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; ++ reg = <0x0 0x26028000 0x0 0x2000>; ++ }; ++ ++ pipe_phy1_grf: syscon@2602a000 { ++ compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; ++ reg = <0x0 0x2602a000 0x0 0x2000>; ++ }; ++ ++ usbdpphy_grf: syscon@2602c000 { ++ compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; ++ reg = <0x0 0x2602c000 0x0 0x2000>; ++ }; ++ ++ sdgmac_grf: syscon@26038000 { ++ compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; ++ reg = <0x0 0x26038000 0x0 0x1000>; ++ }; ++ ++ ioc_grf: syscon@26040000 { ++ compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; ++ reg = <0x0 0x26040000 0x0 0xc000>; ++ }; ++ ++ cru: clock-controller@27200000 { ++ compatible = "rockchip,rk3576-cru"; ++ reg = <0x0 0x27200000 0x0 0x50000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ ++ assigned-clocks = ++ <&cru CLK_AUDIO_FRAC_1_SRC>, ++ <&cru PLL_GPLL>, <&cru PLL_CPLL>, ++ <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, ++ <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>, ++ <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>, ++ <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>, ++ <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>, ++ <&cru ACLK_PHP_ROOT>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clock-rates = ++ <0>, ++ <1188000000>, <1000000000>, ++ <786432000>, <18432000>, ++ <96000000>, <128000000>, ++ <45158400>, <49152000>, ++ <500000000>, <250000000>, ++ <100000000>, <500000000>, ++ <250000000>; ++ }; ++ ++ i2c0: i2c@27300000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x27300000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m0_xfer>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@27310000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x27310000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 8>, <&dmac0 9>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1m0_xfer>; ++ status = "disabled"; ++ }; ++ ++ pmu: power-management@27380000 { ++ compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; ++ reg = <0x0 0x27380000 0x0 0x800>; ++ ++ power: power-controller { ++ compatible = "rockchip,rk3576-power-controller"; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3576_PD_NPU { ++ reg = ; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3576_PD_NPUTOP { ++ reg = ; ++ clocks = <&cru ACLK_RKNN0>, ++ <&cru ACLK_RKNN1>, ++ <&cru ACLK_RKNN_CBUF>, ++ <&cru CLK_RKNN_DSU0>, ++ <&cru HCLK_RKNN_CBUF>, ++ <&cru HCLK_RKNN_ROOT>, ++ <&cru HCLK_NPU_CM0_ROOT>, ++ <&cru PCLK_NPUTOP_ROOT>; ++ pm_qos = <&qos_npu_mcu>, ++ <&qos_npu_nsp0>, ++ <&qos_npu_nsp1>, ++ <&qos_npu_m0ro>, ++ <&qos_npu_m1ro>; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3576_PD_NPU0 { ++ reg = ; ++ clocks = <&cru HCLK_RKNN_ROOT>, ++ <&cru ACLK_RKNN0>; ++ pm_qos = <&qos_npu_m0>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3576_PD_NPU1 { ++ reg = ; ++ clocks = <&cru HCLK_RKNN_ROOT>, ++ <&cru ACLK_RKNN1>; ++ pm_qos = <&qos_npu_m1>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ ++ power-domain@RK3576_PD_GPU { ++ reg = ; ++ clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; ++ pm_qos = <&qos_gpu>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3576_PD_NVM { ++ reg = ; ++ clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>; ++ pm_qos = <&qos_emmc>, ++ <&qos_fspi0>; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3576_PD_SDGMAC { ++ reg = ; ++ clocks = <&cru ACLK_HSGPIO>, ++ <&cru ACLK_GMAC0>, ++ <&cru ACLK_GMAC1>, ++ <&cru CCLK_SRC_SDIO>, ++ <&cru CCLK_SRC_SDMMC0>, ++ <&cru HCLK_HSGPIO>, ++ <&cru HCLK_SDIO>, ++ <&cru HCLK_SDMMC0>, ++ <&cru PCLK_SDGMAC_ROOT>; ++ pm_qos = <&qos_fspi1>, ++ <&qos_gmac0>, ++ <&qos_gmac1>, ++ <&qos_sdio>, ++ <&qos_sdmmc>, ++ <&qos_flexbus>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ ++ power-domain@RK3576_PD_PHP { ++ reg = ; ++ clocks = <&cru ACLK_PHP_ROOT>, ++ <&cru PCLK_PHP_ROOT>, ++ <&cru ACLK_MMU0>, ++ <&cru ACLK_MMU1>; ++ pm_qos = <&qos_mmu0>, ++ <&qos_mmu1>; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3576_PD_SUBPHP { ++ reg = ; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ ++ power-domain@RK3576_PD_AUDIO { ++ reg = ; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3576_PD_VEPU1 { ++ reg = ; ++ clocks = <&cru ACLK_VEPU1>, ++ <&cru HCLK_VEPU1>; ++ pm_qos = <&qos_vepu1>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3576_PD_VPU { ++ reg = ; ++ clocks = <&cru ACLK_EBC>, ++ <&cru HCLK_EBC>, ++ <&cru ACLK_JPEG>, ++ <&cru HCLK_JPEG>, ++ <&cru ACLK_RGA2E_0>, ++ <&cru HCLK_RGA2E_0>, ++ <&cru ACLK_RGA2E_1>, ++ <&cru HCLK_RGA2E_1>, ++ <&cru ACLK_VDPP>, ++ <&cru HCLK_VDPP>; ++ pm_qos = <&qos_ebc>, ++ <&qos_jpeg>, ++ <&qos_rga0>, ++ <&qos_rga1>, ++ <&qos_vdpp>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3576_PD_VDEC { ++ reg = ; ++ clocks = <&cru ACLK_RKVDEC_ROOT>, ++ <&cru HCLK_RKVDEC>; ++ pm_qos = <&qos_rkvdec>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3576_PD_VI { ++ reg = ; ++ clocks = <&cru ACLK_VICAP>, ++ <&cru HCLK_VICAP>, ++ <&cru DCLK_VICAP>, ++ <&cru ACLK_VI_ROOT>, ++ <&cru HCLK_VI_ROOT>, ++ <&cru PCLK_VI_ROOT>, ++ <&cru CLK_ISP_CORE>, ++ <&cru ACLK_ISP>, ++ <&cru HCLK_ISP>, ++ <&cru CLK_CORE_VPSS>, ++ <&cru ACLK_VPSS>, ++ <&cru HCLK_VPSS>; ++ pm_qos = <&qos_isp_mro>, ++ <&qos_isp_mwo>, ++ <&qos_vicap_m0>, ++ <&qos_vpss_mro>, ++ <&qos_vpss_mwo>; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3576_PD_VEPU0 { ++ reg = ; ++ clocks = <&cru ACLK_VEPU0>, ++ <&cru HCLK_VEPU0>; ++ pm_qos = <&qos_vepu0>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ ++ power-domain@RK3576_PD_VOP { ++ reg = ; ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru HCLK_VOP_ROOT>, ++ <&cru PCLK_VOP_ROOT>; ++ pm_qos = <&qos_vop_m0>, ++ <&qos_vop_m1ro>; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3576_PD_USB { ++ reg = ; ++ clocks = <&cru PCLK_PHP_ROOT>, ++ <&cru ACLK_USB_ROOT>, ++ <&cru ACLK_MMU2>, ++ <&cru ACLK_SLV_MMU2>, ++ <&cru ACLK_UFS_SYS>; ++ pm_qos = <&qos_mmu2>, ++ <&qos_ufshc>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3576_PD_VO0 { ++ reg = ; ++ clocks = <&cru ACLK_HDCP0>, ++ <&cru HCLK_HDCP0>, ++ <&cru ACLK_VO0_ROOT>, ++ <&cru PCLK_VO0_ROOT>, ++ <&cru HCLK_VOP_ROOT>; ++ pm_qos = <&qos_hdcp0>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3576_PD_VO1 { ++ reg = ; ++ clocks = <&cru ACLK_HDCP1>, ++ <&cru HCLK_HDCP1>, ++ <&cru ACLK_VO1_ROOT>, ++ <&cru PCLK_VO1_ROOT>, ++ <&cru HCLK_VOP_ROOT>; ++ pm_qos = <&qos_hdcp1>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ }; ++ ++ gpu: gpu@27800000 { ++ compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; ++ reg = <0x0 0x27800000 0x0 0x200000>; ++ assigned-clocks = <&scmi_clk CLK_GPU>; ++ assigned-clock-rates = <198000000>; ++ clocks = <&cru CLK_GPU>; ++ clock-names = "core"; ++ dynamic-power-coefficient = <1625>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "job", "mmu", "gpu"; ++ operating-points-v2 = <&gpu_opp_table>; ++ power-domains = <&power RK3576_PD_GPU>; ++ #cooling-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ qos_hdcp1: qos@27f02000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f02000 0x0 0x20>; ++ }; ++ ++ qos_fspi1: qos@27f04000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f04000 0x0 0x20>; ++ }; ++ ++ qos_gmac0: qos@27f04080 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f04080 0x0 0x20>; ++ }; ++ ++ qos_gmac1: qos@27f04100 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f04100 0x0 0x20>; ++ }; ++ ++ qos_sdio: qos@27f04180 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f04180 0x0 0x20>; ++ }; ++ ++ qos_sdmmc: qos@27f04200 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f04200 0x0 0x20>; ++ }; ++ ++ qos_flexbus: qos@27f04280 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f04280 0x0 0x20>; ++ }; ++ ++ qos_gpu: qos@27f05000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f05000 0x0 0x20>; ++ }; ++ ++ qos_vepu1: qos@27f06000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f06000 0x0 0x20>; ++ }; ++ ++ qos_npu_mcu: qos@27f08000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f08000 0x0 0x20>; ++ }; ++ ++ qos_npu_nsp0: qos@27f08080 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f08080 0x0 0x20>; ++ }; ++ ++ qos_npu_nsp1: qos@27f08100 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f08100 0x0 0x20>; ++ }; ++ ++ qos_emmc: qos@27f09000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f09000 0x0 0x20>; ++ }; ++ ++ qos_fspi0: qos@27f09080 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f09080 0x0 0x20>; ++ }; ++ ++ qos_mmu0: qos@27f0a000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f0a000 0x0 0x20>; ++ }; ++ ++ qos_mmu1: qos@27f0a080 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f0a080 0x0 0x20>; ++ }; ++ ++ qos_rkvdec: qos@27f0c000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f0c000 0x0 0x20>; ++ }; ++ ++ qos_crypto: qos@27f0d000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f0d000 0x0 0x20>; ++ }; ++ ++ qos_mmu2: qos@27f0e000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f0e000 0x0 0x20>; ++ }; ++ ++ qos_ufshc: qos@27f0e080 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f0e080 0x0 0x20>; ++ }; ++ ++ qos_vepu0: qos@27f0f000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f0f000 0x0 0x20>; ++ }; ++ ++ qos_isp_mro: qos@27f10000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f10000 0x0 0x20>; ++ }; ++ ++ qos_isp_mwo: qos@27f10080 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f10080 0x0 0x20>; ++ }; ++ ++ qos_vicap_m0: qos@27f10100 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f10100 0x0 0x20>; ++ }; ++ ++ qos_vpss_mro: qos@27f10180 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f10180 0x0 0x20>; ++ }; ++ ++ qos_vpss_mwo: qos@27f10200 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f10200 0x0 0x20>; ++ }; ++ ++ qos_hdcp0: qos@27f11000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f11000 0x0 0x20>; ++ }; ++ ++ qos_vop_m0: qos@27f12800 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f12800 0x0 0x20>; ++ }; ++ ++ qos_vop_m1ro: qos@27f12880 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f12880 0x0 0x20>; ++ }; ++ ++ qos_ebc: qos@27f13000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f13000 0x0 0x20>; ++ }; ++ ++ qos_rga0: qos@27f13080 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f13080 0x0 0x20>; ++ }; ++ ++ qos_rga1: qos@27f13100 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f13100 0x0 0x20>; ++ }; ++ ++ qos_jpeg: qos@27f13180 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f13180 0x0 0x20>; ++ }; ++ ++ qos_vdpp: qos@27f13200 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f13200 0x0 0x20>; ++ }; ++ ++ qos_npu_m0: qos@27f20000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f20000 0x0 0x20>; ++ }; ++ ++ qos_npu_m1: qos@27f21000 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f21000 0x0 0x20>; ++ }; ++ ++ qos_npu_m0ro: qos@27f22080 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f22080 0x0 0x20>; ++ }; ++ ++ qos_npu_m1ro: qos@27f22100 { ++ compatible = "rockchip,rk3576-qos", "syscon"; ++ reg = <0x0 0x27f22100 0x0 0x20>; ++ }; ++ ++ gmac0: ethernet@2a220000 { ++ compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0x2a220000 0x0 0x10000>; ++ clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, ++ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, ++ <&cru CLK_GMAC0_PTP_REF>; ++ clock-names = "stmmaceth", "clk_mac_ref", ++ "pclk_mac", "aclk_mac", ++ "ptp_ref"; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ power-domains = <&power RK3576_PD_SDGMAC>; ++ resets = <&cru SRST_A_GMAC0>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&sdgmac_grf>; ++ rockchip,php-grf = <&ioc_grf>; ++ snps,axi-config = <&gmac0_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; ++ ++ mdio0: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ }; ++ ++ gmac0_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,rd_osr_lmt = <8>; ++ snps,wr_osr_lmt = <4>; ++ }; ++ ++ gmac0_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ ++ gmac0_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ }; ++ ++ gmac1: ethernet@2a230000 { ++ compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0x2a230000 0x0 0x10000>; ++ clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, ++ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, ++ <&cru CLK_GMAC1_PTP_REF>; ++ clock-names = "stmmaceth", "clk_mac_ref", ++ "pclk_mac", "aclk_mac", ++ "ptp_ref"; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ power-domains = <&power RK3576_PD_SDGMAC>; ++ resets = <&cru SRST_A_GMAC1>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&sdgmac_grf>; ++ rockchip,php-grf = <&ioc_grf>; ++ snps,axi-config = <&gmac1_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; ++ ++ mdio1: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ }; ++ ++ gmac1_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,rd_osr_lmt = <8>; ++ snps,wr_osr_lmt = <4>; ++ }; ++ ++ gmac1_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ ++ gmac1_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ }; ++ ++ sdmmc: mmc@2a310000 { ++ compatible = "rockchip,rk3576-dw-mshc"; ++ reg = <0x0 0x2a310000 0x0 0x4000>; ++ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; ++ clock-names = "biu", "ciu"; ++ fifo-depth = <0x100>; ++ interrupts = ; ++ max-frequency = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; ++ power-domains = <&power RK3576_PD_SDGMAC>; ++ resets = <&cru SRST_H_SDMMC0>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ ++ sdhci: mmc@2a330000 { ++ compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; ++ reg = <0x0 0x2a330000 0x0 0x10000>; ++ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; ++ assigned-clock-rates = <200000000>, <24000000>, <200000000>; ++ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, ++ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, ++ <&cru TCLK_EMMC>; ++ clock-names = "core", "bus", "axi", "block", "timer"; ++ interrupts = ; ++ max-frequency = <200000000>; ++ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, ++ <&emmc_cmd>, <&emmc_strb>; ++ pinctrl-names = "default"; ++ power-domains = <&power RK3576_PD_NVM>; ++ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, ++ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, ++ <&cru SRST_T_EMMC>; ++ reset-names = "core", "bus", "axi", "block", "timer"; ++ supports-cqe; ++ status = "disabled"; ++ }; ++ ++ gic: interrupt-controller@2a701000 { ++ compatible = "arm,gic-400"; ++ reg = <0x0 0x2a701000 0 0x10000>, ++ <0x0 0x2a702000 0 0x10000>, ++ <0x0 0x2a704000 0 0x10000>, ++ <0x0 0x2a706000 0 0x10000>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ }; ++ ++ dmac0: dma-controller@2ab90000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0x2ab90000 0x0 0x4000>; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_DMAC0>; ++ clock-names = "apb_pclk"; ++ interrupts = , ++ ; ++ #dma-cells = <1>; ++ }; ++ ++ dmac1: dma-controller@2abb0000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0x2abb0000 0x0 0x4000>; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_DMAC1>; ++ clock-names = "apb_pclk"; ++ interrupts = , ++ ; ++ #dma-cells = <1>; ++ }; ++ ++ dmac2: dma-controller@2abd0000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0x2abd0000 0x0 0x4000>; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_DMAC2>; ++ clock-names = "apb_pclk"; ++ interrupts = , ++ ; ++ #dma-cells = <1>; ++ }; ++ ++ i2c1: i2c@2ac40000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x2ac40000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1m0_xfer>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@2ac50000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x2ac50000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2m0_xfer>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@2ac60000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x2ac60000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3m0_xfer>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@2ac70000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x2ac70000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4m0_xfer>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@2ac80000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x2ac80000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c5m0_xfer>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ ++ i2c6: i2c@2ac90000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x2ac90000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c6m0_xfer>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c7: i2c@2aca0000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x2aca0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c7m0_xfer>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c8: i2c@2acb0000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x2acb0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8m0_xfer>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ timer0: timer@2acc0000 { ++ compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; ++ reg = <0x0 0x2acc0000 0x0 0x20>; ++ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; ++ clock-names = "pclk", "timer"; ++ interrupts = ; ++ }; ++ ++ wdt: watchdog@2ace0000 { ++ compatible = "rockchip,rk3576-wdt", "snps,dw-wdt"; ++ reg = <0x0 0x2ace0000 0x0 0x100>; ++ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; ++ clock-names = "tclk", "pclk"; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ spi0: spi@2acf0000 { ++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0x2acf0000 0x0 0x1000>; ++ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 14>, <&dmac0 15>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ num-cs = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@2ad00000 { ++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0x2ad00000 0x0 0x1000>; ++ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 16>, <&dmac0 17>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ num-cs = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@2ad10000 { ++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0x2ad10000 0x0 0x1000>; ++ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac1 15>, <&dmac1 16>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ num-cs = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi3: spi@2ad20000 { ++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0x2ad20000 0x0 0x1000>; ++ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac1 17>, <&dmac1 18>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ num-cs = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi4: spi@2ad30000 { ++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0x2ad30000 0x0 0x1000>; ++ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac2 12>, <&dmac2 13>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ num-cs = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart0: serial@2ad40000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2ad40000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 6>, <&dmac0 7>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ pinctrl-0 = <&uart0m0_xfer>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@2ad50000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2ad50000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 10>, <&dmac0 11>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@2ad60000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2ad60000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 12>, <&dmac0 13>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ pinctrl-0 = <&uart3m0_xfer>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@2ad70000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2ad70000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac1 9>, <&dmac1 10>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ pinctrl-0 = <&uart4m0_xfer>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@2ad80000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2ad80000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac1 11>, <&dmac1 12>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ pinctrl-0 = <&uart5m0_xfer>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ uart6: serial@2ad90000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2ad90000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac1 13>, <&dmac1 14>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ pinctrl-0 = <&uart6m0_xfer>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ uart7: serial@2ada0000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2ada0000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 6>, <&dmac2 7>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ pinctrl-0 = <&uart7m0_xfer>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ uart8: serial@2adb0000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2adb0000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 8>, <&dmac2 9>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ pinctrl-0 = <&uart8m0_xfer>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ uart9: serial@2adc0000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2adc0000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 10>, <&dmac2 11>; ++ dma-names = "tx", "rx"; ++ interrupts = ; ++ pinctrl-0 = <&uart9m0_xfer>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ ++ saradc: adc@2ae00000 { ++ compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; ++ reg = <0x0 0x2ae00000 0x0 0x10000>; ++ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; ++ clock-names = "saradc", "apb_pclk"; ++ interrupts = ; ++ resets = <&cru SRST_P_SARADC>; ++ reset-names = "saradc-apb"; ++ #io-channel-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ i2c9: i2c@2ae80000 { ++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0x2ae80000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c9m0_xfer>; ++ resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>; ++ reset-names = "i2c", "apb"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart10: serial@2afc0000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2afc0000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 21>, <&dmac2 22>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart10m0_xfer>; ++ status = "disabled"; ++ }; ++ ++ uart11: serial@2afd0000 { ++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0x2afd0000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 23>, <&dmac2 24>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart11m0_xfer>; ++ status = "disabled"; ++ }; ++ ++ sram: sram@3ff88000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0x3ff88000 0x0 0x78000>; ++ ranges = <0x0 0x0 0x3ff88000 0x78000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ /* start address and size should be 4k align */ ++ rkvdec_sram: rkvdec-sram@0 { ++ reg = <0x0 0x78000>; ++ }; ++ }; ++ ++ scmi_shmem: scmi-shmem@4010f000 { ++ compatible = "arm,scmi-shmem"; ++ reg = <0x0 0x4010f000 0x0 0x100>; ++ }; ++ ++ pinctrl: pinctrl { ++ compatible = "rockchip,rk3576-pinctrl"; ++ rockchip,grf = <&ioc_grf>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ gpio0: gpio@27320000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0x27320000 0x0 0x200>; ++ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 0 32>; ++ interrupts = ; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio1: gpio@2ae10000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0x2ae10000 0x0 0x200>; ++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 32 32>; ++ interrupts = ; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio2: gpio@2ae20000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0x2ae20000 0x0 0x200>; ++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 64 32>; ++ interrupts = ; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio3: gpio@2ae30000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0x2ae30000 0x0 0x200>; ++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 96 32>; ++ interrupts = ; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio4: gpio@2ae40000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0x2ae40000 0x0 0x200>; ++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 128 32>; ++ interrupts = ; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ }; ++ }; ++}; ++ ++#include "rk3576-pinctrl.dtsi" diff --git a/target/linux/rockchip/patches-6.6/106-rockchip-rock-pi-4.patch b/target/linux/rockchip/patches-6.6/106-rockchip-rock-pi-4.patch index 3bdfe022f..e3da05f6f 100644 --- a/target/linux/rockchip/patches-6.6/106-rockchip-rock-pi-4.patch +++ b/target/linux/rockchip/patches-6.6/106-rockchip-rock-pi-4.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -38,6 +38,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gr +@@ -39,6 +39,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gr dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-dumo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb @@ -9,7 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb -@@ -59,6 +61,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro +@@ -60,6 +62,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4c-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4se.dtb diff --git a/target/linux/rockchip/patches-6.6/113-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support.patch b/target/linux/rockchip/patches-6.6/113-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support.patch index ac646edc1..5c9e71410 100644 --- a/target/linux/rockchip/patches-6.6/113-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support.patch +++ b/target/linux/rockchip/patches-6.6/113-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support.patch @@ -250,7 +250,7 @@ Signed-off-by: David Wu .set_rgmii_speed = rk3568_set_gmac_speed, .set_rmii_speed = rk3568_set_gmac_speed, .regs_valid = true, -@@ -1580,7 +1750,7 @@ static int gmac_clk_enable(struct rk_pri +@@ -1735,7 +1905,7 @@ static int gmac_clk_enable(struct rk_pri return 0; } @@ -259,7 +259,7 @@ Signed-off-by: David Wu { struct regulator *ldo = bsp_priv->regulator; int ret; -@@ -1679,6 +1849,18 @@ static struct rk_priv_data *rk_gmac_setu +@@ -1834,6 +2004,18 @@ static struct rk_priv_data *rk_gmac_setu "rockchip,grf"); bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,php-grf"); @@ -278,7 +278,7 @@ Signed-off-by: David Wu if (plat->phy_node) { bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, -@@ -1756,11 +1938,19 @@ static int rk_gmac_powerup(struct rk_pri +@@ -1911,11 +2093,19 @@ static int rk_gmac_powerup(struct rk_pri dev_info(dev, "init for RMII\n"); bsp_priv->ops->set_to_rmii(bsp_priv); break; @@ -299,7 +299,7 @@ Signed-off-by: David Wu if (ret) { gmac_clk_enable(bsp_priv, false); return ret; -@@ -1781,7 +1971,7 @@ static void rk_gmac_powerdown(struct rk_ +@@ -1936,7 +2126,7 @@ static void rk_gmac_powerdown(struct rk_ pm_runtime_put_sync(&gmac->pdev->dev); @@ -308,7 +308,7 @@ Signed-off-by: David Wu gmac_clk_enable(gmac, false); } -@@ -1802,6 +1992,9 @@ static void rk_fix_speed(void *priv, uns +@@ -1957,6 +2147,9 @@ static void rk_fix_speed(void *priv, uns if (bsp_priv->ops->set_rmii_speed) bsp_priv->ops->set_rmii_speed(bsp_priv, speed); break; diff --git a/target/linux/rockchip/patches-6.6/120-phy-rockchip-naneng-combo-add-rk3576-support.patch b/target/linux/rockchip/patches-6.6/120-phy-rockchip-naneng-combo-add-rk3576-support.patch new file mode 100644 index 000000000..943584dba --- /dev/null +++ b/target/linux/rockchip/patches-6.6/120-phy-rockchip-naneng-combo-add-rk3576-support.patch @@ -0,0 +1,375 @@ +From: Frank Wang +To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, + krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de +Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, + william.wu@rock-chips.com, tim.chen@rock-chips.com, + Kever Yang , + Frank Wang +Subject: [PATCH v3 2/2] phy: rockchip-naneng-combo: add rk3576 support +Date: Fri, 18 Oct 2024 14:25:26 +0800 [thread overview] +Message-ID: <20241018062526.33994-2-frawang.cn@gmail.com> (raw) +In-Reply-To: <20241018062526.33994-1-frawang.cn@gmail.com> + +From: Kever Yang + +Rockchip RK3576 integrates two naneng-combo PHY, PHY0 is used for +PCIE and SATA, PHY1 is used for PCIE, SATA and USB3. + +This adds device specific data support. + +Signed-off-by: Kever Yang +Signed-off-by: William Wu +Signed-off-by: Frank Wang +--- +Changelog: +v3: + - add detail commit contents. + - using FIELD_PREP() instead of bit shift. + - leave a blank line after each switch break case. + +v2: + - using constants macro instead of magic values. + - add more comments for PHY tuning operations. + +v1: + - https://patchwork.kernel.org/project/linux-phy/patch/20241015013351.4884-2-frawang.cn@gmail.com/ + + .../rockchip/phy-rockchip-naneng-combphy.c | 279 ++++++++++++++++++ + 1 file changed, 279 insertions(+) + +--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -37,6 +37,10 @@ + #define PHYREG8 0x1C + #define PHYREG8_SSC_EN BIT(4) + ++#define PHYREG10 0x24 ++#define PHYREG10_SSC_PCM_MASK GENMASK(3, 0) ++#define PHYREG10_SSC_PCM_3500PPM 7 ++ + #define PHYREG11 0x28 + #define PHYREG11_SU_TRIM_0_7 0xF0 + +@@ -61,17 +65,26 @@ + #define PHYREG16 0x3C + #define PHYREG16_SSC_CNT_VALUE 0x5f + ++#define PHYREG17 0x40 ++ + #define PHYREG18 0x44 + #define PHYREG18_PLL_LOOP 0x32 + ++#define PHYREG21 0x50 ++#define PHYREG21_RX_SQUELCH_VAL 0x0D ++ + #define PHYREG27 0x6C + #define PHYREG27_RX_TRIM_RK3588 0x4C + ++#define PHYREG30 0x74 ++ + #define PHYREG32 0x7C + #define PHYREG32_SSC_MASK GENMASK(7, 4) ++#define PHYREG32_SSC_DIR_MASK GENMASK(5, 4) + #define PHYREG32_SSC_DIR_SHIFT 4 + #define PHYREG32_SSC_UPWARD 0 + #define PHYREG32_SSC_DOWNWARD 1 ++#define PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6) + #define PHYREG32_SSC_OFFSET_SHIFT 6 + #define PHYREG32_SSC_OFFSET_500PPM 1 + +@@ -79,6 +92,7 @@ + #define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) + #define PHYREG33_PLL_KVCO_SHIFT 2 + #define PHYREG33_PLL_KVCO_VALUE 2 ++#define PHYREG33_PLL_KVCO_VALUE_RK3576 4 + + struct rockchip_combphy_priv; + +@@ -98,6 +112,7 @@ struct rockchip_combphy_grfcfg { + struct combphy_reg pipe_rxterm_set; + struct combphy_reg pipe_txelec_set; + struct combphy_reg pipe_txcomp_set; ++ struct combphy_reg pipe_clk_24m; + struct combphy_reg pipe_clk_25m; + struct combphy_reg pipe_clk_100m; + struct combphy_reg pipe_phymode_sel; +@@ -584,6 +599,266 @@ static const struct rockchip_combphy_cfg + .combphy_cfg = rk3568_combphy_cfg, + }; + ++static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) ++{ ++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; ++ unsigned long rate; ++ u32 val; ++ ++ switch (priv->type) { ++ case PHY_TYPE_PCIE: ++ /* Set SSC downward spread spectrum */ ++ val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD); ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); ++ break; ++ ++ case PHY_TYPE_USB3: ++ /* Set SSC downward spread spectrum */ ++ val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD); ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ ++ /* Enable adaptive CTLE for USB3.0 Rx */ ++ val = readl(priv->mmio + PHYREG15); ++ val |= PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + PHYREG15); ++ ++ /* Set PLL KVCO fine tuning signals */ ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33); ++ ++ /* Set PLL LPF R1 to su_trim[10:7]=1001 */ ++ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ ++ /* Set PLL input clock divider 1/2 */ ++ val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2); ++ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6); ++ ++ /* Set PLL loop divider */ ++ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); ++ ++ /* Set PLL KVCO to min and set PLL charge pump current to max */ ++ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ ++ /* Set Rx squelch input filler bandwidth */ ++ writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); ++ break; ++ ++ case PHY_TYPE_SATA: ++ /* Enable adaptive CTLE for SATA Rx */ ++ val = readl(priv->mmio + PHYREG15); ++ val |= PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + PHYREG15); ++ ++ /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ ++ val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; ++ val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; ++ writel(val, priv->mmio + PHYREG7); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); ++ break; ++ ++ default: ++ dev_err(priv->dev, "incompatible PHY type\n"); ++ return -EINVAL; ++ } ++ ++ rate = clk_get_rate(priv->refclk); ++ ++ switch (rate) { ++ case REF_CLOCK_24MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); ++ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { ++ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ ++ val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE); ++ rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, ++ val, PHYREG15); ++ ++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ } else if (priv->type == PHY_TYPE_PCIE) { ++ /* PLL KVCO tuning fine */ ++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ val, PHYREG33); ++ ++ /* Set up rx_pck invert and rx msb to disable */ ++ writel(0x00, priv->mmio + PHYREG27); ++ ++ /* ++ * Set up SU adjust signal: ++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min ++ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b011 ++ * su_trim[31:24], CKDRV adjust ++ */ ++ writel(0x90, priv->mmio + PHYREG11); ++ writel(0x02, priv->mmio + PHYREG12); ++ writel(0x57, priv->mmio + PHYREG14); ++ ++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ } ++ break; ++ ++ case REF_CLOCK_25MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); ++ break; ++ ++ case REF_CLOCK_100MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); ++ if (priv->type == PHY_TYPE_PCIE) { ++ /* gate_tx_pck_sel length select work for L1SS */ ++ writel(0xc0, priv->mmio + PHYREG30); ++ ++ /* PLL KVCO tuning fine */ ++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ val, PHYREG33); ++ ++ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ ++ writel(0x4c, priv->mmio + PHYREG27); ++ ++ /* ++ * Set up SU adjust signal: ++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min ++ * su_trim[15:8], bypass PLL loop divider code, and ++ * PLL LPF R1 adujst bits[9:7]=3'b101 ++ * su_trim[23:16], CKRCV adjust ++ * su_trim[31:24], CKDRV adjust ++ */ ++ writel(0x90, priv->mmio + PHYREG11); ++ writel(0x43, priv->mmio + PHYREG12); ++ writel(0x88, priv->mmio + PHYREG13); ++ writel(0x56, priv->mmio + PHYREG14); ++ } else if (priv->type == PHY_TYPE_SATA) { ++ /* downward spread spectrum +500ppm */ ++ val = FIELD_PREP(PHYREG32_SSC_DIR_MASK, PHYREG32_SSC_DOWNWARD); ++ val |= FIELD_PREP(PHYREG32_SSC_OFFSET_MASK, PHYREG32_SSC_OFFSET_500PPM); ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ ++ /* ssc ppm adjust to 3500ppm */ ++ rockchip_combphy_updatel(priv, PHYREG10_SSC_PCM_MASK, ++ PHYREG10_SSC_PCM_3500PPM, ++ PHYREG10); ++ } ++ break; ++ ++ default: ++ dev_err(priv->dev, "Unsupported rate: %lu\n", rate); ++ return -EINVAL; ++ } ++ ++ if (priv->ext_refclk) { ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); ++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { ++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ val, PHYREG33); ++ ++ /* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */ ++ writel(0x0c, priv->mmio + PHYREG27); ++ ++ /* ++ * Set up SU adjust signal: ++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min ++ * su_trim[15:8], bypass PLL loop divider code, and ++ * PLL LPF R1 adujst bits[9:7]=3'b101. ++ * su_trim[23:16], CKRCV adjust ++ * su_trim[31:24], CKDRV adjust ++ */ ++ writel(0x90, priv->mmio + PHYREG11); ++ writel(0x43, priv->mmio + PHYREG12); ++ writel(0x88, priv->mmio + PHYREG13); ++ writel(0x56, priv->mmio + PHYREG14); ++ } ++ } ++ ++ if (priv->enable_ssc) { ++ val = readl(priv->mmio + PHYREG8); ++ val |= PHYREG8_SSC_EN; ++ writel(val, priv->mmio + PHYREG8); ++ ++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { ++ /* Set PLL loop divider */ ++ writel(0x00, priv->mmio + PHYREG17); ++ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); ++ ++ /* Set up rx_pck invert and rx msb to disable */ ++ writel(0x00, priv->mmio + PHYREG27); ++ ++ /* ++ * Set up SU adjust signal: ++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min ++ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101 ++ * su_trim[23:16], CKRCV adjust ++ * su_trim[31:24], CKDRV adjust ++ */ ++ writel(0x90, priv->mmio + PHYREG11); ++ writel(0x02, priv->mmio + PHYREG12); ++ writel(0x08, priv->mmio + PHYREG13); ++ writel(0x57, priv->mmio + PHYREG14); ++ writel(0x40, priv->mmio + PHYREG15); ++ ++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ ++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576); ++ writel(val, priv->mmio + PHYREG33); ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { ++ /* pipe-phy-grf */ ++ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, ++ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, ++ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, ++ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, ++ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, ++ .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, ++ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, ++ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, ++ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, ++ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, ++ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, ++ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, ++ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, ++ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, ++ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, ++ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, ++ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, ++ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, ++ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, ++ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, ++ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, ++ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, ++ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, ++ /* php-grf */ ++ .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, ++ .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, ++}; ++ ++static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { ++ .num_phys = 2, ++ .phy_ids = { ++ 0x2b050000, ++ 0x2b060000 ++ }, ++ .grfcfg = &rk3576_combphy_grfcfgs, ++ .combphy_cfg = rk3576_combphy_cfg, ++}; ++ + static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) + { + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; +@@ -776,6 +1051,10 @@ static const struct of_device_id rockchi + .data = &rk3568_combphy_cfgs, + }, + { ++ .compatible = "rockchip,rk3576-naneng-combphy", ++ .data = &rk3576_combphy_cfgs, ++ }, ++ { + .compatible = "rockchip,rk3588-naneng-combphy", + .data = &rk3588_combphy_cfgs, + }, diff --git a/target/linux/rockchip/patches-6.6/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch b/target/linux/rockchip/patches-6.6/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch index cef31ad0f..ce42f18e7 100644 --- a/target/linux/rockchip/patches-6.6/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch +++ b/target/linux/rockchip/patches-6.6/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch @@ -35,7 +35,7 @@ to status_led in accordance with the board schematics. --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev +@@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-na dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s-plus.dtb diff --git a/target/linux/rockchip/patches-6.6/210-rockchip-rk356x-add-support-for-new-boards.patch b/target/linux/rockchip/patches-6.6/210-rockchip-rk356x-add-support-for-new-boards.patch index 192bd9a10..9f3cb9bff 100644 --- a/target/linux/rockchip/patches-6.6/210-rockchip-rk356x-add-support-for-new-boards.patch +++ b/target/linux/rockchip/patches-6.6/210-rockchip-rk356x-add-support-for-new-boards.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -81,10 +81,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-an +@@ -82,10 +82,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-an dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb @@ -13,7 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb -@@ -98,9 +100,20 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lu +@@ -99,9 +101,20 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lu dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb diff --git a/target/linux/rockchip/patches-6.6/211-rockchip-rk3399-add-support-more-devices.patch b/target/linux/rockchip/patches-6.6/211-rockchip-rk3399-add-support-more-devices.patch index 10b0bfe86..87aa98cc6 100644 --- a/target/linux/rockchip/patches-6.6/211-rockchip-rk3399-add-support-more-devices.patch +++ b/target/linux/rockchip/patches-6.6/211-rockchip-rk3399-add-support-more-devices.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -68,6 +68,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro +@@ -69,6 +69,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb diff --git a/target/linux/rockchip/patches-6.6/212-rockchip-rk3528-add-support-for-new-boards.patch b/target/linux/rockchip/patches-6.6/212-rockchip-rk3528-add-support-for-new-boards.patch index 56594d8ab..abd23fad3 100644 --- a/target/linux/rockchip/patches-6.6/212-rockchip-rk3528-add-support-for-new-boards.patch +++ b/target/linux/rockchip/patches-6.6/212-rockchip-rk3528-add-support-for-new-boards.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -80,6 +80,13 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro +@@ -81,6 +81,13 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb diff --git a/target/linux/rockchip/patches-6.6/301-pinctrl-rockchip-add-rk3528-support.patch b/target/linux/rockchip/patches-6.6/301-pinctrl-rockchip-add-rk3528-support.patch index 27bfa756d..b8bf869eb 100644 --- a/target/linux/rockchip/patches-6.6/301-pinctrl-rockchip-add-rk3528-support.patch +++ b/target/linux/rockchip/patches-6.6/301-pinctrl-rockchip-add-rk3528-support.patch @@ -12,7 +12,7 @@ Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c -@@ -2005,6 +2005,150 @@ static int rk3568_calc_pull_reg_and_bit( +@@ -2036,6 +2036,150 @@ static int rk3568_calc_pull_reg_and_bit( return 0; } @@ -163,7 +163,7 @@ Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536 #define RK3568_DRV_PMU_OFFSET 0x70 #define RK3568_DRV_GRF_OFFSET 0x200 #define RK3568_DRV_BITS_PER_PIN 8 -@@ -2328,6 +2472,10 @@ static int rockchip_set_drive_perpin(str +@@ -2495,6 +2639,10 @@ static int rockchip_set_drive_perpin(str rmask_bits = RK3588_DRV_BITS_PER_PIN; ret = strength; goto config; @@ -174,31 +174,31 @@ Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536 } else if (ctrl->type == RK3568) { rmask_bits = RK3568_DRV_BITS_PER_PIN; ret = (1 << (strength + 1)) - 1; -@@ -2468,6 +2616,7 @@ static int rockchip_get_pull(struct rock +@@ -2639,6 +2787,7 @@ static int rockchip_get_pull(struct rock case RK3328: case RK3368: case RK3399: + case RK3528: case RK3568: + case RK3576: case RK3588: - pull_type = bank->pull_type[pin_num / 8]; -@@ -2527,6 +2676,7 @@ static int rockchip_set_pull(struct rock +@@ -2699,6 +2848,7 @@ static int rockchip_set_pull(struct rock case RK3328: case RK3368: case RK3399: + case RK3528: case RK3568: + case RK3576: case RK3588: - pull_type = bank->pull_type[pin_num / 8]; -@@ -2792,6 +2942,7 @@ static bool rockchip_pinconf_pull_valid( +@@ -2965,6 +3115,7 @@ static bool rockchip_pinconf_pull_valid( case RK3328: case RK3368: case RK3399: + case RK3528: case RK3568: + case RK3576: case RK3588: - return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); -@@ -3917,6 +4068,49 @@ static struct rockchip_pin_ctrl rk3399_p +@@ -4091,6 +4242,49 @@ static struct rockchip_pin_ctrl rk3399_p .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; @@ -248,7 +248,7 @@ Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536 static struct rockchip_pin_bank rk3568_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, -@@ -4010,6 +4204,8 @@ static const struct of_device_id rockchi +@@ -4215,6 +4409,8 @@ static const struct of_device_id rockchi .data = &rk3368_pin_ctrl }, { .compatible = "rockchip,rk3399-pinctrl", .data = &rk3399_pin_ctrl }, @@ -256,7 +256,7 @@ Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536 + .data = &rk3528_pin_ctrl }, { .compatible = "rockchip,rk3568-pinctrl", .data = &rk3568_pin_ctrl }, - { .compatible = "rockchip,rk3588-pinctrl", + { .compatible = "rockchip,rk3576-pinctrl", --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -196,6 +196,7 @@ enum rockchip_pinctrl_type { @@ -265,5 +265,5 @@ Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536 RK3399, + RK3528, RK3568, + RK3576, RK3588, - }; diff --git a/target/linux/rockchip/patches-6.6/303-soc-rockchip-power-domain-Add-always-on.patch b/target/linux/rockchip/patches-6.6/303-soc-rockchip-power-domain-Add-always-on.patch index 83434c946..f46ef605d 100644 --- a/target/linux/rockchip/patches-6.6/303-soc-rockchip-power-domain-Add-always-on.patch +++ b/target/linux/rockchip/patches-6.6/303-soc-rockchip-power-domain-Add-always-on.patch @@ -12,15 +12,15 @@ Change-Id: Ic57f7f3a564f7d71b680e3c435d0460474b5a4a0 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c -@@ -45,6 +45,7 @@ struct rockchip_domain_info { - int req_w_mask; +@@ -47,6 +47,7 @@ struct rockchip_domain_info { + int clk_ungate_mask; int mem_status_mask; int repair_status_mask; + bool always_on; u32 pwr_offset; u32 mem_offset; u32 req_offset; -@@ -612,6 +613,26 @@ static void rockchip_pd_detach_dev(struc +@@ -660,6 +661,26 @@ static void rockchip_pd_detach_dev(struc pm_clk_destroy(dev); } @@ -47,7 +47,7 @@ Change-Id: Ic57f7f3a564f7d71b680e3c435d0460474b5a4a0 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, struct device_node *node) { -@@ -730,6 +751,11 @@ static int rockchip_pm_add_one_domain(st +@@ -778,6 +799,11 @@ static int rockchip_pm_add_one_domain(st pd->genpd.flags = GENPD_FLAG_PM_CLK; if (pd_info->active_wakeup) pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; diff --git a/target/linux/rockchip/patches-6.6/304-soc-rockchip-power-domain-add-rk3528-support.patch b/target/linux/rockchip/patches-6.6/304-soc-rockchip-power-domain-add-rk3528-support.patch index f83ceafa9..842dd1855 100644 --- a/target/linux/rockchip/patches-6.6/304-soc-rockchip-power-domain-add-rk3528-support.patch +++ b/target/linux/rockchip/patches-6.6/304-soc-rockchip-power-domain-add-rk3528-support.patch @@ -20,9 +20,9 @@ Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612 #include +#include #include + #include #include - -@@ -125,6 +126,20 @@ struct rockchip_pmu { +@@ -128,6 +129,20 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } @@ -43,7 +43,7 @@ Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \ { \ .name = _name, \ -@@ -171,6 +186,9 @@ struct rockchip_pmu { +@@ -193,6 +208,9 @@ struct rockchip_pmu { #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ DOMAIN(name, pwr, status, req, req, req, wakeup) @@ -53,7 +53,7 @@ Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612 #define DOMAIN_RK3568(name, pwr, req, wakeup) \ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) -@@ -1125,6 +1143,18 @@ static const struct rockchip_domain_info +@@ -1173,6 +1191,18 @@ static const struct rockchip_domain_info [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; @@ -72,7 +72,7 @@ Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612 static const struct rockchip_domain_info rk3568_pm_domains[] = { [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), -@@ -1304,6 +1334,17 @@ static const struct rockchip_pmu_info rk +@@ -1374,6 +1404,17 @@ static const struct rockchip_pmu_info rk .domain_info = rk3399_pm_domains, }; @@ -90,7 +90,7 @@ Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612 static const struct rockchip_pmu_info rk3568_pmu = { .pwr_offset = 0xa0, .status_offset = 0x98, -@@ -1387,6 +1428,10 @@ static const struct of_device_id rockchi +@@ -1473,6 +1514,10 @@ static const struct of_device_id rockchi .data = (void *)&rk3399_pmu, }, { diff --git a/target/linux/rockchip/patches-6.6/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch b/target/linux/rockchip/patches-6.6/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch index cbffd443f..a61b532b7 100644 --- a/target/linux/rockchip/patches-6.6/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch +++ b/target/linux/rockchip/patches-6.6/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch @@ -79,12 +79,13 @@ Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224 depends on ARM64 || COMPILE_TEST --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile -@@ -27,5 +27,6 @@ obj-$(CONFIG_CLK_RK3308) += clk-r +@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-r obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o +obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o + obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -140,7 +141,7 @@ Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224 #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) #define RK3568_MODE_CON0 0xc0 #define RK3568_MISC_CON0 0xc4 -@@ -408,6 +436,7 @@ struct rockchip_pll_clock { +@@ -461,6 +489,7 @@ struct rockchip_pll_clock { }; #define ROCKCHIP_PLL_SYNC_RATE BIT(0) @@ -148,7 +149,7 @@ Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ _lshift, _pflags, _rtable) \ -@@ -516,6 +545,7 @@ enum rockchip_clk_branch_type { +@@ -569,6 +598,7 @@ enum rockchip_clk_branch_type { branch_muxgrf, branch_divider, branch_fraction_divider, @@ -156,7 +157,7 @@ Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224 branch_gate, branch_mmc, branch_inverter, -@@ -836,6 +866,19 @@ struct rockchip_clk_branch { +@@ -889,6 +919,19 @@ struct rockchip_clk_branch { .name = cname, \ .parent_names = (const char *[]){ pname }, \ .num_parents = 1, \ diff --git a/target/linux/rockchip/patches-6.6/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch b/target/linux/rockchip/patches-6.6/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch index 5547584d3..b75531d43 100644 --- a/target/linux/rockchip/patches-6.6/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch +++ b/target/linux/rockchip/patches-6.6/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch @@ -217,11 +217,11 @@ Change-Id: I8a69a1239ed3ae91bfe44c96287210da758f9cf9 #define RK3568_GRF_GMAC0_CON0 0x0380 #define RK3568_GRF_GMAC0_CON1 0x0384 #define RK3568_GRF_GMAC1_CON0 0x0388 -@@ -2106,6 +2301,7 @@ static const struct of_device_id rk_gmac +@@ -2261,6 +2456,7 @@ static const struct of_device_id rk_gmac { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, + { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, + { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, - { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, diff --git a/target/linux/rockchip/patches-6.6/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch b/target/linux/rockchip/patches-6.6/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch index 2e6ab180d..31eb31f92 100644 --- a/target/linux/rockchip/patches-6.6/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch +++ b/target/linux/rockchip/patches-6.6/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch @@ -1,6 +1,6 @@ --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1761,6 +1761,53 @@ static const struct rockchip_usb2phy_cfg +@@ -1813,6 +1813,53 @@ static const struct rockchip_usb2phy_cfg { /* sentinel */ } }; @@ -54,11 +54,11 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { { .reg = 0xfe8a0000, -@@ -1997,6 +2044,7 @@ static const struct of_device_id rockchi +@@ -2127,6 +2174,7 @@ static const struct of_device_id rockchi { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, + { .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs }, { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, + { .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs }, { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs }, - { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, diff --git a/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch b/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch index ca277999f..8aca368f3 100644 --- a/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch +++ b/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch @@ -19,7 +19,7 @@ Signed-off-by: Jianwei Zheng --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -@@ -83,7 +83,7 @@ +@@ -97,7 +97,7 @@ struct rockchip_combphy_priv; struct combphy_reg { @@ -28,7 +28,7 @@ Signed-off-by: Jianwei Zheng u16 bitend; u16 bitstart; u16 disable; -@@ -93,11 +93,13 @@ struct combphy_reg { +@@ -107,6 +107,7 @@ struct combphy_reg { struct rockchip_combphy_grfcfg { struct combphy_reg pcie_mode_set; struct combphy_reg usb_mode_set; @@ -36,13 +36,7 @@ Signed-off-by: Jianwei Zheng struct combphy_reg sgmii_mode_set; struct combphy_reg qsgmii_mode_set; struct combphy_reg pipe_rxterm_set; - struct combphy_reg pipe_txelec_set; - struct combphy_reg pipe_txcomp_set; -+ struct combphy_reg pipe_clk_24m; - struct combphy_reg pipe_clk_25m; - struct combphy_reg pipe_clk_100m; - struct combphy_reg pipe_phymode_sel; -@@ -378,6 +380,120 @@ static int rockchip_combphy_probe(struct +@@ -393,6 +394,120 @@ static int rockchip_combphy_probe(struct return PTR_ERR_OR_ZERO(phy_provider); } @@ -163,7 +157,7 @@ Signed-off-by: Jianwei Zheng static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; -@@ -772,6 +888,10 @@ static const struct rockchip_combphy_cfg +@@ -1047,6 +1162,10 @@ static const struct rockchip_combphy_cfg static const struct of_device_id rockchip_combphy_of_match[] = { { diff --git a/target/linux/rockchip/patches-6.6/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch b/target/linux/rockchip/patches-6.6/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch index ce7733722..428822e45 100644 --- a/target/linux/rockchip/patches-6.6/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch +++ b/target/linux/rockchip/patches-6.6/310-mmc-dw_mmc-rockchip-add-v2-tuning-support.patch @@ -17,16 +17,16 @@ Signed-off-by: Shawn Lin --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c -@@ -24,6 +24,8 @@ struct dw_mci_rockchip_priv_data { - struct clk *sample_clk; +@@ -35,6 +35,8 @@ struct dw_mci_rockchip_priv_data { int default_sample_phase; int num_phases; + bool internal_phase; + int last_degree; + bool use_v2_tuning; }; - static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) -@@ -134,6 +136,58 @@ static void dw_mci_rk3288_set_ios(struct + /* +@@ -279,6 +281,58 @@ static void dw_mci_rk3288_set_ios(struct #define TUNING_ITERATION_TO_PHASE(i, num_phases) \ (DIV_ROUND_UP((i) * 360, num_phases)) @@ -85,7 +85,7 @@ Signed-off-by: Shawn Lin static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) { struct dw_mci *host = slot->host; -@@ -157,6 +211,12 @@ static int dw_mci_rk3288_execute_tuning( +@@ -303,6 +357,12 @@ static int dw_mci_rk3288_execute_tuning( return -EIO; } @@ -98,9 +98,17 @@ Signed-off-by: Shawn Lin ranges = kmalloc_array(priv->num_phases / 2 + 1, sizeof(*ranges), GFP_KERNEL); if (!ranges) -@@ -277,6 +337,9 @@ static int dw_mci_rk3288_parse_dt(struct - &priv->default_sample_phase)) - priv->default_sample_phase = 0; +@@ -431,6 +491,7 @@ static int dw_mci_common_parse_dt(struct + + static int dw_mci_rk3288_parse_dt(struct dw_mci *host) + { ++ struct device_node *np = host->dev->of_node; + struct dw_mci_rockchip_priv_data *priv; + int err; + +@@ -440,6 +501,9 @@ static int dw_mci_rk3288_parse_dt(struct + + priv = host->priv; + if (of_property_read_bool(np, "rockchip,use-v2-tuning")) + priv->use_v2_tuning = true; diff --git a/target/linux/rockchip/patches-6.6/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch b/target/linux/rockchip/patches-6.6/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch index 7f2d7175a..b4c061019 100644 --- a/target/linux/rockchip/patches-6.6/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch +++ b/target/linux/rockchip/patches-6.6/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch @@ -179,7 +179,7 @@ Signed-off-by: hmz007 GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h -@@ -515,7 +515,8 @@ struct clk *rockchip_clk_register_mmc(co +@@ -568,7 +568,8 @@ struct clk *rockchip_clk_register_mmc(co * DDRCLK flags, including method of setting the rate * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. */ diff --git a/target/linux/rockchip/patches-6.6/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch b/target/linux/rockchip/patches-6.6/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch index ca567660d..ec615a835 100644 --- a/target/linux/rockchip/patches-6.6/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch +++ b/target/linux/rockchip/patches-6.6/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch @@ -9,7 +9,7 @@ Signed-off-by: hmz007 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -1034,6 +1034,13 @@ +@@ -1033,6 +1033,13 @@ status = "disabled"; };