From aa7601b13fd610495a8a6f5f3f89603220aab03a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=99=93=E4=B8=9C?= <1052672227@qq.com> Date: Wed, 23 Aug 2023 15:16:23 +0800 Subject: [PATCH] meson: add 5.15 kernel support (#11477) --- target/linux/meson/Makefile | 1 + .../arch/arm/boot/dts/meson8b-onecloud.dts | 355 ++++++++----- target/linux/meson/image/Makefile | 11 +- target/linux/meson/image/boot.txt | 12 + target/linux/meson/meson8b/config-5.10 | 3 + target/linux/meson/meson8b/config-5.15 | 482 ++++++++++++++++++ .../902-use-system-LED-for-OpenWrt.patch | 14 + .../patches-5.15/903-Support-for-EMMC.patch | 58 +++ 8 files changed, 808 insertions(+), 128 deletions(-) create mode 100644 target/linux/meson/image/boot.txt create mode 100644 target/linux/meson/meson8b/config-5.15 create mode 100644 target/linux/meson/patches-5.15/902-use-system-LED-for-OpenWrt.patch create mode 100644 target/linux/meson/patches-5.15/903-Support-for-EMMC.patch diff --git a/target/linux/meson/Makefile b/target/linux/meson/Makefile index a8bf6842f..3d7180431 100644 --- a/target/linux/meson/Makefile +++ b/target/linux/meson/Makefile @@ -12,6 +12,7 @@ MAINTAINER:=Stijn Tintel SUBTARGETS:=meson8b mesongx KERNEL_PATCHVER:=5.10 +KERNEL_TESTING_PATCHVER:=5.15 define Target/Description Build firmware image for Amlogic Meson SoC devices. diff --git a/target/linux/meson/files/arch/arm/boot/dts/meson8b-onecloud.dts b/target/linux/meson/files/arch/arm/boot/dts/meson8b-onecloud.dts index 45cde3543..ec6066aba 100644 --- a/target/linux/meson/files/arch/arm/boot/dts/meson8b-onecloud.dts +++ b/target/linux/meson/files/arch/arm/boot/dts/meson8b-onecloud.dts @@ -30,12 +30,21 @@ }; gpio-keys { + // compatible = "gpio-keys-polled"; + // poll-interval = <100>; + compatible = "gpio-keys"; - reset { + autorepeat; + + reset-button { label = "reset"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_LOW>; + linux,code = ; + + // gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; // GPIOAO 5 }; }; @@ -58,143 +67,99 @@ }; }; - p12v0: regulator-p12v0 { + p12v: regulator-p12v { compatible = "regulator-fixed"; - regulator-name = "P12V0"; + regulator-name = "P12V"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; - vcc_1v8: regulator-vcc-1v8 { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; - vin-supply = <&p12v0>; + vin-supply = <&p12v>; + + regulator-boot-on; + regulator-always-on; }; vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; - regulator-always-on; regulator-name = "VCC3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&p12v0>; - }; + vin-supply = <&p12v>; - vcc_5v0: regulator-vcc5v0 { - compatible = "regulator-fixed"; - - regulator-always-on; - regulator-name = "VCC5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&p12v0>; - }; - - vcck: regulator-vcck { - compatible = "pwm-regulator"; - - regulator-always-on; regulator-boot-on; - regulator-name = "VCCK"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - pwm-supply = <&p12v0>; - - pwms = <&pwm_cd 1 12001 0>; - pwm-dutycycle-range = <10 0>; + regulator-always-on; }; - vddc_ddr: regulator-vddc-ddr { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&p12v>; + + regulator-boot-on; regulator-always-on; - regulator-name = "DDR_VDDC"; + }; + + vcc_ddr: regulator-vcc-ddr { + compatible = "regulator-fixed"; + + regulator-name = "VCC_DDR"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; - vin-supply = <&p12v0>; + vin-supply = <&vcc_3v3>; + + regulator-boot-on; + regulator-always-on; }; + + vcc_core: regulator-vcc-core { + compatible = "pwm-regulator"; + + regulator-name = "VCC_CORE"; + + pwms = <&pwm_cd 1 12001 0>; // PWM_D + pwm-dutycycle-range = <10 0>; + regulator-min-microvolt = <860000>; + regulator-max-microvolt = <1140000>; + + pwm-supply = <&p12v>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&pwm_cd { + status = "okay"; + pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; + pinctrl-names = "default"; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; }; &cpu0 { - cpu-supply = <&vcck>; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy>; - phy-mode = "rgmii-id"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy: ethernet-phy@0 { - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&gpio { - gpio-line-names = - /* Bank GPIODV */ - "VCCK_PWM (PWM_C)", "I2CA_SDA", "I2CA_SCL", - "I2CB_SDA", "I2CB_SCL", "VDDEE_PWM (PWM_D)", - "", - /* Bank GPIOH */ - "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", - "ETH_PHY_INTR", "ETH_PHY_NRST", "ETH_TXD1", - "ETH_TXD0", "ETH_TXD3", "ETH_TXD2", - "ETH_RGMII_TX_CLK", - /* Bank CARD */ - "SD_D1", "SD_D0", "SD_CLK", "SD_CMD", - "SD_D3", "SD_D2", "SD_CD", - /* Bank BOOT */ - "EMMC_D0", "EMMC_D1", "EMMC_D2", "EMMC_D3", - "EMMC_D4", "EMMC_D5", "EMMC_D6", "EMMC_D7", - "EMMC_CLK", "EMMC_RSTn", "EMMC_CMD", - "BOOT_SEL", "", "", "", "", "", "", "", - /* Bank DIF */ - "ETH_RXD1", "ETH_RXD0", "ETH_RX_DV", - "RGMII_RX_CLK", "ETH_RXD3", "ETH_RXD2", - "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT", - "ETH_MDC", "ETH_MDIO"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", "UART RX", - "RED_LED", "GREEN_LED", - "BLUE_LED", "BUTTON", "", - "IR_IN", "", "", "", - "", "", "", "", ""; -}; - -&ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; - pinctrl-names = "default"; + cpu-supply = <&vcc_core>; }; &saradc { @@ -202,23 +167,137 @@ vref-supply = <&vcc_1v8>; }; + +&gpio { + gpio-line-names = + /* 0 */ "WIFI_SDIO_D0 PIN18 (GPIOX_0)", + /* 1 */ "WIFI_SDIO_D1 PIN19 (GPIOX_1)", + /* 2 */ "WIFI_SDIO_D2 PIN14 (GPIOX_2)", + /* 3 */ "WIFI_SDIO_D3 PIN15 (GPIOX_3)", + /* 4 */ "WIFI_PCM_DIN PIN27 (GPIOX_4)", + /* 5 */ "WIFI_PCM_DOUT PIN25 (GPIOX_5)", + /* 6 */ "WIFI_PCM_SYNC PIN28 (GPIOX_6)", + /* 7 */ "WIFI_PCM_CLK PIN26 (GPIOX_7)", + /* 8 */ "WIFI_SDIO_CLK PIN17_Resistor (GPIOX_8)", + /* 9 */ "WIFI_SDIO_CMD PIN16 (GPIOX_9)", + /* 10 */ "GPIOX_10", + /* 11 */ "WIFI PIN12 (GPIOX_11)", + /* 12 */ "WIFI_UART_RX PIN43 (GPIOX_16)", + /* 13 */ "WIFI_UART_TX PIN42 (GPIOX_17)", + /* 14 */ "WIFI_UART_RTS PIN41_Resistor (GPIOX_18)", + /* 15 */ "WIFI_UART_CTS PIN44 (GPIOX_19)", + /* 16 */ "WIFI PIN34 (GPIOX_20)", + /* 17 */ "WIFI_WAKE PIN13 (GPIOX_21)", + + /* 18 */ "Resistor_TopOf_LED (GPIOY_0)", + /* 19 */ "GPIOY_1", + /* 20 */ "GPIOY_3", + /* 21 */ "GPIOY_6", + /* 22 */ "GPIOY_7", + /* 23 */ "GPIOY_8", + /* 24 */ "GPIOY_9", + /* 25 */ "GPIOY_10", + /* 26 */ "GPIOY_11", + /* 27 */ "GPIOY_12", + /* 28 */ "Left_BottomOf_CPU (GPIOY_13)", + /* 29 */ "Right_BottomOf_CPU (GPIOY_14)", + + /* 30 */ "GPIODV_9 (PWM_C)", + /* 31 */ "GPIODV_24", + /* 32 */ "GPIODV_25", + /* 33 */ "GPIODV_26", + /* 34 */ "GPIODV_27", + /* 35 */ "VCC_CPU_PWM (GPIODV_28)", + /* 36 */ "GPIODV_29", + + /* 37 */ "HDMI_HPD (GPIOH_0)", + /* 38 */ "HDMI_SDA (GPIOH_1)", + /* 39 */ "HDMI_SCL (GPIOH_2)", + /* 40 */ "ETH_PHY_INTR (GPIOH_3)", + /* 41 */ "ETH_PHY_nRST (GPIOH_4)", + /* 42 */ "ETH_TXD1 (GPIOH_5)", + /* 43 */ "ETH_TXD0 (GPIOH_6)", + /* 44 */ "ETH_TXD3 (GPIOH_7)", + /* 45 */ "ETH_TXD2 (GPIOH_8)", + /* 46 */ "ETH_TX_CLK (GPIOH_9)", + + /* 47 */ "SDCARD_D1 (CARD_0)", + /* 48 */ "SDCARD_D0 (CARD_1)", + /* 49 */ "SDCARD_CLK (CARD_2)", + /* 50 */ "SDCARD_CMD (CARD_3)", + /* 51 */ "SDCARD_D3 (CARD_4)", + /* 52 */ "SDCARD_D2 (CARD_5)", + /* 53 */ "SDCARD_CD (CARD_6)", + + /* 54 */ "EMMC_D0 (BOOT_0)", + /* 55 */ "EMMC_D1 (BOOT_1)", + /* 56 */ "EMMC_D2 (BOOT_2)", + /* 57 */ "EMMC_D3 (BOOT_3)", + /* 58 */ "EMMC_D4 (BOOT_4)", + /* 59 */ "EMMC_D5 (BOOT_5)", + /* 60 */ "EMMC_D6 (BOOT_6)", + /* 61 */ "EMMC_D7 (BOOT_7)", + /* 62 */ "EMMC_CLK (BOOT_8)", + /* 63 */ "EMMC_nRST (BOOT_9)", + /* 64 */ "EMMC_CMD (BOOT_10)", + /* 65 */ "BOOT_11", + /* 66 */ "BOOT_12", + /* 67 */ "BOOT_13", + /* 68 */ "BOOT_14", + /* 69 */ "BOOT_15", + /* 70 */ "BOOT_16", + /* 71 */ "BOOT_17", + /* 72 */ "BOOT_18", + + /* 73 */ "ETH_RXD1 (DIF_0_P)", + /* 74 */ "ETH_RXD0 (DIF_0_N)", + /* 75 */ "ETH_RX_DV (DIF_1_P)", + /* 76 */ "ETH_RX_CLK (DIF_1_N)", + /* 77 */ "ETH_RXD3 (DIF_2_P)", + /* 78 */ "ETH_RXD2 (DIF_2_N)", + /* 79 */ "ETH_TX_EN (DIF_3_P)", + /* 80 */ "ETH_REF_CLK (DIF_3_N)", + /* 81 */ "ETH_MDC (DIF_4_P)", + /* 82 */ "ETH_MDIO_EN (DIF_4_N)"; +}; + +&gpio_ao { + gpio-line-names = + /* 0 */ "UART TX (GPIOAO_0)", + /* 1 */ "UART RX (GPIOAO_1)", + /* 2 */ "RED_LED (GPIOAO_2)", + /* 3 */ "GREEN_LED (GPIOAO_3)", + /* 4 */ "BLUE_LED (GPIOAO_4)", + /* 5 */ "BUTTON (GPIOAO_5)", + /* 6 */ "GPIOAO_6", + /* 7 */ "IR_IN (GPIOAO_7)", + /* 8 */ "GPIOAO_8", + /* 9 */ "GPIOAO_9", + /* 10 */ "GPIOAO_10", + /* 11 */ "GPIOAO_11", + /* 12 */ "GPIOAO_12", + /* 13 */ "GPIOAO_13", + + /* 14 */ "GPIO_BSD_EN", + /* 15 */ "GPIO_TEST_N"; +}; + +// eMMC &sdhc { status = "okay"; pinctrl-0 = <&sdxc_c_pins>; pinctrl-names = "default"; + non-removable; bus-width = <8>; - max-frequency = <100000000>; - - disable-wp; + max-frequency = <200000000>; cap-mmc-highspeed; mmc-hs200-1_8v; - no-sdio; mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; + // vqmmc-supply = <&vcc_3v3>; }; &sdio { @@ -227,7 +306,7 @@ pinctrl-0 = <&sd_b_pins>; pinctrl-names = "default"; - /* SD card */ + // SD card sd_card_slot: slot@1 { compatible = "mmc-slot"; reg = <1>; @@ -242,35 +321,59 @@ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; vmmc-supply = <&vcc_3v3>; + // vqmmc-supply = <&vcc_3v3>; }; }; -&pwm_cd { +ðmac { status = "okay"; - pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; + + pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; + + phy-handle = <ð_phy>; + phy-mode = "rgmii-rxid"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + // Realtek RTL8211F (0x001cc916) + eth_phy: ethernet-phy@0 { + reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; // GPIOH 3 + }; + }; }; -&uart_AO { +&usb0 { status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; }; &usb0_phy { status = "okay"; }; +&usb1 { + status = "okay"; +}; + &usb1_phy { status = "okay"; }; -&usb0 { - status = "okay"; -}; - -&usb1 { +&ir_receiver { status = "okay"; + pinctrl-0 = <&ir_recv_pins>; + pinctrl-names = "default"; }; diff --git a/target/linux/meson/image/Makefile b/target/linux/meson/image/Makefile index 0b5883afa..dfdb8c317 100644 --- a/target/linux/meson/image/Makefile +++ b/target/linux/meson/image/Makefile @@ -16,6 +16,8 @@ define Build/sdcard-img mcopy -i $@.boot $(KDIR)/uInitrd :: mcopy -i $@.boot $(KDIR)/s805_autoscript :: mcopy -i $@.boot $(KDIR)/s805_autoscript.txt :: + mcopy -i $@.boot $(KDIR)/boot.scr :: + mcopy -i $@.boot $(KDIR)/boot.txt :: #For S905 mcopy -i $@.boot $(KDIR)/uEnv.ini :: mcopy -i $@.boot $(KDIR)/s905_autoscript :: @@ -35,10 +37,13 @@ define Build/sdcard-img endef define Build/uImage-meson -#For S805 autoscript +#For S805 autoscript && boot.scr $(RM) -rf $(KDIR)/uInitrd $(RM) -rf $(KDIR)/s805_autoscript $(RM) -rf $(KDIR)/s805_autoscript.txt + $(RM) -rf $(KDIR)/boot.scr + $(RM) -rf $(KDIR)/boot.txt + #For S905 autoscript $(RM) -rf $(KDIR)/s905_autoscript @@ -47,10 +52,12 @@ define Build/uImage-meson $(call Build/uImage,none) -#For S805 autoscript +#For S805 autoscript && boot.scr touch $(KDIR)/uInitrd $(CP) s805_autoscript.txt $(KDIR)/s805_autoscript.txt mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "s805_autoscript" -d s805_autoscript.txt $(KDIR)/s805_autoscript + $(CP) boot.txt $(KDIR)/boot.txt + mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "boot.scr" -d boot.txt $(KDIR)/boot.scr #For S905 autoscript $(CP) uEnv.ini $(KDIR)/uEnv.ini diff --git a/target/linux/meson/image/boot.txt b/target/linux/meson/image/boot.txt new file mode 100644 index 000000000..f044982c1 --- /dev/null +++ b/target/linux/meson/image/boot.txt @@ -0,0 +1,12 @@ + +setenv condev "console=ttyAML0,115200n8 no_console_suspend consoleblank=0" +setenv bootargs_emmc "root=/dev/mmcblk1p2 rootwait ro ${condev} fsck.repair=yes net.ifnames=0 mac=${mac}" +setenv kernel_loadaddr "0x00208000" +setenv dtb_loadaddr "0x21800000" +setenv initrd_loadaddr "0x22000000" +setenv dtb_name "dtb" +#setenv boot_start bootm ${kernel_loadaddr} ${initrd_loadaddr} ${dtb_loadaddr} +setenv boot_start bootm ${kernel_loadaddr} - ${dtb_loadaddr} + +if fatload mmc 1 ${initrd_loadaddr} uInitrd; setenv bootargs ${bootargs_emmc}; then if fatload mmc 1 ${kernel_loadaddr} uImage; then if fatload mmc 1 ${dtb_loadaddr} ${dtb_name}; then run boot_start; else imgread dtb boot ${loadaddr} ${dtb_loadaddr}; run boot_start;fi;fi;fi; + diff --git a/target/linux/meson/meson8b/config-5.10 b/target/linux/meson/meson8b/config-5.10 index 612450f82..3c467b3e1 100644 --- a/target/linux/meson/meson8b/config-5.10 +++ b/target/linux/meson/meson8b/config-5.10 @@ -17,6 +17,7 @@ CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM=y CONFIG_ARM_GIC=y +CONFIG_ARM_CRYPTO=y CONFIG_ARM_GLOBAL_TIMER=y CONFIG_ARM_HAS_SG_CHAIN=y CONFIG_ARM_HEAVY_MB=y @@ -477,3 +478,5 @@ CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_XPS=y CONFIG_ZBOOT_ROM_BSS=0 CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y diff --git a/target/linux/meson/meson8b/config-5.15 b/target/linux/meson/meson8b/config-5.15 new file mode 100644 index 000000000..3c467b3e1 --- /dev/null +++ b/target/linux/meson/meson8b/config-5.15 @@ -0,0 +1,482 @@ +# CONFIG_AIO is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_AMLOGIC_THERMAL=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MESON=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_CRYPTO=y +CONFIG_ARM_GLOBAL_TIMER=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ASN1=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_PM=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_CACHE_L2X0=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_QORIQ=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_MESON8B=y +CONFIG_COMMON_CLK_MESON_MPLL=y +CONFIG_COMMON_CLK_MESON_PLL=y +CONFIG_COMMON_CLK_MESON_REGMAP=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_THERMAL=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRC7=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA256=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DMA_CMA=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DRM=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_MALI_DISPLAY=y +# CONFIG_DRM_MESON is not set +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DWMAC_DWC_QOS_ETH=y +# CONFIG_DWMAC_GENERIC is not set +CONFIG_DWMAC_MESON=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_ELF_CORE=y +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXTCON=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FTRACE=y +# CONFIG_FTRACE_SYSCALLS is not set +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ADC_THERMAL=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_HAVE_SMP=y +CONFIG_HDMI=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MESON=y +CONFIG_HZ=100 +CONFIG_HZ_100=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_MESON=y +CONFIG_ICPLUS_PHY=y +CONFIG_IIO=y +CONFIG_INPUT=y +CONFIG_IPV6=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_PIMSM_V2 is not set +CONFIG_IPV6_SUBTREES=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IR_IMON_RAW is not set +# CONFIG_IR_MESON is not set +# CONFIG_IR_SERIAL is not set +# CONFIG_IR_SIR is not set +# CONFIG_IR_TOY is not set +CONFIG_JBD2=y +CONFIG_KCMP=y +CONFIG_KEYS=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LIB_MEMNEQ=y +# CONFIG_LIRC is not set +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +# CONFIG_MACH_MESON6 is not set +CONFIG_MACH_MESON8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +# CONFIG_MDIO_BUS_MUX_MESON_G12A is not set +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_GPIO is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MESON6_TIMER=y +# CONFIG_MESON_CANVAS is not set +CONFIG_MESON_CLK_MEASURE=y +CONFIG_MESON_EE_PM_DOMAINS=y +# CONFIG_MESON_GXBB_WATCHDOG is not set +# CONFIG_MESON_GXL_PHY is not set +CONFIG_MESON_GX_PM_DOMAINS=y +# CONFIG_MESON_GX_SOCINFO is not set +CONFIG_MESON_IRQ_GPIO=y +CONFIG_MESON_MX_EFUSE=y +CONFIG_MESON_MX_SOCINFO=y +CONFIG_MESON_SARADC=y +CONFIG_MESON_WATCHDOG=y +# CONFIG_MFD_KHADAS_MCU is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_CQHCI=y +CONFIG_MMC_DW=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +CONFIG_MMC_DW_K3=y +CONFIG_MMC_DW_PLTFM=y +# CONFIG_MMC_MESON_GX is not set +CONFIG_MMC_MESON_MX_SDHC=y +CONFIG_MMC_MESON_MX_SDIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SPI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MPILIB=y +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_EMATCH=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OID_REGISTRY=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PCS_XPCS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHY_MESON8B_USB2=y +# CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set +# CONFIG_PHY_MESON_AXG_PCIE is not set +# CONFIG_PHY_MESON_G12A_USB2 is not set +# CONFIG_PHY_MESON_G12A_USB3_PCIE is not set +# CONFIG_PHY_MESON_GXL_USB2 is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON=y +CONFIG_PINCTRL_MESON8=y +CONFIG_PINCTRL_MESON8B=y +CONFIG_PINCTRL_MESON8_PMX=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PLATFORM_MHU=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POWER_RESET=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPS=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PWM=y +CONFIG_PWM_MESON=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RC_CORE=y +CONFIG_RC_DEVICES=y +# CONFIG_RC_XBOX_DVD is not set +CONFIG_REALTEK_AUTOPM=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_MESON=y +# CONFIG_RESET_MESON_AUDIO_ARB is not set +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MESON=y +# CONFIG_RTC_DRV_MESON_VRTC is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_THERMAL_PRESSURE=y +CONFIG_SCSI=y +CONFIG_SDIO_UART=y +CONFIG_SENSORS_IIO_HWMON=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_MESON=y +CONFIG_SERIAL_MESON_CONSOLE=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOC_BUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MESON_SPICC=y +CONFIG_SPI_MESON_SPIFC=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYNC_FILE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_DUAL_ROLE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_DUAL_ROLE=y +# CONFIG_USB_DWC3_GADGET is not set +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_MESON_G12A is not set +CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_ETH is not set +CONFIG_USB_GADGET=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_PHY=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USE_OF=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_XPS=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y diff --git a/target/linux/meson/patches-5.15/902-use-system-LED-for-OpenWrt.patch b/target/linux/meson/patches-5.15/902-use-system-LED-for-OpenWrt.patch new file mode 100644 index 000000000..a387fde89 --- /dev/null +++ b/target/linux/meson/patches-5.15/902-use-system-LED-for-OpenWrt.patch @@ -0,0 +1,14 @@ +--- a/arch/arm/boot/dts/meson8b-onecloud.dts ++++ b/arch/arm/boot/dts/meson8b-onecloud.dts +@@ -13,6 +13,11 @@ + serial0 = &uart_AO; + mmc0 = &sd_card_slot; + mmc1 = &sdhc; ++ ++ led-boot = &led_status_red; ++ led-failsafe = &led_status_red; ++ led-running = &led_status_blue; ++ led-upgrade = &led_status_green; + }; + + chosen { diff --git a/target/linux/meson/patches-5.15/903-Support-for-EMMC.patch b/target/linux/meson/patches-5.15/903-Support-for-EMMC.patch new file mode 100644 index 000000000..da689353b --- /dev/null +++ b/target/linux/meson/patches-5.15/903-Support-for-EMMC.patch @@ -0,0 +1,58 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -365,6 +365,7 @@ dtb-$(CONFIG_MACH_MESON8) += \ + meson8b-ec100.dtb \ + meson8b-mxq.dtb \ + meson8b-odroidc1.dtb \ ++ meson8b-onecloud.dtb \ + meson8m2-mxiii-plus.dtb + dtb-$(CONFIG_ARCH_MMP) += \ + pxa168-aspenite.dtb \ +--- a/drivers/mmc/core/mmc.c ++++ b/drivers/mmc/core/mmc.c +@@ -1386,12 +1386,13 @@ static int mmc_select_hs400es(struct mmc + * SEND_STATUS reliably at the initial frequency. + */ + mmc_set_timing(host, MMC_TIMING_MMC_HS); +- mmc_set_bus_speed(card); + + err = mmc_switch_status(card, true); + if (err) + goto out_err; + ++ mmc_set_clock(host, card->ext_csd.hs_max_dtr); ++ + /* Switch card to DDR with strobe bit */ + val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE; + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, +@@ -1449,7 +1450,7 @@ out_err: + static int mmc_select_hs200(struct mmc_card *card) + { + struct mmc_host *host = card->host; +- unsigned int old_timing, old_signal_voltage, old_clock; ++ unsigned int old_timing, old_signal_voltage; + int err = -EINVAL; + u8 val; + +@@ -1488,9 +1489,7 @@ static int mmc_select_hs200(struct mmc_c + * successfully switched over. + */ + old_timing = host->ios.timing; +- old_clock = host->ios.clock; + mmc_set_timing(host, MMC_TIMING_MMC_HS200); +- mmc_set_clock(card->host, card->ext_csd.hs_max_dtr); + + /* + * For HS200, CRC errors are not a reliable way to know the +@@ -1503,10 +1502,8 @@ static int mmc_select_hs200(struct mmc_c + * mmc_select_timing() assumes timing has not changed if + * it is a switch error. + */ +- if (err == -EBADMSG) { +- mmc_set_clock(host, old_clock); ++ if (err == -EBADMSG) + mmc_set_timing(host, old_timing); +- } + } + err: + if (err) {