From f3225f6770eea621b4b6f0b647bdec20206bac4c Mon Sep 17 00:00:00 2001 From: goldkeyber112 <45441606+goldkeyber112@users.noreply.github.com> Date: Wed, 24 Jun 2020 05:25:15 +0800 Subject: [PATCH] bump to 9.003.05 add RTL8125B(S) support --- package/lean/r8125/Makefile | 2 +- package/lean/r8125/src/Makefile | 6 +- package/lean/r8125/src/r8125.h | 74 +- package/lean/r8125/src/r8125_dash.h | 14 +- package/lean/r8125/src/r8125_n.c | 3996 +++++++++++++++++------- package/lean/r8125/src/r8125_realwow.h | 2 +- package/lean/r8125/src/rtl_eeprom.c | 117 +- package/lean/r8125/src/rtl_eeprom.h | 19 +- package/lean/r8125/src/rtltool.c | 14 +- package/lean/r8125/src/rtltool.h | 2 +- 10 files changed, 3061 insertions(+), 1185 deletions(-) diff --git a/package/lean/r8125/Makefile b/package/lean/r8125/Makefile index 053147a28..cc7b50238 100755 --- a/package/lean/r8125/Makefile +++ b/package/lean/r8125/Makefile @@ -65,7 +65,7 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=r8125 -PKG_VERSION:=9.002.02 +PKG_VERSION:=9.003.05 PKG_RELEASE:=1 #PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 diff --git a/package/lean/r8125/src/Makefile b/package/lean/r8125/src/Makefile index 3724d0089..02d58004a 100644 --- a/package/lean/r8125/src/Makefile +++ b/package/lean/r8125/src/Makefile @@ -37,8 +37,9 @@ CONFIG_DOWN_SPEED_100 = n CONFIG_ASPM = y ENABLE_S5WOL = y ENABLE_S5_KEEP_CURR_MAC = n -ENABLE_EEE = n +ENABLE_EEE = y ENABLE_S0_MAGIC_PACKET = n +ENABLE_TX_NO_CLOSE = y ifneq ($(KERNELRELEASE),) obj-m := r8125.o @@ -78,6 +79,9 @@ ifneq ($(KERNELRELEASE),) ifeq ($(ENABLE_S0_MAGIC_PACKET), y) EXTRA_CFLAGS += -DENABLE_S0_MAGIC_PACKET endif + ifeq ($(ENABLE_TX_NO_CLOSE), y) + EXTRA_CFLAGS += -DENABLE_TX_NO_CLOSE + endif else BASEDIR := /lib/modules/$(shell uname -r) KERNELDIR ?= $(BASEDIR)/build diff --git a/package/lean/r8125/src/r8125.h b/package/lean/r8125/src/r8125.h index fcddf1846..23a45a100 100644 --- a/package/lean/r8125/src/r8125.h +++ b/package/lean/r8125/src/r8125.h @@ -4,7 +4,7 @@ # r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -249,6 +249,14 @@ do { \ #define SUPPORTED_Asym_Pause (1 << 14) #endif +#ifndef MDIO_EEE_100TX +#define MDIO_EEE_100TX 0x0002 +#endif + +#ifndef MDIO_EEE_1000T +#define MDIO_EEE_1000T 0x0004 +#endif + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) #ifdef CONFIG_NET_POLL_CONTROLLER #define RTL_NET_POLL_CONTROLLER dev->poll_controller=rtl8125_netpoll @@ -315,12 +323,12 @@ do { \ #define DASH_SUFFIX "" #endif -#define RTL8125_VERSION "9.002.02" NAPI_SUFFIX DASH_SUFFIX +#define RTL8125_VERSION "9.003.05" NAPI_SUFFIX DASH_SUFFIX #define MODULENAME "r8125" #define PFX MODULENAME ": " #define GPL_CLAIM "\ -r8125 Copyright (C) 2019 Realtek NIC software team \n \ +r8125 Copyright (C) 2020 Realtek NIC software team \n \ This program comes with ABSOLUTELY NO WARRANTY; for details, please see . \n \ This is free software, and you are welcome to redistribute it under certain conditions; see . \n" @@ -339,9 +347,6 @@ This is free software, and you are welcome to redistribute it under certain cond #define R8125_MSG_DEFAULT \ (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) -#define TX_BUFFS_AVAIL(tp) \ - (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) - #ifdef CONFIG_R8125_NAPI #define rtl8125_rx_hwaccel_skb vlan_hwaccel_receive_skb #define rtl8125_rx_quota(count, quota) min(count, quota) @@ -417,13 +422,15 @@ This is free software, and you are welcome to redistribute it under certain cond #define SHORT_PACKET_PADDING_BUF_SIZE 256 +#define RTK_MAGIC_DEBUG_VALUE 0x0badbeef + /* write/read MMIO register */ -#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) -#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) -#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) -#define RTL_R8(reg) readb (ioaddr + (reg)) -#define RTL_R16(reg) readw (ioaddr + (reg)) -#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) +#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) +#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) +#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) +#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) +#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) +#define RTL_R32(tp, reg) ((unsigned long) readl(tp->mmio_addr + (reg))) #ifndef DMA_64BIT_MASK #define DMA_64BIT_MASK 0xffffffffffffffffULL @@ -479,6 +486,10 @@ This is free software, and you are welcome to redistribute it under certain cond #define RTK_ADVERTISE_2500FULL 0x80 +/* Tx NO CLOSE */ +#define MAX_TX_NO_CLOSE_DESC_PTR_V2 0x10000 +#define TX_NO_CLOSE_SW_PTR_MASK_V2 0x1FFFF + /*****************************************************************************/ //#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) @@ -1099,6 +1110,9 @@ enum RTL8125_registers { TIMER_INT1_8125 = 0x005C, TIMER_INT2_8125 = 0x008C, TIMER_INT3_8125 = 0x00F4, + EEE_TXIDLE_TIMER_8125 = 0x6048, + SW_TAIL_PTR0_8125 = 0x2800, + HW_CLO_PTR0_8125 = 0x2802, }; enum RTL8125_register_content { @@ -1562,6 +1576,7 @@ struct rtl8125_private { u8 ShortPacketSwChecksum; u8 UseSwPaddingShortPkt; + u16 SwPaddingShortPktLen; void *ShortPacketEmptyBuffer; dma_addr_t ShortPacketEmptyBufferPhy; @@ -1576,6 +1591,10 @@ struct rtl8125_private { u8 RequiredSecLanDonglePatch; + u8 RequirePhyMdiSwapPatch; + + u8 RequireLSOPatch; + u32 HwFiberModeVer; u32 HwFiberStat; u8 HwSwitchMdiToFiber; @@ -1594,6 +1613,11 @@ struct rtl8125_private { u32 HwPcieSNOffset; + u8 HwSuppTxNoCloseVer; + u8 EnableTxNoClose; + u32 NextHwDesCloPtr0; + u32 BeginHwDesCloPtr0; + //Dash+++++++++++++++++ u8 HwSuppDashVer; u8 DASH; @@ -1683,6 +1707,9 @@ struct rtl8125_private { //Realwow-------------- #endif //ENABLE_REALWOW_SUPPORT + u32 eee_adv_t; + u8 eee_enabled; + #ifdef ENABLE_R8125_PROCFS //Procfs support struct proc_dir_entry *proc_dir; @@ -1697,8 +1724,10 @@ enum eetype { }; enum mcfg { - CFG_METHOD_2=0, + CFG_METHOD_2=2, CFG_METHOD_3, + CFG_METHOD_4, + CFG_METHOD_5, CFG_METHOD_MAX, CFG_METHOD_DEFAULT = 0xFF }; @@ -1731,6 +1760,8 @@ enum mcfg { //Ram Code Version #define NIC_RAMCODE_VERSION_CFG_METHOD_2 (0x0b11) #define NIC_RAMCODE_VERSION_CFG_METHOD_3 (0x0b33) +#define NIC_RAMCODE_VERSION_CFG_METHOD_4 (0x0b17) +#define NIC_RAMCODE_VERSION_CFG_METHOD_5 (0x0b34) //hwoptimize #define HW_PATCH_SOC_LAN (BIT_0) @@ -1738,11 +1769,11 @@ enum mcfg { void rtl8125_mdio_write(struct rtl8125_private *tp, u32 RegAddr, u32 value); void rtl8125_mdio_prot_write(struct rtl8125_private *tp, u32 RegAddr, u32 value); -void rtl8125_mdio_prot_write_phy_ocp(struct rtl8125_private *tp, u32 RegAddr, u32 value); +void rtl8125_mdio_prot_direct_write_phy_ocp(struct rtl8125_private *tp, u32 RegAddr, u32 value); u32 rtl8125_mdio_read(struct rtl8125_private *tp, u32 RegAddr); u32 rtl8125_mdio_prot_read(struct rtl8125_private *tp, u32 RegAddr); -u32 rtl8125_mdio_prot_read_phy_ocp(struct rtl8125_private *tp, u32 RegAddr); -void rtl8125_ephy_write(void __iomem *ioaddr, int RegAddr, int value); +u32 rtl8125_mdio_prot_direct_read_phy_ocp(struct rtl8125_private *tp, u32 RegAddr); +void rtl8125_ephy_write(struct rtl8125_private *tp, int RegAddr, int value); void rtl8125_mac_ocp_write(struct rtl8125_private *tp, u16 reg_addr, u16 value); u16 rtl8125_mac_ocp_read(struct rtl8125_private *tp, u16 reg_addr); void rtl8125_clear_eth_phy_bit(struct rtl8125_private *tp, u8 addr, u16 mask); @@ -1750,16 +1781,16 @@ void rtl8125_set_eth_phy_bit(struct rtl8125_private *tp, u8 addr, u16 mask); void rtl8125_ocp_write(struct rtl8125_private *tp, u16 addr, u8 len, u32 data); void rtl8125_oob_notify(struct rtl8125_private *tp, u8 cmd); void rtl8125_init_ring_indexes(struct rtl8125_private *tp); -int rtl8125_eri_write(void __iomem *ioaddr, int addr, int len, u32 value, int type); +int rtl8125_eri_write(struct rtl8125_private *tp, int addr, int len, u32 value, int type); void rtl8125_oob_mutex_lock(struct rtl8125_private *tp); u32 rtl8125_mdio_read(struct rtl8125_private *tp, u32 RegAddr); u32 rtl8125_ocp_read(struct rtl8125_private *tp, u16 addr, u8 len); u32 rtl8125_ocp_read_with_oob_base_address(struct rtl8125_private *tp, u16 addr, u8 len, u32 base_address); u32 rtl8125_ocp_write_with_oob_base_address(struct rtl8125_private *tp, u16 addr, u8 len, u32 value, u32 base_address); -u32 rtl8125_eri_read(void __iomem *ioaddr, int addr, int len, int type); -u32 rtl8125_eri_read_with_oob_base_address(void __iomem *ioaddr, int addr, int len, int type, u32 base_address); -int rtl8125_eri_write_with_oob_base_address(void __iomem *ioaddr, int addr, int len, u32 value, int type, u32 base_address); -u16 rtl8125_ephy_read(void __iomem *ioaddr, int RegAddr); +u32 rtl8125_eri_read(struct rtl8125_private *tp, int addr, int len, int type); +u32 rtl8125_eri_read_with_oob_base_address(struct rtl8125_private *tp, int addr, int len, int type, u32 base_address); +int rtl8125_eri_write_with_oob_base_address(struct rtl8125_private *tp, int addr, int len, u32 value, int type, u32 base_address); +u16 rtl8125_ephy_read(struct rtl8125_private *tp, int RegAddr); void rtl8125_wait_txrx_fifo_empty(struct net_device *dev); void rtl8125_enable_now_is_oob(struct rtl8125_private *tp); void rtl8125_disable_now_is_oob(struct rtl8125_private *tp); @@ -1771,6 +1802,7 @@ void rtl8125_dash2_enable_rx(struct rtl8125_private *tp); void rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev); #define HW_SUPPORT_CHECK_PHY_DISABLE_MODE(_M) ((_M)->HwSuppCheckPhyDisableModeVer > 0 ) +#define HW_HAS_WRITE_PHY_MCU_RAM_CODE(_M) (((_M)->HwHasWrRamCodeToMicroP == TRUE) ? 1 : 0) #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) #define netdev_mc_count(dev) ((dev)->mc_count) diff --git a/package/lean/r8125/src/r8125_dash.h b/package/lean/r8125/src/r8125_dash.h index 61d378174..9125eddd3 100644 --- a/package/lean/r8125/src/r8125_dash.h +++ b/package/lean/r8125/src/r8125_dash.h @@ -4,7 +4,7 @@ # r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -241,12 +241,12 @@ RX_DASH_BUFFER_TYPE_2, *PRX_DASH_BUFFER_TYPE_2; #define CMAC_TXDESC_OFFSET 0x98 //TX: 0x98 - 0x9F /* cmac write/read MMIO register */ -#define RTL_CMAC_W8(reg, val8) writeb ((val8), tp->cmac_ioaddr + (reg)) -#define RTL_CMAC_W16(reg, val16) writew ((val16), tp->cmac_ioaddr + (reg)) -#define RTL_CMAC_W32(reg, val32) writel ((val32), tp->cmac_ioaddr + (reg)) -#define RTL_CMAC_R8(reg) readb (tp->cmac_ioaddr + (reg)) -#define RTL_CMAC_R16(reg) readw (tp->cmac_ioaddr + (reg)) -#define RTL_CMAC_R32(reg) ((unsigned long) readl (tp->cmac_ioaddr + (reg))) +#define RTL_CMAC_W8(tp, reg, val8) writeb ((val8), tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_W16(tp, reg, val16) writew ((val16), tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_W32(tp, reg, val32) writel ((val32), tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_R8(tp, reg) readb (tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_R16(tp, reg) readw (tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_R32(tp, reg) ((unsigned long) readl (tp->cmac_ioaddr + (reg))) int rtl8125_dash_ioctl(struct net_device *dev, struct ifreq *ifr); void HandleDashInterrupt(struct net_device *dev); diff --git a/package/lean/r8125/src/r8125_n.c b/package/lean/r8125/src/r8125_n.c index 667f1aa1a..5dabc179b 100644 --- a/package/lean/r8125/src/r8125_n.c +++ b/package/lean/r8125/src/r8125_n.c @@ -4,7 +4,7 @@ # r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -57,8 +57,10 @@ #include #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) #include #endif +#endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) #include #endif @@ -100,18 +102,30 @@ static const struct { u32 RxConfigMask; /* Clears the bits supported by this chip */ u32 jumbo_frame_sz; } rtl_chip_info[] = { - _R("RTL8125", + _R("RTL8125A", CFG_METHOD_2, BIT_30 | BIT_22 | BIT_23 | (RX_DMA_BURST << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_9k), - _R("RTL8125", + _R("RTL8125A", CFG_METHOD_3, BIT_30 | BIT_22 | BIT_23 | (RX_DMA_BURST << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_9k), + _R("RTL8125B", + CFG_METHOD_4, + BIT_30 | BIT_22 | BIT_23 | (RX_DMA_BURST << RxCfgDMAShift), + 0xff7e5880, + Jumbo_Frame_9k), + + _R("RTL8125B", + CFG_METHOD_5, + BIT_30 | BIT_22 | BIT_23 | (RX_DMA_BURST << RxCfgDMAShift), + 0xff7e5880, + Jumbo_Frame_9k), + _R("Unknown", CFG_METHOD_DEFAULT, (RX_DMA_BURST << RxCfgDMAShift), @@ -180,9 +194,14 @@ static int s0_magic_packet = 1; #else static int s0_magic_packet = 0; #endif +#ifdef ENABLE_TX_NO_CLOSE +static int tx_no_close_enable = 1; +#else +static int tx_no_close_enable = 0; +#endif MODULE_AUTHOR("Realtek and the Linux r8125 crew "); -MODULE_DESCRIPTION("RealTek RTL8125 2.5Gigabit Ethernet driver"); +MODULE_DESCRIPTION("Realtek RTL8125 2.5Gigabit Ethernet driver"); module_param(speed_mode, uint, 0); MODULE_PARM_DESC(speed_mode, "force phy operation. Deprecated by ethtool (8)."); @@ -223,6 +242,9 @@ MODULE_PARM_DESC(hwoptimize, "Enable HW optimization function."); module_param(s0_magic_packet, int, 0); MODULE_PARM_DESC(s0_magic_packet, "Enable S0 Magic Packet."); +module_param(tx_no_close_enable, int, 0); +MODULE_PARM_DESC(tx_no_close_enable, "Enable TX No Close."); + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) module_param_named(debug, debug.msg_enable, int, 0); MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); @@ -257,9 +279,13 @@ static void rtl8125_hw_config(struct net_device *dev); static void rtl8125_hw_start(struct net_device *dev); static int rtl8125_close(struct net_device *dev); static void rtl8125_set_rx_mode(struct net_device *dev); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) +static void rtl8125_tx_timeout(struct net_device *dev, unsigned int txqueue); +#else static void rtl8125_tx_timeout(struct net_device *dev); +#endif static struct net_device_stats *rtl8125_get_stats(struct net_device *dev); -static int rtl8125_rx_interrupt(struct net_device *, struct rtl8125_private *, void __iomem *, napi_budget); +static int rtl8125_rx_interrupt(struct net_device *, struct rtl8125_private *, napi_budget); static int rtl8125_change_mtu(struct net_device *dev, int new_mtu); static void rtl8125_down(struct net_device *dev); @@ -588,6 +614,7 @@ static int proc_get_driver_variable(struct seq_file *m, void *v) seq_puts(m, "Variable\tValue\n----------\t-----\n"); seq_printf(m, "MODULENAME\t%s\n", MODULENAME); seq_printf(m, "driver version\t%s\n", RTL8125_VERSION); + seq_printf(m, "mcfg\t%d\n", tp->mcfg); seq_printf(m, "chipset\t%d\n", tp->chipset); seq_printf(m, "chipset_name\t%s\n", rtl_chip_info[tp->chipset].name); seq_printf(m, "mtu\t%d\n", dev->mtu); @@ -652,7 +679,7 @@ static int proc_get_driver_variable(struct seq_file *m, void *v) seq_printf(m, "aspm\t0x%x\n", aspm); seq_printf(m, "s5wol\t0x%x\n", s5wol); seq_printf(m, "s5_keep_curr_mac\t0x%x\n", s5_keep_curr_mac); - seq_printf(m, "eee_enable\t0x%x\n", eee_enable); + seq_printf(m, "eee_enable\t0x%x\n", tp->eee_enabled); seq_printf(m, "hwoptimize\t0x%lx\n", hwoptimize); seq_printf(m, "proc_init_num\t0x%x\n", proc_init_num); seq_printf(m, "s0_magic_packet\t0x%x\n", s0_magic_packet); @@ -660,6 +687,10 @@ static int proc_get_driver_variable(struct seq_file *m, void *v) seq_printf(m, "HwSuppCheckPhyDisableModeVer\t0x%x\n", tp->HwSuppCheckPhyDisableModeVer); seq_printf(m, "HwPkgDet\t0x%x\n", tp->HwPkgDet); seq_printf(m, "HwSuppGigaForceMode\t0x%x\n", tp->HwSuppGigaForceMode); + seq_printf(m, "HwSuppTxNoCloseVer\t0x%x\n", tp->HwSuppTxNoCloseVer); + seq_printf(m, "EnableTxNoClose\t0x%x\n", tp->EnableTxNoClose); + seq_printf(m, "NextHwDesCloPtr0\t0x%x\n", tp->NextHwDesCloPtr0); + seq_printf(m, "BeginHwDesCloPtr0\t0x%x\n", tp->BeginHwDesCloPtr0); seq_printf(m, "random_mac\t0x%x\n", tp->random_mac); seq_printf(m, "org_mac_addr\t%pM\n", tp->org_mac_addr); #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) @@ -676,7 +707,6 @@ static int proc_get_tally_counter(struct seq_file *m, void *v) { struct net_device *dev = m->private; struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; struct rtl8125_counters *counters; dma_addr_t paddr; u32 cmd; @@ -695,13 +725,13 @@ static int proc_get_tally_counter(struct seq_file *m, void *v) } spin_lock_irqsave(&tp->lock, flags); - RTL_W32(CounterAddrHigh, (u64)paddr >> 32); + RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); cmd = (u64)paddr & DMA_BIT_MASK(32); - RTL_W32(CounterAddrLow, cmd); - RTL_W32(CounterAddrLow, cmd | CounterDump); + RTL_W32(tp, CounterAddrLow, cmd); + RTL_W32(tp, CounterAddrLow, cmd | CounterDump); WaitCnt = 0; - while (RTL_R32(CounterAddrLow) & CounterDump) { + while (RTL_R32(tp, CounterAddrLow) & CounterDump) { udelay(10); WaitCnt++; @@ -761,7 +791,6 @@ static int proc_get_pcie_phy(struct seq_file *m, void *v) int i, n, max = R8125_EPHY_REGS_SIZE/2; u16 word_rd; struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; unsigned long flags; seq_puts(m, "\nDump PCIE PHY\n"); @@ -772,7 +801,7 @@ static int proc_get_pcie_phy(struct seq_file *m, void *v) seq_printf(m, "\n0x%02x:\t", n); for (i = 0; i < 8 && n < max; i++, n++) { - word_rd = rtl8125_ephy_read(ioaddr, n); + word_rd = rtl8125_ephy_read(tp, n); seq_printf(m, "%04x ", word_rd); } } @@ -816,7 +845,6 @@ static int proc_get_extended_registers(struct seq_file *m, void *v) int i, n, max = R8125_ERI_REGS_SIZE; u32 dword_rd; struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; unsigned long flags; seq_puts(m, "\nDump Extended Registers\n"); @@ -827,7 +855,7 @@ static int proc_get_extended_registers(struct seq_file *m, void *v) seq_printf(m, "\n0x%02x:\t", n); for (i = 0; i < 4 && n < max; i++, n+=4) { - dword_rd = rtl8125_eri_read(ioaddr, n, 4, ERIAR_ExGMAC); + dword_rd = rtl8125_eri_read(tp, n, 4, ERIAR_ExGMAC); seq_printf(m, "%08x ", dword_rd); } } @@ -891,6 +919,7 @@ static int proc_get_driver_variable(char *page, char **start, len += snprintf(page + len, count - len, "MODULENAME\t%s\n" "driver version\t%s\n" + "mcfg\t%d\n" "chipset\t%d\n" "chipset_name\t%s\n" "mtu\t%d\n" @@ -963,6 +992,10 @@ static int proc_get_driver_variable(char *page, char **start, "HwSuppCheckPhyDisableModeVer\t0x%x\n" "HwPkgDet\t0x%x\n" "HwSuppGigaForceMode\t0x%x\n" + "HwSuppTxNoCloseVer\t0x%x\n" + "EnableTxNoClose\t0x%x\n" + "NextHwDesCloPtr0\t0x%x\n" + "BeginHwDesCloPtr0\t0x%x\n" "random_mac\t0x%x\n" "org_mac_addr\t%pM\n" #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) @@ -971,6 +1004,7 @@ static int proc_get_driver_variable(char *page, char **start, "dev_addr\t%pM\n", MODULENAME, RTL8125_VERSION, + tp->mcfg, tp->chipset, rtl_chip_info[tp->chipset].name, dev->mtu, @@ -1035,7 +1069,7 @@ static int proc_get_driver_variable(char *page, char **start, aspm, s5wol, s5_keep_curr_mac, - eee_enable, + tp->eee_enabled, hwoptimize, proc_init_num, s0_magic_packet, @@ -1043,6 +1077,10 @@ static int proc_get_driver_variable(char *page, char **start, tp->HwSuppCheckPhyDisableModeVer, tp->HwPkgDet, tp->HwSuppGigaForceMode, + tp->HwSuppTxNoCloseVer, + tp->EnableTxNoClose, + tp->NextHwDesCloPtr0, + tp->BeginHwDesCloPtr0, tp->random_mac, tp->org_mac_addr, #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) @@ -1064,7 +1102,6 @@ static int proc_get_tally_counter(char *page, char **start, { struct net_device *dev = data; struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; struct rtl8125_counters *counters; dma_addr_t paddr; u32 cmd; @@ -1086,13 +1123,13 @@ static int proc_get_tally_counter(char *page, char **start, } spin_lock_irqsave(&tp->lock, flags); - RTL_W32(CounterAddrHigh, (u64)paddr >> 32); + RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); cmd = (u64)paddr & DMA_BIT_MASK(32); - RTL_W32(CounterAddrLow, cmd); - RTL_W32(CounterAddrLow, cmd | CounterDump); + RTL_W32(tp, CounterAddrLow, cmd); + RTL_W32(tp, CounterAddrLow, cmd | CounterDump); WaitCnt = 0; - while (RTL_R32(CounterAddrLow) & CounterDump) { + while (RTL_R32(tp, CounterAddrLow) & CounterDump) { udelay(10); WaitCnt++; @@ -1182,7 +1219,6 @@ static int proc_get_pcie_phy(char *page, char **start, int i, n, max = R8125_EPHY_REGS_SIZE/2; u16 word_rd; struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; unsigned long flags; int len = 0; @@ -1197,7 +1233,7 @@ static int proc_get_pcie_phy(char *page, char **start, n); for (i = 0; i < 8 && n < max; i++, n++) { - word_rd = rtl8125_ephy_read(ioaddr, n); + word_rd = rtl8125_ephy_read(tp, n); len += snprintf(page + len, count - len, "%04x ", word_rd); @@ -1258,7 +1294,6 @@ static int proc_get_extended_registers(char *page, char **start, int i, n, max = R8125_ERI_REGS_SIZE; u32 dword_rd; struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; unsigned long flags; int len = 0; @@ -1273,7 +1308,7 @@ static int proc_get_extended_registers(char *page, char **start, n); for (i = 0; i < 4 && n < max; i++, n+=4) { - dword_rd = rtl8125_eri_read(ioaddr, n, 4, ERIAR_ExGMAC); + dword_rd = rtl8125_eri_read(tp, n, 4, ERIAR_ExGMAC); len += snprintf(page + len, count - len, "%08x ", dword_rd); @@ -1360,6 +1395,14 @@ static int rtl8125_proc_open(struct inode *inode, struct file *file) return single_open(file, show, dev); } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) +static const struct proc_ops rtl8125_proc_fops = { + .proc_open = rtl8125_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = single_release, +}; +#else static const struct file_operations rtl8125_proc_fops = { .open = rtl8125_proc_open, .read = seq_read, @@ -1368,6 +1411,8 @@ static const struct file_operations rtl8125_proc_fops = { }; #endif +#endif + /* * Table of proc files we need to create. */ @@ -1496,11 +1541,10 @@ static inline u16 map_phy_ocp_addr(u16 PageNum, u8 RegNum) return OcpPhyAddress; } -static void mdio_real_write_phy_ocp(struct rtl8125_private *tp, - u16 RegAddr, - u16 value) +static void mdio_real_direct_write_phy_ocp(struct rtl8125_private *tp, + u16 RegAddr, + u16 value) { - void __iomem *ioaddr = tp->mmio_addr; u32 data32; int i; @@ -1511,11 +1555,11 @@ static void mdio_real_write_phy_ocp(struct rtl8125_private *tp, data32 <<= OCPR_Addr_Reg_shift; data32 |= OCPR_Write | value; - RTL_W32(PHYOCP, data32); + RTL_W32(tp, PHYOCP, data32); for (i = 0; i < 100; i++) { udelay(1); - if (!(RTL_R32(PHYOCP) & OCPR_Flag)) + if (!(RTL_R32(tp, PHYOCP) & OCPR_Flag)) break; } } @@ -1526,9 +1570,10 @@ static void mdio_direct_write_phy_ocp(struct rtl8125_private *tp, { if (tp->rtk_enable_diag) return; - mdio_real_write_phy_ocp(tp, RegAddr, value); + mdio_real_direct_write_phy_ocp(tp, RegAddr, value); } +/* static void rtl8125_mdio_write_phy_ocp(struct rtl8125_private *tp, u16 PageNum, u32 RegAddr, @@ -1540,6 +1585,19 @@ static void rtl8125_mdio_write_phy_ocp(struct rtl8125_private *tp, mdio_direct_write_phy_ocp(tp, ocp_addr, value); } +*/ + +static void rtl8125_mdio_real_write_phy_ocp(struct rtl8125_private *tp, + u16 PageNum, + u32 RegAddr, + u32 value) +{ + u16 ocp_addr; + + ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); + + mdio_real_direct_write_phy_ocp(tp, ocp_addr, value); +} static void mdio_real_write(struct rtl8125_private *tp, u32 RegAddr, @@ -1549,7 +1607,7 @@ static void mdio_real_write(struct rtl8125_private *tp, tp->cur_page = value; return; } - rtl8125_mdio_write_phy_ocp(tp, tp->cur_page, RegAddr, value); + rtl8125_mdio_real_write_phy_ocp(tp, tp->cur_page, RegAddr, value); } void rtl8125_mdio_write(struct rtl8125_private *tp, @@ -1568,17 +1626,16 @@ void rtl8125_mdio_prot_write(struct rtl8125_private *tp, mdio_real_write(tp, RegAddr, value); } -void rtl8125_mdio_prot_write_phy_ocp(struct rtl8125_private *tp, - u32 RegAddr, - u32 value) +void rtl8125_mdio_prot_direct_write_phy_ocp(struct rtl8125_private *tp, + u32 RegAddr, + u32 value) { - mdio_real_write_phy_ocp(tp, RegAddr, value); + mdio_real_direct_write_phy_ocp(tp, RegAddr, value); } -static u32 mdio_real_read_phy_ocp(struct rtl8125_private *tp, - u16 RegAddr) +static u32 mdio_real_direct_read_phy_ocp(struct rtl8125_private *tp, + u16 RegAddr) { - void __iomem *ioaddr = tp->mmio_addr; u32 data32; int i, value = 0; @@ -1588,14 +1645,14 @@ static u32 mdio_real_read_phy_ocp(struct rtl8125_private *tp, data32 = RegAddr/2; data32 <<= OCPR_Addr_Reg_shift; - RTL_W32(PHYOCP, data32); + RTL_W32(tp, PHYOCP, data32); for (i = 0; i < 100; i++) { udelay(1); - if (RTL_R32(PHYOCP) & OCPR_Flag) + if (RTL_R32(tp, PHYOCP) & OCPR_Flag) break; } - value = RTL_R32(PHYOCP) & OCPDR_Data_Mask; + value = RTL_R32(tp, PHYOCP) & OCPDR_Data_Mask; return value; } @@ -1605,9 +1662,10 @@ static u32 mdio_direct_read_phy_ocp(struct rtl8125_private *tp, { if (tp->rtk_enable_diag) return 0xffffffff; - return mdio_real_read_phy_ocp(tp, RegAddr); + return mdio_real_direct_read_phy_ocp(tp, RegAddr); } +/* static u32 rtl8125_mdio_read_phy_ocp(struct rtl8125_private *tp, u16 PageNum, u32 RegAddr) @@ -1618,11 +1676,23 @@ static u32 rtl8125_mdio_read_phy_ocp(struct rtl8125_private *tp, return mdio_direct_read_phy_ocp(tp, ocp_addr); } +*/ + +static u32 rtl8125_mdio_real_read_phy_ocp(struct rtl8125_private *tp, + u16 PageNum, + u32 RegAddr) +{ + u16 ocp_addr; + + ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); + + return mdio_real_direct_read_phy_ocp(tp, ocp_addr); +} static u32 mdio_real_read(struct rtl8125_private *tp, u32 RegAddr) { - return rtl8125_mdio_read_phy_ocp(tp, tp->cur_page, RegAddr); + return rtl8125_mdio_real_read_phy_ocp(tp, tp->cur_page, RegAddr); } u32 rtl8125_mdio_read(struct rtl8125_private *tp, @@ -1639,10 +1709,10 @@ u32 rtl8125_mdio_prot_read(struct rtl8125_private *tp, return mdio_real_read(tp, RegAddr); } -u32 rtl8125_mdio_prot_read_phy_ocp(struct rtl8125_private *tp, - u32 RegAddr) +u32 rtl8125_mdio_prot_direct_read_phy_ocp(struct rtl8125_private *tp, + u32 RegAddr) { - return mdio_real_read_phy_ocp(tp, RegAddr); + return mdio_real_direct_read_phy_ocp(tp, RegAddr); } static void ClearAndSetEthPhyBit(struct rtl8125_private *tp, u8 addr, u16 clearmask, u16 setmask) @@ -1703,7 +1773,6 @@ void SetEthPhyOcpBit(struct rtl8125_private *tp, u16 addr, u16 mask) void rtl8125_mac_ocp_write(struct rtl8125_private *tp, u16 reg_addr, u16 value) { - void __iomem *ioaddr = tp->mmio_addr; u32 data32; #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) @@ -1715,12 +1784,11 @@ void rtl8125_mac_ocp_write(struct rtl8125_private *tp, u16 reg_addr, u16 value) data32 += value; data32 |= OCPR_Write; - RTL_W32(MACOCP, data32); + RTL_W32(tp, MACOCP, data32); } u16 rtl8125_mac_ocp_read(struct rtl8125_private *tp, u16 reg_addr) { - void __iomem *ioaddr = tp->mmio_addr; u32 data32; u16 data16 = 0; @@ -1731,8 +1799,8 @@ u16 rtl8125_mac_ocp_read(struct rtl8125_private *tp, u16 reg_addr) data32 = reg_addr/2; data32 <<= OCPR_Addr_Reg_shift; - RTL_W32(MACOCP, data32); - data16 = (u16)RTL_R32(MACOCP); + RTL_W32(tp, MACOCP, data32); + data16 = (u16)RTL_R32(tp, MACOCP); return data16; } @@ -1783,9 +1851,7 @@ SetMcuAccessRegBit( u32 rtl8125_ocp_read_with_oob_base_address(struct rtl8125_private *tp, u16 addr, u8 len, const u32 base_address) { - void __iomem *ioaddr = tp->mmio_addr; - - return rtl8125_eri_read_with_oob_base_address(ioaddr, addr, len, ERIAR_OOB, base_address); + return rtl8125_eri_read_with_oob_base_address(tp, addr, len, ERIAR_OOB, base_address); } u32 rtl8125_ocp_read(struct rtl8125_private *tp, u16 addr, u8 len) @@ -1802,9 +1868,7 @@ u32 rtl8125_ocp_read(struct rtl8125_private *tp, u16 addr, u8 len) u32 rtl8125_ocp_write_with_oob_base_address(struct rtl8125_private *tp, u16 addr, u8 len, u32 value, const u32 base_address) { - void __iomem *ioaddr = tp->mmio_addr; - - return rtl8125_eri_write_with_oob_base_address(ioaddr, addr, len, value, ERIAR_OOB, base_address); + return rtl8125_eri_write_with_oob_base_address(tp, addr, len, value, ERIAR_OOB, base_address); } void rtl8125_ocp_write(struct rtl8125_private *tp, u16 addr, u8 len, u32 value) @@ -1828,6 +1892,8 @@ void rtl8125_oob_mutex_lock(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: default: ocp_reg_mutex_oob = 0x110; ocp_reg_mutex_ib = 0x114; @@ -1875,6 +1941,8 @@ void rtl8125_oob_mutex_unlock(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: default: ocp_reg_mutex_oob = 0x110; ocp_reg_mutex_ib = 0x114; @@ -1888,9 +1956,7 @@ void rtl8125_oob_mutex_unlock(struct rtl8125_private *tp) void rtl8125_oob_notify(struct rtl8125_private *tp, u8 cmd) { - void __iomem *ioaddr = tp->mmio_addr; - - rtl8125_eri_write(ioaddr, 0xE8, 1, cmd, ERIAR_ExGMAC); + rtl8125_eri_write(tp, 0xE8, 1, cmd, ERIAR_ExGMAC); rtl8125_ocp_write(tp, 0x30, 1, 0x01); } @@ -1914,12 +1980,12 @@ void rtl8125_dash2_disable_tx(struct rtl8125_private *tp) u8 TmpUchar; //Disable oob Tx - RTL_CMAC_W8(CMAC_IBCR2, RTL_CMAC_R8(CMAC_IBCR2) & ~( BIT_0 )); + RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) & ~( BIT_0 )); WaitCnt = 0; //wait oob tx disable do { - TmpUchar = RTL_CMAC_R8(CMAC_IBISR0); + TmpUchar = RTL_CMAC_R8(tp, CMAC_IBISR0); if ( TmpUchar & ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE ) { break; @@ -1930,7 +1996,7 @@ void rtl8125_dash2_disable_tx(struct rtl8125_private *tp) } while(WaitCnt < 2000); //Clear ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE - RTL_CMAC_W8(CMAC_IBISR0, RTL_CMAC_R8(CMAC_IBISR0) | ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE); + RTL_CMAC_W8(tp, CMAC_IBISR0, RTL_CMAC_R8(tp, CMAC_IBISR0) | ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE); } } @@ -1939,7 +2005,7 @@ void rtl8125_dash2_enable_tx(struct rtl8125_private *tp) if (!tp->DASH) return; if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(CMAC_IBCR2, RTL_CMAC_R8(CMAC_IBCR2) | BIT_0); + RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) | BIT_0); } } @@ -1948,7 +2014,7 @@ void rtl8125_dash2_disable_rx(struct rtl8125_private *tp) if (!tp->DASH) return; if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(CMAC_IBCR0, RTL_CMAC_R8(CMAC_IBCR0) & ~( BIT_0 )); + RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) & ~( BIT_0 )); } } @@ -1957,7 +2023,7 @@ void rtl8125_dash2_enable_rx(struct rtl8125_private *tp) if (!tp->DASH) return; if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(CMAC_IBCR0, RTL_CMAC_R8(CMAC_IBCR0) | BIT_0); + RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) | BIT_0); } } @@ -2018,11 +2084,11 @@ static void rtl8125_driver_stop(struct rtl8125_private *tp) } } -void rtl8125_ephy_write(void __iomem *ioaddr, int RegAddr, int value) +void rtl8125_ephy_write(struct rtl8125_private *tp, int RegAddr, int value) { int i; - RTL_W32(EPHYAR, + RTL_W32(tp, EPHYAR, EPHYAR_Write | (RegAddr & EPHYAR_Reg_Mask_v2) << EPHYAR_Reg_shift | (value & EPHYAR_Data_Mask)); @@ -2031,27 +2097,27 @@ void rtl8125_ephy_write(void __iomem *ioaddr, int RegAddr, int value) udelay(100); /* Check if the RTL8125 has completed EPHY write */ - if (!(RTL_R32(EPHYAR) & EPHYAR_Flag)) + if (!(RTL_R32(tp, EPHYAR) & EPHYAR_Flag)) break; } udelay(20); } -u16 rtl8125_ephy_read(void __iomem *ioaddr, int RegAddr) +u16 rtl8125_ephy_read(struct rtl8125_private *tp, int RegAddr) { int i; u16 value = 0xffff; - RTL_W32(EPHYAR, + RTL_W32(tp, EPHYAR, EPHYAR_Read | (RegAddr & EPHYAR_Reg_Mask_v2) << EPHYAR_Reg_shift); for (i = 0; i < 10; i++) { udelay(100); /* Check if the RTL8125 has completed EPHY read */ - if (RTL_R32(EPHYAR) & EPHYAR_Flag) { - value = (u16) (RTL_R32(EPHYAR) & EPHYAR_Data_Mask); + if (RTL_R32(tp, EPHYAR) & EPHYAR_Flag) { + value = (u16) (RTL_R32(tp, EPHYAR) & EPHYAR_Data_Mask); break; } } @@ -2061,16 +2127,14 @@ u16 rtl8125_ephy_read(void __iomem *ioaddr, int RegAddr) return value; } -/* static void ClearAndSetPCIePhyBit(struct rtl8125_private *tp, u8 addr, u16 clearmask, u16 setmask) { - void __iomem *ioaddr = tp->mmio_addr; u16 EphyValue; - EphyValue = rtl8125_ephy_read( ioaddr, addr ); + EphyValue = rtl8125_ephy_read(tp, addr); EphyValue &= ~clearmask; EphyValue |= setmask; - rtl8125_ephy_write( ioaddr, addr, EphyValue); + rtl8125_ephy_write(tp, addr, EphyValue); } static void ClearPCIePhyBit(struct rtl8125_private *tp, u8 addr, u16 mask) @@ -2090,14 +2154,12 @@ static void SetPCIePhyBit( struct rtl8125_private *tp, u8 addr, u16 mask) mask ); } -*/ static u32 rtl8125_csi_other_fun_read(struct rtl8125_private *tp, u8 multi_fun_sel_bit, u32 addr) { - void __iomem *ioaddr = tp->mmio_addr; u32 cmd; int i; u32 value = 0; @@ -2112,14 +2174,14 @@ rtl8125_csi_other_fun_read(struct rtl8125_private *tp, cmd |= multi_fun_sel_bit << 16; - RTL_W32(CSIAR, cmd); + RTL_W32(tp, CSIAR, cmd); for (i = 0; i < 10; i++) { udelay(100); /* Check if the RTL8125 has completed CSI read */ - if (RTL_R32(CSIAR) & CSIAR_Flag) { - value = (u32)RTL_R32(CSIDR); + if (RTL_R32(tp, CSIAR) & CSIAR_Flag) { + value = (u32)RTL_R32(tp, CSIDR); break; } } @@ -2135,11 +2197,10 @@ rtl8125_csi_other_fun_write(struct rtl8125_private *tp, u32 addr, u32 value) { - void __iomem *ioaddr = tp->mmio_addr; u32 cmd; int i; - RTL_W32(CSIDR, value); + RTL_W32(tp, CSIDR, value); cmd = CSIAR_Write | CSIAR_ByteEn << CSIAR_ByteEn_shift | (addr & CSIAR_Addr_Mask); if (tp->mcfg == CFG_METHOD_DEFAULT) multi_fun_sel_bit = 0; @@ -2149,13 +2210,13 @@ rtl8125_csi_other_fun_write(struct rtl8125_private *tp, cmd |= multi_fun_sel_bit << 16; - RTL_W32(CSIAR, cmd); + RTL_W32(tp, CSIAR, cmd); for (i = 0; i < 10; i++) { udelay(100); /* Check if the RTL8125 has completed CSI write */ - if (!(RTL_R32(CSIAR) & CSIAR_Flag)) + if (!(RTL_R32(tp, CSIAR) & CSIAR_Flag)) break; } @@ -2168,10 +2229,7 @@ rtl8125_csi_read(struct rtl8125_private *tp, { u8 multi_fun_sel_bit; - if (tp->mcfg == CFG_METHOD_DEFAULT) - multi_fun_sel_bit = 0; - else - multi_fun_sel_bit = 1; + multi_fun_sel_bit = 0; return rtl8125_csi_other_fun_read(tp, multi_fun_sel_bit, addr); } @@ -2183,10 +2241,7 @@ rtl8125_csi_write(struct rtl8125_private *tp, { u8 multi_fun_sel_bit; - if (tp->mcfg == CFG_METHOD_DEFAULT) - multi_fun_sel_bit = 0; - else - multi_fun_sel_bit = 1; + multi_fun_sel_bit = 0; rtl8125_csi_other_fun_write(tp, multi_fun_sel_bit, addr, value); } @@ -2243,7 +2298,7 @@ rtl8125_csi_fun0_write_byte(struct rtl8125_private *tp, udelay(20); } -u32 rtl8125_eri_read_with_oob_base_address(void __iomem *ioaddr, int addr, int len, int type, const u32 base_address) +u32 rtl8125_eri_read_with_oob_base_address(struct rtl8125_private *tp, int addr, int len, int type, const u32 base_address) { int i, val_shift, shift = 0; u32 value1 = 0, value2 = 0, mask; @@ -2270,13 +2325,13 @@ u32 rtl8125_eri_read_with_oob_base_address(void __iomem *ioaddr, int addr, int l eri_cmd |= (tmp << 20) & 0x00F00000; } - RTL_W32(ERIAR, eri_cmd); + RTL_W32(tp, ERIAR, eri_cmd); for (i = 0; i < 10; i++) { udelay(100); /* Check if the RTL8125 has completed ERI read */ - if (RTL_R32(ERIAR) & ERIAR_Flag) + if (RTL_R32(tp, ERIAR) & ERIAR_Flag) break; } @@ -2285,7 +2340,7 @@ u32 rtl8125_eri_read_with_oob_base_address(void __iomem *ioaddr, int addr, int l else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; - value1 = RTL_R32(ERIDR) & mask; + value1 = RTL_R32(tp, ERIDR) & mask; value2 |= (value1 >> val_shift * 8) << shift * 8; if (len <= 4 - val_shift) { @@ -2302,12 +2357,12 @@ u32 rtl8125_eri_read_with_oob_base_address(void __iomem *ioaddr, int addr, int l return value2; } -u32 rtl8125_eri_read(void __iomem *ioaddr, int addr, int len, int type) +u32 rtl8125_eri_read(struct rtl8125_private *tp, int addr, int len, int type) { - return rtl8125_eri_read_with_oob_base_address(ioaddr, addr, len, type, 0); + return rtl8125_eri_read_with_oob_base_address(tp, addr, len, type, 0); } -int rtl8125_eri_write_with_oob_base_address(void __iomem *ioaddr, int addr, int len, u32 value, int type, const u32 base_address) +int rtl8125_eri_write_with_oob_base_address(struct rtl8125_private *tp, int addr, int len, u32 value, int type, const u32 base_address) { int i, val_shift, shift = 0; u32 value1 = 0, mask; @@ -2326,10 +2381,10 @@ int rtl8125_eri_write_with_oob_base_address(void __iomem *ioaddr, int addr, int else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; - value1 = rtl8125_eri_read_with_oob_base_address(ioaddr, addr, 4, type, base_address) & ~mask; + value1 = rtl8125_eri_read_with_oob_base_address(tp, addr, 4, type, base_address) & ~mask; value1 |= ((value << val_shift * 8) >> shift * 8); - RTL_W32(ERIDR, value1); + RTL_W32(tp, ERIDR, value1); eri_cmd = ERIAR_Write | transformed_base_address | @@ -2344,13 +2399,13 @@ int rtl8125_eri_write_with_oob_base_address(void __iomem *ioaddr, int addr, int eri_cmd |= (tmp << 20) & 0x00F00000; } - RTL_W32(ERIAR, eri_cmd); + RTL_W32(tp, ERIAR, eri_cmd); for (i = 0; i < 10; i++) { udelay(100); /* Check if the RTL8125 has completed ERI write */ - if (!(RTL_R32(ERIAR) & ERIAR_Flag)) + if (!(RTL_R32(tp, ERIAR) & ERIAR_Flag)) break; } @@ -2368,21 +2423,22 @@ int rtl8125_eri_write_with_oob_base_address(void __iomem *ioaddr, int addr, int return 0; } -int rtl8125_eri_write(void __iomem *ioaddr, int addr, int len, u32 value, int type) +int rtl8125_eri_write(struct rtl8125_private *tp, int addr, int len, u32 value, int type) { - return rtl8125_eri_write_with_oob_base_address(ioaddr, addr, len, value, type, NO_BASE_ADDRESS); + return rtl8125_eri_write_with_oob_base_address(tp, addr, len, value, type, NO_BASE_ADDRESS); } static void rtl8125_enable_rxdvgate(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W8(0xF2, RTL_R8(0xF2) | BIT_3); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_3); mdelay(2); break; } @@ -2392,12 +2448,13 @@ static void rtl8125_disable_rxdvgate(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W8(0xF2, RTL_R8(0xF2) & ~BIT_3); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_3); mdelay(2); break; } @@ -2426,12 +2483,11 @@ static u8 rtl8125_is_phy_disable_mode_enabled(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; u8 phy_disable_mode_enabled = FALSE; switch (tp->HwSuppCheckPhyDisableModeVer) { case 3: - if (RTL_R8(0xF2) & BIT_5) + if (RTL_R8(tp, 0xF2) & BIT_5) phy_disable_mode_enabled = TRUE; break; } @@ -2460,11 +2516,10 @@ static void rtl8125_enable_phy_disable_mode(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->HwSuppCheckPhyDisableModeVer) { case 3: - RTL_W8(0xF2, RTL_R8(0xF2) | BIT_5); + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_5); break; } @@ -2475,11 +2530,10 @@ static void rtl8125_disable_phy_disable_mode(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->HwSuppCheckPhyDisableModeVer) { case 3: - RTL_W8(0xF2, RTL_R8(0xF2) & ~BIT_5); + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_5); break; } @@ -2492,15 +2546,28 @@ void rtl8125_wait_txrx_fifo_empty(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; int i; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - for (i = 0; i < 10; i++) { - udelay(100); - if ((RTL_R8(MCUCmd_reg) & (Txfifo_empty | Rxfifo_empty)) == (Txfifo_empty | Rxfifo_empty)) + case CFG_METHOD_4: + case CFG_METHOD_5: + for (i = 0; i < 3000; i++) { + udelay(50); + if ((RTL_R8(tp, MCUCmd_reg) & (Txfifo_empty | Rxfifo_empty)) == (Txfifo_empty | Rxfifo_empty)) + break; + + } + break; + } + + switch (tp->mcfg) { + case CFG_METHOD_4: + case CFG_METHOD_5: + for (i = 0; i < 3000; i++) { + udelay(50); + if ((RTL_R16(tp, IntrMitigate) & (BIT_0 | BIT_1 | BIT_8)) == (BIT_0 | BIT_1 | BIT_8)) break; } @@ -2511,93 +2578,93 @@ rtl8125_wait_txrx_fifo_empty(struct net_device *dev) #ifdef ENABLE_DASH_SUPPORT inline void -rtl8125_enable_dash2_interrupt(struct rtl8125_private *tp, void __iomem *ioaddr) +rtl8125_enable_dash2_interrupt(struct rtl8125_private *tp) { if (!tp->DASH) return; if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(CMAC_IBIMR0, ( ISRIMR_DASH_TYPE2_ROK | ISRIMR_DASH_TYPE2_TOK | ISRIMR_DASH_TYPE2_TDU | ISRIMR_DASH_TYPE2_RDU | ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE )); + RTL_CMAC_W8(tp, CMAC_IBIMR0, ( ISRIMR_DASH_TYPE2_ROK | ISRIMR_DASH_TYPE2_TOK | ISRIMR_DASH_TYPE2_TDU | ISRIMR_DASH_TYPE2_RDU | ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE )); } } static inline void -rtl8125_disable_dash2_interrupt(struct rtl8125_private *tp, void __iomem *ioaddr) +rtl8125_disable_dash2_interrupt(struct rtl8125_private *tp) { if (!tp->DASH) return; if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(CMAC_IBIMR0, 0); + RTL_CMAC_W8(tp, CMAC_IBIMR0, 0); } } #endif static inline void -rtl8125_enable_hw_interrupt(struct rtl8125_private *tp, void __iomem *ioaddr) +rtl8125_enable_hw_interrupt(struct rtl8125_private *tp) { - RTL_W32(IMR0_8125, tp->intr_mask); + RTL_W32(tp, IMR0_8125, tp->intr_mask); #ifdef ENABLE_DASH_SUPPORT if (tp->DASH) - rtl8125_enable_dash2_interrupt(tp, ioaddr); + rtl8125_enable_dash2_interrupt(tp); #endif } static inline void -rtl8125_disable_hw_interrupt(struct rtl8125_private *tp, void __iomem *ioaddr) +rtl8125_disable_hw_interrupt(struct rtl8125_private *tp) { - RTL_W32(IMR0_8125, 0x0000); + RTL_W32(tp, IMR0_8125, 0x0000); #ifdef ENABLE_DASH_SUPPORT if (tp->DASH) - rtl8125_disable_dash2_interrupt(tp, ioaddr); + rtl8125_disable_dash2_interrupt(tp); #endif } static inline void -rtl8125_switch_to_hw_interrupt(struct rtl8125_private *tp, void __iomem *ioaddr) +rtl8125_switch_to_hw_interrupt(struct rtl8125_private *tp) { - RTL_W32(TIMER_INT0_8125, 0x0000); + RTL_W32(tp, TIMER_INT0_8125, 0x0000); - rtl8125_enable_hw_interrupt(tp, ioaddr); + rtl8125_enable_hw_interrupt(tp); } static inline void -rtl8125_switch_to_timer_interrupt(struct rtl8125_private *tp, void __iomem *ioaddr) +rtl8125_switch_to_timer_interrupt(struct rtl8125_private *tp) { if (tp->use_timer_interrrupt) { - RTL_W32(TIMER_INT0_8125, timer_count); - RTL_W32(TCTR0_8125, timer_count); - RTL_W32(IMR0_8125, tp->timer_intr_mask); + RTL_W32(tp, TIMER_INT0_8125, timer_count); + RTL_W32(tp, TCTR0_8125, timer_count); + RTL_W32(tp, IMR0_8125, tp->timer_intr_mask); #ifdef ENABLE_DASH_SUPPORT if (tp->DASH) - rtl8125_enable_dash2_interrupt(tp, ioaddr); + rtl8125_enable_dash2_interrupt(tp); #endif } else { - rtl8125_switch_to_hw_interrupt(tp, ioaddr); + rtl8125_switch_to_hw_interrupt(tp); } } static void -rtl8125_irq_mask_and_ack(struct rtl8125_private *tp, void __iomem *ioaddr) +rtl8125_irq_mask_and_ack(struct rtl8125_private *tp) { - rtl8125_disable_hw_interrupt(tp, ioaddr); + rtl8125_disable_hw_interrupt(tp); #ifdef ENABLE_DASH_SUPPORT if (tp->DASH) { if (tp->dash_printer_enabled) { - RTL_W16(IntrStatus, RTL_R16(IntrStatus) & + RTL_W16(tp, IntrStatus, RTL_R16(tp, IntrStatus) & ~(ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET)); } else { if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(CMAC_IBISR0, RTL_CMAC_R8(CMAC_IBISR0)); + RTL_CMAC_W8(tp, CMAC_IBISR0, RTL_CMAC_R8(tp, CMAC_IBISR0)); } } } else { - RTL_W16(IntrStatus, RTL_R16(IntrStatus)); + RTL_W16(tp, IntrStatus, RTL_R16(tp, IntrStatus)); } #else - RTL_W16(IntrStatus, RTL_R16(IntrStatus)); + RTL_W16(tp, IntrStatus, RTL_R16(tp, IntrStatus)); #endif } @@ -2605,10 +2672,9 @@ static void rtl8125_nic_reset(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; int i; - RTL_W32(RxConfig, (RX_DMA_BURST << RxCfgDMAShift)); + RTL_W32(tp, RxConfig, (RX_DMA_BURST << RxCfgDMAShift)); rtl8125_enable_rxdvgate(dev); @@ -2617,18 +2683,20 @@ rtl8125_nic_reset(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: default: mdelay(2); break; } /* Soft reset the chip. */ - RTL_W8(ChipCmd, CmdReset); + RTL_W8(tp, ChipCmd, CmdReset); /* Check that the chip has finished the reset. */ for (i = 100; i > 0; i--) { udelay(100); - if ((RTL_R8(ChipCmd) & CmdReset) == 0) + if ((RTL_R8(tp, ChipCmd) & CmdReset) == 0) break; } } @@ -2637,15 +2705,16 @@ static void rtl8125_hw_clear_timer_int(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W32(TIMER_INT0_8125, 0x0000); - RTL_W32(TIMER_INT1_8125, 0x0000); - RTL_W32(TIMER_INT2_8125, 0x0000); - RTL_W32(TIMER_INT3_8125, 0x0000); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W32(tp, TIMER_INT0_8125, 0x0000); + RTL_W32(tp, TIMER_INT1_8125, 0x0000); + RTL_W32(tp, TIMER_INT2_8125, 0x0000); + RTL_W32(tp, TIMER_INT3_8125, 0x0000); break; } } @@ -2654,15 +2723,16 @@ static void rtl8125_hw_clear_int_miti(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; int i; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: //IntMITI_0-IntMITI_31 for (i=0xA00; i<0xB00; i+=4) { - RTL_W32(i, 0x0000); + RTL_W32(tp, i, 0x0000); } break; } @@ -2672,10 +2742,9 @@ static void rtl8125_hw_reset(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; /* Disable interrupts */ - rtl8125_irq_mask_and_ack(tp, ioaddr); + rtl8125_irq_mask_and_ack(tp); rtl8125_hw_clear_timer_int(dev); @@ -2698,10 +2767,9 @@ static unsigned int rtl8125_xmii_link_ok(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; unsigned int retval; - retval = (RTL_R16(PHYstatus) & LinkStatus) ? 1 : 0; + retval = (RTL_R16(tp, PHYstatus) & LinkStatus) ? 1 : 0; return retval; } @@ -2745,6 +2813,8 @@ void rtl8125_init_ring_indexes(struct rtl8125_private *tp) tp->dirty_rx = 0; tp->cur_tx = 0; tp->cur_rx = 0; + tp->NextHwDesCloPtr0 = 0; + tp->BeginHwDesCloPtr0 = 0; } static void @@ -2753,6 +2823,8 @@ rtl8125_issue_offset_99_event(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xE09A, rtl8125_mac_ocp_read(tp, 0xE09A) | BIT_0); break; } @@ -2762,15 +2834,13 @@ rtl8125_issue_offset_99_event(struct rtl8125_private *tp) static void NICChkTypeEnableDashInterrupt(struct rtl8125_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - if (tp->DASH) { // // even disconnected, enable 3 dash interrupt mask bits for in-band/out-band communication // if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - rtl8125_enable_dash2_interrupt(tp, ioaddr); - RTL_W16(IntrMask, (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET)); + rtl8125_enable_dash2_interrupt(tp); + RTL_W16(tp, IntrMask, (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET)); } } } @@ -2784,6 +2854,8 @@ static int rtl8125_enable_eee_plus(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xE080, rtl8125_mac_ocp_read(tp, 0xE080)|BIT_1); break; @@ -2804,6 +2876,8 @@ static int rtl8125_disable_eee_plus(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xE080, rtl8125_mac_ocp_read(tp, 0xE080)&~BIT_1); break; @@ -2820,7 +2894,6 @@ static void rtl8125_check_link_status(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; int link_status_on; link_status_on = tp->link_ok(dev); @@ -2831,14 +2904,17 @@ rtl8125_check_link_status(struct net_device *dev) if ((tp->mcfg == CFG_METHOD_2) && netif_running(dev)) { - if (RTL_R16(PHYstatus)&FullDup) - RTL_W32(TxConfig, (RTL_R32(TxConfig) | (BIT_24 | BIT_25)) & ~BIT_19); + if (RTL_R16(tp, PHYstatus)&FullDup) + RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) | (BIT_24 | BIT_25)) & ~BIT_19); else - RTL_W32(TxConfig, (RTL_R32(TxConfig) | BIT_25) & ~(BIT_19 | BIT_24)); + RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) | BIT_25) & ~(BIT_19 | BIT_24)); } - if ((tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3) && - (RTL_R8(PHYstatus) & _10bps)) + if ((tp->mcfg == CFG_METHOD_2 || + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) && + (RTL_R8(tp, PHYstatus) & _10bps)) rtl8125_enable_eee_plus(tp); rtl8125_hw_start(dev); @@ -2858,7 +2934,10 @@ rtl8125_check_link_status(struct net_device *dev) tp->phy_reg_anlpar = 0; - if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3) + if (tp->mcfg == CFG_METHOD_2 || + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) rtl8125_disable_eee_plus(tp); netif_stop_queue(dev); @@ -2924,7 +3003,10 @@ rtl8125_enable_ocp_phy_power_saving(struct net_device *dev) struct rtl8125_private *tp = netdev_priv(dev); u16 val; - if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3) { + if (tp->mcfg == CFG_METHOD_2 || + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) { val = mdio_direct_read_phy_ocp(tp, 0xC416); if (val != 0x0050) { rtl8125_set_phy_mcu_patch_request(tp); @@ -2942,7 +3024,10 @@ rtl8125_disable_ocp_phy_power_saving(struct net_device *dev) struct rtl8125_private *tp = netdev_priv(dev); u16 val; - if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3) { + if (tp->mcfg == CFG_METHOD_2 || + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) { val = mdio_direct_read_phy_ocp(tp, 0xC416); if (val != 0x0500) { rtl8125_set_phy_mcu_patch_request(tp); @@ -2957,12 +3042,11 @@ static void rtl8125_wait_ll_share_fifo_ready(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; int i; for (i = 0; i < 10; i++) { udelay(100); - if (RTL_R16(0xD2) & BIT_9) + if (RTL_R16(tp, 0xD2) & BIT_9) break; } } @@ -2973,6 +3057,8 @@ rtl8125_disable_pci_offset_99(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xE032, rtl8125_mac_ocp_read(tp, 0xE032) & ~(BIT_0 | BIT_1)); break; } @@ -2980,6 +3066,8 @@ rtl8125_disable_pci_offset_99(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_csi_fun0_write_byte(tp, 0x99, 0x00); break; } @@ -2993,6 +3081,8 @@ rtl8125_enable_pci_offset_99(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_csi_fun0_write_byte(tp, 0x99, tp->org_pci_offset_99); break; } @@ -3000,6 +3090,8 @@ rtl8125_enable_pci_offset_99(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: csi_tmp = rtl8125_mac_ocp_read(tp, 0xE032); csi_tmp &= ~(BIT_0 | BIT_1); if (!(tp->org_pci_offset_99 & (BIT_5 | BIT_6))) @@ -3036,6 +3128,31 @@ rtl8125_init_pci_offset_99(struct rtl8125_private *tp) csi_tmp |= (BIT_0); rtl8125_mac_ocp_write(tp, 0xE0A2, csi_tmp); break; + case CFG_METHOD_4: + case CFG_METHOD_5: + rtl8125_mac_ocp_write(tp, 0xCDD0, 0x9003); + csi_tmp = rtl8125_mac_ocp_read(tp, 0xE034); + csi_tmp |= (BIT_15 | BIT_14); + rtl8125_mac_ocp_write(tp, 0xE034, csi_tmp); + rtl8125_mac_ocp_write(tp, 0xCDD2, 0x889C); + rtl8125_mac_ocp_write(tp, 0xCDD8, 0x9003); + rtl8125_mac_ocp_write(tp, 0xCDD4, 0x8C30); + rtl8125_mac_ocp_write(tp, 0xCDDA, 0x9003); + rtl8125_mac_ocp_write(tp, 0xCDD6, 0x9003); + rtl8125_mac_ocp_write(tp, 0xCDDC, 0x9003); + rtl8125_mac_ocp_write(tp, 0xCDE8, 0x883E); + rtl8125_mac_ocp_write(tp, 0xCDEA, 0x9003); + rtl8125_mac_ocp_write(tp, 0xCDEC, 0x889C); + rtl8125_mac_ocp_write(tp, 0xCDEE, 0x9003); + rtl8125_mac_ocp_write(tp, 0xCDF0, 0x8C09); + rtl8125_mac_ocp_write(tp, 0xCDF2, 0x9003); + csi_tmp = rtl8125_mac_ocp_read(tp, 0xE032); + csi_tmp |= (BIT_14); + rtl8125_mac_ocp_write(tp, 0xE032, csi_tmp); + csi_tmp = rtl8125_mac_ocp_read(tp, 0xE0A2); + csi_tmp |= (BIT_0); + rtl8125_mac_ocp_write(tp, 0xE0A2, csi_tmp); + break; } rtl8125_enable_pci_offset_99(tp); @@ -3049,7 +3166,8 @@ rtl8125_disable_pci_offset_180(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - csi_tmp = rtl8125_mac_ocp_read(tp, 0xE032); + case CFG_METHOD_4: + case CFG_METHOD_5: csi_tmp = rtl8125_mac_ocp_read(tp, 0xE092); csi_tmp &= 0xFF00; rtl8125_mac_ocp_write(tp, 0xE092, csi_tmp); @@ -3065,6 +3183,8 @@ rtl8125_enable_pci_offset_180(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: csi_tmp = rtl8125_mac_ocp_read(tp, 0xE094); csi_tmp &= 0x00FF; rtl8125_mac_ocp_write(tp, 0xE094, csi_tmp); @@ -3074,15 +3194,14 @@ rtl8125_enable_pci_offset_180(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - csi_tmp = rtl8125_mac_ocp_read(tp, 0xE032); + case CFG_METHOD_4: + case CFG_METHOD_5: csi_tmp = rtl8125_mac_ocp_read(tp, 0xE092); csi_tmp &= 0xFF00; csi_tmp |= BIT_2; rtl8125_mac_ocp_write(tp, 0xE092, csi_tmp); break; } - - rtl8125_mac_ocp_write(tp, 0xE094, 0x0000); } static void @@ -3102,6 +3221,8 @@ rtl8125_set_pci_99_180_exit_driver_para(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_issue_offset_99_event(tp); break; } @@ -3109,12 +3230,16 @@ rtl8125_set_pci_99_180_exit_driver_para(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_disable_pci_offset_99(tp); break; } switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_disable_pci_offset_180(tp); break; } @@ -3123,34 +3248,31 @@ rtl8125_set_pci_99_180_exit_driver_para(struct net_device *dev) static void rtl8125_enable_cfg9346_write(struct rtl8125_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - - RTL_W8(Cfg9346, RTL_R8(Cfg9346) | Cfg9346_Unlock); + RTL_W8(tp, Cfg9346, RTL_R8(tp, Cfg9346) | Cfg9346_Unlock); } static void rtl8125_disable_cfg9346_write(struct rtl8125_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - - RTL_W8(Cfg9346, RTL_R8(Cfg9346) & ~Cfg9346_Unlock); + RTL_W8(tp, Cfg9346, RTL_R8(tp, Cfg9346) & ~Cfg9346_Unlock); } static void rtl8125_hw_d3_para(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; - RTL_W16(RxMaxSize, RX_BUF_SIZE); + RTL_W16(tp, RxMaxSize, RX_BUF_SIZE); switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7); rtl8125_enable_cfg9346_write(tp); - RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7); - RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0); + RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); rtl8125_disable_cfg9346_write(tp); break; } @@ -3162,6 +3284,8 @@ rtl8125_hw_d3_para(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xEA18, 0x0064); break; } @@ -3169,7 +3293,10 @@ rtl8125_hw_d3_para(struct net_device *dev) rtl8125_set_pci_99_180_exit_driver_para(dev); /*disable ocp phy power saving*/ - if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3) + if (tp->mcfg == CFG_METHOD_2 || + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) rtl8125_disable_ocp_phy_power_saving(dev); rtl8125_disable_rxdvgate(dev); @@ -3204,7 +3331,6 @@ static void rtl8125_get_hw_wol(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; u8 options; u32 csi_tmp; unsigned long flags; @@ -3212,11 +3338,11 @@ rtl8125_get_hw_wol(struct net_device *dev) spin_lock_irqsave(&tp->lock, flags); tp->wol_opts = 0; - options = RTL_R8(Config1); + options = RTL_R8(tp, Config1); if (!(options & PMEnable)) goto out_unlock; - options = RTL_R8(Config3); + options = RTL_R8(tp, Config3); if (options & LinkUp) tp->wol_opts |= WAKE_PHY; @@ -3228,7 +3354,7 @@ rtl8125_get_hw_wol(struct net_device *dev) break; } - options = RTL_R8(Config5); + options = RTL_R8(tp, Config5); if (options & UWF) tp->wol_opts |= WAKE_UCAST; if (options & BWF) @@ -3246,7 +3372,6 @@ static void rtl8125_set_hw_wol(struct net_device *dev, u32 wolopts) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; int i,tmp; static struct { u32 opt; @@ -3275,10 +3400,10 @@ rtl8125_set_hw_wol(struct net_device *dev, u32 wolopts) rtl8125_enable_cfg9346_write(tp); for (i = 0; i < tmp; i++) { - u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; + u8 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; if (wolopts & cfg[i].opt) options |= cfg[i].mask; - RTL_W8(cfg[i].reg, options); + RTL_W8(tp, cfg[i].reg, options); } rtl8125_disable_cfg9346_write(tp); @@ -3327,7 +3452,6 @@ static void rtl8125_powerdown_pll(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; if (tp->wol_enabled == WOL_ENABLED || tp->DASH || tp->EnableKCPOffload) { int auto_nego; @@ -3337,9 +3461,11 @@ rtl8125_powerdown_pll(struct net_device *dev) rtl8125_set_hw_wol(dev, tp->wol_opts); if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3) { + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) { rtl8125_enable_cfg9346_write(tp); - RTL_W8(Config2, RTL_R8(Config2) | PMSTS_En); + RTL_W8(tp, Config2, RTL_R8(tp, Config2) | PMSTS_En); rtl8125_disable_cfg9346_write(tp); } @@ -3369,7 +3495,9 @@ rtl8125_powerdown_pll(struct net_device *dev) rtl8125_mdio_write(tp, MII_ADVERTISE, auto_nego); rtl8125_mdio_write(tp, MII_CTRL1000, giga_ctrl); if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3) { + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) { int ctrl_2500; ctrl_2500 = mdio_direct_read_phy_ocp(tp, 0xA5D4); @@ -3378,7 +3506,7 @@ rtl8125_powerdown_pll(struct net_device *dev) } rtl8125_phy_restart_nway(dev); - RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); + RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); return; } @@ -3391,14 +3519,18 @@ rtl8125_powerdown_pll(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W8(PMCH, RTL_R8(PMCH) & ~BIT_7); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~BIT_7); break; } switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W8(0xF2, RTL_R8(0xF2) & ~BIT_6); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_6); break; } } @@ -3406,12 +3538,13 @@ rtl8125_powerdown_pll(struct net_device *dev) static void rtl8125_powerup_pll(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W8(PMCH, RTL_R8(PMCH) | BIT_7 | BIT_6); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | BIT_7 | BIT_6); break; } @@ -3424,7 +3557,6 @@ rtl8125_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; u8 options; unsigned long flags; @@ -3439,7 +3571,7 @@ rtl8125_get_wol(struct net_device *dev, spin_lock_irqsave(&tp->lock, flags); - options = RTL_R8(Config1); + options = RTL_R8(tp, Config1); if (!(options & PMEnable)) goto out_unlock; @@ -3705,7 +3837,6 @@ rtl8125_set_rx_csum(struct net_device *dev, u32 data) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; unsigned long flags; if (tp->mcfg == CFG_METHOD_DEFAULT) @@ -3718,7 +3849,7 @@ rtl8125_set_rx_csum(struct net_device *dev, else tp->cp_cmd &= ~RxChkSum; - RTL_W16(CPlusCmd, tp->cp_cmd); + RTL_W16(tp, CPlusCmd, tp->cp_cmd); spin_unlock_irqrestore(&tp->lock, flags); @@ -3756,19 +3887,20 @@ rtl8125_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; unsigned long flags; spin_lock_irqsave(&tp->lock, flags); tp->vlgrp = grp; if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3) { + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) { if (tp->vlgrp) { tp->rtl8125_rx_config |= (BIT_22 | BIT_23); - RTL_W32(RxConfig, RTL_R32(RxConfig) | (BIT_22 | BIT_23)) + RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | (BIT_22 | BIT_23)) } else { tp->rtl8125_rx_config &= ~(BIT_22 | BIT_23); - RTL_W32(RxConfig, RTL_R32(RxConfig) & ~(BIT_22 | BIT_23)) + RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~(BIT_22 | BIT_23)) } } spin_unlock_irqrestore(&tp->lock, flags); @@ -3855,6 +3987,9 @@ static netdev_features_t rtl8125_fix_features(struct net_device *dev, features &= ~NETIF_F_ALL_TSO; features &= ~NETIF_F_ALL_CSUM; } +#ifndef CONFIG_R8125_VLAN + features &= ~NETIF_F_ALL_CSUM; +#endif spin_unlock_irqrestore(&tp->lock, flags); return features; @@ -3864,10 +3999,9 @@ static int rtl8125_hw_set_features(struct net_device *dev, netdev_features_t features) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; u32 rx_config; - rx_config = RTL_R32(RxConfig); + rx_config = RTL_R32(tp, RxConfig); if (features & NETIF_F_RXALL) rx_config |= (AcceptErr | AcceptRunt); else @@ -3878,15 +4012,15 @@ static int rtl8125_hw_set_features(struct net_device *dev, else rx_config &= ~(BIT_22 | BIT_23); - RTL_W32(RxConfig, rx_config); + RTL_W32(tp, RxConfig, rx_config); if (features & NETIF_F_RXCSUM) tp->cp_cmd |= RxChkSum; else tp->cp_cmd &= ~RxChkSum; - RTL_W16(CPlusCmd, tp->cp_cmd); - RTL_R16(CPlusCmd); + RTL_W16(tp, CPlusCmd, tp->cp_cmd); + RTL_R16(tp, CPlusCmd); return 0; } @@ -3918,7 +4052,6 @@ static void rtl8125_gset_xmii(struct net_device *dev, ) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; u16 status; u8 autoneg, duplex; u32 speed = 0; @@ -3964,7 +4097,7 @@ static void rtl8125_gset_xmii(struct net_device *dev, autoneg = AUTONEG_DISABLE; } - status = RTL_R16(PHYstatus); + status = RTL_R16(tp, PHYstatus); if (status & LinkStatus) { /*link on*/ @@ -4054,7 +4187,7 @@ static void rtl8125_get_regs(struct net_device *dev, struct ethtool_regs *regs, data = (u8*)p + 256 * 2; for (i = 0; i < R8125_EPHY_REGS_SIZE/2; i++) { - *(u16*)data = rtl8125_ephy_read(ioaddr, i); + *(u16*)data = rtl8125_ephy_read(tp, i); data += 2; } data = (u8*)p + 256 * 3; @@ -4062,9 +4195,11 @@ static void rtl8125_get_regs(struct net_device *dev, struct ethtool_regs *regs, switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: default: for (i = 0; i < R8125_ERI_REGS_SIZE; i+=4) { - *(u32*)data = rtl8125_eri_read(ioaddr, i , 4, ERIAR_ExGMAC); + *(u32*)data = rtl8125_eri_read(tp, i , 4, ERIAR_ExGMAC); data += 4; } break; @@ -4132,7 +4267,6 @@ rtl8125_get_ethtool_stats(struct net_device *dev, u64 *data) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; struct rtl8125_counters *counters; dma_addr_t paddr; u32 cmd; @@ -4147,13 +4281,13 @@ rtl8125_get_ethtool_stats(struct net_device *dev, return; spin_lock_irqsave(&tp->lock, flags); - RTL_W32(CounterAddrHigh, (u64)paddr >> 32); + RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); cmd = (u64)paddr & DMA_BIT_MASK(32); - RTL_W32(CounterAddrLow, cmd); - RTL_W32(CounterAddrLow, cmd | CounterDump); + RTL_W32(tp, CounterAddrLow, cmd); + RTL_W32(tp, CounterAddrLow, cmd | CounterDump); WaitCnt = 0; - while (RTL_R32(CounterAddrLow) & CounterDump) { + while (RTL_R32(tp, CounterAddrLow) & CounterDump) { udelay(10); WaitCnt++; @@ -4217,6 +4351,8 @@ static int rtl_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: default: VPD_addr = 0xD2; VPD_data = 0xD4; @@ -4298,106 +4434,111 @@ static int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data) } #endif -#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) -static int -rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *eee) +static int rtl8125_enable_eee(struct rtl8125_private *tp) { - struct rtl8125_private *tp = netdev_priv(net); - void __iomem *ioaddr = tp->mmio_addr; - u32 lp, adv, supported = 0; - unsigned long flags; - u16 val; + int ret; + ret = 0; switch (tp->mcfg) { - default: - return -EOPNOTSUPP; - } + case CFG_METHOD_2: + case CFG_METHOD_3: + SetMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); + SetMcuAccessRegBit(tp, 0xEB62, (BIT_2|BIT_1)); - if (unlikely(tp->rtk_enable_diag)) - return -EBUSY; - - spin_lock_irqsave(&tp->lock, flags); - - rtl8125_mdio_write(tp, 0x1F, 0x0A5C); - val = rtl8125_mdio_read(tp, 0x12); - supported = mmd_eee_cap_to_ethtool_sup_t(val); - - rtl8125_mdio_write(tp, 0x1F, 0x0A5D); - val = rtl8125_mdio_read(tp, 0x10); - adv = mmd_eee_adv_to_ethtool_adv_t(val); - - val = rtl8125_mdio_read(tp, 0x11); - lp = mmd_eee_adv_to_ethtool_adv_t(val); - - val = rtl8125_eri_read(ioaddr, 0x1B0, 2, ERIAR_ExGMAC); - val &= BIT_1 | BIT_0; - - rtl8125_mdio_write(tp, 0x1F, 0x0000); - - spin_unlock_irqrestore(&tp->lock, flags); - - eee->eee_enabled = !!val; - eee->eee_active = !!(supported & adv & lp); - eee->supported = supported; - eee->advertised = adv; - eee->lp_advertised = lp; - - return 0; -} - -static int -rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *eee) -{ - struct rtl8125_private *tp = netdev_priv(net); - unsigned long flags; - u32 data; - - switch (tp->mcfg) { - default: - return -EOPNOTSUPP; - } - - if (unlikely(tp->rtk_enable_diag)) - return -EBUSY; - - spin_lock_irqsave(&tp->lock, flags); - - if (eee->eee_enabled) { - data = rtl8125_mac_ocp_read(tp, 0xE040); - data &= ~(BIT_1 | BIT_0); - rtl8125_mac_ocp_write(tp, 0xE040, data); - ClearEthPhyOcpBit(tp, 0xA432, BIT_4); - ClearEthPhyOcpBit(tp, 0xA5D0, (BIT_2 | BIT_1)); - ClearEthPhyOcpBit(tp, 0xA428, BIT_7); + SetEthPhyOcpBit(tp, 0xA432, BIT_4); + SetEthPhyOcpBit(tp, 0xA5D0, tp->eee_adv_t); ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); ClearEthPhyOcpBit(tp, 0xA428, BIT_7); ClearEthPhyOcpBit(tp, 0xA4A2, BIT_9); - } else { - data = rtl8125_mac_ocp_read(tp, 0xE040); - data &= ~(BIT_1 | BIT_0); - rtl8125_mac_ocp_write(tp, 0xE040, data); - ClearEthPhyOcpBit(tp, 0xA432, BIT_4); - ClearEthPhyOcpBit(tp, 0xA5D0, (BIT_2 | BIT_1)); - ClearEthPhyOcpBit(tp, 0xA428, BIT_7); + break; + case CFG_METHOD_4: + case CFG_METHOD_5: + SetMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); + + SetEthPhyOcpBit(tp, 0xA5D0, tp->eee_adv_t); ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); ClearEthPhyOcpBit(tp, 0xA428, BIT_7); ClearEthPhyOcpBit(tp, 0xA4A2, BIT_9); + break; + default: +// dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support EEE\n"); + ret = -EOPNOTSUPP; + break; } - rtl8125_mdio_write(tp, 0x1F, 0x0000); - data = rtl8125_mdio_read(tp, MII_BMCR); - data |= BMCR_RESET; - rtl8125_mdio_write(tp, MII_BMCR, data); + /*Advanced EEE*/ + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: + rtl8125_set_phy_mcu_patch_request(tp); + ClearMcuAccessRegBit(tp, 0xE052, BIT_0); + ClearEthPhyOcpBit(tp, 0xA442, BIT_12 | BIT_13); + ClearEthPhyOcpBit(tp, 0xA430, BIT_15); + rtl8125_clear_phy_mcu_patch_request(tp); + break; + } - spin_unlock_irqrestore(&tp->lock, flags); - - return 0; + return ret; +} + +static int rtl8125_disable_eee(struct rtl8125_private *tp) +{ + int ret; + + ret = 0; + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + ClearMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); + ClearMcuAccessRegBit(tp, 0xEB62, (BIT_2|BIT_1)); + + ClearEthPhyOcpBit(tp, 0xA432, BIT_4); + ClearEthPhyOcpBit(tp, 0xA5D0, (BIT_2 | BIT_1)); + ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); + + ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); + ClearEthPhyOcpBit(tp, 0xA428, BIT_7); + ClearEthPhyOcpBit(tp, 0xA4A2, BIT_9); + break; + case CFG_METHOD_4: + case CFG_METHOD_5: + ClearMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); + + ClearEthPhyOcpBit(tp, 0xA5D0, (BIT_2 | BIT_1)); + ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); + + ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); + ClearEthPhyOcpBit(tp, 0xA428, BIT_7); + ClearEthPhyOcpBit(tp, 0xA4A2, BIT_9); + break; + default: +// dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support EEE\n"); + ret = -EOPNOTSUPP; + break; + } + + /*Advanced EEE*/ + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: + rtl8125_set_phy_mcu_patch_request(tp); + ClearMcuAccessRegBit(tp, 0xE052, BIT_0); + ClearEthPhyOcpBit(tp, 0xA442, BIT_12 | BIT_13); + ClearEthPhyOcpBit(tp, 0xA430, BIT_15); + rtl8125_clear_phy_mcu_patch_request(tp); + break; + } + + return ret; } -#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) */ static int rtl_nway_reset(struct net_device *dev) { @@ -4405,11 +4546,13 @@ static int rtl_nway_reset(struct net_device *dev) unsigned long flags; int ret, bmcr; - if (unlikely(tp->rtk_enable_diag)) - return -EBUSY; - spin_lock_irqsave(&tp->lock, flags); + if (unlikely(tp->rtk_enable_diag)) { + spin_unlock_irqrestore(&tp->lock, flags); + return -EBUSY; + } + /* if autoneg is off, it's an error */ rtl8125_mdio_write(tp, 0x1F, 0x0000); bmcr = rtl8125_mdio_read(tp, MII_BMCR); @@ -4427,6 +4570,81 @@ static int rtl_nway_reset(struct net_device *dev) return ret; } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) +static int +rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *eee) +{ + struct rtl8125_private *tp = netdev_priv(net); + u32 lp, adv, supported = 0; + unsigned long flags; + u16 val; + + spin_lock_irqsave(&tp->lock, flags); + + if (unlikely(tp->rtk_enable_diag)) { + spin_unlock_irqrestore(&tp->lock, flags); + return -EBUSY; + } + + /* Get Supported EEE */ + val = mdio_direct_read_phy_ocp(tp, 0xA5C4); + supported = mmd_eee_cap_to_ethtool_sup_t(val); + + /* Get advertisement EEE */ + val = mdio_direct_read_phy_ocp(tp, 0xA5D0); + adv = mmd_eee_adv_to_ethtool_adv_t(val); + + /* Get LP advertisement EEE */ + val = mdio_direct_read_phy_ocp(tp, 0xA5D2); + lp = mmd_eee_adv_to_ethtool_adv_t(val); + + val = rtl8125_mac_ocp_read(tp, 0xE040); + val &= BIT_1 | BIT_0; + + spin_unlock_irqrestore(&tp->lock, flags); + + eee->eee_enabled = !!val; + eee->eee_active = !!(supported & adv & lp); + eee->supported = supported; + eee->advertised = adv; + eee->lp_advertised = lp; + + return 0; +} + +static int +rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *eee) +{ + struct rtl8125_private *tp = netdev_priv(net); + unsigned long flags; + + if (!HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + return -EOPNOTSUPP; + + spin_lock_irqsave(&tp->lock, flags); + + if (unlikely(tp->rtk_enable_diag)) { + spin_unlock_irqrestore(&tp->lock, flags); + return -EBUSY; + } + + tp->eee_enabled = eee->eee_enabled; + tp->eee_adv_t = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); + + if (tp->eee_enabled) { + rtl8125_enable_eee(tp); + } else { + rtl8125_disable_eee(tp); + } + + spin_unlock_irqrestore(&tp->lock, flags); + + rtl_nway_reset(net); + + return 0; +} +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) */ + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) static const struct ethtool_ops rtl8125_ethtool_ops = { .get_drvinfo = rtl8125_get_drvinfo, @@ -4481,88 +4699,6 @@ static const struct ethtool_ops rtl8125_ethtool_ops = { }; #endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) -static int rtl8125_enable_eee(struct rtl8125_private *tp) -{ - int ret; - - ret = 0; - switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: - SetMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); - SetMcuAccessRegBit(tp, 0xEB62, (BIT_2|BIT_1)); - - SetEthPhyOcpBit(tp, 0xA432, BIT_4); - SetEthPhyOcpBit(tp, 0xA5D0, (BIT_2 | BIT_1)); - ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); - - ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); - SetEthPhyOcpBit(tp, 0xA4A2, BIT_9); - SetEthPhyOcpBit(tp, 0xA428, BIT_7); - break; - - default: -// dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support EEE\n"); - ret = -EOPNOTSUPP; - break; - } - - /*Advanced EEE*/ - switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: - rtl8125_set_phy_mcu_patch_request(tp); - SetMcuAccessRegBit(tp, 0xE052, BIT_0); - ClearEthPhyOcpBit(tp, 0xA442, BIT_12 | BIT_13); - ClearEthPhyOcpBit(tp, 0xA430, BIT_15); - rtl8125_clear_phy_mcu_patch_request(tp); - break; - } - - return ret; -} - -static int rtl8125_disable_eee(struct rtl8125_private *tp) -{ - int ret; - - ret = 0; - switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: - ClearMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); - ClearMcuAccessRegBit(tp, 0xEB62, (BIT_2|BIT_1)); - - ClearEthPhyOcpBit(tp, 0xA432, BIT_4); - ClearEthPhyOcpBit(tp, 0xA5D0, (BIT_2 | BIT_1)); - ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); - - ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); - ClearEthPhyOcpBit(tp, 0xA428, BIT_7); - ClearEthPhyOcpBit(tp, 0xA4A2, BIT_9); - break; - - default: -// dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support EEE\n"); - ret = -EOPNOTSUPP; - break; - } - - /*Advanced EEE*/ - switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: - rtl8125_set_phy_mcu_patch_request(tp); - ClearMcuAccessRegBit(tp, 0xE052, BIT_0); - ClearEthPhyOcpBit(tp, 0xA442, BIT_12 | BIT_13); - ClearEthPhyOcpBit(tp, 0xA430, BIT_15); - rtl8125_clear_phy_mcu_patch_request(tp); - break; - } - - return ret; -} - #if 0 static int rtl8125_enable_green_feature(struct rtl8125_private *tp) @@ -4573,6 +4709,8 @@ static int rtl8125_enable_green_feature(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: mdio_direct_write_phy_ocp(tp, 0xA436, 0x8011); SetEthPhyOcpBit(tp, 0xA438, BIT_15); rtl8125_mdio_write(tp, 0x00, 0x9200); @@ -4593,6 +4731,8 @@ static int rtl8125_disable_green_feature(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: mdio_direct_write_phy_ocp(tp, 0xA436, 0x8011); ClearEthPhyOcpBit(tp, 0xA438, BIT_15); rtl8125_mdio_write(tp, 0x00, 0x9200); @@ -4607,12 +4747,12 @@ static int rtl8125_disable_green_feature(struct rtl8125_private *tp) #endif -static void rtl8125_get_mac_version(struct rtl8125_private *tp, void __iomem *ioaddr) +static void rtl8125_get_mac_version(struct rtl8125_private *tp) { u32 reg,val32; u32 ICVerID; - val32 = RTL_R32(TxConfig); + val32 = RTL_R32(tp, TxConfig); reg = val32 & 0x7c800000; ICVerID = val32 & 0x00700000; @@ -4627,6 +4767,18 @@ static void rtl8125_get_mac_version(struct rtl8125_private *tp, void __iomem *io tp->HwIcVerUnknown = TRUE; } + tp->efuse_ver = EFUSE_SUPPORT_V4; + break; + case 0x64000000: + if (ICVerID == 0x00000000) { + tp->mcfg = CFG_METHOD_4; + } else if (ICVerID == 0x100000) { + tp->mcfg = CFG_METHOD_5; + } else { + tp->mcfg = CFG_METHOD_5; + tp->HwIcVerUnknown = TRUE; + } + tp->efuse_ver = EFUSE_SUPPORT_V4; break; default: @@ -4656,25 +4808,21 @@ rtl8125_print_mac_version(struct rtl8125_private *tp) static void rtl8125_tally_counter_addr_fill(struct rtl8125_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - if (!tp->tally_paddr) return; - RTL_W32(CounterAddrHigh, (u64)tp->tally_paddr >> 32); - RTL_W32(CounterAddrLow, (u64)tp->tally_paddr & (DMA_BIT_MASK(32))); + RTL_W32(tp, CounterAddrHigh, (u64)tp->tally_paddr >> 32); + RTL_W32(tp, CounterAddrLow, (u64)tp->tally_paddr & (DMA_BIT_MASK(32))); } static void rtl8125_tally_counter_clear(struct rtl8125_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - if (!tp->tally_paddr) return; - RTL_W32(CounterAddrHigh, (u64)tp->tally_paddr >> 32); - RTL_W32(CounterAddrLow, ((u64)tp->tally_paddr & (DMA_BIT_MASK(32))) | CounterReset); + RTL_W32(tp, CounterAddrHigh, (u64)tp->tally_paddr >> 32); + RTL_W32(tp, CounterAddrLow, ((u64)tp->tally_paddr & (DMA_BIT_MASK(32))) | CounterReset); } static void @@ -4682,6 +4830,12 @@ rtl8125_clear_phy_ups_reg(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); + switch (tp->mcfg) { + case CFG_METHOD_4: + case CFG_METHOD_5: + ClearEthPhyOcpBit(tp, 0xA466, BIT_0); + break; + }; ClearEthPhyOcpBit(tp, 0xA468, BIT_3 | BIT_1); } @@ -4691,7 +4845,9 @@ rtl8125_is_ups_resume(struct net_device *dev) struct rtl8125_private *tp = netdev_priv(dev); if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3) + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) return (rtl8125_mac_ocp_read(tp, 0xD42C) & BIT_8); return 0; @@ -4703,7 +4859,9 @@ rtl8125_clear_ups_resume_bit(struct net_device *dev) struct rtl8125_private *tp = netdev_priv(dev); if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3) + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) rtl8125_mac_ocp_write(tp, 0xD408, rtl8125_mac_ocp_read(tp, 0xD408) & ~(BIT_8)); } @@ -4715,7 +4873,9 @@ rtl8125_wait_phy_ups_resume(struct net_device *dev, u16 PhyState) int i=0; if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3) { + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) { do { TmpPhyState = mdio_direct_read_phy_ocp(tp, 0xA420); TmpPhyState &= 0x7; @@ -4732,20 +4892,16 @@ rtl8125_wait_phy_ups_resume(struct net_device *dev, u16 PhyState) void rtl8125_enable_now_is_oob(struct rtl8125_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - if ( tp->HwSuppNowIsOobVer == 1 ) { - RTL_W8(MCUCmd_reg, RTL_R8(MCUCmd_reg) | Now_is_oob); + RTL_W8(tp, MCUCmd_reg, RTL_R8(tp, MCUCmd_reg) | Now_is_oob); } } void rtl8125_disable_now_is_oob(struct rtl8125_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - if ( tp->HwSuppNowIsOobVer == 1 ) { - RTL_W8(MCUCmd_reg, RTL_R8(MCUCmd_reg) & ~Now_is_oob); + RTL_W8(tp, MCUCmd_reg, RTL_R8(tp, MCUCmd_reg) & ~Now_is_oob); } } @@ -4753,14 +4909,15 @@ static void rtl8125_exit_oob(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; u16 data16; - RTL_W32(RxConfig, RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys)); + RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys)); switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_dash2_disable_txrx(dev); break; } @@ -4780,6 +4937,8 @@ rtl8125_exit_oob(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xC0BC, 0x00FF); break; } @@ -4790,6 +4949,8 @@ rtl8125_exit_oob(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_disable_now_is_oob(tp); data16 = rtl8125_mac_ocp_read(tp, 0xE8DE) & ~BIT_14; @@ -4797,7 +4958,7 @@ rtl8125_exit_oob(struct net_device *dev) rtl8125_wait_ll_share_fifo_ready(dev); rtl8125_mac_ocp_write(tp, 0xC0AA, 0x07D0); - rtl8125_mac_ocp_write(tp, 0xC0A6, 0x0150); + rtl8125_mac_ocp_write(tp, 0xC0A6, 0x01B5); rtl8125_mac_ocp_write(tp, 0xC01E, 0x5555); rtl8125_wait_ll_share_fifo_ready(dev); @@ -4808,6 +4969,8 @@ rtl8125_exit_oob(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: if (rtl8125_is_ups_resume(dev)) { rtl8125_wait_phy_ups_resume(dev, 2); rtl8125_clear_ups_resume_bit(dev); @@ -4823,14 +4986,15 @@ void rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_enable_cfg9346_write(tp); - RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0); - RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); + RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); rtl8125_disable_cfg9346_write(tp); break; } @@ -4838,6 +5002,8 @@ rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xFC38, 0x0000); break; } @@ -4845,6 +5011,8 @@ rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xFC28, 0x0000); rtl8125_mac_ocp_write(tp, 0xFC2A, 0x0000); rtl8125_mac_ocp_write(tp, 0xFC2C, 0x0000); @@ -4859,124 +5027,102 @@ rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev) } } +static void +rtl8125_set_mac_mcu_8125a_1(struct net_device *dev) +{ + rtl8125_hw_disable_mac_mcu_bps(dev); +} + static void rtl8125_set_mac_mcu_8125a_2(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); + u16 i; + static const u16 mcu_patch_code_8125a_2[] = { + 0xE008, 0xE01E, 0xE02E, 0xE054, 0xE057, 0xE059, 0xE0C2, 0xE0CB, 0x9996, + 0x49D1, 0xF005, 0x49D4, 0xF10A, 0x49D8, 0xF108, 0xC00F, 0x7100, 0x209C, + 0x249C, 0xC009, 0x9900, 0xE004, 0xC006, 0x1900, 0x9900, 0xC602, 0xBE00, + 0x5A48, 0xE0C2, 0x0004, 0xE10A, 0xC60F, 0x73C4, 0x49B3, 0xF106, 0x73C2, + 0xC608, 0xB406, 0xC609, 0xFF80, 0xC605, 0xB406, 0xC605, 0xFF80, 0x0544, + 0x0568, 0xE906, 0xCDE8, 0xC724, 0xC624, 0x9EE2, 0x1E01, 0x9EE0, 0x76E0, + 0x49E0, 0xF1FE, 0x76E6, 0x486D, 0x4868, 0x9EE4, 0x1E03, 0x9EE0, 0x76E0, + 0x49E0, 0xF1FE, 0xC615, 0x9EE2, 0x1E01, 0x9EE0, 0x76E0, 0x49E0, 0xF1FE, + 0x76E6, 0x486F, 0x9EE4, 0x1E03, 0x9EE0, 0x76E0, 0x49E0, 0xF1FE, 0x7196, + 0xC702, 0xBF00, 0x5A44, 0xEB0E, 0x0070, 0x00C3, 0x1BC0, 0xC602, 0xBE00, + 0x0E26, 0xC602, 0xBE00, 0x0EBA, 0x1501, 0xF02A, 0x1500, 0xF15D, 0xC661, + 0x75C8, 0x49D5, 0xF00A, 0x49D6, 0xF008, 0x49D7, 0xF006, 0x49D8, 0xF004, + 0x75D2, 0x49D9, 0xF150, 0xC553, 0x77A0, 0x75C8, 0x4855, 0x4856, 0x4857, + 0x4858, 0x48DA, 0x48DB, 0x49FE, 0xF002, 0x485A, 0x49FF, 0xF002, 0x485B, + 0x9DC8, 0x75D2, 0x4859, 0x9DD2, 0xC643, 0x75C0, 0x49D4, 0xF033, 0x49D0, + 0xF137, 0xE030, 0xC63A, 0x75C8, 0x49D5, 0xF00E, 0x49D6, 0xF00C, 0x49D7, + 0xF00A, 0x49D8, 0xF008, 0x75D2, 0x49D9, 0xF005, 0xC62E, 0x75C0, 0x49D7, + 0xF125, 0xC528, 0x77A0, 0xC627, 0x75C8, 0x4855, 0x4856, 0x4857, 0x4858, + 0x48DA, 0x48DB, 0x49FE, 0xF002, 0x485A, 0x49FF, 0xF002, 0x485B, 0x9DC8, + 0x75D2, 0x4859, 0x9DD2, 0xC616, 0x75C0, 0x4857, 0x9DC0, 0xC613, 0x75C0, + 0x49DA, 0xF003, 0x49D0, 0xF107, 0xC60B, 0xC50E, 0x48D9, 0x9DC0, 0x4859, + 0x9DC0, 0xC608, 0xC702, 0xBF00, 0x3AE0, 0xE860, 0xB400, 0xB5D4, 0xE908, + 0xE86C, 0x1200, 0xC409, 0x6780, 0x48F1, 0x8F80, 0xC404, 0xC602, 0xBE00, + 0x10AA, 0xC010, 0xEA7C, 0xC602, 0xBE00, 0x0000 + }; rtl8125_hw_disable_mac_mcu_bps(dev); - rtl8125_mac_ocp_write(tp, 0xF800, 0xE008); - rtl8125_mac_ocp_write(tp, 0xF802, 0xE01E); - rtl8125_mac_ocp_write(tp, 0xF804, 0xE02E); - rtl8125_mac_ocp_write(tp, 0xF806, 0xE054); - rtl8125_mac_ocp_write(tp, 0xF808, 0xE057); - rtl8125_mac_ocp_write(tp, 0xF80A, 0xE059); - rtl8125_mac_ocp_write(tp, 0xF80C, 0xE05B); - rtl8125_mac_ocp_write(tp, 0xF80E, 0xE05D); - rtl8125_mac_ocp_write(tp, 0xF810, 0x9996); - rtl8125_mac_ocp_write(tp, 0xF812, 0x49D1); - rtl8125_mac_ocp_write(tp, 0xF814, 0xF005); - rtl8125_mac_ocp_write(tp, 0xF816, 0x49D4); - rtl8125_mac_ocp_write(tp, 0xF818, 0xF10A); - rtl8125_mac_ocp_write(tp, 0xF81A, 0x49D8); - rtl8125_mac_ocp_write(tp, 0xF81C, 0xF108); - rtl8125_mac_ocp_write(tp, 0xF81E, 0xC00F); - rtl8125_mac_ocp_write(tp, 0xF820, 0x7100); - rtl8125_mac_ocp_write(tp, 0xF822, 0x209C); - rtl8125_mac_ocp_write(tp, 0xF824, 0x249C); - rtl8125_mac_ocp_write(tp, 0xF826, 0xC009); - rtl8125_mac_ocp_write(tp, 0xF828, 0x9900); - rtl8125_mac_ocp_write(tp, 0xF82A, 0xE004); - rtl8125_mac_ocp_write(tp, 0xF82C, 0xC006); - rtl8125_mac_ocp_write(tp, 0xF82E, 0x1900); - rtl8125_mac_ocp_write(tp, 0xF830, 0x9900); - rtl8125_mac_ocp_write(tp, 0xF832, 0xC602); - rtl8125_mac_ocp_write(tp, 0xF834, 0xBE00); - rtl8125_mac_ocp_write(tp, 0xF836, 0x5A48); - rtl8125_mac_ocp_write(tp, 0xF838, 0xE0C2); - rtl8125_mac_ocp_write(tp, 0xF83A, 0x0004); - rtl8125_mac_ocp_write(tp, 0xF83C, 0xE10A); - rtl8125_mac_ocp_write(tp, 0xF83E, 0xC60F); - rtl8125_mac_ocp_write(tp, 0xF840, 0x73C4); - rtl8125_mac_ocp_write(tp, 0xF842, 0x49B3); - rtl8125_mac_ocp_write(tp, 0xF844, 0xF106); - rtl8125_mac_ocp_write(tp, 0xF846, 0x73C2); - rtl8125_mac_ocp_write(tp, 0xF848, 0xC608); - rtl8125_mac_ocp_write(tp, 0xF84A, 0xB406); - rtl8125_mac_ocp_write(tp, 0xF84C, 0xC609); - rtl8125_mac_ocp_write(tp, 0xF84E, 0xFF80); - rtl8125_mac_ocp_write(tp, 0xF850, 0xC605); - rtl8125_mac_ocp_write(tp, 0xF852, 0xB406); - rtl8125_mac_ocp_write(tp, 0xF854, 0xC605); - rtl8125_mac_ocp_write(tp, 0xF856, 0xFF80); - rtl8125_mac_ocp_write(tp, 0xF858, 0x0544); - rtl8125_mac_ocp_write(tp, 0xF85A, 0x0568); - rtl8125_mac_ocp_write(tp, 0xF85C, 0xE906); - rtl8125_mac_ocp_write(tp, 0xF85E, 0xCDE8); - rtl8125_mac_ocp_write(tp, 0xF860, 0xC724); - rtl8125_mac_ocp_write(tp, 0xF862, 0xC624); - rtl8125_mac_ocp_write(tp, 0xF864, 0x9EE2); - rtl8125_mac_ocp_write(tp, 0xF866, 0x1E01); - rtl8125_mac_ocp_write(tp, 0xF868, 0x9EE0); - rtl8125_mac_ocp_write(tp, 0xF86A, 0x76E0); - rtl8125_mac_ocp_write(tp, 0xF86C, 0x49E0); - rtl8125_mac_ocp_write(tp, 0xF86E, 0xF1FE); - rtl8125_mac_ocp_write(tp, 0xF870, 0x76E6); - rtl8125_mac_ocp_write(tp, 0xF872, 0x486D); - rtl8125_mac_ocp_write(tp, 0xF874, 0x4868); - rtl8125_mac_ocp_write(tp, 0xF876, 0x9EE4); - rtl8125_mac_ocp_write(tp, 0xF878, 0x1E03); - rtl8125_mac_ocp_write(tp, 0xF87A, 0x9EE0); - rtl8125_mac_ocp_write(tp, 0xF87C, 0x76E0); - rtl8125_mac_ocp_write(tp, 0xF87E, 0x49E0); - rtl8125_mac_ocp_write(tp, 0xF880, 0xF1FE); - rtl8125_mac_ocp_write(tp, 0xF882, 0xC615); - rtl8125_mac_ocp_write(tp, 0xF884, 0x9EE2); - rtl8125_mac_ocp_write(tp, 0xF886, 0x1E01); - rtl8125_mac_ocp_write(tp, 0xF888, 0x9EE0); - rtl8125_mac_ocp_write(tp, 0xF88A, 0x76E0); - rtl8125_mac_ocp_write(tp, 0xF88C, 0x49E0); - rtl8125_mac_ocp_write(tp, 0xF88E, 0xF1FE); - rtl8125_mac_ocp_write(tp, 0xF890, 0x76E6); - rtl8125_mac_ocp_write(tp, 0xF892, 0x486F); - rtl8125_mac_ocp_write(tp, 0xF894, 0x9EE4); - rtl8125_mac_ocp_write(tp, 0xF896, 0x1E03); - rtl8125_mac_ocp_write(tp, 0xF898, 0x9EE0); - rtl8125_mac_ocp_write(tp, 0xF89A, 0x76E0); - rtl8125_mac_ocp_write(tp, 0xF89C, 0x49E0); - rtl8125_mac_ocp_write(tp, 0xF89E, 0xF1FE); - rtl8125_mac_ocp_write(tp, 0xF8A0, 0x7196); - rtl8125_mac_ocp_write(tp, 0xF8A2, 0xC702); - rtl8125_mac_ocp_write(tp, 0xF8A4, 0xBF00); - rtl8125_mac_ocp_write(tp, 0xF8A6, 0x5A44); - rtl8125_mac_ocp_write(tp, 0xF8A8, 0xEB0E); - rtl8125_mac_ocp_write(tp, 0xF8AA, 0x0070); - rtl8125_mac_ocp_write(tp, 0xF8AC, 0x00C3); - rtl8125_mac_ocp_write(tp, 0xF8AE, 0x1BC0); - rtl8125_mac_ocp_write(tp, 0xF8B0, 0xC602); - rtl8125_mac_ocp_write(tp, 0xF8B2, 0xBE00); - rtl8125_mac_ocp_write(tp, 0xF8B4, 0x0E26); - rtl8125_mac_ocp_write(tp, 0xF8B6, 0xC602); - rtl8125_mac_ocp_write(tp, 0xF8B8, 0xBE00); - rtl8125_mac_ocp_write(tp, 0xF8BA, 0x0EBA); - rtl8125_mac_ocp_write(tp, 0xF8BC, 0xC602); - rtl8125_mac_ocp_write(tp, 0xF8BE, 0xBE00); - rtl8125_mac_ocp_write(tp, 0xF8C0, 0x0000); - rtl8125_mac_ocp_write(tp, 0xF8C2, 0xC602); - rtl8125_mac_ocp_write(tp, 0xF8C4, 0xBE00); - rtl8125_mac_ocp_write(tp, 0xF8C6, 0x0000); - rtl8125_mac_ocp_write(tp, 0xF8C8, 0xC602); - rtl8125_mac_ocp_write(tp, 0xF8CA, 0xBE00); - rtl8125_mac_ocp_write(tp, 0xF8CC, 0x0000); + for (i = 0; i < ARRAY_SIZE(mcu_patch_code_8125a_2); i++) { + rtl8125_mac_ocp_write(tp, 0xF800 + i * 2, mcu_patch_code_8125a_2[i]); + } rtl8125_mac_ocp_write(tp, 0xFC26, 0x8000); rtl8125_mac_ocp_write(tp, 0xFC2A, 0x0540); rtl8125_mac_ocp_write(tp, 0xFC2E, 0x0E24); rtl8125_mac_ocp_write(tp, 0xFC30, 0x0EB8); + rtl8125_mac_ocp_write(tp, 0xFC32, 0x3A5C); + rtl8125_mac_ocp_write(tp, 0xFC34, 0x10A8); - rtl8125_mac_ocp_write(tp, 0xFC48, 0x001A); + rtl8125_mac_ocp_write(tp, 0xFC48, 0x007A); +} + +static void +rtl8125_set_mac_mcu_8125b_1(struct net_device *dev) +{ + rtl8125_hw_disable_mac_mcu_bps(dev); +} + +static void +rtl8125_set_mac_mcu_8125b_2(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + u16 i; + static const u16 mcu_patch_code_8125b_2[] = { + 0xE008, 0xE013, 0xE01E, 0xE02F, 0xE035, 0xE04F, 0xE053, 0xE055, 0x740A, + 0x4846, 0x4847, 0x9C0A, 0xC607, 0x74C0, 0x48C6, 0x9CC0, 0xC602, 0xBE00, + 0x13F0, 0xE054, 0x72CA, 0x4826, 0x4827, 0x9ACA, 0xC607, 0x72C0, 0x48A6, + 0x9AC0, 0xC602, 0xBE00, 0x081C, 0xE054, 0xC60F, 0x74C4, 0x49CC, 0xF109, + 0xC60C, 0x74CA, 0x48C7, 0x9CCA, 0xC609, 0x74C0, 0x4846, 0x9CC0, 0xC602, + 0xBE00, 0x2494, 0xE092, 0xE0C0, 0xE054, 0x7420, 0x48C0, 0x9C20, 0x7444, + 0xC602, 0xBE00, 0x12DC, 0x733A, 0x21B5, 0x25BC, 0x1304, 0xF111, 0x1B12, + 0x1D2A, 0x3168, 0x3ADA, 0x31AB, 0x1A00, 0x9AC0, 0x1300, 0xF1FB, 0x7620, + 0x236E, 0x276F, 0x1A3C, 0x22A1, 0x41B5, 0x9EE2, 0x76E4, 0x486F, 0x9EE4, + 0xC602, 0xBE00, 0x4A26, 0x733A, 0x49BB, 0xC602, 0xBE00, 0x47A2, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000 + }; + + rtl8125_hw_disable_mac_mcu_bps(dev); + + for (i = 0; i < ARRAY_SIZE(mcu_patch_code_8125b_2); i++) { + rtl8125_mac_ocp_write(tp, 0xF800 + i * 2, mcu_patch_code_8125b_2[i]); + } + + rtl8125_mac_ocp_write(tp, 0xFC26, 0x8000); + + rtl8125_mac_ocp_write(tp, 0xFC28, 0x13E6); + rtl8125_mac_ocp_write(tp, 0xFC2A, 0x0812); + rtl8125_mac_ocp_write(tp, 0xFC2C, 0x248C); + rtl8125_mac_ocp_write(tp, 0xFC2E, 0x12DA); + rtl8125_mac_ocp_write(tp, 0xFC30, 0x4A20); + rtl8125_mac_ocp_write(tp, 0xFC32, 0x47A0); + + rtl8125_mac_ocp_write(tp, 0xFC48, 0x003F); } static void @@ -4988,11 +5134,17 @@ rtl8125_hw_mac_mcu_config(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: - rtl8125_hw_disable_mac_mcu_bps(dev); + rtl8125_set_mac_mcu_8125a_1(dev); break; case CFG_METHOD_3: rtl8125_set_mac_mcu_8125a_2(dev); break; + case CFG_METHOD_4: + rtl8125_set_mac_mcu_8125b_1(dev); + break; + case CFG_METHOD_5: + rtl8125_set_mac_mcu_8125b_2(dev); + break; } } @@ -5000,17 +5152,18 @@ static void rtl8125_hw_init(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; u32 csi_tmp; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_enable_cfg9346_write(tp); - RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0); - RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); + RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); rtl8125_disable_cfg9346_write(tp); - RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7); + RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7); break; } @@ -5018,6 +5171,8 @@ rtl8125_hw_init(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xD40A, rtl8125_mac_ocp_read( tp, 0xD40A) & ~(BIT_4)); break; } @@ -5025,7 +5180,10 @@ rtl8125_hw_init(struct net_device *dev) rtl8125_hw_mac_mcu_config(dev); /*disable ocp phy power saving*/ - if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3) + if (tp->mcfg == CFG_METHOD_2 || + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) rtl8125_disable_ocp_phy_power_saving(dev); //Set PCIE uncorrectable error status mask pcie 0x108 @@ -5041,50 +5199,118 @@ static void rtl8125_hw_ephy_config(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->mcfg) { case CFG_METHOD_2: - rtl8125_ephy_write(ioaddr, 0x01, 0xA812); - rtl8125_ephy_write(ioaddr, 0x09, 0x520C); - rtl8125_ephy_write(ioaddr, 0x04, 0xD000); - rtl8125_ephy_write(ioaddr, 0x0D, 0xF702); - rtl8125_ephy_write(ioaddr, 0x0A, 0x8653); - rtl8125_ephy_write(ioaddr, 0x06, 0x001E); - rtl8125_ephy_write(ioaddr, 0x08, 0x3595); - rtl8125_ephy_write(ioaddr, 0x20, 0x9455); - rtl8125_ephy_write(ioaddr, 0x21, 0x99FF); - rtl8125_ephy_write(ioaddr, 0x02, 0x6046); - rtl8125_ephy_write(ioaddr, 0x29, 0xFE00); - rtl8125_ephy_write(ioaddr, 0x23, 0xAB62); + rtl8125_ephy_write(tp, 0x01, 0xA812); + rtl8125_ephy_write(tp, 0x09, 0x520C); + rtl8125_ephy_write(tp, 0x04, 0xD000); + rtl8125_ephy_write(tp, 0x0D, 0xF702); + rtl8125_ephy_write(tp, 0x0A, 0x8653); + rtl8125_ephy_write(tp, 0x06, 0x001E); + rtl8125_ephy_write(tp, 0x08, 0x3595); + rtl8125_ephy_write(tp, 0x20, 0x9455); + rtl8125_ephy_write(tp, 0x21, 0x99FF); + rtl8125_ephy_write(tp, 0x02, 0x6046); + rtl8125_ephy_write(tp, 0x29, 0xFE00); + rtl8125_ephy_write(tp, 0x23, 0xAB62); - rtl8125_ephy_write(ioaddr, 0x41, 0xA80C); - rtl8125_ephy_write(ioaddr, 0x49, 0x520C); - rtl8125_ephy_write(ioaddr, 0x44, 0xD000); - rtl8125_ephy_write(ioaddr, 0x4D, 0xF702); - rtl8125_ephy_write(ioaddr, 0x4A, 0x8653); - rtl8125_ephy_write(ioaddr, 0x46, 0x001E); - rtl8125_ephy_write(ioaddr, 0x48, 0x3595); - rtl8125_ephy_write(ioaddr, 0x60, 0x9455); - rtl8125_ephy_write(ioaddr, 0x61, 0x99FF); - rtl8125_ephy_write(ioaddr, 0x42, 0x6046); - rtl8125_ephy_write(ioaddr, 0x69, 0xFE00); - rtl8125_ephy_write(ioaddr, 0x63, 0xAB62); + rtl8125_ephy_write(tp, 0x41, 0xA80C); + rtl8125_ephy_write(tp, 0x49, 0x520C); + rtl8125_ephy_write(tp, 0x44, 0xD000); + rtl8125_ephy_write(tp, 0x4D, 0xF702); + rtl8125_ephy_write(tp, 0x4A, 0x8653); + rtl8125_ephy_write(tp, 0x46, 0x001E); + rtl8125_ephy_write(tp, 0x48, 0x3595); + rtl8125_ephy_write(tp, 0x60, 0x9455); + rtl8125_ephy_write(tp, 0x61, 0x99FF); + rtl8125_ephy_write(tp, 0x42, 0x6046); + rtl8125_ephy_write(tp, 0x69, 0xFE00); + rtl8125_ephy_write(tp, 0x63, 0xAB62); break; case CFG_METHOD_3: - rtl8125_ephy_write(ioaddr, 0x04, 0xD000); - rtl8125_ephy_write(ioaddr, 0x0A, 0x8653); - rtl8125_ephy_write(ioaddr, 0x23, 0xAB66); - rtl8125_ephy_write(ioaddr, 0x20, 0x9455); - rtl8125_ephy_write(ioaddr, 0x21, 0x99FF); - rtl8125_ephy_write(ioaddr, 0x29, 0xFE04); + rtl8125_ephy_write(tp, 0x04, 0xD000); + rtl8125_ephy_write(tp, 0x0A, 0x8653); + rtl8125_ephy_write(tp, 0x23, 0xAB66); + rtl8125_ephy_write(tp, 0x20, 0x9455); + rtl8125_ephy_write(tp, 0x21, 0x99FF); + rtl8125_ephy_write(tp, 0x29, 0xFE04); - rtl8125_ephy_write(ioaddr, 0x44, 0xD000); - rtl8125_ephy_write(ioaddr, 0x4A, 0x8653); - rtl8125_ephy_write(ioaddr, 0x63, 0xAB66); - rtl8125_ephy_write(ioaddr, 0x60, 0x9455); - rtl8125_ephy_write(ioaddr, 0x61, 0x99FF); - rtl8125_ephy_write(ioaddr, 0x69, 0xFE04); + rtl8125_ephy_write(tp, 0x44, 0xD000); + rtl8125_ephy_write(tp, 0x4A, 0x8653); + rtl8125_ephy_write(tp, 0x63, 0xAB66); + rtl8125_ephy_write(tp, 0x60, 0x9455); + rtl8125_ephy_write(tp, 0x61, 0x99FF); + rtl8125_ephy_write(tp, 0x69, 0xFE04); + + ClearAndSetPCIePhyBit(tp, + 0x2A, + (BIT_14 | BIT_13 | BIT_12), + (BIT_13 | BIT_12) + ); + ClearPCIePhyBit(tp, 0x19, BIT_6); + SetPCIePhyBit(tp, 0x1B, (BIT_11 | BIT_10 | BIT_9)); + ClearPCIePhyBit(tp, 0x1B, (BIT_14 | BIT_13 | BIT_12)); + rtl8125_ephy_write(tp, 0x02, 0x6042); + rtl8125_ephy_write(tp, 0x06, 0x0014); + + ClearAndSetPCIePhyBit(tp, + 0x6A, + (BIT_14 | BIT_13 | BIT_12), + (BIT_13 | BIT_12) + ); + ClearPCIePhyBit(tp, 0x59, BIT_6); + SetPCIePhyBit(tp, 0x5B, (BIT_11 | BIT_10 | BIT_9)); + ClearPCIePhyBit(tp, 0x5B, (BIT_14 | BIT_13 | BIT_12)); + rtl8125_ephy_write(tp, 0x42, 0x6042); + rtl8125_ephy_write(tp, 0x46, 0x0014); + break; + case CFG_METHOD_4: + rtl8125_ephy_write(tp, 0x06, 0x001F); + rtl8125_ephy_write(tp, 0x0A, 0xB66B); + rtl8125_ephy_write(tp, 0x01, 0xA852); + rtl8125_ephy_write(tp, 0x24, 0x0008); + rtl8125_ephy_write(tp, 0x2F, 0x6052); + rtl8125_ephy_write(tp, 0x0D, 0xF716); + rtl8125_ephy_write(tp, 0x20, 0xD477); + rtl8125_ephy_write(tp, 0x21, 0x4477); + rtl8125_ephy_write(tp, 0x22, 0x0013); + rtl8125_ephy_write(tp, 0x23, 0xBB66); + rtl8125_ephy_write(tp, 0x0B, 0xA909); + rtl8125_ephy_write(tp, 0x29, 0xFF04); + rtl8125_ephy_write(tp, 0x1B, 0x1EA0); + + rtl8125_ephy_write(tp, 0x46, 0x001F); + rtl8125_ephy_write(tp, 0x4A, 0xB66B); + rtl8125_ephy_write(tp, 0x41, 0xA84A); + rtl8125_ephy_write(tp, 0x64, 0x000C); + rtl8125_ephy_write(tp, 0x6F, 0x604A); + rtl8125_ephy_write(tp, 0x4D, 0xF716); + rtl8125_ephy_write(tp, 0x60, 0xD477); + rtl8125_ephy_write(tp, 0x61, 0x4477); + rtl8125_ephy_write(tp, 0x62, 0x0013); + rtl8125_ephy_write(tp, 0x63, 0xBB66); + rtl8125_ephy_write(tp, 0x4B, 0xA909); + rtl8125_ephy_write(tp, 0x69, 0xFF04); + rtl8125_ephy_write(tp, 0x5B, 0x1EA0); + break; + case CFG_METHOD_5: + rtl8125_ephy_write(tp, 0x0B, 0xA908); + rtl8125_ephy_write(tp, 0x1E, 0x20EB); + + rtl8125_ephy_write(tp, 0x4B, 0xA908); + rtl8125_ephy_write(tp, 0x5E, 0x20EB); + + ClearAndSetPCIePhyBit(tp, + 0x22, + (BIT_5 | BIT_4), + BIT_5 + ); + ClearAndSetPCIePhyBit(tp, + 0x62, + (BIT_5 | BIT_4), + BIT_5 + ); break; } } @@ -5098,6 +5324,8 @@ rtl8125_check_hw_phy_mcu_code_ver(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: mdio_direct_write_phy_ocp(tp, 0xA436, 0x801E); tp->hw_ram_code_ver = mdio_direct_read_phy_ocp(tp, 0xA438); break; @@ -5122,6 +5350,8 @@ rtl8125_write_hw_phy_mcu_code_ver(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: mdio_direct_write_phy_ocp(tp, 0xA436, 0x801E); mdio_direct_write_phy_ocp(tp, 0xA438, tp->sw_ram_code_ver); tp->hw_ram_code_ver = tp->sw_ram_code_ver; @@ -5141,6 +5371,12 @@ rtl8125_acquire_phy_mcu_patch_key_lock(struct rtl8125_private *tp) case CFG_METHOD_3: PatchKey = 0x8601; break; + case CFG_METHOD_4: + PatchKey = 0x3700; + break; + case CFG_METHOD_5: + PatchKey = 0x3701; + break; default: return; } @@ -5156,6 +5392,8 @@ rtl8125_release_phy_mcu_patch_key_lock(struct rtl8125_private *tp) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: mdio_direct_write_phy_ocp(tp, 0xA436, 0x0000); mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); ClearEthPhyOcpBit(tp, 0xB82E, BIT_0); @@ -5216,7 +5454,32 @@ rtl8125_clear_phy_mcu_patch_request(struct rtl8125_private *tp) } static void -rtl8125_real_set_phy_mcu_8125_2(struct net_device *dev) +rtl8125_set_phy_mcu_ram_code(struct net_device *dev, const u16 *ramcode, u16 codesize) +{ + struct rtl8125_private *tp = netdev_priv(dev); + u16 i; + u16 addr; + u16 val; + + if (ramcode == NULL || codesize % 2) { + goto out; + } + + for (i = 0; i < codesize; i += 2) { + addr = ramcode[i]; + val = ramcode[i + 1]; + if (addr == 0xFFFF && val == 0xFFFF) { + break; + } + mdio_direct_write_phy_ocp(tp, addr, val); + } + +out: + return; +} + +static void +rtl8125_real_set_phy_mcu_8125a_1(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); @@ -6049,19 +6312,19 @@ rtl8125_real_set_phy_mcu_8125_2(struct net_device *dev) } static void -rtl8125_set_phy_mcu_8125_2(struct net_device *dev) +rtl8125_set_phy_mcu_8125a_1(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); rtl8125_set_phy_mcu_patch_request(tp); - rtl8125_real_set_phy_mcu_8125_2(dev); + rtl8125_real_set_phy_mcu_8125a_1(dev); rtl8125_clear_phy_mcu_patch_request(tp); } static void -rtl8125_real_set_phy_mcu_8125_3(struct net_device *dev) +rtl8125_real_set_phy_mcu_8125a_2(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); @@ -6636,13 +6899,829 @@ rtl8125_real_set_phy_mcu_8125_3(struct net_device *dev) } static void -rtl8125_set_phy_mcu_8125_3(struct net_device *dev) +rtl8125_set_phy_mcu_8125a_2(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); rtl8125_set_phy_mcu_patch_request(tp); - rtl8125_real_set_phy_mcu_8125_3(dev); + rtl8125_real_set_phy_mcu_8125a_2(dev); + + rtl8125_clear_phy_mcu_patch_request(tp); +} + +static const u16 phy_mcu_ram_code_8125b_1[] = { + 0xa436, 0x8024, 0xa438, 0x3700, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x8025, 0xa438, 0x1800, 0xa438, 0x803a, + 0xa438, 0x1800, 0xa438, 0x8044, 0xa438, 0x1800, 0xa438, 0x8083, + 0xa438, 0x1800, 0xa438, 0x808d, 0xa438, 0x1800, 0xa438, 0x808d, + 0xa438, 0x1800, 0xa438, 0x808d, 0xa438, 0xd712, 0xa438, 0x4077, + 0xa438, 0xd71e, 0xa438, 0x4159, 0xa438, 0xd71e, 0xa438, 0x6099, + 0xa438, 0x7f44, 0xa438, 0x1800, 0xa438, 0x1a14, 0xa438, 0x9040, + 0xa438, 0x9201, 0xa438, 0x1800, 0xa438, 0x1b1a, 0xa438, 0xd71e, + 0xa438, 0x2425, 0xa438, 0x1a14, 0xa438, 0xd71f, 0xa438, 0x3ce5, + 0xa438, 0x1afb, 0xa438, 0x1800, 0xa438, 0x1b00, 0xa438, 0xd712, + 0xa438, 0x4077, 0xa438, 0xd71e, 0xa438, 0x4159, 0xa438, 0xd71e, + 0xa438, 0x60b9, 0xa438, 0x2421, 0xa438, 0x1c17, 0xa438, 0x1800, + 0xa438, 0x1a14, 0xa438, 0x9040, 0xa438, 0x1800, 0xa438, 0x1c2c, + 0xa438, 0xd71e, 0xa438, 0x2425, 0xa438, 0x1a14, 0xa438, 0xd71f, + 0xa438, 0x3ce5, 0xa438, 0x1c0f, 0xa438, 0x1800, 0xa438, 0x1c13, + 0xa438, 0xd702, 0xa438, 0xd501, 0xa438, 0x6072, 0xa438, 0x8401, + 0xa438, 0xf002, 0xa438, 0xa401, 0xa438, 0x1000, 0xa438, 0x146e, + 0xa438, 0x1800, 0xa438, 0x0b77, 0xa438, 0xd703, 0xa438, 0x665d, + 0xa438, 0x653e, 0xa438, 0x641f, 0xa438, 0xd700, 0xa438, 0x62c4, + 0xa438, 0x6185, 0xa438, 0x6066, 0xa438, 0x1800, 0xa438, 0x165a, + 0xa438, 0xc101, 0xa438, 0xcb00, 0xa438, 0x1000, 0xa438, 0x1945, + 0xa438, 0xd700, 0xa438, 0x7fa6, 0xa438, 0x1800, 0xa438, 0x807d, + 0xa438, 0xc102, 0xa438, 0xcb00, 0xa438, 0x1000, 0xa438, 0x1945, + 0xa438, 0xd700, 0xa438, 0x2569, 0xa438, 0x8058, 0xa438, 0x1800, + 0xa438, 0x807d, 0xa438, 0xc104, 0xa438, 0xcb00, 0xa438, 0x1000, + 0xa438, 0x1945, 0xa438, 0xd700, 0xa438, 0x7fa4, 0xa438, 0x1800, + 0xa438, 0x807d, 0xa438, 0xc120, 0xa438, 0xcb00, 0xa438, 0x1000, + 0xa438, 0x1945, 0xa438, 0xd703, 0xa438, 0x7fbf, 0xa438, 0x1800, + 0xa438, 0x807d, 0xa438, 0xc140, 0xa438, 0xcb00, 0xa438, 0x1000, + 0xa438, 0x1945, 0xa438, 0xd703, 0xa438, 0x7fbe, 0xa438, 0x1800, + 0xa438, 0x807d, 0xa438, 0xc180, 0xa438, 0xcb00, 0xa438, 0x1000, + 0xa438, 0x1945, 0xa438, 0xd703, 0xa438, 0x7fbd, 0xa438, 0xc100, + 0xa438, 0xcb00, 0xa438, 0xd708, 0xa438, 0x6018, 0xa438, 0x1800, + 0xa438, 0x165a, 0xa438, 0x1000, 0xa438, 0x14f6, 0xa438, 0xd014, + 0xa438, 0xd1e3, 0xa438, 0x1000, 0xa438, 0x1356, 0xa438, 0xd705, + 0xa438, 0x5fbe, 0xa438, 0x1800, 0xa438, 0x1559, 0xa436, 0xA026, + 0xa438, 0xffff, 0xa436, 0xA024, 0xa438, 0xffff, 0xa436, 0xA022, + 0xa438, 0xffff, 0xa436, 0xA020, 0xa438, 0x1557, 0xa436, 0xA006, + 0xa438, 0x1677, 0xa436, 0xA004, 0xa438, 0x0b75, 0xa436, 0xA002, + 0xa438, 0x1c17, 0xa436, 0xA000, 0xa438, 0x1b04, 0xa436, 0xA008, + 0xa438, 0x1f00, 0xa436, 0xA016, 0xa438, 0x0020, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x817f, 0xa438, 0x1800, 0xa438, 0x82ab, + 0xa438, 0x1800, 0xa438, 0x83f8, 0xa438, 0x1800, 0xa438, 0x8444, + 0xa438, 0x1800, 0xa438, 0x8454, 0xa438, 0x1800, 0xa438, 0x8459, + 0xa438, 0x1800, 0xa438, 0x8465, 0xa438, 0xcb11, 0xa438, 0xa50c, + 0xa438, 0x8310, 0xa438, 0xd701, 0xa438, 0x4076, 0xa438, 0x0c03, + 0xa438, 0x0903, 0xa438, 0xd700, 0xa438, 0x6083, 0xa438, 0x0c1f, + 0xa438, 0x0d00, 0xa438, 0xf003, 0xa438, 0x0c1f, 0xa438, 0x0d00, + 0xa438, 0x1000, 0xa438, 0x0a7d, 0xa438, 0x1000, 0xa438, 0x0a4d, + 0xa438, 0xcb12, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, + 0xa438, 0x5f84, 0xa438, 0xd102, 0xa438, 0xd040, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xd701, + 0xa438, 0x60f3, 0xa438, 0xd413, 0xa438, 0x1000, 0xa438, 0x0a37, + 0xa438, 0xd410, 0xa438, 0x1000, 0xa438, 0x0a37, 0xa438, 0xcb13, + 0xa438, 0xa108, 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8108, + 0xa438, 0xa00a, 0xa438, 0xa910, 0xa438, 0xa780, 0xa438, 0xd14a, + 0xa438, 0xd048, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd701, + 0xa438, 0x6255, 0xa438, 0xd700, 0xa438, 0x5f74, 0xa438, 0x6326, + 0xa438, 0xd702, 0xa438, 0x5f07, 0xa438, 0x800a, 0xa438, 0xa004, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8004, 0xa438, 0xa001, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8001, 0xa438, 0x0c03, + 0xa438, 0x0902, 0xa438, 0xffe2, 0xa438, 0x1000, 0xa438, 0x0a5e, + 0xa438, 0xd71f, 0xa438, 0x5fab, 0xa438, 0xba08, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd71f, 0xa438, 0x7f8b, 0xa438, 0x9a08, + 0xa438, 0x800a, 0xa438, 0xd702, 0xa438, 0x6535, 0xa438, 0xd40d, + 0xa438, 0x1000, 0xa438, 0x0a37, 0xa438, 0xcb14, 0xa438, 0xa004, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8004, 0xa438, 0xa001, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8001, 0xa438, 0xa00a, + 0xa438, 0xa780, 0xa438, 0xd14a, 0xa438, 0xd048, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0x6206, + 0xa438, 0xd702, 0xa438, 0x5f47, 0xa438, 0x800a, 0xa438, 0xa004, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8004, 0xa438, 0xa001, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8001, 0xa438, 0x0c03, + 0xa438, 0x0902, 0xa438, 0x1800, 0xa438, 0x8064, 0xa438, 0x800a, + 0xa438, 0xd40e, 0xa438, 0x1000, 0xa438, 0x0a37, 0xa438, 0xb920, + 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, 0xa438, 0x5fac, + 0xa438, 0x9920, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, + 0xa438, 0x7f8c, 0xa438, 0xd701, 0xa438, 0x6073, 0xa438, 0xd701, + 0xa438, 0x4216, 0xa438, 0xa004, 0xa438, 0x1000, 0xa438, 0x0a42, + 0xa438, 0x8004, 0xa438, 0xa001, 0xa438, 0x1000, 0xa438, 0x0a42, + 0xa438, 0x8001, 0xa438, 0xd120, 0xa438, 0xd040, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0x8504, + 0xa438, 0xcb21, 0xa438, 0xa301, 0xa438, 0x1000, 0xa438, 0x0a5e, + 0xa438, 0xd700, 0xa438, 0x5f9f, 0xa438, 0x8301, 0xa438, 0xd704, + 0xa438, 0x40e0, 0xa438, 0xd196, 0xa438, 0xd04d, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xcb22, + 0xa438, 0x1000, 0xa438, 0x0a6d, 0xa438, 0x0c03, 0xa438, 0x1502, + 0xa438, 0xa640, 0xa438, 0x9503, 0xa438, 0x8910, 0xa438, 0x8720, + 0xa438, 0xd700, 0xa438, 0x6083, 0xa438, 0x0c1f, 0xa438, 0x0d01, + 0xa438, 0xf003, 0xa438, 0x0c1f, 0xa438, 0x0d01, 0xa438, 0x1000, + 0xa438, 0x0a7d, 0xa438, 0x0c1f, 0xa438, 0x0f14, 0xa438, 0xcb23, + 0xa438, 0x8fc0, 0xa438, 0x1000, 0xa438, 0x0a25, 0xa438, 0xaf40, + 0xa438, 0x1000, 0xa438, 0x0a25, 0xa438, 0x0cc0, 0xa438, 0x0f80, + 0xa438, 0x1000, 0xa438, 0x0a25, 0xa438, 0xafc0, 0xa438, 0x1000, + 0xa438, 0x0a25, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd701, + 0xa438, 0x5dee, 0xa438, 0xcb24, 0xa438, 0x8f1f, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd701, 0xa438, 0x7f6e, 0xa438, 0xa111, + 0xa438, 0xa215, 0xa438, 0xa401, 0xa438, 0x8404, 0xa438, 0xa720, + 0xa438, 0xcb25, 0xa438, 0x0c03, 0xa438, 0x1502, 0xa438, 0x8640, + 0xa438, 0x9503, 0xa438, 0x1000, 0xa438, 0x0b43, 0xa438, 0x1000, + 0xa438, 0x0b86, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xb920, + 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, 0xa438, 0x5fac, + 0xa438, 0x9920, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, + 0xa438, 0x7f8c, 0xa438, 0xcb26, 0xa438, 0x1000, 0xa438, 0x0a5e, + 0xa438, 0xd71f, 0xa438, 0x5f82, 0xa438, 0x8111, 0xa438, 0x8205, + 0xa438, 0x8404, 0xa438, 0xcb27, 0xa438, 0xd404, 0xa438, 0x1000, + 0xa438, 0x0a37, 0xa438, 0xd700, 0xa438, 0x6083, 0xa438, 0x0c1f, + 0xa438, 0x0d02, 0xa438, 0xf003, 0xa438, 0x0c1f, 0xa438, 0x0d02, + 0xa438, 0x1000, 0xa438, 0x0a7d, 0xa438, 0xa710, 0xa438, 0xa104, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8104, 0xa438, 0xa001, + 0xa438, 0x1000, 0xa438, 0x0a42, 0xa438, 0x8001, 0xa438, 0xa120, + 0xa438, 0xaa0f, 0xa438, 0x8110, 0xa438, 0xa284, 0xa438, 0xa404, + 0xa438, 0xa00a, 0xa438, 0xd193, 0xa438, 0xd046, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xcb28, + 0xa438, 0xa110, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd700, + 0xa438, 0x5fa8, 0xa438, 0x8110, 0xa438, 0x8284, 0xa438, 0xa404, + 0xa438, 0x800a, 0xa438, 0x8710, 0xa438, 0xb804, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd71f, 0xa438, 0x7f82, 0xa438, 0x9804, + 0xa438, 0xcb29, 0xa438, 0x1000, 0xa438, 0x0a5e, 0xa438, 0xd71f, + 0xa438, 0x5f85, 0xa438, 0xa710, 0xa438, 0xb820, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd71f, 0xa438, 0x7f65, 0xa438, 0x9820, + 0xa438, 0xcb2a, 0xa438, 0xa190, 0xa438, 0xa284, 0xa438, 0xa404, + 0xa438, 0xa00a, 0xa438, 0xd13d, 0xa438, 0xd04a, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x3444, 0xa438, 0x8149, + 0xa438, 0xa220, 0xa438, 0xd1a0, 0xa438, 0xd040, 0xa438, 0x1000, + 0xa438, 0x0a5e, 0xa438, 0xd700, 0xa438, 0x3444, 0xa438, 0x8151, + 0xa438, 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0xd200, + 0xa438, 0xdbf6, 0xa438, 0x05ef, 0xa438, 0x021f, 0xa438, 0x110d, + 0xa438, 0x42bf, 0xa438, 0x8b45, 0xa438, 0x026c, 0xa438, 0x4eef, + 0xa438, 0x021b, 0xa438, 0x031f, 0xa438, 0x110d, 0xa438, 0x42bf, + 0xa438, 0x8b3f, 0xa438, 0x026c, 0xa438, 0x4eef, 0xa438, 0x021a, + 0xa438, 0x031f, 0xa438, 0x110d, 0xa438, 0x42bf, 0xa438, 0x8b42, + 0xa438, 0x026c, 0xa438, 0x4eef, 0xa438, 0x56d0, 0xa438, 0x201f, + 0xa438, 0x11bf, 0xa438, 0x8b4e, 0xa438, 0x026c, 0xa438, 0x4ebf, + 0xa438, 0x8b48, 0xa438, 0x026c, 0xa438, 0x4ebf, 0xa438, 0x8b4b, + 0xa438, 0x026c, 0xa438, 0x4ee1, 0xa438, 0x8578, 0xa438, 0xef03, + 0xa438, 0x480a, 0xa438, 0x2805, 0xa438, 0xef20, 0xa438, 0x1b01, + 0xa438, 0xad27, 0xa438, 0x3f1f, 0xa438, 0x44e0, 0xa438, 0x8560, + 0xa438, 0xe185, 0xa438, 0x61bf, 0xa438, 0x8b51, 0xa438, 0x026c, + 0xa438, 0x4ee0, 0xa438, 0x8566, 0xa438, 0xe185, 0xa438, 0x67bf, + 0xa438, 0x8b54, 0xa438, 0x026c, 0xa438, 0x4ee0, 0xa438, 0x856c, + 0xa438, 0xe185, 0xa438, 0x6dbf, 0xa438, 0x8b57, 0xa438, 0x026c, + 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0x6c4e, 0xa438, 0xe085, 0xa438, 0x70e1, 0xa438, 0x8571, + 0xa438, 0xbf8b, 0xa438, 0x5702, 0xa438, 0x6c4e, 0xa438, 0xe085, + 0xa438, 0x76e1, 0xa438, 0x8577, 0xa438, 0xbf8b, 0xa438, 0x5a02, + 0xa438, 0x6c4e, 0xa438, 0xe18f, 0xa438, 0xb859, 0xa438, 0x00f7, + 0xa438, 0x28e5, 0xa438, 0x8fb8, 0xa438, 0xae0c, 0xa438, 0xe18f, + 0xa438, 0xb839, 0xa438, 0x04ac, 0xa438, 0x2f04, 0xa438, 0xee8f, + 0xa438, 0xb800, 0xa438, 0xfefd, 0xa438, 0xfc04, 0xa438, 0xf0ac, + 0xa438, 0x8efc, 0xa438, 0xac8c, 0xa438, 0xf0ac, 0xa438, 0xfaf0, + 0xa438, 0xacf8, 0xa438, 0xf0ac, 0xa438, 0xf6f0, 0xa438, 0xad00, + 0xa438, 0xf0ac, 0xa438, 0xfef0, 0xa438, 0xacfc, 0xa438, 0xf0ac, + 0xa438, 0xf4f0, 0xa438, 0xacf2, 0xa438, 0xf0ac, 0xa438, 0xf0f0, + 0xa438, 0xacb0, 0xa438, 0xf0ac, 0xa438, 0xaef0, 0xa438, 0xacac, + 0xa438, 0xf0ac, 0xa438, 0xaaf0, 0xa438, 0xacee, 0xa438, 0xf0b0, + 0xa438, 0x24f0, 0xa438, 0xb0a4, 0xa438, 0xf0b1, 0xa438, 0x24f0, + 0xa438, 0xb1a4, 0xa438, 0xee8f, 0xa438, 0xb800, 0xa438, 0xd400, + 0xa438, 0x00af, 0xa438, 0x3976, 0xa438, 0x66ac, 0xa438, 0xeabb, + 0xa438, 0xa430, 0xa438, 0x6e50, 0xa438, 0x6e53, 0xa438, 0x6e56, + 0xa438, 0x6e59, 0xa438, 0x6e5c, 0xa438, 0x6e5f, 0xa438, 0x6e62, + 0xa438, 0x6e65, 0xa438, 0xd9ac, 0xa438, 0x70f0, 0xa438, 0xac6a, + 0xa436, 0xb85e, 0xa438, 0x23b7, 0xa436, 0xb860, 0xa438, 0x74db, + 0xa436, 0xb862, 0xa438, 0x268c, 0xa436, 0xb864, 0xa438, 0x3FE5, + 0xa436, 0xb886, 0xa438, 0x2250, 0xa436, 0xb888, 0xa438, 0x140e, + 0xa436, 0xb88a, 0xa438, 0x3696, 0xa436, 0xb88c, 0xa438, 0x3973, + 0xa436, 0xb838, 0xa438, 0x00ff, 0xb820, 0x0010, 0xa436, 0x8464, + 0xa438, 0xaf84, 0xa438, 0x7caf, 0xa438, 0x8485, 0xa438, 0xaf85, + 0xa438, 0x13af, 0xa438, 0x851e, 0xa438, 0xaf85, 0xa438, 0xb9af, + 0xa438, 0x8684, 0xa438, 0xaf87, 0xa438, 0x01af, 0xa438, 0x8701, + 0xa438, 0xac38, 0xa438, 0x03af, 0xa438, 0x38bb, 0xa438, 0xaf38, + 0xa438, 0xc302, 0xa438, 0x4618, 0xa438, 0xbf85, 0xa438, 0x0a02, + 0xa438, 0x54b7, 0xa438, 0xbf85, 0xa438, 0x1002, 0xa438, 0x54c0, + 0xa438, 0xd400, 0xa438, 0x0fbf, 0xa438, 0x8507, 0xa438, 0x024f, + 0xa438, 0x48bf, 0xa438, 0x8504, 0xa438, 0x024f, 0xa438, 0x6759, + 0xa438, 0xf0a1, 0xa438, 0x3008, 0xa438, 0xbf85, 0xa438, 0x0d02, + 0xa438, 0x54c0, 0xa438, 0xae06, 0xa438, 0xbf85, 0xa438, 0x0d02, + 0xa438, 0x54b7, 0xa438, 0xbf85, 0xa438, 0x0402, 0xa438, 0x4f67, + 0xa438, 0xa183, 0xa438, 0x02ae, 0xa438, 0x15a1, 0xa438, 0x8502, + 0xa438, 0xae10, 0xa438, 0x59f0, 0xa438, 0xa180, 0xa438, 0x16bf, + 0xa438, 0x8501, 0xa438, 0x024f, 0xa438, 0x67a1, 0xa438, 0x381b, + 0xa438, 0xae0b, 0xa438, 0xe18f, 0xa438, 0xffbf, 0xa438, 0x84fe, + 0xa438, 0x024f, 0xa438, 0x48ae, 0xa438, 0x17bf, 0xa438, 0x84fe, + 0xa438, 0x0254, 0xa438, 0xb7bf, 0xa438, 0x84fb, 0xa438, 0x0254, + 0xa438, 0xb7ae, 0xa438, 0x09a1, 0xa438, 0x5006, 0xa438, 0xbf84, + 0xa438, 0xfb02, 0xa438, 0x54c0, 0xa438, 0xaf04, 0xa438, 0x4700, + 0xa438, 0xad34, 0xa438, 0xfdad, 0xa438, 0x0670, 0xa438, 0xae14, + 0xa438, 0xf0a6, 0xa438, 0x00b8, 0xa438, 0xbd32, 0xa438, 0x30bd, + 0xa438, 0x30aa, 0xa438, 0xbd2c, 0xa438, 0xccbd, 0xa438, 0x2ca1, + 0xa438, 0x0705, 0xa438, 0xec80, 0xa438, 0xaf40, 0xa438, 0xf7af, + 0xa438, 0x40f5, 0xa438, 0xd101, 0xa438, 0xbf85, 0xa438, 0xa402, + 0xa438, 0x4f48, 0xa438, 0xbf85, 0xa438, 0xa702, 0xa438, 0x54c0, + 0xa438, 0xd10f, 0xa438, 0xbf85, 0xa438, 0xaa02, 0xa438, 0x4f48, + 0xa438, 0x024d, 0xa438, 0x6abf, 0xa438, 0x85ad, 0xa438, 0x024f, + 0xa438, 0x67bf, 0xa438, 0x8ff7, 0xa438, 0xddbf, 0xa438, 0x85b0, + 0xa438, 0x024f, 0xa438, 0x67bf, 0xa438, 0x8ff8, 0xa438, 0xddbf, + 0xa438, 0x85b3, 0xa438, 0x024f, 0xa438, 0x67bf, 0xa438, 0x8ff9, + 0xa438, 0xddbf, 0xa438, 0x85b6, 0xa438, 0x024f, 0xa438, 0x67bf, + 0xa438, 0x8ffa, 0xa438, 0xddd1, 0xa438, 0x00bf, 0xa438, 0x85aa, + 0xa438, 0x024f, 0xa438, 0x4802, 0xa438, 0x4d6a, 0xa438, 0xbf85, + 0xa438, 0xad02, 0xa438, 0x4f67, 0xa438, 0xbf8f, 0xa438, 0xfbdd, + 0xa438, 0xbf85, 0xa438, 0xb002, 0xa438, 0x4f67, 0xa438, 0xbf8f, + 0xa438, 0xfcdd, 0xa438, 0xbf85, 0xa438, 0xb302, 0xa438, 0x4f67, + 0xa438, 0xbf8f, 0xa438, 0xfddd, 0xa438, 0xbf85, 0xa438, 0xb602, + 0xa438, 0x4f67, 0xa438, 0xbf8f, 0xa438, 0xfedd, 0xa438, 0xbf85, + 0xa438, 0xa702, 0xa438, 0x54b7, 0xa438, 0xbf85, 0xa438, 0xa102, + 0xa438, 0x54b7, 0xa438, 0xaf3c, 0xa438, 0x2066, 0xa438, 0xb800, + 0xa438, 0xb8bd, 0xa438, 0x30ee, 0xa438, 0xbd2c, 0xa438, 0xb8bd, + 0xa438, 0x7040, 0xa438, 0xbd86, 0xa438, 0xc8bd, 0xa438, 0x8640, + 0xa438, 0xbd88, 0xa438, 0xc8bd, 0xa438, 0x8802, 0xa438, 0x1929, + 0xa438, 0xa202, 0xa438, 0x02ae, 0xa438, 0x03a2, 0xa438, 0x032e, + 0xa438, 0xd10f, 0xa438, 0xbf85, 0xa438, 0xaa02, 0xa438, 0x4f48, + 0xa438, 0xe18f, 0xa438, 0xf7bf, 0xa438, 0x85ad, 0xa438, 0x024f, + 0xa438, 0x48e1, 0xa438, 0x8ff8, 0xa438, 0xbf85, 0xa438, 0xb002, + 0xa438, 0x4f48, 0xa438, 0xe18f, 0xa438, 0xf9bf, 0xa438, 0x85b3, + 0xa438, 0x024f, 0xa438, 0x48e1, 0xa438, 0x8ffa, 0xa438, 0xbf85, + 0xa438, 0xb602, 0xa438, 0x4f48, 0xa438, 0xae2c, 0xa438, 0xd100, + 0xa438, 0xbf85, 0xa438, 0xaa02, 0xa438, 0x4f48, 0xa438, 0xe18f, + 0xa438, 0xfbbf, 0xa438, 0x85ad, 0xa438, 0x024f, 0xa438, 0x48e1, + 0xa438, 0x8ffc, 0xa438, 0xbf85, 0xa438, 0xb002, 0xa438, 0x4f48, + 0xa438, 0xe18f, 0xa438, 0xfdbf, 0xa438, 0x85b3, 0xa438, 0x024f, + 0xa438, 0x48e1, 0xa438, 0x8ffe, 0xa438, 0xbf85, 0xa438, 0xb602, + 0xa438, 0x4f48, 0xa438, 0xbf86, 0xa438, 0x7e02, 0xa438, 0x4f67, + 0xa438, 0xa100, 0xa438, 0x02ae, 0xa438, 0x25a1, 0xa438, 0x041d, + 0xa438, 0xe18f, 0xa438, 0xf1bf, 0xa438, 0x8675, 0xa438, 0x024f, + 0xa438, 0x48e1, 0xa438, 0x8ff2, 0xa438, 0xbf86, 0xa438, 0x7802, + 0xa438, 0x4f48, 0xa438, 0xe18f, 0xa438, 0xf3bf, 0xa438, 0x867b, + 0xa438, 0x024f, 0xa438, 0x48ae, 0xa438, 0x29a1, 0xa438, 0x070b, + 0xa438, 0xae24, 0xa438, 0xbf86, 0xa438, 0x8102, 0xa438, 0x4f67, + 0xa438, 0xad28, 0xa438, 0x1be1, 0xa438, 0x8ff4, 0xa438, 0xbf86, + 0xa438, 0x7502, 0xa438, 0x4f48, 0xa438, 0xe18f, 0xa438, 0xf5bf, + 0xa438, 0x8678, 0xa438, 0x024f, 0xa438, 0x48e1, 0xa438, 0x8ff6, + 0xa438, 0xbf86, 0xa438, 0x7b02, 0xa438, 0x4f48, 0xa438, 0xaf09, + 0xa438, 0x8420, 0xa438, 0xbc32, 0xa438, 0x20bc, 0xa438, 0x3e76, + 0xa438, 0xbc08, 0xa438, 0xfda6, 0xa438, 0x1a00, 0xa438, 0xb64e, + 0xa438, 0xd101, 0xa438, 0xbf85, 0xa438, 0xa402, 0xa438, 0x4f48, + 0xa438, 0xbf85, 0xa438, 0xa702, 0xa438, 0x54c0, 0xa438, 0xd10f, + 0xa438, 0xbf85, 0xa438, 0xaa02, 0xa438, 0x4f48, 0xa438, 0x024d, + 0xa438, 0x6abf, 0xa438, 0x85ad, 0xa438, 0x024f, 0xa438, 0x67bf, + 0xa438, 0x8ff7, 0xa438, 0xddbf, 0xa438, 0x85b0, 0xa438, 0x024f, + 0xa438, 0x67bf, 0xa438, 0x8ff8, 0xa438, 0xddbf, 0xa438, 0x85b3, + 0xa438, 0x024f, 0xa438, 0x67bf, 0xa438, 0x8ff9, 0xa438, 0xddbf, + 0xa438, 0x85b6, 0xa438, 0x024f, 0xa438, 0x67bf, 0xa438, 0x8ffa, + 0xa438, 0xddd1, 0xa438, 0x00bf, 0xa438, 0x85aa, 0xa438, 0x024f, + 0xa438, 0x4802, 0xa438, 0x4d6a, 0xa438, 0xbf85, 0xa438, 0xad02, + 0xa438, 0x4f67, 0xa438, 0xbf8f, 0xa438, 0xfbdd, 0xa438, 0xbf85, + 0xa438, 0xb002, 0xa438, 0x4f67, 0xa438, 0xbf8f, 0xa438, 0xfcdd, + 0xa438, 0xbf85, 0xa438, 0xb302, 0xa438, 0x4f67, 0xa438, 0xbf8f, + 0xa438, 0xfddd, 0xa438, 0xbf85, 0xa438, 0xb602, 0xa438, 0x4f67, + 0xa438, 0xbf8f, 0xa438, 0xfedd, 0xa438, 0xbf85, 0xa438, 0xa702, + 0xa438, 0x54b7, 0xa438, 0xaf00, 0xa438, 0x8800, 0xa436, 0xb818, + 0xa438, 0x38b8, 0xa436, 0xb81a, 0xa438, 0x0444, 0xa436, 0xb81c, + 0xa438, 0x40ee, 0xa436, 0xb81e, 0xa438, 0x3C1A, 0xa436, 0xb850, + 0xa438, 0x0981, 0xa436, 0xb852, 0xa438, 0x0085, 0xa436, 0xb878, + 0xa438, 0xffff, 0xa436, 0xb884, 0xa438, 0xffff, 0xa436, 0xb832, + 0xa438, 0x003f, 0xa436, 0x0000, 0xa438, 0x0000, 0xa436, 0xB82E, + 0xa438, 0x0000, 0xa436, 0x8024, 0xa438, 0x0000, 0xb820, 0x0000, + 0xa436, 0x801E, 0xa438, 0x0021, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8125b_2[] = { + 0xa436, 0x8024, 0xa438, 0x3701, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x801a, 0xa438, 0x1800, 0xa438, 0x8024, + 0xa438, 0x1800, 0xa438, 0x802f, 0xa438, 0x1800, 0xa438, 0x8051, + 0xa438, 0x1800, 0xa438, 0x8057, 0xa438, 0x1800, 0xa438, 0x8063, + 0xa438, 0x1800, 0xa438, 0x8068, 0xa438, 0xd093, 0xa438, 0xd1c4, + 0xa438, 0x1000, 0xa438, 0x135c, 0xa438, 0xd704, 0xa438, 0x5fbc, + 0xa438, 0xd504, 0xa438, 0xc9f1, 0xa438, 0x1800, 0xa438, 0x0fc9, + 0xa438, 0xbb50, 0xa438, 0xd505, 0xa438, 0xa202, 0xa438, 0xd504, + 0xa438, 0x8c0f, 0xa438, 0xd500, 0xa438, 0x1000, 0xa438, 0x1519, + 0xa438, 0x1800, 0xa438, 0x1548, 0xa438, 0x2f70, 0xa438, 0x802a, + 0xa438, 0x2f73, 0xa438, 0x156a, 0xa438, 0x1800, 0xa438, 0x155c, + 0xa438, 0xd505, 0xa438, 0xa202, 0xa438, 0xd500, 0xa438, 0x1800, + 0xa438, 0x1551, 0xa438, 0xc0c1, 0xa438, 0xc0c0, 0xa438, 0xd05a, + 0xa438, 0xd1ba, 0xa438, 0xd701, 0xa438, 0x2529, 0xa438, 0x022a, + 0xa438, 0xd0a7, 0xa438, 0xd1b9, 0xa438, 0xa208, 0xa438, 0x1000, + 0xa438, 0x080e, 0xa438, 0xd701, 0xa438, 0x408b, 0xa438, 0x1000, + 0xa438, 0x0a65, 0xa438, 0xf003, 0xa438, 0x1000, 0xa438, 0x0a6b, + 0xa438, 0xd701, 0xa438, 0x1000, 0xa438, 0x0920, 0xa438, 0x1000, + 0xa438, 0x0915, 0xa438, 0x1000, 0xa438, 0x0909, 0xa438, 0x228f, + 0xa438, 0x8038, 0xa438, 0x9801, 0xa438, 0xd71e, 0xa438, 0x5d61, + 0xa438, 0xd701, 0xa438, 0x1800, 0xa438, 0x022a, 0xa438, 0x2005, + 0xa438, 0x091a, 0xa438, 0x3bd9, 0xa438, 0x0919, 0xa438, 0x1800, + 0xa438, 0x0916, 0xa438, 0x1000, 0xa438, 0x14c5, 0xa438, 0xd703, + 0xa438, 0x3181, 0xa438, 0x8061, 0xa438, 0x60ad, 0xa438, 0x1000, + 0xa438, 0x135c, 0xa438, 0xd703, 0xa438, 0x5fba, 0xa438, 0x1800, + 0xa438, 0x0cc7, 0xa438, 0xd096, 0xa438, 0xd1a9, 0xa438, 0xd503, + 0xa438, 0x1800, 0xa438, 0x0c94, 0xa436, 0xA026, 0xa438, 0xffff, + 0xa436, 0xA024, 0xa438, 0x0c93, 0xa436, 0xA022, 0xa438, 0x0cc5, + 0xa436, 0xA020, 0xa438, 0x0915, 0xa436, 0xA006, 0xa438, 0x020a, + 0xa436, 0xA004, 0xa438, 0x155b, 0xa436, 0xA002, 0xa438, 0x1542, + 0xa436, 0xA000, 0xa438, 0x0fc7, 0xa436, 0xA008, 0xa438, 0x7f00, + 0xa436, 0xA016, 0xa438, 0x0010, 0xa436, 0xA012, 0xa438, 0x0000, + 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, 0xa438, 0x1800, + 0xa438, 0x801d, 0xa438, 0x1800, 0xa438, 0x802c, 0xa438, 0x1800, + 0xa438, 0x802c, 0xa438, 0x1800, 0xa438, 0x802c, 0xa438, 0x1800, + 0xa438, 0x802c, 0xa438, 0x1800, 0xa438, 0x802c, 0xa438, 0x1800, + 0xa438, 0x802c, 0xa438, 0xd700, 0xa438, 0x6090, 0xa438, 0x60d1, + 0xa438, 0xc95c, 0xa438, 0xf007, 0xa438, 0x60b1, 0xa438, 0xc95a, + 0xa438, 0xf004, 0xa438, 0xc956, 0xa438, 0xf002, 0xa438, 0xc94e, + 0xa438, 0x1800, 0xa438, 0x00cd, 0xa438, 0xd700, 0xa438, 0x6090, + 0xa438, 0x60d1, 0xa438, 0xc95c, 0xa438, 0xf007, 0xa438, 0x60b1, + 0xa438, 0xc95a, 0xa438, 0xf004, 0xa438, 0xc956, 0xa438, 0xf002, + 0xa438, 0xc94e, 0xa438, 0x1000, 0xa438, 0x022a, 0xa438, 0x1800, + 0xa438, 0x0132, 0xa436, 0xA08E, 0xa438, 0xffff, 0xa436, 0xA08C, + 0xa438, 0xffff, 0xa436, 0xA08A, 0xa438, 0xffff, 0xa436, 0xA088, + 0xa438, 0xffff, 0xa436, 0xA086, 0xa438, 0xffff, 0xa436, 0xA084, + 0xa438, 0xffff, 0xa436, 0xA082, 0xa438, 0x012f, 0xa436, 0xA080, + 0xa438, 0x00cc, 0xa436, 0xA090, 0xa438, 0x0103, 0xa436, 0xA016, + 0xa438, 0x0020, 0xa436, 0xA012, 0xa438, 0x0000, 0xa436, 0xA014, + 0xa438, 0x1800, 0xa438, 0x8010, 0xa438, 0x1800, 0xa438, 0x801e, + 0xa438, 0x1800, 0xa438, 0x8026, 0xa438, 0x1800, 0xa438, 0x802f, + 0xa438, 0x1800, 0xa438, 0x8036, 0xa438, 0x1800, 0xa438, 0x8036, + 0xa438, 0x1800, 0xa438, 0x8036, 0xa438, 0x1800, 0xa438, 0x8036, + 0xa438, 0xd107, 0xa438, 0xd042, 0xa438, 0xa404, 0xa438, 0xd700, + 0xa438, 0x5ff4, 0xa438, 0x8280, 0xa438, 0xd700, 0xa438, 0x6065, + 0xa438, 0xd125, 0xa438, 0xf002, 0xa438, 0xd12b, 0xa438, 0xd040, + 0xa438, 0x1800, 0xa438, 0x077f, 0xa438, 0x0cf0, 0xa438, 0x0c50, + 0xa438, 0xd104, 0xa438, 0xd040, 0xa438, 0xd700, 0xa438, 0x5ff4, + 0xa438, 0x1800, 0xa438, 0x0a2e, 0xa438, 0xcb9b, 0xa438, 0xd110, + 0xa438, 0xd040, 0xa438, 0x1000, 0xa438, 0x0b7b, 0xa438, 0xd700, + 0xa438, 0x5ff4, 0xa438, 0x1800, 0xa438, 0x081b, 0xa438, 0x1000, + 0xa438, 0x09df, 0xa438, 0xd704, 0xa438, 0x7fb8, 0xa438, 0xa718, + 0xa438, 0x1800, 0xa438, 0x074e, 0xa436, 0xA10E, 0xa438, 0xffff, + 0xa436, 0xA10C, 0xa438, 0xffff, 0xa436, 0xA10A, 0xa438, 0xffff, + 0xa436, 0xA108, 0xa438, 0xffff, 0xa436, 0xA106, 0xa438, 0x074d, + 0xa436, 0xA104, 0xa438, 0x0818, 0xa436, 0xA102, 0xa438, 0x0a2c, + 0xa436, 0xA100, 0xa438, 0x077e, 0xa436, 0xA110, 0xa438, 0x000f, + 0xa436, 0xb87c, 0xa438, 0x8625, 0xa436, 0xb87e, 0xa438, 0xaf86, + 0xa438, 0x3daf, 0xa438, 0x8689, 0xa438, 0xaf88, 0xa438, 0x69af, + 0xa438, 0x8887, 0xa438, 0xaf88, 0xa438, 0x9caf, 0xa438, 0x889c, + 0xa438, 0xaf88, 0xa438, 0x9caf, 0xa438, 0x889c, 0xa438, 0xbf86, + 0xa438, 0x49d7, 0xa438, 0x0040, 0xa438, 0x0277, 0xa438, 0x7daf, + 0xa438, 0x2727, 0xa438, 0x0000, 0xa438, 0x7205, 0xa438, 0x0000, + 0xa438, 0x7208, 0xa438, 0x0000, 0xa438, 0x71f3, 0xa438, 0x0000, + 0xa438, 0x71f6, 0xa438, 0x0000, 0xa438, 0x7229, 0xa438, 0x0000, + 0xa438, 0x722c, 0xa438, 0x0000, 0xa438, 0x7217, 0xa438, 0x0000, + 0xa438, 0x721a, 0xa438, 0x0000, 0xa438, 0x721d, 0xa438, 0x0000, + 0xa438, 0x7211, 0xa438, 0x0000, 0xa438, 0x7220, 0xa438, 0x0000, + 0xa438, 0x7214, 0xa438, 0x0000, 0xa438, 0x722f, 0xa438, 0x0000, + 0xa438, 0x7223, 0xa438, 0x0000, 0xa438, 0x7232, 0xa438, 0x0000, + 0xa438, 0x7226, 0xa438, 0xf8f9, 0xa438, 0xfae0, 0xa438, 0x85b3, + 0xa438, 0x3802, 0xa438, 0xad27, 0xa438, 0x02ae, 0xa438, 0x03af, + 0xa438, 0x8830, 0xa438, 0x1f66, 0xa438, 0xef65, 0xa438, 0xbfc2, + 0xa438, 0x1f1a, 0xa438, 0x96f7, 0xa438, 0x05ee, 0xa438, 0xffd2, + 0xa438, 0x00da, 0xa438, 0xf605, 0xa438, 0xbfc2, 0xa438, 0x2f1a, + 0xa438, 0x96f7, 0xa438, 0x05ee, 0xa438, 0xffd2, 0xa438, 0x00db, + 0xa438, 0xf605, 0xa438, 0xef02, 0xa438, 0x1f11, 0xa438, 0x0d42, + 0xa438, 0xbf88, 0xa438, 0x4202, 0xa438, 0x6e7d, 0xa438, 0xef02, + 0xa438, 0x1b03, 0xa438, 0x1f11, 0xa438, 0x0d42, 0xa438, 0xbf88, + 0xa438, 0x4502, 0xa438, 0x6e7d, 0xa438, 0xef02, 0xa438, 0x1a03, + 0xa438, 0x1f11, 0xa438, 0x0d42, 0xa438, 0xbf88, 0xa438, 0x4802, + 0xa438, 0x6e7d, 0xa438, 0xbfc2, 0xa438, 0x3f1a, 0xa438, 0x96f7, + 0xa438, 0x05ee, 0xa438, 0xffd2, 0xa438, 0x00da, 0xa438, 0xf605, + 0xa438, 0xbfc2, 0xa438, 0x4f1a, 0xa438, 0x96f7, 0xa438, 0x05ee, + 0xa438, 0xffd2, 0xa438, 0x00db, 0xa438, 0xf605, 0xa438, 0xef02, + 0xa438, 0x1f11, 0xa438, 0x0d42, 0xa438, 0xbf88, 0xa438, 0x4b02, + 0xa438, 0x6e7d, 0xa438, 0xef02, 0xa438, 0x1b03, 0xa438, 0x1f11, + 0xa438, 0x0d42, 0xa438, 0xbf88, 0xa438, 0x4e02, 0xa438, 0x6e7d, + 0xa438, 0xef02, 0xa438, 0x1a03, 0xa438, 0x1f11, 0xa438, 0x0d42, + 0xa438, 0xbf88, 0xa438, 0x5102, 0xa438, 0x6e7d, 0xa438, 0xef56, + 0xa438, 0xd020, 0xa438, 0x1f11, 0xa438, 0xbf88, 0xa438, 0x5402, + 0xa438, 0x6e7d, 0xa438, 0xbf88, 0xa438, 0x5702, 0xa438, 0x6e7d, + 0xa438, 0xbf88, 0xa438, 0x5a02, 0xa438, 0x6e7d, 0xa438, 0xe185, + 0xa438, 0xa0ef, 0xa438, 0x0348, 0xa438, 0x0a28, 0xa438, 0x05ef, + 0xa438, 0x201b, 0xa438, 0x01ad, 0xa438, 0x2735, 0xa438, 0x1f44, + 0xa438, 0xe085, 0xa438, 0x88e1, 0xa438, 0x8589, 0xa438, 0xbf88, + 0xa438, 0x5d02, 0xa438, 0x6e7d, 0xa438, 0xe085, 0xa438, 0x8ee1, + 0xa438, 0x858f, 0xa438, 0xbf88, 0xa438, 0x6002, 0xa438, 0x6e7d, + 0xa438, 0xe085, 0xa438, 0x94e1, 0xa438, 0x8595, 0xa438, 0xbf88, + 0xa438, 0x6302, 0xa438, 0x6e7d, 0xa438, 0xe085, 0xa438, 0x9ae1, + 0xa438, 0x859b, 0xa438, 0xbf88, 0xa438, 0x6602, 0xa438, 0x6e7d, + 0xa438, 0xaf88, 0xa438, 0x3cbf, 0xa438, 0x883f, 0xa438, 0x026e, + 0xa438, 0x9cad, 0xa438, 0x2835, 0xa438, 0x1f44, 0xa438, 0xe08f, + 0xa438, 0xf8e1, 0xa438, 0x8ff9, 0xa438, 0xbf88, 0xa438, 0x5d02, + 0xa438, 0x6e7d, 0xa438, 0xe08f, 0xa438, 0xfae1, 0xa438, 0x8ffb, + 0xa438, 0xbf88, 0xa438, 0x6002, 0xa438, 0x6e7d, 0xa438, 0xe08f, + 0xa438, 0xfce1, 0xa438, 0x8ffd, 0xa438, 0xbf88, 0xa438, 0x6302, + 0xa438, 0x6e7d, 0xa438, 0xe08f, 0xa438, 0xfee1, 0xa438, 0x8fff, + 0xa438, 0xbf88, 0xa438, 0x6602, 0xa438, 0x6e7d, 0xa438, 0xaf88, + 0xa438, 0x3ce1, 0xa438, 0x85a1, 0xa438, 0x1b21, 0xa438, 0xad37, + 0xa438, 0x341f, 0xa438, 0x44e0, 0xa438, 0x858a, 0xa438, 0xe185, + 0xa438, 0x8bbf, 0xa438, 0x885d, 0xa438, 0x026e, 0xa438, 0x7de0, + 0xa438, 0x8590, 0xa438, 0xe185, 0xa438, 0x91bf, 0xa438, 0x8860, + 0xa438, 0x026e, 0xa438, 0x7de0, 0xa438, 0x8596, 0xa438, 0xe185, + 0xa438, 0x97bf, 0xa438, 0x8863, 0xa438, 0x026e, 0xa438, 0x7de0, + 0xa438, 0x859c, 0xa438, 0xe185, 0xa438, 0x9dbf, 0xa438, 0x8866, + 0xa438, 0x026e, 0xa438, 0x7dae, 0xa438, 0x401f, 0xa438, 0x44e0, + 0xa438, 0x858c, 0xa438, 0xe185, 0xa438, 0x8dbf, 0xa438, 0x885d, + 0xa438, 0x026e, 0xa438, 0x7de0, 0xa438, 0x8592, 0xa438, 0xe185, + 0xa438, 0x93bf, 0xa438, 0x8860, 0xa438, 0x026e, 0xa438, 0x7de0, + 0xa438, 0x8598, 0xa438, 0xe185, 0xa438, 0x99bf, 0xa438, 0x8863, + 0xa438, 0x026e, 0xa438, 0x7de0, 0xa438, 0x859e, 0xa438, 0xe185, + 0xa438, 0x9fbf, 0xa438, 0x8866, 0xa438, 0x026e, 0xa438, 0x7dae, + 0xa438, 0x0ce1, 0xa438, 0x85b3, 0xa438, 0x3904, 0xa438, 0xac2f, + 0xa438, 0x04ee, 0xa438, 0x85b3, 0xa438, 0x00af, 0xa438, 0x39d9, + 0xa438, 0x22ac, 0xa438, 0xeaf0, 0xa438, 0xacf6, 0xa438, 0xf0ac, + 0xa438, 0xfaf0, 0xa438, 0xacf8, 0xa438, 0xf0ac, 0xa438, 0xfcf0, + 0xa438, 0xad00, 0xa438, 0xf0ac, 0xa438, 0xfef0, 0xa438, 0xacf0, + 0xa438, 0xf0ac, 0xa438, 0xf4f0, 0xa438, 0xacf2, 0xa438, 0xf0ac, + 0xa438, 0xb0f0, 0xa438, 0xacae, 0xa438, 0xf0ac, 0xa438, 0xacf0, + 0xa438, 0xacaa, 0xa438, 0xa100, 0xa438, 0x0ce1, 0xa438, 0x8ff7, + 0xa438, 0xbf88, 0xa438, 0x8402, 0xa438, 0x6e7d, 0xa438, 0xaf26, + 0xa438, 0xe9e1, 0xa438, 0x8ff6, 0xa438, 0xbf88, 0xa438, 0x8402, + 0xa438, 0x6e7d, 0xa438, 0xaf26, 0xa438, 0xf520, 0xa438, 0xac86, + 0xa438, 0xbf88, 0xa438, 0x3f02, 0xa438, 0x6e9c, 0xa438, 0xad28, + 0xa438, 0x03af, 0xa438, 0x3324, 0xa438, 0xad38, 0xa438, 0x03af, + 0xa438, 0x32e6, 0xa438, 0xaf32, 0xa438, 0xfb00, 0xa436, 0xb87c, + 0xa438, 0x8ff6, 0xa436, 0xb87e, 0xa438, 0x0705, 0xa436, 0xb87c, + 0xa438, 0x8ff8, 0xa436, 0xb87e, 0xa438, 0x19cc, 0xa436, 0xb87c, + 0xa438, 0x8ffa, 0xa436, 0xb87e, 0xa438, 0x28e3, 0xa436, 0xb87c, + 0xa438, 0x8ffc, 0xa436, 0xb87e, 0xa438, 0x1047, 0xa436, 0xb87c, + 0xa438, 0x8ffe, 0xa436, 0xb87e, 0xa438, 0x0a45, 0xa436, 0xb85e, + 0xa438, 0x271E, 0xa436, 0xb860, 0xa438, 0x3846, 0xa436, 0xb862, + 0xa438, 0x26E6, 0xa436, 0xb864, 0xa438, 0x32E3, 0xa436, 0xb886, + 0xa438, 0xffff, 0xa436, 0xb888, 0xa438, 0xffff, 0xa436, 0xb88a, + 0xa438, 0xffff, 0xa436, 0xb88c, 0xa438, 0xffff, 0xa436, 0xb838, + 0xa438, 0x000f, 0xb820, 0x0010, 0xa436, 0x0000, 0xa438, 0x0000, + 0xa436, 0xB82E, 0xa438, 0x0000, 0xa436, 0x8024, 0xa438, 0x0000, + 0xb820, 0x0000, 0xa436, 0x801E, 0xa438, 0x0015, 0xFFFF, 0xFFFF +}; + +static void +rtl8125_real_set_phy_mcu_8125b_1(struct net_device *dev) +{ + rtl8125_set_phy_mcu_ram_code(dev, + phy_mcu_ram_code_8125b_1, + ARRAY_SIZE(phy_mcu_ram_code_8125b_1) + ); +} + +static void +rtl8125_set_phy_mcu_8125b_1(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + rtl8125_set_phy_mcu_patch_request(tp); + + rtl8125_real_set_phy_mcu_8125b_1(dev); + + rtl8125_clear_phy_mcu_patch_request(tp); +} + +static void +rtl8125_real_set_phy_mcu_8125b_2(struct net_device *dev) +{ + rtl8125_set_phy_mcu_ram_code(dev, + phy_mcu_ram_code_8125b_2, + ARRAY_SIZE(phy_mcu_ram_code_8125b_2) + ); +} + +static void +rtl8125_set_phy_mcu_8125b_2(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + rtl8125_set_phy_mcu_patch_request(tp); + + rtl8125_real_set_phy_mcu_8125b_2(dev); rtl8125_clear_phy_mcu_patch_request(tp); } @@ -6664,10 +7743,16 @@ rtl8125_init_hw_phy_mcu(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: - rtl8125_set_phy_mcu_8125_2(dev); + rtl8125_set_phy_mcu_8125a_1(dev); break; case CFG_METHOD_3: - rtl8125_set_phy_mcu_8125_3(dev); + rtl8125_set_phy_mcu_8125a_2(dev); + break; + case CFG_METHOD_4: + rtl8125_set_phy_mcu_8125b_1(dev); + break; + case CFG_METHOD_5: + rtl8125_set_phy_mcu_8125b_2(dev); break; } @@ -6681,6 +7766,917 @@ rtl8125_init_hw_phy_mcu(struct net_device *dev) tp->HwHasWrRamCodeToMicroP = TRUE; } +static void +rtl8125_enable_phy_aldps(struct rtl8125_private *tp) +{ + //enable aldps + //GPHY OCP 0xA430 bit[2] = 0x1 (en_aldps) + SetEthPhyOcpBit(tp, 0xA430, BIT_2); +} + +static void +rtl8125_hw_phy_config_8125a_1(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + ClearAndSetEthPhyOcpBit(tp, + 0xAD40, + 0x03FF, + 0x84 + ); + + SetEthPhyOcpBit(tp, 0xAD4E, BIT_4); + ClearAndSetEthPhyOcpBit(tp, + 0xAD16, + 0x03FF, + 0x0006 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xAD32, + 0x003F, + 0x0006 + ); + ClearEthPhyOcpBit(tp, 0xAC08, BIT_12); + ClearEthPhyOcpBit(tp, 0xAC08, BIT_8); + ClearAndSetEthPhyOcpBit(tp, + 0xAC8A, + BIT_15|BIT_14|BIT_13|BIT_12, + BIT_14|BIT_13|BIT_12 + ); + SetEthPhyOcpBit(tp, 0xAD18, BIT_10); + SetEthPhyOcpBit(tp, 0xAD1A, 0x3FF); + SetEthPhyOcpBit(tp, 0xAD1C, 0x3FF); + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EA); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0xC400 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EB); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0x0700, + 0x0300 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80F8); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x1C00 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80F1); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x3000 + ); + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80FE); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0xA500 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8102); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x5000 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8105); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x3300 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8100); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x7000 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8104); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0xF000 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8106); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x6500 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DC); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0xED00 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DF); + SetEthPhyOcpBit(tp, 0xA438, BIT_8); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80E1); + ClearEthPhyOcpBit(tp, 0xA438, BIT_8); + + ClearAndSetEthPhyOcpBit(tp, + 0xBF06, + 0x003F, + 0x38 + ); + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x819F); + mdio_direct_write_phy_ocp(tp, 0xA438, 0xD0B6); + + mdio_direct_write_phy_ocp(tp, 0xBC34, 0x5555); + ClearAndSetEthPhyOcpBit(tp, + 0xBF0A, + BIT_11|BIT_10|BIT_9, + BIT_11|BIT_9 + ); + + ClearEthPhyOcpBit(tp, 0xA5C0, BIT_10); + + SetEthPhyOcpBit(tp, 0xA442, BIT_11); + + //enable aldps + //GPHY OCP 0xA430 bit[2] = 0x1 (en_aldps) + if (aspm) { + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + rtl8125_enable_phy_aldps(tp); + } + } +} + +static void +rtl8125_hw_phy_config_8125a_2(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + SetEthPhyOcpBit(tp, 0xAD4E, BIT_4); + ClearAndSetEthPhyOcpBit(tp, + 0xAD16, + 0x03FF, + 0x03FF + ); + ClearAndSetEthPhyOcpBit(tp, + 0xAD32, + 0x003F, + 0x0006 + ); + ClearEthPhyOcpBit(tp, 0xAC08, BIT_12); + ClearEthPhyOcpBit(tp, 0xAC08, BIT_8); + ClearAndSetEthPhyOcpBit(tp, + 0xACC0, + BIT_1|BIT_0, + BIT_1 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xAD40, + BIT_7|BIT_6|BIT_5, + BIT_6 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xAD40, + BIT_2|BIT_1|BIT_0, + BIT_2 + ); + ClearEthPhyOcpBit(tp, 0xAC14, BIT_7); + ClearEthPhyOcpBit(tp, 0xAC80, BIT_9|BIT_8); + ClearAndSetEthPhyOcpBit(tp, + 0xAC5E, + BIT_2|BIT_1|BIT_0, + BIT_1 + ); + mdio_direct_write_phy_ocp(tp, 0xAD4C, 0x00A8); + mdio_direct_write_phy_ocp(tp, 0xAC5C, 0x01FF); + ClearAndSetEthPhyOcpBit(tp, + 0xAC8A, + BIT_7|BIT_6|BIT_5|BIT_4, + BIT_5|BIT_4 + ); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8157); + ClearAndSetEthPhyOcpBit(tp, + 0xB87E, + 0xFF00, + 0x0500 + ); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8159); + ClearAndSetEthPhyOcpBit(tp, + 0xB87E, + 0xFF00, + 0x0700 + ); + + + RTL_W16(tp, EEE_TXIDLE_TIMER_8125, 0x2400 + 0x20); + + + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80A2); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0153); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x809C); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0153); + + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x81B3); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0043); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x00A7); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x00D6); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x00EC); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x00F6); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FB); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FD); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FF); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x00BB); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0058); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0029); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0013); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0009); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0004); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0002); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8257); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x020F); + + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EA); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x7843); + + + rtl8125_set_phy_mcu_patch_request(tp); + + ClearEthPhyOcpBit(tp, 0xB896, BIT_0); + ClearEthPhyOcpBit(tp, 0xB892, 0xFF00); + + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC091); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E12); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC092); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x1214); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC094); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x1516); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC096); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x171B); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC098); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x1B1C); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09A); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x1F1F); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09C); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x2021); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09E); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x2224); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A0); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A2); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A4); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC018); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x0AF2); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01A); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x0D4A); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01C); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x0F26); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01E); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x118D); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC020); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x14F3); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC022); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x175A); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC024); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x19C0); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC026); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x1C26); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC089); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x6050); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08A); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x5F6E); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08C); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E6E); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08E); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E6E); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC090); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E12); + + SetEthPhyOcpBit(tp, 0xB896, BIT_0); + + rtl8125_clear_phy_mcu_patch_request(tp); + + + SetEthPhyOcpBit(tp, 0xD068, BIT_13); + + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x81A2); + SetEthPhyOcpBit(tp, 0xA438, BIT_8); + ClearAndSetEthPhyOcpBit(tp, + 0xB54C, + 0xFF00, + 0xDB00); + + + ClearEthPhyOcpBit(tp, 0xA454, BIT_0); + + + SetEthPhyOcpBit(tp, 0xA5D4, BIT_5); + ClearEthPhyOcpBit(tp, 0xAD4E, BIT_4); + ClearEthPhyOcpBit(tp, 0xA86A, BIT_0); + + + SetEthPhyOcpBit(tp, 0xA442, BIT_11); + + + if (tp->RequirePhyMdiSwapPatch) { + u16 adccal_offset_p0; + u16 adccal_offset_p1; + u16 adccal_offset_p2; + u16 adccal_offset_p3; + u16 rg_lpf_cap_xg_p0; + u16 rg_lpf_cap_xg_p1; + u16 rg_lpf_cap_xg_p2; + u16 rg_lpf_cap_xg_p3; + u16 rg_lpf_cap_p0; + u16 rg_lpf_cap_p1; + u16 rg_lpf_cap_p2; + u16 rg_lpf_cap_p3; + + ClearAndSetEthPhyOcpBit(tp, + 0xD068, + 0x0007, + 0x0001 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xD068, + 0x0018, + 0x0000 + ); + adccal_offset_p0 = mdio_direct_read_phy_ocp(tp, 0xD06A); + adccal_offset_p0 &= 0x07FF; + ClearAndSetEthPhyOcpBit(tp, + 0xD068, + 0x0018, + 0x0008 + ); + adccal_offset_p1 = mdio_direct_read_phy_ocp(tp, 0xD06A); + adccal_offset_p1 &= 0x07FF; + ClearAndSetEthPhyOcpBit(tp, + 0xD068, + 0x0018, + 0x0010 + ); + adccal_offset_p2 = mdio_direct_read_phy_ocp(tp, 0xD06A); + adccal_offset_p2 &= 0x07FF; + ClearAndSetEthPhyOcpBit(tp, + 0xD068, + 0x0018, + 0x0018 + ); + adccal_offset_p3 = mdio_direct_read_phy_ocp(tp, 0xD06A); + adccal_offset_p3 &= 0x07FF; + + + ClearAndSetEthPhyOcpBit(tp, + 0xD068, + 0x0018, + 0x0000 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xD06A, + 0x07FF, + adccal_offset_p3 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xD068, + 0x0018, + 0x0008 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xD06A, + 0x07FF, + adccal_offset_p2 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xD068, + 0x0018, + 0x0010 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xD06A, + 0x07FF, + adccal_offset_p1 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xD068, + 0x0018, + 0x0018 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xD06A, + 0x07FF, + adccal_offset_p0 + ); + + + rg_lpf_cap_xg_p0 = mdio_direct_read_phy_ocp(tp, 0xBD5A); + rg_lpf_cap_xg_p0 &= 0x001F; + rg_lpf_cap_xg_p1 = mdio_direct_read_phy_ocp(tp, 0xBD5A); + rg_lpf_cap_xg_p1 &= 0x1F00; + rg_lpf_cap_xg_p2 = mdio_direct_read_phy_ocp(tp, 0xBD5C); + rg_lpf_cap_xg_p2 &= 0x001F; + rg_lpf_cap_xg_p3 = mdio_direct_read_phy_ocp(tp, 0xBD5C); + rg_lpf_cap_xg_p3 &= 0x1F00; + rg_lpf_cap_p0 = mdio_direct_read_phy_ocp(tp, 0xBC18); + rg_lpf_cap_p0 &= 0x001F; + rg_lpf_cap_p1 = mdio_direct_read_phy_ocp(tp, 0xBC18); + rg_lpf_cap_p1 &= 0x1F00; + rg_lpf_cap_p2 = mdio_direct_read_phy_ocp(tp, 0xBC1A); + rg_lpf_cap_p2 &= 0x001F; + rg_lpf_cap_p3 = mdio_direct_read_phy_ocp(tp, 0xBC1A); + rg_lpf_cap_p3 &= 0x1F00; + + + ClearAndSetEthPhyOcpBit(tp, + 0xBD5A, + 0x001F, + rg_lpf_cap_xg_p3 >> 8 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xBD5A, + 0x1F00, + rg_lpf_cap_xg_p2 << 8 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xBD5C, + 0x001F, + rg_lpf_cap_xg_p1 >> 8 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xBD5C, + 0x1F00, + rg_lpf_cap_xg_p0 << 8 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xBC18, + 0x001F, + rg_lpf_cap_p3 >> 8 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xBC18, + 0x1F00, + rg_lpf_cap_p2 << 8 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xBC1A, + 0x001F, + rg_lpf_cap_p1 >> 8 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xBC1A, + 0x1F00, + rg_lpf_cap_p0 << 8 + ); + } + + + if (aspm) { + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + rtl8125_enable_phy_aldps(tp); + } + } +} + +static void +rtl8125_hw_phy_config_8125b_1(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + SetEthPhyOcpBit(tp, 0xA442, BIT_11); + + + SetEthPhyOcpBit(tp, 0xBC08, (BIT_3 | BIT_2)); + + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FFF); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x0400 + ); + } + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8560); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x19CC); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8562); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x19CC); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8564); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x19CC); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8566); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x147D); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8568); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x147D); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x856A); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x147D); + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FFE); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0907); + } + ClearAndSetEthPhyOcpBit(tp, + 0xACDA, + 0xFF00, + 0xFF00 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xACDE, + 0xF000, + 0xF000 + ); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80D6); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2801); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80F2); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2801); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80F4); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x6077); + mdio_direct_write_phy_ocp(tp, 0xB506, 0x01E7); + mdio_direct_write_phy_ocp(tp, 0xAC8C, 0x0FFC); + mdio_direct_write_phy_ocp(tp, 0xAC46, 0xB7B4); + mdio_direct_write_phy_ocp(tp, 0xAC50, 0x0FBC); + mdio_direct_write_phy_ocp(tp, 0xAC3C, 0x9240); + mdio_direct_write_phy_ocp(tp, 0xAC4E, 0x0DB4); + mdio_direct_write_phy_ocp(tp, 0xACC6, 0x0707); + mdio_direct_write_phy_ocp(tp, 0xACC8, 0xA0D3); + mdio_direct_write_phy_ocp(tp, 0xAD08, 0x0007); + + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8013); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0700); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FB9); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2801); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FBA); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0100); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FBC); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x1900); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FBE); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xE100); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC0); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0800); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC2); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xE500); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC4); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0F00); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC6); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF100); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC8); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0400); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FCa); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF300); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FCc); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFD00); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FCe); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFF00); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD0); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFB00); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD2); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0100); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD4); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF400); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD6); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFF00); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD8); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF600); + + + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x813D); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x390E); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x814F); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x790E); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80B0); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0F31); + SetEthPhyOcpBit(tp, 0xBF4C, BIT_1); + SetEthPhyOcpBit(tp, 0xBCCA, (BIT_9 | BIT_8)); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8141); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x320E); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8153); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x720E); + ClearEthPhyOcpBit(tp, 0xA432, BIT_6); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8529); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x050E); + + + RTL_W16(tp, EEE_TXIDLE_TIMER_8125, 0x2400 + 0x20); + + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x816C); + mdio_direct_write_phy_ocp(tp, 0xA438, 0xC4A0); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8170); + mdio_direct_write_phy_ocp(tp, 0xA438, 0xC4A0); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8174); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x04A0); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8178); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x04A0); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x817C); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0719); + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF4); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0400); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF1); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0404); + } + mdio_direct_write_phy_ocp(tp, 0xBF4A, 0x001B); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8033); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8037); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x803B); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFC32); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x803F); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8043); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8047); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + + + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8145); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x370E); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8157); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x770E); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8169); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0D0A); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x817B); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x1D0A); + + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x8217); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x5000 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x821A); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x5000 + ); + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DA); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0403); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DC); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x1000 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B3); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x0384); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B7); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x2007); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80BA); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x6C00 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B5); + mdio_direct_write_phy_ocp(tp, 0xA438, 0xF009); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80BD); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x9F00 + ); + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80C7); + mdio_direct_write_phy_ocp(tp, 0xA438, 0xf083); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DD); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x03f0); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DF); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x1000 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80CB); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x2007); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80CE); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x6C00 + ); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80C9); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x8009); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80D1); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0x8000 + ); + + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A3); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x200A); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A5); + mdio_direct_write_phy_ocp(tp, 0xA438, 0xF0AD); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x809F); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x6073); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A1); + mdio_direct_write_phy_ocp(tp, 0xA438, 0x000B); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A9); + ClearAndSetEthPhyOcpBit(tp, + 0xA438, + 0xFF00, + 0xC000 + ); + + rtl8125_set_phy_mcu_patch_request(tp); + + ClearEthPhyOcpBit(tp, 0xB896, BIT_0); + ClearEthPhyOcpBit(tp, 0xB892, 0xFF00); + + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC23E); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x0000); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC240); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x0103); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC242); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x0507); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC244); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x090B); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC246); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x0C0E); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC248); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x1012); + mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC24A); + mdio_direct_write_phy_ocp(tp, 0xB890, 0x1416); + + SetEthPhyOcpBit(tp, 0xB896, BIT_0); + + rtl8125_clear_phy_mcu_patch_request(tp); + + + SetEthPhyOcpBit(tp, 0xA86A, BIT_0); + SetEthPhyOcpBit(tp, 0xA6F0, BIT_0); + + + mdio_direct_write_phy_ocp(tp, 0xBFA0, 0xD70D); + mdio_direct_write_phy_ocp(tp, 0xBFA2, 0x4100); + mdio_direct_write_phy_ocp(tp, 0xBFA4, 0xE868); + mdio_direct_write_phy_ocp(tp, 0xBFA6, 0xDC59); + mdio_direct_write_phy_ocp(tp, 0xB54C, 0x3C18); + ClearEthPhyOcpBit(tp, 0xBFA4, BIT_5); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x817D); + SetEthPhyOcpBit(tp, 0xA438, BIT_12); + + + if (aspm) { + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + rtl8125_enable_phy_aldps(tp); + } + } +} + +static void +rtl8125_hw_phy_config_8125b_2(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + SetEthPhyOcpBit(tp, 0xA442, BIT_11); + + + ClearAndSetEthPhyOcpBit(tp, + 0xAC46, + 0x00F0, + 0x0090 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xAD30, + 0x0003, + 0x0001 + ); + + + RTL_W16(tp, EEE_TXIDLE_TIMER_8125, 0x2400 + 0x20); + + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80F5); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x760E); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8107); + mdio_direct_write_phy_ocp(tp, 0xB87E, 0x360E); + mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8551); + ClearAndSetEthPhyOcpBit(tp, + 0xB87E, + BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8, + BIT_11 + ); + + ClearAndSetEthPhyOcpBit(tp, + 0xbf00, + 0xE000, + 0xA000 + ); + ClearAndSetEthPhyOcpBit(tp, + 0xbf46, + 0x0F00, + 0x0300 + ); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x8044); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x804A); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x8050); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x8056); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x805C); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x8062); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x8068); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x806E); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x8074); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + mdio_direct_write_phy_ocp(tp, 0xa436, 0x807A); + mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + + + SetEthPhyOcpBit(tp, 0xA4CA, BIT_6); + + /* + mdio_direct_write_phy_ocp(tp, 0xBFA0, 0xD70D); + mdio_direct_write_phy_ocp(tp, 0xBFA2, 0x4100); + mdio_direct_write_phy_ocp(tp, 0xBFA4, 0xE868); + mdio_direct_write_phy_ocp(tp, 0xBFA6, 0xDC59); + mdio_direct_write_phy_ocp(tp, 0xB54C, 0x3C18); + ClearEthPhyOcpBit(tp, 0xBFA4, BIT_5); + mdio_direct_write_phy_ocp(tp, 0xA436, 0x817D); + SetEthPhyOcpBit(tp, 0xA438, BIT_12); + */ + + + if (aspm) { + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + rtl8125_enable_phy_aldps(tp); + } + } +} + +static void +rtl8125_set_hw_phy_before_init_phy_mcu(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + u16 PhyRegValue; + + switch (tp->mcfg) { + case CFG_METHOD_4: + case CFG_METHOD_5: + mdio_direct_write_phy_ocp(tp, 0xBF86, 0x9000); + + SetEthPhyOcpBit(tp, 0xC402, BIT_10); + ClearEthPhyOcpBit(tp, 0xC402, BIT_10); + + PhyRegValue = mdio_direct_read_phy_ocp(tp, 0xBF86); + PhyRegValue &= (BIT_1 | BIT_0); + if (PhyRegValue != 0) + dprintk("PHY watch dog not clear, value = 0x%x \n", PhyRegValue); + + mdio_direct_write_phy_ocp(tp, 0xBD86, 0x1010); + mdio_direct_write_phy_ocp(tp, 0xBD88, 0x1010); + + ClearAndSetEthPhyOcpBit(tp, + 0xBD4E, + BIT_11 | BIT_10, + BIT_11); + ClearAndSetEthPhyOcpBit(tp, + 0xBF46, + BIT_11 | BIT_10 | BIT_9 | BIT_8, + BIT_10 | BIT_9 | BIT_8); + break; + } +} + static void rtl8125_hw_phy_config(struct net_device *dev) { @@ -6690,324 +8686,23 @@ rtl8125_hw_phy_config(struct net_device *dev) if (HW_DASH_SUPPORT_TYPE_3(tp) && tp->HwPkgDet == 0x06) return; + rtl8125_set_hw_phy_before_init_phy_mcu(dev); + rtl8125_init_hw_phy_mcu(dev); - if (tp->mcfg == CFG_METHOD_2) { - ClearAndSetEthPhyOcpBit(tp, - 0xAD40, - 0x03FF, - 0x84 - ); - - SetEthPhyOcpBit(tp, 0xAD4E, BIT_4); - ClearAndSetEthPhyOcpBit(tp, - 0xAD16, - 0x03FF, - 0x0006 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xAD32, - 0x003F, - 0x0006 - ); - ClearEthPhyOcpBit(tp, 0xAC08, BIT_12); - ClearEthPhyOcpBit(tp, 0xAC08, BIT_8); - ClearAndSetEthPhyOcpBit(tp, - 0xAC8A, - BIT_15|BIT_14|BIT_13|BIT_12, - BIT_14|BIT_13|BIT_12 - ); - SetEthPhyOcpBit(tp, 0xAD18, BIT_10); - SetEthPhyOcpBit(tp, 0xAD1A, 0x3FF); - SetEthPhyOcpBit(tp, 0xAD1C, 0x3FF); - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EA); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0xC400 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EB); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0x0700, - 0x0300 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80F8); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x1C00 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80F1); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x3000 - ); - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80FE); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0xA500 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8102); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x5000 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8105); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x3300 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8100); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x7000 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8104); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0xF000 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8106); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x6500 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DC); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0xED00 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DF); - SetEthPhyOcpBit(tp, 0xA438, BIT_8); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80E1); - ClearEthPhyOcpBit(tp, 0xA438, BIT_8); - - ClearAndSetEthPhyOcpBit(tp, - 0xBF06, - 0x003F, - 0x38 - ); - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x819F); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xD0B6); - - mdio_direct_write_phy_ocp(tp, 0xBC34, 0x5555); - ClearAndSetEthPhyOcpBit(tp, - 0xBF0A, - BIT_11|BIT_10|BIT_9, - BIT_11|BIT_9 - ); - - ClearEthPhyOcpBit(tp, 0xA5C0, BIT_10); - - SetEthPhyOcpBit(tp, 0xA442, BIT_11); - - //enable aldps - //GPHY OCP 0xA430 bit[2] = 0x1 (en_aldps) - if (aspm) { - if (tp->HwHasWrRamCodeToMicroP == TRUE) { - SetEthPhyOcpBit(tp, 0xA430, BIT_2); - } - } - } else if (tp->mcfg == CFG_METHOD_3) { - SetEthPhyOcpBit(tp, 0xAD4E, BIT_4); - ClearAndSetEthPhyOcpBit(tp, - 0xAD16, - 0x03FF, - 0x03FF - ); - ClearAndSetEthPhyOcpBit(tp, - 0xAD32, - 0x003F, - 0x0006 - ); - ClearEthPhyOcpBit(tp, 0xAC08, BIT_12); - ClearEthPhyOcpBit(tp, 0xAC08, BIT_8); - ClearAndSetEthPhyOcpBit(tp, - 0xACC0, - BIT_1|BIT_0, - BIT_1 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xAD40, - BIT_7|BIT_6|BIT_5, - BIT_6 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xAD40, - BIT_2|BIT_1|BIT_0, - BIT_2 - ); - ClearEthPhyOcpBit(tp, 0xAC14, BIT_7); - ClearEthPhyOcpBit(tp, 0xAC80, BIT_9|BIT_8); - ClearAndSetEthPhyOcpBit(tp, - 0xAC5E, - BIT_2|BIT_1|BIT_0, - BIT_1 - ); - mdio_direct_write_phy_ocp(tp, 0xAD4C, 0x00A8); - mdio_direct_write_phy_ocp(tp, 0xAC5C, 0x01FF); - ClearAndSetEthPhyOcpBit(tp, - 0xAC8A, - BIT_7|BIT_6|BIT_5|BIT_4, - BIT_5|BIT_4 - ); - - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80A2); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0153); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x809C); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0153); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x81B3); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0043); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00A7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00D6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00EC); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00F6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FB); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FD); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FF); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00BB); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0058); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0029); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0013); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0009); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0004); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8257); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x020F); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EA); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7843); - - - rtl8125_set_phy_mcu_patch_request(tp); - - ClearEthPhyOcpBit(tp, 0xB896, BIT_0); - ClearEthPhyOcpBit(tp, 0xB892, 0xFF00); - - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC091); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E12); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC092); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1214); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC094); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1516); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC096); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x171B); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC098); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1B1C); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09A); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1F1F); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09C); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2021); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09E); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2224); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A0); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A2); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A4); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC018); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0AF2); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01A); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0D4A); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01C); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0F26); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01E); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x118D); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC020); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x14F3); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC022); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x175A); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC024); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x19C0); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC026); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1C26); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC089); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6050); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08A); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x5F6E); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08C); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E6E); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08E); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E6E); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC090); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E12); - - SetEthPhyOcpBit(tp, 0xB896, BIT_0); - - rtl8125_clear_phy_mcu_patch_request(tp); - - - SetEthPhyOcpBit(tp, 0xD068, BIT_13); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x81A2); - SetEthPhyOcpBit(tp, 0xA438, BIT_8); - ClearAndSetEthPhyOcpBit(tp, - 0xB54C, - 0xFF00, - 0xDB00); - - - ClearEthPhyOcpBit(tp, 0xA454, BIT_0); - - - SetEthPhyOcpBit(tp, 0xA5D4, BIT_5); - ClearEthPhyOcpBit(tp, 0xAD4E, BIT_4); - ClearEthPhyOcpBit(tp, 0xA86A, BIT_0); - - - SetEthPhyOcpBit(tp, 0xA442, BIT_11); - - //enable aldps - //GPHY OCP 0xA430 bit[2] = 0x1 (en_aldps) - if (aspm) { - if (tp->HwHasWrRamCodeToMicroP == TRUE) { - SetEthPhyOcpBit(tp, 0xA430, BIT_2); - } - } + switch (tp->mcfg) { + case CFG_METHOD_2: + rtl8125_hw_phy_config_8125a_1(dev); + break; + case CFG_METHOD_3: + rtl8125_hw_phy_config_8125a_2(dev); + break; + case CFG_METHOD_4: + rtl8125_hw_phy_config_8125b_1(dev); + break; + case CFG_METHOD_5: + rtl8125_hw_phy_config_8125b_2(dev); + break; } /*ocp phy power saving*/ @@ -7020,8 +8715,8 @@ rtl8125_hw_phy_config(struct net_device *dev) rtl8125_mdio_write(tp, 0x1F, 0x0000); - if (tp->HwHasWrRamCodeToMicroP == TRUE) { - if (eee_enable == 1) + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + if (tp->eee_enabled == 1) rtl8125_enable_eee(tp); else rtl8125_disable_eee(tp); @@ -7089,12 +8784,13 @@ static void rtl8125_get_bios_setting(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - tp->bios_setting = RTL_R32(TimeInt2); + case CFG_METHOD_4: + case CFG_METHOD_5: + tp->bios_setting = RTL_R32(tp, TimeInt2); break; } } @@ -7103,12 +8799,13 @@ static void rtl8125_set_bios_setting(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W32(TimeInt2, tp->bios_setting); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W32(tp, TimeInt2, tp->bios_setting); break; } } @@ -7118,13 +8815,14 @@ rtl8125_init_software_variable(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); struct pci_dev *pdev = tp->pci_dev; - void __iomem *ioaddr = tp->mmio_addr; rtl8125_get_bios_setting(dev); switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: //tp->HwSuppDashVer = 3; break; default: @@ -7135,6 +8833,8 @@ rtl8125_init_software_variable(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: tp->HwPkgDet = rtl8125_mac_ocp_read(tp, 0xDC00); tp->HwPkgDet = (tp->HwPkgDet >> 3) & 0x07; break; @@ -7146,6 +8846,8 @@ rtl8125_init_software_variable(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: tp->HwSuppNowIsOobVer = 1; break; } @@ -7153,6 +8855,8 @@ rtl8125_init_software_variable(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: tp->HwPcieSNOffset = 0x16C; break; } @@ -7203,6 +8907,8 @@ rtl8125_init_software_variable(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: default: tp->intr_mask = RxDescUnavail | TxOK | RxOK | SWInt; tp->timer_intr_mask = PCSTimeout; @@ -7221,6 +8927,8 @@ rtl8125_init_software_variable(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: tp->org_pci_offset_99 = rtl8125_csi_fun0_read_byte(tp, 0x99); tp->org_pci_offset_99 &= ~(BIT_5|BIT_6); break; @@ -7229,6 +8937,10 @@ rtl8125_init_software_variable(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + tp->org_pci_offset_180 = rtl8125_csi_fun0_read_byte(tp, 0x264); + break; + case CFG_METHOD_4: + case CFG_METHOD_5: tp->org_pci_offset_180 = rtl8125_csi_fun0_read_byte(tp, 0x214); break; } @@ -7240,6 +8952,8 @@ rtl8125_init_software_variable(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: default: tp->use_timer_interrrupt = TRUE; break; @@ -7248,9 +8962,17 @@ rtl8125_init_software_variable(struct net_device *dev) if (timer_count == 0 || tp->mcfg == CFG_METHOD_DEFAULT) tp->use_timer_interrrupt = FALSE; + switch (tp->mcfg) { + default: + tp->SwPaddingShortPktLen = ETH_ZLEN; + break; + } + switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: tp->HwSuppMagicPktVer = WAKEUP_MAGIC_PACKET_V3; break; default: @@ -7261,6 +8983,8 @@ rtl8125_init_software_variable(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: tp->HwSuppCheckPhyDisableModeVer = 3; break; } @@ -7268,10 +8992,31 @@ rtl8125_init_software_variable(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: tp->HwSuppGigaForceMode = TRUE; break; } + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: + tp->HwSuppTxNoCloseVer = 3; + break; + } + + if (tp->HwSuppTxNoCloseVer > 0 && tx_no_close_enable == 1) + tp->EnableTxNoClose = TRUE; + + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + tp->RequireLSOPatch = TRUE; + break; + } + switch (tp->mcfg) { case CFG_METHOD_2: tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_2; @@ -7279,6 +9024,12 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_3: tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_3; break; + case CFG_METHOD_4: + tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_4; + break; + case CFG_METHOD_5: + tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_5; + break; } if (tp->HwIcVerUnknown) { @@ -7286,7 +9037,17 @@ rtl8125_init_software_variable(struct net_device *dev) tp->NotWrMcuPatchCode = TRUE; } - tp->NicCustLedValue = RTL_R16(CustomLED); + switch (tp->mcfg) { + case CFG_METHOD_3: + if ((rtl8125_mac_ocp_read(tp, 0xD442) & BIT_5) && + (mdio_direct_read_phy_ocp(tp, 0xD068) & BIT_1) + ) { + tp->RequirePhyMdiSwapPatch = TRUE; + } + break; + } + + tp->NicCustLedValue = RTL_R16(tp, CustomLED); rtl8125_get_hw_wol(dev); @@ -7303,14 +9064,16 @@ rtl8125_init_software_variable(struct net_device *dev) dev->min_mtu = ETH_ZLEN; dev->max_mtu = tp->max_jumbo_frame_size; #endif //LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) + tp->eee_enabled = eee_enable; + tp->eee_adv_t = MDIO_EEE_1000T | MDIO_EEE_100TX; } static void rtl8125_release_board(struct pci_dev *pdev, - struct net_device *dev, - void __iomem *ioaddr) + struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); + void __iomem *ioaddr = tp->mmio_addr; rtl8125_set_bios_setting(dev); rtl8125_rar_set(tp, tp->org_mac_addr); @@ -7337,17 +9100,18 @@ static int rtl8125_get_mac_address(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; int i; u8 mac_addr[MAC_ADDR_LEN]; for (i = 0; i < MAC_ADDR_LEN; i++) - mac_addr[i] = RTL_R8(MAC0 + i); + mac_addr[i] = RTL_R8(tp, MAC0 + i); if(tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3) { - *(u32*)&mac_addr[0] = RTL_R32(BACKUP_ADDR0_8125); - *(u16*)&mac_addr[4] = RTL_R16(BACKUP_ADDR1_8125); + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) { + *(u32*)&mac_addr[0] = RTL_R32(tp, BACKUP_ADDR0_8125); + *(u16*)&mac_addr[4] = RTL_R16(tp, BACKUP_ADDR1_8125); } if (!is_valid_ether_addr(mac_addr)) { @@ -7363,7 +9127,7 @@ rtl8125_get_mac_address(struct net_device *dev) rtl8125_rar_set(tp, mac_addr); for (i = 0; i < MAC_ADDR_LEN; i++) { - dev->dev_addr[i] = RTL_R8(MAC0 + i); + dev->dev_addr[i] = RTL_R8(tp, MAC0 + i); tp->org_mac_addr[i] = dev->dev_addr[i]; /* keep the original MAC address */ } #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) @@ -7413,7 +9177,6 @@ void rtl8125_rar_set(struct rtl8125_private *tp, uint8_t *addr) { - void __iomem *ioaddr = tp->mmio_addr; uint32_t rar_low = 0; uint32_t rar_high = 0; @@ -7426,8 +9189,8 @@ rtl8125_rar_set(struct rtl8125_private *tp, ((uint32_t) addr[5] << 8)); rtl8125_enable_cfg9346_write(tp); - RTL_W32(MAC0, rar_low); - RTL_W32(MAC4, rar_high); + RTL_W32(tp, MAC0, rar_low); + RTL_W32(tp, MAC4, rar_high); rtl8125_disable_cfg9346_write(tp); } @@ -8184,6 +9947,8 @@ rtl8125_phy_power_up(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_wait_phy_ups_resume(dev, 3); break; }; @@ -8320,8 +10085,10 @@ rtl8125_init_board(struct pci_dev *pdev, goto err_out_free_res; } + tp->mmio_addr = ioaddr; + /* Identify chip attached to board */ - rtl8125_get_mac_version(tp, ioaddr); + rtl8125_get_mac_version(tp); rtl8125_print_mac_version(tp); @@ -8638,7 +10405,6 @@ rtl8125_init_one(struct pci_dev *pdev, tp = netdev_priv(dev); assert(ioaddr != NULL); - tp->mmio_addr = ioaddr; tp->set_speed = rtl8125_set_speed_xmii; tp->get_settings = rtl8125_gset_xmii; tp->phy_reset_enable = rtl8125_xmii_reset_enable; @@ -8670,7 +10436,7 @@ rtl8125_init_one(struct pci_dev *pdev, } #endif - tp->cp_cmd |= RTL_R16(CPlusCmd); + tp->cp_cmd |= RTL_R16(tp, CPlusCmd); if (tp->mcfg != CFG_METHOD_DEFAULT) { dev->features |= NETIF_F_IP_CSUM; #if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) @@ -8722,11 +10488,12 @@ rtl8125_init_one(struct pci_dev *pdev, rtl8125_eeprom_type(tp); if (tp->eeprom_type == EEPROM_TYPE_93C46 || tp->eeprom_type == EEPROM_TYPE_93C56) - rtl8125_set_eeprom_sel_low(ioaddr); + rtl8125_set_eeprom_sel_low(tp); rtl8125_get_mac_address(dev); - tp->tally_vaddr = pci_alloc_consistent(pdev, sizeof(*tp->tally_vaddr), &tp->tally_paddr); + tp->tally_vaddr = dma_alloc_coherent(&pdev->dev, sizeof(*tp->tally_vaddr), + &tp->tally_paddr, GFP_KERNEL); if (!tp->tally_vaddr) { rc = -ENOMEM; goto err_out; @@ -8755,8 +10522,8 @@ out: err_out: if (tp->tally_vaddr != NULL) { - pci_free_consistent(pdev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, - tp->tally_paddr); + dma_free_coherent(&pdev->dev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, + tp->tally_paddr); tp->tally_vaddr = NULL; } @@ -8764,7 +10531,7 @@ err_out: RTL_NAPI_DEL(tp); #endif rtl8125_disable_msi(pdev, tp); - rtl8125_release_board(pdev, dev, ioaddr); + rtl8125_release_board(pdev, dev); goto out; } @@ -8790,11 +10557,11 @@ rtl8125_remove_one(struct pci_dev *pdev) rtl8125_proc_remove(dev); #endif if (tp->tally_vaddr != NULL) { - pci_free_consistent(pdev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, tp->tally_paddr); + dma_free_coherent(&pdev->dev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, tp->tally_paddr); tp->tally_vaddr = NULL; } - rtl8125_release_board(pdev, dev, tp->mmio_addr); + rtl8125_release_board(pdev, dev); pci_set_drvdata(pdev, NULL); } @@ -8824,19 +10591,19 @@ static int rtl8125_open(struct net_device *dev) * Rx and Tx descriptors needs 256 bytes alignment. * pci_alloc_consistent provides more. */ - tp->TxDescArray = pci_alloc_consistent(pdev, R8125_TX_RING_BYTES, - &tp->TxPhyAddr); + tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8125_TX_RING_BYTES, + &tp->TxPhyAddr, GFP_KERNEL); if (!tp->TxDescArray) goto err_free_all_allocated_mem; - tp->RxDescArray = pci_alloc_consistent(pdev, R8125_RX_RING_BYTES, - &tp->RxPhyAddr); + tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8125_RX_RING_BYTES, + &tp->RxPhyAddr, GFP_KERNEL); if (!tp->RxDescArray) goto err_free_all_allocated_mem; if (tp->UseSwPaddingShortPkt) { - tp->ShortPacketEmptyBuffer = pci_alloc_consistent(pdev, SHORT_PACKET_PADDING_BUF_SIZE, - &tp->ShortPacketEmptyBufferPhy); + tp->ShortPacketEmptyBuffer = dma_alloc_coherent(&pdev->dev, SHORT_PACKET_PADDING_BUF_SIZE, + &tp->ShortPacketEmptyBufferPhy, GFP_KERNEL); if (!tp->ShortPacketEmptyBuffer) goto err_free_all_allocated_mem; @@ -8905,20 +10672,20 @@ out: err_free_all_allocated_mem: if (tp->RxDescArray != NULL) { - pci_free_consistent(pdev, R8125_RX_RING_BYTES, tp->RxDescArray, - tp->RxPhyAddr); + dma_free_coherent(&pdev->dev, R8125_RX_RING_BYTES, tp->RxDescArray, + tp->RxPhyAddr); tp->RxDescArray = NULL; } if (tp->TxDescArray != NULL) { - pci_free_consistent(pdev, R8125_TX_RING_BYTES, tp->TxDescArray, - tp->TxPhyAddr); + dma_free_coherent(&pdev->dev, R8125_TX_RING_BYTES, tp->TxDescArray, + tp->TxPhyAddr); tp->TxDescArray = NULL; } if (tp->ShortPacketEmptyBuffer != NULL) { - pci_free_consistent(pdev, ETH_ZLEN, tp->ShortPacketEmptyBuffer, - tp->ShortPacketEmptyBufferPhy); + dma_free_coherent(&pdev->dev, ETH_ZLEN, tp->ShortPacketEmptyBuffer, + tp->ShortPacketEmptyBufferPhy); tp->ShortPacketEmptyBuffer = NULL; } @@ -8958,7 +10725,6 @@ static void rtl8125_hw_set_rx_packet_filter(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; u32 mc_filter[2]; /* Multicast hash filter */ int rx_mode; u32 tmp = 0; @@ -9012,11 +10778,11 @@ rtl8125_hw_set_rx_packet_filter(struct net_device *dev) mc_filter[1] = swab32(tmp); tp->rtl8125_rx_config = rtl_chip_info[tp->chipset].RCR_Cfg; - tmp = tp->rtl8125_rx_config | rx_mode | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); + tmp = tp->rtl8125_rx_config | rx_mode | (RTL_R32(tp, RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); - RTL_W32(RxConfig, tmp); - RTL_W32(MAR0 + 0, mc_filter[0]); - RTL_W32(MAR0 + 4, mc_filter[1]); + RTL_W32(tp, RxConfig, tmp); + RTL_W32(tp, MAR0 + 0, mc_filter[0]); + RTL_W32(tp, MAR0 + 4, mc_filter[1]); } static void @@ -9036,20 +10802,11 @@ static void rtl8125_hw_config(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; struct pci_dev *pdev = tp->pci_dev; u16 mac_ocp_data; int i; -#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) - if (dev->mtu > ETH_DATA_LEN) { - dev->features &= ~(NETIF_F_IP_CSUM); - } else { - dev->features |= NETIF_F_IP_CSUM; - } -#endif - - RTL_W32(RxConfig, (RX_DMA_BURST << RxCfgDMAShift)); + RTL_W32(tp, RxConfig, (RX_DMA_BURST << RxCfgDMAShift)); rtl8125_hw_reset(dev); @@ -9057,9 +10814,11 @@ rtl8125_hw_config(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7); - RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7); - RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7); + RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); break; } @@ -9067,16 +10826,20 @@ rtl8125_hw_config(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - RTL_W8(Config3, RTL_R8(Config3) & ~BIT_1); + case CFG_METHOD_4: + case CFG_METHOD_5: + RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~BIT_1); break; } switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: //IntMITI_0-IntMITI_31 for (i=0xA00; i<0xB00; i+=4) - RTL_W32(i, 0x00000000); + RTL_W32(tp, i, 0x00000000); break; } @@ -9084,8 +10847,10 @@ rtl8125_hw_config(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xC0B6); - mac_ocp_data &= ~(BIT_0); + mac_ocp_data &= BIT_0; rtl8125_mac_ocp_write(tp, 0xC0B6, mac_ocp_data); break; } @@ -9095,20 +10860,25 @@ rtl8125_hw_config(struct net_device *dev) rtl8125_desc_addr_fill(tp); /* Set DMA burst size and Interframe Gap Time */ - RTL_W32(TxConfig, (TX_DMA_BURST_unlimited << TxDMAShift) | + RTL_W32(tp, TxConfig, (TX_DMA_BURST_unlimited << TxDMAShift) | (InterFrameGap << TxInterFrameGapShift)); + if (tp->EnableTxNoClose) + RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) | BIT_6)); + if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3) { + tp->mcfg == CFG_METHOD_3 || + tp->mcfg == CFG_METHOD_4 || + tp->mcfg == CFG_METHOD_5) { set_offset70F(tp, 0x27); set_offset79(tp, 0x50); - RTL_W16(0x382, 0x221B); + RTL_W16(tp, 0x382, 0x221B); - RTL_W8(0x4500, 0x00); - RTL_W16(0x4800, 0x0000); + RTL_W8(tp, 0x4500, 0x00); + RTL_W16(tp, 0x4800, 0x0000); - RTL_W8(Config1, RTL_R8(Config1) & ~0x10); + RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); rtl8125_mac_ocp_write(tp, 0xC140, 0xFFFF); rtl8125_mac_ocp_write(tp, 0xC142, 0xFFFF); @@ -9133,10 +10903,14 @@ rtl8125_hw_config(struct net_device *dev) mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE614); mac_ocp_data &= ~( BIT_10 | BIT_9 | BIT_8); - if (tp->DASH && !(rtl8125_csi_fun0_read_byte(tp, 0x79) & BIT_0)) - mac_ocp_data |= ((3 & 0x07) << 8); - else - mac_ocp_data |= ((4 & 0x07) << 8); + if (tp->mcfg == CFG_METHOD_4 || tp->mcfg == CFG_METHOD_5) { + mac_ocp_data |= ((2 & 0x07) << 8); + } else { + if (tp->DASH && !(rtl8125_csi_fun0_read_byte(tp, 0x79) & BIT_0)) + mac_ocp_data |= ((3 & 0x07) << 8); + else + mac_ocp_data |= ((4 & 0x07) << 8); + } rtl8125_mac_ocp_write(tp, 0xE614, mac_ocp_data); mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE63E); @@ -9146,7 +10920,8 @@ rtl8125_hw_config(struct net_device *dev) mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE63E); mac_ocp_data &= ~(BIT_5 | BIT_4); - mac_ocp_data |= ((0x02 & 0x03) << 4); + if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3) + mac_ocp_data |= ((0x02 & 0x03) << 4); rtl8125_mac_ocp_write(tp, 0xE63E, mac_ocp_data); mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xC0B4); @@ -9168,14 +10943,19 @@ rtl8125_hw_config(struct net_device *dev) mac_ocp_data |= (BIT_4 | BIT_5); rtl8125_mac_ocp_write(tp, 0xE056, mac_ocp_data); - RTL_W8(TDFNR, 0x10); + RTL_W8(tp, TDFNR, 0x10); - //RTL_W8(0xD0, RTL_R8(0xD0) | BIT_7); + RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_7); mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE040); mac_ocp_data &= ~(BIT_12); rtl8125_mac_ocp_write(tp, 0xE040, mac_ocp_data); + mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xEA1C); + mac_ocp_data &= ~(BIT_1 | BIT_0); + mac_ocp_data |= (BIT_0); + rtl8125_mac_ocp_write(tp, 0xEA1C, mac_ocp_data); + mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE0C0); mac_ocp_data &= ~(BIT_14 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_3 | BIT_2 | BIT_1 | BIT_0); mac_ocp_data |= (BIT_14 | BIT_10 | BIT_1 | BIT_0); @@ -9196,9 +10976,17 @@ rtl8125_hw_config(struct net_device *dev) //rtl8125_mac_ocp_write(tp, 0xE0C0, 0x4F87); mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE84C); - mac_ocp_data |= (BIT_7 | BIT_6); + mac_ocp_data &= ~BIT_6; + if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3) + mac_ocp_data |= BIT_6; + mac_ocp_data |= BIT_7; rtl8125_mac_ocp_write(tp, 0xE84C, mac_ocp_data); + RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_6); + + if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3) + RTL_W8(tp, 0xD3, RTL_R8(tp, 0xD3) | BIT_0); + rtl8125_disable_eee_plus(tp); mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xEA1C); @@ -9208,7 +10996,7 @@ rtl8125_hw_config(struct net_device *dev) SetMcuAccessRegBit(tp, 0xEB54, BIT_0); udelay(1); ClearMcuAccessRegBit(tp, 0xEB54, BIT_0); - RTL_W16(0x1880, RTL_R16(0x1880)&~(BIT_4 | BIT_5)); + RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~(BIT_4 | BIT_5)); } /* csum offload command for RTL8125 */ @@ -9226,6 +11014,8 @@ rtl8125_hw_config(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: rtl8125_mac_ocp_write(tp, 0xE098, 0xC302); break; } @@ -9233,6 +11023,8 @@ rtl8125_hw_config(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: if (aspm) { rtl8125_init_pci_offset_99(tp); } @@ -9241,6 +11033,8 @@ rtl8125_hw_config(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: if (aspm) { rtl8125_init_pci_offset_180(tp); } @@ -9252,14 +11046,16 @@ rtl8125_hw_config(struct net_device *dev) ASF | Macdbgo_sel); #if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) - RTL_W16(CPlusCmd, tp->cp_cmd); + RTL_W16(tp, CPlusCmd, tp->cp_cmd); #else rtl8125_hw_set_features(dev, dev->features); #endif switch (tp->mcfg) { case CFG_METHOD_2: - case CFG_METHOD_3: { + case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: { int timeout; for (timeout = 0; timeout < 10; timeout++) { if ((rtl8125_mac_ocp_read(tp, 0xE00E) & BIT_13)==0) @@ -9270,7 +11066,7 @@ rtl8125_hw_config(struct net_device *dev) break; } - RTL_W16(RxMaxSize, tp->rx_buf_sz); + RTL_W16(tp, RxMaxSize, tp->rx_buf_sz); rtl8125_disable_rxdvgate(dev); @@ -9308,12 +11104,14 @@ rtl8125_hw_config(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: if (aspm) { - RTL_W8(Config5, RTL_R8(Config5) | BIT_0); - RTL_W8(Config2, RTL_R8(Config2) | BIT_7); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) | BIT_0); + RTL_W8(tp, Config2, RTL_R8(tp, Config2) | BIT_7); } else { - RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7); - RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0); + RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); } break; } @@ -9327,11 +11125,10 @@ static void rtl8125_hw_start(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; - RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); - rtl8125_enable_hw_interrupt(tp, ioaddr); + rtl8125_enable_hw_interrupt(tp); } @@ -9408,8 +11205,8 @@ rtl8125_free_rx_skb(struct rtl8125_private *tp, { struct pci_dev *pdev = tp->pci_dev; - pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, - PCI_DMA_FROMDEVICE); + dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), tp->rx_buf_sz, + DMA_FROM_DEVICE); dev_kfree_skb(*sk_buff); *sk_buff = NULL; rtl8125_make_unusable_by_asic(desc); @@ -9455,8 +11252,8 @@ rtl8125_alloc_rx_skb(struct rtl8125_private *tp, skb_reserve(skb, RTK_RX_ALIGN); - mapping = pci_map_single(tp->pci_dev, skb->data, rx_buf_sz, - PCI_DMA_FROMDEVICE); + mapping = dma_map_single(&tp->pci_dev->dev, skb->data, rx_buf_sz, + DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping))) { if (unlikely(net_ratelimit())) netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); @@ -9522,15 +11319,13 @@ rtl8125_mark_as_last_descriptor(struct RxDesc *desc) static void rtl8125_desc_addr_fill(struct rtl8125_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - if (!tp->TxPhyAddr || !tp->RxPhyAddr) return; - RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_BIT_MASK(32))); - RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32)); - RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_BIT_MASK(32))); - RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); + RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_BIT_MASK(32))); + RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32)); + RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_BIT_MASK(32))); + RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); } static void @@ -9584,8 +11379,9 @@ rtl8125_unmap_tx_skb(struct pci_dev *pdev, { unsigned int len = tx_skb->len; - pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); - desc->opts1 = 0x00; + dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); + + desc->opts1 = cpu_to_le32(RTK_MAGIC_DEBUG_VALUE); desc->opts2 = 0x00; desc->addr = 0x00; tx_skb->len = 0; @@ -9650,6 +11446,9 @@ static void rtl8125_schedule_work(struct net_device *dev, work_func_t task) static void rtl8125_cancel_schedule_work(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); + struct work_struct *work = &tp->task.work; + + if (!work->func) return; cancel_delayed_work_sync(&tp->task); } @@ -9659,7 +11458,6 @@ static void rtl8125_wait_for_quiescence(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; synchronize_irq(dev->irq); @@ -9670,7 +11468,7 @@ rtl8125_wait_for_quiescence(struct net_device *dev) #endif #endif//CONFIG_R8125_NAPI - rtl8125_irq_mask_and_ack(tp, ioaddr); + rtl8125_irq_mask_and_ack(tp); #ifdef CONFIG_R8125_NAPI #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) @@ -9737,9 +11535,9 @@ static void rtl8125_reset_task(struct work_struct *work) rtl8125_wait_for_quiescence(dev); #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) - rtl8125_rx_interrupt(dev, tp, tp->mmio_addr, &budget); + rtl8125_rx_interrupt(dev, tp, &budget); #else - rtl8125_rx_interrupt(dev, tp, tp->mmio_addr, budget); + rtl8125_rx_interrupt(dev, tp, budget); #endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) spin_lock_irqsave(&tp->lock, flags); @@ -9764,9 +11562,13 @@ static void rtl8125_reset_task(struct work_struct *work) rtl8125_schedule_work(dev, rtl8125_reset_task); } } - +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) +static void +rtl8125_tx_timeout(struct net_device *dev, unsigned int txqueue) +#else static void rtl8125_tx_timeout(struct net_device *dev) +#endif { struct rtl8125_private *tp = netdev_priv(dev); unsigned long flags; @@ -9781,6 +11583,17 @@ rtl8125_tx_timeout(struct net_device *dev) rtl8125_schedule_work(dev, rtl8125_reset_task); } +static u32 +rtl8125_get_txd_opts1(u32 opts1, u32 len, unsigned int entry) +{ + u32 status = opts1 | len; + + if (entry == NUM_TX_DESC - 1) + status |= RingEnd; + + return status; +} + static int rtl8125_xmit_frags(struct rtl8125_private *tp, struct sk_buff *skb, @@ -9792,6 +11605,7 @@ rtl8125_xmit_frags(struct rtl8125_private *tp, struct TxDesc *txd = NULL; const unsigned char nr_frags = info->nr_frags; unsigned long PktLenCnt = 0; + bool LsoPatchEnabled = FALSE; entry = tp->cur_tx; for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) { @@ -9810,12 +11624,13 @@ rtl8125_xmit_frags(struct rtl8125_private *tp, len = skb_frag_size(frag); addr = skb_frag_address(frag); #endif - if ((cur_frag == nr_frags - 1) && + if (tp->RequireLSOPatch && + (cur_frag == nr_frags - 1) && (opts1 & (GiantSendv4|GiantSendv6)) && PktLenCnt < ETH_FRAME_LEN && len > 1) { len -= 1; - mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); + mapping = dma_map_single(&tp->pci_dev->dev, addr, len, DMA_TO_DEVICE); if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping))) { if (unlikely(net_ratelimit())) @@ -9825,14 +11640,15 @@ rtl8125_xmit_frags(struct rtl8125_private *tp, } /* anti gcc 2.95.3 bugware (sic) */ - status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); + status = rtl8125_get_txd_opts1(opts1, len, entry); txd->addr = cpu_to_le64(mapping); tp->tx_skb[entry].len = len; - txd->opts1 = cpu_to_le32(status); txd->opts2 = cpu_to_le32(opts2); + wmb(); + txd->opts1 = cpu_to_le32(status); //second txd addr += len; @@ -9840,9 +11656,11 @@ rtl8125_xmit_frags(struct rtl8125_private *tp, entry = (entry + 1) % NUM_TX_DESC; txd = tp->TxDescArray + entry; cur_frag += 1; + + LsoPatchEnabled = TRUE; } - mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); + mapping = dma_map_single(&tp->pci_dev->dev, addr, len, DMA_TO_DEVICE); if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping))) { if (unlikely(net_ratelimit())) @@ -9852,24 +11670,23 @@ rtl8125_xmit_frags(struct rtl8125_private *tp, } /* anti gcc 2.95.3 bugware (sic) */ - status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); + status = rtl8125_get_txd_opts1(opts1, len, entry); + if (cur_frag == (nr_frags - 1) || LsoPatchEnabled == TRUE) { + tp->tx_skb[entry].skb = skb; + status |= LastFrag; + } txd->addr = cpu_to_le64(mapping); tp->tx_skb[entry].len = len; - txd->opts1 = cpu_to_le32(status); txd->opts2 = cpu_to_le32(opts2); + wmb(); + txd->opts1 = cpu_to_le32(status); PktLenCnt += len; } - if (cur_frag) { - tp->tx_skb[entry].skb = skb; - wmb(); - txd->opts1 |= cpu_to_le32(LastFrag); - } - return cur_frag; err_out: @@ -9949,7 +11766,9 @@ rtl8125_tx_csum(struct sk_buff *skb, } } - if (tp->ShortPacketSwChecksum && skb->len < 60 && csum_cmd != 0) + if (tp->ShortPacketSwChecksum && + skb->len < tp->SwPaddingShortPktLen && + csum_cmd != 0) sw_calc_csum = TRUE; if (sw_calc_csum) { @@ -9979,7 +11798,7 @@ rtl8125_sw_padding_short_pkt(struct rtl8125_private *tp, struct TxDesc *txd = NULL; int ret = 0; - if (skb->len >= ETH_ZLEN) + if (skb->len >= tp->SwPaddingShortPktLen) goto out; entry = tp->cur_tx; @@ -9987,9 +11806,9 @@ rtl8125_sw_padding_short_pkt(struct rtl8125_private *tp, entry = (entry + 1) % NUM_TX_DESC; txd = tp->TxDescArray + entry; - len = ETH_ZLEN - skb->len; + len = tp->SwPaddingShortPktLen - skb->len; addr = tp->ShortPacketEmptyBuffer; - mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); + mapping = dma_map_single(&tp->pci_dev->dev, addr, len, DMA_TO_DEVICE); if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping))) { if (unlikely(net_ratelimit())) netif_err(tp, drv, tp->dev, @@ -9997,15 +11816,14 @@ rtl8125_sw_padding_short_pkt(struct rtl8125_private *tp, ret = -ENOMEM; goto out; } - status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); + status = rtl8125_get_txd_opts1(opts1, len, entry); + status |= LastFrag; txd->addr = cpu_to_le64(mapping); - txd->opts1 = cpu_to_le32(status); txd->opts2 = cpu_to_le32(opts2); - wmb(); - txd->opts1 |= cpu_to_le32(LastFrag); + txd->opts1 = cpu_to_le32(status); out: return ret; } @@ -10074,6 +11892,15 @@ static int msdn_giant_send_check(struct sk_buff *skb) } #endif +static bool rtl8125_tx_slots_avail(struct rtl8125_private *tp, + unsigned int nr_frags) +{ + unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; + + /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ + return slots_avail > nr_frags; +} + static int rtl8125_start_xmit(struct sk_buff *skb, struct net_device *dev) @@ -10081,7 +11908,6 @@ rtl8125_start_xmit(struct sk_buff *skb, struct rtl8125_private *tp = netdev_priv(dev); unsigned int entry; struct TxDesc *txd; - void __iomem *ioaddr = tp->mmio_addr; dma_addr_t mapping; u32 len; u32 opts1; @@ -10089,10 +11915,11 @@ rtl8125_start_xmit(struct sk_buff *skb, int ret = NETDEV_TX_OK; unsigned long flags, large_send; int frags; + u8 EnableTxNoClose = tp->EnableTxNoClose; spin_lock_irqsave(&tp->lock, flags); - if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { + if (unlikely(!rtl8125_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) { if (netif_msg_drv(tp)) { printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n", @@ -10104,8 +11931,16 @@ rtl8125_start_xmit(struct sk_buff *skb, entry = tp->cur_tx % NUM_TX_DESC; txd = tp->TxDescArray + entry; - if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) - goto err_stop; + if (!EnableTxNoClose) { + if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) { + if (netif_msg_drv(tp)) { + printk(KERN_ERR + "%s: BUG! Tx Desc is own by hardware!\n", + dev->name); + } + goto err_stop; + } + } opts1 = DescOwn; opts2 = rtl8125_tx_vlan_tag(tp, skb); @@ -10176,7 +12011,7 @@ rtl8125_start_xmit(struct sk_buff *skb, tp->tx_skb[entry].skb = skb; - if (tp->UseSwPaddingShortPkt && len < 60) { + if (tp->UseSwPaddingShortPkt && len < tp->SwPaddingShortPktLen) { if (unlikely(rtl8125_sw_padding_short_pkt(tp, skb, opts1, opts2))) goto err_dma_1; opts1 |= FirstFrag; @@ -10186,8 +12021,8 @@ rtl8125_start_xmit(struct sk_buff *skb, } } - opts1 |= len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); - mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); + opts1 = rtl8125_get_txd_opts1(opts1, len, entry); + mapping = dma_map_single(&tp->pci_dev->dev, skb->data, len, DMA_TO_DEVICE); if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping))) { if (unlikely(net_ratelimit())) netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); @@ -10196,7 +12031,6 @@ rtl8125_start_xmit(struct sk_buff *skb, tp->tx_skb[entry].len = len; txd->addr = cpu_to_le64(mapping); txd->opts2 = cpu_to_le32(opts2); - txd->opts1 = cpu_to_le32(opts1&~DescOwn); wmb(); txd->opts1 = cpu_to_le32(opts1); @@ -10210,12 +12044,15 @@ rtl8125_start_xmit(struct sk_buff *skb, wmb(); - RTL_W16(TPPOLL_8125, BIT_0); /* set polling bit */ + if (EnableTxNoClose) + RTL_W16(tp, SW_TAIL_PTR0_8125, tp->cur_tx % MAX_TX_NO_CLOSE_DESC_PTR_V2); + else + RTL_W16(tp, TPPOLL_8125, BIT_0); /* set polling bit */ - if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { + if (!rtl8125_tx_slots_avail(tp, MAX_SKB_FRAGS)) { netif_stop_queue(dev); smp_rmb(); - if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) + if (rtl8125_tx_slots_avail(tp, MAX_SKB_FRAGS)) netif_wake_queue(dev); } @@ -10240,20 +12077,33 @@ err_stop: goto out; } +static u32 +rtl8125_fast_mod(const u32 input, const u32 ceil) +{ + return input >= ceil ? input % ceil : input; +} + static void rtl8125_tx_interrupt(struct net_device *dev, - struct rtl8125_private *tp, - void __iomem *ioaddr) + struct rtl8125_private *tp) { unsigned int dirty_tx, tx_left; + u8 EnableTxNoClose = tp->EnableTxNoClose; assert(dev != NULL); assert(tp != NULL); - assert(ioaddr != NULL); dirty_tx = tp->dirty_tx; - smp_rmb(); - tx_left = tp->cur_tx - dirty_tx; + if (EnableTxNoClose) { + u32 NextHwDesCloPtr0 = RTL_R16(tp, HW_CLO_PTR0_8125); + tp->NextHwDesCloPtr0 = NextHwDesCloPtr0; + smp_rmb(); + tx_left = rtl8125_fast_mod(NextHwDesCloPtr0 - tp->BeginHwDesCloPtr0, MAX_TX_NO_CLOSE_DESC_PTR_V2); + tp->BeginHwDesCloPtr0 = NextHwDesCloPtr0; + } else { + smp_rmb(); + tx_left = tp->cur_tx - dirty_tx; + } while (tx_left > 0) { unsigned int entry = dirty_tx % NUM_TX_DESC; @@ -10263,7 +12113,7 @@ rtl8125_tx_interrupt(struct net_device *dev, rmb(); status = le32_to_cpu(tp->TxDescArray[entry].opts1); - if (status & DescOwn) + if (!EnableTxNoClose && (status & DescOwn)) break; RTLDEV->stats.tx_bytes += len; @@ -10289,12 +12139,12 @@ rtl8125_tx_interrupt(struct net_device *dev, tp->dirty_tx = dirty_tx; smp_wmb(); if (netif_queue_stopped(dev) && - (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { + (rtl8125_tx_slots_avail(tp, MAX_SKB_FRAGS))) { netif_wake_queue(dev); } smp_rmb(); - if (tp->cur_tx != dirty_tx) { - RTL_W16(TPPOLL_8125, BIT_0); + if (!EnableTxNoClose && (tp->cur_tx != dirty_tx)) { + RTL_W16(tp, TPPOLL_8125, BIT_0); } } } @@ -10372,7 +12222,7 @@ rtl8125_rx_skb(struct rtl8125_private *tp, static int rtl8125_rx_interrupt(struct net_device *dev, struct rtl8125_private *tp, - void __iomem *ioaddr, napi_budget budget) + napi_budget budget) { unsigned int cur_rx, rx_left; unsigned int delta, count = 0; @@ -10383,7 +12233,6 @@ rtl8125_rx_interrupt(struct net_device *dev, assert(dev != NULL); assert(tp != NULL); - assert(ioaddr != NULL); if ((tp->RxDescArray == NULL) || (tp->Rx_skbuff == NULL)) goto rx_out; @@ -10420,8 +12269,6 @@ rtl8125_rx_interrupt(struct net_device *dev, } else { struct sk_buff *skb; int pkt_size; - void (*pci_action)(struct pci_dev *, dma_addr_t, - size_t, int); process_pkt: if (likely(!(dev->features & NETIF_F_RXFCS))) @@ -10442,22 +12289,23 @@ process_pkt: } skb = tp->Rx_skbuff[entry]; - if (tp->cp_cmd & RxChkSum) - rtl8125_rx_csum(tp, skb, desc); - pci_dma_sync_single_for_cpu(tp->pci_dev, - le64_to_cpu(desc->addr), tp->rx_buf_sz, - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&tp->pci_dev->dev, + le64_to_cpu(desc->addr), tp->rx_buf_sz, + DMA_FROM_DEVICE); - pci_action = pci_dma_sync_single_for_device; if (rtl8125_try_rx_copy(tp, &skb, pkt_size, desc, tp->rx_buf_sz)) { - pci_action = pci_unmap_single; tp->Rx_skbuff[entry] = NULL; + dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), + tp->rx_buf_sz, DMA_FROM_DEVICE); + } else { + dma_sync_single_for_device(&tp->pci_dev->dev, le64_to_cpu(desc->addr), + tp->rx_buf_sz, DMA_FROM_DEVICE); } - pci_action(tp->pci_dev, le64_to_cpu(desc->addr), - tp->rx_buf_sz, PCI_DMA_FROMDEVICE); + if (tp->cp_cmd & RxChkSum) + rtl8125_rx_csum(tp, skb, desc); skb->dev = dev; skb_put(skb, pkt_size); @@ -10517,12 +12365,11 @@ static irqreturn_t rtl8125_interrupt(int irq, void *dev_instance) { struct net_device *dev = (struct net_device *) dev_instance; struct rtl8125_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; u32 status; int handled = 0; do { - status = RTL_R32(ISR0_8125); + status = RTL_R32(tp, ISR0_8125); if (!(tp->features & RTL_FEATURE_MSI)) { /* hotplug/major error/no more work/shared irq */ @@ -10538,9 +12385,9 @@ static irqreturn_t rtl8125_interrupt(int irq, void *dev_instance) handled = 1; - rtl8125_disable_hw_interrupt(tp, ioaddr); + rtl8125_disable_hw_interrupt(tp); - RTL_W32(ISR0_8125, status&~RxFIFOOver); + RTL_W32(tp, ISR0_8125, status&~RxFIFOOver); #ifdef ENABLE_DASH_SUPPORT if (tp->DASH) { @@ -10550,7 +12397,7 @@ static irqreturn_t rtl8125_interrupt(int irq, void *dev_instance) if (status & ISRIMR_DASH_INTR_CMAC_RESET) tp->CmacResetIntr = TRUE; - DashIntType2Status = RTL_CMAC_R8(CMAC_IBISR0); + DashIntType2Status = RTL_CMAC_R8(tp, CMAC_IBISR0); if (DashIntType2Status & ISRIMR_DASH_TYPE2_ROK) { tp->RcvFwDashOkEvt = TRUE; } @@ -10561,7 +12408,7 @@ static irqreturn_t rtl8125_interrupt(int irq, void *dev_instance) tp->DashFwDisableRx = TRUE; } - RTL_CMAC_W8(CMAC_IBISR0, DashIntType2Status); + RTL_CMAC_W8(tp, CMAC_IBISR0, DashIntType2Status); } } #endif @@ -10578,7 +12425,7 @@ static irqreturn_t rtl8125_interrupt(int irq, void *dev_instance) dev->name, status); } else { tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT; - rtl8125_switch_to_hw_interrupt(tp, ioaddr); + rtl8125_switch_to_hw_interrupt(tp); } #else if (status & tp->intr_mask || tp->keep_intr_cnt-- > 0) { @@ -10587,11 +12434,11 @@ static irqreturn_t rtl8125_interrupt(int irq, void *dev_instance) if (status & tp->intr_mask) tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT; #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) - rtl8125_rx_interrupt(dev, tp, tp->mmio_addr, &budget); + rtl8125_rx_interrupt(dev, tp, &budget); #else - rtl8125_rx_interrupt(dev, tp, tp->mmio_addr, budget); + rtl8125_rx_interrupt(dev, tp, budget); #endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) - rtl8125_tx_interrupt(dev, tp, ioaddr); + rtl8125_tx_interrupt(dev, tp); #ifdef ENABLE_DASH_SUPPORT if (tp->DASH) { @@ -10601,10 +12448,10 @@ static irqreturn_t rtl8125_interrupt(int irq, void *dev_instance) } #endif - rtl8125_switch_to_timer_interrupt(tp, ioaddr); + rtl8125_switch_to_timer_interrupt(tp); } else { tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT; - rtl8125_switch_to_hw_interrupt(tp, ioaddr); + rtl8125_switch_to_hw_interrupt(tp); } #endif @@ -10617,16 +12464,15 @@ static irqreturn_t rtl8125_interrupt(int irq, void *dev_instance) static int rtl8125_poll(napi_ptr napi, napi_budget budget) { struct rtl8125_private *tp = RTL_GET_PRIV(napi, struct rtl8125_private); - void __iomem *ioaddr = tp->mmio_addr; RTL_GET_NETDEV(tp) unsigned int work_to_do = RTL_NAPI_QUOTA(budget, dev); unsigned int work_done; unsigned long flags; - work_done = rtl8125_rx_interrupt(dev, tp, ioaddr, budget); + work_done = rtl8125_rx_interrupt(dev, tp, budget); spin_lock_irqsave(&tp->lock, flags); - rtl8125_tx_interrupt(dev, tp, ioaddr); + rtl8125_tx_interrupt(dev, tp); spin_unlock_irqrestore(&tp->lock, flags); RTL_NAPI_QUOTA_UPDATE(dev, work_done, budget); @@ -10655,7 +12501,7 @@ static int rtl8125_poll(napi_ptr napi, napi_budget budget) */ smp_wmb(); - rtl8125_switch_to_timer_interrupt(tp, ioaddr); + rtl8125_switch_to_timer_interrupt(tp); } return RTL_NAPI_RETURN_VALUE; @@ -10724,16 +12570,16 @@ static int rtl8125_close(struct net_device *dev) free_irq(dev->irq, dev); - pci_free_consistent(pdev, R8125_RX_RING_BYTES, tp->RxDescArray, - tp->RxPhyAddr); - pci_free_consistent(pdev, R8125_TX_RING_BYTES, tp->TxDescArray, - tp->TxPhyAddr); + dma_free_coherent(&pdev->dev, R8125_RX_RING_BYTES, tp->RxDescArray, + tp->RxPhyAddr); + dma_free_coherent(&pdev->dev, R8125_TX_RING_BYTES, tp->TxDescArray, + tp->TxPhyAddr); tp->TxDescArray = NULL; tp->RxDescArray = NULL; if (tp->ShortPacketEmptyBuffer != NULL) { - pci_free_consistent(pdev, SHORT_PACKET_PADDING_BUF_SIZE, tp->ShortPacketEmptyBuffer, - tp->ShortPacketEmptyBufferPhy); + dma_free_coherent(&pdev->dev, SHORT_PACKET_PADDING_BUF_SIZE, tp->ShortPacketEmptyBuffer, + tp->ShortPacketEmptyBufferPhy); tp->ShortPacketEmptyBuffer = NULL; } } else { diff --git a/package/lean/r8125/src/r8125_realwow.h b/package/lean/r8125/src/r8125_realwow.h index 982530091..c42e1118e 100644 --- a/package/lean/r8125/src/r8125_realwow.h +++ b/package/lean/r8125/src/r8125_realwow.h @@ -4,7 +4,7 @@ # r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free diff --git a/package/lean/r8125/src/rtl_eeprom.c b/package/lean/r8125/src/rtl_eeprom.c index 596548777..3f1eb98bd 100644 --- a/package/lean/r8125/src/rtl_eeprom.c +++ b/package/lean/r8125/src/rtl_eeprom.c @@ -4,7 +4,7 @@ # r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -52,18 +52,17 @@ //------------------------------------------------------------------- void rtl8125_eeprom_type(struct rtl8125_private *tp) { - void __iomem *ioaddr=tp->mmio_addr; u16 magic = 0; if (tp->mcfg == CFG_METHOD_DEFAULT) goto out_no_eeprom; - if(RTL_R8(0xD2)&0x04) { + if(RTL_R8(tp, 0xD2)&0x04) { //not support //tp->eeprom_type = EEPROM_TWSI; //tp->eeprom_len = 256; goto out_no_eeprom; - } else if(RTL_R32(RxConfig) & RxCfg_9356SEL) { + } else if(RTL_R32(tp, RxConfig) & RxCfg_9356SEL) { tp->eeprom_type = EEPROM_TYPE_93C56; tp->eeprom_len = 256; } else { @@ -80,28 +79,28 @@ out_no_eeprom: } } -void rtl8125_eeprom_cleanup(void __iomem *ioaddr) +void rtl8125_eeprom_cleanup(struct rtl8125_private *tp) { u8 x; - x = RTL_R8(Cfg9346); + x = RTL_R8(tp, Cfg9346); x &= ~(Cfg9346_EEDI | Cfg9346_EECS); - RTL_W8(Cfg9346, x); + RTL_W8(tp, Cfg9346, x); - rtl8125_raise_clock(&x, ioaddr); - rtl8125_lower_clock(&x, ioaddr); + rtl8125_raise_clock(tp, &x); + rtl8125_lower_clock(tp, &x); } -int rtl8125_eeprom_cmd_done(void __iomem *ioaddr) +int rtl8125_eeprom_cmd_done(struct rtl8125_private *tp) { u8 x; int i; - rtl8125_stand_by(ioaddr); + rtl8125_stand_by(tp); for (i = 0; i < 50000; i++) { - x = RTL_R8(Cfg9346); + x = RTL_R8(tp, Cfg9346); if (x & Cfg9346_EEDO) { udelay(RTL_CLOCK_RATE * 2 * 3); @@ -119,7 +118,6 @@ int rtl8125_eeprom_cmd_done(void __iomem *ioaddr) //------------------------------------------------------------------- u16 rtl8125_eeprom_read_sc(struct rtl8125_private *tp, u16 reg) { - void __iomem *ioaddr=tp->mmio_addr; int addr_sz = 6; u8 x; u16 data; @@ -134,16 +132,16 @@ u16 rtl8125_eeprom_read_sc(struct rtl8125_private *tp, u16 reg) addr_sz = 8; x = Cfg9346_EEM1 | Cfg9346_EECS; - RTL_W8(Cfg9346, x); + RTL_W8(tp, Cfg9346, x); - rtl8125_shift_out_bits(RTL_EEPROM_READ_OPCODE, 3, ioaddr); - rtl8125_shift_out_bits(reg, addr_sz, ioaddr); + rtl8125_shift_out_bits(tp, RTL_EEPROM_READ_OPCODE, 3); + rtl8125_shift_out_bits(tp, reg, addr_sz); - data = rtl8125_shift_in_bits(ioaddr); + data = rtl8125_shift_in_bits(tp); - rtl8125_eeprom_cleanup(ioaddr); + rtl8125_eeprom_cleanup(tp); - RTL_W8(Cfg9346, 0); + RTL_W8(tp, Cfg9346, 0); return data; } @@ -154,7 +152,6 @@ u16 rtl8125_eeprom_read_sc(struct rtl8125_private *tp, u16 reg) //------------------------------------------------------------------- void rtl8125_eeprom_write_sc(struct rtl8125_private *tp, u16 reg, u16 data) { - void __iomem *ioaddr=tp->mmio_addr; u8 x; int addr_sz = 6; int w_dummy_addr = 4; @@ -172,56 +169,56 @@ void rtl8125_eeprom_write_sc(struct rtl8125_private *tp, u16 reg, u16 data) } x = Cfg9346_EEM1 | Cfg9346_EECS; - RTL_W8(Cfg9346, x); + RTL_W8(tp, Cfg9346, x); - rtl8125_shift_out_bits(RTL_EEPROM_EWEN_OPCODE, 5, ioaddr); - rtl8125_shift_out_bits(reg, w_dummy_addr, ioaddr); - rtl8125_stand_by(ioaddr); + rtl8125_shift_out_bits(tp, RTL_EEPROM_EWEN_OPCODE, 5); + rtl8125_shift_out_bits(tp, reg, w_dummy_addr); + rtl8125_stand_by(tp); - rtl8125_shift_out_bits(RTL_EEPROM_ERASE_OPCODE, 3, ioaddr); - rtl8125_shift_out_bits(reg, addr_sz, ioaddr); - if (rtl8125_eeprom_cmd_done(ioaddr) < 0) { + rtl8125_shift_out_bits(tp, RTL_EEPROM_ERASE_OPCODE, 3); + rtl8125_shift_out_bits(tp, reg, addr_sz); + if (rtl8125_eeprom_cmd_done(tp) < 0) { return; } - rtl8125_stand_by(ioaddr); + rtl8125_stand_by(tp); - rtl8125_shift_out_bits(RTL_EEPROM_WRITE_OPCODE, 3, ioaddr); - rtl8125_shift_out_bits(reg, addr_sz, ioaddr); - rtl8125_shift_out_bits(data, 16, ioaddr); - if (rtl8125_eeprom_cmd_done(ioaddr) < 0) { + rtl8125_shift_out_bits(tp, RTL_EEPROM_WRITE_OPCODE, 3); + rtl8125_shift_out_bits(tp, reg, addr_sz); + rtl8125_shift_out_bits(tp, data, 16); + if (rtl8125_eeprom_cmd_done(tp) < 0) { return; } - rtl8125_stand_by(ioaddr); + rtl8125_stand_by(tp); - rtl8125_shift_out_bits(RTL_EEPROM_EWDS_OPCODE, 5, ioaddr); - rtl8125_shift_out_bits(reg, w_dummy_addr, ioaddr); + rtl8125_shift_out_bits(tp, RTL_EEPROM_EWDS_OPCODE, 5); + rtl8125_shift_out_bits(tp, reg, w_dummy_addr); - rtl8125_eeprom_cleanup(ioaddr); - RTL_W8(Cfg9346, 0); + rtl8125_eeprom_cleanup(tp); + RTL_W8(tp, Cfg9346, 0); } -void rtl8125_raise_clock(u8 *x, void __iomem *ioaddr) +void rtl8125_raise_clock(struct rtl8125_private *tp, u8 *x) { *x = *x | Cfg9346_EESK; - RTL_W8(Cfg9346, *x); + RTL_W8(tp, Cfg9346, *x); udelay(RTL_CLOCK_RATE); } -void rtl8125_lower_clock(u8 *x, void __iomem *ioaddr) +void rtl8125_lower_clock(struct rtl8125_private *tp, u8 *x) { *x = *x & ~Cfg9346_EESK; - RTL_W8(Cfg9346, *x); + RTL_W8(tp, Cfg9346, *x); udelay(RTL_CLOCK_RATE); } -void rtl8125_shift_out_bits(int data, int count, void __iomem *ioaddr) +void rtl8125_shift_out_bits(struct rtl8125_private *tp, int data, int count) { u8 x; int mask; mask = 0x01 << (count - 1); - x = RTL_R8(Cfg9346); + x = RTL_R8(tp, Cfg9346); x &= ~(Cfg9346_EEDI | Cfg9346_EEDO); do { @@ -230,62 +227,62 @@ void rtl8125_shift_out_bits(int data, int count, void __iomem *ioaddr) else x &= ~Cfg9346_EEDI; - RTL_W8(Cfg9346, x); + RTL_W8(tp, Cfg9346, x); udelay(RTL_CLOCK_RATE); - rtl8125_raise_clock(&x, ioaddr); - rtl8125_lower_clock(&x, ioaddr); + rtl8125_raise_clock(tp, &x); + rtl8125_lower_clock(tp, &x); mask = mask >> 1; } while(mask); x &= ~Cfg9346_EEDI; - RTL_W8(Cfg9346, x); + RTL_W8(tp, Cfg9346, x); } -u16 rtl8125_shift_in_bits(void __iomem *ioaddr) +u16 rtl8125_shift_in_bits(struct rtl8125_private *tp) { u8 x; u16 d, i; - x = RTL_R8(Cfg9346); + x = RTL_R8(tp, Cfg9346); x &= ~(Cfg9346_EEDI | Cfg9346_EEDO); d = 0; for (i = 0; i < 16; i++) { d = d << 1; - rtl8125_raise_clock(&x, ioaddr); + rtl8125_raise_clock(tp, &x); - x = RTL_R8(Cfg9346); + x = RTL_R8(tp, Cfg9346); x &= ~Cfg9346_EEDI; if (x & Cfg9346_EEDO) d |= 1; - rtl8125_lower_clock(&x, ioaddr); + rtl8125_lower_clock(tp, &x); } return d; } -void rtl8125_stand_by(void __iomem *ioaddr) +void rtl8125_stand_by(struct rtl8125_private *tp) { u8 x; - x = RTL_R8(Cfg9346); + x = RTL_R8(tp, Cfg9346); x &= ~(Cfg9346_EECS | Cfg9346_EESK); - RTL_W8(Cfg9346, x); + RTL_W8(tp, Cfg9346, x); udelay(RTL_CLOCK_RATE); x |= Cfg9346_EECS; - RTL_W8(Cfg9346, x); + RTL_W8(tp, Cfg9346, x); } -void rtl8125_set_eeprom_sel_low(void __iomem *ioaddr) +void rtl8125_set_eeprom_sel_low(struct rtl8125_private *tp) { - RTL_W8(Cfg9346, Cfg9346_EEM1); - RTL_W8(Cfg9346, Cfg9346_EEM1 | Cfg9346_EESK); + RTL_W8(tp, Cfg9346, Cfg9346_EEM1); + RTL_W8(tp, Cfg9346, Cfg9346_EEM1 | Cfg9346_EESK); udelay(20); - RTL_W8(Cfg9346, Cfg9346_EEM1); + RTL_W8(tp, Cfg9346, Cfg9346_EEM1); } diff --git a/package/lean/r8125/src/rtl_eeprom.h b/package/lean/r8125/src/rtl_eeprom.h index 36cdd1bc6..e8d55091b 100644 --- a/package/lean/r8125/src/rtl_eeprom.h +++ b/package/lean/r8125/src/rtl_eeprom.h @@ -4,7 +4,7 @@ # r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -41,15 +41,12 @@ #define RTL_CLOCK_RATE 3 void rtl8125_eeprom_type(struct rtl8125_private *tp); -void rtl8125_eeprom_cleanup(void __iomem *ioaddr); +void rtl8125_eeprom_cleanup(struct rtl8125_private *tp); u16 rtl8125_eeprom_read_sc(struct rtl8125_private *tp, u16 reg); void rtl8125_eeprom_write_sc(struct rtl8125_private *tp, u16 reg, u16 data); -void rtl8125_shift_out_bits(int data, int count, void __iomem *ioaddr); -u16 rtl8125_shift_in_bits(void __iomem *ioaddr); -void rtl8125_raise_clock(u8 *x, void __iomem *ioaddr); -void rtl8125_lower_clock(u8 *x, void __iomem *ioaddr); -void rtl8125_stand_by(void __iomem *ioaddr); -void rtl8125_set_eeprom_sel_low(void __iomem *ioaddr); - - - +void rtl8125_shift_out_bits(struct rtl8125_private *tp, int data, int count); +u16 rtl8125_shift_in_bits(struct rtl8125_private *tp); +void rtl8125_raise_clock(struct rtl8125_private *tp, u8 *x); +void rtl8125_lower_clock(struct rtl8125_private *tp, u8 *x); +void rtl8125_stand_by(struct rtl8125_private *tp); +void rtl8125_set_eeprom_sel_low(struct rtl8125_private *tp); diff --git a/package/lean/r8125/src/rtltool.c b/package/lean/r8125/src/rtltool.c index a0a7dbba9..614fd91e1 100644 --- a/package/lean/r8125/src/rtltool.c +++ b/package/lean/r8125/src/rtltool.c @@ -4,7 +4,7 @@ # r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -121,7 +121,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr) return -EPERM; spin_lock_irqsave(&tp->lock, flags); - my_cmd.data = rtl8125_ephy_read(tp->mmio_addr, my_cmd.offset); + my_cmd.data = rtl8125_ephy_read(tp, my_cmd.offset); spin_unlock_irqrestore(&tp->lock, flags); if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { @@ -136,7 +136,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr) return -EPERM; spin_lock_irqsave(&tp->lock, flags); - rtl8125_ephy_write(tp->mmio_addr, my_cmd.offset, my_cmd.data); + rtl8125_ephy_write(tp, my_cmd.offset, my_cmd.data); spin_unlock_irqrestore(&tp->lock, flags); break; @@ -144,7 +144,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr) my_cmd.data = 0; if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) { spin_lock_irqsave(&tp->lock, flags); - my_cmd.data = rtl8125_eri_read(tp->mmio_addr, my_cmd.offset, my_cmd.len, ERIAR_ExGMAC); + my_cmd.data = rtl8125_eri_read(tp, my_cmd.offset, my_cmd.len, ERIAR_ExGMAC); spin_unlock_irqrestore(&tp->lock, flags); } else { ret = -EOPNOTSUPP; @@ -167,7 +167,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr) if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) { spin_lock_irqsave(&tp->lock, flags); - rtl8125_eri_write(tp->mmio_addr, my_cmd.offset, my_cmd.len, my_cmd.data, ERIAR_ExGMAC); + rtl8125_eri_write(tp, my_cmd.offset, my_cmd.len, my_cmd.data, ERIAR_ExGMAC); spin_unlock_irqrestore(&tp->lock, flags); } else { ret = -EOPNOTSUPP; @@ -330,7 +330,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr) return -EPERM; spin_lock_irqsave(&tp->lock, flags); - my_cmd.data = rtl8125_mdio_prot_read_phy_ocp(tp, my_cmd.offset); + my_cmd.data = rtl8125_mdio_prot_direct_read_phy_ocp(tp, my_cmd.offset); spin_unlock_irqrestore(&tp->lock, flags); if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { @@ -345,7 +345,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr) return -EPERM; spin_lock_irqsave(&tp->lock, flags); - rtl8125_mdio_prot_write_phy_ocp(tp, my_cmd.offset, my_cmd.data); + rtl8125_mdio_prot_direct_write_phy_ocp(tp, my_cmd.offset, my_cmd.data); spin_unlock_irqrestore(&tp->lock, flags); break; diff --git a/package/lean/r8125/src/rtltool.h b/package/lean/r8125/src/rtltool.h index c70594eb8..97e22a4c1 100644 --- a/package/lean/r8125/src/rtltool.h +++ b/package/lean/r8125/src/rtltool.h @@ -4,7 +4,7 @@ # r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free