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mediatek: fix mt7981 clk clock support

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This commit is contained in:
coolsnowwolf 2022-11-18 03:36:57 +08:00
parent cce06e82a4
commit a01f34b7be
1 changed files with 21 additions and 21 deletions
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42
target/linux/mediatek/patches-5.15/951-add-mt7981-clock-support.patch
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@ -64,7 +64,7 @@ index 000000000000..b517d20b5fde
+#include "clk-gate.h"
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-pll.h"
+
+
+#include <dt-bindings/clock/mt7981-clk.h>
+#include <linux/clk.h>
@ -117,7 +117,7 @@ index 000000000000..b517d20b5fde
+
+static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
@ -127,9 +127,9 @@ index 000000000000..b517d20b5fde
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
+ clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r) {
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
@ -243,7 +243,7 @@ index 000000000000..36f0fa222675
+
+static void __init mtk_sgmiisys_0_init(struct device_node *node)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
@ -251,7 +251,7 @@ index 000000000000..36f0fa222675
+ mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
+ clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
@ -261,7 +261,7 @@ index 000000000000..36f0fa222675
+
+static void __init mtk_sgmiisys_1_init(struct device_node *node)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
@ -269,7 +269,7 @@ index 000000000000..36f0fa222675
+ mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
+ clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
@ -280,14 +280,14 @@ index 000000000000..36f0fa222675
+
+static void __init mtk_ethsys_init(struct device_node *node)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
+
+ mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
@ -364,7 +364,7 @@ index 000000000000..d483e654606f
+
+static int clk_mt7981_infracfg_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int nr = ARRAY_SIZE(infra_divs);
+ void __iomem *base;
@ -383,7 +383,7 @@ index 000000000000..d483e654606f
+
+ mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r) {
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
@ -574,7 +574,7 @@ index 000000000000..d483e654606f
+
+static int clk_mt7981_infracfg_ao_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks);
+ void __iomem *base;
@ -596,7 +596,7 @@ index 000000000000..d483e654606f
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r) {
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
@ -1005,7 +1005,7 @@ index 000000000000..a136c0b36469
+
+static int clk_mt7981_topckgen_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+ void __iomem *base;
@ -1027,13 +1027,13 @@ index 000000000000..a136c0b36469
+ mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
+ base, &mt7981_clk_lock, clk_data);
+
+ clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
+ clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
+ clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
+ clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
+ clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
+ clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
+ clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
+ clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
+ clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
+ clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r) {
+ pr_err("%s(): could not register clock provider: %d\n",