From 9a50fdefc90ec473251c78a1f2b62b5d208ed5b4 Mon Sep 17 00:00:00 2001 From: KLT007 <84753324+KLT007@users.noreply.github.com> Date: Wed, 20 Oct 2021 17:24:04 +0800 Subject: [PATCH] rockchip:add arm64-dts-doornet1-add-rk3328-dmc-relate-node (#8092) * Delete 809-arm64-dts-DoorNet1-add-dmc-and-dram-timing.patch * Add files via upload * Update 809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch --- ...dts-DoorNet1-add-dmc-and-dram-timing.patch | 428 ------------------ ...-doornet1-add-rk3328-dmc-relate-node.patch | 124 +++++ 2 files changed, 124 insertions(+), 428 deletions(-) delete mode 100644 target/linux/rockchip/patches-5.4/809-arm64-dts-DoorNet1-add-dmc-and-dram-timing.patch create mode 100644 target/linux/rockchip/patches-5.4/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch diff --git a/target/linux/rockchip/patches-5.4/809-arm64-dts-DoorNet1-add-dmc-and-dram-timing.patch b/target/linux/rockchip/patches-5.4/809-arm64-dts-DoorNet1-add-dmc-and-dram-timing.patch deleted file mode 100644 index d993083b2..000000000 --- a/target/linux/rockchip/patches-5.4/809-arm64-dts-DoorNet1-add-dmc-and-dram-timing.patch +++ /dev/null @@ -1,428 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts -@@ -7,6 +7,7 @@ - - #include - #include -+#include "rk3328-dram-default-timing.dtsi" - #include "rk3328.dtsi" - - / { -@@ -120,6 +121,82 @@ - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -+ -+ dmc: dmc { -+ compatible = "rockchip,rk3328-dmc"; -+ devfreq-events = <&dfi>; -+ center-supply = <&vdd_log>; -+ clocks = <&cru SCLK_DDRCLK>; -+ clock-names = "dmc_clk"; -+ operating-points-v2 = <&dmc_opp_table>; -+ ddr_timing = <&ddr_timing>; -+ upthreshold = <40>; -+ downdifferential = <20>; -+ auto-min-freq = <786000>; -+ auto-freq-en = <1>; -+ #cooling-cells = <2>; -+ status = "okay"; -+ -+ ddr_power_model: ddr_power_model { -+ compatible = "ddr_power_model"; -+ dynamic-power-coefficient = <120>; -+ static-power-coefficient = <200>; -+ ts = <32000 4700 (-80) 2>; -+ thermal-zone = "soc-thermal"; -+ }; -+ }; -+ -+ dmc_opp_table: dmc-opp-table { -+ compatible = "operating-points-v2"; -+ -+ rockchip,leakage-voltage-sel = < -+ 1 10 0 -+ 11 254 1 -+ >; -+ nvmem-cells = <&logic_leakage>; -+ nvmem-cell-names = "ddr_leakage"; -+ -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <950000>; -+ opp-microvolt-L0 = <950000>; -+ opp-microvolt-L1 = <950000>; -+ }; -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <1025000>; -+ opp-microvolt-L0 = <1025000>; -+ opp-microvolt-L1 = <1000000>; -+ }; -+ opp-786000000 { -+ opp-hz = /bits/ 64 <786000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-840000000 { -+ opp-hz = /bits/ 64 <840000000>; -+ opp-microvolt = <1075000>; -+ opp-microvolt-L0 = <1075000>; -+ opp-microvolt-L1 = <1050000>; -+ }; -+ opp-924000000 { -+ opp-hz = /bits/ 64 <924000000>; -+ opp-microvolt = <1125000>; -+ opp-microvolt-L0 = <1125000>; -+ opp-microvolt-L1 = <1100000>; -+ }; -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1175000>; -+ opp-microvolt-L0 = <1175000>; -+ opp-microvolt-L1 = <1150000>; -+ }; -+ }; -+}; -+ -+&dfi { -+ status = "okay"; - }; - - &cpu0 { -@@ -201,6 +278,7 @@ - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1075000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; -@@ -215,6 +293,7 @@ - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; -+ regulator-init-microvolt = <1225000>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; -@@ -419,3 +498,4 @@ - realtek,led-data = <0x87>; - }; - }; -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi -@@ -0,0 +1,311 @@ -+/* -+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+#include -+#include -+ -+/ { -+ ddr_timing: ddr_timing { -+ compatible = "rockchip,ddr-timing"; -+ ddr3_speed_bin = ; -+ ddr4_speed_bin = ; -+ pd_idle = <0>; -+ sr_idle = <0>; -+ sr_mc_gate_idle = <0>; -+ srpd_lite_idle = <0>; -+ standby_idle = <0>; -+ -+ auto_pd_dis_freq = <1066>; -+ auto_sr_dis_freq = <800>; -+ ddr3_dll_dis_freq = <300>; -+ ddr4_dll_dis_freq = <625>; -+ phy_dll_dis_freq = <400>; -+ -+ ddr3_odt_dis_freq = <100>; -+ phy_ddr3_odt_dis_freq = <100>; -+ ddr3_drv = ; -+ ddr3_odt = ; -+ phy_ddr3_ca_drv = ; -+ phy_ddr3_ck_drv = ; -+ phy_ddr3_dq_drv = ; -+ phy_ddr3_odt = ; -+ -+ lpddr3_odt_dis_freq = <666>; -+ phy_lpddr3_odt_dis_freq = <666>; -+ lpddr3_drv = ; -+ lpddr3_odt = ; -+ phy_lpddr3_ca_drv = ; -+ phy_lpddr3_ck_drv = ; -+ phy_lpddr3_dq_drv = ; -+ phy_lpddr3_odt = ; -+ -+ lpddr4_odt_dis_freq = <800>; -+ phy_lpddr4_odt_dis_freq = <800>; -+ lpddr4_drv = ; -+ lpddr4_dq_odt = ; -+ lpddr4_ca_odt = ; -+ phy_lpddr4_ca_drv = ; -+ phy_lpddr4_ck_cs_drv = ; -+ phy_lpddr4_dq_drv = ; -+ phy_lpddr4_odt = ; -+ -+ ddr4_odt_dis_freq = <666>; -+ phy_ddr4_odt_dis_freq = <666>; -+ ddr4_drv = ; -+ ddr4_odt = ; -+ phy_ddr4_ca_drv = ; -+ phy_ddr4_ck_drv = ; -+ phy_ddr4_dq_drv = ; -+ phy_ddr4_odt = ; -+ -+ /* CA de-skew, one step is 47.8ps, range 0-15 */ -+ ddr3a1_ddr4a9_de-skew = <7>; -+ ddr3a0_ddr4a10_de-skew = <7>; -+ ddr3a3_ddr4a6_de-skew = <8>; -+ ddr3a2_ddr4a4_de-skew = <8>; -+ ddr3a5_ddr4a8_de-skew = <7>; -+ ddr3a4_ddr4a5_de-skew = <9>; -+ ddr3a7_ddr4a11_de-skew = <7>; -+ ddr3a6_ddr4a7_de-skew = <9>; -+ ddr3a9_ddr4a0_de-skew = <8>; -+ ddr3a8_ddr4a13_de-skew = <7>; -+ ddr3a11_ddr4a3_de-skew = <9>; -+ ddr3a10_ddr4cs0_de-skew = <7>; -+ ddr3a13_ddr4a2_de-skew = <8>; -+ ddr3a12_ddr4ba1_de-skew = <7>; -+ ddr3a15_ddr4odt0_de-skew = <7>; -+ ddr3a14_ddr4a1_de-skew = <8>; -+ ddr3ba1_ddr4a15_de-skew = <7>; -+ ddr3ba0_ddr4bg0_de-skew = <7>; -+ ddr3ras_ddr4cke_de-skew = <7>; -+ ddr3ba2_ddr4ba0_de-skew = <8>; -+ ddr3we_ddr4bg1_de-skew = <8>; -+ ddr3cas_ddr4a12_de-skew = <7>; -+ ddr3ckn_ddr4ckn_de-skew = <8>; -+ ddr3ckp_ddr4ckp_de-skew = <8>; -+ ddr3cke_ddr4a16_de-skew = <8>; -+ ddr3odt0_ddr4a14_de-skew = <7>; -+ ddr3cs0_ddr4act_de-skew = <8>; -+ ddr3reset_ddr4reset_de-skew = <7>; -+ ddr3cs1_ddr4cs1_de-skew = <7>; -+ ddr3odt1_ddr4odt1_de-skew = <7>; -+ -+ /* DATA de-skew -+ * RX one step is 25.1ps, range 0-15 -+ * TX one step is 47.8ps, range 0-15 -+ */ -+ cs0_dm0_rx_de-skew = <7>; -+ cs0_dm0_tx_de-skew = <8>; -+ cs0_dq0_rx_de-skew = <7>; -+ cs0_dq0_tx_de-skew = <8>; -+ cs0_dq1_rx_de-skew = <7>; -+ cs0_dq1_tx_de-skew = <8>; -+ cs0_dq2_rx_de-skew = <7>; -+ cs0_dq2_tx_de-skew = <8>; -+ cs0_dq3_rx_de-skew = <7>; -+ cs0_dq3_tx_de-skew = <8>; -+ cs0_dq4_rx_de-skew = <7>; -+ cs0_dq4_tx_de-skew = <8>; -+ cs0_dq5_rx_de-skew = <7>; -+ cs0_dq5_tx_de-skew = <8>; -+ cs0_dq6_rx_de-skew = <7>; -+ cs0_dq6_tx_de-skew = <8>; -+ cs0_dq7_rx_de-skew = <7>; -+ cs0_dq7_tx_de-skew = <8>; -+ cs0_dqs0_rx_de-skew = <6>; -+ cs0_dqs0p_tx_de-skew = <9>; -+ cs0_dqs0n_tx_de-skew = <9>; -+ -+ cs0_dm1_rx_de-skew = <7>; -+ cs0_dm1_tx_de-skew = <7>; -+ cs0_dq8_rx_de-skew = <7>; -+ cs0_dq8_tx_de-skew = <8>; -+ cs0_dq9_rx_de-skew = <7>; -+ cs0_dq9_tx_de-skew = <7>; -+ cs0_dq10_rx_de-skew = <7>; -+ cs0_dq10_tx_de-skew = <8>; -+ cs0_dq11_rx_de-skew = <7>; -+ cs0_dq11_tx_de-skew = <7>; -+ cs0_dq12_rx_de-skew = <7>; -+ cs0_dq12_tx_de-skew = <8>; -+ cs0_dq13_rx_de-skew = <7>; -+ cs0_dq13_tx_de-skew = <7>; -+ cs0_dq14_rx_de-skew = <7>; -+ cs0_dq14_tx_de-skew = <8>; -+ cs0_dq15_rx_de-skew = <7>; -+ cs0_dq15_tx_de-skew = <7>; -+ cs0_dqs1_rx_de-skew = <7>; -+ cs0_dqs1p_tx_de-skew = <9>; -+ cs0_dqs1n_tx_de-skew = <9>; -+ -+ cs0_dm2_rx_de-skew = <7>; -+ cs0_dm2_tx_de-skew = <8>; -+ cs0_dq16_rx_de-skew = <7>; -+ cs0_dq16_tx_de-skew = <8>; -+ cs0_dq17_rx_de-skew = <7>; -+ cs0_dq17_tx_de-skew = <8>; -+ cs0_dq18_rx_de-skew = <7>; -+ cs0_dq18_tx_de-skew = <8>; -+ cs0_dq19_rx_de-skew = <7>; -+ cs0_dq19_tx_de-skew = <8>; -+ cs0_dq20_rx_de-skew = <7>; -+ cs0_dq20_tx_de-skew = <8>; -+ cs0_dq21_rx_de-skew = <7>; -+ cs0_dq21_tx_de-skew = <8>; -+ cs0_dq22_rx_de-skew = <7>; -+ cs0_dq22_tx_de-skew = <8>; -+ cs0_dq23_rx_de-skew = <7>; -+ cs0_dq23_tx_de-skew = <8>; -+ cs0_dqs2_rx_de-skew = <6>; -+ cs0_dqs2p_tx_de-skew = <9>; -+ cs0_dqs2n_tx_de-skew = <9>; -+ -+ cs0_dm3_rx_de-skew = <7>; -+ cs0_dm3_tx_de-skew = <7>; -+ cs0_dq24_rx_de-skew = <7>; -+ cs0_dq24_tx_de-skew = <8>; -+ cs0_dq25_rx_de-skew = <7>; -+ cs0_dq25_tx_de-skew = <7>; -+ cs0_dq26_rx_de-skew = <7>; -+ cs0_dq26_tx_de-skew = <7>; -+ cs0_dq27_rx_de-skew = <7>; -+ cs0_dq27_tx_de-skew = <7>; -+ cs0_dq28_rx_de-skew = <7>; -+ cs0_dq28_tx_de-skew = <7>; -+ cs0_dq29_rx_de-skew = <7>; -+ cs0_dq29_tx_de-skew = <7>; -+ cs0_dq30_rx_de-skew = <7>; -+ cs0_dq30_tx_de-skew = <7>; -+ cs0_dq31_rx_de-skew = <7>; -+ cs0_dq31_tx_de-skew = <7>; -+ cs0_dqs3_rx_de-skew = <7>; -+ cs0_dqs3p_tx_de-skew = <9>; -+ cs0_dqs3n_tx_de-skew = <9>; -+ -+ cs1_dm0_rx_de-skew = <7>; -+ cs1_dm0_tx_de-skew = <8>; -+ cs1_dq0_rx_de-skew = <7>; -+ cs1_dq0_tx_de-skew = <8>; -+ cs1_dq1_rx_de-skew = <7>; -+ cs1_dq1_tx_de-skew = <8>; -+ cs1_dq2_rx_de-skew = <7>; -+ cs1_dq2_tx_de-skew = <8>; -+ cs1_dq3_rx_de-skew = <7>; -+ cs1_dq3_tx_de-skew = <8>; -+ cs1_dq4_rx_de-skew = <7>; -+ cs1_dq4_tx_de-skew = <8>; -+ cs1_dq5_rx_de-skew = <7>; -+ cs1_dq5_tx_de-skew = <8>; -+ cs1_dq6_rx_de-skew = <7>; -+ cs1_dq6_tx_de-skew = <8>; -+ cs1_dq7_rx_de-skew = <7>; -+ cs1_dq7_tx_de-skew = <8>; -+ cs1_dqs0_rx_de-skew = <6>; -+ cs1_dqs0p_tx_de-skew = <9>; -+ cs1_dqs0n_tx_de-skew = <9>; -+ -+ cs1_dm1_rx_de-skew = <7>; -+ cs1_dm1_tx_de-skew = <7>; -+ cs1_dq8_rx_de-skew = <7>; -+ cs1_dq8_tx_de-skew = <8>; -+ cs1_dq9_rx_de-skew = <7>; -+ cs1_dq9_tx_de-skew = <7>; -+ cs1_dq10_rx_de-skew = <7>; -+ cs1_dq10_tx_de-skew = <8>; -+ cs1_dq11_rx_de-skew = <7>; -+ cs1_dq11_tx_de-skew = <7>; -+ cs1_dq12_rx_de-skew = <7>; -+ cs1_dq12_tx_de-skew = <8>; -+ cs1_dq13_rx_de-skew = <7>; -+ cs1_dq13_tx_de-skew = <7>; -+ cs1_dq14_rx_de-skew = <7>; -+ cs1_dq14_tx_de-skew = <8>; -+ cs1_dq15_rx_de-skew = <7>; -+ cs1_dq15_tx_de-skew = <7>; -+ cs1_dqs1_rx_de-skew = <7>; -+ cs1_dqs1p_tx_de-skew = <9>; -+ cs1_dqs1n_tx_de-skew = <9>; -+ -+ cs1_dm2_rx_de-skew = <7>; -+ cs1_dm2_tx_de-skew = <8>; -+ cs1_dq16_rx_de-skew = <7>; -+ cs1_dq16_tx_de-skew = <8>; -+ cs1_dq17_rx_de-skew = <7>; -+ cs1_dq17_tx_de-skew = <8>; -+ cs1_dq18_rx_de-skew = <7>; -+ cs1_dq18_tx_de-skew = <8>; -+ cs1_dq19_rx_de-skew = <7>; -+ cs1_dq19_tx_de-skew = <8>; -+ cs1_dq20_rx_de-skew = <7>; -+ cs1_dq20_tx_de-skew = <8>; -+ cs1_dq21_rx_de-skew = <7>; -+ cs1_dq21_tx_de-skew = <8>; -+ cs1_dq22_rx_de-skew = <7>; -+ cs1_dq22_tx_de-skew = <8>; -+ cs1_dq23_rx_de-skew = <7>; -+ cs1_dq23_tx_de-skew = <8>; -+ cs1_dqs2_rx_de-skew = <6>; -+ cs1_dqs2p_tx_de-skew = <9>; -+ cs1_dqs2n_tx_de-skew = <9>; -+ -+ cs1_dm3_rx_de-skew = <7>; -+ cs1_dm3_tx_de-skew = <7>; -+ cs1_dq24_rx_de-skew = <7>; -+ cs1_dq24_tx_de-skew = <8>; -+ cs1_dq25_rx_de-skew = <7>; -+ cs1_dq25_tx_de-skew = <7>; -+ cs1_dq26_rx_de-skew = <7>; -+ cs1_dq26_tx_de-skew = <7>; -+ cs1_dq27_rx_de-skew = <7>; -+ cs1_dq27_tx_de-skew = <7>; -+ cs1_dq28_rx_de-skew = <7>; -+ cs1_dq28_tx_de-skew = <7>; -+ cs1_dq29_rx_de-skew = <7>; -+ cs1_dq29_tx_de-skew = <7>; -+ cs1_dq30_rx_de-skew = <7>; -+ cs1_dq30_tx_de-skew = <7>; -+ cs1_dq31_rx_de-skew = <7>; -+ cs1_dq31_tx_de-skew = <7>; -+ cs1_dqs3_rx_de-skew = <7>; -+ cs1_dqs3p_tx_de-skew = <9>; -+ cs1_dqs3n_tx_de-skew = <9>; -+ }; -+}; diff --git a/target/linux/rockchip/patches-5.4/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch b/target/linux/rockchip/patches-5.4/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch new file mode 100644 index 000000000..54cd42051 --- /dev/null +++ b/target/linux/rockchip/patches-5.4/809-arm64-dts-doornet1-add-rk3328-dmc-relate-node.patch @@ -0,0 +1,124 @@ +From 2184ab853067b484ba5677e35f1a6955a5c023a1 Mon Sep 17 00:00:00 2001 +From: wowowow +Date: Wed, 20 Oct 2021 13:46:46 +0800 +Subject: [PATCH] arm64-dts-doornet1-add-rk3328-dmc-relate-node + +--- + .../boot/dts/rockchip/rk3328-doornet1.dts | 73 +++++++++++++++++++ + 1 file changed, 73 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts +index 8333351..d984163 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts +@@ -7,6 +7,7 @@ + + #include + #include ++#include "rk3328-dram-nanopi2-timing.dtsi" + #include "rk3328.dtsi" + + / { +@@ -56,6 +57,72 @@ + enable-active-high; + }; + ++ dmc: dmc { ++ compatible = "rockchip,rk3328-dmc"; ++ devfreq-events = <&dfi>; ++ center-supply = <&vdd_log>; ++ clocks = <&cru SCLK_DDRCLK>; ++ clock-names = "dmc_clk"; ++ operating-points-v2 = <&dmc_opp_table>; ++ ddr_timing = <&ddr_timing>; ++ upthreshold = <40>; ++ downdifferential = <20>; ++ auto-min-freq = <786000>; ++ auto-freq-en = <1>; ++ #cooling-cells = <2>; ++ status = "okay"; ++ ++ ddr_power_model: ddr_power_model { ++ compatible = "ddr_power_model"; ++ dynamic-power-coefficient = <120>; ++ static-power-coefficient = <200>; ++ ts = <32000 4700 (-80) 2>; ++ thermal-zone = "soc-thermal"; ++ }; ++ }; ++ ++ dmc_opp_table: dmc-opp-table { ++ compatible = "operating-points-v2"; ++ ++ rockchip,leakage-voltage-sel = < ++ 1 10 0 ++ 11 254 1 ++ >; ++ nvmem-cells = <&logic_leakage>; ++ nvmem-cell-names = "ddr_leakage"; ++ ++ opp-786000000 { ++ opp-hz = /bits/ 64 <786000000>; ++ opp-microvolt = <1075000>; ++ opp-microvolt-L0 = <1075000>; ++ opp-microvolt-L1 = <1050000>; ++ }; ++ opp-798000000 { ++ opp-hz = /bits/ 64 <798000000>; ++ opp-microvolt = <1075000>; ++ opp-microvolt-L0 = <1075000>; ++ opp-microvolt-L1 = <1050000>; ++ }; ++ opp-840000000 { ++ opp-hz = /bits/ 64 <840000000>; ++ opp-microvolt = <1075000>; ++ opp-microvolt-L0 = <1075000>; ++ opp-microvolt-L1 = <1050000>; ++ }; ++ opp-924000000 { ++ opp-hz = /bits/ 64 <924000000>; ++ opp-microvolt = <1100000>; ++ opp-microvolt-L0 = <1100000>; ++ opp-microvolt-L1 = <1075000>; ++ }; ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1175000>; ++ opp-microvolt-L0 = <1175000>; ++ opp-microvolt-L1 = <1150000>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; +@@ -138,6 +205,10 @@ + cpu-supply = <&vdd_arm>; + }; + ++&dfi { ++ status = "okay"; ++}; ++ + &gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; +@@ -201,6 +272,7 @@ + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; ++ regulator-init-microvolt = <1075000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; +@@ -215,6 +287,7 @@ + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; ++ regulator-init-microvolt = <1225000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; +-- +2.25.1 +