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atf-rockchip: add support for rk3568/rk3588

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coolsnowwolf 2024-08-18 23:05:39 +08:00
parent 9fcac0612c
commit 95c79b7036
3 changed files with 224 additions and 38 deletions
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96
package/boot/arm-trusted-firmware-rockchip/Makefile
View File

@ -6,44 +6,90 @@
#
include $(TOPDIR)/rules.mk
PKG_NAME:=arm-trusted-firmware-rockchip
PKG_VERSION:=2.8
PKG_RELEASE:=1
PKG_SOURCE:=atf-v$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/atf-builds/atf/releases/download/v$(PKG_VERSION)/atf-v$(PKG_VERSION).tar.gz?
PKG_HASH:=61df69619fd611da9e43abf66be28d6d59722feef559587fad0ca4cd9e499758
PKG_LICENSE:=BSD-3-Clause
PKG_LICENSE_FILES:=license.md
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/ARM-software/arm-trusted-firmware
PKG_SOURCE_DATE:=2024-09-09
PKG_SOURCE_VERSION:=0631d68d85881d4b8ffa571f49eb8b767c005f6a
PKG_MIRROR_HASH:=6e8a83c6ee64faab46e1531948180199fa70194bb2ffec4d4a521c2b2d136cf3
PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
MAKE_PATH:=$(PKG_NAME)
include $(INCLUDE_DIR)/kernel.mk
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
define Package/arm-trusted-firmware-rockchip
SECTION:=boot
CATEGORY:=Boot Loaders
TITLE:=ARM Trusted Firmware for Rockchip
DEPENDS:=@TARGET_rockchip_armv8
define Trusted-Firmware-A/Default
NAME:=Rockchip $(1) SoCs
BUILD_TARGET:=rockchip
endef
define Build/Prepare
$(TAR) -C $(PKG_BUILD_DIR) -xf $(DL_DIR)/$(PKG_SOURCE)
define Trusted-Firmware-A/rk3328
BUILD_SUBTARGET:=armv8
PLAT=rk3328
endef
define Trusted-Firmware-A/rk3399
BUILD_SUBTARGET:=armv8
PLAT:=rk3399
endef
define Trusted-Firmware-A/rk3568
BUILD_SUBTARGET:=armv8
PLAT:=rk3568
endef
define Trusted-Firmware-A/rk3588
BUILD_SUBTARGET:=armv8
PLAT:=rk3588
endef
TFA_TARGETS:= \
rk3328 \
rk3399 \
rk3568 \
rk3588
ifeq ($(BUILD_VARIANT),rk3399)
M0_GCC_NAME:=gcc-arm
M0_GCC_RELEASE:=11.2-2022.02
M0_GCC_VERSION:=$(HOST_ARCH)-arm-none-eabi
M0_GCC_SOURCE:=$(M0_GCC_NAME)-$(M0_GCC_RELEASE)-$(M0_GCC_VERSION).tar.xz
define Download/m0-gcc
FILE:=$(M0_GCC_SOURCE)
URL:=https://developer.arm.com/-/media/Files/downloads/gnu/$(M0_GCC_RELEASE)/binrel
ifeq ($(HOST_ARCH),aarch64)
HASH:=ef1d82e5894e3908cb7ed49c5485b5b95deefa32872f79c2b5f6f5447cabf55f
else
HASH:=8c5acd5ae567c0100245b0556941c237369f210bceb196edfe5a2e7532c60326
endif
endef
define Build/Prepare
$(eval $(call Download,m0-gcc))
$(call Build/Prepare/Default)
xzcat $(DL_DIR)/$(M0_GCC_SOURCE) | $(HOST_TAR) -C $(PKG_BUILD_DIR)/ $(TAR_OPTIONS)
endef
TFA_MAKE_FLAGS+= \
M0_CROSS_COMPILE=$(PKG_BUILD_DIR)/$(M0_GCC_NAME)-$(M0_GCC_RELEASE)-$(M0_GCC_VERSION)/bin/arm-none-eabi-
endif
define Build/Compile
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
CROSS_COMPILE=$(TARGET_CROSS) \
OPENSSL_DIR=$(STAGING_DIR_HOST) \
$(if $(DTC),DTC="$(DTC)") \
PLAT=$(PLAT) \
$(TFA_MAKE_FLAGS)
endef
define Build/InstallDev
$(INSTALL_DIR) -p $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/rk*.elf $(STAGING_DIR_IMAGE)/
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl31/bl31.elf $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)_bl31.elf
endef
define Package/arm-trusted-firmware-rockchip/install
endef
$(eval $(call BuildPackage,arm-trusted-firmware-rockchip))
$(eval $(call BuildPackage/Trusted-Firmware-A))

140
package/boot/arm-trusted-firmware-rockchip/patches/001-feat-rk3588-enable-crypto-function.patch Normal file
View File

@ -0,0 +1,140 @@
From 35cb9811b8cc2099ce11e2c86d9da6786c28a6c6 Mon Sep 17 00:00:00 2001
From: XiaoDong Huang <derrick.huang@rock-chips.com>
Date: Mon, 17 Jun 2024 10:55:27 +0800
Subject: [PATCH] feat(rk3588): enable crypto function
The CPU crypto is not default on when power up, need to enable it by
software.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifee2eab55d9c13cef5f15926fb80016845e2a66d
---
bl31/aarch64/bl31_entrypoint.S | 9 +++
plat/rockchip/rk3588/drivers/pmu/pmu.c | 79 ++++++++++++++++++++++++++
plat/rockchip/rk3588/platform.mk | 1 +
3 files changed, 89 insertions(+)
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -16,6 +16,11 @@
.globl bl31_entrypoint
.globl bl31_warm_entrypoint
+#ifdef PLAT_RK_BL31_ENTRYPOINT
+ .globl plat_rockchip_bl31_entrypoint
+ .globl plat_rockchip_bl31_entrypoint_set_sp
+#endif
+
/* -----------------------------------------------------
* bl31_entrypoint() is the cold boot entrypoint,
* executed only by the primary cpu.
@@ -23,6 +28,10 @@
*/
func bl31_entrypoint
+#ifdef PLAT_RK_BL31_ENTRYPOINT
+ bl plat_rockchip_bl31_entrypoint_set_sp
+ bl plat_rockchip_bl31_entrypoint
+#endif
/* ---------------------------------------------------------------
* Stash the previous bootloader arguments x0 - x3 for later use.
* ---------------------------------------------------------------
--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c
@@ -136,6 +136,22 @@ static __pmusramfunc void dsu_restore_ea
static __pmusramfunc void ddr_resume(void)
{
+ /* check the crypto function had been enabled or not */
+ if (mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) {
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
+ dsb();
+ isb();
+
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ }
+
dsu_restore_early();
}
@@ -1437,3 +1453,66 @@ void plat_rockchip_pmu_init(void)
pm_reg_rgns_init();
}
+
+void bl31_entrypoint(void);
+
+static uint64_t boot_cpu_save[4];
+
+void plat_rockchip_bl31_entrypoint_set_sp(uint64_t reg0, uint64_t reg1,
+ uint64_t reg2, uint64_t reg3)
+{
+ __asm__ volatile("mov x10, %0\n" : : "r" (reg0) : );
+
+ reg0 = PSRAM_SP_TOP;
+ __asm__ volatile("mov sp, %0\n" : : "r" (reg0) : );
+
+ __asm__ volatile("mov %0, x10\n" : "=r" (reg0) : :);
+}
+
+void plat_rockchip_bl31_entrypoint(uint64_t reg0, uint64_t reg1,
+ uint64_t reg2, uint64_t reg3)
+{
+ uint32_t tmp = mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4));
+
+ /* check the crypto function had been enabled or not */
+ if (tmp & BIT(4)) {
+ /* save x0~x3 */
+ boot_cpu_save[0] = reg0;
+ boot_cpu_save[1] = reg1;
+ boot_cpu_save[2] = reg2;
+ boot_cpu_save[3] = reg3;
+
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
+
+ /* remap pmusram to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001);
+ dsb();
+ psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT;
+ cpuson_flags[0] = PMU_CPU_HOTPLUG;
+ cpuson_entry_point[0] = (uintptr_t)bl31_entrypoint;
+ dsb();
+
+ /* to enable the crypto function, must reset the core0 */
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ } else {
+ /* remap bootrom to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000);
+
+ /*
+ * the crypto function has been enabled,
+ * restore the x0~x3.
+ */
+ __asm__ volatile ("ldr x0, [%0]\n"
+ "ldr x1, [%0 , 0x8]\n"
+ "ldr x2, [%0 , 0x10]\n"
+ "ldr x3, [%0 , 0x18]\n"
+ : : "r" (&boot_cpu_save[0]));
+ }
+}
--- a/plat/rockchip/rk3588/platform.mk
+++ b/plat/rockchip/rk3588/platform.mk
@@ -96,3 +96,4 @@ ENABLE_SPE_FOR_LOWER_ELS := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
$(eval $(call add_define,PLAT_SKIP_DFS_TLB_DCACHE_MAINTENANCE))
+$(eval $(call add_define,PLAT_RK_BL31_ENTRYPOINT))

26
package/boot/rockchip-rkbin/Makefile
View File

@ -25,54 +25,54 @@ define Trusted-Firmware-A/Default
BUILD_TARGET:=rockchip
endef
define Trusted-Firmware-A/rk3328
define Trusted-Firmware-A/rk3328-bin
BUILD_SUBTARGET:=armv8
ATF:=rk33/rk322xh_bl31_v1.49.elf
TPL:=rk33/rk3328_ddr_333MHz_v1.19.bin
SPL:=rk33/rk322xh_miniloader_v2.50.bin
endef
define Trusted-Firmware-A/rk3399
define Trusted-Firmware-A/rk3399-bin
BUILD_SUBTARGET:=armv8
ATF:=rk33/rk3399_bl31_v1.36.elf
TPL:=rk33/rk3399_ddr_800MHz_v1.30.bin
SPL:=rk33/rk3399_miniloader_v1.30.bin
endef
define Trusted-Firmware-A/rk3528
define Trusted-Firmware-A/rk3528-bin
BUILD_SUBTARGET:=armv8
ATF:=rk35/rk3528_bl31_v1.17.elf
TPL:=rk35/rk3528_ddr_1056MHz_v1.09.bin
endef
define Trusted-Firmware-A/rk3566
define Trusted-Firmware-A/rk3566-bin
BUILD_SUBTARGET:=armv8
ATF:=rk35/rk3568_bl31_v1.44.elf
TPL:=rk35/rk3566_ddr_1056MHz_v1.21.bin
endef
define Trusted-Firmware-A/rk3568
define Trusted-Firmware-A/rk3568-bin
BUILD_SUBTARGET:=armv8
ATF:=rk35/rk3568_bl31_v1.44.elf
TPL:=rk35/rk3568_ddr_1560MHz_v1.21.bin
endef
define Trusted-Firmware-A/rk3588
define Trusted-Firmware-A/rk3588-bin
BUILD_SUBTARGET:=armv8
ATF:=rk35/rk3588_bl31_v1.45.elf
TPL:=rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin
endef
TFA_TARGETS:= \
rk3328 \
rk3399 \
rk3528 \
rk3566 \
rk3568 \
rk3588
rk3328-bin \
rk3399-bin \
rk3528-bin \
rk3566-bin \
rk3568-bin \
rk3588-bin
define Build/Compile
# workaround for "extraneous 'endif'" error
@echo Building idbLoader from Rockchip rkbin project...
ifneq ($(SPL),)
( \
pushd $(PKG_BUILD_DIR) ; \