mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-18 17:33:31 +00:00
add sgr-w500-n85b-v2
This commit is contained in:
imbrolla
parent
1de9ee7e73
commit
95a7137bf8
@ -565,6 +565,9 @@ re450)
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ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "$board:blue:wlan2g" "phy1tpt"
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ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "$board:blue:wlan5g" "phy0tpt"
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;;
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sgr-w500-n85b-v2)
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ucidef_set_led_wlan "wlan" "WLAN" "grentech:green:wlan2g" "phy0tpt"
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;;
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smart-300)
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ucidef_set_led_netdev "wan" "WAN" "nc-link:green:wan" "eth0"
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ucidef_set_led_switch "lan1" "LAN1" "nc-link:green:lan1" "switch0" "0x04"
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@ -132,6 +132,7 @@ ar71xx_setup_interfaces()
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unifiac-lite|\
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wi2a-ac200i|\
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wndap360|\
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sgr-w500-n85b-v2 |\
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wp543)
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ucidef_set_interface_lan "eth0"
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;;
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@ -350,6 +350,9 @@ get_status_led() {
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rw2458n)
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status_led="$board:green:d3"
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;;
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sgr-w500-n85b-v2)
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status_led="grentech:green:status"
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;;
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smart-300)
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status_led="nc-link:green:system"
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;;
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@ -992,6 +992,9 @@ ar71xx_board_detect() {
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*"SC450")
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name="sc450"
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;;
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"GRENTECH SGR-W500-N85b v2.0")
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name="sgr-w500-n85b-v2"
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;;
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*"SMART-300")
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name="smart-300"
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;;
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@ -328,6 +328,7 @@ platform_check_image() {
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hornet-ub|\
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mr12|\
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mr16|\
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sgr-w500-n85b-v2|\
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zbt-we1526|\
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zcn-1523h-2|\
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zcn-1523h-5)
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@ -168,6 +168,7 @@ CONFIG_ATH79_MACH_RW2458N=y
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CONFIG_ATH79_MACH_SC1750=y
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CONFIG_ATH79_MACH_SC300M=y
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CONFIG_ATH79_MACH_SC450=y
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CONFIG_ATH79_MACH_SGR_W500_N85B_V2=y
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CONFIG_ATH79_MACH_SMART_300=y
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CONFIG_ATH79_MACH_SOM9331=y
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CONFIG_ATH79_MACH_SR3200=y
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@ -166,6 +166,7 @@ CONFIG_ATH79_MACH_RW2458N=y
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CONFIG_ATH79_MACH_SC1750=y
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CONFIG_ATH79_MACH_SC300M=y
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CONFIG_ATH79_MACH_SC450=y
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CONFIG_ATH79_MACH_SGR_W500_N85B_V2=y
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CONFIG_ATH79_MACH_SMART_300=y
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CONFIG_ATH79_MACH_SOM9331=y
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CONFIG_ATH79_MACH_SR3200=y
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@ -2171,3 +2171,14 @@ config ATH79_MACH_FRITZ300E
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_M25P80
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config ATH79_MACH_SGR_W500_N85B_V2
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bool "GRENTECH SGR-W500-N85b v2.0 support"
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select SOC_AR934X
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select ATH79_DEV_AP9X_PCI if PCI
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select ATH79_DEV_ETH
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_M25P80
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select ATH79_DEV_WMAC
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select ATH79_DEV_USB
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@ -175,6 +175,7 @@ obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o
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obj-$(CONFIG_ATH79_MACH_SC1750) += mach-sc1750.o
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obj-$(CONFIG_ATH79_MACH_SC300M) += mach-sc300m.o
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obj-$(CONFIG_ATH79_MACH_SC450) += mach-sc450.o
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obj-$(CONFIG_ATH79_MACH_SGR_W500_N85B_V2) += mach-sgr-w500-n85b-v2.o
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obj-$(CONFIG_ATH79_MACH_SMART_300) += mach-smart-300.o
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obj-$(CONFIG_ATH79_MACH_SOM9331) += mach-som9331.o
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obj-$(CONFIG_ATH79_MACH_SR3200) += mach-sr3200.o
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134
target/linux/ar71xx/files/arch/mips/ath79/mach-sgr-w500-n85b-v2.c
Executable file
134
target/linux/ar71xx/files/arch/mips/ath79/mach-sgr-w500-n85b-v2.c
Executable file
@ -0,0 +1,134 @@
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/*
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* GRENTECH SGR-W500-N85b v2.0 board support
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*
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* Copyright (c) 2017 Weijie Gao <hackpascal@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define GRENTECH_GPIO_LED_STATUS 21
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#define GRENTECH_GPIO_LED_WLAN2G 20
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#define GRENTECH_GPIO_BUTTON_RESET 3
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#define GRENTECH_GPIO_RTL8211E_RESET_L 11
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#define GRENTECH_GPIO_EXTERNAL_LNA0 18
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#define GRENTECH_GPIO_EXTERNAL_LNA1 19
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#define GRENTECH_KEYS_POLL_INTERVAL 20 /* msecs */
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#define GRENTECH_KEYS_DEBOUNCE_INTERVAL (3 * GRENTECH_KEYS_POLL_INTERVAL)
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#define GRENTECH_MAC_OFFSET 0
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#define GRENTECH_WMAC_CALDATA_OFFSET 0x1000
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#define GRENTECH_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led grentech_leds_gpio[] __initdata = {
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{
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.name = "grentech:green:status",
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.gpio = GRENTECH_GPIO_LED_STATUS,
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.active_low = 1,
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},
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{
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.name = "grentech:green:wlan2g",
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.gpio = GRENTECH_GPIO_LED_WLAN2G,
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.active_low = 1,
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}
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};
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static struct gpio_keys_button grentech_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = GRENTECH_KEYS_DEBOUNCE_INTERVAL,
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.gpio = GRENTECH_GPIO_BUTTON_RESET,
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.active_low = 1,
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},
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};
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static struct mdio_board_info grentech_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 1,
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},
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};
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static void __init grentech_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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u8 tmpmac[ETH_ALEN];
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ath79_register_m25p80(NULL);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(grentech_leds_gpio),
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grentech_leds_gpio);
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ath79_register_gpio_keys_polled(-1, GRENTECH_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(grentech_gpio_keys),
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grentech_gpio_keys);
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gpio_request_one(GRENTECH_GPIO_RTL8211E_RESET_L,
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GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
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"RTL8211E reset pin");
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ath79_wmac_set_ext_lna_gpio(0, GRENTECH_GPIO_EXTERNAL_LNA0);
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ath79_wmac_set_ext_lna_gpio(1, GRENTECH_GPIO_EXTERNAL_LNA1);
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ath79_init_mac(tmpmac, art + GRENTECH_MAC_OFFSET, 1);
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ath79_register_wmac(art + GRENTECH_WMAC_CALDATA_OFFSET, tmpmac);
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/* AR9382 */
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ath79_init_mac(tmpmac, art + GRENTECH_MAC_OFFSET, 2);
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ap9x_pci_setup_wmac_led_pin(0, 6);
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ap91_pci_init(art + GRENTECH_PCIE_CALDATA_OFFSET, tmpmac);
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
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ath79_register_mdio(0, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, art + GRENTECH_MAC_OFFSET, 0);
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mdiobus_register_board_info(grentech_mdio0_info,
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ARRAY_SIZE(grentech_mdio0_info));
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/* GMAC0 is connected to a RTL8211E Gigabit PHY */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(1);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_pll_data.pll_1000 = 0x46000000;
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ath79_eth0_pll_data.pll_100 = 0x0101;
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ath79_eth0_pll_data.pll_10 = 0x1313;
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ath79_register_eth(0);
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}
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MIPS_MACHINE(ATH79_MACH_SGR_W500_N85B_V2, "SGRW500N85BV2", "GRENTECH SGR-W500-N85b v2.0",
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grentech_setup);
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@ -1,279 +0,0 @@
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/*
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* TP-LINK TL-WR941N v7 board support
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*
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* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2014 Weijie Gao <hackpacsal@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define WR941NV7_GPIO_LED_WLAN 12
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#define WR941NV7_GPIO_LED_SYSTEM 19
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#define WR941NV7_GPIO_LED_QSS 15
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#define WR941NV7_GPIO_BTN_RESET 16
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#define WR941NV7_KEYS_POLL_INTERVAL 20 /* msecs */
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#define WR941NV7_KEYS_DEBOUNCE_INTERVAL (3 * WR941NV7_KEYS_POLL_INTERVAL)
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#define ATH_MII_MGMT_CMD 0x24
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#define ATH_MGMT_CMD_READ 0x1
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#define ATH_MII_MGMT_ADDRESS 0x28
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#define ATH_ADDR_SHIFT 8
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#define ATH_MII_MGMT_CTRL 0x2c
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#define ATH_MII_MGMT_STATUS 0x30
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#define ATH_MII_MGMT_IND 0x34
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#define ATH_MGMT_IND_BUSY (1 << 0)
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#define ATH_MGMT_IND_INVALID (1 << 2)
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static const char *wr941nv7_part_probes[] = {
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"tp-link",
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NULL,
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};
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static struct flash_platform_data wr941nv7_flash_data = {
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.part_probes = wr941nv7_part_probes,
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};
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static struct gpio_led wr941nv7_leds_gpio[] __initdata = {
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{
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.name = "tp-link:green:qss",
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.gpio = WR941NV7_GPIO_LED_QSS,
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.active_low = 1,
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},
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{
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.name = "tp-link:green:system",
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.gpio = WR941NV7_GPIO_LED_SYSTEM,
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.active_low = 1,
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},
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{
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.name = "tp-link:green:wlan",
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.gpio = WR941NV7_GPIO_LED_WLAN,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button wr941nv7_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = WR941NV7_KEYS_DEBOUNCE_INTERVAL,
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.gpio = WR941NV7_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static struct mdio_board_info wr941nv7_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 0,
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.platform_data = NULL,
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},
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};
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static unsigned long __init ath_gmac_reg_rd(unsigned long reg)
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{
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void __iomem *base;
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unsigned long t;
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base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE);
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t = __raw_readl(base + reg);
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iounmap(base);
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return t;
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}
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static void __init ath_gmac_reg_wr(unsigned long reg, unsigned long value)
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{
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void __iomem *base;
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unsigned long t = value;
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base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE);
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__raw_writel(t, base + reg);
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iounmap(base);
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}
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static void __init phy_reg_write(unsigned char phy_addr, unsigned char reg, unsigned short data)
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{
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unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg;
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volatile int rddata;
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unsigned short ii = 0xFFFF;
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do
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{
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udelay(5);
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rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
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} while (rddata && --ii);
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ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr);
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ath_gmac_reg_wr(ATH_MII_MGMT_CTRL, data);
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do
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{
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udelay(5);
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rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
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} while (rddata && --ii);
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}
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static unsigned short __init phy_reg_read(unsigned char phy_addr, unsigned char reg)
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{
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unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg, val;
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volatile int rddata;
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unsigned short ii = 0xffff;
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do
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{
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udelay(5);
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rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
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} while (rddata && --ii);
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ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0);
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ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr);
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ath_gmac_reg_wr(ATH_MII_MGMT_CMD, ATH_MGMT_CMD_READ);
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do
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{
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udelay(5);
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rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
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} while (rddata && --ii);
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val = ath_gmac_reg_rd(ATH_MII_MGMT_STATUS);
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ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0);
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return val;
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}
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static void __init athrs27_reg_write(unsigned int s27_addr, unsigned int s27_write_data)
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{
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unsigned int addr_temp;
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unsigned int data;
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unsigned char phy_address, reg_address;
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addr_temp = (s27_addr) >> 2;
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data = addr_temp >> 7;
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phy_address = 0x1f;
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reg_address = 0x10;
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phy_reg_write(phy_address, reg_address, data);
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phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
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reg_address = (((addr_temp << 1) & 0x1e) | 0x1);
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data = (s27_write_data >> 16) & 0xffff;
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phy_reg_write(phy_address, reg_address, data);
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|
||||
reg_address = ((addr_temp << 1) & 0x1e);
|
||||
data = s27_write_data & 0xffff;
|
||||
phy_reg_write(phy_address, reg_address, data);
|
||||
}
|
||||
|
||||
static unsigned int __init athrs27_reg_read(unsigned int s27_addr)
|
||||
{
|
||||
unsigned int addr_temp;
|
||||
unsigned int s27_rd_csr_low, s27_rd_csr_high, s27_rd_csr;
|
||||
unsigned int data;
|
||||
unsigned char phy_address, reg_address;
|
||||
|
||||
addr_temp = s27_addr >>2;
|
||||
data = addr_temp >> 7;
|
||||
|
||||
phy_address = 0x1f;
|
||||
reg_address = 0x10;
|
||||
|
||||
phy_reg_write(phy_address, reg_address, data);
|
||||
|
||||
phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
|
||||
reg_address = ((addr_temp << 1) & 0x1e);
|
||||
s27_rd_csr_low = (unsigned int) phy_reg_read(phy_address, reg_address);
|
||||
|
||||
reg_address = reg_address | 0x1;
|
||||
s27_rd_csr_high = (unsigned int) phy_reg_read(phy_address, reg_address);
|
||||
s27_rd_csr = (s27_rd_csr_high << 16) | s27_rd_csr_low ;
|
||||
|
||||
return (s27_rd_csr);
|
||||
}
|
||||
|
||||
static void __init ar8236_reset(void)
|
||||
{
|
||||
unsigned short i = 60;
|
||||
|
||||
athrs27_reg_write(0x0, athrs27_reg_read(0x0) | 0x80000000);
|
||||
while (i--)
|
||||
{
|
||||
mdelay(100);
|
||||
if (!(athrs27_reg_read(0x0) & 0x80000000))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init wr941nv7_setup(void)
|
||||
{
|
||||
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
|
||||
u8 *art = (u8 *) KSEG1ADDR(0x1fff1000);
|
||||
|
||||
ath79_register_m25p80(&wr941nv7_flash_data);
|
||||
ath79_register_leds_gpio(-1, ARRAY_SIZE(wr941nv7_leds_gpio),
|
||||
wr941nv7_leds_gpio);
|
||||
ath79_register_gpio_keys_polled(-1, WR941NV7_KEYS_POLL_INTERVAL,
|
||||
ARRAY_SIZE(wr941nv7_gpio_keys),
|
||||
wr941nv7_gpio_keys);
|
||||
|
||||
ath79_register_wmac(art, mac);
|
||||
|
||||
ar8236_reset();
|
||||
|
||||
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_MII_GE0 |
|
||||
QCA955X_ETH_CFG_MII_GE0_SLAVE);
|
||||
|
||||
mdiobus_register_board_info(wr941nv7_mdio0_info,
|
||||
ARRAY_SIZE(wr941nv7_mdio0_info));
|
||||
ath79_register_mdio(0, 0x0);
|
||||
|
||||
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
|
||||
|
||||
/* GMAC0 is connected to an AR8236 switch */
|
||||
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
|
||||
ath79_eth0_data.speed = SPEED_100;
|
||||
ath79_eth0_data.duplex = DUPLEX_FULL;
|
||||
ath79_eth0_data.phy_mask = BIT(0);
|
||||
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
|
||||
ath79_register_eth(0);
|
||||
|
||||
ath79_register_usb();
|
||||
}
|
||||
|
||||
MIPS_MACHINE(ATH79_MACH_TL_WR941N_V7, "TL-WR941N-v7",
|
||||
"TP-LINK TL-WR941N v7",
|
||||
wr941nv7_setup);
|
||||
@ -203,6 +203,7 @@ enum ath79_mach_type {
|
||||
ATH79_MACH_SC1750, /* Abicom SC1750 */
|
||||
ATH79_MACH_SC300M, /* Abicom SC300M */
|
||||
ATH79_MACH_SC450, /* Abicom SC450 */
|
||||
ATH79_MACH_SGR_W500_N85B_V2, /* GRENTECH SGR-W500-N85B v2 */
|
||||
ATH79_MACH_SMART_300, /* NC-LINK SMART-300 */
|
||||
ATH79_MACH_SOM9331, /* OpenEmbed SOM9331 */
|
||||
ATH79_MACH_SR3200, /* YunCore SR3200 */
|
||||
|
||||
@ -589,3 +589,9 @@ define LegacyDevice/NBG_460N_550N_550NH
|
||||
DEVICE_PACKAGES := kmod-rtc-pcf8563
|
||||
endef
|
||||
LEGACY_DEVICES += NBG_460N_550N_550NH
|
||||
|
||||
define LegacyDevice/SGRW500N85BV2
|
||||
DEVICE_TITLE := GRENTECH SGR-W500-N85b v2.0 board
|
||||
DEVICE_PACKAGES := kmod-usb-core kmod-usb2 kmod-usb-storage
|
||||
endef
|
||||
LEGACY_DEVICES += SGRW500N85BV2
|
||||
|
||||
@ -1004,6 +1004,7 @@ $(eval $(call SingleProfile,Zcomax,64k,ZCN1523H28,zcn-1523h-2-8,ZCN-1523H-2,ttyS
|
||||
$(eval $(call SingleProfile,Zcomax,64k,ZCN1523H516,zcn-1523h-5-16,ZCN-1523H-5,ttyS0,115200,$$(zcn1523h_mtdlayout)))
|
||||
|
||||
$(eval $(call SingleProfile,ZyXEL,64k,NBG_460N_550N_550NH,nbg460n_550n_550nh,NBG460N,ttyS0,115200,NBG-460N))
|
||||
$(eval $(call SingleProfile,AthLzma,64k,SGRW500N85BV2,sgr-w500-n85b-v2,SGRW500N85BV2,ttyS0,115200,$$(ap147_mtdlayout),RKuImage))
|
||||
|
||||
endif # ifeq ($(SUBTARGET),generic)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user