mirror of
https://github.com/coolsnowwolf/lede.git
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commit
933f77cc81
@ -239,7 +239,7 @@ CONFIG_ATH79=y
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# CONFIG_ATH79_MACH_TL_WR940N_V4 is not set
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# CONFIG_ATH79_MACH_TL_WR941ND is not set
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# CONFIG_ATH79_MACH_TL_WR941ND_V6 is not set
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# CONFIG_ATH79_MACH_TL_WR941N_V7 is not set
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CONFIG_ATH79_MACH_TL_WR941N_V7=y
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# CONFIG_ATH79_MACH_TL_WR942N_V1 is not set
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# CONFIG_ATH79_MACH_TS_D084 is not set
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# CONFIG_ATH79_MACH_TUBE2H is not set
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@ -239,7 +239,7 @@ CONFIG_ATH79=y
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# CONFIG_ATH79_MACH_TL_WR940N_V4 is not set
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# CONFIG_ATH79_MACH_TL_WR941ND is not set
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# CONFIG_ATH79_MACH_TL_WR941ND_V6 is not set
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# CONFIG_ATH79_MACH_TL_WR941N_V7 is not set
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CONFIG_ATH79_MACH_TL_WR941N_V7=y
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# CONFIG_ATH79_MACH_TL_WR942N_V1 is not set
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# CONFIG_ATH79_MACH_TS_D084 is not set
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# CONFIG_ATH79_MACH_TUBE2H is not set
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@ -511,3 +511,12 @@ define Device/tl-wr942n-v1
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SUPPORTED_DEVICES := tl-wr942n-v1
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endef
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TARGET_DEVICES += tl-wr942n-v1
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define Device/tl-wr941n-v7
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$(Device/tplink-8mlzma)
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DEVICE_TITLE := TP-LINK TL-WR941N/ND v7
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BOARDNAME := TL-WR941N-v7
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DEVICE_PROFILE := TLWR941
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TPLINK_HWID := 0x09410007
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endef
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TARGET_DEVICES += tl-wr941n-v7
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@ -217,7 +217,7 @@
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#define AR71XX_GPIO_COUNT 16
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#define AR7240_GPIO_COUNT 18
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#define AR7241_GPIO_COUNT 20
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@@ -570,4 +681,235 @@
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@@ -570,4 +681,237 @@
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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@ -433,6 +433,8 @@
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+#define QCA955X_GMAC_REG_ETH_CFG 0x00
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+
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+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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+#define QCA955X_ETH_CFG_GE0_MII_EN BIT(1)
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+#define QCA955X_ETH_CFG_GE0_MII_SLAVE BIT(4)
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+#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
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+#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
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+#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
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@ -217,7 +217,7 @@
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#define AR71XX_GPIO_COUNT 16
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#define AR7240_GPIO_COUNT 18
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#define AR7241_GPIO_COUNT 20
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@@ -570,4 +681,235 @@
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@@ -570,4 +681,237 @@
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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@ -433,6 +433,8 @@
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+#define QCA955X_GMAC_REG_ETH_CFG 0x00
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+
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+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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+#define QCA955X_ETH_CFG_GE0_MII_EN BIT(1)
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+#define QCA955X_ETH_CFG_GE0_MII_SLAVE BIT(4)
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+#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
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+#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
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+#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
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