From 922b9fd73bf8375ff9a45bc8b3447670fe3cae1a Mon Sep 17 00:00:00 2001 From: coolsnowwolf Date: Fri, 7 Feb 2025 12:04:28 +0800 Subject: [PATCH] qualcommax: sync ipq50xx with upstream --- target/linux/qualcommax/Makefile | 1 + target/linux/qualcommax/config-6.6 | 12 +- .../arm64/boot/dts/qcom/ipq5018-mx-base.dtsi | 325 +++++++++++ .../arm64/boot/dts/qcom/ipq5018-mx2000.dts | 519 ++---------------- .../arm64/boot/dts/qcom/ipq5018-mx5500.dts | 426 +------------- .../arch/arm64/boot/dts/qcom/ipq5018.dtsi | 515 ----------------- .../ipq50xx/base-files/etc/board.d/02_network | 7 +- .../etc/hotplug.d/firmware/11-ath11k-caldata | 2 +- .../linux/qualcommax/ipq50xx/config-default | 7 +- ...-arm64-dts-qcom-ipq5018-add-watchdog.patch | 4 +- ...-indicate-that-SDI-shoud-be-disabled.patch | 26 + ...s-qcom-ipq5018-Add-USB-related-nodes.patch | 18 +- ...qcom-ipq5018-add-QUP1-SPI-controller.patch | 12 +- ...m-ipq5018-enable-the-CPUFreq-support.patch | 34 +- ...add-few-more-reserved-memory-regions.patch | 18 +- ...ops-for-IPQ5018-to-fix-boot-failure.patch} | 0 ...ss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch} | 0 ...dts-qcom-ipq6018-add-LDOA2-regulator.patch | 5 +- ...qcom-ipq6018-add-NSS-reserved-memory.patch | 27 + ...-tsens-add-support-for-IPQ5018-tsens.patch | 2 +- ...0154-dts-qcom-IPQ5018-add-tsens-node.patch | 12 +- ...ndings-phy-qcom-document-PCIe-uniphy.patch | 92 ---- ...com-uniphy-pcie-Document-PCIe-uniphy.patch | 85 +++ ...m-Introduce-PCIe-UNIPHY-28LP-driver.patch} | 277 ++++------ ...m-uniphy-pcie-add-IPQ5018-compatible.patch | 25 + ...hy-pcie-28lp-add-support-for-IPQ5018.patch | 77 +++ ...t-bindings-PCI-qcom-Add-IPQ5018-SoC.patch} | 4 +- ...61-PCI-qcom-add-support-for-IPQ5018.patch} | 8 +- ...qcom-IPQ5018-add-PCIe-related-nodes.patch} | 87 +-- ...arm64-dts-qcom-IPQ5018-add-TCSR-node.patch | 2 +- ...018-enable-the-download-mode-support.patch | 2 +- ...nctrl-qcom-IPQ5018-update-pwm-groups.patch | 9 + ...-arm64-dts-qcom-ipq5018-Add-PWM-node.patch | 2 +- ...64-dts-qcom-ipq5018-Add-crypto-nodes.patch | 2 +- ...arm64-dts-qcom-ipq5018-Add-PRNG-node.patch | 2 +- ...dts-qcom-ipq5018-Add-QUP1-UART2-node.patch | 2 +- ...4-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch | 2 +- ...nand-add-support-for-TH58NYG3S0HBAI4.patch | 30 - ...spi-spi-qpic-fix-compilation-issues.patch} | 19 +- ...0411-spi-spi-qpic-snand-support-BCH8.patch | 5 +- ...and-qpic-only-support-max-4-bytes-ID.patch | 8 +- ...-dts-qcom-ipq5018-Add-SPI-nand-node.patch} | 9 +- ...pq5018-Add-more-nand-compatible-for-.patch | 5 +- ...clk-qcom-cmn-pll-add-IPQ5018-support.patch | 7 +- ...s-qcom-ipq5018-Add-ethernet-cmn-node.patch | 6 +- ...ntroduce-IPQ5018-internal-PHY-driver.patch | 9 +- ...arm64-dts-qcom-ipq5018-add-mdio-node.patch | 10 +- ...m64-dts-qcom-ipq5018-add-ge_phy-node.patch | 19 +- ...enable-configuration-of-DAC-settings.patch | 111 ++++ ...add-IPQ5018-initvals-and-CDT-feature.patch | 108 ++++ ...remove-the-unsupported-clk-combinati.patch | 6 +- ...phy-rx-and-tx-clk-providers-by-name.patch} | 10 +- ...always-enable-SGMII-auto-negotiation.patch | 4 +- ...sa-qca8k-support-PHY-to-PHY-CPU-link.patch | 49 ++ ...mpd-split-q6_wcss-to-rootpd-and-user.patch | 7 +- ...q6v5_mpd-fix-incorrent-use-of-rproc-.patch | 2 +- ... 0811-firmware-qcom_scm-support-MPD.patch} | 8 +- ...812-soc-qcom-mdt_loader-support-MPD.patch} | 8 +- ...moteproc-qcom_q6v5_mpd-enable-clocks.patch | 2 +- ...teproc-qcom_q6v5_mpd-support-ipq5018.patch | 4 +- ...-add-support-for-passing-v1-bootargs.patch | 163 ++++++ ...4-dts-qcom-ipq5018-add-wifi-support.patch} | 69 ++- ...8-add-tz_apps-reserved-memory-region.patch | 22 + ...less-ath11k-add-bindings-for-QCN6122.patch | 62 +++ .../0900-power-Add-Qualcomm-APM.patch | 3 +- ...egulator-add-Qualcomm-CPR-regulators.patch | 6 +- ...arm64-dts-qcom-ipq6018-add-wifi-node.patch | 2 +- ...07-soc-qcom-fix-smp2p-ack-on-ipq6018.patch | 2 +- ...pq6018-assign-QDSS_AT-clock-to-wifi-.patch | 2 +- .../0911-arm64-cmdline-replacement.patch | 105 ++++ 70 files changed, 1685 insertions(+), 1847 deletions(-) create mode 100644 target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx-base.dtsi delete mode 100644 target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018.dtsi create mode 100644 target/linux/qualcommax/patches-6.6/0069-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch rename target/linux/qualcommax/patches-6.6/{0162-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch => 0080-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch} (100%) rename target/linux/qualcommax/patches-6.6/{0163-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch => 0081-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch} (100%) create mode 100644 target/linux/qualcommax/patches-6.6/0140-arm64-dts-qcom-ipq6018-add-NSS-reserved-memory.patch delete mode 100644 target/linux/qualcommax/patches-6.6/0155-dt-bindings-phy-qcom-document-PCIe-uniphy.patch create mode 100644 target/linux/qualcommax/patches-6.6/0155-dt-bindings-phy-qcom-uniphy-pcie-Document-PCIe-uniphy.patch rename target/linux/qualcommax/patches-6.6/{0157-phy-qcom-add-uniphy-pcie-gen2-driver.patch => 0156-phy-qcom-Introduce-PCIe-UNIPHY-28LP-driver.patch} (53%) create mode 100644 target/linux/qualcommax/patches-6.6/0157-dt-bindings-phy-qcom-uniphy-pcie-add-IPQ5018-compatible.patch create mode 100644 target/linux/qualcommax/patches-6.6/0158-phy-qcom-uniphy-pcie-28lp-add-support-for-IPQ5018.patch rename target/linux/qualcommax/patches-6.6/{0156-dt-bindings-pci-qcom-add-IPQ5018-soc.patch => 0160-dt-bindings-PCI-qcom-Add-IPQ5018-SoC.patch} (98%) rename target/linux/qualcommax/patches-6.6/{0158-pci-qcom-add-support-for-ipq5018.patch => 0161-PCI-qcom-add-support-for-IPQ5018.patch} (90%) rename target/linux/qualcommax/patches-6.6/{0159-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch => 0162-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch} (81%) rename target/linux/qualcommax/patches-6.6/{0408-spi-spi-qpic-fixes-compilation-issues.patch => 0408-spi-spi-qpic-fix-compilation-issues.patch} (50%) rename target/linux/qualcommax/patches-6.6/{0421-arm64-dts-qcom-ipq5018-Add-nand-node.patch => 0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch} (84%) create mode 100644 target/linux/qualcommax/patches-6.6/0714-net-phy-qcom-IPQ5018-enable-configuration-of-DAC-settings.patch create mode 100644 target/linux/qualcommax/patches-6.6/0715-net-phy-qcom-add-IPQ5018-initvals-and-CDT-feature.patch rename target/linux/qualcommax/patches-6.6/{0722-clk-gcc-ipq5018-hack-for-qca-ssdk.patch => 0722-clk-gcc-ipq5018-refer-to-ge-phy-rx-and-tx-clk-providers-by-name.patch} (82%) create mode 100644 target/linux/qualcommax/patches-6.6/0752-net-dsa-qca8k-support-PHY-to-PHY-CPU-link.patch rename target/linux/qualcommax/patches-6.6/{0811-qcom_scm-support-MPD.patch => 0811-firmware-qcom_scm-support-MPD.patch} (92%) rename target/linux/qualcommax/patches-6.6/{0812-mdt_loader-support-MPD.patch => 0812-soc-qcom-mdt_loader-support-MPD.patch} (96%) create mode 100644 target/linux/qualcommax/patches-6.6/0815-remoteproc-qcom_q6v5_mpd-add-support-for-passing-v1-bootargs.patch rename target/linux/qualcommax/patches-6.6/{0815-arm64-dts-qcom-ipq5018-add-wifi-support.patch => 0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch} (73%) create mode 100644 target/linux/qualcommax/patches-6.6/0817-arm64-dts-qcom-ipq5018-add-tz_apps-reserved-memory-region.patch create mode 100644 target/linux/qualcommax/patches-6.6/0820-dt-bindings-net-wireless-ath11k-add-bindings-for-QCN6122.patch create mode 100644 target/linux/qualcommax/patches-6.6/0911-arm64-cmdline-replacement.patch diff --git a/target/linux/qualcommax/Makefile b/target/linux/qualcommax/Makefile index 5829f1fb5..bf63827ac 100644 --- a/target/linux/qualcommax/Makefile +++ b/target/linux/qualcommax/Makefile @@ -9,6 +9,7 @@ CPU_TYPE:=cortex-a53 SUBTARGETS:=ipq50xx ipq60xx ipq807x KERNEL_PATCHVER:=6.1 +KERNEL_TESTING_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ diff --git a/target/linux/qualcommax/config-6.6 b/target/linux/qualcommax/config-6.6 index 1d05868ca..7cdb9dbd4 100644 --- a/target/linux/qualcommax/config-6.6 +++ b/target/linux/qualcommax/config-6.6 @@ -65,8 +65,6 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y CONFIG_CAVIUM_TX2_ERRATUM_219=y CONFIG_CC_HAVE_SHADOW_CALL_STACK=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_QCOM=y @@ -93,6 +91,7 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y @@ -151,8 +150,6 @@ CONFIG_FUNCTION_ALIGNMENT_4B=y CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y @@ -201,8 +198,10 @@ CONFIG_I2C_QUP=y CONFIG_IIO=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IPQ5018_PHY is not set CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_PLL=y +# CONFIG_IPQ_CMN_PLL is not set # CONFIG_IPQ_GCC_4019 is not set # CONFIG_IPQ_GCC_5018 is not set # CONFIG_IPQ_GCC_5332 is not set @@ -280,6 +279,7 @@ CONFIG_NR_CPUS=4 CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y CONFIG_NVMEM=y CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y CONFIG_NVMEM_QCOM_QFPROM=y # CONFIG_NVMEM_QCOM_SEC_QFPROM is not set CONFIG_NVMEM_SYSFS=y @@ -336,6 +336,7 @@ CONFIG_PHY_QCOM_QMP_USB=y CONFIG_PHY_QCOM_QUSB2=y # CONFIG_PHY_QCOM_SGMII_ETH is not set # CONFIG_PHY_QCOM_SNPS_EUSB2 is not set +# CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP is not set # CONFIG_PHY_QCOM_USB_HS_28NM is not set # CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set # CONFIG_PHY_QCOM_USB_SS is not set @@ -409,6 +410,7 @@ CONFIG_QCOM_NET_PHYLIB=y CONFIG_QCOM_PIL_INFO=y # CONFIG_QCOM_Q6V5_ADSP is not set CONFIG_QCOM_Q6V5_COMMON=y +# CONFIG_QCOM_Q6V5_MPD is not set # CONFIG_QCOM_Q6V5_MSS is not set # CONFIG_QCOM_Q6V5_PAS is not set CONFIG_QCOM_Q6V5_WCSS=y @@ -447,7 +449,6 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGULATOR=y # CONFIG_REGULATOR_CPR3 is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_QCOM_REFGEN is not set # CONFIG_REGULATOR_VQMMC_IPQ4019 is not set CONFIG_RELOCATABLE=y CONFIG_REMOTEPROC=y @@ -540,6 +541,7 @@ CONFIG_SPARSE_IRQ=y CONFIG_SPI=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y +# CONFIG_SPI_QPIC_SNAND is not set CONFIG_SPI_QUP=y CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y CONFIG_SWIOTLB=y diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx-base.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx-base.dtsi new file mode 100644 index 000000000..57fe5c53a --- /dev/null +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx-base.dtsi @@ -0,0 +1,325 @@ +#include "ipq5018.dtsi" +#include "ipq5018-ess.dtsi" + +#include +#include +#include + +/ { + + aliases { + ethernet0 = &dp1; + ethernet1 = &dp2; + led-boot = &led_system_blue; + led-failsafe = &led_system_red; + led-running = &led_system_blue; + led-upgrade = &led_system_red; + serial0 = &blsp1_uart1; + }; + + chosen { + bootargs-append = " root=/dev/ubiblock0_0 coherent_pool=2M"; + stdout-path = "serial0:115200n8"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wps-button { + label = "wps"; + gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + reset-button { + label = "reset"; + gpios = <&tlmm 28 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "pwm-leds"; + + led_system_red: red { + color = ; + function = LED_FUNCTION_POWER; + pwms = <&pwm 3 1250000>; + max-brightness = <255>; + }; + + green { + color = ; + function = LED_FUNCTION_POWER; + pwms = <&pwm 0 1250000>; + max-brightness = <255>; + }; + + led_system_blue: blue { + color = ; + function = LED_FUNCTION_POWER; + pwms = <&pwm 1 1250000>; + max-brightness = <255>; + }; + }; + + reserved-memory { + q6_mem_regions: q6_mem_regions@4b000000 { + no-map; + reg = <0x0 0x4b000000 0x0 0x3000000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; +}; + +&crypto { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&pwm { + status = "okay"; + + #pwm-cells = <2>; + pinctrl-0 = <&pwm_pins>; + pinctrl-names = "default"; +}; + +&qfprom { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_pins>; + pinctrl-names = "default"; + status = "okay"; + + partitions { + status = "disabled"; + }; + + nand@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-engine = <&qpic_nand>; + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:SBL1"; + reg = <0x00000000 0x80000>; + read-only; + }; + + partition@80000 { + label = "0:MIBIB"; + reg = <0x00080000 0x80000>; + read-only; + }; + + partition@100000 { + label = "0:QSEE"; + reg = <0x00100000 0x100000>; + read-only; + }; + + partition@200000 { + label = "0:DEVCFG"; + reg = <0x00200000 0x40000>; + read-only; + }; + + partition@240000 { + label = "0:CDT"; + reg = <0x00240000 0x40000>; + read-only; + }; + + partition@280000 { + label = "0:APPSBLENV"; + reg = <0x00280000 0x80000>; + }; + + partition@300000 { + label = "0:APPSBL"; + reg = <0x00300000 0x140000>; + read-only; + }; + + partition@440000 { + label = "0:ART"; + reg = <0x00440000 0x100000>; + read-only; + }; + + partition@540000 { + label = "0:TRAINING"; + reg = <0x00540000 0x80000>; + read-only; + }; + + partition@5c0000 { + label = "u_env"; + reg = <0x005c0000 0x80000>; + }; + + partition@640000 { + label = "s_env"; + reg = <0x00640000 0x40000>; + }; + + partition@680000 { + label = "devinfo"; + reg = <0x00680000 0x40000>; + read-only; + }; + + partition@6c0000 { + label = "kernel"; + reg = <0x006c0000 0x5200000>; + }; + + partition@ec0000 { + label = "rootfs"; + reg = <0x0ec0000 0x4a00000>; + }; + + partition@58c0000 { + label = "alt_kernel"; + reg = <0x058c0000 0x5200000>; + }; + + partition@60c0000 { + label = "alt_rootfs"; + reg = <0x060c0000 0x4a00000>; + }; + + partition@aac0000 { + label = "sysdiag"; + reg = <0x0aac0000 0x200000>; + read-only; + }; + + partition@acc0000 { + label = "syscfg"; + reg = <0x0acc0000 0x4400000>; + read-only; + }; + }; + }; +}; + +&tlmm { + button_pins: button-state { + pins = "gpio27", "gpio28"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio1_pins: mdio-state { + mdc-pins { + pins = "gpio36"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio37"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pwm_pins: pwm-state { + mux_1 { + pins = "gpio1"; + function = "pwm1"; + drive-strength = <8>; + }; + + mux_2 { + pins = "gpio30"; + function = "pwm3"; + drive-strength = <8>; + }; + + mux_3 { + pins = "gpio46"; + function = "pwm0"; + drive-strength = <8>; + }; + }; + + qpic_pins: qpic-state { + clock-pins { + pins = "gpio9"; + function = "qspi_clk"; + drive-strength = <8>; + bias-disable; + }; + + cs-pins { + pins = "gpio8"; + function = "qspi_cs"; + drive-strength = <8>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "qspi_data"; + drive-strength = <8>; + bias-disable; + }; + }; + + serial_0_pins: uart0-state { + pins = "gpio20", "gpio21"; + function = "blsp0_uart0"; + bias-disable; + }; +}; + +&tsens { + status = "okay"; +}; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts index ee95498d0..db045d9a5 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx2000.dts @@ -1,152 +1,28 @@ /dts-v1/; #include "ipq5018.dtsi" -#include "ipq5018-ess.dtsi" - -#include -#include -#include +#include "ipq5018-mx-base.dtsi" / { model = "Linksys MX2000"; compatible = "linksys,mx2000", "qcom,ipq5018"; - - aliases { - ethernet0 = &dp1; - ethernet1 = &dp2; - led-boot = &led_system_blue; - led-failsafe = &led_system_red; - led-running = &led_system_blue; - led-upgrade = &led_system_red; - serial0 = &blsp1_uart1; - }; - - chosen { - bootargs-append = " root=/dev/ubiblock0_0 coherent_pool=2M"; - stdout-path = "serial0:115200n8"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wps-button { - label = "wps"; - gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset-button { - label = "reset"; - gpios = <&tlmm 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "pwm-leds"; - - led_system_red: red { - label = "red:system"; - pwms = <&pwm 3 1250000>; - max-brightness = <255>; - }; - - green { - label = "green:system"; - pwms = <&pwm 0 1250000>; - max-brightness = <255>; - }; - - led_system_blue: blue { - label = "blue:system"; - pwms = <&pwm 1 1250000>; - max-brightness = <255>; - //linux,default-trigger = "default-on"; - }; - }; - - reserved-memory { - tz_appps@4a400000 { - no-map; - reg = <0x0 0x4a400000 0x0 0x400000>; - }; - - q6_mem_regions: q6_mem_regions@4b000000 { - no-map; - reg = <0x0 0x4b000000 0x0 0x3000000>; - }; - - /* from stock DTS: - q6_code_data: q6_code_data@4b000000 { - no-map; - reg = <0x0 0x4b000000 0x0 0x60000>; - }; - - q6_ipq5018_data: q6_ipq5018_data@4c400000 { - no-map; - reg = <0x0 0x4c400000 0x0 0xe00000>; - }; - - q6_m3_region: m3_dump@4d200000 { - no-map; - reg = <0x0 0x4d200000 0x0 0x100000>; - }; - - q6_etr_region: q6_etr_dump@4d300000 { - no-map; - reg = <0x0 0x4d300000 0x0 0x100000>; - }; - - q6_caldb_region: q6_caldb_region@4d400000 { - no-map; - reg = <0x0 0x4d400000 0x0 0x200000>; - }; - - q6_qcn6122_data1: q6_qcn6122_data1@4d600000 { - no-map; - reg = <0x0 0x4d600000 0x0 0x1000000>; - }; - - q6_qcn6122_m3_1: q6_qcn6122_m3_1@4e600000 { - no-map; - reg = <0x0 0x4e600000 0x0 0x100000>; - }; - - q6_qcn6122_etr_1: q6_qcn6122_etr_1@4e700000 { - no-map; - reg = <0x0 0x4e700000 0x0 0x100000>; - }; - - q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4e800000 { - no-map; - reg = <0x0 0x4e800000 0x0 0x500000>; - }; - - q6_qcn6122_data2: q6_qcn6122_data20@4ed00000 { - no-map; - reg = <0x0 0x4ed00000 0x0 0x1000000>; - }; - - q6_qcn6122_m3_2: q6_qcn6122_m3_2@4fd00000 { - no-map; - reg = <0x0 0x4fd00000 0x0 0x100000>; - }; - - q6_qcn6122_etr_2: q6_qcn6122_etr_2@4fe00000 { - no-map; - reg = <0x0 0x4fe00000 0x0 0x100000>; - }; - - q6_qcn6122_caldb_2: q6_qcn6122_caldb_2@4ff00000 { - no-map; - reg = <0x0 0x4ff00000 0x0 0x500000>; - }; - */ - }; }; +/* + * =============================================================== + * _______________________ _______________________ + * | IPQ5018 | | QCA8337 | + * | +------+ +--------+ | | +--------+ +------+ | + * | | MAC0 |---| GE Phy | | | | Phy0 |---| MAC1 | | + * | +------+ +--------+ | | +--------+ +------+ | + * | +------+ +--------+ | | +--------+ +------+ | + * | | MAC1 |---| Uniphy |-+-SGMII-+-| SerDes |---| MAC6 | | + * | +------+ +--------+ | | +--------+ +------+ | + * |_______________________| |_______________________| + * + * =============================================================== + */ + &switch { status = "okay"; @@ -158,7 +34,6 @@ port_id = <1>; mdiobus = <&mdio0>; phy_address = <7>; - // status = "disabled"; }; // MAC1 ---SGMII---> QCA8337 SerDes @@ -170,29 +45,6 @@ }; }; -// MAC0 -> GE Phy -&dp1 { - /* - * =============================================================== - * _______________________ _______________________ - * | IPQ5018 | | QCA8337 | - * | +------+ +--------+ | | +--------+ +------+ | - * | | MAC0 |---| GE Phy |-+--UTP--+-| Phy4 |---| MAC5 | | - * | +------+ +--------+ | | +--------+ +------+ | - * | +------+ +--------+ | | +--------+ +------+ | - * | | MAC1 |---| Uniphy |-+-SGMII-+-| SerDes |---| MAC0 | | - * | +------+ +--------+ | | +--------+ +------+ | - * |_______________________| |_______________________| - * - * =============================================================== - * - * Current drivers don't support such topology. So dp1 and ge_phy - * are useless. But they can't be disabled dut to qca-ssdk use - * ge_phy to detect IPQ5018 dummy switch. - */ - status = "okay"; -}; - // MAC1 ---SGMII---> QCA8337 SerDes &dp2 { status = "okay"; @@ -208,7 +60,9 @@ status = "okay"; }; -// IPQ5018 GE Phy -> QCA8337 Phy1 +/* IPQ5018 GE Phy -> Not connected + * needs to be enabled for QSDK to identify the IPQ5018 dummy switch + */ &ge_phy { status = "okay"; }; @@ -220,7 +74,7 @@ pinctrl-names = "default"; reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; - // QCA8337 Phy0 -> IPQ5018 GE Phy + // QCA8337 Phy0 not connected qca8337_0: ethernet-phy@0 { reg = <0>; }; @@ -256,13 +110,6 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { - reg = <1>; - label = "cpu1"; - phy-handle = <&qca8337_0>; - status = "disabled"; - }; - port@2 { reg = <2>; label = "wan"; @@ -271,7 +118,7 @@ port@3 { reg = <3>; - label = "lan1"; + label = "lan3"; phy-handle = <&qca8337_2>; }; @@ -283,7 +130,7 @@ port@5 { reg = <5>; - label = "lan3"; + label = "lan1"; phy-handle = <&qca8337_4>; }; @@ -303,276 +150,23 @@ }; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board_clk { - clock-frequency = <24000000>; -}; - -&blsp1_uart1 { - status = "okay"; - - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; -}; - -&crypto { - status = "okay"; -}; - -&cryptobam { - status = "okay"; -}; - -&prng { - status = "okay"; -}; - -&pwm { - status = "okay"; - - #pwm-cells = <2>; - pinctrl-0 = <&pwm_pins>; - pinctrl-names = "default"; -}; - -&qfprom { - status = "okay"; -}; - -&qpic_bam { - status = "okay"; -}; - -&qpic_nand { - pinctrl-0 = <&qpic_pins>; - pinctrl-names = "default"; - status = "okay"; - - partitions { - status = "disabled"; - }; - - nand@0 { - compatible = "spi-nand"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-engine = <&qpic_nand>; - - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x00000000 0x80000>; - read-only; - }; - - partition@80000 { - label = "0:MIBIB"; - reg = <0x00080000 0x20000>; - read-only; - }; - - partition@100000 { - label = "0:QSEE"; - reg = <0x00100000 0x100000>; - read-only; - }; - - partition@200000 { - label = "0:DEVCFG"; - reg = <0x00200000 0x40000>; - read-only; - }; - - partition@240000 { - label = "0:CDT"; - reg = <0x00240000 0x40000>; - read-only; - }; - - partition@280000 { - label = "0:APPSBLENV"; - reg = <0x00280000 0x20000>; - }; - - partition@300000 { - label = "0:APPSBL"; - reg = <0x00300000 0x140000>; - read-only; - }; - - partition@440000 { - compatible = "nvmem-cells"; - label = "0:ART"; - reg = <0x00440000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - }; - - partition@540000 { - label = "0:TRAINING"; - reg = <0x00540000 0x80000>; - read-only; - }; - - partition@5c0000 { - label = "u_env"; - reg = <0x005c0000 0x80000>; - }; - - partition@640000 { - label = "s_env"; - reg = <0x00640000 0x40000>; - }; - - partition@680000 { - label = "devinfo"; - reg = <0x00680000 0x40000>; - read-only; - }; - - partition@6c0000 { - label = "kernel"; - reg = <0x006c0000 0x5200000>; - }; - - partition@ec0000 { - label = "rootfs"; - reg = <0x0ec0000 0x4a00000>; - }; - - partition@58c0000 { - label = "alt_kernel"; - reg = <0x058c0000 0x5200000>; - }; - - partition@60c0000 { - label = "alt_rootfs"; - reg = <0x060c0000 0x4a00000>; - }; - - partition@aac0000 { - label = "sysdiag"; - reg = <0x0aac0000 0x200000>; - read-only; - }; - - partition@acc0000 { - label = "syscfg"; - reg = <0x0acc0000 0x4400000>; - read-only; - }; - }; - }; -}; - -&tlmm { - button_pins: button-state { - pins = "gpio27", "gpio28"; - function = "gpio"; - drive-strength = <8>; - bias-pull-up; - }; - - mdio1_pins: mdio-state { - mdc-pins { - pins = "gpio36"; - function = "mdc"; - drive-strength = <8>; - bias-pull-up; - }; - - mdio-pins { - pins = "gpio37"; - function = "mdio"; - drive-strength = <8>; - bias-pull-up; - }; - }; - - pwm_pins: pwm-state { - mux_1 { - pins = "gpio1"; - function = "pwm1"; - drive-strength = <8>; - }; - - mux_2 { - pins = "gpio30"; - function = "pwm3"; - drive-strength = <8>; - }; - - mux_3 { - pins = "gpio46"; - function = "pwm0"; - drive-strength = <8>; - }; - }; - - qpic_pins: qpic-state { - clock-pins { - pins = "gpio9"; - function = "qspi_clk"; - drive-strength = <8>; - bias-disable; - }; - - cs-pins { - pins = "gpio8"; - function = "qspi_cs"; - drive-strength = <8>; - bias-disable; - }; - - data-pins { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "qspi_data"; - drive-strength = <8>; - bias-disable; - }; - }; - - serial_0_pins: uart0-state { - pins = "gpio20", "gpio21"; - function = "blsp0_uart0"; - bias-disable; - }; -}; - -&tsens { - status = "okay"; -}; - &q6v5_wcss { status = "okay"; memory-region = <&q6_mem_regions>; firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt", "ath11k/IPQ5018/hw1.0/m3_fw.mdt", - "ath11k/qcn6122/hw1.0/m3_fw.mdt"; + "ath11k/QCN6122/hw1.0/m3_fw.mdt"; + + /* The QCN6102 radio should map to UPD ID 2. Without */ + /* bootargs, the firmware will expect it to be on UPD ID 3 */ + boot-args = < + /* type: */ 0x1 /* PCIE0 */ + /* length: */ 4 + /* UPD ID: */ 2 + /* reset GPIO: */ 15 + /* reserved: */ 0 0>; - /*qcom,bootargs_smem = <507>;*/ /* hard-coded in mpd driver */ - boot-args = - ; - // IPQ5018 q6_wcss_pd1: pd-1 { firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt"; @@ -597,10 +191,10 @@ // qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>; interrupts-extended = - <&wcss_smp2p_in 8 0>, - <&wcss_smp2p_in 9 0>, - <&wcss_smp2p_in 12 0>, - <&wcss_smp2p_in 11 0>; + <&wcss_smp2p_in 8 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 9 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 12 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 11 IRQ_TYPE_NONE>; interrupt-names = "fatal", "ready", @@ -618,15 +212,15 @@ status = "okay"; }; - // QCN6102 6G + // QCN6102 5G q6_wcss_pd2: pd-2 { firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt"; interrupts-extended = - <&wcss_smp2p_in 16 0>, - <&wcss_smp2p_in 17 0>, - <&wcss_smp2p_in 20 0>, - <&wcss_smp2p_in 19 0>; + <&wcss_smp2p_in 16 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 17 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 20 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 19 IRQ_TYPE_NONE>; interrupt-names = "fatal", "ready", @@ -641,32 +235,6 @@ "shutdown", "stop", "spawn"; - status = "disabled"; - }; - - // QCN6102 5G - q6_wcss_pd3: pd-3 { - firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt"; - - interrupts-extended = - <&wcss_smp2p_in 24 0>, - <&wcss_smp2p_in 25 0>, - <&wcss_smp2p_in 28 0>, - <&wcss_smp2p_in 27 0>; - interrupt-names = - "fatal", - "ready", - "spawn-ack", - "stop-ack"; - - qcom,smem-states = - <&wcss_smp2p_out 24>, - <&wcss_smp2p_out 25>, - <&wcss_smp2p_out 26>; - qcom,smem-state-names = - "shutdown", - "stop", - "spawn"; status = "okay"; }; }; @@ -674,7 +242,6 @@ &wifi0 { // IPQ5018 qcom,rproc = <&q6_wcss_pd1>; - qcom,userpd-subsys-name = "q6v5_wcss_userpd1"; qcom,ath11k-calibration-variant = "Linksys-MX2000"; qcom,ath11k-fw-memory-mode = <2>; qcom,bdf-addr = <0x4c400000>; @@ -684,8 +251,8 @@ &wifi1 { // QCN6102 5G - qcom,rproc = <&q6_wcss_pd3>; - qcom,userpd-subsys-name = "q6v5_wcss_userpd3"; + qcom,rproc = <&q6_wcss_pd2>; + qcom,userpd-subsys-name = "q6v5_wcss_userpd2"; qcom,ath11k-calibration-variant = "Linksys-MX2000"; qcom,ath11k-fw-memory-mode = <2>; qcom,bdf-addr = <0x4d100000>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx5500.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx5500.dts index b1a46ee67..43672d3b5 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx5500.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-mx5500.dts @@ -1,113 +1,28 @@ /dts-v1/; #include "ipq5018.dtsi" -#include "ipq5018-ess.dtsi" - -#include -#include -#include +#include "ipq5018-mx-base.dtsi" / { model = "Linksys MX5500"; compatible = "linksys,mx5500", "qcom,ipq5018"; - - aliases { - ethernet0 = &dp1; - ethernet1 = &dp2; - led-boot = &led_system_blue; - led-failsafe = &led_system_red; - led-running = &led_system_blue; - led-upgrade = &led_system_red; - serial0 = &blsp1_uart1; - }; - - chosen { - bootargs-append = " root=/dev/ubiblock0_0 coherent_pool=2M"; - stdout-path = "serial0:115200n8"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wps-button { - label = "wps"; - gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset-button { - label = "reset"; - gpios = <&tlmm 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "pwm-leds"; - - led_system_red: red { - label = "red:system"; - pwms = <&pwm 3 1250000>; - max-brightness = <255>; - }; - - green { - label = "green:system"; - pwms = <&pwm 0 1250000>; - max-brightness = <255>; - }; - - led_system_blue: blue { - label = "blue:system"; - pwms = <&pwm 1 1250000>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - reserved-memory { - q6_mem_regions: q6_mem_regions@4b000000 { - no-map; - reg = <0x0 0x4b000000 0x0 0x3000000>; - }; - - /* - q6_region: wcnss@4b000000 { - no-map; - reg = <0x0 0x4b000000 0x0 0x01800000>; - }; - - q6_m3_region: m3_dump@4c800000 { - no-map; - reg = <0x0 0x4c800000 0x0 0x100000>; - }; - - q6_etr_region: q6_etr_dump@4c900000 { - no-map; - reg = <0x0 0x4c900000 0x0 0x100000>; - }; - - q6_caldb_region: q6_caldb_region@4cd00000 { - no-map; - reg = <0x0 0x4cd00000 0x0 0x200000>; - }; - - qcn9000_pcie0@4cc00000 { - no-map; - reg = <0x0 0x4cc00000 0x0 0x01e00000>; - }; - */ - - mhi_region1: dma_pool1@4ea00000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x0 0x4ea00000 0x0 0x01000000>; - }; - }; }; +/* + * =============================================================== + * _______________________ _______________________ + * | IPQ5018 | | QCA8337 | + * | +------+ +--------+ | | +--------+ +------+ | + * | | MAC0 |---| GE Phy | | | | Phy0 |---| MAC1 | | + * | +------+ +--------+ | | +--------+ +------+ | + * | +------+ +--------+ | | +--------+ +------+ | + * | | MAC1 |---| Uniphy |-+-SGMII-+-| SerDes |---| MAC6 | | + * | +------+ +--------+ | | +--------+ +------+ | + * |_______________________| |_______________________| + * + * =============================================================== + */ + &switch { status = "okay"; @@ -119,7 +34,6 @@ port_id = <1>; mdiobus = <&mdio0>; phy_address = <7>; - // status = "disabled"; }; // MAC1 ---SGMII---> QCA8337 SerDes @@ -131,29 +45,6 @@ }; }; -// MAC0 -> GE Phy -&dp1 { - /* - * =============================================================== - * _______________________ _______________________ - * | IPQ5018 | | QCA8337 | - * | +------+ +--------+ | | +--------+ +------+ | - * | | MAC0 |---| GE Phy |-+--UTP--+-| Phy4 |---| MAC5 | | - * | +------+ +--------+ | | +--------+ +------+ | - * | +------+ +--------+ | | +--------+ +------+ | - * | | MAC1 |---| Uniphy |-+-SGMII-+-| SerDes |---| MAC0 | | - * | +------+ +--------+ | | +--------+ +------+ | - * |_______________________| |_______________________| - * - * =============================================================== - * - * Current drivers don't support such topology. So dp1 and ge_phy - * are useless. But they can't be disabled dut to qca-ssdk use - * ge_phy to detect IPQ5018 dummy switch. - */ - status = "okay"; -}; - // MAC1 ---SGMII---> QCA8337 SerDes &dp2 { status = "okay"; @@ -169,7 +60,9 @@ status = "okay"; }; -// IPQ5018 GE Phy -> QCA8337 Phy1 +/* IPQ5018 GE Phy -> Not connected + * needs to be enabled for QSDK to identify the IPQ5018 dummy switch + */ &ge_phy { status = "okay"; }; @@ -181,7 +74,7 @@ pinctrl-names = "default"; reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; - // QCA8337 Phy0 -> IPQ5018 GE Phy + // QCA8337 Phy0 not connected qca8337_0: ethernet-phy@0 { reg = <0>; }; @@ -207,24 +100,16 @@ }; // QCA8337 switch - switch1: ethernet-switch@10 { + switch1: ethernet-switch@17 { compatible = "qca,qca8337"; + reg = <17>; #address-cells = <1>; #size-cells = <0>; - reg = <10>; - ports { #address-cells = <1>; #size-cells = <0>; - port@1 { - reg = <1>; - label = "cpu1"; - phy-handle = <&qca8337_0>; - status = "disabled"; - }; - port@2 { reg = <2>; label = "wan"; @@ -233,7 +118,7 @@ port@3 { reg = <3>; - label = "lan1"; + label = "lan3"; phy-handle = <&qca8337_2>; }; @@ -245,7 +130,7 @@ port@5 { reg = <5>; - label = "lan3"; + label = "lan1"; phy-handle = <&qca8337_4>; }; @@ -265,266 +150,11 @@ }; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board_clk { - clock-frequency = <24000000>; -}; - -&blsp1_uart1 { - status = "okay"; - - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; -}; - -&crypto { +&pcie0_phy { status = "okay"; }; -&cryptobam { - status = "okay"; -}; - -&prng { - status = "okay"; -}; - -&pwm { - status = "okay"; - - #pwm-cells = <2>; - - pinctrl-0 = <&pwm_pins>; - pinctrl-names = "default"; -}; - -&qfprom { - status = "okay"; -}; - -&qpic_bam { - status = "okay"; -}; - -&qpic_nand { - pinctrl-0 = <&qpic_pins>; - pinctrl-names = "default"; - status = "okay"; - - partitions { - status = "disabled"; - }; - - nand@0 { - compatible = "spi-nand"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-engine = <&qpic_nand>; - - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x00000000 0x80000>; - read-only; - }; - - partition@80000 { - label = "0:MIBIB"; - reg = <0x00080000 0x20000>; - read-only; - }; - - partition@100000 { - label = "0:QSEE"; - reg = <0x00100000 0x100000>; - read-only; - }; - - partition@200000 { - label = "0:DEVCFG"; - reg = <0x00200000 0x40000>; - read-only; - }; - - partition@240000 { - label = "0:CDT"; - reg = <0x00240000 0x40000>; - read-only; - }; - - partition@280000 { - label = "0:APPSBLENV"; - reg = <0x00280000 0x20000>; - }; - - partition@300000 { - label = "0:APPSBL"; - reg = <0x00300000 0x140000>; - read-only; - }; - - partition@440000 { - compatible = "nvmem-cells"; - label = "0:ART"; - reg = <0x00440000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - }; - - partition@540000 { - label = "0:TRAINING"; - reg = <0x00540000 0x80000>; - read-only; - }; - - partition@5c0000 { - label = "u_env"; - reg = <0x005c0000 0x80000>; - }; - - partition@640000 { - label = "s_env"; - reg = <0x00640000 0x40000>; - }; - - partition@680000 { - label = "devinfo"; - reg = <0x00680000 0x40000>; - read-only; - }; - - partition@6c0000 { - label = "kernel"; - reg = <0x006c0000 0x5200000>; - }; - - partition@ec0000 { - label = "rootfs"; - reg = <0x0ec0000 0x4a00000>; - }; - - partition@58c0000 { - label = "alt_kernel"; - reg = <0x058c0000 0x5200000>; - }; - - partition@60c0000 { - label = "alt_rootfs"; - reg = <0x060c0000 0x4a00000>; - }; - - partition@aac0000 { - label = "sysdiag"; - reg = <0x0aac0000 0x200000>; - read-only; - }; - - partition@acc0000 { - label = "syscfg"; - reg = <0x0acc0000 0x4400000>; - read-only; - }; - }; - }; -}; - -&tlmm { - button_pins: button-state { - pins = "gpio27", "gpio28"; - function = "gpio"; - drive-strength = <8>; - bias-pull-up; - }; - - mdio1_pins: mdio-state { - mdc-pins { - pins = "gpio36"; - function = "mdc"; - drive-strength = <8>; - bias-pull-up; - }; - - mdio-pins { - pins = "gpio37"; - function = "mdio"; - drive-strength = <8>; - bias-pull-up; - }; - }; - - pwm_pins: pwm-state { - mux_1 { - pins = "gpio1"; - function = "pwm1"; - drive-strength = <8>; - }; - - mux_2 { - pins = "gpio30"; - function = "pwm3"; - drive-strength = <8>; - }; - - mux_3 { - pins = "gpio46"; - function = "pwm0"; - drive-strength = <8>; - }; - }; - - qpic_pins: qpic-state { - clock-pins { - pins = "gpio9"; - function = "qspi_clk"; - drive-strength = <8>; - bias-disable; - }; - - cs-pins { - pins = "gpio8"; - function = "qspi_cs"; - drive-strength = <8>; - bias-disable; - }; - - data-pins { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "qspi_data"; - drive-strength = <8>; - bias-disable; - }; - }; - - serial_0_pins: uart0-state { - pins = "gpio20", "gpio21"; - function = "blsp0_uart0"; - bias-disable; - }; -}; - -&tsens { - status = "okay"; -}; - -&pcie_x2phy { - status = "okay"; -}; - -&pcie_x2 { +&pcie0 { status = "okay"; perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; @@ -553,7 +183,7 @@ memory-region = <&q6_mem_regions>; firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt", "ath11k/IPQ5018/hw1.0/m3_fw.mdt"; - + // IPQ5018 q6_wcss_pd1: pd-1 { firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt"; @@ -576,7 +206,6 @@ "gcc_wcss_acmt_clk", "gcc_wcss_axi_m_clk"; - // qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>; interrupts-extended = <&wcss_smp2p_in 8 0>, <&wcss_smp2p_in 9 0>, @@ -603,7 +232,6 @@ &wifi0 { // IPQ5018 qcom,rproc = <&q6_wcss_pd1>; - //qcom,userpd-subsys-name = "q6v5_wcss_userpd1"; qcom,ath11k-calibration-variant = "Linksys-MX5500"; qcom,ath11k-fw-memory-mode = <2>; qcom,bdf-addr = <0x4c400000>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018.dtsi deleted file mode 100644 index 2cbe54efe..000000000 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ /dev/null @@ -1,515 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * IPQ5018 SoC device tree source - * - * Copyright (c) 2023 The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - #address-cells = <2>; - #size-cells = <2>; - - clocks { - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - xo_board_clk: xo-board-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x80000>; - cache-unified; - }; - }; - - cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <200000>; - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <200000>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-ipq5018", "qcom,scm"; - qcom,sdi-enabled; - }; - }; - - memory@40000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x40000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bootloader@4a800000 { - reg = <0x0 0x4a800000 0x0 0x200000>; - no-map; - }; - - sbl@4aa00000 { - reg = <0x0 0x4aa00000 0x0 0x100000>; - no-map; - }; - - smem@4ab00000 { - compatible = "qcom,smem"; - reg = <0x0 0x4ab00000 0x0 0x100000>; - no-map; - - hwlocks = <&tcsr_mutex 3>; - }; - - tz_region: tz@4ac00000 { - reg = <0x0 0x4ac00000 0x0 0x200000>; - no-map; - }; - }; - - soc: soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - - usbphy0: phy@5b000 { - compatible = "qcom,ipq5018-usb-hsphy"; - reg = <0x0005b000 0x120>; - - clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; - - resets = <&gcc GCC_QUSB2_0_PHY_BCR>; - - #phy-cells = <0>; - - status = "disabled"; - }; - - mdio0: mdio@88000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio"; - reg = <0x88000 0x64>; - resets = <&gcc GCC_GEPHY_MDC_SW_ARES>, - <&gcc GCC_GEPHY_DSP_HW_ARES>; - clocks = <&gcc GCC_MDIO0_AHB_CLK>; - clock-names = "gcc_mdio_ahb_clk"; - status = "disabled"; - - gephy: ethernet-phy@7 { - #clock-cells = <1>; - reg = <7>; - resets = <&gcc GCC_GEPHY_BCR>, - <&gcc GCC_GEPHY_RX_ARES>, - <&gcc GCC_GEPHY_TX_ARES>; - clocks = <&gcc GCC_GEPHY_RX_CLK>, - <&gcc GCC_GEPHY_TX_CLK>; - }; - }; - - mdio1: mdio@90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "qcom,ipq5018-mdio"; - reg = <0x90000 0x64>; - clocks = <&gcc GCC_MDIO1_AHB_CLK>; - clock-names = "gcc_mdio_ahb_clk"; - status = "disabled"; - }; - - uniphy0: eth-uniphy@98000 { - compatible = "qcom,ipq5018-eth-uniphy"; - #clock-cells = <1>; - #phy-cells = <0>; - reg = <0x98000 0x800>, - <0x9b000 0x800>, - <0x19475c4 0x4>; - reg-names = "uniphy", - "cmn", - "tcsr"; - clocks = <&gcc GCC_CMN_BLK_AHB_CLK>, - <&gcc GCC_CMN_BLK_SYS_CLK>, - <&gcc GCC_UNIPHY_AHB_CLK>, - <&gcc GCC_UNIPHY_SYS_CLK>, - <&gcc GCC_UNIPHY_RX_CLK>, - <&gcc GCC_UNIPHY_TX_CLK>; - resets = <&gcc GCC_UNIPHY_BCR>, - <&gcc GCC_UNIPHY_AHB_ARES>, - <&gcc GCC_UNIPHY_SYS_ARES>, - <&gcc GCC_UNIPHY_RX_ARES>, - <&gcc GCC_UNIPHY_TX_ARES>; - - status = "disabled"; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq5018-tlmm"; - reg = <0x01000000 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 47>; - interrupt-controller; - #interrupt-cells = <2>; - - uart1_pins: uart1-state { - pins = "gpio31", "gpio32", "gpio33", "gpio34"; - function = "blsp1_uart1"; - drive-strength = <8>; - bias-pull-down; - }; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-ipq5018"; - reg = <0x01800000 0x80000>; - clocks = <&xo_board_clk>, - <&sleep_clk>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <&gephy 0>, - <&gephy 1>, - <&uniphy0 0>, - <&uniphy0 1>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - tcsr_mutex: hwlock@1905000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01905000 0x20000>; - #hwlock-cells = <1>; - }; - - sdhc_1: mmc@7804000 { - compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x7804000 0x1000>; - reg-names = "hc"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board_clk>; - clock-names = "iface", "core", "xo"; - non-removable; - status = "disabled"; - }; - - blsp_dma: dma-controller@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x1d000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x078b5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 4>, <&blsp_dma 5>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - usb: usb@8af8800 { - compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; - reg = <0x08af8800 0x400>; - - interrupts = ; - interrupt-names = "hs_phy_irq"; - - clocks = <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_SLEEP_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; - clock-names = "core", - "iface", - "sleep", - "mock_utmi"; - - resets = <&gcc GCC_USB0_BCR>; - - qcom,select-utmi-as-pipe-clk; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - status = "disabled"; - - usb_dwc: usb@8a00000 { - compatible = "snps,dwc3"; - reg = <0x08a00000 0xe000>; - clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; - clock-names = "ref"; - interrupts = ; - phy-names = "usb2-phy"; - phys = <&usbphy0>; - tx-fifo-resize; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - }; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - reg = <0x0b000000 0x1000>, /* GICD */ - <0x0b002000 0x2000>, /* GICC */ - <0x0b001000 0x1000>, /* GICH */ - <0x0b004000 0x2000>; /* GICV */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0b00a000 0x1ffa>; - - v2m0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - reg = <0x00000000 0xff8>; - msi-controller; - }; - - v2m1: v2m@1000 { - compatible = "arm,gic-v2m-frame"; - reg = <0x00001000 0xff8>; - msi-controller; - }; - }; - - watchdog: watchdog@b017000 { - compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; - reg = <0x0b017000 0x40>; - interrupts = ; - clocks = <&sleep_clk>; - }; - - apcs_glb: mailbox@b111000 { - compatible = "qcom,ipq5018-apcs-apps-global", - "qcom,ipq6018-apcs-apps-global"; - reg = <0x0b111000 0x1000>; - #clock-cells = <1>; - clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; - clock-names = "pll", "xo", "gpll0"; - #mbox-cells = <1>; - }; - - a53pll: clock@b116000 { - compatible = "qcom,ipq5018-a53pll"; - reg = <0x0b116000 0x40>; - #clock-cells = <0>; - clocks = <&xo_board_clk>; - clock-names = "xo"; - }; - - timer@b120000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - frame@b120000 { - reg = <0x0b121000 0x1000>, - <0x0b122000 0x1000>; - interrupts = , - ; - frame-number = <0>; - }; - - frame@b123000 { - reg = <0xb123000 0x1000>; - interrupts = ; - frame-number = <1>; - status = "disabled"; - }; - - frame@b124000 { - frame-number = <2>; - interrupts = ; - reg = <0x0b124000 0x1000>; - status = "disabled"; - }; - - frame@b125000 { - reg = <0x0b125000 0x1000>; - interrupts = ; - frame-number = <3>; - status = "disabled"; - }; - - frame@b126000 { - reg = <0x0b126000 0x1000>; - interrupts = ; - frame-number = <4>; - status = "disabled"; - }; - - frame@b127000 { - reg = <0x0b127000 0x1000>; - interrupts = ; - frame-number = <5>; - status = "disabled"; - }; - - frame@b128000 { - reg = <0x0b128000 0x1000>; - interrupts = ; - frame-number = <6>; - status = "disabled"; - }; - }; - - gmac0: ethernet@39c00000 { - compatible = "qcom,ipq50xx-gmac", "snps,dwmac"; - reg = <0x39C00000 0x10000>; - clocks = <&gcc GCC_GMAC0_SYS_CLK>, - <&gcc GCC_GMAC0_CFG_CLK>, - <&gcc GCC_SNOC_GMAC0_AHB_CLK>, - <&gcc GCC_SNOC_GMAC0_AXI_CLK>, - <&gcc GCC_GMAC0_RX_CLK>, - <&gcc GCC_GMAC0_TX_CLK>, - <&gcc GCC_GMAC0_PTP_CLK>; - clock-names = "sys", - "cfg", - "ahb", - "axi", - "rx", - "tx", - "ptp"; - resets = <&gcc GCC_GMAC0_BCR>; - interrupts = ; - interrupt-names = "macirq"; - - phy-handle = <&gephy>; - phy-mode = "sgmii"; - - status = "disabled"; - }; - - gmac1: ethernet@39d00000 { - compatible = "qcom,ipq50xx-gmac", "snps,dwmac"; - reg = <0x39D00000 0x10000>; - reg-names = "stmmaceth"; - clocks = <&gcc GCC_GMAC1_SYS_CLK>, - <&gcc GCC_GMAC1_CFG_CLK>, - <&gcc GCC_SNOC_GMAC1_AHB_CLK>, - <&gcc GCC_SNOC_GMAC1_AXI_CLK>, - <&gcc GCC_GMAC1_RX_CLK>, - <&gcc GCC_GMAC1_TX_CLK>, - <&gcc GCC_GMAC1_PTP_CLK>; - clock-names = "sys", - "cfg", - "ahb", - "axi", - "rx", - "tx", - "ptp"; - resets = <&gcc GCC_GMAC1_BCR>; - interrupts = ; - interrupt-names = "macirq"; - - phys = <&uniphy0>; - phy-names = "uniphy"; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/target/linux/qualcommax/ipq50xx/base-files/etc/board.d/02_network b/target/linux/qualcommax/ipq50xx/base-files/etc/board.d/02_network index 75f93cc84..363c446af 100644 --- a/target/linux/qualcommax/ipq50xx/base-files/etc/board.d/02_network +++ b/target/linux/qualcommax/ipq50xx/base-files/etc/board.d/02_network @@ -28,9 +28,10 @@ ipq50xx_setup_macs() case "$board" in linksys,mx2000|\ linksys,mx5500) - wan_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) - lan_mac=$(macaddr_add "$wan_mac" 1) - label_mac="$wan_mac" + label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) + lan_mac=$label_mac + wan_mac=$label_mac + ucidef_set_network_device_mac eth0 $label_mac ;; esac diff --git a/target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata index aff880013..77311502b 100644 --- a/target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata +++ b/target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata @@ -28,7 +28,7 @@ case "$FIRMWARE" in ;; esac ;; -"ath11k/qcn6122/hw1.0/cal-ahb-soc@0:wifi1@c000000.bin") +"ath11k/QCN6122/hw1.0/cal-ahb-b00a040.wifi1.bin") case "$board" in glinet,gl-b3000) caldata_extract "0:ART" 0x26800 0x20000 diff --git a/target/linux/qualcommax/ipq50xx/config-default b/target/linux/qualcommax/ipq50xx/config-default index bc5daabd1..63c1d9dd9 100644 --- a/target/linux/qualcommax/ipq50xx/config-default +++ b/target/linux/qualcommax/ipq50xx/config-default @@ -15,9 +15,12 @@ CONFIG_QCA83XX_PHY=y CONFIG_QCOM_Q6V5_MPD=y CONFIG_QCOM_QMI_HELPERS=y -CONFIG_PHY_QCOM_IPQ5018_UNIPHY_PCIE=y +CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP=y CONFIG_PCIE_QCOM=y CONFIG_PWM=y CONFIG_PWM_IPQ=y -CONFIG_LEDS_PWM=y \ No newline at end of file +CONFIG_LEDS_PWM=y + +CONFIG_PHY_QCOM_M31_USB=y +CONFIG_USB_DWC3_QCOM=y diff --git a/target/linux/qualcommax/patches-6.6/0065-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch b/target/linux/qualcommax/patches-6.6/0065-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch index e6f42a228..8e973e63f 100644 --- a/target/linux/qualcommax/patches-6.6/0065-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch +++ b/target/linux/qualcommax/patches-6.6/0065-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch @@ -15,8 +15,8 @@ Signed-off-by: Bjorn Andersson --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -391,6 +391,13 @@ - clock-names = "xo"; +@@ -181,6 +181,13 @@ + }; }; + watchdog: watchdog@b017000 { diff --git a/target/linux/qualcommax/patches-6.6/0069-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch b/target/linux/qualcommax/patches-6.6/0069-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch new file mode 100644 index 000000000..6d598bf50 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0069-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch @@ -0,0 +1,26 @@ +From 79796e87215db9587d6c66ec6f6781e091bc6464 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 16 Aug 2023 18:45:41 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq5018: indicate that SDI should be + disabled + +Now that SCM has support for indicating that SDI has been enabled by +default, lets set the property so SCM disables it during probing. + +Signed-off-by: Robert Marko +Link: https://lore.kernel.org/r/20230816164641.3371878-4-robimarko@gmail.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -57,6 +57,7 @@ + firmware { + scm { + compatible = "qcom,scm-ipq5018", "qcom,scm"; ++ qcom,sdi-enabled; + }; + }; + diff --git a/target/linux/qualcommax/patches-6.6/0073-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch b/target/linux/qualcommax/patches-6.6/0073-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch index 5fb0c0bd1..99fdae732 100644 --- a/target/linux/qualcommax/patches-6.6/0073-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch +++ b/target/linux/qualcommax/patches-6.6/0073-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch @@ -16,9 +16,9 @@ Signed-off-by: Bjorn Andersson --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -204,6 +204,19 @@ - status = "disabled"; - }; +@@ -94,6 +94,19 @@ + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + usbphy0: phy@5b000 { + compatible = "qcom,ipq5018-usb-hsphy"; @@ -36,10 +36,11 @@ Signed-off-by: Bjorn Andersson tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; -@@ -300,6 +313,47 @@ +@@ -156,6 +169,47 @@ + status = "disabled"; }; - usb: usb@8af8800 { ++ usb: usb@8af8800 { + compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + @@ -80,7 +81,6 @@ Signed-off-by: Bjorn Andersson + }; + }; + -+ usb: usb@8af8800 { - compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; - reg = <0x08af8800 0x400>; - + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ diff --git a/target/linux/qualcommax/patches-6.6/0074-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch b/target/linux/qualcommax/patches-6.6/0074-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch index a0e901a46..d0d9e45de 100644 --- a/target/linux/qualcommax/patches-6.6/0074-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch +++ b/target/linux/qualcommax/patches-6.6/0074-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch @@ -16,8 +16,8 @@ Signed-off-by: Bjorn Andersson --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -288,6 +288,16 @@ - qcom,ee = <0>; +@@ -159,6 +159,16 @@ + status = "disabled"; }; + blsp_dma: dma-controller@7884000 { @@ -33,7 +33,7 @@ Signed-off-by: Bjorn Andersson blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078af000 0x200>; -@@ -298,6 +308,20 @@ +@@ -169,6 +179,20 @@ status = "disabled"; }; @@ -51,6 +51,6 @@ Signed-off-by: Bjorn Andersson + status = "disabled"; + }; + - blsp1_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; + usb: usb@8af8800 { + compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; diff --git a/target/linux/qualcommax/patches-6.6/0077-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch b/target/linux/qualcommax/patches-6.6/0077-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch index ed4ce2746..72bec54cb 100644 --- a/target/linux/qualcommax/patches-6.6/0077-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch +++ b/target/linux/qualcommax/patches-6.6/0077-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch @@ -14,12 +14,38 @@ Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230925102826.405446-4-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson --- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 37 +++++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -76,6 +76,25 @@ +@@ -5,6 +5,7 @@ + * Copyright (c) 2023 The Linux Foundation. All rights reserved. + */ + ++#include + #include + #include + #include +@@ -36,6 +37,8 @@ + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ operating-points-v2 = <&cpu_opp_table>; + }; + + CPU1: cpu@1 { +@@ -44,6 +47,8 @@ + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ operating-points-v2 = <&cpu_opp_table>; + }; + + L2_0: l2-cache { +@@ -54,6 +59,25 @@ }; }; @@ -45,7 +71,7 @@ Signed-off-by: Bjorn Andersson firmware { scm { compatible = "qcom,scm-ipq5018", "qcom,scm"; -@@ -476,6 +495,24 @@ +@@ -267,6 +291,24 @@ clocks = <&sleep_clk>; }; diff --git a/target/linux/qualcommax/patches-6.6/0078-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch b/target/linux/qualcommax/patches-6.6/0078-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch index 2b165c59b..97631e715 100644 --- a/target/linux/qualcommax/patches-6.6/0078-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch +++ b/target/linux/qualcommax/patches-6.6/0078-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch @@ -26,9 +26,9 @@ Signed-off-by: Bjorn Andersson --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -141,6 +141,24 @@ - hwlocks = <&tcsr_mutex 3>; - }; +@@ -106,6 +106,24 @@ + #size-cells = <2>; + ranges; + bootloader@4a800000 { + reg = <0x0 0x4a800000 0x0 0x200000>; @@ -51,16 +51,16 @@ Signed-off-by: Bjorn Andersson tz_region: tz@4ac00000 { reg = <0x0 0x4ac00000 0x0 0x200000>; no-map; -@@ -275,6 +293,12 @@ +@@ -166,6 +184,12 @@ + #power-domain-cells = <1>; }; - tcsr_mutex: hwlock@1905000 { ++ tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + -+ tcsr_mutex: hwlock@1905000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01905000 0x20000>; - #hwlock-cells = <1>; + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x7804000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.6/0162-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch b/target/linux/qualcommax/patches-6.6/0080-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch similarity index 100% rename from target/linux/qualcommax/patches-6.6/0162-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch rename to target/linux/qualcommax/patches-6.6/0080-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch diff --git a/target/linux/qualcommax/patches-6.6/0163-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.6/0081-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch similarity index 100% rename from target/linux/qualcommax/patches-6.6/0163-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch rename to target/linux/qualcommax/patches-6.6/0081-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch diff --git a/target/linux/qualcommax/patches-6.6/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch b/target/linux/qualcommax/patches-6.6/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch index 2f7746646..69b009745 100644 --- a/target/linux/qualcommax/patches-6.6/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch +++ b/target/linux/qualcommax/patches-6.6/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch @@ -1,12 +1,11 @@ From d24bc08bfc66f47d6e0a294a080d62893a7696b5 Mon Sep 17 00:00:00 2001 -From: Chukun Pan +From: Robert Marko Date: Thu, 18 Jan 2024 21:30:21 +0800 Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator Add LDOA2 regulator of MP5496 to support SDCC voltage scaling. -Suggested-by: Robert Marko -Signed-off-by: Chukun Pan +Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/linux/qualcommax/patches-6.6/0140-arm64-dts-qcom-ipq6018-add-NSS-reserved-memory.patch b/target/linux/qualcommax/patches-6.6/0140-arm64-dts-qcom-ipq6018-add-NSS-reserved-memory.patch new file mode 100644 index 000000000..84591c845 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0140-arm64-dts-qcom-ipq6018-add-NSS-reserved-memory.patch @@ -0,0 +1,27 @@ +From 7e102b1eb2ca3eff7a6f33ebeab17825e6f70956 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 4 Nov 2024 22:01:24 +0100 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add NSS reserved memory + +It seems that despite NSS not being supported in OpenWrt the memory it +usually uses needs to be reserved anyway for stability reasons. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -199,6 +199,11 @@ + no-map; + }; + ++ nss_region: memory@40000000 { ++ reg = <0x0 0x40000000 0x0 0x01000000>; ++ no-map; ++ }; ++ + bootloader@4a100000 { + reg = <0x0 0x4a100000 0x0 0x400000>; + no-map; diff --git a/target/linux/qualcommax/patches-6.6/0153-thermal-qcom-tsens-add-support-for-IPQ5018-tsens.patch b/target/linux/qualcommax/patches-6.6/0153-thermal-qcom-tsens-add-support-for-IPQ5018-tsens.patch index 85bb7f66d..0de11daf7 100644 --- a/target/linux/qualcommax/patches-6.6/0153-thermal-qcom-tsens-add-support-for-IPQ5018-tsens.patch +++ b/target/linux/qualcommax/patches-6.6/0153-thermal-qcom-tsens-add-support-for-IPQ5018-tsens.patch @@ -112,7 +112,7 @@ Signed-off-by: Sricharan Ramabadhran /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_8956; -+extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956, data_ipq5018; ++extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_8956, data_ipq5018; /* TSENS v2 targets */ extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; diff --git a/target/linux/qualcommax/patches-6.6/0154-dts-qcom-IPQ5018-add-tsens-node.patch b/target/linux/qualcommax/patches-6.6/0154-dts-qcom-IPQ5018-add-tsens-node.patch index b520e6104..4f9b8abfa 100644 --- a/target/linux/qualcommax/patches-6.6/0154-dts-qcom-IPQ5018-add-tsens-node.patch +++ b/target/linux/qualcommax/patches-6.6/0154-dts-qcom-IPQ5018-add-tsens-node.patch @@ -15,7 +15,7 @@ Signed-off-by: Sricharan Ramabadhran --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -254,6 +254,117 @@ +@@ -149,6 +149,117 @@ status = "disabled"; }; @@ -133,10 +133,11 @@ Signed-off-by: Sricharan Ramabadhran tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; -@@ -651,6 +762,64 @@ - }; +@@ -391,6 +502,64 @@ + }; + }; }; - ++ + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; @@ -194,7 +195,6 @@ Signed-off-by: Sricharan Ramabadhran + }; + }; + }; -+ + timer { compatible = "arm,armv8-timer"; - interrupts = , diff --git a/target/linux/qualcommax/patches-6.6/0155-dt-bindings-phy-qcom-document-PCIe-uniphy.patch b/target/linux/qualcommax/patches-6.6/0155-dt-bindings-phy-qcom-document-PCIe-uniphy.patch deleted file mode 100644 index a66d027ce..000000000 --- a/target/linux/qualcommax/patches-6.6/0155-dt-bindings-phy-qcom-document-PCIe-uniphy.patch +++ /dev/null @@ -1,92 +0,0 @@ -From: Nitheesh Sekar -Subject: [PATCH] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy -Date: Tue, 3 Oct 2023 17:38:41 +0530 - -Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018. - -Signed-off-by: Nitheesh Sekar ---- - .../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 77 +++++++++++++++++++ - 1 file changed, 77 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml -@@ -0,0 +1,77 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/qcom,ipq5018-uniphy-pcie.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Qualcomm IPQ5018 UNIPHY PCIe PHY driver -+ -+maintainers: -+ - Nitheesh Sekar -+ - Sricharan Ramabadhran -+ -+properties: -+ compatible: -+ enum: -+ - qcom,ipq5018-uniphy-pcie-gen2x1 -+ - qcom,ipq5018-uniphy-pcie-gen2x2 -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ maxItems: 1 -+ -+ clock-names: -+ items: -+ - const: pipe_clk -+ -+ resets: -+ maxItems: 2 -+ -+ reset-names: -+ items: -+ - const: phy -+ - const: phy_phy -+ -+ "#phy-cells": -+ const: 0 -+ -+ "#clock-cells": -+ const: 0 -+ -+ clock-output-names: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - resets -+ - reset-names -+ - clocks -+ - clock-names -+ - "#phy-cells" -+ - "#clock-cells" -+ - clock-output-names -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ -+ phy@86000 { -+ compatible = "qcom,ipq5018-uniphy-pcie-gen2x2"; -+ reg = <0x86000 0x800>; -+ #phy-cells = <0>; -+ #clock-cells = <0>; -+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -+ clock-names = "pipe_clk"; -+ clock-output-names = "pcie0_pipe_clk"; -+ assigned-clocks = <&gcc GCC_PCIE1_PIPE_CLK>; -+ assigned-clock-rates = <125000000>; -+ resets = <&gcc GCC_PCIE0_PHY_BCR>, -+ <&gcc GCC_PCIE0PHY_PHY_BCR>; -+ reset-names = "phy", "phy_phy"; -+ }; diff --git a/target/linux/qualcommax/patches-6.6/0155-dt-bindings-phy-qcom-uniphy-pcie-Document-PCIe-uniphy.patch b/target/linux/qualcommax/patches-6.6/0155-dt-bindings-phy-qcom-uniphy-pcie-Document-PCIe-uniphy.patch new file mode 100644 index 000000000..7997976d7 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0155-dt-bindings-phy-qcom-uniphy-pcie-Document-PCIe-uniphy.patch @@ -0,0 +1,85 @@ +From: Varadarajan Narayanan +Date: Thu, 2 Jan 2025 17:00:15 +0530 +Subject: [PATCH] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy + +From: Nitheesh Sekar + +Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332. + +Signed-off-by: Nitheesh Sekar +Signed-off-by: Varadarajan Narayanan +--- +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml +@@ -0,0 +1,71 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm UNIPHY PCIe 28LP PHY ++ ++maintainers: ++ - Nitheesh Sekar ++ - Varadarajan Narayanan ++ ++description: ++ PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC ++ ++properties: ++ compatible: ++ enum: ++ - qcom,ipq5332-uniphy-pcie-phy ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: pcie pipe clock ++ - description: pcie ahb clock ++ ++ resets: ++ items: ++ - description: phy reset ++ - description: ahb reset ++ - description: cfg reset ++ ++ "#phy-cells": ++ const: 0 ++ ++ "#clock-cells": ++ const: 0 ++ ++ num-lanes: true ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - resets ++ - "#phy-cells" ++ - "#clock-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ pcie0_phy: phy@4b0000 { ++ compatible = "qcom,ipq5332-uniphy-pcie-phy"; ++ reg = <0x004b0000 0x800>; ++ ++ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, ++ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; ++ ++ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, ++ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, ++ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; ++ ++ #clock-cells = <0>; ++ ++ #phy-cells = <0>; ++ }; diff --git a/target/linux/qualcommax/patches-6.6/0157-phy-qcom-add-uniphy-pcie-gen2-driver.patch b/target/linux/qualcommax/patches-6.6/0156-phy-qcom-Introduce-PCIe-UNIPHY-28LP-driver.patch similarity index 53% rename from target/linux/qualcommax/patches-6.6/0157-phy-qcom-add-uniphy-pcie-gen2-driver.patch rename to target/linux/qualcommax/patches-6.6/0156-phy-qcom-Introduce-PCIe-UNIPHY-28LP-driver.patch index 06b8a2c9e..f30db1463 100644 --- a/target/linux/qualcommax/patches-6.6/0157-phy-qcom-add-uniphy-pcie-gen2-driver.patch +++ b/target/linux/qualcommax/patches-6.6/0156-phy-qcom-Introduce-PCIe-UNIPHY-28LP-driver.patch @@ -1,77 +1,79 @@ -From: Nitheesh Sekar +From: Varadarajan Narayanan +Date: Thu, 2 Jan 2025 17:00:16 +0530 Subject: [PATCH] phy: qcom: Introduce PCIe UNIPHY 28LP driver -Date: Tue, 3 Oct 2023 17:38:43 +0530 + +From: Nitheesh Sekar Add Qualcomm PCIe UNIPHY 28LP driver support present -in Qualcomm IPQ5018 SoC and the phy init sequence. +in Qualcomm IPQ5332 SoC and the phy init sequence. +Reviewed-by: Dmitry Baryshkov Signed-off-by: Nitheesh Sekar +Signed-off-by: Varadarajan Narayanan --- - drivers/phy/qualcomm/Kconfig | 12 + - drivers/phy/qualcomm/Makefile | 1 + - .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 336 ++++++++++++++++++ - 3 files changed, 349 insertions(+) - create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c - --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig -@@ -35,6 +35,18 @@ config PHY_QCOM_IPQ4019_USB - help - Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. +@@ -154,6 +154,18 @@ config PHY_QCOM_M31_USB + management. This driver is required even for peripheral only or + host only mode configurations. -+config PHY_QCOM_IPQ5018_UNIPHY_PCIE -+ bool "PCIE IPQ5018 UNIPHY PHY driver" ++config PHY_QCOM_UNIPHY_PCIE_28LP ++ bool "PCIE UNIPHY 28LP PHY driver" + depends on ARCH_QCOM + depends on HAS_IOMEM + depends on OF + select GENERIC_PHY + help -+ Enable this to support the IPQ5018 PCIe UNIPHY phy transceiver that -+ is used with PCIe controllers on Qualcomm IPQ5018 chips. It ++ Enable this to support the PCIe UNIPHY 28LP phy transceiver that ++ is used with PCIe controllers on Qualcomm IPQ5332 chips. It + handles PHY initialization, clock management required after + resetting the hardware and power management. + - config PHY_QCOM_IPQ806X_SATA - tristate "Qualcomm IPQ806x SATA SerDes/PHY driver" - depends on ARCH_QCOM + config PHY_QCOM_USB_HS + tristate "Qualcomm USB HS PHY module" + depends on USB_ULPI_BUS --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile -@@ -3,6 +3,7 @@ obj-$(CONFIG_PHY_ATH79_USB) += phy-ath7 - obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o - obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o - obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o -+obj-$(CONFIG_PHY_QCOM_IPQ5018_UNIPHY_PCIE) += phy-qcom-ipq5018-uniphy-pcie.o - obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o - obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o - obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o +@@ -17,6 +17,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY) += + obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o + obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o + obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o ++obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP) += phy-qcom-uniphy-pcie-28lp.o + obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o + obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o + obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o --- /dev/null -+++ b/drivers/phy/qualcomm/phy-qcom-ipq5018-uniphy-pcie.c -@@ -0,0 +1,332 @@ ++++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +@@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* -+ * Copyright (c) 2023, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2025, The Linux Foundation. All rights reserved. + */ + +#include +#include ++#include +#include +#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include +#include ++#include ++#include ++#include ++#include ++#include +#include ++#include + -+#define PIPE_CLK_DELAY_MIN_US 5000 -+#define PIPE_CLK_DELAY_MAX_US 5100 ++#define RST_ASSERT_DELAY_MIN_US 100 ++#define RST_ASSERT_DELAY_MAX_US 150 ++#define PIPE_CLK_DELAY_MIN_US 5000 ++#define PIPE_CLK_DELAY_MAX_US 5100 ++#define CLK_EN_DELAY_MIN_US 30 ++#define CLK_EN_DELAY_MAX_US 50 +#define CDR_CTRL_REG_1 0x80 +#define CDR_CTRL_REG_2 0x84 +#define CDR_CTRL_REG_3 0x88 -+#define CDR_CTRL_REG_4 0x8C ++#define CDR_CTRL_REG_4 0x8c +#define CDR_CTRL_REG_5 0x90 +#define CDR_CTRL_REG_6 0x94 +#define CDR_CTRL_REG_7 0x98 @@ -83,6 +85,10 @@ Signed-off-by: Nitheesh Sekar +#define SSCG_CTRL_REG_6 0xb0 +#define PCS_INTERNAL_CONTROL_2 0x2d8 + ++#define PHY_CFG_PLLCFG 0x220 ++#define PHY_CFG_EIOS_DTCT_REG 0x3e4 ++#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 ++ +#define PHY_MODE_FIXED 0x1 + +enum qcom_uniphy_pcie_type { @@ -91,93 +97,65 @@ Signed-off-by: Nitheesh Sekar + PHY_TYPE_PCIE_GEN3, +}; + -+struct uniphy_regs { -+ unsigned int offset; -+ unsigned int val; ++struct qcom_uniphy_pcie_regs { ++ u32 offset; ++ u32 val; +}; + -+struct uniphy_pcie_data { -+ int lanes; -+ /* 2nd lane offset */ -+ int lane_offset; -+ unsigned int phy_type; -+ const struct uniphy_regs *init_seq; -+ unsigned int init_seq_num; ++struct qcom_uniphy_pcie_data { ++ int lane_offset; /* offset between the lane register bases */ ++ u32 phy_type; ++ const struct qcom_uniphy_pcie_regs *init_seq; ++ u32 init_seq_num; ++ u32 pipe_clk_rate; +}; + +struct qcom_uniphy_pcie { + struct phy phy; + struct device *dev; -+ const struct uniphy_pcie_data *data; ++ const struct qcom_uniphy_pcie_data *data; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *resets; + void __iomem *base; ++ int lanes; +}; + -+#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) ++#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) + -+static const struct uniphy_regs ipq5018_regs[] = { ++static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { + { -+ .offset = SSCG_CTRL_REG_4, -+ .val = 0x1cb9, ++ .offset = PHY_CFG_PLLCFG, ++ .val = 0x30, + }, { -+ .offset = SSCG_CTRL_REG_5, -+ .val = 0x023a, ++ .offset = PHY_CFG_EIOS_DTCT_REG, ++ .val = 0x53ef, + }, { -+ .offset = SSCG_CTRL_REG_3, -+ .val = 0xd360, -+ }, { -+ .offset = SSCG_CTRL_REG_1, -+ .val = 0x1, -+ }, { -+ .offset = SSCG_CTRL_REG_2, -+ .val = 0xeb, -+ }, { -+ .offset = CDR_CTRL_REG_4, -+ .val = 0x3f9, -+ }, { -+ .offset = CDR_CTRL_REG_5, -+ .val = 0x1c9, -+ }, { -+ .offset = CDR_CTRL_REG_2, -+ .val = 0x419, -+ }, { -+ .offset = CDR_CTRL_REG_1, -+ .val = 0x200, -+ }, { -+ .offset = PCS_INTERNAL_CONTROL_2, -+ .val = 0xf101, ++ .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, ++ .val = 0xcf, + }, +}; + -+static const struct uniphy_pcie_data ipq5018_2x1_data = { -+ .lanes = 1, ++static const struct qcom_uniphy_pcie_data ipq5332_data = { + .lane_offset = 0x800, -+ .phy_type = PHY_TYPE_PCIE_GEN2, -+ .init_seq = ipq5018_regs, -+ .init_seq_num = ARRAY_SIZE(ipq5018_regs), -+}; -+ -+static const struct uniphy_pcie_data ipq5018_2x2_data = { -+ .lanes = 2, -+ .lane_offset = 0x800, -+ .phy_type = PHY_TYPE_PCIE_GEN2, -+ .init_seq = ipq5018_regs, -+ .init_seq_num = ARRAY_SIZE(ipq5018_regs), ++ .phy_type = PHY_TYPE_PCIE_GEN3, ++ .init_seq = ipq5332_regs, ++ .init_seq_num = ARRAY_SIZE(ipq5332_regs), ++ .pipe_clk_rate = 250000000, +}; + +static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) +{ -+ const struct uniphy_pcie_data *data = phy->data; -+ const struct uniphy_regs *init_seq; ++ const struct qcom_uniphy_pcie_data *data = phy->data; ++ const struct qcom_uniphy_pcie_regs *init_seq; + void __iomem *base = phy->base; ++ int lane, i; + -+ for (int lane = 0; lane < data->lanes; lane++) { ++ for (lane = 0; lane < phy->lanes; lane++) { + init_seq = data->init_seq; + -+ for (int i = 0; i < data->init_seq_num; i++, init_seq++) -+ writel(init_seq->val, base + init_seq->offset); ++ for (i = 0; i < data->init_seq_num; i++) ++ writel(init_seq[i].val, base + init_seq[i].offset); + + base += data->lane_offset; + } @@ -189,15 +167,13 @@ Signed-off-by: Nitheesh Sekar + + clk_bulk_disable_unprepare(phy->num_clks, phy->clks); + -+ reset_control_assert(phy->resets); -+ -+ return 0; ++ return reset_control_assert(phy->resets); +} + +static int qcom_uniphy_pcie_power_on(struct phy *x) +{ -+ int ret; + struct qcom_uniphy_pcie *phy = phy_get_drvdata(x); ++ int ret; + + ret = reset_control_assert(phy->resets); + if (ret) { @@ -205,11 +181,7 @@ Signed-off-by: Nitheesh Sekar + return ret; + } + -+ /* -+ * Delay periods before and after reset deassert are working values -+ * from downstream Codeaurora kernel -+ */ -+ usleep_range(100, 150); ++ usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US); + + ret = reset_control_deassert(phy->resets); + if (ret) { @@ -225,22 +197,20 @@ Signed-off-by: Nitheesh Sekar + return ret; + } + -+ usleep_range(30, 50); ++ usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US); + + qcom_uniphy_pcie_init(phy); + return 0; +} + +static inline int qcom_uniphy_pcie_get_resources(struct platform_device *pdev, -+ struct qcom_uniphy_pcie *phy) ++ struct qcom_uniphy_pcie *phy) +{ + struct resource *res; + + phy->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); -+ if (IS_ERR(phy->base)) { -+ dev_err(phy->dev, "cannot get phy registers\n"); ++ if (IS_ERR(phy->base)) + return PTR_ERR(phy->base); -+ } + + phy->num_clks = devm_clk_bulk_get_all(phy->dev, &phy->clks); + if (phy->num_clks < 0) @@ -271,49 +241,29 @@ Signed-off-by: Nitheesh Sekar + * clk | +-------+ | +-----+ + * +---------------+ + */ -+static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, -+ struct device_node *np) ++static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id) +{ -+ struct clk_fixed_rate *fixed; -+ struct clk_init_data init = { }; -+ int ret; ++ const struct qcom_uniphy_pcie_data *data = phy->data; ++ struct clk_hw *hw; ++ char name[64]; + -+ ret = of_property_read_string(np, "clock-output-names", &init.name); -+ if (ret) { -+ dev_err(phy->dev, "%pOFn: No clock-output-names\n", np); -+ return ret; -+ } ++ snprintf(name, sizeof(name), "phy%d_pipe_clk_src", id); ++ hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0, ++ data->pipe_clk_rate); ++ if (IS_ERR(hw)) ++ return dev_err_probe(phy->dev, PTR_ERR(hw), ++ "Unable to register %s\n", name); + -+ fixed = devm_kzalloc(phy->dev, sizeof(*fixed), GFP_KERNEL); -+ if (!fixed) -+ return -ENOMEM; -+ -+ init.ops = &clk_fixed_rate_ops; -+ fixed->fixed_rate = 125000000; -+ fixed->hw.init = &init; -+ -+ ret = devm_clk_hw_register(phy->dev, &fixed->hw); -+ if (ret) -+ return ret; -+ -+ ret = devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, -+ &fixed->hw); -+ if (ret) -+ return ret; -+ -+ return 0; ++ return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw); +} + +static const struct of_device_id qcom_uniphy_pcie_id_table[] = { + { -+ .compatible = "qcom,ipq5018-uniphy-pcie-gen2x1", -+ .data = &ipq5018_2x1_data, ++ .compatible = "qcom,ipq5332-uniphy-pcie-phy", ++ .data = &ipq5332_data, ++ }, { ++ /* Sentinel */ + }, -+ { -+ .compatible = "qcom,ipq5018-uniphy-pcie-gen2x2", -+ .data = &ipq5018_2x2_data, -+ }, -+ { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table); + @@ -325,12 +275,11 @@ Signed-off-by: Nitheesh Sekar + +static int qcom_uniphy_pcie_probe(struct platform_device *pdev) +{ -+ struct qcom_uniphy_pcie *phy; -+ int ret; -+ struct phy *generic_phy; + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; -+ struct device_node *np = of_node_get(dev->of_node); ++ struct qcom_uniphy_pcie *phy; ++ struct phy *generic_phy; ++ int ret; + + phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); + if (!phy) @@ -343,21 +292,24 @@ Signed-off-by: Nitheesh Sekar + if (!phy->data) + return -EINVAL; + -+ ret = qcom_uniphy_pcie_get_resources(pdev, phy); -+ if (ret < 0) { -+ dev_err_probe(&pdev->dev, ret, "failed to get resources: %d\n", ret); -+ return ret; -+ } ++ phy->lanes = 1; ++ ret = of_property_read_u32(dev->of_node, "num-lanes", &phy->lanes); + -+ ret = phy_pipe_clk_register(phy, np); -+ if (ret) -+ dev_err_probe(&pdev->dev, ret, "failed to register phy pipe clk\n"); ++ ret = qcom_uniphy_pcie_get_resources(pdev, phy); ++ if (ret < 0) ++ return dev_err_probe(&pdev->dev, ret, ++ "failed to get resources: %d\n", ret); + + generic_phy = devm_phy_create(phy->dev, NULL, &pcie_ops); + if (IS_ERR(generic_phy)) + return PTR_ERR(generic_phy); + + phy_set_drvdata(generic_phy, phy); ++ ++ ret = phy_pipe_clk_register(phy, generic_phy->id); ++ if (ret) ++ dev_err(&pdev->dev, "failed to register phy pipe clk\n"); ++ + phy_provider = devm_of_phy_provider_register(phy->dev, + of_phy_simple_xlate); + if (IS_ERR(phy_provider)) @@ -369,13 +321,12 @@ Signed-off-by: Nitheesh Sekar +static struct platform_driver qcom_uniphy_pcie_driver = { + .probe = qcom_uniphy_pcie_probe, + .driver = { -+ .name = "qcom-ipq5018-uniphy-pcie", -+ .owner = THIS_MODULE, ++ .name = "qcom-uniphy-pcie", + .of_match_table = qcom_uniphy_pcie_id_table, + }, +}; + +module_platform_driver(qcom_uniphy_pcie_driver); + -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("PCIE QCOM IPQ5018 UNIPHY driver"); ++MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/qualcommax/patches-6.6/0157-dt-bindings-phy-qcom-uniphy-pcie-add-IPQ5018-compatible.patch b/target/linux/qualcommax/patches-6.6/0157-dt-bindings-phy-qcom-uniphy-pcie-add-IPQ5018-compatible.patch new file mode 100644 index 000000000..9951daa8f --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0157-dt-bindings-phy-qcom-uniphy-pcie-add-IPQ5018-compatible.patch @@ -0,0 +1,25 @@ +From: George Moussalem +Date: Tue, 07 Jan 2025 17:34:13 +0400 +Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie add IPQ5018 compatible + +The Qualcomm UNIPHY PCIe PHY 28lp part of the IPQ5332 SoC is also present on +the IPQ5018 SoC, so adding the compatible for IPQ5018. + +Signed-off-by: George Moussalem +--- +--- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml ++++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml +@@ -11,11 +11,12 @@ maintainers: + - Varadarajan Narayanan + + description: +- PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC ++ PCIe and USB combo PHY found in Qualcomm IPQ5018 and IPQ5332 SoCs + + properties: + compatible: + enum: ++ - qcom,ipq5018-uniphy-pcie-phy + - qcom,ipq5332-uniphy-pcie-phy + + reg: diff --git a/target/linux/qualcommax/patches-6.6/0158-phy-qcom-uniphy-pcie-28lp-add-support-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.6/0158-phy-qcom-uniphy-pcie-28lp-add-support-for-IPQ5018.patch new file mode 100644 index 000000000..aedb95987 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0158-phy-qcom-uniphy-pcie-28lp-add-support-for-IPQ5018.patch @@ -0,0 +1,77 @@ +From: George Moussalem +Date: Tue, 07 Jan 2025 17:34:13 +0400 +Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie 28lp add support for IPQ5018 + +The Qualcomm UNIPHY PCIe PHY 28lp is found on both IPQ5332 and IPQ5018. +Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018. + +Signed-off-by: George Moussalem +--- +--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c ++++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +@@ -76,6 +76,40 @@ struct qcom_uniphy_pcie { + + #define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) + ++static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = { ++ { ++ .offset = SSCG_CTRL_REG_4, ++ .val = 0x1cb9, ++ }, { ++ .offset = SSCG_CTRL_REG_5, ++ .val = 0x023a, ++ }, { ++ .offset = SSCG_CTRL_REG_3, ++ .val = 0xd360, ++ }, { ++ .offset = SSCG_CTRL_REG_1, ++ .val = 0x1, ++ }, { ++ .offset = SSCG_CTRL_REG_2, ++ .val = 0xeb, ++ }, { ++ .offset = CDR_CTRL_REG_4, ++ .val = 0x3f9, ++ }, { ++ .offset = CDR_CTRL_REG_5, ++ .val = 0x1c9, ++ }, { ++ .offset = CDR_CTRL_REG_2, ++ .val = 0x419, ++ }, { ++ .offset = CDR_CTRL_REG_1, ++ .val = 0x200, ++ }, { ++ .offset = PCS_INTERNAL_CONTROL_2, ++ .val = 0xf101, ++ }, ++}; ++ + static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { + { + .offset = PHY_CFG_PLLCFG, +@@ -89,6 +123,14 @@ static const struct qcom_uniphy_pcie_reg + }, + }; + ++static const struct qcom_uniphy_pcie_data ipq5018_data = { ++ .lane_offset = 0x800, ++ .phy_type = PHY_TYPE_PCIE_GEN2, ++ .init_seq = ipq5018_regs, ++ .init_seq_num = ARRAY_SIZE(ipq5018_regs), ++ .pipe_clk_rate = 125000000, ++}; ++ + static const struct qcom_uniphy_pcie_data ipq5332_data = { + .lane_offset = 0x800, + .phy_type = PHY_TYPE_PCIE_GEN3, +@@ -212,6 +254,9 @@ static inline int phy_pipe_clk_register( + + static const struct of_device_id qcom_uniphy_pcie_id_table[] = { + { ++ .compatible = "qcom,ipq5018-uniphy-pcie-phy", ++ .data = &ipq5018_data, ++ }, { + .compatible = "qcom,ipq5332-uniphy-pcie-phy", + .data = &ipq5332_data, + }, { diff --git a/target/linux/qualcommax/patches-6.6/0156-dt-bindings-pci-qcom-add-IPQ5018-soc.patch b/target/linux/qualcommax/patches-6.6/0160-dt-bindings-PCI-qcom-Add-IPQ5018-SoC.patch similarity index 98% rename from target/linux/qualcommax/patches-6.6/0156-dt-bindings-pci-qcom-add-IPQ5018-soc.patch rename to target/linux/qualcommax/patches-6.6/0160-dt-bindings-PCI-qcom-Add-IPQ5018-SoC.patch index db59aea28..caa988910 100644 --- a/target/linux/qualcommax/patches-6.6/0156-dt-bindings-pci-qcom-add-IPQ5018-soc.patch +++ b/target/linux/qualcommax/patches-6.6/0160-dt-bindings-PCI-qcom-Add-IPQ5018-SoC.patch @@ -1,6 +1,6 @@ From: Nitheesh Sekar -Subject: [PATCH] dt-bindings: PCI: qcom: Add IPQ5108 SoC Date: Tue, 3 Oct 2023 17:38:42 +0530 +Subject: [PATCH] dt-bindings: PCI: qcom: Add IPQ5108 SoC Add support for the PCIe controller on the Qualcomm IPQ5108 SoC to the bindings. @@ -16,7 +16,7 @@ Signed-off-by: Nitheesh Sekar - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 -+ - qcom,pcie-ipq5018 ++ - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 diff --git a/target/linux/qualcommax/patches-6.6/0158-pci-qcom-add-support-for-ipq5018.patch b/target/linux/qualcommax/patches-6.6/0161-PCI-qcom-add-support-for-IPQ5018.patch similarity index 90% rename from target/linux/qualcommax/patches-6.6/0158-pci-qcom-add-support-for-ipq5018.patch rename to target/linux/qualcommax/patches-6.6/0161-PCI-qcom-add-support-for-IPQ5018.patch index 0acc24cfc..bd8f51b84 100644 --- a/target/linux/qualcommax/patches-6.6/0158-pci-qcom-add-support-for-ipq5018.patch +++ b/target/linux/qualcommax/patches-6.6/0161-PCI-qcom-add-support-for-IPQ5018.patch @@ -28,7 +28,7 @@ Signed-off-by: Nitheesh Sekar }; union qcom_pcie_resources { -@@ -1056,17 +1057,10 @@ static int qcom_pcie_get_resources_2_9_0 +@@ -1073,17 +1074,10 @@ static int qcom_pcie_get_resources_2_9_0 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; @@ -49,7 +49,7 @@ Signed-off-by: Nitheesh Sekar res->rst = devm_reset_control_array_get_exclusive(dev); if (IS_ERR(res->rst)) -@@ -1079,7 +1073,7 @@ static void qcom_pcie_deinit_2_9_0(struc +@@ -1096,7 +1090,7 @@ static void qcom_pcie_deinit_2_9_0(struc { struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; @@ -58,7 +58,7 @@ Signed-off-by: Nitheesh Sekar } static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) -@@ -1108,7 +1102,7 @@ static int qcom_pcie_init_2_9_0(struct q +@@ -1125,7 +1119,7 @@ static int qcom_pcie_init_2_9_0(struct q usleep_range(2000, 2500); @@ -67,7 +67,7 @@ Signed-off-by: Nitheesh Sekar } static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) -@@ -1613,6 +1607,7 @@ static const struct of_device_id qcom_pc +@@ -1641,6 +1635,7 @@ static const struct of_device_id qcom_pc { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, diff --git a/target/linux/qualcommax/patches-6.6/0159-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch b/target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch similarity index 81% rename from target/linux/qualcommax/patches-6.6/0159-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch rename to target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch index 1641cd0a8..f51d10350 100644 --- a/target/linux/qualcommax/patches-6.6/0159-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch +++ b/target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch @@ -2,79 +2,88 @@ From: Nitheesh Sekar Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PCIe related nodes Date: Tue, 3 Oct 2023 17:38:45 +0530 -Add phy and controller nodes for PCIe_x2 and PCIe_x1. -PCIe_x2 is 2-lane Gen2 and PCIe_x1 is 1-lane Gen2. +Add phy and controller nodes for PCIe0 and PCIe1. +PCIe0 is 2-lane Gen2 and PCIe1 is 1-lane Gen2. Signed-off-by: Nitheesh Sekar +Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 186 +++++++++++++++++++++++++- 1 file changed, 184 insertions(+), 2 deletions(-) --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -254,6 +254,38 @@ +@@ -149,6 +149,42 @@ status = "disabled"; }; -+ pcie_x1phy: phy@7e000{ -+ compatible = "qcom,ipq5018-uniphy-pcie-gen2x1"; ++ pcie1_phy: phy@7e000{ ++ compatible = "qcom,ipq5018-uniphy-pcie-phy"; + reg = <0x0007e000 0x800>; -+ #phy-cells = <0>; -+ #clock-cells = <0>; ++ + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; -+ clock-names = "pipe_clk"; -+ clock-output-names = "pcie1_pipe_clk"; -+ assigned-clocks = <&gcc GCC_PCIE1_PIPE_CLK>; -+ assigned-clock-rates = <125000000>; ++ + resets = <&gcc GCC_PCIE1_PHY_BCR>, -+ <&gcc GCC_PCIE1PHY_PHY_BCR>; -+ reset-names = "phy", "phy_phy"; ++ <&gcc GCC_PCIE1PHY_PHY_BCR>; ++ ++ #clock-cells = <0>; ++ ++ #phy-cells = <0>; ++ ++ num-lanes = <1>; ++ + status = "disabled"; + }; + -+ pcie_x2phy: phy@86000{ -+ compatible = "qcom,ipq5018-uniphy-pcie-gen2x2"; ++ pcie0_phy: phy@86000{ ++ compatible = "qcom,ipq5018-uniphy-pcie-phy"; + reg = <0x00086000 0x800>; -+ #phy-cells = <0>; -+ #clock-cells = <0>; ++ + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -+ clock-names = "pipe_clk"; -+ clock-output-names = "pcie0_pipe_clk"; -+ assigned-clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -+ assigned-clock-rates = <125000000>; ++ + resets = <&gcc GCC_PCIE0_PHY_BCR>, -+ <&gcc GCC_PCIE0PHY_PHY_BCR>; -+ reset-names = "phy", "phy_phy"; ++ <&gcc GCC_PCIE0PHY_PHY_BCR>; ++ ++ #clock-cells = <0>; ++ ++ #phy-cells = <0>; ++ ++ num-lanes = <2>; ++ + status = "disabled"; + }; + qfprom: qfprom@a0000 { compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; reg = <0xa0000 0x1000>; -@@ -388,8 +420,8 @@ +@@ -283,8 +319,8 @@ reg = <0x01800000 0x80000>; clocks = <&xo_board_clk>, <&sleep_clk>, - <0>, - <0>, -+ <&pcie_x2phy>, -+ <&pcie_x1phy>, ++ <&pcie0_phy>, ++ <&pcie1_phy>, <0>, <0>, <0>, -@@ -818,6 +850,142 @@ - }; +@@ -501,6 +537,146 @@ + status = "disabled"; }; }; + -+ pcie_x1: pcie@80000000 { ++ pcie1: pcie@80000000 { + compatible = "qcom,pcie-ipq5018"; + reg = <0x80000000 0xf1d>, + <0x80000f20 0xa8>, + <0x80001000 0x1000>, + <0x00078000 0x3000>, + <0x80100000 0x1000>; -+ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ reg-names = "dbi", ++ "elbi", ++ "atu", ++ "parf", ++ "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; @@ -83,7 +92,7 @@ Signed-off-by: Nitheesh Sekar + #address-cells = <3>; + #size-cells = <2>; + -+ phys = <&pcie_x1phy>; ++ phys = <&pcie1_phy>; + phy-names ="pciephy"; + + ranges = <0x81000000 0 0x80200000 0x80200000 0 0x00100000>, /* I/O */ @@ -105,7 +114,6 @@ Signed-off-by: Nitheesh Sekar + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; -+ + clock-names = "iface", + "axi_m", + "axi_s", @@ -121,7 +129,6 @@ Signed-off-by: Nitheesh Sekar + <&gcc GCC_PCIE1_AHB_ARES>, + <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; -+ + reset-names = "pipe", + "sleep", + "sticky", @@ -135,14 +142,18 @@ Signed-off-by: Nitheesh Sekar + status = "disabled"; + }; + -+ pcie_x2: pcie@a0000000 { ++ pcie0: pcie@a0000000 { + compatible = "qcom,pcie-ipq5018"; + reg = <0xa0000000 0xf1d>, + <0xa0000f20 0xa8>, + <0xa0001000 0x1000>, + <0x00080000 0x3000>, + <0xa0100000 0x1000>; -+ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ reg-names = "dbi", ++ "elbi", ++ "atu", ++ "parf", ++ "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; @@ -151,7 +162,7 @@ Signed-off-by: Nitheesh Sekar + #address-cells = <3>; + #size-cells = <2>; + -+ phys = <&pcie_x2phy>; ++ phys = <&pcie0_phy>; + phy-names ="pciephy"; + + ranges = <0x81000000 0 0xa0200000 0xa0200000 0 0x00100000>, /* I/O */ @@ -173,7 +184,6 @@ Signed-off-by: Nitheesh Sekar + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; -+ + clock-names = "iface", + "axi_m", + "axi_s", @@ -189,7 +199,6 @@ Signed-off-by: Nitheesh Sekar + <&gcc GCC_PCIE0_AHB_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; -+ + reset-names = "pipe", + "sleep", + "sticky", @@ -204,4 +213,4 @@ Signed-off-by: Nitheesh Sekar + }; }; - timer { + thermal-zones { diff --git a/target/linux/qualcommax/patches-6.6/0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch b/target/linux/qualcommax/patches-6.6/0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch index 9f4386a29..7a0031666 100644 --- a/target/linux/qualcommax/patches-6.6/0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch +++ b/target/linux/qualcommax/patches-6.6/0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch @@ -8,7 +8,7 @@ Signed-off-by: George Moussalem --- --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -447,6 +447,11 @@ +@@ -337,6 +337,11 @@ #hwlock-cells = <1>; }; diff --git a/target/linux/qualcommax/patches-6.6/0303-arm64-dts-qcom-IPQ5018-enable-the-download-mode-support.patch b/target/linux/qualcommax/patches-6.6/0303-arm64-dts-qcom-IPQ5018-enable-the-download-mode-support.patch index 5707e6858..265695d1c 100644 --- a/target/linux/qualcommax/patches-6.6/0303-arm64-dts-qcom-IPQ5018-enable-the-download-mode-support.patch +++ b/target/linux/qualcommax/patches-6.6/0303-arm64-dts-qcom-IPQ5018-enable-the-download-mode-support.patch @@ -9,7 +9,7 @@ Signed-off-by: George Moussalem --- --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -99,6 +99,7 @@ +@@ -82,6 +82,7 @@ scm { compatible = "qcom,scm-ipq5018", "qcom,scm"; qcom,sdi-enabled; diff --git a/target/linux/qualcommax/patches-6.6/0305-pinctrl-qcom-IPQ5018-update-pwm-groups.patch b/target/linux/qualcommax/patches-6.6/0305-pinctrl-qcom-IPQ5018-update-pwm-groups.patch index 486112295..476e5f6ba 100644 --- a/target/linux/qualcommax/patches-6.6/0305-pinctrl-qcom-IPQ5018-update-pwm-groups.patch +++ b/target/linux/qualcommax/patches-6.6/0305-pinctrl-qcom-IPQ5018-update-pwm-groups.patch @@ -1,3 +1,12 @@ +From: George Moussalem +Subject: [PATCH] pinctrl: qcom: IPQ5018: update pwm groups +Date: Wed, 27 Nov 2024 09:14:11 +0400 + +GPIO 1, 30, and 46 are used to control PWM1, PWM3, and PWM0 respectively which +in turn drive the PWM led, so let's update the pwm# and pingroups accordingly. + +Signed-off-by: George Moussalem +--- --- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c @@ -541,7 +541,7 @@ static const char * const qdss_tracectl_ diff --git a/target/linux/qualcommax/patches-6.6/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch b/target/linux/qualcommax/patches-6.6/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch index 74b82ea0a..d60e91697 100644 --- a/target/linux/qualcommax/patches-6.6/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch +++ b/target/linux/qualcommax/patches-6.6/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch @@ -8,7 +8,7 @@ Signed-off-by: George Moussalem --- --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -453,6 +453,16 @@ +@@ -343,6 +343,16 @@ reg = <0x01937000 0x21000>; }; diff --git a/target/linux/qualcommax/patches-6.6/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch b/target/linux/qualcommax/patches-6.6/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch index 97ddceb95..57d434271 100644 --- a/target/linux/qualcommax/patches-6.6/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch +++ b/target/linux/qualcommax/patches-6.6/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch @@ -8,7 +8,7 @@ Signed-off-by: George Moussalem --- --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -398,6 +398,30 @@ +@@ -297,6 +297,30 @@ #thermal-sensor-cells = <1>; }; diff --git a/target/linux/qualcommax/patches-6.6/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch b/target/linux/qualcommax/patches-6.6/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch index 72551502f..87d9bdb27 100644 --- a/target/linux/qualcommax/patches-6.6/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch +++ b/target/linux/qualcommax/patches-6.6/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch @@ -8,7 +8,7 @@ Signed-off-by: George Moussalem --- --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -359,6 +359,14 @@ +@@ -258,6 +258,14 @@ }; }; diff --git a/target/linux/qualcommax/patches-6.6/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch b/target/linux/qualcommax/patches-6.6/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch index 788d6cb92..72085061f 100644 --- a/target/linux/qualcommax/patches-6.6/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch +++ b/target/linux/qualcommax/patches-6.6/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch @@ -8,7 +8,7 @@ Signed-off-by: George Moussalem --- --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -542,6 +542,16 @@ +@@ -422,6 +422,16 @@ status = "disabled"; }; diff --git a/target/linux/qualcommax/patches-6.6/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch b/target/linux/qualcommax/patches-6.6/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch index 94002f7b5..5447e78fa 100644 --- a/target/linux/qualcommax/patches-6.6/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch +++ b/target/linux/qualcommax/patches-6.6/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch @@ -8,7 +8,7 @@ Signed-off-by: George Moussalem --- --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -580,6 +580,21 @@ +@@ -446,6 +446,21 @@ status = "disabled"; }; diff --git a/target/linux/qualcommax/patches-6.6/0400-mtd-rawnand-add-support-for-TH58NYG3S0HBAI4.patch b/target/linux/qualcommax/patches-6.6/0400-mtd-rawnand-add-support-for-TH58NYG3S0HBAI4.patch index c7632d47c..b293c26fb 100644 --- a/target/linux/qualcommax/patches-6.6/0400-mtd-rawnand-add-support-for-TH58NYG3S0HBAI4.patch +++ b/target/linux/qualcommax/patches-6.6/0400-mtd-rawnand-add-support-for-TH58NYG3S0HBAI4.patch @@ -1,33 +1,3 @@ -From 8d8b37d3af2bdccf0a37d2017d876bfc6ce42552 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Fri, 20 Oct 2023 23:18:21 +0800 -Subject: [PATCH 1/1] mtd: rawnand: add support for TH58NYG3S0HBAI4 NAND flash - -The Toshiba TH58NYG3S0HBAI4 is detected with 128 byte OOB while the flash -has 256 bytes OOB. Since it is not an ONFI compliant NAND, the model name -cannot be read from anywhere, add a static NAND ID entry to correct this. - -However, the NAND ID of this flash is inconsistent with the datasheet. -The actual NAND ID is only 4 ID bytes, the last ID byte is missing. - -Datasheet available at (the ID table is on page 50): -https://europe.kioxia.com/content/dam/kioxia/newidr/productinfo/datasheet/201910/DST_TH58NYG3S0HBAI4-TDE_EN_31565.pdf - -Datasheet NAND ID: {0x98, 0xa3, 0x91, 0x26, 0x76} -Actual NAND ID: {0x98, 0xa3, 0x91, 0x26} - -It seems that this flash may be counterfeit, but another Toshiba flash -also has the same problem. Maybe the driver has a bug, or some Toshiba -nand flash is like this. Anyway, add a static NAND ID entry with only -4 ID bytes as a hack to make sure it works. - -Tested on Arcadyan AW1000 flashed with OpenWrt. - -Signed-off-by: Chukun Pan ---- - drivers/mtd/nand/raw/nand_ids.c | 3 +++ - 1 file changed, 3 insertions(+) - --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -58,6 +58,9 @@ struct nand_flash_dev nand_flash_ids[] = diff --git a/target/linux/qualcommax/patches-6.6/0408-spi-spi-qpic-fixes-compilation-issues.patch b/target/linux/qualcommax/patches-6.6/0408-spi-spi-qpic-fix-compilation-issues.patch similarity index 50% rename from target/linux/qualcommax/patches-6.6/0408-spi-spi-qpic-fixes-compilation-issues.patch rename to target/linux/qualcommax/patches-6.6/0408-spi-spi-qpic-fix-compilation-issues.patch index 9cf56af55..03b18e082 100644 --- a/target/linux/qualcommax/patches-6.6/0408-spi-spi-qpic-fixes-compilation-issues.patch +++ b/target/linux/qualcommax/patches-6.6/0408-spi-spi-qpic-fix-compilation-issues.patch @@ -1,11 +1,26 @@ +From: George Moussalem +Subject: [PATCH] spi: spi-qpic: fix compilation issues +Date: Sun, 06 Oct 2024 16:34:11 +0400 + +The compiler will throw a warning when freeing a variable, setting values +of u32 to zero using memset, when the number of bytes is greater than the +size of the variable passed, so let's set each of the 8 variables +contiguously set in memory as part of the structure to zero. + +The output type of the remove function is void while it should return an +integer indicating success (0) or a negative number as an error. So let's +switch to use the new .remove_new function which expects nothing to be +returned + +Signed-off-by: George Moussalem +--- --- a/drivers/mtd/nand/qpic_common.c +++ b/drivers/mtd/nand/qpic_common.c -@@ -82,7 +82,15 @@ void qcom_clear_bam_transaction(struct q +@@ -82,7 +82,14 @@ void qcom_clear_bam_transaction(struct q if (!nandc->props->supports_bam) return; - memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8); -+ // memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8); + bam_txn->bam_ce_pos = 0; + bam_txn->bam_ce_start = 0; + bam_txn->cmd_sgl_pos = 0; diff --git a/target/linux/qualcommax/patches-6.6/0411-spi-spi-qpic-snand-support-BCH8.patch b/target/linux/qualcommax/patches-6.6/0411-spi-spi-qpic-snand-support-BCH8.patch index 056fc3ea9..6442361b0 100644 --- a/target/linux/qualcommax/patches-6.6/0411-spi-spi-qpic-snand-support-BCH8.patch +++ b/target/linux/qualcommax/patches-6.6/0411-spi-spi-qpic-snand-support-BCH8.patch @@ -3,7 +3,10 @@ From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:11 +0800 Subject: [PATCH 1/2] spi: spi-qpic-snand: support BCH8 -Signed-off-by: hzy +Add BCH8 error-correcting code support for QPIC SPI Nand controller. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- drivers/spi/spi-qpic-snand.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/linux/qualcommax/patches-6.6/0412-mtd-spinand-qpic-only-support-max-4-bytes-ID.patch b/target/linux/qualcommax/patches-6.6/0412-mtd-spinand-qpic-only-support-max-4-bytes-ID.patch index 0d246fd5e..3f50be257 100644 --- a/target/linux/qualcommax/patches-6.6/0412-mtd-spinand-qpic-only-support-max-4-bytes-ID.patch +++ b/target/linux/qualcommax/patches-6.6/0412-mtd-spinand-qpic-only-support-max-4-bytes-ID.patch @@ -1,9 +1,13 @@ From 3d550dc3eb4eaa2fe1d0668ed67e835c91487d61 Mon Sep 17 00:00:00 2001 -From: hzy +From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:11 +0800 Subject: [PATCH 2/2] mtd: spinand: qpic only support max 4 bytes ID -Signed-off-by: hzy +The QPIC SPI NAND controller supports a max of 4 bytes of device ID. +As such, set a maximum of 4 bytes. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- drivers/mtd/nand/spi/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-nand-node.patch b/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch similarity index 84% rename from target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-nand-node.patch rename to target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch index b725400d7..2de155637 100644 --- a/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-nand-node.patch +++ b/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch @@ -1,16 +1,19 @@ From c2019f64539dd24e6e0da3cea2219d6f9e6b03e4 Mon Sep 17 00:00:00 2001 From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:11 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq5018: Add nand node +Subject: [PATCH] arm64: dts: qcom: ipq5018: Add SPI nand node -Signed-off-by: hzy +Add SPI NAND support for IPQ5018 SoC. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -595,6 +595,36 @@ +@@ -461,6 +461,36 @@ status = "disabled"; }; diff --git a/target/linux/qualcommax/patches-6.6/0431-arm64-dts-qcom-ipq5018-Add-more-nand-compatible-for-.patch b/target/linux/qualcommax/patches-6.6/0431-arm64-dts-qcom-ipq5018-Add-more-nand-compatible-for-.patch index 16f0bfda0..fdbea3cf6 100644 --- a/target/linux/qualcommax/patches-6.6/0431-arm64-dts-qcom-ipq5018-Add-more-nand-compatible-for-.patch +++ b/target/linux/qualcommax/patches-6.6/0431-arm64-dts-qcom-ipq5018-Add-more-nand-compatible-for-.patch @@ -4,14 +4,15 @@ Date: Sun, 8 Sep 2024 16:40:11 +0800 Subject: [PATCH] arm64: dts: qcom: ipq5018: Add more nand compatible for uboot to fix partitions -Signed-off-by: hzy +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -607,7 +607,7 @@ +@@ -473,7 +473,7 @@ }; qpic_nand: qpic-nand@79b0000 { diff --git a/target/linux/qualcommax/patches-6.6/0703-clk-qcom-cmn-pll-add-IPQ5018-support.patch b/target/linux/qualcommax/patches-6.6/0703-clk-qcom-cmn-pll-add-IPQ5018-support.patch index 9c46fa153..9d0d52b8e 100644 --- a/target/linux/qualcommax/patches-6.6/0703-clk-qcom-cmn-pll-add-IPQ5018-support.patch +++ b/target/linux/qualcommax/patches-6.6/0703-clk-qcom-cmn-pll-add-IPQ5018-support.patch @@ -3,7 +3,12 @@ From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:11 +0800 Subject: [PATCH 1/2] clk: qcom: cmn-pll: add IPQ5018 support -Signed-off-by: hzy +Add support for IPQ5018 (and removing dependency on the IPQ9574 platform). +The common network block in IPQ5018 must be enabled first through a +specific register at a fixed offset in the TCSR area, set in the DTS. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- drivers/clk/qcom/Kconfig | 1 - drivers/clk/qcom/clk-ipq-cmn-pll.c | 29 +++++++++++++++++++++++++++++ diff --git a/target/linux/qualcommax/patches-6.6/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch b/target/linux/qualcommax/patches-6.6/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch index a87ab835a..8127656dd 100644 --- a/target/linux/qualcommax/patches-6.6/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch +++ b/target/linux/qualcommax/patches-6.6/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch @@ -3,7 +3,7 @@ From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:11 +0800 Subject: [PATCH 2/2] arm64: dts: qcom: ipq5018: Add ethernet cmn node -Signed-off-by: hzy +Signed-off-by: Ziyang Huang --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) @@ -23,11 +23,11 @@ Signed-off-by: hzy sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; -@@ -287,6 +293,19 @@ +@@ -186,6 +192,19 @@ status = "disabled"; }; -+ clock-controller@9b000 { ++ cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>, + <0x19475c4 0x4>; diff --git a/target/linux/qualcommax/patches-6.6/0711-net-phy-qcom-Introduce-IPQ5018-internal-PHY-driver.patch b/target/linux/qualcommax/patches-6.6/0711-net-phy-qcom-Introduce-IPQ5018-internal-PHY-driver.patch index 3fd14dcf6..7764df421 100644 --- a/target/linux/qualcommax/patches-6.6/0711-net-phy-qcom-Introduce-IPQ5018-internal-PHY-driver.patch +++ b/target/linux/qualcommax/patches-6.6/0711-net-phy-qcom-Introduce-IPQ5018-internal-PHY-driver.patch @@ -1,9 +1,14 @@ From 77ad12b3a5e21cae859247c0b82cf9a5b661e531 Mon Sep 17 00:00:00 2001 -From: hzy +From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:11 +0800 Subject: [PATCH 1/3] net: phy: qcom: Introduce IPQ5018 internal PHY driver -Signed-off-by: hzy +Introduce the internal GE PHY driver, part of the Qualcomm IPQ50xx SoC. +The driver registers two clock providers needed and referenced by the GCC +using DT properties and phandles. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- drivers/net/phy/qcom/Kconfig | 6 ++ drivers/net/phy/qcom/Makefile | 1 + diff --git a/target/linux/qualcommax/patches-6.6/0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch b/target/linux/qualcommax/patches-6.6/0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch index 7ad4ac7a3..ce5367a08 100644 --- a/target/linux/qualcommax/patches-6.6/0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch +++ b/target/linux/qualcommax/patches-6.6/0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch @@ -3,14 +3,18 @@ From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:12 +0800 Subject: [PATCH 2/3] arm64: dts: qcom: ipq5018: add mdio node -Signed-off-by: hzy +The IPQ5018 SoC contains two MDIO controllers. MDIO0 is used to control +its internal GE Phy, while MDIO1 is wired to external PHYs/switch. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -293,6 +293,26 @@ +@@ -192,6 +192,26 @@ status = "disabled"; }; @@ -34,6 +38,6 @@ Signed-off-by: hzy + status = "disabled"; + }; + - clock-controller@9b000 { + cmn_pll: clock-controller@9b000 { compatible = "qcom,ipq9574-cmn-pll"; reg = <0x0009b000 0x800>, diff --git a/target/linux/qualcommax/patches-6.6/0713-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch b/target/linux/qualcommax/patches-6.6/0713-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch index 3caa659a0..9ac109858 100644 --- a/target/linux/qualcommax/patches-6.6/0713-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch +++ b/target/linux/qualcommax/patches-6.6/0713-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch @@ -1,16 +1,19 @@ From 28490d95fe9e059c5ce74b2289d66e0d7ede2d50 Mon Sep 17 00:00:00 2001 -From: hzy +From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:12 +0800 Subject: [PATCH 3/3] arm64: dts: qcom: ipq5018: add ge_phy node -Signed-off-by: hzy +Add the GE PHY node and register the output clocks in the GCC node. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -301,6 +301,18 @@ +@@ -200,6 +200,18 @@ clocks = <&gcc GCC_MDIO0_AHB_CLK>; clock-names = "gcc_mdio_ahb_clk"; status = "disabled"; @@ -29,14 +32,14 @@ Signed-off-by: hzy }; mdio1: mdio@90000 { -@@ -495,8 +507,8 @@ - <&pcie_x2phy>, - <&pcie_x1phy>, +@@ -394,8 +406,8 @@ + <&pcie0_phy>, + <&pcie1_phy>, <0>, - <0>, - <0>, + <&ge_phy 0>, + <&ge_phy 1>, <0>, - <0>, - <&gephy 0>, + <0>; + #clock-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.6/0714-net-phy-qcom-IPQ5018-enable-configuration-of-DAC-settings.patch b/target/linux/qualcommax/patches-6.6/0714-net-phy-qcom-IPQ5018-enable-configuration-of-DAC-settings.patch new file mode 100644 index 000000000..0c773caf3 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0714-net-phy-qcom-IPQ5018-enable-configuration-of-DAC-settings.patch @@ -0,0 +1,111 @@ +From: George Moussalem +Date: Sun, 19 Jan 2025 11:25:27 +0400 +Subject: [PATCH] net: phy: qcom: ipq5018 enable configuration of DAC settings + +Allow setting amplitude and bias current as needed on the IPQ5018 Internal +GE PHY. When the "qcom,dac" property is set in the DTS, the driver expects +a pair of u32 values: + +(from QCA8337 datasheet) +11: follow DSP setting +10: bypass half amplitude and follow DSP half bias current +01: half amplitude follow DSP and bypass half bias current +00: full amplitude and full bias current + +Signed-off-by: George Moussalem +--- +--- a/drivers/net/phy/qcom/ipq5018.c ++++ b/drivers/net/phy/qcom/ipq5018.c +@@ -13,6 +13,10 @@ + #define IPQ5018_PHY_FIFO_CONTROL 0x19 + #define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0) + ++#define IPQ5018_PHY_DEBUG_EDAC 0x4380 ++#define IPQ5018_PHY_MMD1_MDAC 0x8100 ++#define IPQ5018_PHY_DAC_MASK GENMASK(15,8) ++ + struct ipq5018_phy { + int num_clks; + struct clk_bulk_data *clks; +@@ -20,20 +24,35 @@ struct ipq5018_phy { + + struct clk_hw *clk_rx, *clk_tx; + struct clk_hw_onecell_data *clk_data; ++ ++ u32 mdac; ++ u32 edac; + }; + + static int ipq5018_probe(struct phy_device *phydev) + { +- struct ipq5018_phy *priv; + struct device *dev = &phydev->mdio.dev; ++ struct ipq5018_phy *priv; ++ u32 mdac, edac = 0; + char name[64]; +- int ret; ++ int ret, cnt; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate priv\n"); + ++ cnt = of_property_count_u32_elems(dev->of_node, "qcom,dac"); ++ if (cnt == 2) { ++ ret = of_property_read_u32_index(dev->of_node, "qcom,dac", 0, &mdac); ++ if (!ret) ++ priv->mdac = mdac; ++ ++ ret = of_property_read_u32_index(dev->of_node, "qcom,dac", 1, &edac); ++ if (!ret) ++ priv->edac = edac; ++ } ++ + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 0) + return dev_err_probe(dev, priv->num_clks, +@@ -84,6 +103,8 @@ static int ipq5018_probe(struct phy_devi + return dev_err_probe(dev, ret, + "fail to register clock provider\n"); + ++ phydev->priv = priv; ++ + return 0; + } + +@@ -112,12 +133,34 @@ static int ipq5018_cable_test_start(stru + return 0; + } + ++static int ipq5018_config_init(struct phy_device *phydev) ++{ ++ struct ipq5018_phy *priv = phydev->priv; ++ int ret; ++ ++ /* setting mdac in MMD1 */ ++ if (priv->mdac) { ++ ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC, ++ IPQ5018_PHY_DAC_MASK, priv->mdac); ++ if (ret) ++ return ret; ++ } ++ ++ /* setting edac in debug register */ ++ if (priv->edac) ++ return at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC, ++ IPQ5018_PHY_DAC_MASK, priv->edac); ++ ++ return 0; ++} ++ + static struct phy_driver ipq5018_internal_phy_driver[] = { + { + PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), + .name = "Qualcomm IPQ5018 internal PHY", + .flags = PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST, + .probe = ipq5018_probe, ++ .config_init = ipq5018_config_init, + .soft_reset = ipq5018_soft_reset, + .read_status = at803x_read_status, + .config_intr = at803x_config_intr, diff --git a/target/linux/qualcommax/patches-6.6/0715-net-phy-qcom-add-IPQ5018-initvals-and-CDT-feature.patch b/target/linux/qualcommax/patches-6.6/0715-net-phy-qcom-add-IPQ5018-initvals-and-CDT-feature.patch new file mode 100644 index 000000000..ae4214b0c --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0715-net-phy-qcom-add-IPQ5018-initvals-and-CDT-feature.patch @@ -0,0 +1,108 @@ +From: George Moussalem +Date: Fri, 24 Jan 2025 17:18:12 +0400 +Subject: [PATCH] net: phy: qcom: add IPQ5018 initvals and CDT feature + +The Cable Diagnostics Test for IPQ5018 follows the same logic as qca808x. +However, the IPQ5018 GE PHY has its own threshold values. So let's set the +CDT thresholds for the IPQ5018 internal GE PHY. While add it, add and set +thesholds for MSE for signal quality measurement and 8023az for EEE. + +Signed-off-by: George Moussalem +--- +--- a/drivers/net/phy/qcom/ipq5018.c ++++ b/drivers/net/phy/qcom/ipq5018.c +@@ -17,6 +17,38 @@ + #define IPQ5018_PHY_MMD1_MDAC 0x8100 + #define IPQ5018_PHY_DAC_MASK GENMASK(15,8) + ++#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000 ++#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001 ++#define IPQ5018_PHY_MMD3_AZ_CTRL1 0x8008 ++#define IPQ5018_PHY_MMD3_AZ_CTRL2 0x8009 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3 0x8074 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4 0x8075 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5 0x8076 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6 0x8077 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7 0x8078 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9 0x807a ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13 0x807e ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL14 0x807f ++ ++#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1 ++#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6 ++#define IPQ5018_PHY_MMD3_AZ_CTRL1_VAL 0x7880 ++#define IPQ5018_PHY_MMD3_AZ_CTRL2_VAL 0xc8 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3_VAL 0xc040 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4_VAL 0xa060 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5_VAL 0xc040 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6_VAL 0xa060 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7_VAL 0xc24c ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9_VAL 0xc060 ++#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13_VAL 0xb060 ++#define IPQ5018_PHY_MMD3_NEAR_ECHO_THRESH_VAL 0x90b0 ++ ++#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1 ++#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7,4) ++#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50 ++ ++#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080 ++ + struct ipq5018_phy { + int num_clks; + struct clk_bulk_data *clks; +@@ -129,6 +161,24 @@ static int ipq5018_soft_reset(struct phy + + static int ipq5018_cable_test_start(struct phy_device *phydev) + { ++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3, ++ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3_VAL); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4, ++ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4_VAL); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5, ++ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5_VAL); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6, ++ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6_VAL); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7, ++ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7_VAL); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9, ++ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9_VAL); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, ++ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13, ++ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13_VAL); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3, ++ IPQ5018_PHY_MMD3_NEAR_ECHO_THRESH_VAL); ++ + /* we do all the (time consuming) work later */ + return 0; + } +@@ -136,8 +186,30 @@ static int ipq5018_cable_test_start(stru + static int ipq5018_config_init(struct phy_device *phydev) + { + struct ipq5018_phy *priv = phydev->priv; ++ u16 val = 0; + int ret; + ++ /* set LDO efuse: first temporarily store ANA_DAC_FILTER value from ++ debug register as it will be reset once the ANA_LDO_EFUSE register ++ is written to */ ++ val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER); ++ at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE, ++ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK, ++ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT); ++ at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val); ++ ++ /* set 8023AZ CTRL values */ ++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_AZ_CTRL1, ++ IPQ5018_PHY_MMD3_AZ_CTRL1_VAL); ++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_AZ_CTRL2, ++ IPQ5018_PHY_MMD3_AZ_CTRL2_VAL); ++ ++ /* set MSE threshold values */ ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1, ++ IPQ5018_PHY_MMD1_MSE_THRESH1_VAL); ++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2, ++ IPQ5018_PHY_MMD1_MSE_THRESH2_VAL); ++ + /* setting mdac in MMD1 */ + if (priv->mdac) { + ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC, diff --git a/target/linux/qualcommax/patches-6.6/0721-clk-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch b/target/linux/qualcommax/patches-6.6/0721-clk-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch index 47c59f5a9..0a22289d3 100644 --- a/target/linux/qualcommax/patches-6.6/0721-clk-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch +++ b/target/linux/qualcommax/patches-6.6/0721-clk-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch @@ -4,7 +4,11 @@ Date: Sun, 8 Sep 2024 16:40:12 +0800 Subject: [PATCH 1/2] clk: gcc-ipq5018: remove the unsupported clk combination for gmac -Signed-off-by: hzy +Comment out the unsupported clock combination in the frequency table +for GMAC1. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- drivers/clk/qcom/gcc-ipq5018.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/qualcommax/patches-6.6/0722-clk-gcc-ipq5018-hack-for-qca-ssdk.patch b/target/linux/qualcommax/patches-6.6/0722-clk-gcc-ipq5018-refer-to-ge-phy-rx-and-tx-clk-providers-by-name.patch similarity index 82% rename from target/linux/qualcommax/patches-6.6/0722-clk-gcc-ipq5018-hack-for-qca-ssdk.patch rename to target/linux/qualcommax/patches-6.6/0722-clk-gcc-ipq5018-refer-to-ge-phy-rx-and-tx-clk-providers-by-name.patch index 629b095a8..6cd1a2a16 100644 --- a/target/linux/qualcommax/patches-6.6/0722-clk-gcc-ipq5018-hack-for-qca-ssdk.patch +++ b/target/linux/qualcommax/patches-6.6/0722-clk-gcc-ipq5018-refer-to-ge-phy-rx-and-tx-clk-providers-by-name.patch @@ -1,9 +1,15 @@ From ce9e56a436e486690097cfbdda2d0c11b60db4c2 Mon Sep 17 00:00:00 2001 From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:12 +0800 -Subject: [PATCH 2/2] clk: gcc-ipq5018: hack for qca-ssdk +Subject: [PATCH] clk: gcc-ipq5018: refer to GE PHY rx and tx clk providers by name -Signed-off-by: hzy +QCA-SSDK does not register the output clocks of the onboard GE Phy and +uniphy so the GCC and DTS can't reference them by their index. +The SSDK references them by name, so let's change the GCC driver +accordingly. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- drivers/clk/qcom/gcc-ipq5018.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/linux/qualcommax/patches-6.6/0751-net-dsa-qca8k-always-enable-SGMII-auto-negotiation.patch b/target/linux/qualcommax/patches-6.6/0751-net-dsa-qca8k-always-enable-SGMII-auto-negotiation.patch index 3951ef0ed..bccac8a4e 100644 --- a/target/linux/qualcommax/patches-6.6/0751-net-dsa-qca8k-always-enable-SGMII-auto-negotiation.patch +++ b/target/linux/qualcommax/patches-6.6/0751-net-dsa-qca8k-always-enable-SGMII-auto-negotiation.patch @@ -1,11 +1,11 @@ From d7a41a3ab6b8e3a3158997cda13f1fe28a37268c Mon Sep 17 00:00:00 2001 -From: hzy +From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:12 +0800 Subject: [PATCH] net: dsa: qca8k: always enable SGMII auto-negotiation fixed-link can't work well without this -Signed-off-by: hzy +Signed-off-by: Ziyang Huang --- drivers/net/dsa/qca/qca8k-8xxx.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/linux/qualcommax/patches-6.6/0752-net-dsa-qca8k-support-PHY-to-PHY-CPU-link.patch b/target/linux/qualcommax/patches-6.6/0752-net-dsa-qca8k-support-PHY-to-PHY-CPU-link.patch new file mode 100644 index 000000000..e664a717a --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0752-net-dsa-qca8k-support-PHY-to-PHY-CPU-link.patch @@ -0,0 +1,49 @@ +From 8a56ac86c2eed13024413aa23a6cda85613d60f9 Mon Sep 17 00:00:00 2001 +From: Ziyang Huang +Date: Sat, 18 Jan 2025 16:18:40 +0800 +Subject: [PATCH 1/2] net: dsa: qca8k: support PHY-to-PHY CPU link + +PHY-to-PHY CPU link is a common/demo design in IPQ50xx platform, since it only has a SGMII/SGMII+ link and a MDI link. + +For DSA, CPU tag is the only requirement. Fortunately, qca8337 can enable it on any port. So it's ok to trust a PHY-to-PHY link as a CPU link. + +Signed-off-by: Ziyang Huang +--- + drivers/net/dsa/qca/qca8k-8xxx.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +--- a/drivers/net/dsa/qca/qca8k-8xxx.c ++++ b/drivers/net/dsa/qca/qca8k-8xxx.c +@@ -1013,7 +1013,7 @@ qca8k_setup_mdio_bus(struct qca8k_priv * + return err; + } + +- if (!dsa_is_user_port(priv->ds, reg)) ++ if (reg == 0 || reg == 6) + continue; + + of_get_phy_mode(port, &mode); +@@ -1088,17 +1088,19 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri + + static int qca8k_find_cpu_port(struct dsa_switch *ds) + { +- struct qca8k_priv *priv = ds->priv; ++ int i; + +- /* Find the connected cpu port. Valid port are 0 or 6 */ + if (dsa_is_cpu_port(ds, 0)) + return 0; + +- dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); +- + if (dsa_is_cpu_port(ds, 6)) + return 6; + ++ /* PHY-to-PHY link */ ++ for (i = 1; i <= 5; i++) ++ if (dsa_is_cpu_port(ds, i)) ++ return i; ++ + return -EINVAL; + } + diff --git a/target/linux/qualcommax/patches-6.6/0806-rproc-qcom_q6v5_mpd-split-q6_wcss-to-rootpd-and-user.patch b/target/linux/qualcommax/patches-6.6/0806-rproc-qcom_q6v5_mpd-split-q6_wcss-to-rootpd-and-user.patch index 0470f24ab..b3cd492d0 100644 --- a/target/linux/qualcommax/patches-6.6/0806-rproc-qcom_q6v5_mpd-split-q6_wcss-to-rootpd-and-user.patch +++ b/target/linux/qualcommax/patches-6.6/0806-rproc-qcom_q6v5_mpd-split-q6_wcss-to-rootpd-and-user.patch @@ -4,7 +4,12 @@ Date: Sun, 8 Sep 2024 16:40:12 +0800 Subject: [PATCH 1/2] rproc: qcom_q6v5_mpd: split q6_wcss to rootpd and userpd -Signed-off-by: hzy +Split the q6_wcss structure and create a separate userpd struct to clearly +differentiate between the process to bring up the QDSP6 processor vs +process(es) to bring up the Wifi radio(s) (WCSS) for better readability. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- drivers/remoteproc/qcom_q6v5_mpd.c | 126 +++++++++++++---------------- 1 file changed, 56 insertions(+), 70 deletions(-) diff --git a/target/linux/qualcommax/patches-6.6/0807-remoteproc-qcom_q6v5_mpd-fix-incorrent-use-of-rproc-.patch b/target/linux/qualcommax/patches-6.6/0807-remoteproc-qcom_q6v5_mpd-fix-incorrent-use-of-rproc-.patch index f9d3fa285..59f49ad66 100644 --- a/target/linux/qualcommax/patches-6.6/0807-remoteproc-qcom_q6v5_mpd-fix-incorrent-use-of-rproc-.patch +++ b/target/linux/qualcommax/patches-6.6/0807-remoteproc-qcom_q6v5_mpd-fix-incorrent-use-of-rproc-.patch @@ -43,7 +43,7 @@ Subject: [PATCH 2/2] remoteproc: qcom_q6v5_mpd: fix incorrent use of [ 2.011954] kthread+0xdc/0xe0 [ 2.015600] ret_from_fork+0x10/0x20 -Signed-off-by: hzy +Signed-off-by: Ziyang Huang --- drivers/remoteproc/qcom_q6v5_mpd.c | 53 +++++++++++++++++------------- 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/target/linux/qualcommax/patches-6.6/0811-qcom_scm-support-MPD.patch b/target/linux/qualcommax/patches-6.6/0811-firmware-qcom_scm-support-MPD.patch similarity index 92% rename from target/linux/qualcommax/patches-6.6/0811-qcom_scm-support-MPD.patch rename to target/linux/qualcommax/patches-6.6/0811-firmware-qcom_scm-support-MPD.patch index 0b7b119f7..afcc15e69 100644 --- a/target/linux/qualcommax/patches-6.6/0811-qcom_scm-support-MPD.patch +++ b/target/linux/qualcommax/patches-6.6/0811-firmware-qcom_scm-support-MPD.patch @@ -1,9 +1,13 @@ From 6553d598cdb507f7ede020f25da646ba084a23c6 Mon Sep 17 00:00:00 2001 From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:12 +0800 -Subject: [PATCH 1/5] qcom_scm: support MPD +Subject: [PATCH] firmware: qcom_scm: support MPD -Signed-off-by: hzy +Add SCM calls to power up / down the SoC's internal WiFi radio and to +load PIL segments to support the MPD architecture. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- drivers/firmware/qcom_scm.c | 79 ++++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 3 + diff --git a/target/linux/qualcommax/patches-6.6/0812-mdt_loader-support-MPD.patch b/target/linux/qualcommax/patches-6.6/0812-soc-qcom-mdt_loader-support-MPD.patch similarity index 96% rename from target/linux/qualcommax/patches-6.6/0812-mdt_loader-support-MPD.patch rename to target/linux/qualcommax/patches-6.6/0812-soc-qcom-mdt_loader-support-MPD.patch index 6ece3d17b..935a94385 100644 --- a/target/linux/qualcommax/patches-6.6/0812-mdt_loader-support-MPD.patch +++ b/target/linux/qualcommax/patches-6.6/0812-soc-qcom-mdt_loader-support-MPD.patch @@ -1,9 +1,13 @@ From bf42d84868bc82a9cb334a33930f2d1da24f7070 Mon Sep 17 00:00:00 2001 From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:12 +0800 -Subject: [PATCH 2/5] mdt_loader: support MPD +Subject: [PATCH] soc: qcom: mdt_loader: support MPD -Signed-off-by: hzy +Add support for loading user PD specific PIL segments as required by the +MPD architecture. + +Signed-off-by: Ziyang Huang +Signed-off-by: George Moussalem --- drivers/soc/qcom/mdt_loader.c | 110 ++++++++++++++++++++++++++-- include/linux/soc/qcom/mdt_loader.h | 5 ++ diff --git a/target/linux/qualcommax/patches-6.6/0813-remoteproc-qcom_q6v5_mpd-enable-clocks.patch b/target/linux/qualcommax/patches-6.6/0813-remoteproc-qcom_q6v5_mpd-enable-clocks.patch index 204051f56..f549580f3 100644 --- a/target/linux/qualcommax/patches-6.6/0813-remoteproc-qcom_q6v5_mpd-enable-clocks.patch +++ b/target/linux/qualcommax/patches-6.6/0813-remoteproc-qcom_q6v5_mpd-enable-clocks.patch @@ -3,7 +3,7 @@ From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:12 +0800 Subject: [PATCH 3/5] remoteproc: qcom_q6v5_mpd: enable clocks -Signed-off-by: hzy +Signed-off-by: Ziyang Huang --- drivers/remoteproc/qcom_q6v5_mpd.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/linux/qualcommax/patches-6.6/0814-remoteproc-qcom_q6v5_mpd-support-ipq5018.patch b/target/linux/qualcommax/patches-6.6/0814-remoteproc-qcom_q6v5_mpd-support-ipq5018.patch index e22b4b8d5..9316458cb 100644 --- a/target/linux/qualcommax/patches-6.6/0814-remoteproc-qcom_q6v5_mpd-support-ipq5018.patch +++ b/target/linux/qualcommax/patches-6.6/0814-remoteproc-qcom_q6v5_mpd-support-ipq5018.patch @@ -1,9 +1,9 @@ From 4ae334127f073aa5f7c9209c9f0a17fd9e331db1 Mon Sep 17 00:00:00 2001 From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:12 +0800 -Subject: [PATCH 4/5] remoteproc: qcom_q6v5_mpd: support ipq5018 +Subject: [PATCH] remoteproc: qcom_q6v5_mpd: support ipq5018 -Signed-off-by: hzy +Signed-off-by: Ziyang Huang --- drivers/remoteproc/qcom_q6v5_mpd.c | 37 +++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/target/linux/qualcommax/patches-6.6/0815-remoteproc-qcom_q6v5_mpd-add-support-for-passing-v1-bootargs.patch b/target/linux/qualcommax/patches-6.6/0815-remoteproc-qcom_q6v5_mpd-add-support-for-passing-v1-bootargs.patch new file mode 100644 index 000000000..fdc2879f0 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0815-remoteproc-qcom_q6v5_mpd-add-support-for-passing-v1-bootargs.patch @@ -0,0 +1,163 @@ +From: George Moussalem +Date: Mon, 09 Dec 2024 09:59:38 +0400 +Subject: [PATCH] remoteproc: qcom_q6v5_mpd: add support for passing v1 bootargs + +On multi-PD platforms such as IPQ5018, boot args are passed to the root PD +run on the Q6 processor which in turn boots the user PDs for internal +(IPQ5018) and external wifi radios (such as QCN6122). These boot args +let the user PD process know details like what PCIE index, user PD ID, and +reset GPIO is used. These are otherwise hardcoded in the firmware. + +Below is the structure expected of the version 1 boot args including the +default values hardcoded in the firmware for IPQ5018: + ++------------+------+--------------+--------------+ +| Argument | type | def val UPD2 | def val UPD3 | ++------------+------+--------------+--------------+ +| PCIE Index | u32 | 0x02 (PCIE1) | 0x01 (PCIE0) | +| Length | u32 | 0x04 | 0x04 | +| User PD ID | u32 | 0x02 | 0x03 | +| Reset GPIO | u32 | 0x12 | 0x0f | +| Reserved 1 | u32 | 0x00 | 0x00 | +| Reserved 2 | u32 | 0x00 | 0x00 | ++------------+------+--------------+--------------+ + +On IPQ5018/QCN6122 boards, the default mapping is as follows: + + +-> UPD1 ----> IPQ5018 Internal 2.4G Radio + / + / +Root PD +---> UPD2 ----> QCN6122 6G Radio on PCIE1 (if available) + \ + \ + +-> UPD3 ----> QCN6102 5G Radio on PCIE0 + +To support (future) boards with other mappings or control what UPD ID is +used, let's add support for passing boot args for more flexibility. + +Signed-off-by: George Moussalem +--- +--- a/drivers/remoteproc/qcom_q6v5_mpd.c ++++ b/drivers/remoteproc/qcom_q6v5_mpd.c +@@ -42,7 +42,11 @@ + #define UPD_BOOT_INFO_SMEM_SIZE 4096 + #define UPD_BOOT_INFO_HEADER_TYPE 0x2 + #define UPD_BOOT_INFO_SMEM_ID 507 +-#define VERSION2 2 ++ ++enum q6_bootargs_version { ++ VERSION1 = 1, ++ VERSION2, ++}; + + /** + * struct userpd_boot_info_header - header of user pd bootinfo +@@ -94,6 +98,7 @@ struct userpd { + struct wcss_data { + u32 pasid; + bool share_upd_info_to_q6; ++ u8 bootargs_version; + }; + + /** +@@ -298,10 +303,13 @@ static void *q6_wcss_da_to_va(struct rpr + static int share_upd_bootinfo_to_q6(struct rproc *rproc) + { + int i, ret; ++ u32 rd_val; + size_t size; + u16 cnt = 0, version; + void *ptr; ++ u8 *bootargs_arr; + struct q6_wcss *wcss = rproc->priv; ++ struct device_node *np = wcss->dev->of_node; + struct userpd *upd; + struct userpd_boot_info upd_bootinfo = {0}; + const struct firmware *fw; +@@ -323,10 +331,47 @@ static int share_upd_bootinfo_to_q6(stru + } + + /*Version*/ +- version = VERSION2; ++ version = (wcss->desc->bootargs_version) ? wcss->desc->bootargs_version : VERSION2; + memcpy_toio(ptr, &version, sizeof(version)); + ptr += sizeof(version); + ++ cnt = ret = of_property_count_u32_elems(np, "boot-args"); ++ if (ret < 0) { ++ if (ret == -ENODATA) { ++ dev_err(wcss->dev, "failed to read boot args ret:%d\n", ret); ++ return ret; ++ } ++ cnt = 0; ++ } ++ ++ /* No of elements */ ++ memcpy_toio(ptr, &cnt, sizeof(u16)); ++ ptr += sizeof(u16); ++ ++ bootargs_arr = kzalloc(cnt, GFP_KERNEL); ++ if (!bootargs_arr) { ++ dev_err(wcss->dev, "failed to allocate memory\n"); ++ return PTR_ERR(bootargs_arr); ++ } ++ ++ for (i = 0; i < cnt; i++) { ++ ret = of_property_read_u32_index(np, "boot-args", i, &rd_val); ++ if (ret) { ++ dev_err(wcss->dev, "failed to read boot args\n"); ++ kfree(bootargs_arr); ++ return ret; ++ } ++ bootargs_arr[i] = (u8)rd_val; ++ } ++ ++ /* Copy bootargs */ ++ memcpy_toio(ptr, bootargs_arr, cnt); ++ ptr += (cnt); ++ ++ of_node_put(np); ++ kfree(bootargs_arr); ++ cnt = 0; ++ + for (i = 0; i < ARRAY_SIZE(wcss->upd); i++) + if (wcss->upd[i]) + cnt++; +@@ -382,12 +427,14 @@ static int q6_wcss_load(struct rproc *rp + + /* Share user pd boot info to Q6 remote processor */ + if (desc->share_upd_info_to_q6) { +- ret = share_upd_bootinfo_to_q6(rproc); +- if (ret) { +- dev_err(wcss->dev, +- "user pd boot info sharing with q6 failed %d\n", +- ret); +- return ret; ++ if (of_property_present(wcss->dev->of_node, "boot-args")) { ++ ret = share_upd_bootinfo_to_q6(rproc); ++ if (ret) { ++ dev_err(wcss->dev, ++ "user pd boot info sharing with q6 failed %d\n", ++ ret); ++ return ret; ++ } + } + } + +@@ -803,13 +850,15 @@ static int q6_wcss_remove(struct platfor + + static const struct wcss_data q6_ipq5018_res_init = { + .pasid = MPD_WCNSS_PAS_ID, +- // .share_upd_info_to_q6 = true, /* Version 1 */ ++ .share_upd_info_to_q6 = true, ++ .bootargs_version = VERSION1, + // .mdt_load_sec = qcom_mdt_load_pd_seg, + }; + + static const struct wcss_data q6_ipq5332_res_init = { + .pasid = MPD_WCNSS_PAS_ID, + .share_upd_info_to_q6 = true, ++ .bootargs_version = VERSION2, + }; + + static const struct wcss_data q6_ipq9574_res_init = { diff --git a/target/linux/qualcommax/patches-6.6/0815-arm64-dts-qcom-ipq5018-add-wifi-support.patch b/target/linux/qualcommax/patches-6.6/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch similarity index 73% rename from target/linux/qualcommax/patches-6.6/0815-arm64-dts-qcom-ipq5018-add-wifi-support.patch rename to target/linux/qualcommax/patches-6.6/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch index 030922971..786345f64 100644 --- a/target/linux/qualcommax/patches-6.6/0815-arm64-dts-qcom-ipq5018-add-wifi-support.patch +++ b/target/linux/qualcommax/patches-6.6/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch @@ -1,16 +1,19 @@ -From 4e2bfcd24848db58cc2a603acc2418d0190c5466 Mon Sep 17 00:00:00 2001 -From: Ziyang Huang -Date: Sun, 8 Sep 2024 16:40:12 +0800 -Subject: [PATCH 5/5] arm64: dts: qcom: ipq5018: add wifi support +From: George Moussalem +Date: Wed, 27 Oct 2024 16:34:11 +0400 +Subject: [PATCH] arm64: dts: qcom: ipq5018: add wifi support -Signed-off-by: hzy +The IPQ5018 SoC comes with an internal 2x2 2.4Ghz wifi radio. +QCN6122 is a PCIe based wifi solution specific to the IPQ5018 platform which +comes optinally packed with 1 or 2 QCN6122 chips or with an external +PCIe based wifi solution (such as QCN9074) for 5/6 Ghz support. + +As such, add wifi nodes for both IPQ5018 and QCN6122. + +Signed-off-by: George Moussalem --- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 192 ++++++++++++++++++++++++++ - 1 file changed, 192 insertions(+) - --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -1005,6 +1005,197 @@ +@@ -692,6 +692,225 @@ }; }; @@ -127,17 +130,43 @@ Signed-off-by: hzy + status = "disabled"; + }; + ++ //QCN6102 5G + wifi1: wifi1@c000000 { ++ reg = <0x0b00a040 0x0>; + compatible = "qcom,qcn6122-wifi"; -+ msi-parent = <&v2m0>; -+ interrupts = ; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; + status = "disabled"; + }; + ++ //QCN6122 5G/6G + wifi2: wifi2@c000000 { ++ reg = <0x0b00a040 0x0>; + compatible = "qcom,qcn6122-wifi"; -+ msi-parent = <&v2m0>; -+ interrupts = ; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; + status = "disabled"; + }; + @@ -153,10 +182,10 @@ Signed-off-by: hzy + <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>; + + interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, -+ <&wcss_smp2p_in 0 0>, -+ <&wcss_smp2p_in 1 0>, -+ <&wcss_smp2p_in 2 0>, -+ <&wcss_smp2p_in 3 0>; ++ <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, ++ <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, ++ <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, ++ <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", @@ -168,6 +197,8 @@ Signed-off-by: hzy + qcom,smem-state-names = "shutdown", + "stop"; + ++ status = "disabled"; ++ + glink-edge { + interrupts = ; + label = "rtr"; @@ -180,7 +211,7 @@ Signed-off-by: hzy + }; + }; + -+ wcss: wcss-smp2p { ++ wcss: smp2p-wcss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + @@ -205,6 +236,6 @@ Signed-off-by: hzy + }; + }; + - pcie_x1: pcie@80000000 { + pcie1: pcie@80000000 { compatible = "qcom,pcie-ipq5018"; reg = <0x80000000 0xf1d>, diff --git a/target/linux/qualcommax/patches-6.6/0817-arm64-dts-qcom-ipq5018-add-tz_apps-reserved-memory-region.patch b/target/linux/qualcommax/patches-6.6/0817-arm64-dts-qcom-ipq5018-add-tz_apps-reserved-memory-region.patch new file mode 100644 index 000000000..03a9c1c98 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0817-arm64-dts-qcom-ipq5018-add-tz_apps-reserved-memory-region.patch @@ -0,0 +1,22 @@ +From: George Moussalem +Date: Wed, 05 Feb 2025 12:12:47 +0400 +Subject: [PATCH] arm64: dts: qcom: ipq5018: add tz_apps reserved memory region + +Add tz_apps memory region needed for wifi to work. + +Signed-off-by: George Moussalem +--- +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -113,6 +113,11 @@ + #size-cells = <2>; + ranges; + ++ tz_apps@4a400000 { ++ reg = <0x0 0x4a400000 0x0 0x400000>; ++ no-map; ++ }; ++ + bootloader@4a800000 { + reg = <0x0 0x4a800000 0x0 0x200000>; + no-map; diff --git a/target/linux/qualcommax/patches-6.6/0820-dt-bindings-net-wireless-ath11k-add-bindings-for-QCN6122.patch b/target/linux/qualcommax/patches-6.6/0820-dt-bindings-net-wireless-ath11k-add-bindings-for-QCN6122.patch new file mode 100644 index 000000000..d9eaf582c --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0820-dt-bindings-net-wireless-ath11k-add-bindings-for-QCN6122.patch @@ -0,0 +1,62 @@ +From: George Moussalem +Date: Wed, 27 Oct 2024 16:34:11 +0400 +Subject: [PATCH] dt: bindings: net: add bindings for QCN6122 + +QCN6122 is a PCIe based solution that is attached to and enumerated +by the WPSS (Wireless Processor SubSystem) Q6 processor. + +Though it is a PCIe device, since it is not attached to APSS processor +(Application Processor SubSystem), APSS will be unaware of such a decice +and hence it is registered to the APSS processor as a platform device(AHB). +Because of this hybrid nature, it is called as a hybrid bus device. + +As such, QCN6122 is a hybrid bus type device and follows the same codepath +as for WCN6750. + +This is a reversed engineered and heavily simplified version of below +downstream patch: +https://git.codelinaro.org/clo/qsdk/oss/system/feeds/wlan-open/-/ \ +blob/NHSS.QSDK.12.4.5.r2/mac80211/patches/232-ath11k-qcn6122-support.patch + +Signed-off-by: George Moussalem +--- +--- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml ++++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml +@@ -21,6 +21,7 @@ properties: + - qcom,ipq6018-wifi + - qcom,wcn6750-wifi + - qcom,ipq5018-wifi ++ - qcom,qcn6122-wifi + + reg: + maxItems: 1 +@@ -258,6 +259,29 @@ allOf: + - description: interrupt event for ring DP20 + - description: interrupt event for ring DP21 + - description: interrupt event for ring DP22 ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - qcom,qcn6122-wifi ++ then: ++ properties: ++ interrupts: ++ items: ++ - description: interrupt event for ring CE1 ++ - description: interrupt event for ring CE2 ++ - description: interrupt event for ring CE3 ++ - description: interrupt event for ring CE4 ++ - description: interrupt event for ring CE5 ++ - description: interrupt event for ring DP1 ++ - description: interrupt event for ring DP2 ++ - description: interrupt event for ring DP3 ++ - description: interrupt event for ring DP4 ++ - description: interrupt event for ring DP5 ++ - description: interrupt event for ring DP6 ++ - description: interrupt event for ring DP7 ++ - description: interrupt event for ring DP8 + + examples: + - | diff --git a/target/linux/qualcommax/patches-6.6/0900-power-Add-Qualcomm-APM.patch b/target/linux/qualcommax/patches-6.6/0900-power-Add-Qualcomm-APM.patch index 2e5c72b7d..f10535158 100644 --- a/target/linux/qualcommax/patches-6.6/0900-power-Add-Qualcomm-APM.patch +++ b/target/linux/qualcommax/patches-6.6/0900-power-Add-Qualcomm-APM.patch @@ -49,7 +49,7 @@ Signed-off-by: Robert Marko +obj-$(CONFIG_QCOM_APM) += apm.o --- /dev/null +++ b/drivers/power/qcom/apm.c -@@ -0,0 +1,944 @@ +@@ -0,0 +1,943 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * @@ -971,7 +971,6 @@ Signed-off-by: Robert Marko + .driver = { + .name = MSM_APM_DRIVER_NAME, + .of_match_table = msm_apm_match_table, -+ .owner = THIS_MODULE, + }, + .probe = msm_apm_probe, + .remove = msm_apm_remove, diff --git a/target/linux/qualcommax/patches-6.6/0901-regulator-add-Qualcomm-CPR-regulators.patch b/target/linux/qualcommax/patches-6.6/0901-regulator-add-Qualcomm-CPR-regulators.patch index c85be0357..46d4fc246 100644 --- a/target/linux/qualcommax/patches-6.6/0901-regulator-add-Qualcomm-CPR-regulators.patch +++ b/target/linux/qualcommax/patches-6.6/0901-regulator-add-Qualcomm-CPR-regulators.patch @@ -77,7 +77,7 @@ Signed-off-by: Robert Marko obj-$(CONFIG_REGULATOR_PF8X00) += pf8x00-regulator.o --- /dev/null +++ b/drivers/regulator/cpr3-npu-regulator.c -@@ -0,0 +1,695 @@ +@@ -0,0 +1,694 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * @@ -752,7 +752,6 @@ Signed-off-by: Robert Marko + .driver = { + .name = "qcom,cpr3-npu-regulator", + .of_match_table = cpr3_regulator_match_table, -+ .owner = THIS_MODULE, + }, + .probe = cpr3_npu_regulator_probe, + .remove = cpr3_npu_regulator_remove, @@ -9866,7 +9865,7 @@ Signed-off-by: Robert Marko +} --- /dev/null +++ b/drivers/regulator/cpr4-apss-regulator.c -@@ -0,0 +1,1819 @@ +@@ -0,0 +1,1818 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * @@ -11663,7 +11662,6 @@ Signed-off-by: Robert Marko + .driver = { + .name = "qcom,cpr4-apss-regulator", + .of_match_table = cpr4_regulator_match_table, -+ .owner = THIS_MODULE, + }, + .probe = cpr4_apss_regulator_probe, + .remove = cpr4_apss_regulator_remove, diff --git a/target/linux/qualcommax/patches-6.6/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch b/target/linux/qualcommax/patches-6.6/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch index dca43677d..d41244d65 100644 --- a/target/linux/qualcommax/patches-6.6/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch +++ b/target/linux/qualcommax/patches-6.6/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch @@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -805,6 +805,102 @@ +@@ -814,6 +814,102 @@ }; }; diff --git a/target/linux/qualcommax/patches-6.6/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch b/target/linux/qualcommax/patches-6.6/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch index b03870837..5154aad53 100644 --- a/target/linux/qualcommax/patches-6.6/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch +++ b/target/linux/qualcommax/patches-6.6/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch @@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -1153,6 +1153,7 @@ +@@ -1162,6 +1162,7 @@ wcss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; diff --git a/target/linux/qualcommax/patches-6.6/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch b/target/linux/qualcommax/patches-6.6/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch index 5da9761c0..993d60870 100644 --- a/target/linux/qualcommax/patches-6.6/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch +++ b/target/linux/qualcommax/patches-6.6/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch @@ -13,7 +13,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -926,8 +926,8 @@ +@@ -935,8 +935,8 @@ "wcss_reset", "wcss_q6_reset"; diff --git a/target/linux/qualcommax/patches-6.6/0911-arm64-cmdline-replacement.patch b/target/linux/qualcommax/patches-6.6/0911-arm64-cmdline-replacement.patch new file mode 100644 index 000000000..afc71bf99 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0911-arm64-cmdline-replacement.patch @@ -0,0 +1,105 @@ +Subject: qualcommax: add kernel cmdline replacement hack + +Add kernel command line replacement hack to qualcommax. Now we can +find and replace arguments in the kernel command line by setting +bootargs-find-1, bootargs-replace-1, bootargs-exact-match-1 +and bootargs-find-2, bootargs-replace-2, bootargs-exact-match-2 +under the chosen node in the device tree. + +This hack replaces the first occurence of bootargs-find-X with +bootargs-replace-X. If bootargs-exact-match-X is set to "y", +then the replacement happens only if the kernel command line is +identical to bootargs-find-X. + +Signed-off-by: Qiyuan Zhang +--- + drivers/of/fdt.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 71 insertions(+) + +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -1158,6 +1158,14 @@ int __init early_init_dt_scan_chosen(cha + const void *rng_seed; + const void *fdt = initial_boot_params; + ++ int i, cmd_len, f_len, r_len, offset, step; ++ char *s_ptr, *l_end, *r_end, *cur_ptr, *end_ptr; ++ const char *exact_match; ++ const int bootargs_replace_num = 2; ++ const char *bootargs_replace_props[2][3] = ++ { {"bootargs-find-1", "bootargs-replace-1", "bootargs-exact-match-1"}, ++ {"bootargs-find-2", "bootargs-replace-2", "bootargs-exact-match-2"} }; ++ + node = fdt_path_offset(fdt, "/chosen"); + if (node < 0) + node = fdt_path_offset(fdt, "/chosen@0"); +@@ -1186,6 +1194,69 @@ int __init early_init_dt_scan_chosen(cha + p = of_get_flat_dt_prop(node, "bootargs", &l); + if (p != NULL && l > 0) + strscpy(cmdline, p, min(l, COMMAND_LINE_SIZE)); ++ ++ for(i = 0; i < bootargs_replace_num; i++) { ++ p = of_get_flat_dt_prop(node, bootargs_replace_props[i][0], &f_len); ++ ++ if (p == NULL || f_len == 0 ) ++ continue; ++ ++ exact_match = of_get_flat_dt_prop(node, bootargs_replace_props[i][2], &l); ++ ++ if (exact_match != NULL && l > 0 && exact_match[0] == 'y') { ++ if(strncmp(cmdline, p, r_len) == 0) ++ s_ptr = cmdline; ++ else ++ s_ptr = NULL; ++ } else { ++ s_ptr = strstr(cmdline, p); ++ } ++ ++ if(!s_ptr) ++ continue; ++ ++ p = of_get_flat_dt_prop(node, bootargs_replace_props[i][1], &r_len); ++ ++ if (p == NULL || r_len == 0) ++ continue; ++ ++ pr_info("Input kernel commad line: %s\n", cmdline); ++ ++ cmd_len = strlen(cmdline); ++ ++ if (cmd_len - f_len + r_len < COMMAND_LINE_SIZE) { ++ ++ pr_info("Replace kernel command line with %s\n", bootargs_replace_props[i][1]); ++ ++ offset = r_len - f_len; ++ ++ if (offset != 0) { ++ l_end = s_ptr + f_len - 1; ++ r_end = cmdline + cmd_len; ++ ++ if (offset > 0) { ++ step = -1; ++ cur_ptr = r_end; ++ end_ptr = l_end + step; ++ } else { ++ step = 1; ++ cur_ptr = l_end; ++ end_ptr = r_end + step; ++ } ++ ++ for (; cur_ptr != end_ptr; cur_ptr += step) ++ *(cur_ptr + offset) = *cur_ptr; ++ } ++ ++ strncpy(s_ptr, p, r_len - 1); ++ ++ pr_info("Kernel command line after replacement: %s\n", cmdline); ++ } else { ++ pr_err("Replace kernel command line with %s failed\n", bootargs_replace_props[i][1]); ++ } ++ ++ } ++ + p = of_get_flat_dt_prop(node, "bootargs-append", &l); + if (p != NULL && l > 0) + strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));